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AD9020SE/883B [ADI]

IC 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, CQCC68, CERAMIC, LCC-68, Analog to Digital Converter;
AD9020SE/883B
型号： AD9020SE/883B
厂家： ADI    ADI
描述：

IC 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, CQCC68, CERAMIC, LCC-68, Analog to Digital Converter

转换器 模数转换器
文件： 总12页 (文件大小：206K)
中文：  中文翻译
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10-Bit 60 MSPS  
A/D Converter  
a
AD9020  
FUNCTIO NAL BLO CK D IAGRAM  
FEATURES  
Monolithic 10-Bit/ 60 MSPS Converter  
TTL Outputs  
MSB LSBS  
INVERT INVERT  
61 59  
Bipolar (؎1.75 V) Analog Input  
56 dB SNR @ 2.3 MHz Input  
Low (45 pF) Input Capacitance  
MIL-STD-883 Com pliant Versions Available  
8
9
ANALOG IN  
OVERFLOW  
+V  
12  
11  
REF  
+V  
SENSE  
R/2  
512  
385  
APPLICATIONS  
Digital Oscilloscopes  
Medical Im aging  
R
C
O
M
P
A
R
A
T
Professional Video  
Radar Warning/ Guidance System s  
Infrared System s  
R/2  
R/2  
R
7
3/4  
REF  
384  
D
E
C
O
D
E
OVERFLOW  
51  
(MSB)  
D
D
D
D
D
D
D
50  
49  
48  
47  
46  
23  
9
8
7
6
5
4
3
R
257  
256  
L
A
T
OVERFLOW  
OVERFLOW  
R/2  
1/2  
1
REF  
O
R
R/2  
R
GENERAL D ESCRIP TIO N  
L
O
G
I
C
H
1024  
10  
22  
21  
20  
T he AD9020 A/D converter is a 10-bit monolithic converter  
capable of word rates of 60 MSPS and above. Innovative archi-  
tecture using 512 input comparators instead of the traditional  
1024 required by other flash converters reduces input capaci-  
tance and improves linearity.  
L
D
D
2
1
R
A
T
129  
128  
19  
D
(LSB)  
0
C
R/2  
R/2  
R
1/4  
C
H
E
S
63  
REF  
Encode and outputs are T T L-compatible, making the AD9020  
an ideal candidate for use in low power systems. An overflow  
bit is provided to indicate analog input signals greater than  
R
R
2
1
+VSENSE  
.
Voltage sense lines are provided to insure accurate driving of the  
±VREF voltages applied to the units. Quarter-point taps on the  
resistor ladder help optimize the integral linearity of the unit.  
R/2  
–V  
57  
56  
SENSE  
–V  
REF  
14  
ENCODE  
Either 68-pin ceramic leaded (gull wing) packages or ceramic  
LCCs are available and are specifically designed for low thermal  
impedances. T wo performance grades for temperatures of both  
0°C to +70°C and –55°C to +125°C ranges are offered to allow  
the user to select the linearity best suited for each application.  
Dynamic performance is fully characterized and production  
tested at +25°C. MIL-ST D-883 units are available.  
GROUND  
–V  
+V  
S
S
T he AD9020 A/D Converter is available in versions compliant  
with MIL-ST D-883. Refer to the Analog Devices Military Prod-  
ucts Databook or current AD9020/883B data sheet for detailed  
specifications.  
REV. A  
Inform ation furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assum ed by Analog Devices for its  
use, nor for any infringem ents of patents or other rights of third parties  
which m ay result from its use. No license is granted by im plication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A  
.Tel: 617/ 329-4700  
Fax: 617/ 326-8703  
World Wide Web Site: http:/ / w w w .analog.com  
© Analog Devices, Inc., 1997  
AD9020–SPECIFICATIONS  
ABSO LUTE MAXIMUM RATINGS 1  
3/4REF, 1/2REF, 1/4REF Current . . . . . . . . . . . . . . . . . . . ±10 mA  
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
Operating T emperature  
AD9020JE/KE/JZ/KZ . . . . . . . . . . . . . . . . . . 0°C to +70°C  
Storage T emperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C  
Maximum Junction T emperature2 . . . . . . . . . . . . . . . . +175°C  
Lead Soldering T emp (10 sec) . . . . . . . . . . . . . . . . . . . +300°C  
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V  
–VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V  
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +2 V  
+VREF, –VREF, 3/4REF, 1/2REF, 1/4REF . . . . . . . . . . –2 V to +2 V  
+VREF to –VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V  
DIGIT AL INPUT S . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +VS  
ELECTRICAL CHARACTERISTICS (؎V = ؎5 V; ؎V  
SENSE = ؎1.75 V; ENCODE = 40 MSPS unless otherwise noted)  
S
Test  
AD 9020JE/JZ  
AD 9020KE/KZ  
P aram eter (Conditions)  
Tem p  
Level  
Min  
Typ  
Max  
Min  
Typ  
Max  
Units  
RESOLUT ION  
10  
10  
Bits  
DC ACCURACY3  
Differential Nonlinearity  
+25°C  
Full  
+25°C  
Full  
I
VI  
I
VI  
VI  
1.0  
1.25  
1.5  
2.0  
0.75  
1.0  
1.0  
1.25  
1.5  
LSB  
LSB  
LSB  
LSB  
Integral Nonlinearity  
No Missing Codes  
1.25  
2.5  
2.0  
Full  
Guaranteed  
ANALOG INPUT  
Input Bias Current4  
+25°C  
Full  
+25°C  
+25°C  
+25°C  
I
VI  
I
V
V
0.4  
1.0  
2.0  
0.4  
1.0  
2.0  
mA  
mA  
kΩ  
pF  
MHz  
Input Resistance  
Input Capacitance4  
Analog Bandwidth  
2.0  
7.0  
45  
175  
2.0  
7.0  
45  
175  
REFERENCE INPUT  
Reference Ladder Resistance  
+25°C  
Full  
Full  
I
VI  
V
22  
14  
37  
0.1  
45  
45  
50  
56  
66  
22  
14  
37  
0.1  
45  
45  
50  
56  
66  
Ω
Ω
Ω/°C  
Ladder T empco  
Reference Ladder Offset  
T op of Ladder  
+25°C  
Full  
+25°C  
Full  
I
VI  
I
VI  
V
90  
90  
90  
90  
90  
90  
90  
90  
mV  
mV  
mV  
mV  
Bottom of Ladder  
Offset Drift Coefficient  
Full  
µV/°C  
SWIT CHING PERFORMANCE  
Conversion Rate  
Aperture Delay (tA)  
+25°C  
+25°C  
+25°C  
+25°C  
+25°C  
I
60  
6
60  
6
MSPS  
ns  
ps, rms  
ns  
V
V
I
1
5
10  
3
1
5
10  
3
Aperture Uncertainty (Jitter)  
5
Output Delay (tOD  
)
13  
5
13  
5
Output T ime Skew5  
I
ns  
DYNAMIC PERFORMANCE  
T ransient Response  
Overvoltage Recovery T ime  
Effective Number of Bits (ENOB)  
fIN = 2.3 MHz  
+25°C  
+25°C  
V
V
10  
10  
10  
10  
ns  
ns  
+25°C  
+25°C  
+25°C  
I
IV  
IV  
8.6  
8.0  
7.5  
9.0  
8.4  
8.0  
8.6  
8.0  
7.5  
9.0  
8.4  
8.0  
Bits  
Bits  
Bits  
fIN = 10.3 MHz  
fIN = 15.3 MHz  
Signal-to-Noise Ratio6  
fIN = 2.3 MHz  
+25°C  
+25°C  
+25°C  
I
I
I
54  
50  
47  
56  
53  
50  
54  
50  
47  
56  
53  
50  
dB  
dB  
dB  
fIN = 10.3 MHz  
fIN = 15.3 MHz  
Signal-to-Noise Ratio6  
(Without Harmonics)  
fIN = 2.3 MHz  
+25°C  
+25°C  
+25°C  
I
I
I
54  
51  
48  
56  
54  
52  
54  
51  
48  
56  
54  
52  
dB  
dB  
dB  
fIN = 10.3 MHz  
fIN = 15.3 MHz  
–2–  
REV. A  
AD9020  
Test  
AD 9020JE/JZ  
AD 9020KE/KZ  
P aram eter (Conditions)  
Tem p  
Level  
Min  
Typ  
Max  
Min  
Typ  
Max  
Units  
DYNAMIC PERFORMANCE (continued)  
Harmonic Distortion  
fIN = 2.3 MHz  
fIN = 10.3 MHz  
fIN = 15.3 MHz  
+25°C  
+25°C  
+25°C  
I
I
I
61  
55  
49  
67  
59  
53  
61  
55  
49  
67  
59  
53  
dBc  
dBc  
dBc  
T wo-T one Intermodulation  
Distortion Rejection7  
Differential Phase  
Differential Gain  
+25°C  
+25°C  
+25°C  
V
V
V
70  
0.5  
1
70  
0.5  
1
dBc  
Degree  
%
ENCODE INPUT  
Logic “1” Voltage  
Logic “0” Voltage  
Logic “1” Current  
Logic “0” Current  
Input Capacitance  
Pulse Width (High)  
Pulse Width (Low)  
Full  
Full  
Full  
Full  
+25°C  
+25°C  
+25°C  
VI  
VI  
VI  
VI  
V
2.0  
2.0  
V
V
0.8  
20  
800  
0.8  
20  
800  
µA  
µA  
pF  
ns  
ns  
5
5
I
I
6
6
6
6
DIGIT AL OUT PUT S  
Logic “1” Voltage (IOH = 2 mA)  
Logic “0” Voltage (IOL = 6 mA)  
Full  
Full  
VI  
VI  
2.4  
2.4  
V
V
0.4  
POWER SUPPLY  
+VS Supply Current  
+25°C  
Full  
+25°C  
Full  
+25°C  
Full  
I
VI  
I
VI  
I
VI  
440  
140  
2.8  
530  
542  
170  
177  
3.3  
440  
140  
2.8  
530  
542  
170  
177  
3.3  
mA  
mA  
mA  
mA  
W
–VS Supply Current  
Power Dissipation  
3.4  
3.4  
W
Power Supply Rejection  
Ratio (PSRR)8  
Full  
VI  
6
10  
6
10  
mV/V  
NOT ES  
1Absolute maximum ratings are limiting values to be applied individually, and beyond which the service ability of the circuit may be impaired. Functional operability is  
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.  
2T ypical thermal impedances (part soldered onto board): 68-pin leaded ceramic chip carrier: θJC = 1°C/W; θJA = 17°C/W (no air flow); θJA = 15°C/W  
(air flow = 500 LFM). 68-pin ceramic LCC: θJC = 2.6°C/W; θJA = 15°C/W (no air flow); θJA = 13°C/W (air flow = 500 LFM).  
33/4REF, 1/2REF, and 1/4REF reference ladder taps are driven from dc sources at +0.875 V, 0 V, and –0.875 V, respectively. Accuracy of the overflow comparator is not  
tested and not included in linearity specifications.  
4Measured with ANALOG IN = +VSENSE  
.
5Output delay measured as worst-case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of D 0–D9. Output skew  
measured as worst-case difference in output delay among D 0–D9.  
6RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency.  
7Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale.  
8Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change in +V S or –VS.  
Specifications subject to change without notice.  
REV. A  
–3–  
AD9020  
O RD ERING GUID E  
Tem perature  
EXP LANATIO N O F TEST LEVELS  
T est Level  
P ackage  
O ption*  
I
– 100% production tested.  
D evice  
Range  
D escription  
II – 100% production tested at +25°C, and sample tested at  
AD9020JZ  
AD9020JE  
AD9020KZ  
AD9020KE  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
68-Pin Leaded Ceramic  
Z-68  
specified temperatures.  
68-T erminal Ceramic LCC E-68A  
68-Pin Leaded Ceramic Z-68  
68-T erminal Ceramic LCC E-68A  
Z-68  
AD9020SE/883 –55°C to +125°C 68-T erminal Ceramic LCC E-68A  
AD9020T Z/883 –55°C to +125°C 68-Pin Leaded Ceramic Z-68  
AD9020T E/883 –55°C to +125°C 68-T erminal Ceramic LCC E-68A  
AD9020/PCB 0°C to +70°C Evaluation Board  
III – Sample tested only.  
IV – Parameter is guaranteed by design and characterization  
testing.  
AD9020SZ/883 –55°C to +125°C 68-Pin Leaded Ceramic  
V
– Parameter is a typical value only.  
VI – All devices are 100% production tested at +25°C. 100%  
production tested at temperature extremes for extended  
temperature devices; sample tested at temperature ex-  
tremes for commercial/industrial devices.  
*E = Ceramic Leadless Chip Carrier; Z = Ceramic Leaded Chip Carrier.  
+
5.0V  
D IE LAYO UT AND MECH ANICAL INFO RMATIO N  
Die Dimensions . . . . . . . . . . . . . . . 206 ϫ 140 ϫ 15 (±2) mils  
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ϫ 4 mils  
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold  
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None  
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS  
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride  
0.1 µF  
3,6,15,18,25,30,33,34,  
37,40,45,52,55,65,68  
510Ω  
510Ω  
100Ω  
510Ω  
8
9
19  
23  
+
VS  
AD1  
AD2  
ANALOG IN  
D0 – D4  
14 ENCODE  
46  
D
5 – D9  
51  
+
+2V  
–2V  
12  
56  
VREF  
AD9020  
_
VREF  
4,5,13,17,  
27,31,32,  
36,38,39,  
59  
61  
LSBs INVERT  
MSB INVERT  
GROUND  
43,53,66,67  
–
V
S
2,16,28,29,35,  
41,42,54,64  
STATIC: AD1 = –2V; AD2 = +2.4V  
DYNAMIC: AD1 = ±2V TRIANGLE WAVE  
0.1µF  
AD2 = TTL PULSE TRAIN  
–5.2V  
AD9020 Burn-In Circuit  
REV. A  
–4–  
AD9020  
9
61  
60  
10  
NC  
NC  
SENSE  
+V  
LSBs INVERT  
NC  
+V  
REF  
–V  
GND  
SENSE  
–V  
ENCODE  
REF  
+V  
+V  
S
S
–V  
S
GND  
–V  
S
AD9020  
TOP VIEW  
(Not to Scale)  
GND  
+V  
+V  
S
S
(LSB) D  
0
OVERFLOW  
D
D
(MSB)  
1
9
D
2
D
D
D
D
8
7
D
3
D
4
6
5
NC  
+V  
+V  
S
S
26  
NC  
44  
43  
NC  
27  
NC = NO CONNECT  
AD 9020 P IN FUNCTIO N D ESCRIP TIO NS  
P in No.  
Nam e  
Function  
1
1/2REF  
–VS  
Midpoint of internal reference ladder.  
Negative supply voltage; nominally –5.0 V ± 5%.  
2, 16, 28, 29, 35, 41, 42,  
54, 64  
3, 6, 15, 18, 25, 30, 33, 34,  
37, 40, 45, 52, 55, 65, 68  
+VS  
Positive supply voltage; nominally +5 V ± 5%.  
4, 5, 13, 17, 27, 31, 32,  
36, 38, 39, 43, 53, 66, 67  
GROUND  
All ground pins should be connected together and to low impedance ground  
plane.  
7
3/4REF  
T hree-quarter point of internal reference ladder.  
8, 9  
11  
ANALOG IN  
+VSENSE  
Analog input; nominally between ±1.75 V.  
Voltage sense line to most positive point on internal resistor ladder.  
Normally +1.75 V.  
12  
+VREF  
Voltage force connection for top of internal reference ladder. Normally driven  
to provide +1.75 V at +VSENSE  
.
14  
ENCODE  
D0–D9  
T T L-compatible convert command used to begin digitizing process.  
T T L-compatible digital output data.  
19–23, 46–50  
51  
56  
OVERFLOW  
–VREF  
T T L-compatible output indicating ANALOG IN > +VSENSE  
.
Voltage force connection for bottom of internal reference ladder. Normally  
driven to provide –1.75 V at –VSENSE  
.
57  
59  
61  
63  
–VSENSE  
Voltage sense line to most negative point on internal resistor ladder.  
Normally –1.75 V.  
LSBs INVERT  
MSB INVERT  
1/4REF  
Normally grounded. When connected to +VS, lower order bits (D0–D8) are  
inverted.  
Normally grounded. When connected to +VS, most significant bit (MSB; D9)  
is inverted.  
One-quarter point of internal reference ladder.  
REV. A  
–5–  
AD9020  
TH EO RY O F O P ERATIO N  
Receiver sensitivity is limited by the Signal-to-Noise Ratio of the  
system. T he SNR for an ADC is measured in the frequency do-  
main and calculated with a Fast Fourier T ransform (FFT ). T he  
SNR equals the ratio of the fundamental component of the sig-  
nal (rms amplitude) to the rms value of the noise. T he noise is  
the sum of all other spectral components, including harmonic  
distortion, but excluding dc.  
Refer to the AD9020 block diagram. As shown, the AD9020  
uses a modified “flash,” or parallel, A/D architecture. T he ana-  
log input range is determined by an external voltage reference  
(+VREF and –VREF), nominally ±1.75 V. An internal resistor lad-  
der divides this reference into 512 steps, each representing two  
quantization levels. T aps along the resistor ladder (1/4REF  
,
1/2REF and 3/4REF) are provided to optimize linearity. Rated per-  
formance is achieved by driving these points at 1/4, 1/2 and 3/4,  
respectively, of the voltage reference range.  
Good receiver design minimizes the level of spurious signals in  
the system. Spurious signals developed in the ADC are the re-  
sult of imperfections in the device transfer function (non-  
linearities, delay mismatch, varying input impedance, etc.). In  
the ADC, these spurious signals appear as Harmonic Distortion.  
Harmonic Distortion is also measured with an FFT and is speci-  
fied as the ratio of the fundamental component of the signal  
(rms amplitude) to the rms value of the worst case harmonic  
(usually the 2nd or 3rd).  
T he A/D conversion for the nine most significant bits (MSBs) is  
performed by 512 comparators. T he value of the least signifi-  
cant bit (LSB) is determined by a unique interpolation scheme  
between adjacent comparators. T he decoding logic processes  
the comparator outputs and provides a 10-bit code to the output  
stage of the converter.  
Flash architecture has an advantage over other A/D architec-  
tures because conversion occurs in one step. T his means the  
performance of the converter is primarily limited by the speed  
and matching of the individual comparators. In the AD9020, an  
innovative interpolation scheme takes advantage of flash archi-  
tecture but minimizes the input capacitance, power and device  
count usually associated with that method of conversion.  
Two-Tone Intermodulation Distortion (IMD) is a frequently cited  
specification in receiver design. In narrow-band receivers, third-  
order IMD products result in spurious signals in the pass band  
of the receiver. Like mixers and amplifiers, the ADC is charac-  
terized with two, equal-amplitude, pure input frequencies. T he  
IMD equals the ratio of the power of either of the two input sig-  
nals to the power of the strongest third-order IMD signal. Un-  
like mixers and amplifiers, the IMD does not always behave as it  
does in linear devices (reduced input levels do not result in pre-  
dictable reductions in IMD).  
T hese advantages occur by using only half the normal number  
of input comparator cells to accomplish the conversion. In addi-  
tion, a proprietary decoding scheme minimizes error codes. In-  
put control pins allow the user to select from among Binary,  
Inverted Binary, T wos Complement and Inverted T wos  
Complement coding (see AD9020 T ruth T able).  
Performance graphs provide typical harmonic and SNR data for  
the AD9020 for increasing analog input frequencies. In choos-  
ing an A/D converter, always look at the dynamic range for the  
analog input frequency of interest. T he AD9020 specifications  
provide guaranteed minimum limits at three analog test  
frequencies.  
AP P LICATIO NS  
Many of the specifications used to describe analog/digital con-  
verters have evolved from system performance requirements in  
these applications. Different systems emphasize particular speci-  
fications, depending on how the part is used. T he following ap-  
plications highlight some of the specifications and features that  
make the AD9020 attractive in these systems.  
Aperture Delay is the delay between the rising edge of the EN-  
CODE command and the instant at which the analog input is  
sampled. Many systems require simultaneous sampling of more  
than one analog input signal with multiple ADCs. In these situ-  
ations, timing is critical and the absolute value of the aperture  
delay is not as critical as the matching between devices.  
Wideband Receiver s  
Radar and communication receivers (baseband and direct IF  
digitization), ultrasound medical imaging, signal intelligence  
and spectral analysis all place stringent ac performance require-  
ments on analog-to-digital converters (ADCs). Frequency do-  
main characterization of the AD9020 provides signal-to-noise  
ratio (SNR) and harmonic distortion data to simplify selection  
of the ADC.  
Aperture Uncertainty, or jitter, is the sample-to-sample variation  
in aperture delay. T his is especially important when sampling  
high slew rate signals in wide bandwidth systems. Aperture un-  
certainty is one of the factors that degrade dynamic performance  
as the analog input frequency is increased.  
REV. A  
–6–  
AD9020  
D igitizing O scilloscopes  
T he actual resolution of the converter is limited by the thermal  
and quantization noise of the ADC. T he low frequency test for  
SNR or ENOB is a good measure of the noise of the AD9020.  
At this frequency, the static errors in the ADC determine the  
useful dynamic range of the ADC.  
Oscilloscopes provide amplitude information about an observed  
waveform with respect to time. Digitizing oscilloscopes must ac-  
curately sample this signal, without distorting the information to  
be displayed.  
One figure of merit for the ADC in these applications is Effective  
Number of Bits (ENOBs). ENOB is calculated with a sine wave  
curve fit and equals:  
Although the signal being sampled does not have a significant  
slew rate, this does not imply dynamic performance is not im-  
portant. T he Transient Response and Overvoltage Recovery Time  
specifications insure that the ADC can track full-scale changes  
in the analog input sufficiently fast to capture a valid sample.  
ENOB = N – LOG2 [Error (measured)/Error (ideal)]  
N is the resolution (number of bits) of the ADC. T he measured  
error is the actual rms error calculated from the converter out-  
puts with a pure sine wave input.  
Transient Response is the time required for the AD9020 to  
achieve full accuracy when a step function is applied. Overvolt-  
age Recovery Time is the time required for the AD9020 to re-  
cover to full accuracy after an analog input signal 150% of full  
scale is reduced to the full-scale range of the converter.  
T he Analog Bandwidth of the converter is the analog input fre-  
quency at which the spectral power of the fundamental signal is  
reduced 3 dB from its low frequency value. T he analog band-  
width is a good indicator of a converter’s stewing capabilities.  
P r ofessional Video  
Digital Signal Processing (DSP) is now common in television  
production. Modern studios rely on digitized video to create  
state-of-the-art special effects. Video instrumentation also re-  
quires high resolution ADCs for studio quality measurement  
and frame storage.  
T he Maximum Conversion Rate is defined as the encode rate at  
which the SNR for the lowest analog signal test frequency tested  
drops by no more than 3 dB below the guaranteed limit.  
Im aging  
Visible and infrared imaging systems both require similar char-  
acteristics from ADCs. T he signal input (from a CCD camera,  
or multiplexer) is a time division multiplexed signal consisting of  
a series of pulses whose amplitude varies in direct proportion to  
the intensity of the radiation detected at the sensor. T hese vary-  
ing levels are then digitized by applying encode commands at  
the correct times, as shown below.  
T he AD9020 provides sufficient resolution for these demanding  
applications. Conversion speed, dynamic performance and ana-  
log bandwidth are suitable for digitizing both composite and  
RGB video sources.  
FS  
+
AD9020  
A
IN  
FS  
–
ENCODE  
Im aging Application Using AD9020  
REV. A  
–7–  
AD9020  
USING TH E AD 9020  
Voltage Refer ences  
T he select resistors (RS) shown in the schematic (each pair can  
be a potentiometer) are chosen to adjust the quarter-point volt-  
age references, but are not necessary if R1–R4 match within  
0.05%.  
T he AD9020 requires that the user provide two voltage refer-  
ences: +VREF and –VREF. T hese two voltages are applied across  
an internal resistor ladder (nominally 37 Ω) and set the analog  
input voltage range of the converter. T he voltage references  
should be driven from a stable, low impedance source. In addi-  
tion to these two references, three evenly spaced taps on the re-  
sistor ladder (1/4REF, 1/2REF, 3/4REF) are available. Providing a  
reference to these quarter points on the resistor ladder will im-  
prove the integral linearity of the converter and improve ac per-  
formance. (AC and dc specifications are tested while driving the  
quarter points at the indicated levels.) T he figure below is not  
intended to show the transfer function of the ADC, but illus-  
trates how the linearity of the device is affected by reference  
voltages applied to the ladder.  
An alternative approach for defining the quarter-point refer-  
ences of the resistor ladder is to evaluate the integral linearity  
error of an individual device, and adjust the voltage at the  
quarter-points to minimize this error. T his may improve the low  
frequency ac performance of the converter.  
Performance of the AD9020 has been optimized with an analog  
input voltage of ±1.75 V (as measured at ±VSENSE). If the ana-  
log input range is reduced below these values, relatively larger  
differential nonlinearity errors may result because of comparator  
mismatches. As shown in the figure below, performance of the  
converter is a function of ±VSENSE  
.
62  
10.0  
9.0  
56  
50  
8.0  
44  
38  
32  
7.0  
6.0  
5.0  
2.0  
0.4  
0.6  
0.8  
1.0  
±V  
1.2  
1.4  
1.6  
1.8  
– Volts  
SENSE  
AD9020 SNR and ENOB vs. Reference Voltage  
Effect of Reference Taps on Linearity  
Applying a voltage greater than 4 V across the internal resistor  
ladder will cause current densities to exceed rated values, and  
may cause permanent damage to the AD9020. T he design of  
the reference circuit should limit the voltage available to the  
references.  
Resistance between the reference connections and the taps of  
the first and last comparators causes offset errors. T hese errors,  
called “top and bottom of the ladder offsets,” can be nulled by  
using the voltage sense lines, +VSENSE and –VSENSE, to adjust the  
reference voltages. Current through the sense lines should be  
limited to less than 100 µA. Excessive current drawn through  
the voltage sense lines will affect the accuracy of the sense line  
voltage.  
Analog Input Signal  
T he signal applied to ANALOG IN drives the inputs of 512  
parallel comparator cells (see Equivalent Analog Input figure).  
T his connection typically has an input resistance of 7 kΩ, and  
input capacitance of 45 pF. T he input capacitance is nearly  
constant over the analog input voltage range, as shown in the  
graph which illustrates that characteristic.  
T he next page shows a reference circuit which nulls out the off-  
set errors using two op amps and provides appropriate voltage  
references to the quarter-point taps. Feedback from the sense  
lines causes the op amps to compensate for the offset errors.  
T he two transistors limit the amount of current drawn directly  
from the op amps; resistors at the base connections stabilize  
their operation. T he 10 kΩ resistors (R1–R4) between the volt-  
age sense lines form an external resistor ladder; the quarter  
point voltages are taken off this external ladder and buffered by  
an op amp. T he actual values of resistors R1–R4 are not critical,  
but they should match well and be large enough (≥10 kΩ) to  
limit the amount of current drawn from the voltage sense lines.  
T he analog input signal should be driven from a low distortion,  
low noise amplifier. A good choice is the AD9617, a wide band-  
width, monolithic operational amplifier with excellent ac and dc  
performance. T he input capacitance should be isolated by a  
small series resistor (24 Ω for the AD9617) to improve the ac  
performance of the amplifier (see AD9020/PCB Evaluation  
Board Block Diagram).  
REV. A  
–8–  
AD9020  
+V  
ANALOG INPUT  
SENSE  
+5V  
150Ω  
1/2 AD708  
*
12  
11  
+VREF  
0.1µF  
+1.75V  
3/4  
+VSENSE  
REF  
R/2  
R
R1  
10kΩ  
RS  
RS  
+0.875V  
1/2  
R/2  
R/2  
REF  
3/4REF  
1/2REF  
1/4REF  
1/2 AD708  
7
0.1µF  
0.1 µF  
0.1 µF  
R2  
10kΩ  
R
R
1/4  
REF  
+2.5V  
RS  
+1.75V  
356Ω  
0V  
AD580  
R/2  
R/2  
R
150Ω  
RS 1/2 AD708  
1
R3  
10kΩ  
R
–0.875V  
–V  
R/2  
R/2  
R
SENSE  
1/2 AD708  
63  
AD9020 Equivalent Analog Input  
R4  
10kΩ  
+
VS  
R
R
20kΩ  
R/2  
DIGITAL BITS  
AND OVERFLOW  
–VSENSE  
57  
56  
20kΩ  
–1.75V  
*
–VREF  
*
= WIRING  
1/2 AD708  
0.1µF  
RESISTANCE = < 5Ω  
150Ω  
AD9020  
–
5V  
AD9020 Equivalent Digital Outputs  
AD9020 Reference Circuit  
+
5.0V  
13k  
ENCODE 14  
AD9020 Equivalent Encode Circuit  
REV. A  
–9–  
AD9020  
N
ANALOG  
INPUT  
N + 1  
ta  
N
N + 1  
ENCODE  
tOD  
DATA  
OUTPUT  
DATA FOR N  
DATA FOR N + 1  
ta  
tOD  
– Aperture Delay  
– Output Delay  
AD9020 Tim ing Diagram  
Tim ing  
Layout and P ower Supplies  
In the AD9020, the rising edge of the ENCODE signal triggers  
the A/D conversion by latching the comparators. (See the  
AD9020 T iming Diagram.)  
Proper layout of high speed circuits is always critical but is par-  
ticularly important when both analog and digital signals are  
involved.  
T he ENCODE is T T L/CMOS compatible and should be driven  
from a low jitter (phase noise) source. Jitter on the ENCODE  
signal will raise the noise floor of the converter. Fast, clean  
edges will reduce the jitter in the signal and allow optimum ac  
performance. Locking the system clock to a crystal oscillator  
also helps reduce jitter. T he AD9020 is designed to operate with  
a 50% duty cycle; small (10%) variations in duty cycle should  
not degrade performance.  
Analog signal paths should be kept as short as possible and be  
properly terminated to avoid reflections. T he analog input volt-  
age and the voltage references should be kept away from digital  
signal paths; this reduces the amount of digital switching noise  
that is capacitively coupled into the analog section of the circuit.  
Digital signal paths should also be kept short, and run lengths  
should be matched to avoid propagation delay mismatch.  
In high speed circuits, layout of the ground circuit is a critical  
factor. A single, low impedance ground plane, on the compo-  
nent side of the board, will reduce noise on the circuit ground.  
Power supplies should be capacitively coupled to the ground  
plane to reduce noise in the circuit. Multilayer boards allow  
designers to lay out signal traces without interrupting the  
ground plane and provide low impedance power planes.  
D ata For m at  
T he format of the output data (D0–D9) is controlled by the  
MSB INVERT and LSBs INVERT pins. T hese inputs are dc  
control inputs, and should be connected to GROUND or +VS.  
T he AD9020 T ruth T able gives information to choose from  
among Binary, Inverted Binary, T wos Complement and In-  
verted T wos Complement coding.  
It is especially important to maintain the continuity of the  
ground plane under and around the AD9020. In systems with  
dedicated digital and analog grounds, all grounds of the  
AD9020 should be connected to the analog ground plane.  
T he OVERFLOW output is an indication that the analog input  
signal has exceeded the voltage at +VSENSE. T he accuracy of the  
overflow transition voltage and output delay are not tested or in-  
cluded in the data sheet limits. Performance of the overflow in-  
dicator is dependent on circuit layout and slew rate of the  
encode signal. T he operation of this function does not affect the  
other data bits (D0–D9). It is not recommended for applications  
requiring a critical measure of the analog input voltage.  
The power supplies (+VS and –VS) of the AD9020 should be iso-  
lated from the supplies used for external devices; this further re-  
duces the amount of noise coupled into the A/D converter.  
Sockets limit the dynamic performance and should be used only  
for prototypes or evaluation—PCK Elastomerics Part # CCS-68-  
55 is recommended for the LCC package. (Tel. 215-672-0787)  
An evaluation board is available to aid designers and provide a  
suggested layout.  
REV. A  
–10–  
AD9020  
10.0  
62  
56  
62  
56  
10.0  
9.0  
ENCODE RATE = 40MSPS  
9.0  
ANALOG INPUT = 2.3MHz  
8.0  
7.0  
6.0  
50  
44  
8.0  
7.0  
6.0  
50  
44  
38  
+25°C  
+55°C & +125°C  
38  
32  
26  
20  
5.0  
4.0  
32  
26  
20  
5.0  
4.0  
1
2
4
6
8 10  
20  
40 60 100  
200  
1
2
4
6
8 10  
20  
40 60  
100  
INPUT FREQUENCY – MHz  
CONVERSION RATE – MSPS  
AD9020 SNR and ENOB vs. Input Frequency  
AD9020 SNR and ENOB vs. Conversion Rate  
30  
35  
40  
70  
60  
48  
47  
46  
45  
50  
40  
30  
20  
RESISTANCE  
+
125  
C
45  
50  
55  
CAPACITANCE  
–
55 C  
+
25 C  
60  
65  
70  
44  
10  
2
6
8 10  
20  
40 60 100  
1
4
+
+
1.2  
+
1.8  
–1.8  
–1.2  
–0.6  
0
0.6  
INPUT FREQUENCY – MHz  
ANALOG INPUT (AIN ) – Volts  
AD9020 Harm onics vs. Input Frequency  
Input Capacitance/Resistance vs. Input Voltage  
AD 9020 Truth Table  
O ffset Binary  
Inverted  
Twos Com plem ent  
Step  
Range  
= –1.75 V  
FS = +1.75 V  
True  
MSB INV = “ 0”  
LSBs INV = “ 0”  
True  
Inverted  
MSB INV = “ 0”  
LSBs INV = “ 1”  
0
MSB INV = “ 1”  
LSBs INV = “ 1”  
MSB INV = “ 1”  
LSBs INV = “ 0”  
1024  
1023  
1022  
•
> +1.7500  
+1.7466  
+1.7432  
(1)1111111111  
(1)0000000000  
(1)0111111111  
(1)1000000000  
1111111111  
1111111110  
0000000000  
0000000001  
0111111111  
0111111110  
1000000000  
1000000001  
•
•
•
•
•
•
•
•
•
•
•
•
•
+0.0034  
0.000  
–0.0034  
•
•
•
•
•
512  
511  
510  
•
1000000000  
0111111111  
0111111110  
•
0111111111  
1000000000  
1000000001  
•
0000000000  
1111111111  
1111111110  
•
1111111111  
0000000000  
0000000001  
•
•
•
•
•
•
•
•
•
•
•
•
•
02  
01  
00  
–1.7432  
–1.7466  
<–1.7466  
0000000010  
0000000001  
0000000000  
1111111101  
1111111110  
1111111111  
1000000010  
1000000001  
1000000000  
0111111101  
0111111110  
0111111111  
T he overflow bit is always 0 except where noted in parentheses ( ). MSB INVERT and LSBs INVERT are considered dc controls.  
REV. A  
–11–  
AD9020  
AD 9020/P CB EVALUATIO N BO ARD  
On-board reconstruction of the digital data is provided through  
the AD9713, a 12-bit monolithic DAC. T he analog and recon-  
structed waveforms can be summed on the board to allow the  
user to observe the linearity of the AD9020 and the effects of  
the quarterpoint voltages. T he digital data and an adjustable  
Data Ready signal are available through a 37-pin edge connector.  
T he AD9020/PCB Evaluation Board is available from the fac-  
tory and is shown here in block diagram form. T he board in-  
cludes a reference circuit that allows the user to adjust both  
references and the quarter-point voltages. T he AD9617 is in-  
cluded as the drive amplifier, and the user can configure the  
gain from –1 to –15.  
DAC  
OUT  
–
+
5V  
5V  
AD9713 DAC I  
OUT  
TO ERROR  
WAVEFORM  
CIRCUIT  
50Ω  
D
DUT  
ANALOG  
INPUT  
+
–V  
MSB INVERT  
LSBs INVERT  
5V  
+V  
S
GND  
S
BUFFERED  
ANALOG  
INPUT  
400Ω  
J2  
200Ω  
D
D
D
D
D
D
D
D
D
D
D
(LSB) D  
D
0
24Ω  
U5  
AD9617  
ANALOG  
INPUT  
1
2
3
4
5
6
7
8
50Ω  
D
D
D
D
D
D
D
OUTPUT  
DATA  
CONNECTOR  
Q
TTL  
LATCHES  
AD9020  
DUT  
TO ERROR  
WAVEFORM  
CIRCUIT  
+V  
DATA  
READY  
REF  
+V  
SENSE  
3/4  
(MSB) D  
REF  
REF  
9
CLK  
REFERENCE  
CIRCUIT  
OVERFLOW  
1/2  
1/4  
REF  
–V  
SENSE  
REF  
TTL CLK  
TIMING  
CIRCUIT  
–V  
ENCODE  
AD9020/PCB Evaluation Board Block Diagram  
O UTLINE D IMENSIO NS  
D imensions shown in inches and (mm).  
68-Leaded Cer am ic Chip Car r ier  
(Z-68)  
68-Ter m inal  
Leadless Chip Car r ier (LCC)  
(E-68A)  
REV. A  
–12–  

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