AD9022AQ_技术文档

12-Bit 20 MSPS

a

Monolithic A/D Converter

AD9022

FUNCTIO NAL BLO CK D IAGRAM

FEATURES

Monolithic

12-Bit 20 MSPS A/ D Converter

Low Pow er Dissipation: 1.4 Watts

On-Chip T/ H and Reference

High Spurious-Free Dynam ic Range

TTL Logic

5-BIT

ADC

ANALOG

INPUT

T/H

DIGITAL

ERROR

CORRECTION

12

AD9022

TTL

5-BIT

ADC

DAC

ENCODE

+5V

APPLICATIONS

Radar Receivers

Digital Com m unications

Digital Instrum entation

Electro-Optics

T/H

16

DAC

–5.2V

GND

+2V

REF

4-BIT

ADC

8

P RO D UCT D ESCRIP TIO N

With DNL typically less than 0.5 LSB and 20 ns transient re-

sponse settling time, the AD9022 provides excellent results

when low-frequency analog inputs must be oversampled (such

as CCD digitization). T he full scale analog input is ±1 V with a

300 Ω input impedance. T he analog input can be driven directly

from the signal source, or can be buffered by the AD96xx series

of low noise, low distortion buffer amplifiers.

T he AD9022 is a high speed, high performance, monolithic

12-bit analog-to-digital converter. All necessary functions, in-

cluding track-and-hold (T /H ) and reference, are included

on-chip to provide a complete conversion solution. It is a

companion unit to the AD9023; the primary difference between

the two is that all logic for the AD9022 is T T L-compatible,

while the AD9023 utilizes ECL logic for digital inputs and out-

puts. Pinouts for the two parts are nearly identical.

All timing is internal to the AD9022; the clock signal initiates

the conversion cycle. For best results, the encode command

should contain as little jitter as possible. High speed layout

practices must be followed to ensure optimum A/D perfor-

mance.

Operating from +5 V and –5.2 V supplies, the AD9022 pro-

vides excellent dynamic performance. Sampling at 20 MSPS

with A_IN= 1 MHz, the spurious-free dynamic range (SFDR) is

typically 76 dB; with A_IN= 9.6 MHz, SFDR is 74 dB. SNR is

typically 65 dB.

T he AD9022 is built on a trench isolated bipolar process and

utilizes an innovative multipass architecture (see the block

diagram). T he unit is packaged in 28-lead ceramic DIPs and

gullwing surface mount packages. T he AD9022 is specified to

operate over the industrial (–25°C to +85°C) and military

(–55°C to +125°C) temperature ranges.

T he onboard T /H has a 110 MHz bandwidth and, more impor-

tantly, is designed to provide excellent dynamic performance for

analog input frequencies above Nyquist. T his feature is neces-

sary in many undersampling signal processing applications, such

as in direct IF-to-digital conversion.

T o maintain dynamic performance at higher IFs, monolithic

RF track-and-holds (such as the AD9100 and AD9101

Samplifier™) can be used with the AD9022 to process signals

up to and beyond 70 MHz.

Samplifier is a trademark of Analog Devices, Inc.

REV. B

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 781/ 329-4700

Fax: 781/ 326-8703

World Wide Web Site: http:/ / w w w .analog.com

AD9022–SPECIFICATIONS

(+V = +5 V; –V = –5.2 V; Encode = 20 MSPS, unless otherwise noted)

S

ELECTRICAL CHARACTERISTICS

Test

AD 9022AQ /AZ

AD 9022BQ /BZ

AD 9022SQ /SZ

P ar am eter (Conditions)

Tem p

Level

Min Typ Max Min Typ Max

Min Typ Max

Units

RESOLUT ION

12 12

12

Bits

DC ACCURACY

Differential Nonlinearity

+25°C

Full

+25°C

Full

+25°C

Full

+25°C

Full

+25°C

I

VI

I

VI

I

VI

I

0.6

0.75

1.0

2.5

0.4

0.5

1.0

2.0

3.0

0.6

0.75

1.0

2.5

LSB

Integral Nonlinearity

1.3

1.6

Guaranteed

1.3

1.6

Guaranteed

1.3

1.6

Guaranteed

3.0

No Missing Codes

Offset Error

5

15

0.5

0.6

0.57

25

35

2.5

3.5

5

15

0.5

0.6

0.57

25

35

2.5

3.5

5

15

0.5

0.6

0.57

25

35

2.5

3.5

mV

% FS

LSB, rms

Gain Error

VI

V

T hermal Noise

ANALOG INPUT

Input Voltage Range

Input Resistance

±1.024

240 300 360

±1.024

240 300 360

±1.024

240 300 360

V

Ω

pF

MHz

Full

+25°C

IV

V

Input Capacitance

Analog Bandwidth

5

110

5

110

5

110

SWIT CHING PERFORMANCE¹

Minimum Conversion Rate

Maximum Conversion Rate

Aperture Delay (t_A)

+25°C

Full

+25°C

Full

IV

VI

IV

V

4

MSPS

ns

ps, rms

ns

20

0.55 0.71 0.85

6

0.55 0.71 0.85

6

0.55 0.71 0.85

6

Aperture Uncertainty (Jitter)

Output Delay (t_OD

)

VI

15

27.5

15

27.5

15

27.5

ENCODE INPUT

Logic Compatibility

Logic “1” Voltage

Logic “0” Voltage

Logic “1” Current

Logic “0” Current

Input Capacitance

Pulsewidth (High)

Pulsewidth (Low)

T T L

Full

+25°C

VI

V

IV

2.0

V

0.8

20

0.8

20

0.8

20

8

6

8

6

8

6

µA

pF

ns

22.5

20

125

22.5

20

125

22.5

20

125

DYNAMIC PERFORMANCE

T ransient Response

Overvoltage Recovery T ime

Harmonic Distortion

Analog Input @ 1.2 MHz

@ 1.2 MHz

+25°C

V

20

ns

+25°C

Full

+25°C

Full

I

65

63

62

61

73

70

73

72

68

70

69

64

63

75

72

75

74

72

65

63

62

61

73

70

73

72

68

dBc

V

I

@ 4.3 MHz

@ 9.6 MHz

V

Signal-to-Noise Ratio²

Analog Input @ 1.2 MHz

@ 1.2 MHz

+25°C

Full

+25°C

Full

I

64

63

64

63

62

66

65

66

65

63

64

63

64

63

62

dB

V

I

@ 4.3 MHz

@ 9.6 MHz

V

Signal-to-Noise Ratio²

(Without Harmonics)

Analog Input @ 1.2 MHz

@ 1.2 MHz

+25°C

Full

+25°C

Full

I

63

62

66

64

66

65

63

65

64

67

66

65

63

62

66

64

66

65

63

dB

V

I

@ 4.3 MHz

@ 9.6 MHz

V

REV. B

–2–

AD9022

Test

AD 9022AQ /AZ

AD 9022BQ /BZ

AD 9022SQ /SZ

P ar am eter (Conditions)

Tem p

Level

Min Typ Max Min Typ Max

Min Typ Max

Units

T wo-T one Intermodulation

Distortion Rejection³

+25°C

V

74

dBc

DIGIT AL OUT PUT S¹

Logic Compatibility

Logic “1” Voltage

Logic “0” Voltage

Output Coding

T T L

2.4

Full

VI

2.4

V

0.5

Offset Binary

0.5

Offset Binary

0.5

Offset Binary

POWER SUPPLY

+V_SSupply Voltage

+V_SSupply Current

–V_SSupply Voltage

–V_SSupply Current

Power Dissipation

Power Supply

Full

VI

4.75 5.0

100 120

–5.45 –5.2 –4.95 –5.45 –5.2 –4.95 –5.45 –5.2 –4.95

180 220 180 220 180 220

5.25

4.75 5.0

5.25

4.75 5.0

5.25

mA

W

100 120

1.4

1.9

1.4

1.9

1.4

1.9

Rejection Ratio (PSRR)⁴

Full

V

32

mV/V

NOT ES

¹AD9022 load is a single LS latch.

²RMS signal-to-rms noise with analog input signal 1 dB below full scale at specified frequency. T ested at 55% duty cycle.

³Intermodulation measured with analog input frequencies of 8.9 MHz and 9.8 MHz at 7 dB below full scale.

⁴PSRR is sensitivity of offset error to power supply variations within the 5% limits shown.

Specifications subject to change without notice.

N

ANALOG

IN

t_a

N + 1

t_a= 0.7 TYPICAL

N + 2

t_OD

ENCODE

t_OD= 15–27.5 TYPICAL

N – 2

DATA

OUTPUT

N – 3

N – 1

N

AD9022 Tim ing Diagram

ABSO LUTE MAXIMUM RATINGS ¹

O RD ERING GUID E

+V_S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V

–V_S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V

Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +1.5 V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +V_Sto 0 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating T emperature Range

Tem perature

Range

P ackage

D escription

P ackage

O ption

Model

AD9022AQ/BQ –25°C to +85°C 28-Lead Ceramic DIP Q-28

AD9022AZ/BZ –25°C to +85°C 28-Pin Ceramic

Z-28

Leaded Chip Carrier

AD9022AQ/AZ/BQ/BZ . . . . . . . . . . . . . . . –25°C to +85°C

AD9022SQ/SZ . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Maximum Junction T emperature². . . . . . . . . . . . . . . . +175°C

Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C

AD9022SQ

AD9022SZ

–55°C to +125°C 28-Lead Ceramic DIP Q-28

–55°C to +125°C 28-Pin Ceramic

Z-28

Leaded Chip Carrier

NOT ES

¹Absolute maximum ratings are limiting values to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional

operability is not necessarily implied. Exposure to absolute maximum rating

conditions for an extended period of time may affect device reliability.

²T ypical thermal impedances: “Q” Package (Ceramic DIP): θ_JC= 10°C/W; θ_JA

=

35°C/W. “Z” Package (Gullwing Surface Mount): θ_JC= 13°C/W; θ_JA= 45°C/W.

REV. B

–3–

AD9022

P IN FUNCTIO N D ESCRIP TIO NS

EXP LANATIO N O F TEST LEVELS

Test Level

P in No.

Nam e

Function

I

– 100% production tested.

1–3

D3–D1

Digital output bits of ADC; T T L

compatible.

II – 100% production tested at +25°C, and sample tested at

specified temperatures. AC testing done on sample basis.

4

D0 (LSB)

Least significant bit of ADC output;

T T L compatible.

III – Sample tested only.

IV – Parameter is guaranteed by design and characterization

testing.

5

6

7

8

NC

No Connection Internally

+5 V Power Supply

Ground

+V_S

V

– Parameter is a typical value only.

GND

ENCODE

VI – All devices are 100% production tested at +25°C. 100%

production tested at temperature extremes for extended

temperature devices; guaranteed by design and character-

ization testing for industrial devices.

Encode clock input to ADC. Internal

T /H is placed in hold mode (ADC is

encoding) on rising edge of encode

signal.

9

GND

+V_S

Ground

10

11

12

13

14

15

16

17

+5 V Power Supply

Ground

D IE LAYO UT AND MECH ANICAL INFO RMATIO N

Die Dimensions . . . . . . . . . . . . . . . . 205 × 228 × 21 (±1) mils

Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils

Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum

Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V_S

T ransistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4,080

Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride

Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum

GND

A_IN

Noninverting input to T /H amplifier.

–5.2 V Power Supply

+5 V Power Supply

–5.2 V Power Supply

Ground

–V_S

+V_S

–V_S

GND

COMP

Should be connected to –V_Sthrough

0.1 µF capacitor.

18

D11 (MSB) Most significant bit of ADC output;

T T L compatible.

19–25

D10–D4

Digital output bits of ADC; T T L

compatible.

26

27

28

+V_S

–V_S

+5 V Power Supply

–5.2 V Power Supply

Ground

GND

P IN D ESIGNATIO NS

D3

D2

D1

GND

1

2

3

4

5

6

7

8

9

28

27 –V

S

26

25

24

+V

D4

D5

D0 (LSB)

NC

+V

23 D6

S

AD9022

TOP VIEW

(Not to Scale)

22

21

20

19

18

17

16

15

GND

ENCODE

GND

D7

D8

D9

+V 10

S

D10

GND 11

D11(MSB)

COMP

GND

A

12

IN

–V 13

S

+V 14

S

–V

S

NC = NO CONNECT

COMPENSATION (PIN 17) SHOULD BE

CONNECTED TO –V THROUGH 0.01␮F

S

–4–

REV. B

AD9022

+V

S

D EFINITIO NS O F SP ECIFICATIO NS

Analog Bandwidth

T he analog input frequency at which the spectral power of the

fundamental frequency (as determined by FFT analysis) is

reduced by 3 dB.

+V

S

Aper tur e D elay

T he delay between the rising edge of the ENCODE command

and the instant at which the analog input is sampled.

180⍀

120⍀

ANALOG

INPUT

10pF

Aper tur e Uncer tainty (Jitter )

T he sample-to-sample variation in aperture delay.

–V

S

D iffer ential Nonlinear ity

T he deviation of any code from an ideal 1 LSB step.

H ar m onic D istor tion

Analog Input

T he rms value of the fundamental divided by the rms value of

the worst harmonic component.

+V

S

100⍀

Integr al Nonlinear ity

ENCODE

T he deviation of the transfer function from a reference line

measured in fractions of 1 LSB using a “best straight line” de-

termined by a least square curve fit.

900⍀

Minim um Conver sion Rate

T he encode rate at which the SNR of the lowest analog signal

frequency tested drops by no more than 3 dB below the guaran-

teed limit.

–V

S

Encode Input

Maxim um Conver sion Rate

T he encode rate at which parametric testing is performed.

COMPENSATION

O utput P r opagation D elay

T he delay between the 50% point of the rising edge of the EN-

CODE command and the time when all output data bits are

within valid logic levels.

–V

S

50⍀

O ver voltage Recover y Tim e

T he amount of time required for the converter to recover to

12-bit accuracy after an analog input signal 150% of full scale is

reduced to the full-scale range of the converter.

20pF

–V

S

P ower Supply Rejection Ratio (P SRR)

T he ratio of a change in input offset voltage to a change in

power supply voltage.

Com pensation

+V

S

Signal-to-Noise Ratio (SNR)

T he ratio of the rms signal amplitude to the rms value of

“noise,” which is defined as the sum of all other spectral compo-

nents, including harmonics but excluding dc, with an analog

input signal 1 dB below full scale.

11k⍀

12k⍀

DIGITAL

OUTPUT

Signal-to-Noise Ratio (Without H ar m onics)

T he ratio of the rms signal amplitude to the rms value of

“noise,” which is defined as the sum of all other spectral compo-

nents, excluding the first five harmonics and dc, with an analog

input signal 1 dB below full scale.

–V

S

Tr ansient Response

T he time required for the converter to achieve 12-bit accuracy

when a step function is applied to the analog input.

Output Stage

Figure 1. Equivalent Circuits

Two-Tone Inter m odulation D istor tion (IMD ) Rejection

T he ratio of the power of either of two input signals to the

power of the strongest third-order IMD signal.

–5–

REV. B

AD9022–Typical Performance Characteristics

70

65

60

55

50

45

–76

–75

+25؇C

–55؇C

+25؇C

ROOM

–74

–73

–72

–71

–70

–69

–68

–55؇C

+125؇C

40

35

1.24 2.3

5.3

7.3

9.6

11.3 13.3

15.3

17.3

19.3

0

1

2

3

4

5

6

7

8

9

10

ANALOG INPUT FREQUENCY – MHz

Figure 2. Harm onic Distortion vs. Analog Input

Frequency

Figure 5. Signal-to-Noise Ratio vs. Analog Input

Frequency

85

90

A

= 1.2MHz

A

= 1.2MHz

IN

ENCODE = 20MHz

IN

80

70

60

50

40

30

20

10

0

80

75

70

65

SFDR

WORST HARMONICS

SNR

60

55

5.0

7.5

10.0

12.5

15.0

17.5

20.0

22.5

25.0

–50 –45 –40 –35 –30 –25 –20 –15 –10

–5

–1

ENCODE RATE – MSPS

INPUT LEVEL – dB

Figure 3. SNR and Harm onics vs. Encode Rate

Figure 6. SFDR and SNR vs. Analog Input Level

2.0

1.5

80

A

F

= 1.2MHz

IN

A

= 9.6MHz

IN

ENCODE = 20MHz

70

SFDR

= 20MSPS

S

1.0

0.5

60

50

SNR

0

40

30

20

10

–0.5

–1.0

–1.5

–2.0

0

1024

2048

3072

4096

–50 –45 –40 –35 –30 –25 –20 –15 –10

–5

–1

OUTPUT CODE

INPUT LEVEL – dB

Figure 4. Differential Nonlinearity vs. Output Code

Figure 7. SFDR and SNR vs. Analog Input Level

–6–

REV. B

AD9022

is present when the unit is strobed with an ENCODE com-

mand. T he conversion process begins on the rising edge of this

pulse, which should conform to the minimum and maximum

pulsewidth requirements shown in the specifications. Operation

below the recommended encode rate (4 MSPS) may result in

excessive droop in the internal T /H devices–leading to large dc

and ac errors.

0

–10

A

= 1.2MHz

= –1.0dBFS

IN

A

IN

–20

–30

–40

SNR = 66.7dB

THD = 77.51dB

SFDR = 79.49dBFS

–50

–60

T he held analog value of the first track-and-hold is applied to a

5-bit flash converter and a second T /H. T he 5-bit flash con-

verter resolves the most significant bits (MSBs) of the held

analog voltage. T hese five bits are reconstructed via a 5-bit

DAC and subtracted from the original T /H output signal to

form a residue signal.

–70

–80

–90

–100

0

10

A second T /H holds the amplified residue signal while it is en-

coded with a second 5-bit flash ADC. Again the five bits are

reconstructed and subtracted from the second T /H output to

form a residue signal. T his residue is amplified and encoded

with a 4-bit flash ADC to provide the three least significant bits

(LSBs) of the digital output and one bit of error correction.

FREQUENCY – MHz

Figure 8. FFT Plot

0

A

= 9.6MHz

= –1.0dBFS

IN

–10

IN

SNR = 66.05dB

THD = 74.28dB

SFDR = 75.32dBFS

Digital Error Correction logic aligns the data from the three

flash converters and presents the result as a 12-bit parallel digi-

tal word. T he output stage of the AD9022 is T T L. Output data

may be strobed on the rising edge of the ENCODE command.

–20

–30

–40

–50

–60

AD 9022 IN RECEIVER AP P LICATIO NS

Advances in semiconductor processes have resulted in low cost

digital signal processing (DSP) and analog signal processing

which can help create cost effective alternative receiver designs.

T oday, an all-digital receiver allows tuning, demodulation, and

detection of receiver signals in the digital domain. By digitizing

IF signals directly, and utilizing digital techniques, it becomes

possible to make significant improvements in receiver design.

For high frequency IFs, the ADC is the key to the receiver’s

performance. Unfortunately, the specifications frequently used

by receiver designers and analog-to-digital (ADC) manufactur-

ers are often very different. Noise Figure and Intercept Point are

common measures of noise and linearity in analog RF system

design. ADCs are more frequently specified in terms of SNR

and harmonic distortion.

–70

–80

–90

–100

0

10

FREQUENCY – MHz

Figure 9. FFT Plot

0

A

= 8.9MHz

IN1

IN2

IN1

IN2

= 9.8MHz

= 7.0dBFS

20

SFDR = 80.62dBFS

40

60

Noise

Noise figure (NF) is a measure of receiver sensitivity and is

defined as the degradation of signal-to-noise ratio (SNR) as a

signal passes through a device. In equation form:

80

100

120

NF = SNR (in) – SNR (out)

Noise figure is a bandwidth invariant parameter for reasonably

narrow bandwidths in most devices. T he system noise figure for

a combination of amplifiers and mixers, for instance, can be

analyzed without regard to the information bandwidth.

0.0

2.0

4.0

6.0

8.0

10.0

FREQUENCY – MHz

T hermal noise contribution from the ADC behaves in a similar

fashion; however, the spectral density of quantization noise is a

function of the sample rate. In addition, the spectral density of

the quantization noise is flat only in an ADC with perfect linear-

ity, i.e., perfect 1 LSB step sizes.

Figure 10. Two-Tone FFT

TH EO RY O F O P ERATIO N

Refer to the block diagram.

T he AD9022 employs a three-pass subranging architecture and

digital error correction. T his combination of design techniques

ensures 12-bit accuracy at relatively low power.

T o analyze the system noise performance, ADC noise figure is

calculated by normalizing the SNR of the ADC output to a 1 Hz

bandwidth. T his result is given by:

Analog input signals are immediately attenuated through a

resistor divider and applied directly to the sampling bridge of

the track-and-hold (T /H). T he T /H holds whatever analog value

SNR (/Hz) = SNR + 10 log₁₀(F_S/2)

where F_Sis the sample rate.

–7–

REV. B

AD9022

T his will be true only for converters in which perfect quantiza-

tion noise dominates. T here may be an upper sample rate,

above which the thermal noise of the converter is the dominant

source of noise. In this case, normalization would be based on

the noise bandwidth of the ADC. For an AD9022 with a typical

SNR of 64 dB and a sample rate of 20 MSPS, the normalized

SNR is equal to 134 dB (64 + 70). Both thermal and quantiza-

tion noise contribute to this number.

AD 9022 NO ISE P ERFO RMANCE

High speed, wide bandwidth ADCs such as the AD9022 are

optimized for dynamic performance over a wide range of analog

input frequencies. However, there are many applications (Imag-

ing, Instrumentation, etc.) where dc precision is also important.

Due to the wide input bandwidth of the AD9022 for a given

input voltage, there will be a range of output codes which may

occur. T his is caused by unavoidable circuit noise within the

wideband circuits in the ADC. If a dc signal is applied to the

ADC and several thousand outputs are recorded, a distribution

of codes such as that shown in the histogram below may result.

T he SNR of the input is assumed to be limited by the thermal

noise of the input resistance, or –174 dBm/Hz. T he input signal

level is +10 dBm (2 V p-p into 50 Ω). Noise figure of the ADC

can be calculated by:

2.0

NF = SNR (in) – SNR (out) = [+10 – (174)] – 134 = 50 dB

ONE STANDARD

DEVIATION = RMS

NOISE LEVEL

1.5

Most ADCs detect input voltage levels, not power. Conse-

quently, the input SNR can be determined more accurately by

determining the ratio of the signal voltage to the noise voltage of

the terminating resistor. However, both the input signal and

noise voltage delivered to the ADC are also a function of the

source impedance. T he dependence of NF on sample rate,

linearity, source and terminating impedances, and the number

of assumptions required, highlight the weakness of using NF as

a figure of merit for an ADC. T he rather large number that

results bolsters this belief by indicating the ADC is often the

weakest link in the signal processing path.

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

Linear ity

x–3

x–2

x–1

x

x+1

x+2

x+3

OUTPUT CODE

T he T hird Order intercept point for a linear device (with some

nonlinearity) is a good way to predict 3rd order spurious signals

as a function of input signal level. For an ADC, however, this in

an invalid concept except with signals near full scale. As the

input signal is reduced, the performance burden shifts from the

input track-and-hold (T /H) to the encoder. T his creates a non-

linear function, as contrasted with the third order intercept

behavior, which predicts an improvement in dynamic range as

the signal level is decreased.

Figure 11. ADC Equivalent Input Noise

T he correct code appears most of the time, but adjacent codes

also appear with reduced probability. If a normal probability

density curve is fitted to this Gaussian distribution of codes, the

standard deviation will be equal to the equivalent input rms

noise of the ADC. T he rms noise may also be approximated by

converting the SNR, as measured by a low frequency FFT , to

an equivalent input noise. T his method is accurate only if the

SNR performance is dominated by random thermal noise (the

low frequency SNR without harmonics is the best measure).

Sixty-three dB equates to 1 LSB rms for a 2 V p-p (0.707 V

rms) input signal. T he AD9022 has approximately 0.5 LSB of

rms noise or a noise limited SNR of 69 dB, indicating that noise

alone does not limit the SNR performance of the device (quanti-

zation noise and linearity are also major contributors).

For signals near full scale, the intercept point is calculated the

same as any device:

Intercept Point = [Harmonic Suppression/(N –1)] + Input Power

where N = the order of the IMD (3 in this case)

AD9022 Intercept Point = 80/2 + 3 dBm (7 dBm below full scale)

= 43 dBm

For signals below this level, the spurious free dynamic range

(SFDR) curves shown in the data sheet are a more accurate

predictor of dynamic range. T he SFDR curve is generated by

measuring the ratio of the signal (either tone in the two-tone

measurement) to the worst spurious signal, which is observed as

the analog input signal amplitude is swept.

T his thermal noise may come from several sources. T he drive

source impedance should be kept low to minimize resistor

thermal noise. Some of the internal ADC noise is generated in

the wideband T /H. Sampling ADCs generally have input band-

widths which exceed the Nyquist frequency of one-half the

sampling rate. (T he AD9022 has an input bandwidth of over

100 MHz, even though the sampling rate is limited to 20 MSPS.)

T he worst spurious signal is usually the second harmonic or 3rd

order IMD. Actual results are shown on several plots. T he

straightline with a slope of one is constructed at the point where

the worst SFDR touches the line. T his line, extrapolated to full

scale, gives the SFDR of the ADC. T his value can then be used

to predict the dynamic range by simply subtracting the input

level from the SFDR.

Wide bandwidth is required to minimize gain and phase distor-

tion and to permit adequate settling times in the internal ampli-

fiers and T /Hs. But a certain amount of unavoidable noise is

generated in the T /H and other wideband circuits within the

ADC; this causes variation in output codes for dc inputs. Good

layout, grounding and decoupling techniques are essential to

prevent external noise from coupling into the ADC and further

corrupting performance.

It should be noted that all SFDR lines are constructed to be

valid only below a certain level below full scale. Above these

points, the linearity of the device is dominated by the nonlinearities

of the front end and best predicted by the intercept point.

–8–

REV. B

AD9022

USING TH E AD 9022

Layout Infor m ation

Preserving the accuracy and dynamic performance of the

AD9022 requires that designers pay special attention to the

layout of the printed circuit board.

T he duty cycle of the encode clock for the AD9022 is critical for

obtaining rated performance of the ADC. Internal pulsewidths

within the track-and-hold are established by the encode com-

mand pulsewidth; to ensure rated performance, minimum and

maximum pulsewidth restrictions should be observed. Operation at

20 MSPS is optimized when the duty cycle is held at 55%.

Analog paths should be kept as short as possible and be properly

terminated to avoid reflections. T he analog input connection

should be kept away from digital signal paths; this reduces the

amount of digital switching noise, which is capacitively coupled

into the analog section. Digital signal paths should also be kept

short, and run lengths should be matched to avoid propagation

delay mismatch. T he AD9022 digital outputs should be buff-

ered or latched close to the device (<2 cm). T his prevents load

transients that may feed back into the device.

Analog Input

T he analog input (Pin 12) voltage range is nominally ±1.024

volts. T he range is set with an internal voltage reference and

cannot be adjusted by the user. T he input resistance is 300 Ω

and the analog bandwidth is 110 MHz, making the AD9022

useful in undersampling applications.

T he AD9022 should be driven from a low impedance source.

T he noise and distortion of the amplifier should be considered

to preserve the dynamic range of the AD9022.

In high speed circuits, layout of the ground is critical. A single,

low impedance ground plane on the component side of the

board is recommended. Power supplies should be capacitively

coupled to the ground plane with high quality 0.1 µF chip ca-

pacitors to reduce noise in the circuit. All power pins of the

AD9022 should be bypassed individually. T he compensation

pin (COMP Pin 17) should be bypassed directly to the –V_S

supply (Pin 15) as close to the part as possible using a 0.1 µF

chip capacitor.

P ower Supplies

T he power supplies of the AD9022 should be isolated from the

supplies used for noisy devices (digital logic especially) to re-

duce the amount of noise coupled into the ADC. For optimum

performance, linear supplies ensure that switching noise from

the supplies does not introduce distortion products during

the encoding process. If switching supplies must be used,

decoupling recommendations above are critically important.

T he PSRR of the AD9022 is a function of the ripple frequency

present on the supplies. Clearly, power supplies with the lowest

possible frequency should be selected.

Multilayer boards allow designers to lay out signal traces with-

out interrupting the ground plane, and provide low impedance

ground planes. In systems with dedicated analog and digital

grounds, all grounds for the AD9022 should be connected to

the analog ground plane.

AD 9022 EVALUATIO N BO ARD

T he evaluation board for the AD9022 (AD9022/PCB) provides

an easy and flexible method for evaluating the ADC’s perfor-

mance without (or prior to) developing a user-specific printed

circuit board. T he two-sided board includes a reconstruction

DAC and digital output interface, and uses the layout and appli-

cations suggestions outlined above. It is available at nominal

cost from Analog Devices, Inc.

In systems using multilayer boards, dedicated power planes are

recommended to provide low impedance connections for device

power. Sockets limit dynamic performance and are not recom-

mended for use with the AD9022.

Tim ing

Conversion by the AD9022 is initiated by the rising edge of the

ENCODE clock (Pin 8). All required timing is generated inter-

nal to the ADC. Care should be taken to ensure that the encode

clock to the AD9022 is free from jitter that can degrade dy-

namic performance. T he clock driver should be compatible with

T T L LS logic series devices. Drivers with excessive slew rate or

overdrive will degrade the dynamic performance of the AD9022.

Input/O utput/Supply Infor m ation

Power supply, analog input, clock connections and recon-

structed output (RC OUT PUT ) are identified by labels on the

evaluation board.

Operation of the evaluation board will conform to the following

characteristics:

Pulsewidth of the ADC encode clock must be controlled to

ensure the best possible performance. Dynamic performance is

guaranteed with a clock pulse HIGH minimum of 25 ns. Opera-

tion with narrower pulses will degrade SNR and dynamic per-

formance. From a system perspective, this is generally not a

problem, because a simple inverter can be used to generate a

suitable clock if the system clock is less than 25 ns wide.

P aram eter

Typical

Units

Supply Current

+5 V

–5 V

150

300

mA

A_IN

T he AD9022 provides latched data outputs. Data outputs are

available two pipeline delays and one propagation delay after the

rising edge of the encode clock (refer to the AD9022 T iming

Diagram). T he length of the output data lines and the loads

placed on them should be minimized to reduce transients within

the AD9022; these transients can detract from the converter’s

dynamic performance.

Impedance

Voltage Range

CLOCK

Impedance

Frequency

RC OUT PUT

Impedance

Voltage Range

51

±1.024

Ω

V

51

20

Ω

MSPS

51

0 to –1

Ω

V

Operation at encode rates less than 4 MSPS is not recom-

mended. T he internal track-and-hold saturates, causing errone-

ous conversions. T his T /H saturation precludes clocking the

AD9022 in a burst mode.

–9–

REV. B

AD9022

Analog Input

signal. T he AD9713B is terminated into 51 Ω to provide a

Analog input signals can be directly fed into the device under

test input (A_IN). T he A_INinput is terminated at the device with

a 62 Ω resistor to give a parallel equivalent of 51 Ω (62 Ωʈ300 Ω).

1 V p-p signal at the output (RC Output).

O utput D ata

T he output data bits are latched with two 74LS574 latches

which drive a 40-pin connector (AMP p/n 102153-09). T he

data and clock signals are available at the connector per the pin

assignments shown on the schematic of the evaluation board.

Data is latched on the rising edge of the encode clock.

D AC Reconstr uction

T he AD9022 evaluation board provides an onboard AD9713B

reconstruction DAC for observing the digitized analog input

U3

74LS574

U2

BNC

J1

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

AD9698R

5

1D

2D

3D

4D

5D

6D

7D

8D

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

11

CLOCK

R1

51⍀

6

CLK

12

9

D12

R8

U5

AD9713P

R9

E2 E1

D11

R10

R11

2

3

R4

D12 (LSB)

7.5k⍀

D10

CK

OE

24

20

19

18

17

D11

RSET

D9

D8

4

11

1

D10 REFOUT

5

R3

20⍀

U2

D9

D8

D7

D6

D5

D4

D3

D2

CIN

6

AD9698R

4

R12

R14

R15

R16

R17

R18

R19

R20

+5V

U4

74LS574

COUT

U1

AD9022Q

14

7

D7

D6

D5

D4

D3

D2

REFIN

R2

5.1k⍀

8

C5

0.1␮F

25

24

23

22

21

20

19

18

17

3

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

D9

D8

D7

9

1D

2D

3D

4D

5D

6D

7D

8D

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

13

16

D10

–5.2V

10

11

14

28

26

16

14

IOUT

D11

D6

C1

0.1␮F

R5

51⍀

D12 LSB

D5

IOUT

1

2

D4

CR1

D1 (MSB)

LE

D3

9

R21

100⍀

AD589H

BNC

J4

8

ENCODE

10

D2

12

RC

OUT

AIN

MSB D1

COMP

D1

BNC

J2

U6

74AS32

CK

R6

51⍀

OE

A

11

IN

1

R7

62⍀

C4

0.1␮F

–5.2V

H40DMC

J3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

U6

74AS32

CLK

1

3

+5V

D1

D2

D3

D4

D5

D6

D7

D8

2

C2

J5

J6

J7

C11

0.1␮F

C22

0.1␮F

C6

0.1␮F

C8

C9

C10

0.1␮F

C12

0.1␮F 0.1␮F

C13

10␮F

C7

0.1␮F

–5.2V

+5V

0.1␮F 0.1␮F

U6

74AS32

20%

35V

4

6

5

GND

–5.2V

U6

74AS32

12

13

C3

C14

0.1␮F

C15

C16

C17

C18

C19

C20

C21

10␮F

0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F

20%

35V

11

D9

D10

D11

D12

Figure 12. AD9022/PCB Evaluation Board Schem atic

–10–

REV. B

AD9022

Figure 13. Top of Board, Viewed From Top

Figure 14. Center of Board, Viewed From Top

–11–

REV. B

AD9022

Figure 15. Bottom of Board, Viewed from Bottom

O UTLINE D IMENSIO NS

Dimensions shown in inches and (mm).

28-Lead Cer dip

(Q -28)

28-P in Cer am ic Leaded Chip Car r ier

(Z-28)

0.005 (0.13) MIN

28

0.165 (4.191)

MAX

0.100 (2.54) MAX

15

0.73 (18.544)

0.71 (18.036)

0.012 (0.305)

0.009 (0.229)

0.610 (15.49)

0.500 (12.70)

28

15

1

14

0.025

(0.635)

MIN

0.620 (15.75)

0.590 (14.99)

PIN 1

0.015

(0.38)

MIN

1.490 (37.85) MAX

0.225

(5.72)

MAX

0.51 (12.954)

0.49 (12.446)

0.765 (19.431)

0.745 (18.923)

TOP VIEW

0.150

(3.81)

MIN

0.018 (0.46)

0.008 (0.20)

0.200 (5.08)

0.125 (3.18)

SEATING

PLANE

0.026 (0.66) 0.110 (2.79)

0.014 (0.36) 0.090 (2.29)

0.070 (1.78)

0.030 (0.76)

0.060 (1.524)

0.040 (1.016)

15

0

1

14

0.115 (2.921)

MAX

0.050 (1.27)

TYP

0.015 (0.381)

MIN

–12–

REV. B


型号：	AD9022AQ
厂家：	ADI
描述：	12-Bit 20 MSPS Monolithic A/D Converter 12位20 MSPS单片A / D转换器转换器
文件：	总12页 (文件大小：244K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9022AQ [ADI]

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