AD9023AZ [ADI]

IC 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDSO28, CERAMIC, LCC-28, Analog to Digital Converter;


型号：	AD9023AZ
厂家：	ADI
描述：	IC 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDSO28, CERAMIC, LCC-28, Analog to Digital Converter CD 转换器
文件：	总8页 (文件大小：363K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

12-Bit 20 MSPS

Monolithic A/D Converter

AD9023

FEATURES

Monolithic

FUNCTIONAL BLOCK DIAGRAM

12-Bit 20 MSPS A/D Converter

Low Power Dissipation: 1.5 Watts

On-Chip T/H and Reference

High Spurious-Free Dynamic Range

ECL Logic

5-BIT

ADC

ANALOG

INPUT

T/H

DIGITAL

ERROR

CORRECTION

ECL

5-BIT

ADC

DAC

APPLICATIONS

ENCODE

Radar Receivers

Digital Communications

Digital Instrumentation

Electro-Optic

T/H

DAC

+5V

+2V

REF

4-BIT

ADC

–5.2V

GND

Medical Imaging

Digital Filters

PRODUCT DESCRIPTION

With DNL typically less than 0.5 LSB and 20 ns transient re-

sponse settling time, the AD9023 provides excellent results

when low frequency analog inputs must be over-sampled (such

as CCD digitization). The full-scale analog input is ±1 V with a

300 Ω input impedance. The analog input can be driven directly

from the signal source, or can be buffered by the AD96xx series

of low noise, low distortion buffer amplifiers.

The AD9023 is a high speed, high performance, monolithic 12-

bit analog-to-digital converter. All necessary functions, includ-

ing track-and-hold (T/H) and reference, are included on chip to

provide a complete conversion solution. It is a companion unit

to the AD9022; the primary difference between the two is that

all logic for the AD9022 is TTL compatible, while the AD9023

utilizes ECL logic for digital inputs and outputs. Pinouts for the

two parts are nearly identical.

All timing is internal to the AD9023; the clock signal initiates

the conversion cycle. For best results, the encode command

should contain as little jitter as possible. High speed layout prac-

tices must be followed to ensure optimum A/D performance.

Operating from +5 V and –5.2 V supplies, the AD9023 provides

excellent dynamic performance. Sampling at 20 Msps with

A_IN= 1 MHz, the spurious-free dynamic range (SFDR) is typi-

cally 74 dB; with A_IN= 9.6 MHz, SFDR is 72 dB. SNR is typi-

cally 65 dB.

The AD9023 is built on a trench isolated bipolar process and

utilizes an innovative multipass architecture (see the block dia-

gram). The unit is packaged in 28-pin ceramic DIPs and

gullwing surface mount packages. The AD9023 is specified to

operate over the industrial (–25°C to +85°C) and extended

(–55°C to +125°C) temperature ranges.

The on-board T/H has a 110 MHz bandwidth and, more impor-

tantly, is designed to provide excellent dynamic performance for

analog input frequencies above Nyquist. This feature is neces-

sary in many undersampling signal processing applications, such

as in direct IF-to-digital conversion.

To maintain dynamic performance at higher IFs, monolithic RF

track-and-holds (such as the AD9100 and AD9101Samplifier™)

can be used with the AD9023 to process signals up to and

beyond 70 MHz.

Samplifier is a trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

AD9023–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS ^(+V_S^{= +5 V; –V}_S^{= –5.2 V; Encode = 20 MSPS, unless otherwise noted)}

Test

AD9023AQ/AZ

AD9023BQ/BZ

AD9023SQ/SZ

Parameter (Conditions)

Temp

Level

Min Typ Max Min Typ Max

Min Typ Max

Units

RESOLUTION

12 12

Bits

DC ACCURACY

Differential Nonlinearity

+25°C

Full

+25°C

Full

+25°C

Full

+25°C

Full

+25°C

0.6 0.75

1.0

1.2 2.5

1.6 3.0

0.4 0.5

1.0

1.2 2.0

1.6 3.0

0.6 0.75

1.0

1.2 2.5

1.6 3.0

Guaranteed

LSB

Integral Nonlinearity

No Missing Codes

Offset Error

Guaranteed

% FS

LSB, rms

Gain Error

0.5 2.5

0.6 3.5

0.57

0.5 2.5

0.6 3.5

0.57

0.5 2.5

0.6 3.5

0.57

Thermal Noise

ANALOG INPUT

Input Voltage Range

Input Resistance

Input Capacitance

Analog Bandwidth

±1.024

240 300 360

±1.024

240 300 360

±1.024

240 300 360

Ω

MHz

Full

+25°C

110

SWITCHING PERFORMANCE¹

Minimum Conversion Rate

Maximum Conversion Rate

Aperture Delay (t_A)

+25°C

Full

+25°C

Full

Msps

ps, rms

0.50 0.78 1.05 0.50 0.78 1.05

0.50 0.78 1.05

Aperture Uncertainty (Jitter)

Output Delay (t_OD

)

8.5

19.5 8.5

19.5

8.5

19.5

ENCODE INPUT

Logic Compatibility

Logic “1” Voltage

Logic “0” Voltage

Logic “1” Current

Logic “0” Current

Input Capacitance

Pulse Width (High)

Pulse Width (Low)

ECL

Full

+25°C

–1.1

–1.5

µA

22.5

125

22.5

125

22.5

125

DYNAMIC PERFORMANCE

Transient Response

Overvoltage Recovery Time

Harmonic Distortion²

Analog Input @ 1.2 MHz

@ 1.2 MHz

+25°C

Full

+25°C

Full

dBc

@ 4.3 MHz

@ 9.6 MHz

Signal-to-Noise Ratio²

Analog Input @ 1.2 MHz

@ 1.2 MHz

+25°C

Full

+25°C

Full

@ 4.3 MHz

@ 9.6 MHz

Signal-to-Noise Ratio²

(Without Harmonics)

Analog Input @ 1.2 MHz

@ 1.2 MHz

+25°C

Full

+25°C

Full

@ 4.3 MHz

@ 9.6 MHz

REV. A

–2–

AD9023

Test

AD9023AQ/AZ

AD9023BQ/BZ

AD9023SQ/SZ

Parameter (Conditions)

Temp

Level

Min Typ Max Min Typ Max

Min Typ Max

Units

Two-Tone Intermodulation

Distortion Rejection³

+25°C

dBc

DIGITAL OUTPUTS¹

Logic Compatibility

Logic “1” Voltage

Logic “0” Voltage

Output Coding

ECL

–1.1

Full

–1.1

–1.5

Offset Binary

POWER SUPPLY

+V_SSupply Voltage

+V_SSupply Current

–V_SSupply Voltage

–V_SSupply Current

Power Dissipation

Power Supply Rejection

Ratio (PSRR)⁴

Full

4.75 5.0 5.25

100 120

–5.45 –5.2 –4.95 –5.45 –5.2 –4.95 –5.45 –5.2 –4.95 mA

4.75 5.0 5.25

100 120

4.75 5.0 5.25

100 120

195 240

1.5 2.0

195 240

1.5 2.0

195 240

1.5 2.0

Full

mV/V

NOTES

¹AD9023 load is 100 Ω to –2.0 V.

²RMS signal-to-rms noise with analog input signal 1 dB below full scale at specified frequency.

³Intermodulation measured with analog input frequencies of 8.9 MHz and 9.8 MHz at 7 dB below full scale.

⁴PSRR is sensitivity of offset error to power supply variations within the 5% limits shown.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS¹

+V_S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V

–V_S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V

Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–V_Sto +V_S

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V_Sto 0 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature Range

AD9023AQ/AZ/BQ/BZ . . . . . . . . . . . . . . . –25°C to +85°C

AD9023SQ/SZ . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Maximum Junction Temperature^{2 . . . . . . . . . . . . . . . . . . . . . . . .}+175°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

NOTES

¹Absolute maximum ratings are limiting values to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional

operability is not necessarily implied. Exposure to absolute maximum rating

conditions for an extended period of time may affect device reliability.

²Typical thermal impedances: “Q” Package (Ceramic DIP): θ_JC= 10°C/W; θ_JA

35°C/W. “Z” Package (Gullwing Surface Mount): θ_JC= 13°C/W; θ_JA= 45°C/W.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD9023 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom-

mended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–3–

REV. A

AD9023

ANALOG

t_a

N + 1

t_a= 0.8 TYPICAL

N + 2

t_OD

ENCODE

t_OD= 8.5–19.5ns TYPICAL

DATA

OUTPUT

N – 3

N – 2

N – 1

Timing Diagram

ORDERING GUIDE

DIE LAYOUT AND MECHANICAL INFORMATION

Die Dimensions . . . . . . . . . . . . . . . . 205 × 228 × 21 (±1) mils

Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils

Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum

Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None

Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V_S

Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4,128

Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride

Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum

Temperature

Range

Package

Description

Package

Option

Model

AD9023AQ/BQ –25°C to +85°C 28-Pin Ceramic DIP Q-28

AD9023AZ/BZ –25°C to +85°C 28-Pin Ceramic

Z-28

Leaded Chip Carrier

AD9023SQ

AD9023SZ

–55°C to +125°C 28-Pin Ceramic DIP Q-28

–55°C to +125°C 28-Pin Ceramic

Z-28

Leaded Chip Carrier

EXPLANATION OF TEST LEVELS

Test Level

GND

D11 (MSB)

– 100% production tested.

II – 100% production tested at +25°C, and sample tested at

D10

GND

specified temperatures. AC testing done on sample basis.

III – Sample tested only.

ENCODE

IV – Parameter is guaranteed by design and characterization

testing.

V – Parameter is a typical value only.

VI – All devices are 100% production tested at +25°C; guaranteed

by design and characterization testing at temperature

extremes for industrial devices.

GND

ENCODE

D0 (LSB)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD9023 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom-

mended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. A

AD9023

PIN DESIGNATIONS

PIN DESCRIPTION

Function

Pin No.

Name

28 GND

27 –V_S

26 +V_S

25 D4

24 D5

23 D6

22 D7

21 D8

20 D9

19 D10

1–3

D3–D1

Digital output bits of ADC; ECL

compatible.

D0 (LSB)

Least significant bit of ADC output;

ECL compatible.

D0 (LSB)

ENCODE

Complementary encode input to ADC.

AD9023

TOP VIEW

(Not to Scale)

GND

ENCODE

GND

No Connect

Ground

GND

ENCODE

Encode clock input to ADC. Internal

T/H is placed in hold mode (ADC is

encoding) on rising edge of encode

signal.

+V_S10

GND 11

A_IN12

–V_S13

+V_S14

18 D11 (MSB)

17 COMP

16 GND

GND

+V_S

Ground

15 –V_S

+5 V Power Supply

Ground

GND

A_IN

NC = NO CONNECT

COMPENSATION (PIN 17) SHOULD BE

Noninverting input to T/H amplifier.

–5.2 V Power Supply

+5 V Power Supply

–5.2 V Power Supply

Ground

CONNECTED TO –V_STHROUGH 0.1µF

–V_S

+V_S

–V_S

GND

COMP

Should be connected to –V_Sthrough

0.1 µF capacitor.

D11 (MSB) Most significant bit of ADC output;

ECL compatible.

19–25

D10–D4

Digital output bits of ADC; ECL

compatible.

+V_S

+5 V Power Supply

–5.2 V Power Supply

Ground

–V_S

GND

+V_S

COMPENSATION

+V_S

1200

3400

ENCODE

180

–V_S

ANALOG

INPUT

D0 – D11

10 pF

120

20pF

–V_S

Compensation

Figure 1. Equivalent Circuits

Output Stage

Encode Input

Analog Input

REV. A

–5–

AD9023

Typical Characteristics

+2.0

+1.5

+1.0

+0.5

–73

= 1.2MHz

= 20MSPS

–72

+25° C

WORST HARMONICS

–71

–70

–55° C

–69

SNR

+125° C

–68

–67

–66

–65

–0.5

–1.0

–1.5

–2.0

17.5 20 22.5 25

7.5 10 12.5 15

ENCODE RATE – MSPS

1024

2048

OUTPUT CODE

3072

4096

ANALOG INPUT FREQUENCY – MHz

Figure 3. SNR and Harmonics vs. En-

code Rate

Figure 2. Harmonic Distortion vs.

Analog Input Frequency

Figure 4. Differential Nonlinearity vs.

Output Code

= 9.6MHz

= 1.2MHz

ENCODE = 20MHz

SFDR

SNR

+25° C

ENCODE = 20MHz

SFDR

SNR

–55° C

+125° C

1.24

4.3 6.3 8.3 10.3 12.3 14.3 16.3 18.3 20.3

ANALOG INPUT FREQUENCY – MHz

–50 –45 –40 –35 –30 –25 –20 –15 –10 –5 –1

INPUT LEVEL – dB

Figure 5. Signal-to-Noise Ratio vs.

Analog Input Frequency

Figure 6. SFDR and SNR vs. Input

Level

Figure 7. SFDR and SNR vs. Analog

Input Level

1 = 8.9MHz

2 = 9.8MHz

1 = –7.0dBFS

2 = –7.0dBFS

= 9.6MHz

= –1.0dBFS

= 1.2MHz

= –1.0dBFS

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–10

–20

–30

–40

–50

–60

–70

–80

SNR = 65.89dB

THD = 70.16dB

SFDR = 70.94dBFS

SNR = 66.12dB

THD = 73.96dB

SFDR = 76.99dBFS

SFDR = 81.10dBFS

100

–90

120

0.0

–100

0.0

2.0

4.0

6.0

8.0

2.0

4.0

6.0

8.0

10.0

FREQUENCY – MHz

Figure 9. FFT Plot

Figure 10. Two Tone FFT

Figure 8. FFT Plot

–6–

REV. A

AD9023

THEORY OF OPERATION

The correct code appears most of the time, but adjacent codes

also appear with reduced probability. If a normal probability

density curve is fitted to this Gaussian distribution of codes, the

standard deviation will be equal to the equivalent input rms

noise of the ADC. The rms noise may also be approximated by

converting the SNR, as measured by a low frequency FFT, to

an equivalent input noise. This method is accurate only if the

SNR performance is dominated by random thermal noise (the

low frequency SNR without harmonics is the best measure).

Sixty-three dB equates to 1 LSB rms for a 2 V p-p (0.707 V rms)

input signal. The AD9023 has approximately 0.5 LSB of rms

noise or a noise limited SNR of 69 dB, indicating that noise

alone does not limit the SNR performance of the device (quanti-

zation noise and linearity are also major contributors).

Refer to the block diagram. The AD9023 employs a three pass

subranging architecture and digital error correction. This com-

bination of design techniques insures 12-bit accuracy at rela-

tively low power.

Analog input signals are immediately attenuated through a resis-

tor divider and applied directly to the sampling bridge of the

track-and-hold (T/H). The T/H holds whatever analog value is

present when the unit is strobed with an ENCODE command.

The conversion process begins on the rising edge of this pulse,

which should conform to the minimum and maximum pulse

width requirements shown in the specifications. Operation be-

low the recommended encode rate (4 Msps) may result in ex-

cessive droop in the internal T/H devices–leading to large dc

and ac errors.

This thermal noise may come from several sources. The drive

source impedance should be kept low to minimize resistor ther-

mal noise. Some of the internal ADC noise is generated in the

wideband T/H. Sampling ADCs generally have input band-

widths which exceed the Nyquist frequency of one-half the

sampling rate. (The AD9023 has an input bandwidth of over

100 MHz, even though the sampling rate is limited to 20 Msps.)

The held analog value of the first track-and-hold is applied to a

5-bit flash converter and a second T/H. The 5-bit flash con-

verter resolves the most significant bits (MSBs) of the held ana-

log voltage. These 5 bits are reconstructed via a 5-bit DAC and

subtracted from the original T/H output signal to form a residue

signal.

A second T/H holds the amplified residue signal while it is en-

coded with a second 5-bit flash ADC. Again the 5 bits are re-

constructed and subtracted from the second T/H output to form

a residue signal. This residue is amplified and encoded with a 4-

bit flash ADC to provide the 3 least significant bits (LSBs) of

the digital output and one bit of error correction.

USING THE AD9023

Layout Information

Preserving the accuracy and dynamic performance of the

AD9023 requires that designers pay special attention to the lay-

out of the printed circuit board.

Analog paths should be kept as short as possible and be properly

terminated to avoid reflections. The analog input connection

should be kept away from digital signals paths; this reduces the

amount of digital switching noise which is capacitively coupled

into the analog section. Digital signal paths should also be kept

short, and run lengths should be matched to avoid propagation

delay mismatch. The AD9023 digital outputs should be buff-

ered or latched close to the device (< 2 cm). This prevents load

transients which may feed back into the device.

Digital Error Correction logic aligns the data from the three

flash converters and presents the result as a 12-bit parallel digi-

tal word. The output stage of the AD9023 is ECL. Output data

may be strobed on the rising edge of the ENCODE command.

AD9023 Noise Performance

High speed, wide bandwidth ADCs such as the AD9023 are op-

timized for dynamic performance over a wide range of analog

input frequencies. However, there are many applications (Imag-

ing, Instrumentation, etc.) where dc precision is also important.

Due to the wide input bandwidth of the AD9023 for a given in-

put voltage, there will be a range of output codes which may oc-

cur. This is caused by unavoidable circuit noise within the

wideband circuits in the ADC. If a dc signal is applied to the

ADC and several thousand outputs are recorded, a distribution

of codes such as that shown in the histogram below may result.

In high speed circuits, layout of the ground is critical. A single,

low impedance ground plane on the component side of the

board is recommended. Power supplies should be capacitively

coupled to the ground plane with high quality 0.1 µF chip ca-

pacitors to reduce noise in the circuit. All power pins of the

AD9023 should be bypassed individually. The compensation

pin (COMP Pin 17) should be bypassed directly to the –V_Ssup-

ply (Pin 15) as close to the part as possible using a 0.1 µF chip

capacitor.

ONE STANDARD

DEVIATION = RMS

NOISE LEVEL

Multilayer boards allow designers to lay out signal traces with-

out interrupting the ground plane, and provide low impedance

ground planes. In systems with dedicated analog and digital

grounds, all grounds for the AD9023 should be connected to

the analog ground plane.

In systems using multilayer boards, dedicated power planes are

recommended to provide low impedance connections for device

power. Sockets limit dynamic performance and are not recom-

mended for use with the AD9023.

Timing

Conversion by the AD9023 is initiated by the rising edge of the

ENCODE clock (Pin 8). All required timing is generated inter-

nal to the ADC. Care should be taken to ensure that the encode

clock to the AD9023 is free from jitter that can degrade dy-

namic performance.

X–3

x–2

x–1

x+1

x+2

x+3

OUTPUT CODE

Figure 11. Equivalent Input Noise

REV. A

–7–

AD9023

Pulse width of the ADC encode clock must be controlled to en-

sure the best possible performance. Dynamic performance is

guaranteed with a clock pulse HIGH minimum of 25 ns. Opera-

tion with narrower pulses will degrade SNR and dynamic per-

formance. From a system perspective, this is generally not a

problem because a simple inverter can be used to generate a

suitable clock if the system clock is less than 25 ns wide.

Power Supplies

The power supplies of the AD9023 should be isolated from the

supplies used for noisy devices (digital logic especially) to re-

duce the amount of noise coupled into the ADC. For optimum

performance, linear supplies ensure that switching noise from

the supplies does not introduce distortion products during the

encoding process. If switching supplies must be used, decoupling

recommendations above are critically important. The PSRR of

the AD9023 is a function of the ripple frequency present on the

supplies. Clearly, power supplies with the lowest possible fre-

quency should be selected.

The AD9023 provides latched data outputs. Data outputs are

available two pipeline delays and one propagation delay after the

rising edge of the encode clock (refer to the AD9023 Timing

Diagram). The length of the output data lines and the loads

placed on them should be minimized to reduce transients within

the AD9023; these transients can detract from the converter’s

dynamic performance. Operation at encode rates less than

4 Msps is not recommended. The internal track-and-hold satu-

rates, causing erroneous conversions. This T/H saturation pre-

cludes clocking the AD9023 in a burst mode.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Q-28 (Ceramic DIP)

The duty cycle of the encode clock for the AD9023 is critical for

obtaining rated performance of the ADC. Internal pulse widths

within the track-and-hold are established by the encode com-

mand pulse width; to ensure rated performance, minimum and

maximum pulse width restrictions should be observed. Opera-

tion at 20 Msps is optimized when the duty cycle is held at 55%.

0.610 (15.49)

0.500 (12.70)

0.015

(0.38)

MIN

0.620 (15.75)

0.590 (14.99)

1.490 (37.85) MAX

0.225

(5.72)

MAX

Analog Input

The analog input (Pin 12) voltage range is nominally ±1.024

volts. The range is set with an internal voltage reference and

cannot be adjusted by the user. The input resistance is 300 Ω

and the analog bandwidth is 110 MHz, making the AD9023

useful in undersampling applications.

0.150

(3.81)

MIN

0.018 (0.457)

0.008 (0.203)

0.110 (2.79)

0.090 (2.29)

0.07 (1.78)

0.03 (0.76)

0.026 (0.660)

0.014 (0.356)

Z-28 (Ceramic Leaded Chip Carrier)

The AD9023 should be driven from a low impedance source.

The noise and distortion of the amplifier should be considered

to preserve the dynamic range of the AD9023.

0.115

0.73 (18.544)

(2.921)

MAX

0.012 (0.305)

0.009 (0.229)

0.71 (18.036)

10176

AD9023

0.025

(0.635)

MIN

0.51 (12.954)

0.49 (12.446)

TOP VIEW

0.765 (19.431)

0.745 (18.923)

Ω62Ω

Ω(510Ω ON EACH

DATA BIT)

–5.2V

0.060 (1.524)

0.040 (1.016)

0.165

(4.191)

MAX

10176

0.050

(1.27)

TYP

0.015

(0.381)

MIN

ENCODE

Ω(510Ω ON EACH

DATA BIT)

0.1µF

–5.2V

Figure 12. AD9023 Evaluation Board

–8–

REV. A

AD9023AZ [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E