AD9048TQ-883B [ADI]
Monolithic 8-Bit Video A/D Converter; 单片8位视频A / D转换器
| 型号： | AD9048TQ-883B |
| 厂家： | 
ADI |
| 描述： | Monolithic 8-Bit Video A/D Converter |
| 文件： | 总8页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Monolithic 8-Bit
Video A/D Converter
a
AD9048
FUNCTIONAL BLOCK DIAGRAM
FEATURES
35 MSPS Encode Rate
12
28
23
18
NLINV
NMINV
16 pF Input Capacitance
550 mW Power Dissipation
Industry-Standard Pinouts
MIL-STD-883 Compliant Versions Available
AD9048
V
IN
1
2
R
T
R
R
1
2
D1 (MSB)
APPLICATIONS
E
N
C
O
D
I
D2
D3
D3
D5
Professional Video Systems
Special Effects Generators
Electro-Optics
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
3
127
128
L
A
T
C
H
4
R/2
R/2
N
G
27
R
13
M
L
O
G
I
14 D6
15
16
D7
R
R
C
D8 (LSB)
254
255
GENERAL DESCRIPTION
26
17
R
B
The AD9048 is an 8-bit, 35 MSPS flash converter, made on
a high speed bipolar process, which is an alternate source for
the TDC1048 unit, and offers enhancements over its
predecessor. Lower power dissipation makes the AD9048
attractive for a variety of system designs.
CONVERT
5
11
19 25
6
10
7
8
9
V
V
EE
DGND AGND
CC
Because of its wide bandwidth, it is an ideal choice for real-time
conversion of video signals. Input bandwidth is flat with no
missing codes.
Clocked latching comparators, encoding logic, and output
buffer registers operating at minimum rates of 35 MSPS pre-
clude a need for a sample-and-hold (S/H) or track-and-hold
(T/H) in most system designs using the AD9048. All digital
control inputs and outputs are TTL compatible.
Commercial versions are packaged in 28-lead DIPs; extended
temperature versions are available in ceramic DIP and ceramic
LCC packages. Both commercial units and MIL-STD-883 units
are standard products.
Devices operating over two ambient temperature ranges and
with two grades of linearity are available. Linearities of either
0.5 LSB or 0.75 LSB can be ordered for a commercial range of
0°C to 70°C or extended case temperatures of –55°C to +125°C.
The AD9048 A/D converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military Prod-
ucts Databook or current AD9048/883B data sheet for detailed
specifications.
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(typical with nominal supplies, unless otherwise noted.)
AD9048–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . 1.0 sec5
Operating Temperature Range (Ambient)
VCC to DGND . . . . . . . . . . . . . . . . . –0.5 V DC to +7.0 V DC
AGND to DGND . . . . . . . . . . . . . . –0.5 V DC to +0.5 V DC
VEE to AGND . . . . . . . . . . . . . . . . . +0.5 V DC to –7.0 V DC
VIN, VRT, or VRB to AGND . . . . . . . . . . . . . . . . . 0.5 V to VEE
VRT to VRB . . . . . . . . . . . . . . . . . . . . –2.2 V DC to +2.2 V DC
CONV, NMINV or NLINV to DGND–0.5 V DC to +5.5 V DC
Applied Output Voltage to DGND –0.5 V DC to +5.5 V DC2
Applied Output Current, Externally Forced
AD9048JJ/KJ/JQ/KQ . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
AD9048SE/SQ/TE/TQ . . . . . . . . . . . . . . –55°C to +125°C
Maximum Junction Temperature (Plastic) . . . . . . . . . 150°C6
Maximum Junction Temperature (Hermetic) . . . . . . . 150°C6
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 mA to +6.0 mA3, 4
(V = +5.0 V; V = –5.2 V; Differential Reference Voltage = 2.0 V, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
CC
EE
Test
AD9048JJ/JQ
AD9048KJ/KQ
Min Typ Max
AD9048SE/SQ
Min Typ Max
AD9048TE/TQ
Min Typ Max
Parameter (Conditions)
Temp
Level Min Typ Max
Unit
RESOLUTION
8
8
8
8
Bits
DC ACCURACY
Differential Nonlinearity
25°C
Full
25°C
Full
I
VI
I
VI
VI
0.4
0.6
0.75
1.0
0.75
1.0
0.3 0.5
0.75
0.4 0.5
0.75
0.4
0.6
0.75
1.0
0.75
1.0
0.3 0.5
0.75
0.4 0.5
0.75
LSB
LSB
LSB
LSB
Integral Nonlinearity
No Missing Codes
Full
Guaranteed
Guaranteed
Guaranteed
Guaranteed
INITIAL OFFSET ERROR
Top of Reference Ladder
25°C
Full
25°C
Full
I
VI
I
VI
V
5
12
12
8
5
12
12
8
5
12
12
8
5
12
12
8
mV
mV
mV
mV
Bottom of Reference Ladder
Offset Drift Coefficient
4
4
4
4
8
8
8
8
Full
20
20
20
20
µV/°C
ANALOG INPUT
Input Voltage Range
Full
V
–2.1;
+0.1
36
–2.1;
+0.1
36
–2.1;
+0.1
36
–2.1;
+0.1
36
V
Input Bias Current7
Input Resistance
25°C
Full
25°C
Full
25°C
25°C
I
VI
I
VI
IV
IV
60
100
60
100
60
100
60
100
µA
µA
kΩ
kΩ
pF
MHz
200
40
300
200 300
200
40
300
200 300
40
16
40
Input Capacitance
16
15
20
16
15
20
16
15
20
20
Full Power Bandwidth8
10
10
10
10
15
REFERENCE INPUT
Positive Reference Voltage9
Negative Reference Voltage9
Differential Reference Voltage
Reference Ladder Resistance
Ladder Temperature Coefficient
Reference Ladder Current
Reference Input Bandwidth
Full
Full
Full
Full
Full
Full
25°C
V
V
V
VI
V
VI
V
0.0
–2.0
2.0
60
0.22
23
0.0
–2.0
2.0
60
0.22
23
0.0
–2.0
2.0
60
0.22
23
0.0
–2.0
2.0
60
0.22
23
V
V
V
Ω
Ω/°C
mA
MHz
30
125
40
30
125
40
30
125
40
30
125
40
10
10
10
10
DYNAMIC PERFORMANCE10
Conversion Rate
Aperture Delay
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
I
35
5
38
2.4
25
13
8
6
8
35
5
38
2.4
25
9
8
6
35
5
38
2.4
25
9
8
6
35
5
38
2.4
25
9
8
6
MHz
ns
ps
ns
ns
ns
ns
ns
ns
IV
IV
I
5
50
15
5
50
15
5
50
15
5
50
15
Aperture Uncertainty (Jitter)
Output Delay (tPD
)
11
Output Hold Time (tOH
)
I
Transient Response12
IV
V
I
I
I
20
20
20
20
Overvoltage Recovery Time13
Rise Time
8
8
8
9
14
7
9
14
7
9
14
7
9
14
7
Fall Time
Output Time Skew14
4.5
4.5
4.5
4.5
ns
NMINV and NLINV INPUTS
0.4 V Input Current
2.4 V Input Current
Full
Full
Full
VI
VI
VI
200
150
150
200
150
150
200
150
150
200
150
150
µA
µA
µA
5.5 V Input Current
CONVERT INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Convert Pulsewidth (LOW)
Convert Pulsewidth (HIGH)
Full
Full
Full
Full
25°C
25°C
25°C
VI
VI
VI
VI
IV
I
2.0
2.0
2.0
2.0
V
V
µA
µA
pF
ns
ns
0.8
150
500
6
0.8
150
500
6
0.8
150
500
6
0.8
150
500
6
4
4
4
4
18
10
18
10
18
10
18
10
I
–2–
REV. F
AD9048
Test
AD9048JJ/JQ
AD9048KJ/KQ
AD9048SE/SQ
Min Typ Max
AD9048TE/TQ
Min Typ Max
Parameter (Conditions)
Temp
Level Min Typ Max Min Typ Max
Unit
AC LINEARITY
In-Band Harmonics
DC to 2.438 MHz15
25°C
25°C
I
V
47
50
48
49
55
48
47
50
48
49
55
48
dBc
dBc
DC to 9.35 MHz16
Signal-to-Noise Ratio (SNR)15
1.248 MHz Input Frequency17
2.438 MHz Input Frequency17
1.248 MHz Input Frequency18
2.438 MHz Input Frequency18
Signal-to-Noise Ratio (SNR)16
1.248 MHz Input Frequency17
9.35 MHz Input Frequency17
Noise Power Ratio (NPR)19
Differential Phase 20
25°C
25°C
25°C
25°C
I
I
I
I
43.5 44
43 44
52.5 53
52 53
45
44
54
53
46
46
55
55
43.5 44
43 44
52.5 53
52 53
45
44
54
53
46
46
55
55
dB
dB
dB
dB
25°C
25°C
25°C
25°C
25°C
I
V
IV
IV
IV
43.5 44
40.5
36.5 39
45
46
40.5
43.5 44
40.5
36.5 39
45
46
40.5
dB
dB
dB
Degree
%
36.5 39
36.5 39
1
2
1
2
1
2
1
2
Differential Gain 20
DIGITAL OUTPUTS
Logic “1” Voltage
Full
Full
Full
VI
VI
VI
2.4
2.4
2.4
2.4
V
V
mA
Logic “0” Voltage
0.5
30
0.5
30
0.5
30
0.5
30
Short Circuit Current5
POWER SUPPLY
Positive Supply Current
25°C
Full
25°C
Full
25°C
25°C
I
VI
I
VI
V
V
34
90
56
58
110
120
34
90
56
58
110
120
34
90
56
58
110
120
34
90
56
58
110
120
mA
mA
mA
mA
mW
mW
Negative Supply Current
Nominal Power Dissipation
Reference Ladder Dissipation
550
45
550
45
550
45
550
45
NOTES
1Maximum ratings are limiting values to be applied individually, and beyond which
the serviceability of the device may be impaired. Functional operation under any of
these conditions is not necessarily implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect device reliability.
2Applied voltage must be current-limited to specified range.
3Forcing voltage must be limited to specified range.
10Outputs terminated with 40 pF and eight 10 Ω pull-up resistors.
11Interval from 50% point of leading edge CONVERT pulse to change in
output data.
12For full-scale step input, 8-bit accuracy attained in specified time.
13Recovers to 8-bit accuracy in specified time after –3 V input overvoltage.
14Output time skew includes high-to-low and low-to-high transitions as well as
bit-to-bit time skew differences.
4Current is specified as negative when flowing into the device.
5Output High; one pin to ground; 1s duration.
15Measured at 20 MHz encode rate with analog input 1 dB below full scale.
16Measured at 35 MHz encode rate with analog input 1 dB below full scale.
17RMS signal to rms noise.
6Typical thermal impedances (no air flow) are as follows:
Ceramic DIP: θJA = 49°C/W, θJC = 15°C/W; LCC: θJA = 69°C/W, θJC = 21°C/W;
18Peak signal to rms noise.
JLCC: θJA = 59°C/W; θJC = 19°C/W.
19DC to 8 MHz noise bandwidth with 1.248 MHz slot; four sigma loading;
20 MHz encode.
To calculate junction temperature (TJ), use power dissipation (PD) and thermal
impedance: TJ = PD (θJA) + TAMBIENT = PD (θJC) = + TCASE
.
7Measured with VIN = 0 V and CONVERT low (sampling mode).
8Determined by beat frequency testing for no missing codes.
9VRT ≥ VRB under all circumstances.
20Clock frequency = 4 × NTSC = 14.32 MHz. Measured with 40-IRE
modulated ramp.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level I – 100% production tested.
Test Level II – 100% production tested at 25°C and
sample tested at specific temperatures.
Test Level III – Sample tested only.
Test Level IV – Parameter is guaranteed by design and
characterization testing.
Test Level V – Parameter is a typical value only.
Test Level VI – All devices are 100% production tested at
25°C. 100% production tested at temperature
extremes for military temperature devices;
sample tested at temperature extremes for
commercial/industrial devices.
REV. F
–3–
AD9048
ORDERING GUIDE
PIN CONFIGURATIONS
DIP (D Package)
Package
Option1
Model
Linearity Temperature
1
2
(MSB) D1
D2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NMINV
AD9048JJ
0.75 LSB 0°C to 70°C
J-28A
J-28A
D-28
D-28
R
M
3
D3
AD9048KJ
AD9048JQ
AD9048KQ
0.5 LSB
0.75 LSB 0°C to 70°C
0.5 LSB 0°C to 70°C
0°C to 70°C
R
B
4
D4
AGND
NC
5
DGND
AD9048
AD9048SE/833B2 0.75 LSB –55°C to +125°C E-28A
V
6
V
CC
IN
TOP VIEW
AD9048TE/833B2 0.5 LSB
–55°C to +125°C E-28A
NC
(Not to Scale)
7
V
EE
AD9048SQ/833B2 0.75 LSB –55°C to +125°C D-28
NC
8
V
EE
AD9048TQ/833B2 0.5 LSB
–55°C to +125°C D-28
NC
9
V
EE
10
11
12
13
14
V
AGND
CC
NOTES
1E = Leadless Ceramic Chip Carrier; J = J-Leaded Ceramic; D = Cerdip.
2MIL-STD-883 and Standard Military Drawing available.
DGND
NLINV
D5
R
T
CONVERT
D8 (LSB)
D7
D6
NC = NO CONNECT
MECHANICAL INFORMATION
Die Dimensions . . . . . 140 mils × 137 mils × 21 mils ( 2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 mils × 4 mils
Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic
Bond Wire . . . . . . . . . . . . . . . 1 mils Gold; Gold Ball Bonding
LCC (E Package)
4
3
1
28 27 26
2
25 AGND
24 NC
5
6
DGND
V
CC
23
22
V
IN
V
7
EE
AD9048
TOP VIEW
(Not to Scale)
V
8
NC
EE
21 NC
20
V
9
EE
V
NC
19 AGND
10
11
CC
DGND
AGND
AIN
AGND
12 13 14 15 16 17 18
RLOW
RMID
RTOP
NC = NO CONNECT
NMINV
CONV
D8
MSB
D2
J-Leaded Ceramic (J Package)
D7
D6
D3
25 24 23 22 21 20 19
D4
D5
26
27
28
1
18
17
16
15
14
13
12
R
R
T
B
NLINV
DGND
CONVERT
D8 (LSB)
D7
R
M
DGND
NMINV
(MSB) D1
D2
AD9048
TOP VIEW
(Not to Scale)
2
V
V
V
V
DGND
CC CC
D6
V
V
V
CC CC
EE EE EE
3
D5
D3
Figure 1. Bonding Diagram
4
NLINV
D4
5
6
7
8
9
10 11
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9048 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. F
AD9048
PIN FUNCTION DESCRIPTIONS
Mnemonic
Description
Mnemonic
Description
RB
Most Negative Reference Voltage for Internal
Reference Ladder
D1–D8
Eight Digital Outputs. D1 (MSB) is the most
significant bit of the digital output word;
D8 (LSB) is the least significant bit.
RM
RT
Midpoint Tap on Internal Reference Ladder
AGND
DGND
One of Two Analog Ground Returns. Both
grounds should be connected together and to
low impedance ground plane near the AD9048.
Most Positive Reference Voltage for Internal
Reference Ladder
VIN
Analog Input Signal Pin
One of Two Digital Ground Returns. Both
grounds should be connected together and to
low impedance ground plane near the AD9048.
NMINV
“Not Most Significant Bit Invert.” In normal
operation, this pin floats high; logic LOW at
NMINV inverts most significant bit of digital
output word [D1 (MSB)].
VCC
VEE
Positive Supply Terminals; Nominally 5.0 V
Negative Supply Terminals; Nominally –5.2 V
NLINV
“Not Least Significant Bit Invert.” In normal
operation, this pin floats high; logic LOW at
NLINV inverts the seven least significant bits
of the digital output word.
CONVERT Input for Conversion Signal. Sample of analog
input signal taken on rising edge of this pulse.
–5.2V
+5.0V
0.1ꢁF
0.1ꢁF
V
V
CC
EE
100ꢀ
510ꢀ
(MSB) D1
AD1
AD2
V
IN
D2
D3
D4
CONVERT
AD9048
D5
D6
–2.0V
R
B
D7
(LSB) D8
R
T
1kꢀ
LOAD
RESISTORS
DIGITAL
GROUND
ANALOG
GROUND
ALL RESISTORS ꢂ5%
OPTION #1 (STATIC): AD1 = –2.0V; AD2 = +2.4V
OPTION #2 (DYNAMIC): SEEWAVEFORMS
ALL CAPACITORS ꢂ20%
ALL SUPPLYVOLTAGES ꢂ5%
0V
AD1
–2.0V
640ꢁs
V
IH
AD2
V
IL
5ꢁs
Figure 2. Burn-In Diagram
REV. F
–5–
AD9048
THEORY OF OPERATION
System timing, which provides details on delays through the
AD9048 as well as the relationships of various timing events, is
shown in Figure 4.
Refer to the Functional Block Diagram of the AD9048. The
AD9048 comprises three functional sections: a comparator
array, encoding logic, and output latches.
N+1
Within the array, the analog input signal to be digitized is
compared with 255 reference voltages. The outputs of all com-
parators whose references are below the input signal level will be
high; outputs whose references are above that level will be low.
ANALOG
INPUT
N
N+2
APERTURE
DELAY
The n-of-255 code that results from this comparison is applied
to the encoding logic where it is converted into binary coding.
When it is inverted with dc signals applied to the NLINV and/or
NMINV pins, it becomes twos complement.
CONVERT
tOH
OUTPUT
DATA
N
N–1
N+1
tPD
DATA
DATA
After encoding, the signal is applied to the output latch circuits
where it is held constant between updates controlled by the
application of CONVERT pulses.
CHANGING
CHANGING
Figure 4. Timing Diagram
The AD9048 uses strobed latching comparators in which com-
parator outputs are either high or low, as dictated by the analog
input level. Data appearing at the output pins have a pipeline
delay of one encode cycle.
Dynamic performance of the AD9048, i.e., typical signal-to-
noise ratio, is illustrated in Figures 5 and 6.
50
48
46
Input signal levels between the references applied to RT (Pin 18)
and RB (Pin 26) will appear at the output as binary numbers
between 0 and 255, inclusive. Signals outside that range will
show up as either full-scale positive or full-scale negative out-
puts. No damage will occur to the AD9048 as long as the input
is within the voltage range of VEE to 0.5 V.
44
The significantly reduced input capacitance of the AD9048
lowers the drive requirements of the input buffer/amplifier and
also induces much smaller phase shift in the analog input signal.
42
40
38
Applications that depend on controlled phase shift at the con-
verter input can benefit from using the AD9048 because of its
inherently lower phase shift.
100kHz
1MHz
10MHz
ANALOG INPUT FREQUENCY – 1dB BELOW FULL-SCALE
The CONVERT, analog input, and digital output circuits are
shown in Figure 3.
Figure 5. Dynamic Performance (20 MHz Encode Rate)
5.0V
5.0V
50
48
46
13kꢀ
DIGITAL
OUTPUTS
CONVERT
44
R
T
R
42
40
38
R/2
R/2
R
M
100kHz
1MHz
10MHz
–5.2V
–5.2V
ANALOG INPUT FREQUENCY – 1dB BELOW FULL-SCALE
ANALOG
INPUT
Figure 6. Dynamic Performance (35 MHz Encode Rate)
R
R
B
–5.2V
COMPARATOR CELLS
–5.2V
Figure 3. Input/Output Circuits
–6–
REV. F
AD9048
LAYOUT SUGGESTIONS
0.1ꢁF
AD589
10kꢀ
–5.2V
Designs that use the AD9048 or any other high speed device
must follow some basic layout rules to ensure optimum
performance.
2kꢀ
27ꢀ
The first requirement is to have a large, low impedance ground
plane under and around the converter. If the system uses separate
analog and digital grounds, both should be solidly connected
together, and to the ground plane, as closely to the AD9048 as
practical to avoid ground loop currents.
100ꢀ
2N3906
0.1ꢁF
AD741
5ꢀ
1kꢀ
1kꢀ
0.1ꢁF
Ceramic 0.1 µF decoupling capacitors should be placed as closely
as possible to the supply pins of the AD9048. For decoupling
low frequency signals, use 10 µF tantalum capacitors also con-
nected as closely as practical to voltage supply pins.
R
R
B
R
T
ANALOG
INPUT
(0VTO 2V)
R
43ꢀ
D1 (MSB)
V
IN
50ꢀ
AD9617/AD9618,
AD9620/AD9630,
AD847
AD9048
Within the AD9048, reference currents may vary because of
coupling between the clock and input signals. As a result, it is
important that the ends of the reference ladder, RT (Pin 18) and
RB (Pin 26), be connected to low impedances (as measured
from ground).
TTL
CONVERT
SIGNAL
CONVERT
D8 (LSB)
V
V
EE
CC
0.1ꢁF
0.1ꢁF
If the AD9048 is being used in a circuit in which the reference
is not varied, a bypass capacitor to ground is strongly recom-
mended. In applications that use varying references, they must
be driven from a low impedance source.
+5.0V
–5.2V
Figure 7. Typical Connections
Table I. Truth Table
Binary
Offset Twos
Complement
Step
Range
True
Inverted
True
Inverted
–2.000 V FS
–2.0480 V FS
NMINV = 1
0
0
1
7.8431 mV Step 8.000 mV Step
NLINV = 1
00000000
00000001
•
0
1
0
000
001
•
0.0000 V
–0.0078 V
0.0000 V
–0.0080 V
11111111
11111110
•
10000000
10000001
•
01111111
01111110
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
127
128
129
•
–0.9961 V
–1.0039 V
–1.0118 V
•
–1.0160 V
–1.0240 V
–1.0320 V
•
01111111
10000000
10000001
•
10000000
01111111
01111110
•
11111111
00000000
00000001
•
00000000
11111111
11111110
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
254
255
–1.9921 V
–2.0000 V
–2.0320 V
–2.0400 V
11111110
11111111
00000001
00000000
01111110
01111111
10000001
10000000
REV. F
–7–
AD9048
OUTLINE DIMENSIONS
28-Terminal Ceramic Leadless Chip Carrier [LCC]
28-Lead Side-Brazed Ceramic Dual In-Line Package
(E-28A)
[SBDIP]
(D-28)
Dimensions shown in inches and (millimeters)
Dimensions shown in inches and (millimeters)
0.300 (7.62)
REF
0.100 (2.54)
0.064 (1.63)
0.075
(1.91)
REF
0.020 (0.51)
MIN
0.100 (2.54)
0.005 (0.13)
MAX
MIN
19
25
0.028 (0.71)
0.022 (0.56)
28
15
14
18
26
28
0.05 (1.27)
0.610 (15.49)
0.580 (12.73)
0.458
0.458 (11.63)
0.442 (11.23)
(11.63)
MAX
SQ
BOTTOM
VIEW
1
SQ
0.15 (3.81)
REF
PIN 1
1
0.075 (1.91)
0.620 (15.75)
0.590 (14.99)
REF
12
4
1.490 (37.85) MAX
0.085 (2.16)
0.060 (1.52)
0.015 (0.38)
11
5
MAX
0.095 (2.41)
0.075 (1.90)
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
0.150
(3.81)
MIN
0.018 (0.46)
0.008 (0.20)
0.200 (5.08)
0.125 (3.18)
SEATING
PLANE
0.026 (0.66)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.070 (1.78)
0.030 (0.76)
0.100 (2.54)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Lead Ceramic Chip Carrier - J-Formed Leads [JLCC]
(J-28A)
Dimensions shown in inches and (millimeters)
0.040 (1.02)
0.020 (0.51)
REF
x 45
0.125 (3.18)
MAX
REF
x 45
0.460 (11.68)
0.440 (11.18)
SQ
3 PLACES
4
26
26
4
5
25
25
5
0.035 (0.89)
0.025 (0.64)
PIN 1 INDEX
0.055 (1.40)
PIN 1
0.450 (11.43)
0.410 (10.41)
0.050
(1.27)
0.310 (7.87)
0.290 (7.37)
TOP VIEW
BOTTOM VIEW
0.022 (0.56)
0.012 (0.30)
11
19
19
11
12
18
18
12
0.500 (12.70)
0.480 (12.19)
SQ
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
Page
5/03—Data Sheet changed from REV. E to REV. F.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
09/01—Data Sheet changed from REV. D to REV. E.
Change in ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
05/01—Data Sheet changed from REV. C to REV. D.
Change in ORDERING GUIDE and PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to 28-Lead Ceramic Side-Brazed DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
–8–
REV. F
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