AD9049 [ADI]
9-Bit, 30 MSPS ADC; 9位， 30 MSPS ADC
| 型号： | AD9049 |
| 厂家： | 
ADI |
| 描述： | 9-Bit, 30 MSPS ADC |
| 文件： | 总12页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
9-Bit, 30 MSPS ADC
AD9049
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Low Power: 300 mW
On-Chip T/H, Reference
Single +5 V Power Supply Operation
Selectable 5 V or 3 V Logic I/O
Wide Dynamic Performance
GND
+5V
+5V
AD9049
REFERENCE CKTS
ADC
AINB
AIN
T/H
APPLICATIONS
Digital Communications
Professional Video
Medical Imaging
Instrumentation
9
DECODE
LOGIC
SUM
AMP
DAC
ADC
TIMING
ENCODE
+5V
PRODUCT DESCRIPTION
The AD9049 is a complete 9-bit monolithic sampling analog-
to-digital converter (ADC) with an onboard track-and-hold and
reference. The unit is designed for low cost, high performance
applications and requires only +5 V and an encode clock to
achieve 30 MSPS sample rates with 9-bit resolution.
2, 8, 11,
20, 22
4
3
AIN
10
(+3.3V ± 0.512V)
0.1µF
+5V
5
6
9
9 BITS
(2)
74AC574
AD9049
0.1µF
The encode clock is TTL compatible and the digital outputs
are CMOS; both can operate with 5 V/3 V logic, selected by the
user. The two-step architecture used in the AD9049 is opti-
mized to provide the best dynamic performance available while
maintaining low power consumption.
0.1µF
1, 7, 12,
21, 23
13
ENCODE
A 2.5 V reference is included onboard, or the user can provide
an external reference voltage for gain control or matching of
multiple devices. Fabricated on an advanced BiCMOS process,
the AD9049 is packaged in space saving surface mount pack-
ages (SOIC, SSOP) and is specified over the industrial
(–40°C to +85°C) temperature range.
Figure 1. Typical Connections
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1996
AD9049–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (VD, VDD = +5 V; internal reference; ENCODE = 30 MSPS unless otherwise noted)
Test
Level
AD9049BR/BRS
Typ
Parameter
Temp
Min
Max
Units
RESOLUTION
9
Bits
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
Full
+25°C
Full
I
V
I
V
IV
I
0.5
0.5
0.5
0.5
1.0
1.0
LSB
LSB
LSB
LSB
Integral Nonlinearity
No Missing Codes
Gain Error
GUARANTEED
±1.0
±7.5
% FS
ppm/°C
Gain Tempco1
V
±100
ANALOG INPUT
Input Voltage Range
Input Offset Voltage
+25°C
+25°C
Full
+25°C
+25°C
+25°C
V
I
IV
I
V
V
1.024
+7
V p-p
mV
mV
kΩ
pF
–10
–32
3.5
+25
+51
6.5
Input Resistance
Input Capacitance
Analog Bandwidth
5.0
5
100
MHz
BANDGAP REFERENCE
Output Voltage
+25°C
Full
I
V
2.4
30
2.5
±50
2.6
V
Temperature Coefficient1
ppm/°C
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Propagation Delay (tPD
+25°C
+25°C
+25°C
+25°C
Full
I
IV
V
V
IV
MSPS
MSPS
ns
ps, rms
ns
1.5
2.7
5
3
2
)
5
15
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
ENOBS
+25°C
+25°C
V
V
10
10
ns
ns
f
f
IN = 2.3 MHz
IN = 10.3 MHz
+25°C
+25°C
V
I
8.56
8.51
ENOBs
ENOBs
8.01
50
Signal-to-Noise Ratio (SINAD)3
fIN = 2.3 MHz
+25°C
+25°C
V
I
53.3
53
dB
dB
f
IN = 10.3 MHz
Signal-to-Noise Ratio
(Without Harmonics)
f
f
IN = 2.3 MHz
IN = 10.3 MHz
+25°C
+25°C
V
I
53.5
53.3
dB
dB
51
2nd Harmonic Distortion
f
f
IN = 2.3 MHz
IN = 10.3 MHz
+25°C
+25°C
V
I
–69
–67
dBc
dBc
–60
–58
3rd Harmonic Distortion
f
f
IN = 2.3 MHz
IN = 10.3 MHz
+25°C
+25°C
V
I
–75
–66
dBc
dBc
Two-Tone Intermodulation
Distortion (IMD)4
Differential Phase
+25°C
+25°C
+25°C
V
V
V
65
0.15
0.35
dBc
Degrees
%
Differential Gain
–2–
REV. A
AD9049
Test
Level
AD9049BR/BRS
Typ
Parameter
Temp
Min
Max
Units
ENCODE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Encode Pulse Width High (tEH
Full
Full
Full
Full
+25°C
+25°C
+25°C
IV
IV
IV
IV
V
2.0
V
V
0.8
1
1
µA
µA
pF
ns
ns
10
)
)
IV
IV
10
10
166
166
Encode Pulse Width Low (tEL
DIGITAL OUTPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Voltage (3.0 VDD
Logic “0” Voltage (3.0 VDD
Output Coding
Full
Full
Full
Full
IV
IV
IV
IV
4.95
2.95
V
V
V
V
0.05
)
)
0.05
Code
Offset
40
Binary
POWER SUPPLY
VD, VDD Supply Current5
Full
Full
IV
IV
60
300
80
400
mA
mW
Power Dissipation5
Power Supply Rejection Ratio
(PSRR)6
+25°C
I
±10
mV/V
NOTES
1“Gain Tempco” is for converter only; “Temperature Coefficient” is for bandgap reference only.
2Output propagation delay (tPD) is measured from the 50% point of the rising edge of the encode command to the midpoint of the digital outputs with 10 pF
maximum loads.
3RMS signal to rms noise with analog input signal 0.5 dB below full scale at specified frequency.
4Intermodulation measured relative to either tone with analog input frequencies of 9.5 MHz and 9.9 MHz at 7 dB below full scale.
5Power dissipation is measured at 30 MSPS with AIN of 10.3 MHz and digital outputs loaded with 10 pF maximum. See Figure 4 for power dissipation at other
conditions.
6Measured as the ratio of the change in offset voltage for 5% change in +VD
Specifications subject to change without notice.
.
EXPLANATION OF TEST LEVELS
Test Level
ABSOLUTE MAXIMUM RATINGS*
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . –1.0 V to VD + 1.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD
VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature
I
–
–
100% Production Tested.
IV
Parameter is guaranteed by design and characteriza-
tion testing.
V
–
Parameter is a typical value only.
AD9049BR/BRS . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may effect device reliability.
ORDERING GUIDE
Temperature Range Package Option*
Model
AD9049BR
AD9049BRS
–40°C to +85°C
–40°C to +85°C
R-28
RS-28
*R = Small Outline (SO); RS = Shrink Small Outline (SSOP).
REV. A
–3–
AD9049
Table I. AD9049 Digital Coding (Single Ended Input AIN, AINB Bypassed to GND)
Digital Output
Analog Input
Voltage Level
MSB . . . LSB Digital Output
3.810
3.300
2.790
Positive Full Scale
Midscale
Negative Full Scale
111111111
011111111
000000000
PIN DESCRIPTIONS
Pin No
Name
Function
1, 7, 12, 21, 23
GND
Ground.
2, 8, 11
VD
Analog +5 V ± 5% power supply.
3
4
5
6
9
10
13
VREFOUT
VREFIN
COMP
REFBP
AINB
Internal bandgap voltage reference (nominally +2.5 V).
Input to reference amplifier. Voltage reference for ADC is connected here.
Internal compensation pin, 0.1 µF bypass connected here to VD (+5 V).
External connection for (0.1 µF) reference bypass capacitor.
Complementary analog input pin (Analog input bar).
Analog input pin.
AIN
ENCODE
Encode clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding)
on rising edge of encode signal.
14
NC
Not internally connected.
15
D8 (MSB)
D7–D4
VDD
D3–D1
D0 (LSB)
NC
Most significant bit of ADC output.
Digital output bits of ADC.
Digital output power supply (only used by digital outputs).
Digital output bits of ADC.
Least significant bit of ADC output.
16–19
20, 22
24–26
27
28
Not internally connected.
PIN CONNECTIONS
NC
GND
1
2
28
27
V
D
D0 (LSB)
VREF
OUT
3
26 D1
VREF
D2
4
25
24
23
22
IN
COMP
D3
5
6
GND
REF
BP
AD9049
TOP VIEW
(Not to Scale)
GND
7
V
DD
8
V
D
21 GND
9
AINB
AIN
20
V
DD
19 D4
18 D5
17 D6
16 D7
10
11
12
13
14
V
D
GND
ENCODE
NC
D8 (MSB)
15
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9049 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD9049
N
N + 1
N + 2
N + 3
N + 4
N + 5
AIN
MIN
TYP
MAX
tA
APERTURE DELAY
PULSE WIDTH HIGH
PULSE WIDTH LOW
OUTPUT PROP DELAY
2.7ns
tA
tEH tEL
tEH
tEL
tPD
10ns
10ns
5.0ns
166ns
166ns
15.0ns
ENCODE
8.2ns
tPD
DIGITAL
OUTPUTS
N – 5
N – 4
N – 3
N – 2
N – 1
N
Figure 2. Timing Diagram
V
(Pins 20, 22)
V
DD
+3V to +5V
D
V
D
INPUT
BUFFER
8k
8k
AINB (Pin 9)
AIN (Pin 10)
ENCODE
(Pin 13)
D0–D8
16k 16k
Analog Input
Encode Input
Output Stage
V
D
V
D
A
V
VREF
OUT
VREF
IN
(Pin 4)
(Pin 3)
VREF
BF
(Pin 6)
V
REF Output
Reference Circuit
Figure 3. Equivalent Circuits
REV. A
–5–
AD9049–Typical Performance Curves
361
58
57
56
55
54
342
AIN = 10.3 MHz
ENCODE = 30 MSPS
IN = 10.3 MHz
323
A
304
OUTPUTS @ 5V
285
266
53
52
51
50
49
48
247
OUTPUTS @ 3V
228
209
190
171
0
0
20
40
60
80
90
10
20
30
– 20
–40
CLOCK RATE – MSPS
TEMPERATURE – °C
Figure 4. Power Dissipation vs. Clock Rate
Figure 7. SNR vs. Temperature
80
0
ENCODE = 30 MSPS
ENCODE = 30 MSPS
f1 IN = 9.5 MHz @ –7 dBFS
f2 IN = 9.9 MHz @ –7 dBFS
2f1–f2 = –65.4 dBc
–10
74
–20
–30
HARMONIC DISTORTION
2f2–f1 = –65.0 dBc
68
62
–40
–50
–60
SIGNAL-TO-NOISE
56
–70
–80
50
44
38
–90
–100
–110
–120
0
2.5
5
7.5
10
12.5
15
1
10
100
FREQUENCY – MHz
ANALOG INPUT FREQUENCY – MHz
Figure 5. SNR/Distortion vs. Frequency
Figure 8. Two-Tone IMD
60
0.50
0.25
0.00
58
AIN = 10.3 MHz
56
54
–0.25
–0.50
1
2
3
4
5
6
52
50
0.50
0.25
0.00
48
46
–0.25
–0.50
0
5
10
15
20
25
30
1
2
3
4
5
6
CLOCK RATE – MSPS
Figure 9. Differential Gain/Differential Phase
Figure 6. SNR vs. Clock Rate
–6–
REV. A
AD9049
55.0
54.5
54.0
0
ENCODE = 30 MSPS
ANALOG IN = 2.3 MHz
SNR = 53.0 dB
SNR (W/O HAR) = 53.3 dB
2ND HARMONIC = 69.3 dB
3RD HARMONIC = 72.9 dB
–10
ENCODE = 30 MSPS
IN = 2.3 MHz
A
–20
–30
–40
53.5
53.0
–50
–60
–70
–80
52.5
52.0
–90
–100
–110
51.5
51.0
–120
25
30
35
40
45
50
55
60
65
70
75
0
2.5
5
7.5
10
12.5
15
15
15
FREQUENCY – MHz
DUTY CYCLE – %
Figure 10. FFT Plot 30 MSPS, 2.3 MHz
Figure 13. SNR vs. Clock Pulse Width
0
1.0
0.5
0.0
ENCODE = 30 MSPS
ANALOG IN = 4.3 MHz
SNR = 53.0 dB
SNR (W/O HAR) = 53.3 dB
2ND HARMONIC = 69.0 dB
3RD HARMONIC = 72.6 dB
–10
ENCODE = 30 MSPS
–20
–30
–40
–0.5
–1.0
–50
–60
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–70
–80
–90
–100
–110
–120
1
10
ANALOG INPUT FREQUENCY – MHz
100
1000
0
2.5
5
7.5
10
12.5
FREQUENCY – MHz
Figure 11. FFT Plot 30 MSPS, 4.3 MHz
Figure 14. ADC Gain vs. AIN Frequency
15.0
0
ENCODE = 30 MSPS
ANALOG IN = 10.3 MHz
SNR = 52.7 dB
SNR (W/O HAR) = 53.1 dB
2ND HARMONIC = 66.4 dB
3RD HARMONIC = 70.5 dB
[1] - 5V DATA RISING EDGE
[2] - 5V DATA FALLING EDGE
[3] - 3V DATA RISING EDGE
[4] - 3V DATA FALLING EDGE
–10
14.0
13.0
12.0
11.0
10.0
9.0
–20
–30
–40
[3]
[1]
[4]
–50
–60
[2]
–70
–80
8.0
–90
–100
–110
7.0
6.0
5.0
– 40
–120
0
20
40
60
80
100
–20
0
2.5
5
7.5
10
12.5
FREQUENCY – MHz
TEMPERATURE – °C
Figure 12. FFT Plot 30 MSPS, 10.3 MHz
Figure 15. tPD vs. Temperature 3 V/5 V
REV. A
–7–
AD9049
THEORY OF OPERATION
1kΩ
Refer to the block diagram on the front page.
+5V
+5V
1kΩ
The AD9049 employs a subranging architecture with digital
error correction. This combination of design techniques ensures
true 9-bit accuracy at the digital outputs of the converter.
V
IN
–0.5V to +0.5V
10
9
AD9049
AD8041
At the input, the analog signal is buffered by a high speed differ-
ential buffer and applied to a track-and-hold (T/H) that holds
the analog value which is present when the unit is strobed with
an ENCODE command. The conversion process begins on the
rising edge of this pulse. The two stage architecture completes a
coarse and then a fine conversion of the T/H output signal.
0.1µF
+5V
AD820
1kΩ
1kΩ
0.1µF
Figure 16. Single Supply, Single Ended, DC Coupled
AD9049
Error correction and decode logic correct and align data from
the two conversions and present the result as a 9-bit parallel
digital word. Output data are strobed on the rising edge of the
ENCODE command. The subranging architecture results in
five pipeline delays for the output data. Refer to the AD9049
Timing Diagram.
1kΩ
+5V
+5V
1kΩ
0.1µF
0.1µF
V
IN
–0.5V to +0.5V
10
9
AD9049
AD8011
USING THE AD9049
3 V System
–5V
The digital input and outputs of the AD9049 can easily be
configured to directly interface to 3 V logic systems. The encode
input (Pin 13) is TTL compatible with a logic threshold of 1.5
V. This input is actually a CMOS stage (refer to Equivalent En-
code Input Stage) with a TTL threshold, allowing operation
with TTL, CMOS and 3 V CMOS logic families. Using 3 V
CMOS logic allows the user to drive the encode directly without
the need to translate to +5 V. This saves the user power and
board space. As with all high speed data converters, the clock
signal must be clean and jitter free to prevent the degradation of
dynamic performance.
Figure 17. Single Ended, Capacitively Coupled AD9049
1kΩ
+5V
+5V
1kΩ
V
0.1µF
AD8011
IN
–0.5V to +0.5V
T1-1T
10
9
AD9049
50Ω
–5V
The AD9049 outputs can also directly interface to 3 V logic
systems. The digital outputs are standard CMOS stages (refer to
AD9049 Output Stage) with isolated supply pins (Pins 20, 22
Figure 18. Differentially Driven AD9049 Using Trans-
former Coupling.
V
DD). By varying the voltage on the VDD pins, the digital output
The AD830 provides a unique method of providing dc level shift
for the analog input. Using the AD830 allows a great deal of
flexibility for adjusting offset and gain. Figure 19 shows the
AD830 configured to drive the AD9049. The offset is provided
by the internal biasing of the AD9049 differential input (Pin 9).
For more information regarding the AD830, see the AD830
data sheet.
levels vary respectively. By connecting Pins 20 and 22 to the
3 V logic supply, the AD9049 will supply 3 V output levels.
Care should be taken to filter and isolate the output supply of
the AD9049 as noise could be coupled into the ADC, limiting
performance.
Analog Input
The analog input of the AD9049 is a differential input buffer
(refer to AD9049 Equivalent Analog Input). The differential in-
puts are internally biased at +3.3 V, obviating the need for
external biasing. Excellent performance is achieved whether the
analog inputs are driven single-ended or differential. (For best
dynamic performance, impedances at AIN and AINB should
match.)
V
IN
+5V
+15V
AD830
–5V
–0.5V to +0.5V
1
2
3
4
7
10
9
AD9049
0.1µF
Figure 16 shows typical connections for the analog inputs when
using the AD9049 in a dc coupled system with single ended
signals. All components are powered from a single +5 V supply.
The AD820 is used to offset the ground referenced input signal
to the level required by the AD9049.
Figure 19. Level Shifting with the AD830
AC coupling of the analog inputs to the AD9049 is easily accom-
plished. Figure 17 shows capacitive coupling of a single ended
signal while Figure 18 shows transformer coupling differentially
into the AD9049.
–8–
REV. A
AD9049
Overdrive of the Analog Input
Power Dissipation
Special care was taken in the design of the analog input section
of the AD9049 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is +2.788 V to
3.812 V (1.024 V p-p centered at 3.3 V). Out-of-range com-
parators detect when the analog input signal is out of this range
and shut the T/H off. The digital outputs are locked at their
maximum or minimum value (i.e., all “0” or all “1”). This pre-
cludes the digital outputs from changing to an invalid value
when the analog input is out of range.
The power dissipation specification in the parameter table is
measured under the following conditions: encode is 30 MSPS,
analog input is –1 dBFS at 10.3 MHz, the digital outputs are
loaded with approximately 7 pF (10 pF maximum), and VDD is
5 V. These conditions intend to reflect actual usage of the device.
As shown in Figure 4, the actual power dissipation varies based
on these conditions. For instance, reducing the clock rate will
reduce power as expected for CMOS type devices. Also the
loading determines the power dissipated in the output stages.
From an ac standpoint, the capacitive loading will be the key
(refer to Equivalent Output Stage).
When the analog input signal returns to the nominal range, the
out-of-range comparators switch the T/H back to the active
mode and the device recovers in approximately 10 ns.
The analog input frequency and amplitude in conjunction with
the clock rate determine the switching rate of the output data
bits. Power dissipation increases as more data bits switch at
faster rates. For instance, if the input is a dc signal that is out of
range, no output bits will switch. This minimizes power in the
output stages but is not realistic from a usage standpoint.
The input is protected to one volt outside the power supply
rails. For nominal power (+5 V and ground), the analog input
will not be damaged with signals from +6.0 V to –1.0 V.
Timing
The performance of the AD9049 is very insensitive to the duty
cycle of the clock. Pulse width variations of as much as ±10%
will cause no degradation in performance (see Figure 13, SNR
vs. Clock Pulse Width).
The dissipation in the output stages can be minimized by inter-
facing the outputs to 3 V logic (refer to USING THE AD9049,
3 V System). The lower output swings minimize consumption.
Refer to Figure 4 for performance characteristics.
The AD9049 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (tPD
after the rising edge of the encode command (refer to the
AD9049 Timing Diagram). The length of the output data lines
and loads placed on them should be minimized to reduce tran-
sients within the AD9049; these transients can detract from the
converter’s dynamic performance.
)
Voltage Reference
A stable and accurate +2.5 V voltage reference is built into the
AD9049 (Pin 3, VREF Output). In normal operation the internal
reference is used by strapping Pins 3 and 4 of the AD9049 to-
gether. The internal reference has 500 µA of extra drive current
that can be used for other circuits.
The minimum guaranteed conversion rate of the AD9049 is
3 MSPS. Below a nominal of 1.5 MSPS the internal T/H
switches to a track function only. This precludes the T/H from
drooping to the rail during the conversion process and mini-
mizes saturation issues. At clock rates below 3 MSPS dynamic
performance degrades. The AD9049 will operate in burst mode
operation, but the user must flush the internal pipeline each
time the clock stops. This requires 5 clock pulses each time the
clock is restarted for the first valid data output (refer to Fig-
ure 2 Timing Diagram).
Some applications may require greater accuracy, improved tem-
perature performance or adjustment of the gain of the AD9049,
which cannot be obtained by using the internal reference. For
these applications, an external +2.5 V reference can be used to
connect to Pin 4 of the AD9049. The VREFIN requires 5 µA of
drive current.
The input range can be adjusted by varying the reference volt-
age applied to the AD9049. No appreciable degradation in per-
formance occurs when the reference is adjusted ±5%. The
full-scale range of the ADC tracks reference voltage changes
linearly.
REV. A
–9–
AD9049
Figure 20. Evaluation Board Top Layer
Figure 22. Evaluation Board Bottom Layer
Figure 21. Evaluation Board Ground Layer
–10–
REV. A
AD9049
U3
74AC574R
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
8D
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
U1
AD9049R
7D
6D
5D
4D
3D
2D
1D
15
16
17
18
19
24
25
26
27
R5
1k
D8/MSB
3
4
5
6
9
D7
D6
D5
D4
D3
D2
D1
D0
J3
HDR20
VREFOUT
VREFIN
COMP
REFBP
AINB
TP3
U2
AD9631Q
R4
1k
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C9
0.1µF
2
3
J2
CK
IN
IN
6
10
13
OE
OUT
AIN
ENC
R3
50
11
1
NC
+5V
+5V
20
22
U6:B
74AC00R
C1
0.1µF
4
5
6
C2
0.1µF
U4
74AC574R
TP2
+5V
J7
C3
0.1µF
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
8D
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
E1
7D
6D
5D
4D
3D
2D
1D
+5V
R1
50
3
OUT
4
2
GND
VCC
11
Y1
+5V
SW41
CK
+5V
OE
U6:A
1
11
74AC00R
12
13
1
2
3
U6:D
74AC00R
R2
2k
9
8
10
+5V
J6
U6:C
74AC00R
J1
+5V
+5V
+
C7
0.1µF
C5
10µF
C10
0.1µF
C12
0.1µF
C13
0.1µF
C14
0.1µF
C15
0.1µF
C16
0.1µF
C17
0.1µF
C22
0.1µF
C23
0.1µF
C24
0.1µF
J5
–5.2V
–5.2V
C6
10µF
C8
0.1µF
C20
0.1µF
+
Figure 23. Evaluation Board Schematic
REV. A
–11–
AD9049
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SOIC
(R-28)
0.7125 (18.10)
0.6969 (17.70)
29
15
1
14
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
28-Lead SSOP
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
14
1
0.07 (1.79)
0.078 (1.98)
0.068 (1.73)
PIN 1
0.066 (1.67)
0.03 (0.762)
8°
0°
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.022 (0.558)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
–12–
REV. A
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