AD9050JJ [ADI]
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQCC28, CERAMIC, LCC-28, Analog to Digital Converter;
| 型号： | AD9050JJ |
| 厂家： | 
ADI |
| 描述： | IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQCC28, CERAMIC, LCC-28, Analog to Digital Converter 信息通信管理 转换器 |
| 文件： | 总12页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 40 MSPS/60 MSPS
A/D Converter
a
AD9050
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
Low Pow er: 315 m W @ 40 MSPS, 345 m W @ 60 MSPS
On-Chip T/ H, Reference
GND
+5V
Single +5 V Pow er Supply Operation
Selectable 5 V or 3 V Logic I/ O
SNR: 53 dB Minim um at 10 MHz w / 40 MSPS
+5V
AD9050
REFERENCE CKTS
ADC
AINB
AIN
T/H
APPLICATIONS
Medical Im aging
Instrum entation
Digital Com m unications
Professional Video
10
DECODE
LOGIC
SUM
AMP
DAC
ADC
TIMING
ENCODE
P RO D UCT D ESCRIP TIO N
+5V
T he AD9050 is a complete 10-bit monolithic sampling analog-
to-digital converter (ADC) with an onboard track-and-hold and
reference. T he unit is designed for low cost, high performance
applications and requires only +5 V and an encode clock to
achieve 40 MSPS or 60 MSPS sample rates with 10-bit resolution.
2, 8, 11,
20, 22
4
3
AIN
10
(+3.3V ± 0.512V)
0.1µF
+5V
5
6
9
10 BITS
(2)
74AC574
AD9050
0.1µF
T he encode clock is T T L compatible and the digital outputs
are CMOS; both can operate with 5 V/3 V logic, selected by the
user. T he two-step architecture used in the AD9050 is opti-
mized to provide the best dynamic performance available while
maintaining low power consumption.
0.1µF
1, 7, 12,
21, 23
13
ENCODE
A 2.5 V reference is included onboard, or the user can provide
an external reference voltage for gain control or matching of
multiple devices. Fabricated on an advanced BiCMOS pro-
cess, the AD9050 is packaged in space saving surface mount
packages (SOIC, SSOP) and is specified over the industrial
(–40°C to +85°C) temperature range. T he 60 MSPS version
(AD9050BRS-60) is only available in the SSOP package.
Figure 1. Typical Connections
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
AD9050–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V , V = +5 V; internal reference; ENCODE = 40 MSPS for BR/BRS, 60 MSPS for BRS-60
unless otherwise noted)
D
DD
Test
Level
AD 9050BR/BRS
AD 9050BRS-60
P aram eter
Tem p
Min
Typ
Max
Min
Typ
Max
Units
RESOLUT ION
10
10
Bits
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
Full
+25°C
Full
I
V
I
V
IV
I
0.75
1.0
1.0
1.25
GUARANT EED
1.75
1.75
0.85
1.1
1.25
1.50
GUARANT EED
±1.0
1.85
2.0
LSB
LSB
LSB
LSB
Integral Nonlinearity
No Missing Codes
Gain Error
±1.0
±100
7.5
8.5
% FS
ppm/°C
Gain T empco1
V
±100
ANALOG INPUT
Input Voltage Range
Input Offset Voltage
+25°C
+25°C
Full
+25°C
+25°C
+25°C
V
I
IV
I
V
V
1.024
+7
1.024
+7
V p-p
mV
mV
kΩ
pF
MHz
–10
–32
3.5
+25
+51
6.5
–10
–32
3.5
+25
+51
6.5
Input Resistance
Input Capacitance
Analog Bandwidth
5.0
5
100
5.0
5
100
BANDGAP REFERENCE
Output Voltage
+25°C
Full
I
V
2.4
40
2.5
±50
2.6
2.4
60
2.5
±50
2.6
V
T emperature Coefficient1
ppm/°C
SWIT CHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Propagation Delay (tPD
+25°C
+25°C
+25°C
+25°C
Full
I
IV
V
V
IV
MSPS
MSPS
ns
ps, rms
ns
1.5
2.7
5
3
1.5
2.7
5
3
2
)
5
15
5
15
DYNAMIC PERFORMANCE
T ransient Response
Overvoltage Recovery T ime
ENOBS
+25°C
+25°C
V
V
10
10
10
10
ns
ns
fIN = 2.3 MHz
+25°C
+25°C
V
I
8.93
8.85
8.93
8.51
ENOBs
ENOBs
fIN = 10.3 MHz
8.51
53
8.15
51
Signal-to-Noise Ratio (SINAD)3
fIN = 2.3 MHz
+25°C
+25°C
V
I
55.5
55
55.5
53
dB
dB
fIN = 10.3 MHz
Signal-to-Noise Ratio
(Without Harmonics)
fIN = 2.3 MHz
+25°C
+25°C
V
I
56
55.5
56
54.0
dB
dB
fIN = 10.3 MHz
53.5
51.5
2nd Harmonic Distortion
f
IN = 2.3 MHz
+25°C
+25°C
V
I
–69
–67
–69
–64
dBc
dBc
fIN = 10.3 MHz
3rd Harmonic Distortion
fIN = 2.3 MHz
–60
–58
–58.5
–57.5
+25°C
+25°C
V
I
–75
–70
–75
–62
dBc
dBc
fIN = 10.3 MHz
T wo-T one Intermodulation
Distortion (IMD)4
Differential Phase
Differential Gain
+25°C
+25°C
+25°C
V
V
V
65
0.15
0.25
65
0.15
0.25
dBc
Degrees
%
–2–
REV. B
AD9050
Test
AD 9050BR/BRS
AD 9050BRS-60
P aram eter
Tem p
Level
Min
Typ
Max
Min
Typ
Max
Units
ENCODE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Encode Pulse Width High (tEH
Full
Full
Full
Full
+25°C
+25°C
+25°C
IV
IV
IV
IV
V
2.0
2.0
V
V
0.8
1
1
0.8
1
1
µA
µA
pF
ns
ns
10
10
)
IV
IV
10
10
166
166
6.7
6.7
166
166
Encode Pulse Width Low (tEL
)
DIGIT AL OUT PUT S
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Voltage (3.0 VDD
Logic “0” Voltage (3.0 VDD
Output Coding
Full
Full
Full
Full
IV
IV
IV
IV
4.95
2.95
4.95
2.95
V
V
V
V
0.05
0.05
0.05
0.05
)
)
Offset Binary Code
Offset Binary Code
POWER SUPPLY
VD, VDD Supply Current5
Full
Full
IV
IV
40
63
315
80
400
40
69
345
87.2
486
mA
mW
Power Dissipation5
Power Supply Rejection Ratio
(PSRR)6
+25°C
I
±10
±10
mV/V
NOT ES
1“Gain T empco” is for converter only; “T emperature Coefficient” is for bandgap reference only.
2Output propagation delay (tPD) is measured from the 50% point of the rising edge of the encode command to the midpoint of the digital outputs with 10 pF maximum
loads.
3RMS signal to rms noise with analog input signal 0.5 dB below full scale at specified frequency for BR/BRS, 1.0 dB below full scale for BRS-60.
4Intermodulation measured relative to either tone with analog input frequencies of 9.5 MHz and 9.9 MHz at 7 dB below full scale.
5Power dissipation is measured at full update rate with AIN of 10.3 MHz and digital outputs loaded with 10 pF maximum. See Figure 4 for power dissipation at other
conditions.
6Measured as the ratio of the change in offset voltage for 5% change in +VD
Specifications subject to change without notice.
.
EXP LANATIO N O F TEST LEVELS
Test Level
ABSO LUTE MAXIMUM RATINGS*
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . –1.0 V to VD + 1.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD
VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating T emperature
I
–
–
100% Production T ested.
IV
Parameter is guaranteed by design and characteriza-
tion testing.
V
–
Parameter is a typical value only.
AD9050BR/BRS/BRS-60 . . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
O RD ERING GUID E
Tem perature Range P ackage O ption*
Model
AD9050BR
AD9050BRS
AD9050BRS-60
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
R-28
RS-28
RS-28
*R = Small Outline (SO); RS = Shrink Small Outline (SSOP).
REV. B
–3–
AD9050
Table I. AD 9050 D igital Coding (Single Ended Input AIN, AINB Bypassed to GND )
O R
D igital O utput
MSB . . . LSB
Analog Input
Voltage Level
(O ut of Range)
3.813
3.300
2.787
Positive Full Scale + 1 LSB
Midscale
Negative Full Scale – 1 LSB
1
0
1
1111111111
0111111111
0000000000
P IN FUNCTIO N D ESCRIP TIO NS
P in No
Nam e
Function
1, 7, 12, 21, 23
GND
Ground.
2, 8, 11
VD
Analog +5 V ± 5% power supply.
3
4
5
6
9
10
13
VREFOUT
VREFIN
COMP
REFBP
AINB
Internal bandgap voltage reference (nominally +2.5 V).
Input to reference amplifier. Voltage reference for ADC is connected here.
Internal compensation pin, 0.1 µF bypass connected here to VD (+5 V).
External connection for (0.1 µF) reference bypass capacitor.
Complementary analog input pin (Analog input bar).
Analog input pin.
AIN
ENCODE
Encode clock input to ADC. Internal T /H is placed in hold mode (ADC is encoding)
on rising edge of encode signal.
14
OR
Out of range signal. Logic “0” when analog input is in nominal range. Logic “1” when
analog input is out of nominal range.
15
D9 (MSB)
D8–D5
VDD
D4–D1
D0 (LSB)
Most significant bit of ADC output.
Digital output bits of ADC.
Digital output power supply (only used by digital outputs).
Digital output bits of ADC.
Least significant bit of ADC output.
16–19
20, 22
24–27
28
P IN CO NFIGURATIO N
D0 (LSB)
D1
GND
1
2
28
27
V
D
VREF
3
26 D2
OUT
VREF
D3
4
25
24
23
22
IN
COMP
D4
5
6
GND
REF
BP
AD9050
TOP VIEW
(Not to Scale)
GND
7
V
DD
8
V
D
21 GND
9
AINB
AIN
20
V
DD
19 D5
18 D6
17 D7
16 D8
10
11
12
13
14
V
D
GND
ENCODE
OR
D9 (MSB)
15
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9050 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
AD9050
N
N + 1
N + 2
N + 3
N + 4
N + 5
AIN
MIN
TYP
MAX
tA
APERTURE DELAY
PULSE WIDTH HIGH
PULSE WIDTH LOW
OUTPUT PROP DELAY
2.7ns
tA
tEH tEL
tEH
tEL
tPD
10ns*
10ns*
5.0ns
166ns
166ns
15.0ns
ENCODE
8.2ns
tPD
*FOR BR/BRS, SEE SPECIFICATION TABLE
DIGITAL
OUTPUTS
N – 5
N – 4
N – 3
N – 2
N – 1
N
Figure 2. Tim ing Diagram
V
(Pins 20, 22)
V
DD
+3V to +5V
D
V
D
INPUT
BUFFER
8k
8k
AINB (Pin 9)
AIN (Pin 10)
ENCODE
(Pin 13)
D0–D9, OR
16k 16k
Analog Input
Encode Input
Output Stage
V
D
V
D
A
V
VREF
OUT
VREF
IN
(Pin 4)
(Pin 3)
VREF
BF
(Pin 6)
VREF Output
Reference Circuit
Figure 3. Equivalent Circuits
REV. B
–5–
AD9050–Typical Performance Curves
350
60
59
58
57
56
55
54
53
52
51
50
340
ENCODE = 40 MSPS
IN = 10.3 MHz
330
A
5V
320
310
300
290
3V
280
270
260
250
10
20
30
40
50
60
0
0
20
40
60
80
– 20
–40
CLOCK RATE – MSPS
TEMPERATURE – °C
Figure 4. Power Dissipation vs. Clock Rate
Figure 7. SNR vs. Tem perature
80
0
–10
ENCODE = 40 MSPS
f1 IN = 9.5 MHz @ –7 dBFS
f2 IN = 9.9 MHz @ –7 dBFS
2f1–f2 = –65.4 dBc
74
–20
–30
HD 40
68
2f2–f1 = –65.0 dBc
–40
HD 60
–50
62
–60
SNR 40
56
–70
–80
SNR 60
50
44
38
–90
–100
–110
–120
0
2.5
5
7.5
10
12.5
15
17.5
20
1
10
ANALOG INPUT FREQUENCY – MHz
100
FREQUENCY – MHz
Figure 5. SNR/Distortion vs. Frequency
Figure 8. Two-Tone IMD
58
56
54
52
0.50
0.25
0.00
SNR
–0.25
–0.50
1
2
3
4
5
6
0.50
0.25
0.00
50
48
46
–0.25
–0.50
40
CLOCK RATE – MSPS
50
60
10
0
20
30
1
2
3
4
5
6
Figure 6. SNR vs. Clock Rate
Figure 9. Differential Gain/Differential Phase
–6–
REV. B
AD9050
60
54
48
0
SINAD_40
SINAD_60
AIN = 10.3 MHz
ENCODE = 40 MSPS
ANALOG IN = 2.3 MHz
SNR = 55.1 dB
SNR (W/O HAR) = 55.5 dB
2ND HARMONIC = 69.3 dB
3RD HARMONIC = 72.9 dB
–10
–20
–30
–40
–50
–60
–70
42
36
30
–80
–90
–100
–110
–120
0
2.5
5
7.5
10
12.5
15
17.5
20
25
40
45
50
DUTY CYCLE – %
55
60
65
FREQUENCY – MHz
Figure 10. FFT Plot 40 MSPS, 2.3 MHz
Figure 13. SNR vs. Clock Pulse Width
1.0
0
–10
–20
ENCODE = 60 MSPS
ANALOG IN = 10.3 MHz
SNR = 55.8 dB
SNR (W/O HAR) = 56.2 dB
2ND HARMONIC = 67.2 dB
3RD HARMONIC = 73.2 dB
0.5
0.0
–0.5
–1.0
–30
–40
–50
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–60
–70
–80
–90
–100
1
25
30
10
ANALOG INPUT FREQUENCY – MHz
0
5
10
15
20
100
1000
FREQUENCY – MHz
Figure 14. ADC Gain vs. AIN Frequency
Figure 11. FFT Plot 60 MSPS, 10.3 MHz
15.0
0
[1] - 5V DATA RISING EDGE
[2] - 5V DATA FALLING EDGE
[3] - 3V DATA RISING EDGE
[4] - 3V DATA FALLING EDGE
–10
ENCODE = 40 MSPS
ANALOG IN = 10.3 MHz
SNR = 54.6 dB
SNR (W/O HAR) = 55.2 dB
2ND HARMONIC = 66.4 dB
3RD HARMONIC = 70.5 dB
14.0
13.0
12.0
11.0
10.0
9.0
–20
–30
[3]
[1]
[4]
–40
–50
–60
[2]
–70
–80
8.0
–90
7.0
–100
–110
–120
6.0
5.0
–40
– 20
0
20
40
60
80
100
0
2.5
5
7.5
10
12.5
15
17.5
20
FREQUENCY – MHz
TEMPERATURE – °C
Figure 15. tPD vs. Tem perature 3 V/5 V
Figure 12. FFT Plot 40 MSPS, 10.3 MHz
REV. B
–7–
AD9050
1kΩ
TH EO RY O F O P ERATIO N
Refer to the block diagram on the front page.
+5V
+5V
1kΩ
T he AD9050 employs a subranging architecture with digital
error correction. T his combination of design techniques en-
sures true 10-bit accuracy at the digital outputs of the converter.
V
IN
–0.5V to +0.5V
10
9
AD9050
AD8041
At the input, the analog signal is buffered by a high speed differ-
ential buffer and applied to a track-and-hold (T /H) that holds
the analog value present when the unit is strobed with an
ENCODE command. T he conversion process begins on the
rising edge of this pulse. T he two stage architecture completes a
coarse and then a fine conversion of the T /H output signal.
0.1µF
+5V
AD820
1kΩ
1kΩ
0.1µF
Figure 16. Single Supply, Single Ended, DC Coupled
AD9050
Error correction and decode logic correct and align data from
the two conversions and present the result as a 10-bit parallel
digital word. Output data are strobed on the rising edge of the
ENCODE command. T he subranging architecture results in
five pipeline delays for the output data. Refer to the AD9050
T iming Diagram.
1kΩ
+5V
+5V
1kΩ
0.1µF
V
IN
–0.5V to +0.5V
10
9
AD9050
AD8011
USING TH E AD 9050
3 V System
–5V
0.1µF
The digital input and outputs of the AD9050 can be easily
configured to directly interface to 3 V logic systems. T he en-
code input (Pin 13) is T T L compatible with a logic threshold of
1.5 V. T his input is actually a CMOS stage (refer to Equivalent
Encode Input Stage) with a T T L threshold, allowing operation
with T T L, CMOS and 3 V CMOS logic families. Using 3 V
CMOS logic allows the user to drive the encode directly without
the need to translate to +5 V. T his saves the user power and
board space. As with all high speed data converters, the clock
signal must be clean and jitter free to prevent the degradation of
dynamic performance.
Figure 17. Single Ended, Capacitively Coupled AD9050
1kΩ
+5V
+5V
1kΩ
V
0.1µF
AD8011
IN
–0.5V to +0.5V
T1-1T
10
9
AD9050
50Ω
–5V
T he AD9050 outputs can also directly interface to 3 V logic
systems. T he digital outputs are standard CMOS stages (refer
to AD9050 Output Stage) with isolated supply pins (Pins 20, 22
Figure 18. Differentially Driven AD9050 Using Trans-
form er Coupling
V
DD). By varying the voltage on the VDD pins, the digital output
T he AD830 provides a unique method of providing dc level shift
for the analog input. Using the AD830 allows a great deal of
flexibility for adjusting offset and gain. Figure 19 shows the
AD830 configured to drive the AD9050. T he offset is provided
by the internal biasing of the AD9050 differential input (Pin 9).
For more information regarding the AD830, see the AD830
data sheet.
levels vary respectively. By connecting Pins 20 and 22 to the
3 V logic supply, the AD9050 will supply 3 V output levels.
Care should be taken to filter and isolate the output supply of
the AD9050 as noise could be coupled into the ADC, limiting
performance.
Analog Input
T he analog input of the AD9050 is a differential input buffer
(refer to AD9050 Equivalent Analog Input). T he differential
inputs are internally biased at +3.3 V, obviating the need for
external biasing. Excellent performance is achieved whether the
analog inputs are driven single-ended or differential (for best
dynamic performance, impedances at AIN and AINB should
match).
V
IN
+5V
+15V
AD830
–5V
–0.5V to +0.5V
1
2
3
4
7
10
9
AD9050
0.1µF
Figure 16 shows typical connections for the analog inputs when
using the AD9050 in a dc coupled system with single ended
signals. All components are powered from a single +5 V supply.
T he AD820 is used to offset the ground referenced input signal
to the level required by the AD9050.
Figure 19. Level Shifting with the AD830
AC coupling of the analog inputs of the AD9050 is easily ac-
complished. Figure 17 shows capacitive coupling of a single
ended signal while Figure 18 shows transformer coupling differ-
entially into the AD9050.
–8–
REV. B
AD9050
O ver dr ive of the Analog Input
P ower D issipation
Special care was taken in the design of the analog input section
of the AD9050 to prevent damage and corruption of data when
the input is overdriven. T he nominal input range is +2.788 V to
3.812 V (1.024 V p-p centered at 3.3 V). Out-of-range com-
parators detect when the analog input signal is out of this range
and shut the T /H off. T he digital outputs are locked at their
maximum or minimum value (i.e., all “0” or all “1”). T his pre-
cludes the digital outputs from changing to an invalid value
when the analog input is out of range.
T he power dissipation specification in the parameter table is
measured under the following conditions: encode is 40 MSPS
or 60 MSPS, analog input is –0.5 dBFS at 10.3 MHz, the digi-
tal outputs are loaded with approximately 7 pF (10 pF maxi-
mum) and VDD is 5 V. These conditions intend to reflect actual
usage of the device.
As shown in Figure 4, the actual power dissipation varies based
on these conditions. For instance, reducing the clock rate will
reduce power as expected for CMOS-type devices. Also the
loading determines the power dissipated in the output stages.
From an ac standpoint, the capacitive loading will be the key
(refer to Equivalent Output Stage).
When the analog input signal returns to the nominal range, the
out-of-range comparators switch the T /H back to the active
mode and the device recovers in approximately 10 ns.
T he input is protected to one volt outside the power supply
rails. For nominal power (+5 V and ground), the analog input
will not be damaged with signals from +6.0 V to –1.0 V.
T he analog input frequency and amplitude in conjunction with
the clock rate determine the switching rate of the output data
bits. Power dissipation increases as more data bits switch at
faster rates. For instance, if the input is a dc signal that is out of
range, no output bits will switch. T his minimizes power in the
output stages, but is not realistic from a usage standpoint.
Tim ing
T he performance of the AD9050 is very insensitive to the duty
cycle of the clock. Pulse width variations of as much as ±10%
will cause no degradation in performance. (see Figure 13, SNR
vs. Clock Pulse Width).
T he dissipation in the output stages can be minimized by inter-
facing the outputs to 3 V logic (refer to USING T HE AD9050,
3 V System). T he lower output swings minimize consumption.
Refer to Figure 4 for performance characteristics.
T he AD9050 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (tPD
after the rising edge of the encode command (refer to the
)
Voltage Refer ence
AD9050 T iming Diagram). T he length of the output data lines
and loads placed on them should be minimized to reduce tran-
sients within the AD9050; these transients can detract from the
converter’s dynamic performance.
A stable and accurate +2.5 V voltage reference is built into the
AD9050 (Pin 3, VREF Output). In normal operation the internal
reference is used by strapping Pins 3 and 4 of the AD9050 to-
gether. T he internal reference has 500 µA of extra drive current
that can be used for other circuits.
T he minimum guaranteed conversion rate of the AD9050 is
3 MSPS. Below a nominal of 1.5 MSPS the internal T /H
switches to a track function only. T his precludes the T /H from
drooping to the rail during the conversion process and mini-
mizes saturation issues. At clock rates below 3 MSPS dynamic
performance degrades. T he AD9050 will operate in burst mode
operation, but the user must flush the internal pipeline each
time the clock stops. T his requires five clock pulses each time
the clock is restarted for the first valid data output (refer to Fig-
ure 2 T iming Diagram).
Some applications may require greater accuracy, improved tem-
perature performance, or adjustment of the gain of the AD9050,
which cannot be obtained by using the internal reference. For
these applications, an external +2.5 V reference can be used to
connect to Pin 4 of the AD9050. T he VREFIN requires 5 µA of
drive current.
T he input range can be adjusted by varying the reference volt-
age applied to the AD9050. No appreciable degradation in per-
formance occurs when the reference is adjusted ±5%. T he
full-scale range of the ADC tracks reference voltage changes
linearly.
REV. B
–9–
AD9050
Figure 22. Evaluation Board Bottom Layer
Figure 20. Evaluation Board Top Layer
Figure 23. Silkscreen
Figure 21. Evaluation Board Ground Layer
–10–
REV. B
AD9050
U3
74AC574R
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
8D
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
U1
AD9050R
7D
6D
5D
4D
3D
2D
1D
R5
1k
15
16
17
18
19
24
25
26
27
28
20
22
D9/MSB
3
4
5
6
9
10
13
14
D8
D7
D6
D5
D4
D3
D2
D1
D0
VREF
VREF
J3
OUT
IN
HDR20
TP3
U2
AD9631Q
COMP
REF
R4
1k
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C9
BP
2
3
0.1µF
J2
AINB
AIN
ENC
OR
6
IN
IN
CK
11
OUT
OE
R3
50
1
+5V
+5V
TP1
U6:B
74AC00R
C1
0.1µF
4
5
6
C2
0.1µF
U4
74AC574R
TP2
+5V
J7
C3
0.1µF
9
12
13
14
15
16
17
18
19
8D
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
8
7
6
5
4
3
2
E1
7D
6D
5D
4D
3D
2D
1D
+5V
R1
50
3
OUT
4
2
GND
VCC
11
Y1
+5V
SW41
CK
+5V
OE
11
U6:A
1
74AC00R
3
12
13
1
2
U6:D
74AC00R
R2
2k
9
8
10
+5V
J6
U6:C
74AC00R
J1
+5V
+5V
+
C7
0.1µF
C5
10µF
C10
0.1µF
C12
0.1µF
C13
0.1µF
C14
0.1µF
C15
0.1µF
C16
0.1µF
C17
0.1µF
C22
0.1µF
C23
0.1µF
C24
0.1µF
J5
–5.2V
C6
10µF
C8
0.1µF
–5.2V
+
C20
0.1µF
Figure 24. Evaluation Board Schem atic
REV. B
–11–
AD9050
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-Lead SO IC
(R-28)
0.7125 (18.10)
0.6969 (17.70)
28
15
1
14
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
28-Lead SSO P
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
14
1
0.07 (1.79)
0.078 (1.98)
0.068 (1.73)
PIN 1
0.066 (1.67)
0.03 (0.762)
8°
0°
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.022 (0.558)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
–12–
REV. B
相关型号：
AD9051BRSRL-2V
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, MO-150AH, SSOP-28, Analog to Digital Converter
ADI
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