AD9051 [ADI]
10-Bit, 60 MSPS A/D Converter; 10位， 60 MSPS A / D转换器
| 型号： | AD9051 |
| 厂家： | 
ADI |
| 描述： | 10-Bit, 60 MSPS A/D Converter |
| 文件： | 总12页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 60 MSPS
A/D Converter
a
AD9051
FUNCTIONAL BLOCK DIAGRAM
FEATURES
60 MSPS Sampling Rate
9.3 Effective Number of Bits at fIN = 10.3 MHz
250 mW Total Power at 60 MSPS
Selectable Input Bandwidth of 50 MHz or 130 MHz
On-Chip T/H and Voltage Reference
Single +5 V Supply Voltage
BWSEL
+5V
GND
IN
OUT
+5V
REFERENCE
CIRCUITS
AD9051
AINB
AIN
T/H
ADC
+5 V or +3 V Logic I/O Compatible
Input Range and Output Coding Options Available
10
DECODE
LOGIC
DAC
ADC
SUM
AMP
APPLICATIONS
Medical Imaging
Digital Communications
Professional Video
Instrumentation
Set-Top Box
ENCODE
TIMING
A +2.5 V reference is included onboard, or the user can provide
an external reference voltage for gain control or matching of
multiple devices. Fabricated on a state-of-the-art BiCMOS
process, the AD9051 is packaged in a space saving surface
mount package (SSOP) and is specified over the industrial tem-
perature range (–40°C to +85°C).
GENERAL DESCRIPTION
The AD9051 is a complete 10-bit monolithic sampling analog-
to-digital converter (ADC) with an onboard track-and-hold and
reference. The unit is designed for low cost, high performance
applications and requires only +5 V and an encode clock to
achieve 60 MSPS sample rates with 10-bit resolution.
The encode clock is TTL compatible and the digital outputs are
CMOS; both can operate with +5 V/+3 V logic. The two-step
architecture used in the AD9051 is optimized to provide the
best dynamic performance available while maintaining low
power consumption.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
(VD = +5 V, VDD = +3 V; external reference = 2.50 V; ENCODE = 60 MSPS
unless otherwise noted)
AD9051–SPECIFICATIONS
Test
Level Min
AD9051BRS
Typ
AD9051BRS-2V
Parameter
Temp
Max
Min
Typ
Max
Units
RESOLUTION
10
10
Bits
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
I
V
I
0.75
0.90
0.75
0.90
1.50
1.50
0.75
0.90
0.75
0.90
1.50
1.50
LSB
LSB
LSB
LSB
Integral Nonlinearity
V
No Missing Codes
Gain Error1
+25°C
+25°C
Full
I
I
VI
V
GUARANTEED
GUARANTEED
±0.3
±2.5
±0.3
±3.0
% FS
% FS
ppm/°C
±5.0
±5.5
Gain Tempco1
Full
±10
±10
ANALOG INPUT
Input Voltage Range2
Input Offset Voltage
Input Resistance
+25°C
+25°C
+25°C
+25°C
+25°C
V
I
I
V
V
1.25
5.0
6.0
2.0
5.0
6.0
5
V p-p
LSB
kΩ
pF
MHz
–14
4.0
26
–14
4.0
26
Input Capacitance
5
Analog Bandwidth (BW SEL +VD/NC)3
50/130
50/130
BANDGAP REFERENCE
Output Voltage (IO @ 200 µA)
Temperature Coefficient
Power Supply Sensitivity
Reference Input Current (VIN = 2.50 V)
Full
Full
Full
Full
VI
V
V
2.4
2.5
±33
6.2
2.0
2.6
25
2.4
2.5
±33
6.2
2.0
2.6
25
V
ppm/°C
mV/V
µA
VI
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate4
Aperture Delay (tA)
Full
Full
+25°C
+25°C
Full
VI
IV
V
V
VI
VI
60
60
MSPS
MSPS
ns
ps, rms
ns
2.0
2.5
5
5.0
10
2.0
2.5
5
5.0
10
Aperture Uncertainty (Jitter)
Output Valid Time (tV)5
4.0
4.0
5
Output Propagation Delay (tPD
)
Full
5.5
5.5
ns
DYNAMIC PERFORMANCE6
Transient Response
Overvoltage Recovery Time
ENOBS
+25°C
+25°C
V
V
10
10
10
10
ns
ns
fIN = 1.20 MHz
+25°C
+25°C
+25°C
V
I
V
9.6
9.3
9.1
9.6
9.3
9.1
ENOB
ENOB
ENOB
f
IN = 10.3 MHz
8.93
55
8.93
54
fIN = 29.0 MHz
Signal-to-Noise Ratio (SINAD)
fIN = 1.20 MHz
fIN = 10.3 MHz
fIN = 29.0 MHz
+25°C
+25°C
+25°C
V
I
V
58.5
57
55
57.5
56
54
dB
dB
dB
Signal-to-Noise Ratio (Without Harmonics)
fIN = 1.20 MHz
fIN = 10.3 MHz
+25°C
+25°C
+25°C
V
I
V
59
58
56.5
59
58
56.5
dB
dB
dB
56
56
f
IN = 29.0 MHz
2nd Harmonic Distortion
fIN = 1.20 MHz
+25°C
+25°C
+25°C
V
I
V
–74
–73
–67
–68
–64
–60
dBc
dBc
dBc
f
IN = 10.3 MHz
–60
–60
–58
–60
fIN = 29.0 MHz
3rd Harmonic Distortion
fIN = 1.20 MHz
fIN = 10.3 MHz
fIN = 29.0 MHz
+25°C
+25°C
+25°C
V
I
V
–74
–70
–65
–69
–65
–60
dBc
dBc
dBc
Two-Tone Intermodulation
Distortion (IMD)
Differential Phase
Differential Gain
+25°C
+25°C
+25°C
V
V
V
–65
0.1
0.5
–65
0.1
0.5
dBc
Degrees
%
–2–
REV. A
AD9051
Test
Level Min
AD9051BRS
Typ
AD9051BRS-2V
Parameter
Temp
Max
Min
Typ
Max
Units
ENCODE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Encode Pulsewidth High (tEH
Full
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
VI
V
2.0
2.0
V
V
0.8
1
1
0.8
1
1
µA
µA
pF
ns
ns
7.5
7.5
)
)
IV
IV
7.5
7.5
7.5
7.5
Encode Pulsewidth Low (tEL
DIGITAL OUTPUTS
Logic “1” Voltage (5.0 VDD
Logic “0” Voltage (5.0 VDD
Logic “1” Voltage (3.0 VDD
Logic “0” Voltage (3.0 VDD
Output Coding7
)
)
)
)
Full
Full
Full
Full
VI
VI
VI
VI
4.95
2.95
4.95
2.95
V
V
V
V
0.05
0.05
0.05
0.05
Offset Binary
Offset Binary
POWER SUPPLY
VD, VDD Supply Current
Full
Full
VI
VI
50
250
63
315
50
250
63
315
mA
mW
Power Dissipation8
Power Supply Rejection Ratio
(PSRR)9
+25°C
I
±2
±10
±7
±15
mV/V
NOTES
1Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).
2Contact factory or authorized sales agent for information concerning the availability of expanded input voltage range devices.
33 dB bandwidth with full-power input signal.
4Minimum conversion rate at which all data sheet specifications remain stable.
5tV and tPD are measured from the threshold crossing of the ENCODE input to valid TTL levels 0.5 V and 2.4 V of the digital outputs with V DD = 3.0 V. The output
ac load during test is 5 pF.
6SNR/harmonics tested with an analog input voltage of –0.5 dBfs. All tests performed at 60 MSPS.
7Contact factory or authorized sales agent for information concerning the availability of alternative output coding and input range devices.
8Power dissipation is measured under the following conditions: analog input = –FS at 60 MSPS ENCODE.
9A change in input offset voltage with respect to a change in VD.
Specifications subject to change without notice.
REV. A
–3–
AD9051
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD
VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . .+175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . .+150°C
II. 100% production tested at +25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
VI. 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature range.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Options
AD9051BRS
AD9051BRS-2V
AD9051/PCB
–40°C to +85°C
–40°C to +85°C
+25°C
28-Lead Shrink Small Outline Package (SSOP)
28-Lead Shrink Small Outline Package (SSOP)
RS-28
RS-28
Evaluation Board
AD9051-2V/PCB
+25°C
Evaluation Board
Table I. Digital Coding (Single-Ended Input with AIN, AINB Bypassed to GND)
OR
Digital Output
MSB . . . LSB
Analog Input
Voltage Level
(Out of Range)
3.126 (3.50)*
2.5
1.874 (1.50)*
Positive Full Scale + 1 LSB
Midscale
Negative Full Scale – 1 LSB
1
0
1
1111111111
0111111111
0000000000
*(BRS-2V Version)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9051 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
AD9051
PIN FUNCTION DESCRIPTIONS
Function
Pin No.
Name
1, 6, 7, 12, 21, 23
GND
Ground.
2, 8, 11
VD
Analog +5 V power supply.
3
4
5
9
10
13
VREFOUT
VREFIN
BWSEL
AINB
AIN
ENCODE
Internal bandgap voltage reference (nominally +2.5 V).
Input to reference amplifier. Voltage reference for ADC is connected here.
Bandwidth Select. NC = 130 MHz nominal. +VD = 50 MHz nominal.
Complementary analog input pin (Analog input bar).
Analog input pin.
Encode clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding)
on rising edge of encode signal.
14
OR
Out of range signal. Logic “0” when analog input is in nominal range. Logic “1” when
analog input is out of nominal range.
15
D9 (MSB)
D8–D5
VDD
D4–D1
D0 (LSB)
Most significant bit of ADC output.
Digital output bits of ADC.
Digital output power supply (only used by digital outputs).
Digital output bits of ADC.
Least significant bit of ADC output.
16–19
20, 22
24–27
28
N
N + 1
N + 2
N + 3
N + 4
N + 5
PIN CONFIGURATION
AIN
1
2
3
4
5
6
7
D0 (LSB)
28
27
26
25
24
GND
tA
D1
D2
D3
D4
V
D
VREFOUT
VREFIN
BWSEL
GND
ENCODE
tEH tEL
tPD
DIGITAL
OUTPUTS
N – 5
N – 4
N – 3
N – 2
N – 1
N
V
23 GND
V
AD9051
TOP VIEW
(Not to Scale)
GND
22
21
20
19
18
17
DD
8
9
V
D
GND
Figure 1. Timing Diagram
AINB
AIN
V
DD
10
11
D5
D6
V
D
D
V
D
GND 12
D7
12k⍀
12k⍀
INPUT
BUFFER
13
14
16
15
ENCODE
OR
D8
ENCODE
(PIN 13)
AINB (PIN 9)
AIN (PIN 10)
D9 (MSB)
12k⍀ 12k⍀
Analog Input
Encode
V
(PINS 20, 22)
+3V TO +5V
DD
V
D
D0–D9, OR
VREF
OUT
(PIN 3)
Output Stage
Figure 2. Equivalent Circuits
VREF
REV. A
–5–
AD9051–Typical Performance Characteristics
255
250
245
240
235
230
225
220
215
210
0
–1
–2
–3
–4
–5
–6
BWSEL DISABLED
BWSEL ENABLED
1
5
15
20
25
30
35
40
45
50
55
60
1
40
52
80
118
141
201
CLOCK RATE – MSPS
ANALOG INPUT FREQUENCY – MHz
Figure 6. ADC Gain vs. AIN Frequency
Figure 3. Power Dissipation vs. Clock Rate
59
60
AIN = 10.3MHz
59
58.5
58
SNR @ 40MSPS
ENCODE = 40MSPS
58
57
SINAD @ 40MSPS
57.5
57
56
ENCODE = 60MSPS
55
SINAD @ 60MSPS
54
56.5
56
SNR @ 60MSPS
53
52
51
55.5
55
–40
50
0
–20
0
25
45
65
85
10
20
30
40
50
60
70
80
90
TEMPERATURE – ؇C
FREQUENCY – MHz
Figure 7. SNR vs. Temperature
Figure 4. SNR/SINAD vs. AIN Frequency
60
59
58
57
56
55
54
53
52
51
50
–50
AIN = 10.3MHz
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
2ND @ 60MSPS
3RD @ 40MSPS
2ND @ 40MSPS
3RD @ 60MSPS
0
10
20
30
40
50
60
70
80
90
5
10
20
30
40
50
60
70
ENCODE – MSPS
FREQUENCY – MHz
Figure 5. Harmonics vs. AIN Frequency
Figure 8. SNR vs. Clock Rate
–6–
REV. A
AD9051
0
0
AIN = 15.2MHz
ENCODE = 60 MSPS
SNR = 58.29dB
–10
AIN = 10.3MHz
ENCODE = 40 MSPS
SNR = 58.6dB
–10
–20
–30
–40
–50
–60
–20
–30
–40
SINAD = 57.23dB
SINAD = 57.69dB
–50
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
3.8
7.5
11.3
15.0
18.8
22.5
26.3
30
30
30
0
2.5
5.0
7.5
10
12.5
15
17.5
20
20
30
FREQUENCY – MHz
FREQUENCY – MHz
Figure 9. FFT Plot 40 MSPS, 10.3 MHz
Figure 12. FFT Plot 60 MSPS, 15.2 MHz
0
0
AIN = 21.7MHz
ENCODE = 60 MSPS
SNR = 57.76dB
–10
AIN = 15.2MHz
ENCODE = 40 MSPS
SNR = 58.47dB
–10
–20
–30
–40
–50
–60
–20
–30
–40
SINAD = 56.27dB
SINAD = 57.04dB
–50
–60
–70
–80
–70
–80
–90
–90
–100
–100
0
2.5
5.0
7.5
10
12.5
15
17.5
0
3.8
7.5
11.3
15.0
18.8
22.5
26.3
FREQUENCY – MHz
FREQUENCY – MHz
Figure 13. FFT Plot 60 MSPS, 21.7 MHz
Figure 10. FFT Plot 40 MSPS, 15.2 MHz
0
0
AIN = 10.3MHz
ENCODE = 60 MSPS
SNR = 58.15dB
AIN1 = 9.5MHz, –7dBFS
AIN2 = 9.9MHz, –7dBFS
IMD = –65dBc
–10
–20
–30
–40
–50
–60
–10
–20
–30
SINAD = 57.25dB
ENCODE = 60 MSPS
–40
–50
–60
–70
–80
–70
–80
–90
–90
–100
–100
0
3.8
7.5
11.3
15.0
18.8
22.5
26.3
0
3.8
7.5
11.3
15.0
18.8
22.5
26.3
FREQUENCY – MHz
FREQUENCY – MHz
Figure 11. FFT Plot 60 MSPS, 10.3 MHz
Figure 14. Two-Tone IMD
REV. A
–7–
AD9051
1.2
6.5
6
3V RISING
1.0
0.8
0.6
0.4
0.2
5.5
5
5V FALLING
3V FALLING
5V RISING
4.5
0
0
4
–40
10
20
30
40
50
60
–20
0
25
45
65
85
ENCODE – MSPS
TEMPERATURE – ؇C
Figure 15. Gain vs. Clock Rate
Figure 18. tPD vs. Temperature +3 V/+5 V
16
2.51
2.50
2.49
2.48
2.47
2.46
2.45
2.44
2.43
2.42
14
12
10
8
V
OUT
6
4
2
0
0
10
20
30
40
50
60
0.1
0.55 0.7 0.85
1
1.15 1.3 1.45 1.6 1.75 1.9 2.0
0.25 0.4
ENCODE – MSPS
SOURCE CURRENT – mA
Figure 16. Offset vs. Clock Rate
Figure 19. Reference Load Regulation
60
58
56
54
80
70
60
50
40
30
20
10
0
SNR @ 40MSPS
SNR @ 60MSPS
52
50
48
46
44
42
40
25
30
35
40
45
50
55
60
65
70
75
512
513
514
515
516
517
518
CODE
DUTY CYCLE – %
Figure 17. SNR vs. Duty Cycle
Figure 20. Midscale Histogram (Inputs Tied)
–8–
REV. A
AD9051
THEORY OF OPERATION
140⍀
Refer to the block diagram on the front page.
+5V
+5V
140⍀
The AD9051 employs a subranging architecture with digital
error correction. This combination of design techniques ensures
true 10-bit accuracy at the digital outputs of the converter.
V
IN
10
9
–0.625V
TO
+0.625V
AD9631
AD9051
At the input, the analog signal is buffered by a high speed differ-
ential buffer and applied to a track-and-hold (T/H) that holds
the analog value present when the unit is strobed with an
ENCODE command. The conversion process begins on the
rising edge of this pulse. The two stage architecture completes a
coarse and then a fine conversion of the T/H output signal.
0.1F
1k⍀
+5V
AD820
1k⍀
0.1F
Error correction and decode logic correct and align data from
the two conversions and present the result as a 10-bit parallel
digital word. Output data are strobed on the rising edge of the
ENCODE command. The subranging architecture results in five
pipeline delays for the output data. Refer to the AD9051 Timing
Diagram.
Figure 21. Single Supply, Single-Ended, DC-Coupled
AD9051
140⍀
+5V
+5V
140⍀
0.1F
V
IN
10
9
–0.625V
TO
+0.625V
USING THE AD9051
3 V System
AD9051
AD9631
–5V
0.1F
The digital input and outputs of the AD9051 can be easily
configured to directly interface to 3 V logic systems. The encode
input (Pin 13) is TTL compatible with a logic threshold of
1.5 V. This input is actually a CMOS stage (refer to Equivalent
Encode Input Stage) with a TTL threshold, allowing operation
with TTL, CMOS and 3 V CMOS logic families. Using 3 V
CMOS logic allows the user to drive the encode directly without
the need to translate to +5 V. This saves the user power and
board space. As with all high speed data converters, the clock
signal must be clean and jitter free to prevent the degradation of
dynamic performance.
Figure 22. Single-Ended, Capacitively-Coupled AD9051
140⍀
+5V
+5V
140⍀
0.1F
V
IN
T1-1T
10
9
–0.625V
TO
+0.625V
AD9051
AD9631
50⍀
–5V
The AD9051 outputs can also directly interface to 3 V logic
systems. The digital outputs are standard CMOS stages (refer to
AD9051 Output Stage) with isolated supply pins (Pins 20, 22
VDD). By varying the voltage on the VDD pins, the digital output
levels vary respectively. By connecting Pins 20 and 22 to the
3 V logic supply, the AD9051 will supply 3 V output levels.
Care should be taken to filter and isolate the output supply of
the AD9051 as noise could be coupled into the ADC, limiting
performance.
Figure 23. Differentially Driven AD9051 Using Trans-
former Coupling
The AD830 provides a unique method of providing dc level
shift for the analog input. Using the AD830 allows a great deal
of flexibility for adjusting offset and gain. Figure 24 shows the
AD830 configured to drive the AD9051. The offset is provided
by the internal biasing of the AD9051 differential input (Pin 9).
For more information regarding the AD830, see the AD830
data sheet.
Analog Input
The analog input of the AD9051 is a differential input buffer
(refer to AD9051 Equivalent Analog Input). The differential
inputs are internally biased at +2.5 V, obviating the need for
external biasing. Excellent performance is achieved whether the
analog inputs are driven single-endedly or differentially (for best
dynamic performance, impedances at AIN and AINB should
match).
+5V
+15V
AD830
–5V
1
V
IN
2
3
4
7
10
–0.625V
TO
+0.625V
AD9051
9
0.1F
Figure 21 shows typical connections for the analog inputs when
using the AD9051 in a dc coupled system with single-ended
signals. All components are powered from a single +5 V supply.
The AD820 is used to offset the ground referenced input signal
to the level required by the AD9051.
Figure 24. Level-Shifting with the AD830
AC coupling of the analog inputs of the AD9051 is easily accom-
plished. Figure 22 shows capacitive coupling of a single-ended
signal while Figure 23 shows transformer coupling differentially
into the AD9051.
REV. A
–9–
AD9051
Overdrive of the Analog Input
The input range can be adjusted by varying the reference volt-
age applied to the AD9051. No appreciable degradation in
performance occurs when the reference is adjusted ±5%. The
full-scale range of the ADC tracks reference voltage changes
linearly.
Special care was taken in the design of the analog input section
of the AD9051 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is +1.875 V
to 3.125 V (1.25 V p-p centered at 2.5 V). Out-of-range com-
parators detect when the analog input signal is out of this range
and the input buffer is clamped. The digital outputs are locked
at their maximum or minimum value (i.e., all “0” or all “1”).
This precludes the digital outputs changing to an invalid value
when the analog input is out of range.
EVALUATION BOARD
The AD9051 evaluation board is a convenient and easy way to
evaluate the performance of the AD9051.
Analog Input
The input is protected to one volt outside the power supply
rails. For nominal power (+5 V and ground), the analog input
will not be damaged with signals from +5.5 V to –0.5 V.
The evaluation board requires a 1.25 V p-p input. The signal is
buffered by an AD9631 op amp in the unity gain configuration.
The signal is then ac coupled before entering the AD9051
where a dc offset is internally generated. Leave E3 unconnected
to E4 for usage with the AD9631. To evaluate performance
without this buffer, remove the AD9631 and connect E3 to E4.
Keep E1 connected to E2 for use in the low bandwidth mode
(50 MHz). Removing this connector will enable high band-
width mode (130 MHz). Low bandwidth is the recommended
mode of operation in order to minimize any high frequency
noise coupling into the input of the AD9051.
Timing
The performance of the AD9051 is very insensitive to the duty
cycle of the clock. Pulsewidth variations of as much as ±15%
for encode rates of 40 MSPS and ±10% for encode rates of
60 MSPS will cause no degradation in performance. (See Fig-
ure 17, SNR vs. Duty Cycle.)
The AD9051 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (tPD
after the rising edge of the encode command (refer to Fig-
ure 1, Timing Diagram). The length of the output data lines
)
Encode
The evaluation board is driven with a TTL or CMOS clock
into a clock buffer of ac type CMOS logic. This buffer will
drive the encode to the AD9051, the data latches, and a “data
ready.”
and loads placed on them should be minimized to reduce tran-
sients within the AD9051; these transients can detract from the
converter’s dynamic performance.
Data Out
Power Dissipation
The digital data is captured by a pair 74ACQ574 latches. Any
unused connector pins should be grounded to the device that is
capturing data from the evaluation board. This minimizes any
grounding loops that may degrade performance. A separate
power plane is provided for supplying the latches, clock buffer,
and digital outputs of the AD9051. This supply can be 3 V or
5 V.
The power dissipation specification in the parameter table is
measured under the following conditions: encode is 60 MSPS,
analog input is –FS.
As shown in Figure 3, the actual power dissipation varies based
on these conditions. For instance, reducing the clock rate will
reduce power as expected for CMOS-type devices. The loading
determines the power dissipated in the output stages.
Layout
The analog input frequency and amplitude in conjunction with
the clock rate determine the switching rate of the output data
bits. Power dissipation increases as more data bits switch at
faster rates. For instance, if the input is a dc signal that is out of
range, no output bits will switch. This minimizes power in the
output stages, but is not realistic from a usage standpoint.
The AD9051 is not layout sensitive if some important guide-
lines are met. The evaluation board layout provides an ex-
ample where these guidelines have been followed to optimize
performance.
• Provide a solid ground plane connecting both analog and
digital sections. Cuts in this plane near the AD9051 should
be kept to a minimum.
The dissipation in the output stages can be minimized by inter-
facing the outputs to 3 V logic (refer to Using the AD9051, 3 V
System). The lower output swings minimize power consump-
• Excellent bypassing is essential. All capacitors should be
placed as close as possible to the AD9051. No vias should
be used to connect capacitors to the AD9051 as this may
create a parasitic inductance that can reduce bypassing
effectiveness.
2
tion as follows: (1/2 CLOAD × VDD × Update Rate).
Voltage Reference
A stable and accurate +2.5 V voltage reference is built into the
AD9051 (Pin 3, VREFOUT). In normal operation the internal
reference is used by strapping together Pins 3 and 4 of the
AD9051. The internal reference has 500 µA of extra drive cur-
rent that can be used for other circuits.
The AD9051 evaluation board is provided as a design example
for customers of Analog Devices. ADI makes no warranties
express, statutory, or implied regarding merchantability of
fitness for a particular purpose.
Some applications may require greater accuracy, improved
temperature performance, or adjustment of the gain of the
AD9051, which cannot be obtained by using the internal refer-
ence. For these applications, an external +2.5 V reference can
be used to connect to Pin 4 of the AD9051. The VREFIN
requires 2 µA of drive current.
–10–
REV. A
AD9051
Figure 25. Evaluation Board Top Layer
Figure 27. Evaluation Board Bottom Layer
Figure 28. Silkscreen
Figure 26. Evaluation Board Ground Layer
REV. A
–11–
AD9051
GND
V
+5VA
–5V
DD
C17
0.1F
V
C12
1F
C10
0.1F
C11
0.1F
C14
1F
C13
0.1F
C15
1F
DD
74ACQ574
AD9051
1
2
20
19
18
17
16
15
14
13
12
11
GND
OUT_EN VCC
28
27
26
1
2
GND1 (LSB) D0
D0
D1
D2
D3
D4
D5
D6
D7
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
C1
0.1F
3
4
P6
D1
D2
+5VA1
+5VA
GND
P1
1
2
3
4
5
5
C2
0.1F
1
2
3
4
5
+5VA
GND
–5V
3
VREFOUT
VREFIN
BWSEL
6
1
2
3
4
5
6
7
8
9
U4
7
D3
4
25
24
23
22
21
20
19
18
8
GND
E2 E1
9
+5VA
5
D4
V
DD
10
U1
CLOCK
GND
6
GND2
GND
GND
+5VA
GND5
C8
0.1F
7
GND3
+5A2
AINB
AIN
V
V
DD
DD1
C3
0.1F
GND
C16
0.1F
8
GND6
GND
C5
E3 E4
R3
R1
25⍀
C9
0.1F
0.1F
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
DD
9
V
V
DD2
DD
140⍀
74ACQ574
10
11
12
D5
1
2
20
19
18
17
16
15
14
13
12
11
R2
25⍀
C6
0.1F
R4
140⍀
GND
OUT_EN VCC
+5VA
GND
+5A3
D6
D7
2
3
D0
D1
D2
D3
D4
D5
D6
D7
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
C7
0.1F
J1
6
3
U2
R5
50⍀
GND4
17
16
15
4
5
AD9631
13 ENCODE
14
D8
1
6
3
U5
U3
2
7
OR
(MSB) D9
74AC00
8
J1
9
4
R6
50⍀
6
GND
GND
5
U3
10
CLOCK
74AC00
9
8
10 U3
V
DD
74AC00
12
11
U3
13
74AC00
Figure 29. Evaluation Board Schematic
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SSOP
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
1
14
0.07 (1.79)
0.078 (1.98)
0.068 (1.73)
PIN 1
0.066 (1.67)
0.03 (0.762)
8°
0°
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.022 (0.558)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
REV. A
–12–
相关型号：
AD9051BRSRL-2V
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, MO-150AH, SSOP-28, Analog to Digital Converter
ADI
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