AD9054A/PCB_技术文档

8-Bit, 200 MSPS

A/D Converter

a

AD9054A

FEATURES

FUNCTIONAL BLOCK DIAGRAM

200 MSPS Guaranteed Conversion Rate

135 MSPS Low Cost Version Available

350 MHz Analog Bandwidth

1 V p-p Analog Input Range

Internal +2.5 V Reference and T/H

Low Power: 500 mW

VREF IN

VREF OUT

AD9054A

؉2.5V REFERENCE

AIN

8

T/H

QUANTIZER

DA –DA

ENCODE

LOGIC

DEMULTIPLEXER

7

0

AIN

+5 V Single Supply Operation

TTL Output Interface

ENCODE

DB –DB

7

0

TIMING

Single or Demultiplexed Output Ports

V

GND

DEMUX

DS

DD

APPLICATIONS

RGB Graphics Processing

High Resolution Video

Digital Data Storage Read Channels

Digital Communications

Digital Instrumentation

Medical Imaging

GENERAL DESCRIPTION

The AD9054A’s encode input interfaces directly to TTL, CMOS

or positive-ECL logic and will operate with single-ended or

differential inputs. The user may select dual-channel or single-

channel digital outputs. The dual (demultiplexed) mode inter-

leaves ADC data through two 8-bit channels at one-half the

clock rate. Operation in demultiplexed mode reduces the speed

and cost of external digital interfaces while allowing the ADC to

be clocked to the full 200 MSPS conversion rate. In the single-

channel (nondemultiplexed) mode, all data is piped at the full

clock rate to the Channel A outputs.

The AD9054A is an 8-bit monolithic analog-to-digital converter

optimized for high speed, low power, small size and ease of use.

With a 200 MSPS encode rate capability and full-power analog

bandwidth of 350 MHz, the component is ideal for applications

requiring the highest possible dynamic performance.

To minimize system cost and power dissipation, the AD9054A

includes an internal +2.5 V reference and track-and-hold circuit.

The user provides only a +5 V power supply and an encode clock.

No external reference or driver components are required for

many applications.

Fabricated with an advanced BiCMOS process, the AD9054A is

provided in a space-saving 44-lead LQFP surface mount plastic

package (ST-44) and specified over the full industrial (–40°C to

+85°C) temperature range.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

AD9054A–SPECIFICATIONS

(V_DD= +5 V, external reference, f_S= max unless otherwise noted)

ELECTRICAL CHARACTERISTICS

Test

AD9054ABST-200

AD9054ABST-135

Parameter

Temp

Level

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

8

Bits

DC ACCURACY

Differential Nonlinearity

+25°C

Full

+25°C

Full

+25°C

Full

I

VI

I

VI

I

0.9

1.0

0.6

+1.5/–1.0

+2.0/–1.0

1.5

0.9

1.0

0.6

0.9

+1.5/–1.0 LSB

+2.0/–1.0 LSB

Integral Nonlinearity

1.5

2.0

LSB

0.9

Guaranteed

2

2.0

No Missing Codes

Gain Error¹

Guaranteed

7

2

160

7

% FS

Gain Tempco¹

V

160

ppm/°C

ANALOG INPUT

Input Voltage Range

(With Respect to AIN)

Compliance Range AIN or AIN

Input Offset Voltage

Full

+25°C

Full

+25°C

Full

+25°C

Full

V

I

VI

I

VI

V

I

VI

V

512

mV p-p

V

mV

kΩ

1.8

3.2

16

19

1.8

3.2

16

19

4

8

62

4

8

62

Input Resistance

36

23

36

23

kΩ

pF

µA

Input Capacitance

Input Bias Current

4

25

50

75

25

50

75

Analog Bandwidth, Full Power²

+25°C

350

MHz

REFERENCE OUTPUT

Output Voltage

Temperature Coefficient

Full

VI

V

2.4

2.5

110

2.6

2.4

2.5

110

2.6

V

ppm/°C

SWITCHING PERFORMANCE

Maximum Conversion Rate (f_S)

Minimum Conversion Rate (f_S)

Full

VI

IV

V

200

135

MSPS

ns

ps rms

ns

25

22

25

22

Encode Pulsewidth High (t_EH

)

+25°C

Full

2.0

3.0

Encode Pulsewidth Low (t_EL

Aperture Delay (t_A)

)

0.5

2.3

0.5

2.3

Aperture Uncertainty (Jitter)

V

Data Sync Setup Time (t_SDS

Data Sync Hold Time (t_HDS

)

IV

VI

0

0.5

2.0

2.7

0.5

2.0

2.7

Data Sync Pulsewidth (t_PWDS

)

Output Valid Time (t_V)³

5.1

5.9

5.7

7.5

3

Output Propagation Delay (t_PD

)

Full

7.9

8.5

ns

DIGITAL INPUTS

4

HIGH Level Current (I_IH

)

Full

+25°C

VI

V

500

3

625

500

3

625

µA

pF

LOW Level Current (I_IL)⁴

Input Capacitance

DIFFERENTIAL INPUTS

Differential Signal Amplitude (V_ID

HIGH Input Voltage (V_IHD

LOW Input Voltage (V_ILD

)

Full

IV

400

1.5

0

400

1.5

0

mV

V

)

V_DD

V_DD– 0.4

V_DD

V_DD– 0.4

)

Common-Mode Input (V_ICM

)

1.5

V

DEMUX INPUT

HIGH Input Voltage (V_IH

LOW Input Voltage (V_IL)

)

Full

IV

2.0

0

V_DD

0.8

2.0

0

V_DD

0.8

V

DIGITAL OUTPUTS

HIGH Output Voltage (V_OH

)

Full

VI

2.4

V

LOW Output Voltage (V_OL

Output Coding

)

0.4

Binary

–2–

REV. B

AD9054A

Test

AD9054ABST-200

AD9054ABST-135

Parameter

Temp

Level

Min

Typ

Max

Min

Typ

Max

Unit

POWER SUPPLY

V

_DDSupply Current (I_DD

)

Full

+25°C

VI

I

128

640

0.005

145

725

0.015

120

600

0.005

140

700

0.015

mA

mW

V/V

Power Dissipation^{5, 6}

Power Supply Sensitivity⁷

DYNAMIC PERFORMANCE⁸

Transient Response

Overvoltage Recovery Time

Signal-to-Noise Ratio (SNR)

(Without Harmonics)

+25°C

V

1.5

ns

f_IN= 19.7 MHz

+25°C

Full

+25°C

Full

+25°C

Full

IV

V

I

V

I

42

45

42

45

dB

f

_IN= 49.7 MHz

f_IN= 70.1 MHz

V

Signal-to-Noise Ratio (SINAD)

(With Harmonics)

f_IN= 19.7 MHz

+25°C

Full

+25°C

Full

+25°C

Full

IV

V

I

V

I

40

39

43

42

40

43

dB

f_IN= 49.7 MHz

f_IN= 70.1 MHz

V

Effective Number of Bits

f_IN= 19.7 MHz

+25°C

IV

I

6.35

6.18

6.85

6.35

6.85

Bits

f

_IN= 49.7 MHz

f_IN= 70.1 MHz

2nd Harmonic Distortion

f_IN= 19.7 MHz

f_IN= 49.7 MHz

f_IN= 70.1 MHz

+25°C

IV

I

58

54

49

63

59

55

58

54

63

59

dBc

3rd Harmonic Distortion

f_IN= 19.7 MHz

f_IN= 49.7 MHz

+25°C

IV

I

48

43

56

54

50

48

56

54

dBc

f

_IN= 70.1 MHz

Two-Tone Intermod Distortion

(IMD)

f_IN= 19.7 MHz

f_IN= 49.7 MHz

f_IN= 70.1 MHz

+25°C

V

60

55

50

60

55

dBc

NOTES

¹Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).

²3 dB bandwidth with full-power input signal.

³t_Vand t_PDare measured from the threshold crossing of the ENCODE input to valid TTL levels of the digital outputs. The output ac load during test is 5 pF (Refer to

equivalent circuits Figures 5 and 6).

⁴I_IHand I_ILare valid for differential input voltages of less than 1.5 V. At higher differential voltages, the input current will increase to a maximum of 1.5 mA.

⁵Power dissipation is measured under the following conditions: analog input is –1 dBFS at 19.7 MHz.

⁶Typical thermal impedance for the ST-44 (LQFP) 44-lead package (in still air): θ_JC= 20°C/W, θ_CA= 35°C/W, θ_JA= 55°C/W.

⁷A change in input offset voltage with respect to a change in V_DD

.

⁸SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range.

Specifications subject to change without notice.

EXPLANATION OF TEST LEVELS

Test Level

I. 100% production tested.

IV. Parameter is guaranteed by design and characterization testing.

V. Parameter is a typical value only.

VI. 100% production tested at +25°C; guaranteed by design

II. 100% production tested at +25°C and sample tested at

and characterization testing for industrial temperature range.

specified temperatures.

III. Sample tested only.

REV. B

–3–

AD9054A

ABSOLUTE MAXIMUM RATINGS*

Table I. Output Coding

V_DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V

Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . V_DDto 0.0 V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . V_DDto 0.0 V

VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . V_DDto 0.0 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C

Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions outside of those indicated in the operation

sections of this specification is not implied. Exposure to absolute maximum ratings

for extended periods may affect device reliability.

Step

AIN–AIN

Code

Binary

255

254

253

•

129

128

127

126

•

≥0.512 V

0.508 V

0.504 V

•

255

254

253

•

129

128

127

126

•

1111 1111

1111 1110

1111 1101

•

0.006 V

0.002 V

–0.002 V

–0.006 V

•

1000 0001

1000 0000

0111 1111

0111 1110

•

2

1

•

2

1

•

–0.504 V

–0.508 V

≤–0.512 V

0000 0010

0000 0001

0000 0000

ORDERING GUIDE

0

Temperature

Range

Package

Option*

Model

AD9054ABST-200

AD9054ABST-135

AD9054A/PCB

–40°C to +85°C

+25°C

ST-44

Evaluation Board

*ST = Plastic Thin Quad Flatpack (LQFP).

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD9054A features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. B

AD9054A

PIN FUNCTION DESCRIPTIONS

PIN CONFIGURATION

Pin Number

Name

Function

1

ENCODE

Encode Clock for ADC (ADC

Samples on Rising Edge of

ENCODE).

DB

3

VREF IN

GND

2

ENCODE

Encode Clock Complement

(ADC Samples on Falling Edge

of ENCODE).

DB

2

1

VDD

GND

AIN

DB

DB (LSB)

0

3, 5, 15, 18, 28,

30, 31, 36, 41

VDD

GND

Power Supply (+5 V).

VDD

GND

VDD

AD9054A

TOP VIEW

(PINS DOWN)

AIN

GND

VDD

DEMUX

DS

4, 6, 16, 17, 27,

29, 32, 35, 37, 40

14–7

Ground.

DA (LSB)

0

DA₀–DA₇

DB₀–DB₇

Digital Outputs of ADC Channel

A. DA₇is the MSB, DA₀the LSB.

DA

1

PIN 1

IDENTIFIER

DS

DA

2

19–26

33

Digital Outputs of ADC Channel

B. DB₇is the MSB, DB₀the LSB.

VREF OUT Internal Reference Output

(+2.5 V typical); Bypass with

0.1 µF to Ground.

34

38

VREF IN

Reference Input for ADC (+2.5 V

typical, 4%).

AIN

Analog Input—Complement.

Connect to input signal midscale

reference.

39

42

AIN

Analog Input—True.

DEMUX

Format Select. LOW = Dual.

Channel Mode, HIGH = Single.

Channel Mode (Channel A Only).

43

44

DS

Data Sync Complement.

DS

Data Sync—Aligns output chan-

nels in Dual-Channel Mode.

SAMPLE N

SAMPLE N+3

SAMPLE N+4

SAMPLE N–1

AIN

SAMPLE N+1

SAMPLE N+2

t_A

1/f

t_EH

t_EL

S

ENCODE

t_PD

t_V

DATA N–1

DATA N

DATA N–5

DATA N–4

DATA N–3

DATA N–2

D –D

7

0

Figure 1. Timing—Single Channel Mode

REV. B

–5–

AD9054A

SAMPLE N

SAMPLE N+3

SAMPLE N+4

SAMPLE N+5

SAMPLE N–1

AIN

SAMPLE N–2

SAMPLE N+1

SAMPLE N+2

SAMPLE N+6

t_A

t_EH

t_EL

1/f

S

ENCODE

t_HDS

t_SDS

DS

t_PD

t_V

t_PWDS

PORT A

D –D

DATA N–7

OR N–8

INVALID IF OUT OF SYNC

DATA N–4 IF IN SYNC

DATA N–7

OR N–6

DATA N

DATA N–2

7

0

PORT B

D –D

DATA N–8

OR N–7

DATA N–6

OR N–7

INVALID IF OUT OF SYNC

DATA N–5 IF IN SYNC

DATA N+1

DATA N–3

DATA N–1

7

0

Figure 2a. Timing—Dual Channel Mode (One-Shot Data Sync)

SAMPLE N

SAMPLE N+5

SAMPLE N+3

SAMPLE N+4

SAMPLE N–1

AIN

SAMPLE N–2

SAMPLE N+1

SAMPLE N+2

SAMPLE N+6

t_A

t_EH

t_EL

1/f

S

ENCODE

t_HDS

t_SDS

t_HDS

DS

t_PWDS

t_PD

t_V

PORT A

DATA N–7

OR N–8

INVALID IF OUT OF SYNC

DATA N–4 IF IN SYNC

DATA N–7

OR N–6

DATA N

DATA N–2

D –D

7

0

PORT B

D –D

DATA N–8

OR N–7

DATA N–6

OR N–7

INVALID IF OUT OF SYNC

DATA N–5 IF IN SYNC

DATA N+1

DATA N–3

DATA N–1

7

0

Figure 2b. Timing—Dual Channel Mode (Continuous Data Sync)

–6–

REV. B

AD9054A

EQUIVALENT CIRCUITS

V

DD

V

DD

17.5k⍀

300⍀

DEMUX

AIN

7.5k⍀

Figure 3. Equivalent Analog Input Circuit

Figure 6. Equivalent DEMUX Input Circuit

V

DD

VREF IN

DIGITAL

OUTPUTS

Figure 4. Equivalent Reference Input Circuit

Figure 7. Equivalent Digital Output Circuit

V

DD

V

DD

17.5k⍀

300⍀

ENCODE

OR DS

ENCODE

OR DS

VREF

OUT

7.5k⍀

Figure 5. Equivalent ENCODE and Data Select Input Circuit

Figure 8. Equivalent Reference Output Circuit

REV. B

–7–

AD9054A

55

45.4

45.2

45.0

44.8

44.6

44.4

44.2

44.0

50

45

40

35

SNR

20MHz

70MHz

50MHz

SINAD

NYQUIST

FREQUENCY

(100MHz)

30

0

20

40

60

f

80

100

120

140

0

–45

25

– ؇C

70

90

– MHz

T

IN

C

Figure 9. SNR vs. f_IN: f_S= 200 MSPS

Figure 12. SNR vs. Temperature, f_S= 135 MSPS

46.0

45.8

45.6

50

49

48

47

46

45

44

43

42

41

40

20MHz

50MHz

70MHz

45.4

45.2

45.0

SNR

44.8

44.6

44.4

44.2

44.0

SINAD

–60

–40

–20

0

20

– ؇C

40

60

80

100

25 50

75 100 125 150 175 200 225 250 270 300

– MSPS

T

f

C

S

Figure 10. SNR vs. f_S: f_IN= 19.7 MHz

Figure 13. SNR vs. Temperature, f_S= 200 MSPS

50

f

= 135MSPS

= 10.3MHz

S

48

46

44

42

40

38

36

34

32

30

SNR

IN

45

40

35

30

SINAD

SNR

SINAD

25

20

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

50

75 100 125 150 175 200 225 250 270 300

– MSPS

25

ENCODE PULSEWIDTH – ns

f

S

Figure 11. SNR vs. f_S: f_IN= 70.1 MHz

Figure 14. SNR vs. Clock Pulsewidth, (t_PWH): f_S= 135 MSPS

–8–

REV. B

AD9054A

–70

–68

–66

–64

–62

–60

–58

50

48

46

44

42

40

38

f

= 200MSPS

= 10.3MHz

S

2ND HARMONIC

3RD HARMONIC

SNR

IN

SINAD

–56

–54

–52

36

34

32

30

–50

–48

–46

25 50

75 100 125 150 175 200 225 250 270 300

– MSPS

0.0 0.5 1.0 1.5 2.0 2.5

3.0 3.5 4.0 4.5

5.0

f

ENCODE PULSEWIDTH – ns

S

Figure 15. SNR vs. Clock Pulsewidth, (t_PWH): f_S= 200 MSPS

Figure 18. Harmonic Distortion vs. f_S: f_IN= 19.7 MHz

46

45

–60

2ND HARMONIC

–50

44

20MHz

–40

43

3RD HARMONIC

70MHz

–30

–20

42

41

50MHz

40

39

38

–10

0

25

50 75 100 125 150 175 200 225 250 270

300

–60

–40

–20

0

20

– ؇C

40

60

80

100

f_S– MSPS

T

C

Figure 16. SINAD vs. Temperature: f_S= 135 MSPS

Figure 19. Harmonic Distortion vs. f_S: f_IN= 70.1 MHz

–40

–45

–50

46

45

44

20MHz

43

50MHz

–55

42

70MHz

41

40

39

38

–60

50MHz

–65

20MHz

–70

–60

–40

–20

0

20

– ؇C

40

60

80

100

–60

–40

–20

0

20

– ؇C

40

60

80

100

T

C

Figure 20. 2nd Harmonic vs. Temperature: f_S= 135 MSPS

Figure 17. SINAD vs. Temperature: f_S= 200 MSPS

REV. B

–9–

AD9054A

–40

0

–1

–2

–3

–4

–5

–6

–45

–50

–55

–60

–65

70MHz

50MHz

20MHz

NYQUIST FREQUENCY

100MHz

–70

–60

–40

–20

0

20

– ؇C

40

60

80

100

0

50 100 150 200 250 300 350 400 450 500

f

– MHz

T

IN

C

Figure 21. 2nd Harmonic vs. Temperature: f_S= 200 MSPS

Figure 24. Frequency Response: f_S= 200 MSPS

–40

–45

–50

0

FUNDAMENTAL = –0.5dBFS

–10

–20

–30

–40

–50

–60

–70

–80

–90

SNR = 45.8dB

SINAD = 45.2dB

2ND HARMONIC = 69.8dB

3RD HARMONIC = 61.6dB

70MHz

50MHz

–55

20MHz

–60

–65

–70

–60

–40

–20

0

20

– ؇C

40

60

80

100

0

10

20

30

40

50

60

70

80

90

100

T

MHz

C

Figure 22. 3rd Harmonic vs. Temperature: f_S= 135 MSPS

Figure 25. Spectrum: f_S= 200 MSPS, f_IN= 19.7 MHz

–40

0

FUNDAMENTAL = –0.5dBFS

–10

–20

–30

–40

–50

–60

–70

–80

–90

SNR = 44.6dB

–45

SINAD = 37.6dB

2ND HARMONIC = –63.1dB

3RD HARMONIC = –39.1dB

70MHz

–50

50MHz

–55

20MHz

–60

–65

–70

–60

–40

–20

0

20

– ؇C

40

60

80

100

0

10

20

30

40

50

60

70

80

90 100

T

MHz

C

Figure 23. 3rd Harmonic vs. Temperature: f_S= 200 MSPS

Figure 26. Spectrum: f_S= 200 MSPS, f_IN= 70.1 MHz

–10–

REV. B

AD9054A

7

6

5

4

3

2

1

0

–10

–20

–30

–40

–50

–60

–70

–80

F1 = 55.0MHz

F2 = 56.0MHz

F1 = F2 = –7.0dBFS

t_PD

t_V

–90

0

–100

–60

–40

–20

0

20

– ؇C

40

60

80

100

0

10

20

30

40

50

MHz

60

70

80

90 100

T

C

Figure 30. Output Delay vs. Temperature

Figure 27. Two-Tone Intermodulation Distortion

2.55

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

2.54

2.53

2.52

2.51

2.50

2.49

2.48

2.47

2.46

2.45

0.0

–20 –18 –16 –14 –12 –10 –8

–6

–4 –2

0

2

0.0 –1.0 –2.0 –3.0 –4.0 –5.0 –6.0 –7.0 –8.0 –9.0 –10.0

IREF OUT – mA

I

– mA

OH

Figure 31. Reference Voltage vs. Reference Load

Figure 28. Output Voltage HIGH vs. Output Current

2.502

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

2.501

2.500

2.499

2.498

0.1

0.0

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

0.0

1.0

2.0

3.0

4.0

– mA

5.0

6.0

7.0

8.0

V

– Volts

DD

I

OL

Figure 32. Reference Voltage vs. Power Supply Voltage

Figure 29. Output Voltage LOW vs. Output Current

REV. B

–11–

AD9054A

2.502

These applications require the converter to process inputs with

frequency components well in excess of the sampling rate (often

with subnanosecond rise times), after which the A/D must settle

and sample the input in well under one pixel time. The architec-

ture of the AD9054A is vastly superior to older flash architec-

tures, that not only exhibit excessive input capacitance (which is

very hard to drive), but can make major errors when fed a very

rapidly slewing signal. The AD9054A’s extremely wide bandwidth

Track/Hold circuit processes these signals without difficulty.

2.501

2.500

2.499

Using the AD9054A

Good high speed design practices must be followed when using

the AD9054A. To obtain maximum benefit, decoupling capaci-

tors should be physically as close to the chip as possible. We

recommend placing a 0.1 µF capacitor at each power-ground

pin pair (9 total) for high frequency decoupling, and including

one 10 µF capacitor for local low frequency decoupling. The

VREF IN pin should also be decoupled by a 0.1 µF capacitor.

2.498

–40

–20

0

20

T

40

– ؇C

60

80

100

AMB

Figure 33. Reference Voltage vs. Temperature

APPLICATION NOTES

THEORY OF OPERATION

The part should be located on a solid ground plane and output

trace lengths should be short (<1 inch) to minimize transmis-

sion line effects. This avoids the need for termination resistors

on the output bus and reduces the load capacitance that needs

to be driven, which in turn minimizes on-chip noise due to

heavy current flow in the outputs. We have obtained optimum

performance on our evaluation board by tying all V_DDpins to a

quiet analog power supply system, and tying all GND pins to a

quiet analog system ground.

The AD9054A combines Analog Devices’ patented MagAmp

bit-per-stage architecture with flash converter technology to

create a high performance, low power ADC. For ease of use

the part includes an onboard reference and input logic that

accepts TTL, CMOS or PECL levels.

The analog input signal is buffered by a high-speed differential

amplifier and applied to a track-and-hold (T/H) circuit. This

T/H captures the value of the input at the sampling instant and

maintains it for the duration of the conversion. The sampling

and conversion process is initiated by a rising edge on the

ENCODE input. Once the signal is captured by the T/H, the

four Most Significant Bits (MSBs) are sequentially encoded by

the MagAmp string. The residue signal is then encoded by a

flash comparator string to generate the four Least Significant

Bits (LSBs). The comparator outputs are decoded and com-

bined into the 8-bit result.

Minimum Encode Rate

The minimum sampling rate for the AD9054A is 25 MHz.

To achieve very high sampling rates, the track/hold circuit em-

ploys a very small hold capacitor. When operated below the

minimum guaranteed sampling rate, the T/H droop becomes

excessive. This is first observed as an increase in offset voltage,

followed by degraded linearity at even lower frequencies.

Lower effective sampling rates may be easily supported by oper-

ating the converter in dual port output mode and using only

one output channel. A majority of the power dissipated by the

AD9054A is static (not related to conversion rate) so the penalty

for clocking at twice the desired rate is not high.

If the user has selected Single Channel Mode (DEMUX =

HIGH), the 8-bit data word is directed to the Channel A out-

put bank. Data are strobed to the output on the rising edge of

the ENCODE input with four pipeline delays. If the user has

selected Dual Channel Mode (DEMUX = LOW) the data are

alternately directed between the A and B output banks and have

five pipeline delays. At power-up, the N sample data can ap-

pear at either the A or B port. To align the data in a known

state the user must strobe DATA SYNC (DS, DS) per the

conditions described in the Timing section.

Reference

The AD9054A internal reference, VREF, provides a simple, cost

effective reference for many applications. It exhibits reasonable

accuracy and excellent stability over power supply and tempera-

ture variations. The VREF OUT pin can simply be strapped to

the VREF IN pin. The internal reference can be used to drive

additional loads (up to several mA), including multiple A/D con-

verters as might be required in a triple video converter application.

Graphics Applications

The high bandwidth and low power of the AD9054A make it

very attractive for applications that require the digitization of

presampled waveforms, wherein the input signal rapidly slews

from one level to another and is relatively stable for a period of

time. Examples of these include digitizing the output of com-

puter graphic display systems and very high speed solid state

imagers.

When an external reference is desired for accuracy or other

requirements, the AD9054A should be driven directly by the

external reference source connected to pin VREF IN (VREF

OUT can be left floating). The external reference can be set to

2.5 V 0.25 V. If VREF IN is raised by 10% (set to 2.75 V) the

analog full-scale range will increase by 10% to 1.024 × 1.1 =

1.1264 V. The new input range will then be AIN 0.5632 V.

–12–

REV. B

AD9054A

Digital Inputs

When operating in Single-Channel Mode, the outputs at Port B

are held static in a random state.

SNR performance is directly related to the sampling clock sta-

bility in A/D converters, particularly for high input frequencies

and wide bandwidths. A low jitter clock (<10 ps @ 100 MHz)

is essential for optimum performance when digitizing signals

that are not presampled.

Figure 35 shows the AD9054A used in single-channel output

mode. The analog input ( 0.5 V) is ac coupled and the ENCODE

input is driven by a TTL level signal. The chip’s internal refer-

ence is used.

ENCODE and Data Select (DS) can be driven differentially or

single-ended. For single-ended operation, the complement

inputs (ENCODE, DS) are internally biased to V_DD/3 (~1.5 V)

by a high impedance on-chip resistor divider (Figure 5), but

they may be externally driven to establish an alternate threshold

if desired. A 0.1 µF decoupling capacitor to ground is sufficient

to maintain a threshold appropriate for TTL or CMOS logic.

VREF OUT

0.1␮F

VREF IN

A PORT

AIN

1k⍀

AD9054A

VIN

AIN

0.1␮F

When driven differentially, ENCODE and DS will accommo-

date differential signals centered between 1.5 V and 4.5 V with

a total differential swing ≥800 mV (V_ID≥ 400 mV).

+5V

DEMUX

DS

ENC ENC

DS

Note the 6-diode clock input protection circuitry in Figure 5.

This limits the differential input voltage to ~ 2.1 V. When the

diodes turn on, current is limited by the 300 Ω series resistor.

Exceeding 2.1 V across the differential inputs will have no im-

pact on the performance of the converter, but be aware of the

clock signal distortion that may be produced by the nonlinear

impedance at the converter.

0.1␮F

NC

CLOCK

NC = NO CONNECT

Figure 35. Single Port Mode—AC-Coupled Input—Single-

Ended Encode

Dual Port Mode

In Dual Port Mode (DEMUX = LOW), the conversion results

are alternated between the two output ports (Figure 2). This

limits the data output rate at either port to 1/2 the conversion

rate (ENCODE), and supports conversion at up to 200 MSPS

with TTL/CMOS compatible interfaces. Dual Channel Mode is

required for guaranteed operation above 100 MSPS, but may be

enabled at any specified conversion rate.

V

IH D

IC M

CLOCK

ENC

V

ID

CLOCK

ENC

V

IL D

a. Driving Differential Inputs Differentially

The multiplexing is controlled internally via a clock divider,

which introduces a degree of ambiguity in the port assignments.

Figure 2 illustrates that, prior to synchronization, either Port A

or Port B may produce the even or odd samples. This is re-

solved by exercising the Data Sync (DS) control, a differential

input (identical to the ENCODE input), which facilitates opera-

tion at high speed.

V

IH D

CLOCK

ENC

V

ID

V

IC M

ENC

0.1␮F

V

IL D

b. Driving Differential Inputs Single-Endedly

At least once after power-up, and prior to using the conversion

data, the part needs to be synchronized by a falling edge (or a

positive-going pulse) on DS (observing setup and hold times

with respect to ENCODE). If the converter’s internal timing is

in conflict with the DS signal when it is exercised, then two data

samples (one on each port) are corrupted as the converter is

resynchronized. The converter then produces data with a

known phase relationship from that point forward.

Figure 34. Input Signal Level Definitions

Single Port Mode

When operated in a Single Port mode (DEMUX = HIGH), the

timing of the AD9054A is similar to any high speed A/D Con-

verter (Figure 1).

A sample is taken on every rising edge of ENCODE, and the

resulting data is produced on the output pins following the

FOURTH rising edge of ENCODE after the sample was taken

(four pipeline delays). The output data are valid t_PDafter the

rising edge of ENCODE, and remain valid until at least t_Vafter

the next rising edge of ENCODE.

Note that if the converter is already properly synchronized, the

DS pulse has no effect on the output data. This allows the con-

verter to be continuously resynchronized by a pulse at 1/2 the

ENCODE rate. This signal is often available within a system, as

it represents the master clock rate for the demultiplexed output

data. Of course, a single DS signal may be used to synchronize

multiple A/D converters in a multichannel system.

The maximum clock rate is specified as 100 MSPS. This is

recommended because the guaranteed output data valid time

equals the Clock Period (1/f_S) minus the Output Propagation

Delay (t_PD) plus the Output Valid Time (t_V), which comes to

4.8 ns at 100 MHz. This is about as fast as standard logic is able

to capture the data with reasonable design margins. The AD9054A

will operate faster in single-channel mode if you are able to

capture the data.

REV. B

–13–

AD9054A

Applications that call for the AD9054A to be synchronized at

power-up or only periodically during calibration/reset (i.e., valid

data is not required prior to synchronization), need only be

concerned with the timing of the falling edge of DS. The falling

edge of DS must satisfy the setup time defined by Figure 2 and

the specification table. In this case the DS hold time specifica-

tion on the rising edge can be ignored.

In Figure 36, the converter is operating in Dual Port Mode,

with data coming alternately out of Port A and Port B. The

figure illustrates how the output data may be aligned with an

output latch to produce a 16-bit output at 1/2 the conversion

clock rate. The Data Sync input must be properly exercised to

time the A Port with the synchronizing latch.

Applications that will continuously update the synchronization

command need to treat the DS signal as a pulse and satisfy

timing requirements on both rising and falling edges. It is easiest

to consider the DS signal in this case to be a pulse train at one

half the encode rate, the positive pulse nominally bracketing the

ENCODE falling edge on alternate cycles as shown in the tim-

ing diagram (Figure 2b). Both the falling and rising edges of DS

must satisfy minimum setup (t_SDS) and hold (t_HDS) times with

respect to the falling edges of ENCODE. This timing require-

ment produces a tight timing window at higher encode rates.

Synchronization by a single reset edge results in a simpler timing

solution in many applications. For example, synchronization

may be provided at the beginning of each graphics line or frame.

VREF OUT

0.1␮F

VREF IN

A PORT

AIN

'573

AD9054A

1k⍀

AIN

VIN

0.1␮F

B PORT

DEMUX

DS

ENC ENC

DS

0.1␮F

DS

NC

The data are presented at the output of the AD9054A in a ping-

pong (alternating) fashion to optimize the performance of the

converter. It may be aligned for presentation as sixteen bits in

parallel by adding a register stage to the output.

CLOCK

'74

DIVIDE

BY 2

NC = NO CONNECT

In Dual Channel Mode, the converted data is produced five

clock cycles after the rising edge of ENCODE on which the

sample is taken (five pipeline delays).

Figure 36. Dual Port Mode—Aligned Output Data

–14–

REV. B

AD9054A

EVALUATION BOARD

Voltage Reference

The AD9054A evaluation board offers an easy way to test the

AD9054A. It provides dc biasing for the analog input, generates

the latch clocks for both full speed and demuxed modes, and in-

cludes a reconstruction DAC. The board has several different

modes of operation, and is shipped in the following configuration:

The AD9054A has an internal 2.5 V voltage reference. An

external reference may be employed instead. The evaluation

board is configured for the internal reference. To use an exter-

nal reference, connect it to the (VREF) pin on the power con-

nector and move jumper S102.

• DC-Coupled Analog Input

• Demuxed Outputs

Single Port Mode

Single Port Mode sets the AD9054A to produce data on every

clock cycle on output port A only. To test in this mode, jumper

S104 should be set to single channel and S106 and S107 must

be set to F (for Full). The maximum speed in single port mode

is 100 MSPS.

• Differential Clocks

• Internal Voltage Reference.

VREF EXT

DC BIAS

S102

Dual Port Mode

AIN

S103

VREF OUT

VREF IN

AIN

Dual Port or half speed output mode sets the ADC to produce

data alternately on Port A and Port B. In this mode, the reset

function should be implemented. To test in this mode, set

jumper S104 to Dual Channel, and set S106 and S107 to D (for

Dual Port). The maximum speed in this mode is 200 MSPS.

B PORT

A PORT

'574

50⍀

AD9054A

AIN

RESET

BUTTON

RESET

5V

RESET drives the AD9054A’s Data Sync (DS) pins. When

operating in Single Port Mode, RESET is not used. In Dual-

Channel Mode it is needed for two reasons: to synchronize the

timing of Port A data and Port B data with a known clock edge,

as described in the data sheet, and to synchronize the evaluation

board’s latch clocks with the data coming out of the AD9054A.

Reset can be driven in two ways: by pushing the reset button on

the board, or externally, with a TTL pulse through connector J5

or J6.

D

DEMUX

D FF

S104

C

CLK A

CLK B

DS

ENC ENC

DS

S105

DAC

ENC

50⍀

ENC

CLK A

DAC Out

CLOCKING

ENC

CLK B

ENC

The DAC output is a representation of the data on output Port

A only. Output Port B is not reconstructed.

Troubleshooting

If the board does not seem to be working correctly, try the fol-

lowing:

Figure 37. PCB Block Diagram

Analog Input

The evaluation board accepts a 1 V input signal centered at

ground. The board’s input circuitry then biases this signal to

+2.5 V in one of two ways:

•

Check that all jumpers are in the correct position for the

desired mode of operation.

Push the reset button. This will align the AD9054A’s data

output with the half speed latch clocks.

1. DC-coupled through an AD9631 op amp; this is the mode in

which it is shipped. Potentiometer R7 provides adjustment

of the bias voltage.

Switch the jumper S105 from A-R to R-B or vice-versa, then

push the reset button. In demuxed mode, this will have the

effect of inverting the half speed latch clocks.

2. AC-coupled through C1.

These two modes are selected by jumpers S101 and S103. For

dc coupling, the S101 jumper is connected between the two left

pins and the S103 jumper is connected between the two lower

pins. For ac coupling, the S101 jumper is connected between

the two right pins and the S103 jumper is connected between

the two upper pins.

•

At high encode rates, the evaluation board’s clock generation

circuitry is sensitive to the +5 V digital power supply. At

high encode rates, the +5 V digital power should be kept

below +5.2 V. This is an evaluation board sensitivity and

not an AD9054A sensitivity.

The AD9054A Evaluation Board is provided as a design ex-

ample for customers of Analog Devices, Inc. ADI makes no

warranties, express, statutory, or implied, regarding merchant-

ability or fitness for a particular purpose.

ENCODE

The AD9054A ENCODE input can be driven two ways:

1. Differential TTL, CMOS, or PECL; it is shipped in this

mode.

2. Single-ended TTL or CMOS. To use in this mode, remove

R11, the 50 Ω chip resistor located next to the ENCODE

input, and insert a 0.1 µF ceramic capacitor into the C5 slot.

C5 is located between the ENC connector and the ENCODE

input to the DUT and is marked on the back side of the

board. In this mode, ENCODE is biased with internal resis-

tors to 1.5 V, but it can be externally driven to any dc voltage.

REV. B

–15–

AD9054A

( L S B )

D B 0

S L E E P

R E F L O

D B 1

D B 2

D B 3

D B 4

D B 5

D B 6

D B 7

D B 8

D B 9

R E F I O

F S A D J

C O M P 1

C O M P 2

A V D D

D V D D

D B 4

D B 5

D B 6

D B 7

D A 3

D A 4

D A 5

D A 6

D A 7

G N D

V D D

G N D

V D D

G N D

+ 5 V A

G N D

+ 5 V A

G N D

V D D

G N D

V D D

G N D

+ 5 V A

G N D

+ 5 V A

Figure 38. Evaluation Board Schematic

–16–

REV. B

AD9054A

Figure 39. Assembly—Top View

Figure 41. Conductors—Top View

Figure 42. Conductors—Bottom View

Figure 40. Assembly—Bottom View

REV. B

–17–

AD9054A

BILL OF MATERIALS

GS00104 REV. B

ITEM QTY

PART NUMBER

REFERENCE

DESCRIPTION

MFG/DISTRIBUTOR

11

30

GRM40Z5U104M050BL

C1, C2, C4, C6–8,

C10–C22, C24–C29,

C31–C35

0.1 µF CER CHIP CAP 0805

TTI

12

13

14

15

16

17

18

19

10

1

P10FBK-ND

R5

10 Ω SURFACE MT RES 1206

100 Ω SURFACE MT RES 1206

10 µF TANTALUM CHIP CAP

140 Ω SURFACE MT RES 1206

1 kΩ SURFACE MT RES 1206

2 kΩ SURFACE MT RES 1206

1k TRIM POT TOP ADJ, 25 TURN

37P D CONN RT ANG PCMT FEM

49.9 Ω SURFACE MT RES 1206

DIGI-KEY

TTI

21

4

P100FBK-ND

T491C106M016AS

P140FBK-ND

P1KFBK-ND

P2KFBK-ND

3296W-102-ND

K44-C37S-QJ

P49.9FBK-ND

R3, R9, R21–R39

C3, C9, C23, C30

2

R2, R4

DIGI-KEY

CENTURY ELEC

DIGI-KEY

1

R12

3

R6, R8, R14

1

R7

J6

1

5

R1, R10, R11,

R15, R16

11

1

CSC06A-01-511G

51F54113

RP1

510 Ω 6P BUSED RES NETWORK

8291Z 3-PIN TERMINAL BLOCK

8291Z 2-PIN TERMINAL BLOCK

BNC COAX CONN PCMT 5 LEAD

DIP-16 DUAL D FLIP-FLOP

DIP-16 QUAD ECL TO TTL TRANS

SO-14 FAST TTL DUAL D FLIP-FLOP

HEADER STRIP 20P GOLD MALE

40P HEADER

TTI

12

1

TB1

NEWARK

13

1

51F54112

TB1

NEWARK

14

4

AMP-227699-2

MC10H131P

MC10H125P

74F74SC-ND

TSW-120-08-G-S

90F3987

J1–J4

TIME ELEC

15

1

U6

HAMILTON/HALLMARK

DIGI-KEY

16

1

U7

17

1

U2

18

1

J5

SAMTEC

ALT:

19

1/2

1

J5

NEWARK

AD96685BR

S90F9280

U3

HIGH SPEED COMP SOIC-16

SHORTING JUMPER

ANALOG DEVICES, INC.

NEWARK

20

7

S101–S107

S101–S107, GND

21

8

89F4700

3-PIN HEADER (DIVIDE 1 OF THE

8 FOR 3 GND HOLES)

NEWARK

22

23

24

25

26

2

1

MC74F574DW

AD9631AR

U4, U5

U1

SO-20 OCTAL D TYPE FLIP-FLOP

SOIC-8 OP AMP

HAMILTON/HALLMARK

ANALOG DEVICES, INC.

DIGI-KEY

AD9760AR

U8

10-BIT CMOS DAC SOIC-28

8-BIT ADC IN 44-LEAD LQFP

AD9054ABST

P8002SCT-ND

UA1

B1

SURFACE MOUNT MOMENTARY

PUSHBUTTON

27

4

90F1533

–

BUMPON PROTECTIVE BUMPER

NEWARK

PARTS NOT ON BILL OF MATERIALS, AND NOT TO BE INSTALLED: C5, C36, C37, R17–R20.

–18–

REV. B

AD9054A

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

44-Lead Plastic Thin Quad Flatpack (LQFP)

(ST-44)

0.063 (1.60)

MAX

0.472 (12.00) SQ

0.030 (0.75)

0.018 (0.45)

33

23

34

22

SEATING

PLANE

0.394

(10.0)

SQ

TOP VIEW

(PINS DOWN)

44

12

1

11

0.006 (0.15)

0.002 (0.05)

0.018 (0.45)

0.012 (0.30)

0.031 (0.80)

BSC

0.057 (1.45)

0.053 (1.35)

REV. B

–19–


型号：	AD9054A/PCB
厂家：	ADI
描述：	8-Bit, 200 MSPS A/D Converter 8 - BIT ， 200 MSPS A / D转换器转换器
文件：	总19页 (文件大小：332K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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