AD9054 [ADI]
8-Bit, 200 MSPS A/D Converter; 8 - BIT ， 200 MSPS A / D转换器
| 型号： | AD9054 |
| 厂家： | 
ADI |
| 描述： | 8-Bit, 200 MSPS A/D Converter |
| 文件： | 总20页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit, 200 MSPS
A/D Converter
a
AD9054
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
200 MSPS Guaranteed Conversion Rate
135 MSPS Low Cost Version Available
350 MHz Analog Bandw idth
1 V p-p Analog Input Range
Internal +2.5 V Reference and T/ H
Low Pow er: 500 m W
VREF IN
VREF OUT
AD9054
؉2.5V REFERENCE
AIN
8
8
T/H
QUANTIZER
DA –DA
ENCODE
LOGIC
DEMULTIPLEXER
7
0
AIN
+5 V Single Supply Operation
TTL Output Interface
ENCODE
ENCODE
DB –DB
7
0
TIMING
Single or Dem ultiplexed Output Ports
V
DS
GND
DEMUX
DS
DD
APPLICATIONS
RGB Graphics Processing
High Resolution Video
Digital Data Storage Read Channels
Digital Com m unications
Digital Instrum entation
Medical Im aging
T he AD9054’s encode input interfaces directly to T T L, CMOS
or positive-ECL logic and will operate with single-ended or
differential inputs. T he user may select dual-channel or single-
channel digital outputs. T he dual (demultiplexed) mode inter-
leaves ADC data through two 8-bit channels at one-half the
clock rate. Operation in demultiplexed mode reduces the speed
and cost of external digital interfaces while allowing the ADC to
be clocked to the full 200 MSPS conversion rate. In the single-
channel (nondemultiplexed) mode, all data is piped at the full
clock rate to the Channel A outputs.
GENERAL D ESCRIP TIO N
T he AD9054 is an 8-bit monolithic analog-to-digital converter
optimized for high speed, low power, small size and ease of use.
With a 200 MSPS encode rate capability and full-power analog
bandwidth of 350 MHz, the component is ideal for applications
requiring the highest possible dynamic performance.
T o minimize system cost and power dissipation, the AD9054
includes an internal +2.5 V reference and track-and-hold circuit.
T he user provides only a +5 V power supply and an encode
clock. No external reference or driver components are required
for many applications.
Fabricated with an advanced BiCMOS process, the AD9054 is
provided in a space-saving 44-lead T QFP surface mount plastic
package (ST -44) and specified over the full industrial (–40°C to
+85°C) temperature range.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
AD9054–SPECIFICATIONS
(V = +5 V, external reference, fS = max unless otherwise noted)
ELECTRICAL CHARACTERISTICS DD
Test
AD 9054BST-200
AD 9054BST-135
P aram eter
Tem p
Level
Min
Typ
Max
Min
Typ
Max
Units
RESOLUT ION
8
8
Bits
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
Full
+25°C
Full
I
VI
I
VI
VI
I
±0.9
±1.0
±0.6
+1.5/–1.0
+2.0/–1.0
±1.5
±0.9
±1.0
±0.6
±0.9
+1.5/–1.0 LSB
+2.0/–1.0 LSB
Integral Nonlinearity
±1.5
±2.0
LSB
LSB
±0.9
±2.0
No Missing Codes
Gain Error1
Guaranteed
±2
Guaranteed
±7
±2
160
±7
% FS
Gain T empco1
V
160
ppm/°C
ANALOG INPUT
Input Voltage Range
(With Respect to AIN)
Compliance Range AIN or AIN
Input Offset Voltage
Full
Full
+25°C
Full
+25°C
Full
+25°C
+25°C
Full
V
V
I
VI
I
VI
V
I
VI
V
±512
±512
mV p–p
V
mV
mV
kΩ
kΩ
pF
µA
µA
1.8
3.2
±16
±19
1.8
3.2
±16
±19
±4
±8
62
±4
±8
62
Input Resistance
36
23
36
23
Input Capacitance
Input Bias Current
4
25
4
25
50
75
50
75
Analog Bandwidth, Full Power2
+25°C
350
350
MHz
REFERENCE OUT PUT
Output Voltage
T emperature Coefficient
Full
Full
VI
V
2.4
2.5
110
2.6
2.4
2.5
110
2.6
V
ppm/°C
SWIT CHING PERFORMANCE
Maximum Conversion Rate (fS)
Minimum Conversion Rate (fS)
Full
Full
VI
IV
IV
IV
V
200
135
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
25
15
15
25
15
15
Encode Pulsewidth High (tEH
)
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Full
2.0
2.0
3.0
3.0
Encode Pulsewidth Low (tEL
Aperture Delay (tA)
)
0.5
2.3
0.5
2.3
Aperture Uncertainty (Jitter)
V
Data Sync Setup T ime (tSDS
Data Sync Hold T ime (tHDS
)
)
IV
IV
IV
VI
VI
0
0
0.5
2.0
2.7
0.5
2.0
2.7
Data Sync Pulsewidth (tPWDS
)
Output Valid T ime (tV)3
5.1
5.9
5.7
7.5
3
Output Propagation Delay (tPD
)
Full
7.9
8.5
ns
DIGIT AL INPUT S
HIGH Level Current (IIH
LOW Level Current (IIL
Input Capacitance
4
)
Full
Full
+25°C
VI
VI
V
500
500
3
625
625
500
500
3
625
625
µA
µA
pF
4
)
DIFFERENT IAL INPUT S
Differential Signal Amplitude (VID
HIGH Input Voltage (VIHD
LOW Input Voltage (VILD
)
Full
Full
Full
Full
IV
IV
IV
IV
400
1.5
0
400
1.5
0
mV
V
V
)
VDD
VDD – 0.4
VDD
VDD – 0.4
)
Common-Mode Input (VICM
)
1.5
1.5
V
DEMUX INPUT
HIGH Input Voltage (VIH
)
Full
Full
IV
IV
2.0
0
VDD
0.8
2.0
0
VDD
0.8
V
V
LOW Input Voltage (VIL
)
DIGIT AL OUT PUT S
HIGH Input Voltage (VOH
)
Full
Full
VI
VI
2.4
2.4
V
V
LOW Input Voltage (VOL
Output Coding
)
0.4
0.4
Binary
Binary
–2–
REV. 0
AD9054
Test
AD 9054BST-200
AD 9054BST-135
P aram eter
Tem p
Level
Min
Typ
Max
Min
Typ
Max
Units
POWER SUPPLY
VDD Supply Current (IDD
)
Full
Full
VI
VI
100
500
145
725
100
500
140
700
mA
mW
Power Dissipation5, 6
Power Supply Sensitivity7
+25°C
I
0.005
0.015
0.005
0.015
V/V
DYNAMIC PERFORMANCE8
T ransient Response
Overvoltage Recovery T ime
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
+25°C
+25°C
V
V
1.5
1.5
1.5
1.5
ns
ns
fIN = 19.7 MHz
+25°C
Full
+25°C
Full
+25°C
Full
IV
V
I
V
I
42
42
42
45
45
45
45
45
45
42
42
45
45
45
45
dB
dB
dB
dB
dB
dB
fIN = 49.7 MHz
fIN = 70.1 MHz
V
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
fIN = 19.7 MHz
+25°C
Full
+25°C
Full
+25°C
Full
IV
V
I
V
I
40
40
39
43
43
43
43
42
42
40
40
43
43
43
43
dB
dB
dB
dB
dB
dB
fIN = 49.7 MHz
fIN = 70.1 MHz
V
Effective Number of Bits
fIN = 19.7 MHz
fIN = 49.7 MHz
+25°C
+25°C
+25°C
IV
I
I
6.35
6.35
6.18
6.85
6.85
6.85
6.35
6.35
6.85
6.85
Bits
Bits
Bits
fIN = 70.1 MHz
2nd Harmonic Distortion
fIN = 19.7 MHz
fIN = 49.7 MHz
+25°C
+25°C
+25°C
IV
I
I
58
54
52
63
59
55
58
54
63
59
dBc
dBc
dBc
fIN = 70.1 MHz
3rd Harmonic Distortion
fIN = 19.7 MHz
fIN = 49.7 MHz
+25°C
+25°C
+25°C
IV
I
I
48
48
43
56
54
50
48
48
56
54
dBc
dBc
dBc
fIN = 70.1 MHz
Two-Tone Intermod Distortion
(IMD)
fIN = 19.7 MHz
fIN = 49.7 MHz
fIN = 70.1 MHz
+25°C
+25°C
+25°C
V
V
V
60
55
50
60
55
dBc
dBc
dBc
NOT ES
1Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference).
23 dB bandwidth with full-power input signal.
3tV and tPD are measured from the threshold crossing of the ENCODE input to valid T T L levels of the digital outputs. T he output ac load during test is 5 pF (Refer to
equivalent circuits Figures 5 and 6).
4IIH and IIL are valid for differential input voltages of less than 1.5 V. At higher differential voltages, the input current will increase to a maximum of 1.25 mA.
5Power dissipation is measured under the following conditions: analog input is –1 dBfs at 19.7 MHz.
6T ypical thermal impedance for the ST -44 (T QFP) 44–lead package (in still air): θJC = 20°C/W, θCA = 35°C/W, θJA = 55°C/W.
7A change in input offset voltage with respect to a change in VDD
.
8SNR/harmonics based on an analog input voltage of –1.0 dBfs referenced to a 1.024 V full–scale input range.
Specifications subject to change without notice.
EXP LANATIO N O F TEST LEVELS
Test Level
I. 100% production tested.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested at +25°C; guaranteed by design
II. 100% production tested at +25°C and sample tested at
and characterization testing for industrial temperature range.
specified temperatures.
III. Sample tested only.
REV. 0
–3–
AD9054
P IN FUNCTIO N D ESCRIP TIO NS
ABSO LUTE MAXIMUM RATINGS*
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to 0.0 V
VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . VDD to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating T emperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction T emperature . . . . . . . . . . . . . . . +175°C
Maximum Case T emperature . . . . . . . . . . . . . . . . . . +150°C
P in Num ber
Nam e
Function
1
ENCODE
Encode Clock for ADC (ADC
Samples on Rising Edge of
ENCODE).
2
ENCODE
Encode Clock Complement
(ADC Samples on Falling Edge
of ENCODE).
3, 5, 15, 18, 28,
30, 31, 36, 41
VDD
GND
Power Supply (+5 V).
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
4, 6, 16, 17, 27,
29, 32, 35, 37, 40
14–7
Ground.
DA0–DA7
DB0–DB7
Digital Outputs of ADC Channel
A. DA7 is the MSB, DA0 the LSB.
Table I. O utput Coding
19–26
33
Digital Outputs of ADC Channel
B. DB7 is the MSB, DB0 the LSB.
Step
AIN–AIN
Code
Binary
VREF OUT Internal Reference Output
(+2.5 V typical); Bypass with
0.1 µF to Ground.
255
254
253
•
≥0.512 V
0.508 V
0.504 V
255
254
253
•
1111 1111
1111 1110
1111 1101
34
38
VREF IN
Reference Input for ADC (+2.5 V
typical, ±4%).
•
•
•
•
•
•
•
•
•
•
AIN
Analog Input—Complement.
Connect to input signal midscale
reference.
129
128
127
126
•
0.006 V
0.002 V
–0.002 V
–0.006 V
•
129
128
127
126
•
1000 0001
1000 0000
0111 1111
0111 1110
•
39
42
AIN
Analog Input—T rue.
DEMUX
Format Select. LOW = Dual.
Channel Mode, HIGH = Single.
Channel Mode (Channel A Only).
•
•
•
•
•
•
•
•
43
44
DS
Data Sync Complement.
2
1
0
–0.504 V
–0.508 V
≤–0.512 V
2
1
0
0000 0010
0000 0001
0000 0000
DS
Data Sync—Aligns output chan-
nels in Dual-Channel Mode.
P IN CO NFIGURATIO N
O RD ERING GUID E
Tem perature
Range
P ackage
O ption*
Model
AD9054BST -200
AD9054BST -135
AD9054/PCB
–40°C to +85°C
–40°C to +85°C
+25°C
ST -44
ST -44
Evaluation Board
DB
DB
DB
VREF IN
GND
3
2
VDD
GND
AIN
1
DB (LSB)
0
*ST = Plastic T hin Quad Flatpack (T QFP).
VDD
GND
GND
VDD
AD9054
TOP VIEW
(PINS DOWN)
AIN
GND
VDD
DEMUX
DS
DA (LSB)
0
DA
1
PIN 1
IDENTIFIER
DS
DA
2
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9054 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD9054
SAMPLE N
SAMPLE N+3
SAMPLE N+4
SAMPLE N–1
AIN
SAMPLE N+1
SAMPLE N+2
tA
1/f
S
tEH
tEL
ENCODE
ENCODE
tPD
tV
DATA N–1
DATA N
DATA N–5
DATA N–4
DATA N–3
DATA N–2
D –D
7
0
Figure 1. Tim ing—Single Channel Mode
SAMPLE N
SAMPLE N+3
SAMPLE N+4
SAMPLE N+5
SAMPLE N–1
AIN
SAMPLE N–2
SAMPLE N+1
SAMPLE N+2
SAMPLE N+6
tA
tEH
tEL
1/f
S
ENCODE
ENCODE
tHDS
tHDS
tSDS
tSDS
DS
DS
tPD
tV
tPWDS
PORT A
D –D
DATA N–7
OR N–8
INVALID IF OUT OF SYNC
DATA N–4 IF IN SYNC
DATA N–7
OR N–6
DATA N
DATA N–2
7
0
PORT B
D –D
DATA N–8
OR N–7
DATA N–6
OR N–7
INVALID IF OUT OF SYNC
DATA N–5 IF IN SYNC
DATA N+1
DATA N–3
DATA N–1
7
0
Figure 2. Tim ing—Dual Channel Mode
REV. 0
–5–
AD9054
EQ UIVALENT CIRCUITS
V
V
DD
DD
17.5k⍀
300⍀
300⍀
DEMUX
AIN
AIN
7.5k⍀
Figure 3. Equivalent Analog Input Circuit
Figure 6. Equivalent DEMUX Input Circuit
V
DD
V
DD
VREF IN
DIGITAL
OUTPUTS
Figure 7. Equivalent Digital Output Circuit
Figure 4. Equivalent Reference Input Circuit
V
DD
V
DD
17.5k⍀
300⍀
300⍀
ENCODE
OR DS
ENCODE
OR DS
VREF
OUT
7.5k⍀
Figure 5. Equivalent ENCODE and Data Select Input Circuit
Figure 8. Equivalent Reference Output Circuit
–6–
REV. 0
Typical Performance Characteristics–
AD9054
55
50
45
40
35
30
45.4
45.2
50MHz
20MHz
45.0
SNR
44.8
SINAD
70MHz
44.6
NYQUIST
FREQUENCY
(100MHz)
44.4
44.2
44.0
0
20
40
60
80
100
120
140
0
–45
25
– ؇C
70
90
f
– MHz
IN
T
C
Figure 9. SNR vs. fIN: fS = 200 MSPS
Figure 12. SNR vs. Tem perature, fS = 135 MSPS
50
49
48
47
46
45
44
43
42
41
40
46.0
45.8
45.6
20MHz
50MHz
70MHz
45.4
45.2
45.0
SNR
44.8
44.6
44.4
44.2
44.0
SINAD
25 50
75 100 125 150 175 200 225 250 270 300
– MSPS
–60
–40
–20
0
20
– ؇C
40
60
80
100
f
T
S
C
Figure 10. SNR vs. fS: fIN = 19.7 MHz
Figure 13. SNR vs. Tem perature, fS = 200 MSPS
50
50
F
F
= 135MSPS
= 10.3MHz
S
48
46
44
42
40
38
36
34
32
30
SNR
IN
45
40
35
30
SINAD
SNR
SINAD
25
20
50
75 100 125 150 175 200 225 250 270 300
– MSPS
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
25
ENCODE PULSEWIDTH – ns
f
S
Figure 14. SNR vs. Clock Pulsewidth, (tPWH): fS = 135 MSPS
Figure 11. SNR vs. fS: fIN = 70.1 MHz
REV. 0
–7–
AD9054
–70
–68
–66
–64
–62
–60
–58
50
F
F
= 200MSPS
= 10.3MHz
S
48
46
44
42
40
38
2ND HARMONIC
3RD HARMONIC
IN
SNR
SINAD
–56
–54
–52
36
34
32
30
–50
–48
–46
25 50
75 100 125 150 175 200 225 250 270 300
0.0 0.5 1.0 1.5 2.0 2.5
3.0 3.5 4.0 4.5
5.0
ENCODE PULSEWIDTH – ns
f
– MSPS
S
Figure 15. SNR vs. Clock Pulsewidth, (tPWH): fS = 200 MSPS
Figure 18. Harm onic Distortion vs. fS: fIN = 19.7 MHz
46
45
–60
–50
44
2ND HARMONIC
–40
20MHz
43
3RD HARMONIC
70MHz
42
41
40
39
38
–30
–20
50MHz
–10
0
–60
–40
–20
0
20
– ؇C
40
60
80
100
25
50 75 100 125 150 175 200 225 250 270
fS – MSPS
300
T
C
Figure 16. SINAD vs. Tem perature: fS = 135 MSPS
Figure 19. Harm onic Distortion vs. fS: fIN = 70.1 MHz
46
45
–40
–45
–50
44
20MHz
43
50MHz
42
–55
70MHz
70MHz
41
40
39
38
–60
50MHz
–65
20MHz
–70
–60
–60
–40
–20
0
20
– ؇C
40
60
80
100
–40
–20
0
20
– ؇C
40
60
80
100
T
T
C
C
Figure 17. SINAD vs. Tem perature: fS = 200 MSPS
Figure 20. 2nd Harm onic vs. Tem perature: fS = 135 MSPS
–8–
REV. 0
AD9054
–40
–45
–50
–55
–60
–65
–70
0
–1
–2
–3
–4
–5
–6
70MHz
NYQUIST FREQUENCY
100MHz
50MHz
20MHz
–60
–40
–20
0
20
– ؇C
40
60
80
100
0
50 100 150 200 250 300 350 400 450 500
– MHz
f
T
IN
C
Figure 21. 2nd Harm onic vs. Tem perature: fS = 200 MSPS
Figure 24. Frequency Response: fS = 200 MSPS
–40
–45
0
FUNDAMENTAL = –0.5dBfs
SNR = 45.8dB
SINAD = 45.2dB
2ND HARMONIC = 69.8dB
3RD HARMONIC = 61.6dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–50
70MHz
50MHz
–55
20MHz
–60
–65
–70
–60
–40
–20
0
20
– ؇C
40
60
80
100
0
10
20
30
40
50
60
70
80
90 100
MHz
T
C
Figure 25. Spectrum : fS = 200 MSPS, fIN = 19.7 MHz
Figure 22. 3rd Harm onic vs. Tem perature: fS = 135 MSPS
0
–40
FUNDAMENTAL = –0.5dBfs
SNR = 44.6dB
SINAD = 37.6dB
2ND HARMONIC = –63.1dB
3RD HARMONIC = –39.1dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–45
70MHz
–50
50MHz
–55
20MHz
–60
–65
–70
0
10
20
30
40
50
60
70
80
90 100
–60
–40
–20
0
20
– ؇C
40
60
80
100
MHz
T
C
Figure 26. Spectrum : fS = 200 MSPS, fIN = 70.1 MHz
Figure 23. 3rd Harm onic vs. Tem perature: fS = 200 MSPS
REV. 0
–9–
AD9054
7
6
5
4
3
2
1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
F1 = 55.0MHz
F2 = 56.0MHz
F1 = F2 = –7.0dBfs
tPD
tV
0
–60
–100
0
–40
–20
0
20
– ؇C
40
60
80
100
10
20
30
40
50
MHz
60
70
80
90 100
T
C
Figure 27. Two Tone Interm odulation Distortion
Figure 30. Output Delay vs. Tem perature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
0.0
0.0 –1.0 –2.0 –3.0 –4.0 –5.0 –6.0 –7.0 –8.0 –9.0 –10.0
–20 –18 –16 –14 –12 –10 –8
–6
–4 –2
0
2
I
– mA
IREF OUT – mA
OH
Figure 31. Reference Voltage vs. Reference Load
Figure 28. Output Voltage HIGH vs. Output Current
2.502
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
2.501
2.500
2.499
2.498
0.1
0.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0.0
1.0
2.0
3.0
4.0
– mA
5.0
6.0
7.0
8.0
I
V
– Volts
DD
OL
Figure 29. Output Voltage LOW vs. Output Current
Figure 32. Reference Voltage vs. Power Supply Voltage
–10–
REV. 0
AD9054
2.502
2.501
2.500
rapidly slewing signal. The AD9054’s extremely wide bandwidth
Track/Hold circuit processes these signals without difficulty.
Using the AD 9054
Good high speed design practices must be followed when using
the AD9054. T o obtain maximum benefit, decoupling capaci-
tors should be physically as close to the chip as possible. We
recommend placing a 0.1 µF capacitor at each power-ground
pin pair (9 total) for high frequency decoupling, and including
one 10 µF capacitor for local low frequency decoupling. T he
VREF IN pin should also be decoupled by a 0.1 µF capacitor.
2.499
2.498
T he part should be located on a solid ground plane and output
trace lengths should be short (<1 inch) to minimize transmis-
sion line effects. T his avoids the need for termination resistors
on the output bus and reduces the load capacitance that needs
to be driven, which in turn minimizes on-chip noise due to
heavy current flow in the outputs. We have obtained optimum
performance on our evaluation board by tying all VDD pins to a
quiet analog power supply system, and tying all GND pins to a
quiet analog system ground.
–40
–20
0
20
T
40
– ؇C
60
80
100
AMB
Figure 33. Reference Voltage vs. Tem perature
AP P LICATIO N NO TES
TH EO RY O F O P ERATIO N
T he AD9054 combines Analog Devices’ patented MagAmp bit-
per-stage architecture with flash converter technology to create
a high performance, low power ADC. For ease of use the part
includes an onboard reference and input logic that accepts
T T L, CMOS or PECL levels.
Minim um Encode Rate
T he minimum sampling rate for the AD9054 is 25 MHz. T o
achieve very high sampling rates, the track/hold circuit employs
a very small hold capacitor. When operated below the minimum
guaranteed sampling rate, the T /H droop becomes excessive.
T his is first observed as an increase in offset voltage, followed by
degraded linearity at even lower frequencies.
T he analog input signal is buffered by a high-speed differential
amplifier and applied to a track-and-hold (T /H) circuit. T his
T /H captures the value of the input at the sampling instant and
maintains it for the duration of the conversion. T he sampling
and conversion process is initiated by a rising edge on the
ENCODE input. Once the signal is captured by the T /H, the
four Most Significant Bits (MSBs) are sequentially encoded by
the MagAmp string. T he residue signal is then encoded by a
flash comparator string to generate the four Least Significant
Bits (LSBs). T he comparator outputs are decoded and com-
bined into the eight-bit result.
Lower effective sampling rates may be easily supported by oper-
ating the converter in dual port output mode and using only one
output channel. A majority of the power dissipated by the AD9054
is static (not related to conversion rate) so the penalty for clock-
ing at twice the desired rate is not high.
Refer ence
T he AD9054 internal reference, VREF, provides a simple, cost
effective reference for many applications. It exhibits reasonable
accuracy and excellent stability over power supply and tempera-
ture variations. T he VREF OUT pin can simply be strapped to
the VREF IN pin. T he internal reference can be used to drive
additional loads (up to several mA), including multiple A/D con-
verters as might be required in a triple video converter application.
If the user has selected Single Channel Mode (DEMUX =
HIGH), the eight-bit data word is directed to the Channel A
output bank. Data are strobed to the output on the rising edge
of the ENCODE input with four pipeline delays. If the user has
selected Dual Channel Mode (DEMUX = LOW) the data are
alternately directed between the A and B output banks and have
five pipeline delays. At power-up, the N sample data can ap-
pear at either the A or B port. T o align the data in a known
state the user must strobe DAT A SYNC (DS, DS) per the
conditions described in the T iming section.
When an external reference is desired for accuracy or other
requirements, the AD9054 should be driven directly by the
external reference source connected to pin VREF IN (VREF
OUT can be left floating). T he external reference can be set to
2.5 V ± 0.25 V. If VREF IN is raised by 10% (set to 2.75 V) the
analog full-scale range will increase by 10% to 1.024 × 1.1 =
1.1264 V. T he new input range will then be AIN ±0.5632 V.
Gr aphics Applications
T he high bandwidth and low power of the AD9054 make it
very attractive for applications that require the digitization of
presampled waveforms, wherein the input signal rapidly slews
from one level to another and is relatively stable for a period of
time. Examples of these include digitizing the output of com-
puter graphic display systems and very high speed solid state
imagers.
D igital Inputs
SNR performance is directly related to the sampling clock sta-
bility in A/D converters, particularly for high input frequencies
and wide bandwidths. A low jitter clock (<10 ps @ 100 MHz)
is essential for optimum performance when digitizing signals
that are not presampled.
T hese applications require the converter to process inputs with
frequency components well in excess of the sampling rate (often
with subnanosecond rise times), after which the A/D must settle
and sample the input in well under one pixel time. T he archi-
tecture of the AD9054 is vastly superior to older flash architec-
tures, which not only exhibit excessive input capacitance (which
is very hard to drive) but can make major errors when fed a very
ENCODE and Data Select (DS) can be driven differentially or
single-ended. For single-ended operation, the complement
inputs (ENCODE, DS) are internally biased to VDD/3 (~1.5 V)
by a high impedance on-chip resistor divider (Figure 5), but
they may be externally driven to establish an alternate threshold
if desired. A 0.1 µF decoupling capacitor to ground is sufficient
to maintain a threshold appropriate for T T L or CMOS logic.
REV. 0
–11–
AD9054
When driven differentially, ENCODE and DS will accommo-
date differential signals centered between 1.5 V and 4.5 V with
a total differential swing ≥800 mV (VID ≥ 400 mV).
VREF OUT
VREF IN
AIN
0.1F
A PORT
Note the 6-diode clock input protection circuitry in Figure 5.
T his limits the differential input voltage to ~ ±2.1 V. When the
diodes turn on, current is limited by the 300 Ω series resistor.
Exceeding 2.1 V across the differential inputs will have no im-
pact on the performance of the converter, but be aware of the
clock signal distortion that may be produced by the nonlinear
impedance at the converter.
AD9054
1k⍀
AIN
VIN
0.1F
+5V
DEMUX
DS
ENC ENC
0.1F
DS
V
IH D
IC M
CLOCK
ENC
NC
V
V
ID
CLOCK
ENC
CLOCK
NC = NO CONNECT
V
IL D
Figure 35. Single Port Mode—AC-Coupled Input—Single-
Ended Encode
a. Driving Differential Inputs Differentially
D ual P or t Mode
V
IH D
CLOCK
ENC
In Dual Port Mode (DEMUX = LOW), the conversion results
are alternated between the two output ports (Figure 2). T his
limits the data output rate at either port to 1/2 the conversion
rate (ENCODE), and supports conversion at up to 200 MSPS
with T T L/CMOS compatible interfaces. Dual Channel Mode is
required for guaranteed operation above 100 MSPS, but may be
enabled at any specified conversion rate.
V
ID
V
IC M
ENC
0.1F
V
IL D
b. Driving Differential Inputs Single-Endedly
Figure 34. Input Signal Level Definitions
T he multiplexing is controlled internally via a clock divider,
which introduces a degree of ambiguity in the port assignments.
Figure 2 illustrates that, prior to synchronization, either Port A
or Port B may produce the even or odd samples. T his is re-
solved by exercising the Data Sync (DS) control, a differential
input (identical to the ENCODE input), which facilitates opera-
tion at high speed.
Single P or t Mode
When operated in a Single Port mode (DEMUX = HIGH), the
timing of the AD9054 is similar to any high speed A/D Con-
verter (Figure 1).
A sample is taken on every rising edge of ENCODE, and the
resulting data is produced on the output pins following the
FOURT H rising edge of ENCODE after the sample was taken
(four pipeline delays). T he output data are valid tPD after the
rising edge of ENCODE, and remain valid until at least tV after
the next rising edge of ENCODE.
At least once after power-up, and prior to using the conversion
data, the part needs to be synchronized by a falling edge (or a
positive-going pulse) on DS (observing setup and hold times
with respect to ENCODE). If the converter’s internal timing is
in conflict with the DS signal when it is exercised, then two data
samples (one on each port) are corrupted as the converter is
resynchronized. T he converter then produces data with a
known phase relationship from that point forward.
T he maximum clock rate is specified as 100 MSPS. T his is
recommended because the guaranteed output data valid time
equals the Clock Period (1/fS) minus the Output Propagation
Delay (tPD) plus the Output Valid T ime (tV), which comes to
4.8 ns at 100 MHz. T his is about as fast as standard logic is able
to capture the data with reasonable design margins. The AD9054
will operate faster in single-channel mode if you are able to
capture the data.
Note that if the converter is already properly synchronized, the
DS pulse has no effect on the output data. T his allows the con-
verter to be continuously resynchronized by a pulse at 1/2 the
ENCODE rate. T his signal is often available within a system, as
it represents the master clock rate for the demultiplexed output
data. Of course, a single DS signal may be used to synchronize
multiple A/D converters in a multichannel system.
When operating in Single-Channel Mode, the outputs at Port B
are held static in a random state.
Figure 35 shows the AD9054 used in single-channel output
mode. The analog input (±0.5 V) is ac coupled and the ENCODE
input is driven by a T T L level signal. T he chip’s internal refer-
ence is used.
Applications that call for the AD9054 to be synchronized at
power-up or only periodically during calibration/reset (i.e., valid
data is not required prior to synchronization), need only be
concerned with the timing of the falling edge of DS. T he falling
edge of DS must satisfy the setup time defined by Figure 2 and
–12–
REV. 0
AD9054
the specification table. In this case the DS hold time specifica-
tion on the rising edge can be ignored.
In Dual Channel Mode, the converted data is produced five
clock cycles after the rising edge of ENCODE on which the
sample is taken (five pipeline delays).
Applications that will continuously update the synchronization
command need to treat the DS signal as a pulse and satisfy
timing requirements on both rising and falling edges. It is easiest
to consider the DS signal in this case to be a pulse train at one
half the encode rate, the positive pulse nominally bracketing the
ENCODE falling edge on alternate cycles as shown in the tim-
ing diagram (Figure 2). T he falling/rising edge of DS has to
satisfy a minimum setup time (TSDS) before the rising/falling
edge of ENCODE; similarly, the rising/falling edge of DS has to
satisfy a minimum hold time (THDS) relative to the rising/falling
edge of ENCODE. DS can fall a minimum of TH DS after
ENCODE falls and a maximum of T SDS before the next
ENCODE rises. DS can rise a minimum of TH DS after
ENCODE rises and a maximum of TSDS before ENCODE
falls. T his timing requirement produces a tight timing window
at higher encode rates. Synchronization by a single reset edge
results in a simpler timing solution in many applications. For
example, synchronization may be provided at the beginning of
each graphics line or frame.
VREF OUT
0.1F
VREF IN
A PORT
AIN
'573
AD9054
1k⍀
AIN
VIN
0.1F
B PORT
DEMUX
DS
ENC ENC
0.1F
DS
DS
NC
CLOCK
'74
DIVIDE
BY 2
T he data are presented at the output of the AD9054 in a ping-
pong (alternating) fashion to optimize the performance of the
converter. It may be aligned for presentation as sixteen bits in
parallel by adding a register stage to the output.
NC = NO CONNECT
Figure 36. Dual Port Mode—Aligned Output Data
In Figure 36, the converter is operating in Dual Port Mode,
with data coming alternately out of Port A and Port B. T he
figure illustrates how the output data may be aligned with an
output latch to produce a 16-bit output at 1/2 the conversion
clock rate. T he Data Sync input must be properly exercised to
time the A Port with the synchronizing latch.
REV. 0
–13–
AD9054
EVALUATIO N BO ARD
Voltage Refer ence
T he AD9054 evaluation board offers an easy way to test the
AD9054. It provides dc biasing for the analog input, generates
the latch clocks for both full speed and demuxed modes, and in-
cludes a reconstruction DAC. The board has several different
modes of operation, and is shipped in the following configuration:
T he AD9054 has an internal 2.5 V voltage reference. An exter-
nal reference may be employed instead. T he evaluation board is
configured for the internal reference. T o use an external refer-
ence, connect it to the (VREF) pin on the power connector and
move jumper S102.
• DC-Coupled Analog Input
• Demuxed Outputs
• Differential Clocks
Single P or t Mode
Single Port Mode sets the AD9054 to produce data on every
clock cycle on output port A only. T o test in this mode, jumper
S104 should be set to single channel and S106 and S107 must
be set to F (for Full). T he maximum speed in single port mode
is 100 MSPS.
• Internal Voltage Reference.
VREF EXT
DC BIAS
S102
D ual P or t Mode
AIN
S103
VREF OUT
VREF IN
AIN
Dual Port or half speed output mode sets the ADC to produce
data alternately on Port A and Port B. In this mode, the reset
function should be implemented. T o test in this mode, set
jumper S104 to Dual Channel, and set S106 and S107 to D (for
Dual Port). T he maximum speed in this mode is 200 MSPS.
A PORT
A PORT
'574
'574
50⍀
AD9054
AIN
RESET
BUTTON
5V
RESET
D
DEMUX
RESET drives the AD9054’s Data Sync (DS) pins. When
operating in Single Port Mode, RESET is not used. In Dual-
Channel Mode it is needed for two reasons: to synchronize the
timing of Port A data and Port B data with a known clock edge,
as described in the data sheet, and to synchronize the evaluation
board’s latch clocks with the data coming out of the AD9054.
Reset can be driven in two ways: by pushing the reset button on
the board, or externally, with a T T L pulse through connector J5
or J6.
D FF
C
S104
CLK A
DS
ENC ENC
DS
S105
CLK B
DAC
ENC
50⍀
50⍀
ENC
CLK A
CLOCKING
ENC
CLK B
D AC O ut
ENC
T he DAC output is a representation of the data on output Port
A only. Output Port B is not reconstructed.
Tr oubleshooting
If the board does not seem to be working correctly, try the fol-
lowing:
Figure 37. PCB Block Diagram
Analog Input
T he evaluation board accepts a 1 V input signal centered at
ground. T he board’s input circuitry then biases this signal to
+2.5 V in one of two ways:
•
•
•
Check that all jumpers are in the correct position for the
desired mode of operation.
Push the reset button. T his will align the 9054’s data output
with the half speed latch clocks.
1. DC-coupled through an AD9631 op amp; this is the mode in
which it is shipped. Potentiometer R7 provides adjustment
of the bias voltage.
Switch the jumper S105 from A-R to R-B or vice-versa, then
push the reset button. In demuxed mode, this will have the
effect of inverting the half speed latch clocks.
2. AC-coupled through C1.
T hese two modes are selected by jumpers S101 and S103. For
dc coupling, the S101 jumper is connected between the two left
pins and the S103 jumper is connected between the two lower
pins. For ac coupling, the S101 jumper is connected between
the two right pins and the S103 jumper is connected between
the two upper pins.
•
At high encode rates, the evaluation board’s clock generation
circuitry is sensitive to the +5 V digital power supply. At
high encode rates, the +5 V digital power should be kept
below +5.2 V. T his is an evaluation board sensitivity and
not an AD9054 sensitivity.
T he AD9054 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warran-
ties, express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.
ENCO D E
T he AD9054 ENCODE input can be driven two ways:
1. Differential T T L, CMOS, or PECL; it is shipped in this
mode.
2. Single-ended T T L or CMOS. T o use in this mode, remove
R11, the 50 Ω chip resistor located next to the ENCODE
input, and insert a 0.1 µF ceramic capacitor into the C5 slot.
C5 is located between the ENC connector and the ENCODE
input to the DUT and is marked on the back side of the
board. In this mode, ENCODE is biased with internal resis-
tors to 1.5 V, but it can be externally driven to any dc voltage.
–14–
REV. 0
AD9054
( L S B )
D B 0
S L E E P
R E F L O
D B 1
D B 2
D B 3
D B 4
D B 5
D B 6
D B 7
D B 8
D B 9
R E F I O
F S A D J
C O M P 1
C O M P 2
A V D D
D V D D
D B 4
D B 5
D B 6
D B 7
D A 3
D A 4
D A 5
D A 6
D A 7
G N D
V D D
G N D
V D D
V D D
G N D
G N D
+ 5 V A
G N D
+ 5 V A
+ 5 V A
G N D
G N D
V D D
G N D
V D D
G N D
+ 5 V A
G N D
+ 5 V A
Figure 38. Evaluation Board Schem atic
–15–
REV. 0
AD9054
Figure 39. Assem bly—Top View
Figure 41. Conductors—Top View
Figure 42. Conductors—Bottom View
Figure 40. Assem bly—Bottom View
–16–
REV. 0
AD9054
BILL O F MATERIALS
GS00104 REV. B
ITEM
QTY
P ART NUMBER
REFERENCE
D ESCRIP TIO N
MFG/D ISTRIBUTO R
11
30
GRM40Z5U104M050BL
C1, C2, C4, C6–8,
C10–C22, C24–C29,
C31–C35
0.1 µF CER CHIP CAP 0805
T T I
12
13
14
15
16
17
18
19
10
1
P10FBK-ND
R5
10 Ω SURFACE MT RES 1206
100 Ω SURFACE MT RES 1206
10 µF T ANT ALUM CHIP CAP
140 Ω SURFACE MT RES 1206
1 kΩ SURFACE MT RES 1206
2 kΩ SURFACE MT RES 1206
1k T RIM POT T OP ADJ, 25 T URN
37P D CONN RT ANG PCMT FEM
49.9 Ω SURFACE MT RES 1206
DIGI-KEY
DIGI-KEY
T T I
21
4
P100FBK-ND
T 491C106M016AS
P140FBK-ND
P1KFBK-ND
P2KFBK-ND
3296W-102-ND
K44-C37S-QJ
P49.9FBK-ND
R3, R9, R21–R39
C3, C9, C23, C30
2
R2, R4
DIGI-KEY
DIGI-KEY
DIGI-KEY
DIGI-KEY
CENT URY ELEC
DIGI-KEY
1
R12
3
R6, R8, R14
1
R7
J6
1
5
R1, R10, R11,
R15, R16
11
1
CSC06A-01-511G
51F54113
RP1
510 Ω 6P BUSED RES NET WORK
8291Z 3-PIN T ERMINAL BLOCK
8291Z 2-PIN T ERMINAL BLOCK
BNC COAX CONN PCMT 5 LEAD
DIP-16 DUAL D FLIP-FLOP
DIP-16 QUAD ECL T O T T L T RANS
SO-14 FAST T T L DUAL D FLIP-FLOP
HEADER ST RIP 20P GOLD MALE
40P HEADER
T T I
12
1
T B1
NEWARK
13
1
51F54112
T B1
NEWARK
14
4
AMP-227699-2
MC10H131P
MC10H125P
74F74SC-ND
T SW-120-08-G-S
90F3987
J1–J4
T IME ELEC
15
1
U6
HAMILT ON/HALLMARK
HAMILT ON/HALLMARK
DIGI-KEY
16
1
U7
17
1
U2
18
1
J5
SAMT EC
ALT :
19
1/2
1
J5
NEWARK
AD96685BR
S90F9280
U3
HIGH SPEED COMP SOIC-16
SHORT ING JUMPER
ANALOG DEVICES, INC.
NEWARK
20
7
S101–S107
S101–S107, GND
21
8
89F4700
3-PIN HEADER (DIVIDE 1 OF T HE
8 FOR 3 GND HOLES)
NEWARK
22
23
24
25
26
2
1
1
1
1
MC74F574DW
AD9631AR
U4, U5
U1
SO-20 OCT AL D T YPE FLIP-FLOP
SOIC-8 OP AMP
HAMILT ON/HALLMARK
ANALOG DEVICES, INC.
ANALOG DEVICES, INC.
ANALOG DEVICES, INC.
DIGI-KEY
AD9760AR
U8
10-BIT CMOS DAC SOIC-28
T QFP-44 DUAL 8-BIT ADC
AD9054ST
UA1
B1
P8002SCT -ND
SURFACE MOUNT MOMENT ARY
PUSHBUT T ON
27
4
90F1533
–
BUMPON PROT ECT IVE BUMPER
NEWARK
PART S NOT ON BILL OF MAT ERIALS, AND NO T T O BE INST ALLED: C5, C36, C37, R17–R20.
REV. 0
–17–
AD9054
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
44-Lead P lastic Thin Quad Flatpack (TQFP )
(ST-44)
0.063 (1.60)
MAX
0.472 (12.00) SQ
0.030 (0.75)
0.018 (0.45)
33
23
34
22
SEATING
PLANE
0.394
(10.0)
SQ
TOP VIEW
(PINS DOWN)
44
12
1
11
0.006 (0.15)
0.002 (0.05)
0.018 (0.45)
0.012 (0.30)
0.031 (0.80)
BSC
0.057 (1.45)
0.053 (1.35)
–18–
REV. 0
–19–
–20–
相关型号：
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