首页 |元器件品牌

AD9102BCPZ [ADI]

Low Power, 14-Bit, 180 MSPS, Digital-to-Analog Converter and Waveform Generator; 低功耗， 14位， 180 MSPS ，数位类比转换器和波形发生器
AD9102BCPZ
型号： AD9102BCPZ
厂家： ADI    ADI
描述：

Low Power, 14-Bit, 180 MSPS, Digital-to-Analog Converter and Waveform Generator
低功耗， 14位， 180 MSPS ，数位类比转换器和波形发生器

转换器
文件： 总36页 (文件大小：695K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
Low Power, 14-Bit, 180 MSPS, Digital-to-Analog  
Converter and Waveform Generator  
Data Sheet  
AD9102  
The DDS is a 14-bit output, up to 180 MSPS master clock sine  
wave generator with a 24-bit tuning word, allowing 10.8 Hz/LSB  
frequency resolution.  
FEATURES  
On-chip 4096 × 14-bit pattern memory  
On-chip DDS  
Power dissipation @ 3.3 V, 4 mA output  
96.54 mW @ 180 MSPS  
Sleep mode: <5 mW @ 3.3 V  
Supply voltage: 1.8 V to 3.3 V  
SFDR to Nyquist  
87 dBc @ 10 MHz output  
Phase noise @ 1 kHz offset, 180 MSPS, 8 mA: −150 dBc/Hz  
Differential current outputs: 8 mA max @ 3.3 V  
SRAM data can include directly generated stored waveforms,  
amplitude modulation patterns applied to DDS outputs, or DDS  
frequency tuning words.  
An internal pattern control state machine lets the user program  
the pattern period for the DAC as well the start delay within the  
pattern period for the signal output on the DAC .  
A SPI interface is used to configure the digital waveform  
generator and load patterns into the SRAM.  
Small footprint, 32-lead, 5 mm × 5 mm LFCSP with 3.6 mm ×  
3.6 mm exposed paddle, and Pb-free package  
A gain adjustment factor and an offset adjustment are applied to  
the digital signal on their way into the DAC.  
APPLICATIONS  
The AD9102 offers exceptional ac and dc performance and  
supports DAC sampling rates of up to 180 MSPS.  
Medical instrumentation  
Portable instrumentation  
The flexible power supply operating range of 1.8 V to 3.3 V and  
low power dissipation of the AD9102 make it well suited for  
portable and low power applications.  
Signal generators, arbitrary waveform generators  
Automotive radar  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
The AD9102 TxDAC® and waveform generator is a high perfor-  
mance digital-to-analog converter (DAC) integrating on-chip  
pattern memory for complex waveform generation with a direct  
digital synthesizer (DDS).  
1. High Integration.  
On-chip DDS and 4096 × 14 pattern memory.  
2. Low Power.  
Power-down mode provides for low power idle periods.  
FUNCTIONAL BLOCK DIAGRAM  
1V  
AD9102  
SPI  
INTERFACE  
10kΩ  
AGND  
BAND  
GAP  
STOP ADDR  
START ADDR  
START DELAY  
R
SET1  
16kΩ  
DAC  
TIMERS + STATE MACHINE  
ADDRESS  
TRIGGER  
I
REF  
100µA  
IOUTP  
IOUTN  
AVDD1  
AVDD2  
DAC  
GAIN  
OFFSET  
SRAM  
PHASE  
TUNING WORD  
DAC CLOCK  
DDS  
DDS  
1.8V  
LDO  
CLOCK  
DIST  
1.8V  
LDOs  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2013 Analog Devices, Inc. All rights reserved.  
 
 
 
 
 
AD9102  
Data Sheet  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Analog Current Outputs ........................................................... 19  
Setting IOUTFS, DAC Gain ........................................................... 19  
Automatic IOUTFS Calibration..................................................... 19  
Clock Input.................................................................................. 20  
DAC Output Clock Edge........................................................... 21  
Generating Signal Patterns........................................................ 21  
Pattern Generator Programming ............................................. 21  
DAC Input DataPaths ................................................................ 22  
DOUT Function......................................................................... 22  
Direct Digital Synthesizer (DDS)............................................. 23  
SRAM........................................................................................... 23  
Sawtooth Generator ................................................................... 23  
Pseudo Random Signal Generator........................................... 24  
DC Constant ............................................................................... 24  
Power Supply Notes ................................................................... 24  
Power Down Capabilities.......................................................... 24  
Applications..................................................................................... 25  
Signal Generation Examples..................................................... 25  
Register Map ................................................................................... 26  
Register Descriptions..................................................................... 28  
Outline Dimensions....................................................................... 36  
Ordering Guide............................................................................... 36  
Applications....................................................................................... 1  
General Description......................................................................... 1  
Product Highlights ........................................................................... 1  
Functional Block Diagram .............................................................. 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
DC Specifications (3.3 V)............................................................ 3  
DC Specifications (1.8 V)............................................................ 4  
Digital Timing Specifications (3.3 V)........................................ 4  
Digital Timing Specifications (1.8 V)........................................ 5  
Input/Output Signal Specifications............................................ 5  
AC Specifications (3.3 V) ............................................................ 6  
AC Specifications (1.8 V) ............................................................ 6  
Power Supply Voltage Inputs and Power Dissipation.............. 7  
Absolute Maximum Ratings............................................................ 8  
Thermal Resistance ...................................................................... 8  
ESD Caution.................................................................................. 8  
Pin Configuration and Function Descriptions............................. 9  
Typical Performance Characteristics ........................................... 11  
Terminology .................................................................................... 16  
Theory of Operation ...................................................................... 17  
SPI Port ........................................................................................ 18  
DAC Transfer Function ............................................................. 19  
REVISION HISTORY  
1/13—Revision 0: Initial Version  
Rev. 0 | Page 2 of 36  
 
Data Sheet  
AD9102  
SPECIFICATIONS  
DC SPECIFICATIONS (3.3 V)  
TMIN to TMAX; AVDD = 3.3 V; DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1 and DLDO2; IOUTFS = 8 mA; maximum sample rate,  
unless otherwise noted.  
Table 1.  
Parameter  
Min  
Typ  
Max  
Unit  
RESOLUTION  
14  
Bits  
ACCURACY @ 3.3 V  
Differential Nonlinearity (DNL)  
Integral Nonlinearity (INL)  
DAC OUTPUT  
1.4  
2.0  
LSB  
LSB  
Offset Error  
0.00025  
% of FSR  
% of FSR  
Gain Error Internal Reference—No Automatic IOUTFS Calibration  
Full-Scale Output Current  
3.3 V  
−1.0  
2
+1.0  
8
4
mA  
MΩ  
V
Output Resistance  
200  
Output Compliance Voltage  
DAC TEMPERATURE DRIFT  
Gain with Internal Reference  
Internal Reference Voltage  
REFERENCE OUTPUT  
−0.5  
+1.0  
251  
119  
ppm/°C  
ppm/°C  
Internal Reference Voltage with AVDD = 3.3 V  
Output Resistance  
0.8  
0.1  
1.0  
10  
1.2  
V
kΩ  
REFERENCE INPUT  
Voltage Compliance  
1.25  
V
Input Resistance External Reference Mode  
1
MΩ  
Rev. 0 | Page 3 of 36  
 
 
 
AD9102  
Data Sheet  
DC SPECIFICATIONS (1.8 V)  
TMIN to TMAX; AVDD = 1.8 V; DVDD = DLDO1 = DLDO2 = 1.8 V; CLKVDD = CLDO = 1.8 V; IOUTFS = 4 mA; maximum sample rate, unless  
otherwise noted.  
Table 2.  
Parameter  
Min  
Typ  
Max  
Unit  
RESOLUTION  
14  
Bits  
ACCURACY @ 1.8 V  
Differential Nonlinearity (DNL)  
Integral Nonlinearity (INL)  
DAC OUTPUTS  
1.5  
1.4  
LSB  
LSB  
Offset Error  
0.00025  
% of FSR  
% of FSR  
Gain Error Internal Reference—No Automatic IOUTFS Calibration  
Full-Scale Output Current  
VCC = 1.8 V  
−1.0  
2
+1.0  
4
4
mA  
MΩ  
V
Output Resistance  
200  
Output Compliance Voltage  
DAC TEMPERATURE DRIFT  
Gain  
−0.5  
+1.0  
228  
131  
ppm/°C  
ppm/°C  
Reference Voltage  
REFERENCE OUTPUT  
Internal Reference Voltage with AVDD = 1.8 V  
Output Resistance  
0.8  
0.1  
1.0  
10  
1.2  
V
kΩ  
REFERENCE INPUT  
Voltage Compliance  
1.25  
V
Input Resistance External Reference Mode  
1
MΩ  
DIGITAL TIMING SPECIFICATIONS (3.3 V)  
TMIN to TMAX; AVDD = 3.3 V; DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1, and DLDO2; IOUTFS = 8 mA; maximum sample rate,  
unless otherwise noted.  
Table 3.  
Parameter  
Min  
180  
80  
Typ  
Max  
Unit  
DAC CLOCK INPUT (CLKIN)  
Maximum Clock Rate  
MSPS  
SERIAL PERIPHERAL INTERFACE  
Maximum Clock Rate (SCLK)  
Minimum Pulse Width High  
Minimum Pulse Width Low  
Setup Time SDIO to SCLK  
Hold Time SDIO to SCLK  
MHz  
ns  
ns  
ns  
ns  
6.25  
6.25  
4.0  
5.0  
Output Data Valid SCLK to SDO/SDI2/DOUT or SDIO  
Setup Time CS to SCLK  
6.2  
ns  
ns  
4.0  
Rev. 0 | Page 4 of 36  
 
 
 
 
Data Sheet  
AD9102  
DIGITAL TIMING SPECIFICATIONS (1.8 V)  
TMIN to TMAX; AVDD = 1.8 V; DVDD = DLDO1 = DLDO2 = 1.8 V; CLKVDD = CLDO = 1.8 V; IOUTFS = 4 mA; maximum sample rate, unless  
otherwise noted.  
Table 4.  
Parameter  
Min  
180  
80  
Typ  
Max  
Unit  
DAC CLOCK INPUT (CLKIN)  
Maximum Clock Rate  
MSPS  
SERIAL PERIPHERAL INTERFACE  
Maximum Clock Rate (SCLK)  
Minimum Pulse Width High  
Minimum Pulse Width Low  
Setup Time SDIO to SCLK  
Hold Time SDIO to SCLK  
MHz  
ns  
ns  
ns  
ns  
6.25  
6.25  
4.0  
5.0  
Output Data Valid SCLK to SDO/SDI2/DOUT or SDIO  
Setup Time CS to SCLK  
8.8  
ns  
ns  
4.0  
INPUT/OUTPUT SIGNAL SPECIFICATIONS  
Table 5.  
Parameter  
Test Conditions/Comments  
Min  
Typ  
Max  
Unit  
CMOS INPUT LOGIC LEVEL (SCLK, CS, SDIO,  
SDO/SDI2/DOUT, RESET, TRIGGER)  
Input VIN Logic High  
DVDD = 1.8 V  
DVDD = 3.3 V  
DVDD = 1.8 V  
DVDD = 3.3 V  
1.53  
2.475  
V
V
V
V
Input VIN Logic Low  
0.27  
0.825  
CMOS OUTPUT LOGIC LEVEL (SDIO, SDO/SDI2/DOUT)  
Output VOUT Logic High  
DVDD = 1.8 V  
DVDD = 3.3 V  
DVDD = 1.8 V  
DVDD = 3.3 V  
1.79  
3.28  
V
V
V
V
Output VOUT Logic Low  
0.25  
0.625  
DAC CLOCK INPUT (CLKP, CLKN)  
Minimum Peak-to-Peak Differential Input Voltage,  
VCLKP/VCLKN  
150  
mV  
Maximum Voltage at VCLKP or VCLKN  
Minimum Voltage at VCLKP or VCLKN  
Common-Mode Voltage  
VDVDD  
VDGND  
0.9  
V
V
V
Generated on Chip  
Rev. 0 | Page 5 of 36  
 
 
 
AD9102  
Data Sheet  
AC SPECIFICATIONS (3.3 V)  
TMIN to TMAX; AVDD = 3.3 V; DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1, and DLDO2; IOUTFS = 8 mA; maximum sample rate,  
unless otherwise noted.  
Table 6.  
Parameter  
Min  
Typ  
Max  
Unit  
SPURIOUS FREE DYNAMIC RANGE  
fDAC = 180 MSPS, fOUT = 10 MHz  
fDAC = 180 MSPS, fOUT = 50 MHz  
TWO-TONE INTERMODULATION DISTORTION (IMD)  
fDAC = 180 MSPS, fOUT = 10 MHz  
fDAC = 180 MSPS, fOUT = 50 MHz  
NSD  
87  
67  
dBc  
dBc  
88  
68  
dBc  
dBc  
fDAC = 180 MSPS, fOUT = 50 MHz  
PHASE NOISE @ 1 kHz FROM CARRIER  
fDAC = 180 MSPS, fOUT = 10 MHz  
DYNAMIC PERFORMANCE  
−163  
−150  
dBm/Hz  
dBc/Hz  
Output Settling Time, Full-Scale Output Step (to 0.1%)1  
Trigger to Output Delay, fDAC = 180 MSPS2  
Rise Time, Full-Scale Swing1  
31.2  
96  
3.25  
3.26  
ns  
ns  
ns  
ns  
Fall Time, Full-Scale Swing1  
1 Based on 85 Ω resistors from DAC output terminals to ground.  
2 Start delay = 0 fDAC clock cycles.  
AC SPECIFICATIONS (1.8 V)  
TMIN to TMAX; AVDD = 1.8 V; DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO = 1.8 V; IOUTFS = 4 mA; maximum sample rate, unless  
otherwise noted.  
Table 7.  
Parameter  
Min  
Typ  
Max  
Unit  
SPURIOUS FREE DYNAMIC RANGE (SFDR)  
fDAC = 180 MSPS, fOUT = 10 MHz  
fDAC = 180 MSPS, fOUT = 50 MHz  
TWO-TONE INTERMODULATION DISTORTION (IMD)  
fDAC = 180 MSPS, fOUT = 10 MHz  
fDAC = 180 MSPS, fOUT = 50 MHz  
NSD  
84  
73  
dBc  
dBc  
91  
86  
dBc  
dBc  
fDAC = 180 MSPS, fOUT = 50 MHz  
PHASE NOISE @ 1kHz FROM CARRIER  
fDAC = 180 MSPS, fOUT = 10 MHz  
DYNAMIC PERFORMANCE  
Output Settling Time (to 0.1%)1  
Trigger to Output Delay, fDAC = 180 MSPS22  
Rise Time1  
−163  
−150  
dBm/Hz  
dBc/Hz  
31.2  
96  
3.25  
3.26  
ns  
ns  
ns  
ns  
Fall Time1  
1 Based on 85 Ω resistors from DAC output terminals to ground.  
2 Start delay = 0 fDAC clock cycles.  
Rev. 0 | Page 6 of 36  
 
 
 
 
Data Sheet  
AD9102  
POWER SUPPLY VOLTAGE INPUTS AND POWER DISSIPATION  
Table 8.  
Parameter  
Test Conditions/Comments  
Min  
Typ  
Max  
Unit  
ANALOG SUPPLY VOLTAGES  
AVDD1, AVDD2  
CLKVDD  
1.7  
1.7  
1.7  
3.6  
3.6  
1.9  
V
V
V
CLDO  
On-chip LDO not in use  
On-chip LDO not in use  
DIGITAL SUPPLY VOLTAGES  
DVDD  
DLDO1, DLDO2  
POWER CONSUMPTION  
1.7  
1.7  
3.6  
1.9  
V
V
AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V,  
internal CLDO, DLDO1, AND DLDO2  
fDAC = 180 MSPS, Pure CW Sine Wave  
IAVDD  
12.5 MHz (DDS only)  
96.54  
7.67  
mW  
mA  
IDVDD  
DDS Only  
RAM Only  
DDS and RAM Only  
ICLKVDD  
CW sine wave output  
50% duty cycle FS pulse output  
50% duty cycle sine wave output  
17.73  
11.31  
14.6  
3.85  
4.73  
mA  
mA  
mA  
mA  
mW  
Power-Down Mode  
REF on, DACs sleep, CLK power down, external CLK  
and supplies on  
POWER CONSUMPTION  
AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V,  
CLKVDD = CLDO = 1.8 V  
fDAC = 180 MSPS, Pure CW Sine Wave  
IAVDD  
IDVDD  
12.5 MHz (DDS only)  
51.33  
7.54  
0.15  
mW  
mA  
mA  
IDLDO2  
DDS Only  
RAM Only  
DDS and RAM Only  
IDLDO1  
ICLKVDD  
ICLDO  
CW sine wave output  
50% duty cycle FS pulse output  
50% duty cycle sine wave output  
16.03  
10.07  
13.26  
1.129  
0.0096  
3.65  
mA  
mA  
mA  
mA  
mA  
mA  
mW  
Power-Down Mode  
REF on, DACs sleep, CLK power down, external CLK  
and supplies on  
1.49  
Rev. 0 | Page 7 of 36  
 
 
AD9102  
Data Sheet  
ABSOLUTE MAXIMUM RATINGS  
Table 9.  
THERMAL RESISTANCE  
θJA is specified for the worst-case conditions, that is, a device  
soldered in a standard circuit board for surface-mount  
packages. θJC is measured from the solder side (bottom) of the  
package.  
Parameter  
Rating  
AVDD1, AVDD2, DVDD to AGND, DGND, −0.3 V to +3.9 V  
CLKGND  
CLKVDD to AGND, DGND, CLKGND  
−0.3 V to +3.9 V  
CLDO, DLDO1, DLDO2 to AGND, DGND, −0.3 V to 2.2 V  
CLKGND  
Table 10. Thermal Resistance  
Package Type  
θJA  
θJB  
θJC  
Unit  
AGND to DGND, CLKGND  
DGND to AGND, CLKGND  
CLKGND to AGND, DGND  
CS, SDIO, SCLK, SDO/  
SDI2/DOUT, RESET, TRIGGER to  
DGND  
−0.3 V to +0.3 V  
−0.3 V to +0.3 V  
−0.3 V to +0.3 V  
−0.3 V to DVDD + 0.3 V  
32-Lead LFCSP with Exposed  
Paddle  
30.18 6.59  
3.84  
°C/W  
ESD CAUTION  
CLKP, CLKN to CLKGND  
REFIO to AGND  
IOUTP, IOUTN to AGND  
FSADJ, CAL_SENSE to AGND  
Junction Temperature  
Storage Temperature Range  
−0.3 V to CLKVDD + 0.3 V  
−1.0 V to AVDD + 0.3 V  
−0.3 V to DVDD + 0.3 V  
−0.3 V to AVDD + 0.3 V  
125°C  
−65°C to +150°C  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Rev. 0 | Page 8 of 36  
 
 
 
 
Data Sheet  
AD9102  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
SCLK  
SDIO  
DGND  
DLDO2  
DVDD  
1
2
3
4
5
6
7
8
24 CAL_SENSE  
23  
22 CLDO  
21 CLKP  
CLKVDD  
AD9102  
TOP VIEW  
20  
19  
CLKN  
CLKGND  
(Not to Scale)  
DLDO1  
SDO/SDI2/DOUT  
CS  
18 REFIO  
17 NC  
NOTES  
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.  
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY  
CONNECTED TO A COPPER GROUND PLANE FOR ENHANCED  
ELECTRICAL AND THERMAL PERFORMANCE.  
Figure 2. Pin Configuration  
Table 11. Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
1
2
3
4
SCLK  
SDIO  
DGND  
DLDO2  
SPI Clock Input.  
SPI Data Input/Output. Primary bidirectional data line for the SPI port.  
Digital Ground.  
1.8 V Internal Digital LDO1 Outputs. When the internal digital LDO1 is enabled, bypass this pin with a 0.1 μF  
capacitor.  
5
6
DVDD  
DLDO1  
3.3 V External Digital Power Supply. DVDD defines the level of the digital interface of the AD9102 (SPI interface).  
1.8 V Internal Digital LDO2 Outputs. When the internal digital LDO2 is enabled, bypass this pin with a 0.1 μF  
capacitor.  
7
SDO/SDI2/DOUT Digital I/O Pin.  
In 4-wire SPI mode (SDO), this pin outputs the data from the SPI.  
In double-SPI mode (SDI2), this pin is a second data input line for the SPI port that writes to the SRAM.  
In data out mode (DOUT), this terminal is a programmable pulse output.  
SPI Port Chip Select, Active Low.  
8
CS  
9
RESET  
NC  
NC  
AVDD2  
NC  
NC  
AGND  
NC  
NC  
REFIO  
CLKGND  
CLKN  
CLKP  
CLDO  
CLKVDD  
CAL_SENSE  
FSADJ  
Active Low Reset Pin. Resets registers to their default values.  
Not Connected. Do not connect to this pin.  
Not Connected. Do not connect to this pin.  
1.8 V to 3.3 V Power Supply Input.  
Not Connected. Do not connect to this pin.  
Not Connected. Do not connect to this pin.  
Analog Ground.  
Not Connected. Do not connect to this pin.  
Not Connected. Do not connect to this pin.  
DAC Voltage Reference Input/Output.  
Clock Ground.  
Clock Input, Negative Side.  
Clock Input, Positive Side.  
Clock Power Supply Output (Internal Regulator in Use), Clock Power Supply Input (Internal Regulator Bypassed).  
Clock Power Supply Input.  
Sense Input for Automatic IOUTFS Calibration.  
External Full-Scale Current Output Adjust for DAC or Full-Scale Current Output Adjust Reference for  
Automatic IOUTFS Calibration.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
AGND  
IOUTP  
IOUTN  
Analog Ground.  
DAC Current Output, Positive Side.  
DAC Current Output, Negative Side.  
Rev. 0 | Page 9 of 36  
 
AD9102  
Data Sheet  
Pin No.  
29  
30  
31  
32  
Mnemonic  
Description  
AVDD1  
NC  
NC  
TRIGGER  
EPAD  
1.8 V to 3.3 V Power Supply Input for DAC.  
Not Connected. Do not connect to this pin.  
Not Connected. Do not connect to this pin.  
Pattern Trigger Input.  
Exposed Pad. It is recommended that the exposed pad be thermally connected to a copper ground plane for  
enhanced electrical and thermal performance.  
Rev. 0 | Page 10 of 36  
Data Sheet  
AD9102  
TYPICAL PERFORMANCE CHARACTERISTICS  
AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1, and DLDO2.  
–50  
–55  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
–50  
–55  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
SFDR  
SECOND HARMONIC  
THIRD HARMONIC  
8mA  
4mA  
2mA  
0
10  
20  
30  
40  
50  
60  
70  
0
0
0
10  
20  
30  
40  
50  
60  
70  
70  
70  
fOUT (MHz)  
fOUT (MHz)  
Figure 3. SFDR, 2nd and 3rd Harmonics at IOUTFS = 8 mA vs. fOUT  
Figure 6. SFDR at Three IOUTFS Values vs. fOUT  
–50  
–50  
–55  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
–55  
SFDR  
SECOND HARMONIC  
THIRD HARMONIC  
+85°C  
+25°C  
–40°C  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
0
10  
20  
30  
40  
50  
60  
70  
10  
20  
30  
40  
50  
60  
fOUT (MHz)  
fOUT (MHz)  
Figure 4. SFDR, 2nd and 3rd Harmonics at IOUTFS = 4 mA vs. fOUT  
Figure 7. SFDR at Three Temperatures vs. fOUT  
–50  
–50  
–55  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
–55  
SFDR  
SECOND HARMONIC  
THIRD HARMONIC  
180MHz  
100MHz  
50MHz  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
0
10  
20  
30  
40  
50  
60  
70  
10  
20  
30  
40  
50  
60  
fOUT (MHz)  
fOUT (MHz)  
Figure 5. SFDR, 2nd and 3rd Harmonics at IOUTFS = 2 mA vs. fOUT  
Figure 8. SFDR at Three fDAC Values vs. fOUT  
Rev. 0 | Page 11 of 36  
 
AD9102  
Data Sheet  
MKR3 41.73MHz  
–90.031dBm  
–130  
–135  
–140  
–145  
–150  
–155  
–160  
–165  
–170  
REF –5dBm  
ATTEN 18dB  
1
2mA  
4mA  
8mA  
2
3
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
fOUT (MHz)  
START 0Hz  
VBW 5.6kHz  
X-AXIS  
STOP 80MHz  
SWEEP 3.076s (601pts)  
MARKER TRACE TYPE  
AMPLITUDE  
1
2
3
(1)  
(1)  
(1)  
FREQ  
FREQ  
FREQ  
13.87MHz –11.13dBm  
27.87MHz –88.70dBm  
41.73MHz –90.03dBm  
Figure 9. Output Spectrum, fOUT = 13.87 MHz  
Figure 12. NSD vs. fOUT, Three IOUTFS Values  
–130  
–135  
–140  
–145  
–150  
–155  
–160  
–165  
–170  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
50MHz  
100MHz  
180MHz  
+85°C  
+25°C  
–40°C  
0
10  
20  
30  
40  
50  
60  
70  
80  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
fOUT (MHz)  
fOUT (MHz)  
Figure 10. IMD vs. fOUT, Three fDAC Values  
Figure 13. NSD vs. fOUT at Three Temperatures  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
2mA  
4mA  
8mA  
2mA  
4mA  
8mA  
–0.2  
–0.4  
–0.6  
0
2000 4000 6000 8000 10000 12000 14000 16000 18000  
CODE  
0
10  
20  
30  
40  
50  
60  
70  
80  
fOUT (MHz)  
Figure 11. IMD vs. fOUT, Three IOUTFS Values  
Figure 14. DNL, Three IOUTFS Values  
Rev. 0 | Page 12 of 36  
Data Sheet  
AD9102  
1.5  
80  
90  
fS = 160MHz, 10MHz  
fS = 160MHz, 12MHz  
1.0  
100  
110  
120  
130  
140  
150  
160  
170  
180  
0.5  
0
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
2mA  
4mA  
8mA  
100  
1k  
10k  
100k  
1M  
10M  
0
2000 4000 6000 8000 10000 12000 14000 16000 18000  
CODE  
OFFSET (Hz)  
Figure 15. INL, Three IOUTFS Values  
Figure 16. Phase Noise vs. Offset  
Rev. 0 | Page 13 of 36  
AD9102  
Data Sheet  
AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1 . 8 V, CLKVDD = CLDO = 1.8 V  
–50  
–50  
–55  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
–55  
SFDR  
SECOND HARMONIC  
THIRD HARMONIC  
+85°C  
+25°C  
–40°C  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
0
10  
20  
30  
40  
50  
60  
70  
0
10  
20  
30  
40  
50  
60  
70  
fOUT (MHz)  
fOUT (MHz)  
Figure 17. SFDR, 2nd and 3rd Harmonics at IOUTFS = 4 mA vs. fOUT  
Figure 20. SFDR at Three Temperatures vs. fOUT  
–50  
–50  
–55  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
–55  
SFDR  
SECOND HARMONIC  
THIRD HARMONIC  
180MHz  
100MHz  
50MHz  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
0
10  
20  
30  
40  
50  
60  
70  
0
10  
20  
30  
40  
50  
60  
70  
fOUT (MHz)  
fOUT (MHz)  
Figure 18. SFDR, 2nd and 3rd Harmonics at IOUTFS = 2 mA vs. fOUT  
Figure 21. SFDR at Three fDAC Values vs. fOUT  
MKR3 41.73MHz  
–90.563dBm  
–50  
–55  
–60  
–65  
–70  
REF –5dBm  
ATTEN 18dB  
1
4mA  
2mA  
–75  
–80  
–85  
–90  
2
3
–95  
–100  
0
10  
20  
30  
40  
50  
60  
70  
fOUT (MHz)  
START 0Hz  
MARKER TRACE TYPE  
VBW 5.6kHz  
X-AXIS  
13.87MHz –11.23dBm  
27.87MHz –88.79dBm  
41.73MHz –90.56dBm  
STOP 80MHz  
SWEEP 3.076s (601pts)  
AMPLITUDE  
1
2
3
(1)  
(1)  
(1)  
FREQ  
FREQ  
FREQ  
Figure 19. SFDR at Two IOUTFS Values vs. fOUT  
Figure 22. Output Spectrum, fOUT = 13.87 MHz  
Rev. 0 | Page 14 of 36  
Data Sheet  
AD9102  
–130  
–135  
–140  
–145  
–150  
–155  
–160  
–165  
–170  
–60  
–65  
50MHz  
100MHz  
180MHz  
+85°C  
+25°C  
–40°C  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
0
10  
20  
30  
40  
50  
60  
70  
80  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
fOUT (MHz)  
fOUT (MHz)  
Figure 23. IMD vs. fOUT, Three fOUT Values  
Figure 26. NSD vs. fOUT at Three Temperatures  
2.0  
1.5  
1.0  
0.5  
0
–60  
–65  
–70  
–75  
–80  
–85  
–90  
–95  
–100  
2mA  
4mA  
4mA  
2mA  
–0.5  
–1.0  
0
10  
20  
30  
40  
50  
60  
70  
80  
0
500 1000 1500 2000 2500 3000 3500 4000 4500  
CODE  
fOUT (MHz)  
Figure 24. IMD vs. fOUT, Two IOUTFS Values  
Figure 27. DNL, Two IOUTFS Values  
–130  
–135  
–140  
–145  
–150  
–155  
–160  
–165  
–170  
2.0  
1.5  
4mA  
2mA  
1.0  
0.5  
0
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
4mA  
2mA  
0
10  
20  
30  
40  
50  
60  
70  
80  
90  
0
500 1000 1500 2000 2500 3000 3500 4000 4500  
CODE  
fOUT (MHz)  
Figure 25. NSD vs. fOUT, Two IOUTFS Values  
Figure 28. INL, Two IOUTFS Values  
Rev. 0 | Page 15 of 36  
AD9102  
Data Sheet  
TERMINOLOGY  
Power Supply Rejection  
Linearity Error (Integral Nonlinearity or INL)  
INL is defined as the maximum deviation of the actual analog  
output from the ideal output, determined by a straight line  
drawn from zero to full scale.  
Power supply rejection is the maximum change in the full-scale  
output as the supplies are varied from nominal to minimum  
and maximum specified voltages.  
Settling Time  
Differential Nonlinearity (DNL)  
Settling time is the time required for the output to reach and  
remain within a specified error band about its final value,  
measured from the start of the output transition.  
DNL is the measure of the variation in analog value, normalized  
to full scale, associated with a 1 LSB change in digital input code.  
Monotonicity  
Glitch Impulse  
A digital-to-analog converter is monotonic if the output either  
increases or remains constant as the digital input increases.  
Asymmetrical switching times in a DAC give rise to undesired  
output transients that are quantified by a glitch impulse. It is  
specified as the net area of the glitch in picovolt-seconds (pV-s).  
Offset Error  
Offset error is the deviation of the output current from the ideal of  
zero. For IOUTP, 0 mA output is expected when the inputs are all  
0s. For IOUTN, 0 mA output is expected when all inputs are set to 1.  
Spurious-Free Dynamic Range (SFDR)  
SFDR is the difference, in decibels (dB), between the rms  
amplitude of the output signal and the peak spurious signal  
over the specified bandwidth.  
Gain Error  
Gain error is the difference between the actual and ideal output  
span. The actual span is determined by the output when all inputs  
are set to 1, minus the output when all inputs are set to 0. The  
ideal gain is calculated using the measured VREF. Therefore, the  
gain error does not include effects of the reference.  
Noise Spectral Density (NSD)  
Noise spectral density is the average noise power normalized to  
a 1 Hz bandwidth, with the DAC converting and producing an  
output tone.  
Output Compliance Voltage  
Output compliance voltage is the range of allowable voltage at  
the output of a current output DAC. Operation beyond the  
maximum compliance limits can cause either output stage  
saturation or breakdown, resulting in nonlinear performance.  
Temperature Drift  
Temperature drift is specified as the maximum change from the  
ambient (25°C) value to the value at either TMIN or TMAX. For  
offset and gain drift, the drift is reported in ppm of full-scale  
range (FSR) per °C. For reference drift, the drift is reported in  
ppm per °C.  
Rev. 0 | Page 16 of 36  
 
Data Sheet  
AD9102  
THEORY OF OPERATION  
1V  
AD9102  
SPI  
INTERFACE  
10kΩ  
AGND  
BAND  
GAP  
STOP ADDR  
START ADDR  
START DELAY  
R
SET1  
16kΩ  
DAC  
TRIGGER  
I
REF  
100µA  
TIMERS + STATE MACHINE  
ADDRESS  
IOUTP  
IOUTN  
AVDD1  
AVDD2  
DAC  
GAIN  
OFFSET  
SRAM  
PHASE  
TUNING WORD  
DAC CLOCK  
DDS  
DDS  
1.8V  
LDO  
CLOCK  
DIST  
1.8V  
LDOs  
Figure 29. AD9102 Block Diagram  
Figure 29 is a block diagram of the AD9102. The AD9102 has a  
single 14-bit current output DAC.  
Digital signals input to the 14-bit DAC are generated by on-chip  
digital waveform generation resources. The 14-bit samples are  
input to the DAC at the CLKP/CLKN sample rate from the  
digital datapath. The datapath includes gain and offset  
corrections and a digital waveform source selection multiplexer.  
Waveform sources are SRAM, direct digital synthesizer (DDS),  
DDS output amplitude modulated by SRAM data, sawtooth  
generator, dc constant, and pseudorandom sequence generator.  
The waveforms output by the source selection multiplexer have  
programmable pattern characteristics. The waveforms can be  
set up to be continuous, continuous pulsed (fixed pattern  
period and start delay within each pattern period), or finite  
pulsed (a set number of pattern periods are output, then the  
pattern stops).  
An on-chip band gap reference is included. Optionally, an off-  
chip voltage reference may be used. The full-scale DAC output  
current, also known as gain, is governed by the current, IREF. IREF  
is the current that flows through the IREF resistor. The IREF set  
resistor can be on or off chip at the user’s discretion. When the  
on-chip RSET resistor is in use, DAC gain accuracy can be  
improved by employing the built in automatic gain calibration  
capability. Automatic calibration can be used with the on-chip  
reference or an external REFIO voltage. A procedure for  
automatic gain calibration follows.  
The power supply rails for the AD9102 are AVDD for analog  
circuits, CLKVDD/CLKLDO for clock input receivers, and  
DVDD/DLDO1/DLDO2 for digital I/O and for the on-chip  
digital datapath. AVDD, DVDD, and CLKVDD can range from  
1.8 V to 3.3 V nominal. DLDO1, DLDO2, and CLDO run at  
1.8 V. If DVDD = 1.8 V, connect DLDO1 and DLDO2 to  
DVDD, with the on-chip LDOs disabled. All three supplies are  
provided externally in this case. If CLKVDD = 1.8 V, connect  
CLKVDD to CLDO with the on-chip LDOs enabled.  
Pulsed waveforms (finite or continuous) have a programmed  
pattern period and start delay. The waveform is present in each  
pulse period following the programmed pattern period start  
and the start delay.  
A SPI port enables loading of data into SRAM and  
programming of all the control registers inside the device.  
Rev. 0 | Page 17 of 36  
 
 
AD9102  
Data Sheet  
Writing to On-Chip SRAM  
SPI PORT  
The AD9102 includes an internal 4096 × 12 SRAM. The SRAM  
address space is 0x6000 to 0x6FFF of the AD9102 SPI address map.  
The AD9102 provides a flexible, synchronous serial communica-  
tions (SPI) port that allows easy interfacing to ASICs, FPGAs, and  
industry-standard microcontrollers. The interface allows read/write  
access to all registers that configure the AD9102 and to the on-chip  
SRAM. Its data rate can be up to the SCLK clock speed listed in  
Table 3 and Table 4.  
Double SPI for Write for SRAM  
The time to write data to the entire SRAM can be halved using  
the SPI access mode shown in Figure 32. The SDO/SDI2/  
DOUT line becomes a second serial data input line, doubling  
the achievable update rate of the on-chip SRAM. SDO/SDI2/  
DOUT is write only in this mode. The entire SRAM can be  
written in (2 + 2 × 4096) × 8/(2 × fSLCK)seconds.  
The SPI interface operates as a standard synchronous serial  
CS  
CS  
communication port.  
is a low true chip select. When  
goes true, SPI address and data transfer begin. The first bit  
coming from the SPI master on SDIO is a read write indicator  
(high for read, low for write). The next 15 bits are the initial  
register address. The SPI port automatically increments the  
SET WAVEFORM ADDRESS  
TO BE READ/WRITTEN  
WAVEFORM DATA TO BE WRITTEN  
CS  
SCLK  
CS  
register address if  
stays low beyond the first data-word  
allowing writes to or reads from a set of contiguous addresses.  
SDIO  
Table 12. Command Word  
MSB  
DB15  
R/W  
LSB  
WAVEFORM PATTERN  
ADDRESS1 = N  
WAVEFORM  
PATTERN DATA  
DB14 DB13 DB12  
A14 A13 A12  
…
DB2 DB1 DB0  
…
A2  
A1  
A0  
SDO/  
SDI2/  
DOUT  
W
When the first bit of this command byte is a logic low (R/ bit  
= 0), the SPI command is a write operation. In this case, SDIO  
remains an input; see Figure 30.  
WAVEFORM PATTERN  
ADDRESS2 = M  
WAVEFORM  
PATTERN DATA  
Figure 32. Double SPI Write of SRAM Data  
COMMAND CYCLE  
DATA TRANSFER CYCLE  
Configuration Register Update Procedure  
CS  
SCLK  
SDIO  
Most SPI accessible registers are double buffered. An active  
register set controls operation of the AD9102 during pattern  
generation. A set of shadow registers stores updated register  
values. Register updates can be written at any time. When  
configuration update is complete, the user writes a 1 to the  
UPDATE bit in the RAMUPDATE register. The UPDATE bit  
arms the register set for transfer from shadow registers to active  
registers. The AD9102 performs this transfer automatically the  
next time the pattern generator is off. This procedure does not  
apply to the 4k × 14 SRAM. For the SRAM update procedure,  
see the SRAM section.  
Figure 30. Serial Register Interface Timing, MSB First Write, 3-Wire SPI  
W
When the first bit of this command byte is a logic high (R/ bit  
= 1), the SPI command is a read operation. In this case, data is  
driven out of the SPI port as shown in Figure 31 and Figure 33.  
CS  
The SPI communication finishes after the  
pin goes high.  
COMMAND CYCLE  
DATA TRANSFER CYCLE  
CS  
SCLK  
SDIO  
Figure 31. Serial Register Interface Timing, MSB First Read, 3-Wire SPI  
READ  
WRITE  
CS  
SCLK  
SDIO  
SDO/  
SDI2/  
DOUT  
Figure 33. Serial Register Interface Timing, MSB First Read, 4-Wire SPI  
Rev. 0 | Page 18 of 36  
 
 
 
 
 
Data Sheet  
AD9102  
Table 13 summarizes reference connections and programming.  
DAC TRANSFER FUNCTION  
The AD9102 DAC provides a differential current output,  
IOUTP/IOUTN.  
Table 13. Reference Operation  
Reference Mode  
REFIO Pin  
Internal  
Connect 0.1F  
The DAC output current equations are as follows:  
capacitor  
IOUTP = IOUTFS × DAC INPUT CODE/214  
IOUTN = IOUTFS × ((214 − 1) − DAC INPUT CODE)/214 (2)  
(1)  
External  
Connect off-chip reference  
where DAC INPUT CODE = 0 to 214 − 1. Full-scale current or  
When using an external reference, it is recommended to apply  
the external reference to the REFIO pin.  
DAC Gain IOUTFS is 32 times IREF  
OUTFS = 32 × IREF  
where IREF = VREFIO/RSET  
REF is the current that flows through the IREF resistor. The IREF  
.
Programming Internal VREFIO  
I
(3)  
The internal REFIO voltage level is programmable.  
.
When the internal voltage reference is in use, the BGDR field in  
the lower six bits in Register 0x03 adjusts the VREFIO level. This  
adds or subtracts up to 20% from the nominal band gap voltage  
on REFIO. The voltage across the FSADJ resistor tracks this  
change. As a result, IREF varies by the same amount. Figure 35  
shows VREFIO vs. BGDR code for an on-chip reference with a  
default voltage (BGDR = 0x00) of 1.04 V.  
I
resistor may be on or off chip at the users’ discretion. When an  
on-chip RSET resistor is in use, DAC gain accuracy can be improved  
by employing the built-in automatic gain calibration capability.  
ANALOG CURRENT OUTPUTS  
Optimum linearity and noise performance of DAC outputs can  
be achieved when they are connected differentially to an amplifier  
or a transformer. In these configurations, common-mode signals  
at the DAC outputs are rejected.  
1.30  
1.25  
1.20  
1.15  
1.10  
1.05  
1.00  
0.95  
0.90  
0.85  
0.80  
The output compliance voltage specifications listed in Table 1 and  
Table 2 must be adhered to for the performance specifications  
in those tables to be met.  
SETTING IOUTFS, DAC GAIN  
As expressed in Equation 3, DAC gain (IOUTFS) is a function of  
the reference voltage at the REFIO terminal and RSET  
.
Voltage Reference  
The AD9102 contains an internal 1.0 V nominal band gap  
reference. The internal reference can be used, or replaced by a  
more accurate off-chip reference. An external reference can  
provide tighter reference voltage tolerances and/or lower  
temperature drift than the on-chip band gap.  
0
8
16  
24  
32  
40  
48  
56  
CODE  
Figure 35. Typical VREFIO Voltage vs. BGDR  
RSET Resistors  
RSET in the where statement for Equation 3 can be an internal  
resistor or a board level resistor of the user’s choosing  
connected to the FSADJ terminal.  
By default, the on-chip reference is powered up and ready to be  
used. When using the on-chip reference, the REFIO terminal  
needs to be decoupled to AGND using a 0.1 μF capacitor as  
shown in Figure 34.  
To make use of the on-chip RSET resistor, set Bit 15 of the FSADJ  
register to Logic 1. Bits[4:0] of the FSADJ register are used to  
program values for the on-chip RSET manually.  
AD9102  
V
1.0V  
BG  
DAC  
AUTOMATIC IOUTFS CALIBRATION  
REFIO  
FSADJ  
Many applications require tight DAC gain control. The AD9102  
provides an automatic IOUTFS calibration procedure used with an  
on-chip RSET resistor only. The voltage reference, VREFIO, can be  
the on-chip reference or an off-chip reference. The automatic  
calibration procedure does a fine adjustment of the internal RSET  
+
–
CURRENT  
SCALING  
x32  
0.1µF  
I
OUTFS  
R
SET  
I
REF  
AVSS  
value and the current, IREF  
.
Figure 34. On-Chip Reference with External RSET Resistor  
Rev. 0 | Page 19 of 36  
 
 
 
 
 
 
AD9102  
Data Sheet  
When using automatic calibration, the following board level  
connections are required:  
CLOCK INPUT  
For optimum DAC performance, the AD9102 clock input signal  
pair (CLKP/CLKN) should be a very low jitter, fast rise time  
differential signal. The clock receiver generates its own common-  
mode voltage, requiring these two inputs to be ac-coupled.  
1. Connect the FSADJ pin and the CAL_SENSE pin  
together.  
2. Install a resistor between the CAL_SENSE pin and  
AGND. To calculate the value of this resistor, use the  
following equation:  
Figure 36 shows the recommended interface to a number of  
Analog Devices LVDS clock drivers that work well with the  
AD9102. A 100 Ω termination resistor and two 0.1 μF coupling  
capacitors are used. Figure 38 is an interface to an Analog Devices  
differential PECL driver. Figure 39 shows a single-ended to  
differential converter using a balun driving CLKP/CLKN.  
R
CAL_SENSE = 32 × VREFIO/IOUTFS  
where IOUTFS is the target full-scale current.  
Automatic calibration uses an internal clock. This calibration  
clock is equal to the DAC clock divided by the division factor  
chosen by the CAL_CLK_DIV bits of Register 0x0D. Each  
calibration cycle is between 4 and 512 DAC clock cycles,  
depending on the value of CAL_CLK_DIV[2:0]. The frequency  
of the calibration clock should be less than 500 kHz.  
AD9510/AD9511/  
AD9512/AD9513/  
AD9514/AD9515/  
0.1µF  
AD9516/AD9518  
0.1µF  
CLK+  
CLK  
CLKP  
100Ω  
AD9102  
LVDS DRIVER  
CLK  
0.1µF  
0.1µF  
CLK–  
CLKN  
To perform an automatic calibration, the following steps must  
be followed:  
50Ω*  
50Ω*  
1. Set the calibration ranges in Register 0x008[7:0] and  
Register 0x0D[5:4] to their minimum values to allow best  
calibration.  
2. Enable the calibration clock bit, CAL_CLK_EN, in Register  
0x0D.  
*50Ω RESISTORS ARE OPTIONAL.  
Figure 36. Differential LVDS Clock Input  
In applications where the analog output signals are at low  
frequencies, the AD9102 clock input can be driven with a  
single-ended CMOS signal. Figure 37 shows such an interface.  
CLKP is driven directly from a CMOS gate, and the CLKN pin is  
bypassed to ground with a 0.1 μF capacitor in parallel with a  
39 kΩ resistor. The optional resistor is a series termination.  
3. Set the divider ratio for the calibration clock by setting the  
CAL_CLK_DIV[2:0] bits in Register 0x0D. The default is 512.  
4. Set the CAL_MODE_EN bit in Register 0x0D to Logic 1.  
5. Set the START_CAL bit in Register 0x0E to Logic 1. This  
begins the calibration of the comparator, RSET, and gain.  
6. The CAL_MODE flag in Register 0x0D goes to Logic 1 while  
the part is calibrating. The CAL_FIN flag in Register 0x0E  
goes to Logic 1 when the calibration is complete.  
7. Set the START_CAL bit in Register 0x0E to Logic 0.  
8. After calibration, verify that the overflow and underflow  
flags in Register 0x0D are not set (Bits[14:8]). If they are  
set, change the corresponding calibration range to the next  
larger range and start from Step 5 again.  
9. If no flag is set, read the DAC_RSET_CAL and  
DAC_GAIN_CAL values in the DACRSET and  
DACAGAIN registers respectively and write them into  
their corresponding DAC_RSET and DAC_GAIN register  
fields.  
10. Reset the CAL_MODE_EN bit and the calibration clock  
bit, CAL_CLK_EN, in Register 0x0D to Logic 0 to disable  
the calibration clock.  
AD9510/AD9511/  
AD9512/AD9513/  
AD9514/AD9515/  
0.1µF  
AD9516/AD9518  
CLK+  
CLK  
50Ω  
CMOS DRIVER  
CLKP  
OPTIONAL  
100Ω  
AD9102  
CLKN  
CLK  
0.1µF  
0.1µF  
39kΩ  
Figure 37. Single-Ended 1.8 V CMOS Sample Clock  
AD9510/AD9511/  
AD9512/AD9513/  
AD9514/AD9515/  
0.1µF  
AD9516/AD9518  
0.1µF  
CLK+  
CLK–  
CLK  
CLKP  
100Ω  
AD9102  
PECL DRIVER  
0.1µF  
0.1µF  
CLKN  
CLK  
240Ω  
240Ω  
50Ω*  
50Ω*  
11. Set the CAL_MODE_EN bit in Register 0x0D to Logic 0.  
This points the RSET and gain control muxes toward the  
regular registers.  
*50Ω RESISTORS ARE OPTIONAL.  
Figure 38. Differential PECL Sample Clock  
12. Disable the calibration clock bit CAL_CLK_EN in  
Register 0x0D.  
To reset the calibration, pulse the CAL_RESET bit in Register 0x0D  
RESET  
to Logic 1 and Logic 0, pulse the  
RESET bit in the SPICONFIG register.  
pin, or pulse the  
Rev. 0 | Page 20 of 36  
 
 
 
 
Data Sheet  
AD9102  
Periodic pulse trains that repeat a finite number of times  
are the same as those that repeat indefinitely, except that  
the waveforms are output during a finite number of  
consecutive pattern periods.  
®
Mini-Circuits  
ADT1-1WT, 1:1Z  
0.1µF  
0.1µF  
0.1µF  
XFMR  
CLK+  
CLKP  
50Ω  
AD9102  
TRIGGER  
CLKN  
SCHOTTKY  
DIODES:  
HSM2812  
PATTERN  
EXECUTED  
PATTERN  
EXECUTED  
PATTERN  
EXECUTED  
Figure 39. Transformer Coupled Clock  
PATTERN_PERIOD  
START_DLY  
DAC  
DAC OUTPUT CLOCK EDGE  
The DAC can be configured to output samples on the rising or  
falling edge of the CLKP/CLKN clock input by configuring the  
DAC_INV_CLK bit in the CLOCKCONFIG register (Register 0x02).  
This functionality sets the DAC output timing resolution at  
1/(2 × fCLKP/CLKN).  
DATA @  
DATA @  
STOP_ADDR  
START_ADDR  
Figure 40. Periodic Pulse Trains Output on All DACs  
PATTERN GENERATOR PROGRAMMING  
Figure 40 shows periodic pulse train waveforms as seen at the  
output to each of the DACs. The waveform is generated in each  
pattern period. The start delay (START_DLY) is the delay  
between the start of each pattern period and the start of the  
waveform. The DAC waveform is a digital signal stored in  
SRAM and multiplied by the DAC digital gain factor. The  
SRAM data is read using the DAC address counter.  
GENERATING SIGNAL PATTERNS  
The AD9102 can generate three types of signal patterns under  
control of its programmable pattern generator.  
Continuous waveforms  
Periodic pulse train waveforms that repeat indefinitely  
Periodic pulse train waveforms that repeat a finite number  
of times  
Setting Pattern Period  
Two register bit fields are used to set the pattern period. The  
PAT_PERIOD_BASE field in the PAT_TIMEBASE register sets  
the number of CLKP/CLKN clocks per PATTERN_PERIOD  
LSB. The PATTERN_PERIOD is programmed in the  
RUN Bit  
Setting the RUN bit in the PAT_STATUS register (Register 0x1E)  
to 1 arms the AD9102 for pattern generation. Clearing this bit  
shuts down the pattern generator as shown in Figure 43.  
PAT_PERIOD register. The longest pattern period available is  
Pin  
TRIGGER  
A falling edge on the  
pattern. If the RUN bit is set to 1, the falling edge of the  
pin starts the pattern generation. As shown in Figure 41, the pattern  
generator state goes to pattern on a number of CLKP/CLKN clock  
65,535 × 16/fCLKP/N  
.
TRIGGER  
pin starts the generation of a  
TRIGGER  
Setting Waveform Start Delay Base  
The waveform start delay base is programmed in the  
START_DELAY_BASE bits of the PAT_TIMEBASE register  
(Register 0x28[3:0]). The START_DELAY register (Register 0x5C)  
is described in the DAC Input Datapaths section. The start delay  
base determines how many CLKP/CLKN clock cycles there are  
per START_DELAY LSB.  
TRIGGER  
cycles following the falling edge of the  
is programmed in the PATTERN_DELAY bit field.  
pin. This delay  
TRIGGER  
The rising edge on the  
pin is a request for termination  
of pattern generation; see Figure 42.  
RUN BIT  
PATTERN Bit (Read Only)  
tDLY = PATTERN_DELAY VALUE + 1  
When the read only PATTERN bit in the PAT_STATUS register  
is set to 1, it indicates that the pattern generator is in the pattern  
on state. A 0 indicates that the pattern generator is in the  
pattern off state.  
tSU  
PATTERN  
STARTS  
TRIGGER  
Pattern Types  
CLKP/  
CLKN  
Continuous waveforms are output by the DAC for the  
duration of the pattern on state of the pattern generator.  
Continuous waveforms ignore pattern periods.  
Periodic pulse trains that repeat indefinitely are waveforms  
that are output once during each pattern period. Pattern  
periods occur one after the other as long as the pattern  
generator is in the pattern on state.  
PATTERN  
GENERATOR  
STATE  
PATTERN  
GENERTAOR OFF  
PATTERN  
GENERTAOR ON  
TRIGGER  
Figure 41.  
Pin Initiated Pattern Start with Pattern Delay  
Rev. 0 | Page 21 of 36  
 
 
 
 
 
 
AD9102  
Data Sheet  
tSU  
Pattern Period Repeat Controller  
The PATTERN_RPT bit in the PAT_TYPE register (Register  
ꢀx1F[ꢀ]) controls whether the pattern output auto repeats  
(periodic pulse train repeats indefinitely) or repeats a number  
of consecutive times defined by the DAC_REPEAT_CYCLE bits  
in Register ꢀx2B. The latter are periodic pulse trains that repeat  
a finite number of times.  
TRIGGER  
CLKP/  
CLKN  
PATTERN  
GENERATOR  
STATE  
PATTERN ON  
PATTERN OFF  
Number of DDS Cycles  
PATTERN  
STOPS  
The DAC input datapath establishes the pulse width of the sine  
wave output from the DDS in a number of sine wave cycles. The  
cycle counts are programmed in the DDS_CYC register.  
Figure 42. Trigger Rising Edge Initiated Pattern Stop  
DDS Phase Shift  
RUN  
BIT  
The DAC input datapath shifts the phase of the output of the  
single common DDS. The phase shift is programmed using the  
DDS_PHASE field.  
CLKP/  
CLKN  
DOUT FUNCTION  
In applications where the AD91ꢀ2 DAC drives a high voltage  
amplifier, such as in ultrasound transducer array element driver  
signal chains, it can be useful to turn on and off each amplifier  
at precise times relative to the waveform generated by the  
AD91ꢀ2 DAC. The SDO/SDI2/DOUT terminal can be  
configured to provide this function.  
PATTERN  
GENERATOR  
STATE  
PATTERN ON  
PATTERN OFF  
PATTERN  
STOPS  
Figure 43. RUN Bit Driven Pattern Stop  
DAC INPUT DATAPATHS  
The SPI interface needs to be configured in 3-wire mode  
(Figure 3ꢀ and Figure 31). This is accomplished by setting the  
SPI3WIRE or SPI3WIREM bits in the SPICONFIG register  
(Register ꢀxꢀꢀ). When the SPI_DRV or SPI_DRVM bits of the  
SPICONFIG register are set to Logic 1, the SDO/SDI2/DOUT  
terminal provides the DOUT function.  
Timing in the DAC datapaths is governed by the pattern  
generator. The datapath includes a waveform selector, a  
waveform repeat controller, RAM output and DDS output  
multiplier (RAM output can amplitude modulate DDS output),  
DDS cycle counter, DAC digital gain multiplier, and a DAC  
digital offset summer.  
Manually Controlled DOUT  
DAC Digital Gain Multiplier  
If the DOUT_MODE bit = ꢀ in the DOUT_CONFIG register  
(Register ꢀx2D), DOUT can be turned on or off using the  
DOUT_VAL bit of that same register.  
On its way into the DAC, the samples are multiplied by a 12-bit  
gain factor that has a range of 2.ꢀ. These gain values are  
programmed in the DAC_DGAIN register (Register ꢀx35).  
Pattern Generator Controlled DOUT  
DAC Digital Offset Summer  
Figure 44 depicts the rising edge of a pattern generator controlled  
DOUT pulse. Figure 45 shows the falling edge. A pattern generator  
controlled DOUT is set up by setting the DOUT_MODE bit = 1.  
Next, the start delay is programmed in the DOUT_START register  
(Register ꢀx2C) and the stop delay is programmed into the  
DOUT_STOP bit of the DOUT_CONFIG register.  
DAC input samples are summed with a 12-bit dc offset value.  
The dc offset values are programmed in the DACDOF register  
(Register ꢀx25).  
DAC Waveform Selectors  
Waveform selector inputs are:  
Sawtooth generator output  
Pseudorandom sequence generator output  
DC constant generator output  
Pulsed, phase shifted DDS sine wave output  
RAM output  
Pulsed, phase shifted DDS sine wave output amplitude,  
modulated by RAM output  
DOUT goes high when DOUT_START[15:ꢀ] CLKP/CLKN  
TRIGGER  
cycles after the falling edge of the signal input to the  
pin. DOUT stays high as long as a pattern is being generated.  
DOUT goes low when DOUT_STOP[3:ꢀ] CLKP/CLKN cycles  
after the clock edge that causes pattern generation to stop.  
Waveform selection for the DAC is made by programming the  
WAV_CONFIG register (Register ꢀx27).  
Rev. 0 | Page 22 of 36  
 
 
 
 
Data Sheet  
AD9102  
DOUT DELAY =  
DOUT_START[15:0] CLKP/CLKN CYCLES  
The AD9102 allows SPI read/write access to the SRAM while  
the SRAM is actively engaged in pattern generation (RUN = 1)  
with some restrictions.  
tSU  
TRIGGER  
The SPI port address space for SRAM is Location 0x6000  
through Location 0x6FFF.  
SRAM can be accessed using any of the SPI operating modes  
shown in Figure 30 through Figure 32. Using the SPI modes of  
operation shown in Figure 31 and Figure 33, the entire SRAM  
can be written in (2 + 2 × 4096) ×8/fSLCK seconds.  
CLKP/  
CLKN  
DOUT  
Figure 44. DOUT Start Sequence  
When the PAT_STATUS register RUN bit =1 (pattern generation  
enabled) data is read using the SRAM address counter. The  
address counter has a START_ADDR (start address) and  
STOP_ADDR (stop address). During each pattern period, data  
is read from SRAM after the START_DELAY period and while  
each address counter is incrementing.  
PATTERN  
STOPS  
PATTERN  
GENERATOR  
STATE  
PATTERN ON  
PATTERN OFF  
While the PAT_STATUS register RUN bit = 1 (pattern generation  
enabled), data can be written to or read from SRAM via the SPI  
port outside the address range defined by START_ADDR and  
STOP_ADDR.  
CLKP/CLKN  
DOUT DELAY = DOUT_STOP[3:0]  
CLKP/CLKN CYCLES  
DOUT  
Incrementing Pattern Generation Mode SRAM Address  
Counters  
Figure 45. DOUT Stop Sequence  
DIRECT DIGITAL SYNTHESIZER (DDS)  
The SRAM address counter can be programmed to be incremented  
by CLKP/CLKN (default) or by the rising edge of the DDS MSB.  
The DDS_MSB_EN bit in the DDS_CONFIG register makes  
this selection. For example, DDS MSB can be used to clock the  
address counter when generating a chirp waveform from the  
DDS using a list of tuning words in SRAM. Each frequency setting  
dwells for one DDS output sine wave cycle.  
The DDS generates sinusoid at a frequency determined by its  
tuning word input. The tuning word is 24 bits wide. The  
resolution of DDS tuning is fCLKP/N/224. The DDS output  
frequency is DDS_TW × fCLKP/N/224.  
The DDS tuning word is programmed using one of two methods.  
For a fixed frequency, the DDSTW_MSB and DDSTW_LSB bit  
fields are programmed with a constant. When the frequency  
of the DDS needs to change within each pattern period, a sequence  
of values stored in SRAM is combined with a selection of  
DDSTW_MSB bits to form the tuning word.  
SAWTOOTH GENERATOR  
When sawtooth is selected in the PRESTORE_SEL bits in the  
WAV_CONFIG register, the sawtooth generator is connected to  
the DAC digital datapath.  
SRAM  
Sawtooth types, shown in Figure 46, are selected using the  
SAW_TYPE bits in the SAW_CONFIG register. The number of  
samples per sawtooth waveform step is programmed in the  
SAW_STEP bits.  
The AD9102 4k × 14 SRAM can contain signal samples,  
amplitude modulation patterns, lists of DDS tuning words, or  
lists of DDS output phase offset words. Any SRAM data address  
can be written to and read from the SPI port as long as the  
SRAM is not actively engaged in pattern generation (RUN bit =  
0). To write to any SRAM address, set up the PAT_STATUS  
register (Register 0x1E) as follows:  
POSITIVE  
SAWTOOTH  
NEGATIVE  
SAWTOOTH  
BUF_READ = 0  
MEM_ACCESS = 1  
RUN = 0  
TRIANGLE  
WAVE  
To read data from any SRAM address, set up the PAT_STATUS  
as follows:  
Figure 46. Sawtooth Patterns  
BUF_READ = 1  
MEM_ACCESS = 1  
RUN = 0  
Rev. 0 | Page 23 of 36  
 
 
 
 
 
 
AD9102  
Data Sheet  
•
When DVDD is 2.5 V or higher, the 1.8 V on-chip DLDO1  
and DLDO2 regulators may be used. If DVVD is 1.8 V, t h e  
DLDO1 and DLDO2 regulators must be disabled by setting  
the PDN_LDO_DIG1 and PDN_LDO_DIG2 bits in the  
POWERCONFIG register. DVDD, DLDO1, and DLDO2  
are connected together.  
PSEUDORANDOM SIGNAL GENERATOR  
The pseudorandom noise generator generates a noise signal on  
each DAC output when a pseudorandom sequence is selected in  
the PRESTORE_SEL fields in the WAV_CONFIG register.  
Pseudorandom noise signals are generated as continuous  
waveforms only.  
POWER DOWN CAPABILITIES  
DC CONSTANT  
The POWERCONFIG register lets the user place the AD9102 in a  
reduced power dissipation configuration while the CLKP/CLKN  
input is running and the power supplies are on. The DAC can be  
put to sleep by setting the DAC_SLEEP bit in the POWERCONFIG  
register. Clocking of the waveform generator and the DACs can  
be turned on and off by setting the CLK_PDN bit in the  
CLOCKCONFIG register. Taking these actions places the  
AD9102 in the power down mode, specified in Table 8.  
A programmable dc current between 0.0 and IOUTFS can be  
generated on the DAC when a constant value is selected in the  
PRESTORE_SEL bits of the WAV_CONFIG register. DC  
constant current is generated as a continuous waveform only.  
The dc current level is programmed by writing to the  
DAC_CONST field in the appropriate DAC_CST register.  
POWER SUPPLY NOTES  
The AD9102 supply rails are specified in Table 9. The AD9102  
includes three on-chip linear regulators. The supply rails driven by  
these regulators are run at 1.8 V. Some usage rules for these  
regulators include:  
•
When CLKVDD is 2.5 V or higher, the 1.8 V on-chip  
CLDO regulator may be used. If CLKVDD = 1.8 V, the  
CLDO regulator must be disabled by setting the  
PDN_LDO_CLK bit in the POWERCONFIG register.  
CLKVDD and CLDO are connected together.  
Rev. 0 | Page 24 of 36  
 
 
 
 
Data Sheet  
AD9102  
APPLICATIONS  
PATTERN_PERIOD  
START_DLY  
SIGNAL GENERATION EXAMPLES  
Figure 47 shows a waveform stored in the 4k × 14 SRAM in an  
address segment defined by the START_ADDR and STOP_ADDR  
being output by the DAC. The waveform is repeated once  
during each pattern period. In each pattern period, a start delay  
is executed, then the pattern is read from SRAM.  
DAC  
DATA @  
START_ADDR  
DATA @  
STOP_ADDR  
TRIGGER  
Figure 50. DDS Output Amplitude Modulated by SRAM Envelope  
PATTERN  
EXECUTED  
PATTERN  
EXECUTED  
PATTERN  
EXECUTED  
Figure 51 and Figure 52 show the DAC generating continuous  
waveforms, one with start delays, one without.  
START_DLY  
PATTERN_PERIOD  
START_DLY  
DAC  
DAC  
DATA @  
STOP_ADDR  
DATA @  
START_ADDR  
Figure 47. Pattern in SRAM  
Figure 51. Waveform with Start Delays  
Figure 48 shows a pulsed sine wave generated by the DAC. The  
DDS generates a sine wave at a programmed frequency. The  
DAC input datapath is programmed with a start delay and a  
number of sine wave cycles to output.  
DAC  
Figure 52. Waveform Without Start Delays  
PATTERN_PERIOD  
Figure 53 shows an FSK modulated signal generated using a list  
of DDS tuning word bit fields stored in SRAM. The SRAM  
address counter is incremented by the rising edge of the DDS  
output MSB.  
START_DLY #CYCLES  
DAC  
SYMBOL0  
SYMBOL1  
SYMBOL2  
RAM WORD RAM WORD RAM WORD RAM WORD  
10 11  
SYMBOL3  
SYMBOL4  
SYMBOL5  
RAM WORD  
RAM WORD  
Figure 48. Pulsed Sine Wave in Pattern Periods  
0
1
2
3
4
5
6
7
8
9
Figure 49 shows a sawtooth wave shape generated by the DAC  
in successive pattern periods with a start delay.  
DAC  
PATTERN_PERIOD  
START_DLY  
Figure 53. FSK Modulated Signal  
DAC  
Figure 49. Pulsed Sawtooth Waveform in Pattern Periods  
Figure 50 shows the DAC outputting a sine wave modulated by  
an amplitude envelope. The sine wave is generated by the DDS,  
and the amplitude envelope is stored in SRAM. A start delay  
and a digital gain factor are applied in the DAC input datapath.  
Rev. 0 | Page 25 of 36  
 
 
 
 
 
 
 
 
 
AD9102  
Data Sheet  
REGISTER MAP  
Table 14. Register Summary  
Reg  
Name  
Bits Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Reset RW  
0x00  
SPICONFIG  
[15:8] LSBFIRST  
SPI3WIRE  
RESET  
DOUBLESPI  
SPI_DRVM  
SPI_DRV  
DOUBLESPIM  
DOUT_EN  
RESETM  
RESERVED[9:8]  
0x0000 RW  
[7:0]  
POWERCONFIG [15:8]  
RESERVED[7:6]  
DOUT_ENM  
SPI3WIREM  
LSBFIRSTM  
0x01  
RESERVED  
CLK_LDO_STAT DIG1_LDO_ DIG2_LDO_  
PDN_LDO_  
CLK  
0x0000 RW  
STAT  
STAT  
[7:0] PDN_LDO_ PDN_LDO_  
DIG1 DIG2  
REF_PDN  
REF_EXT  
EPS  
DAC_SLEEP  
RESERVED  
0x02  
0x03  
0x07  
0x08  
0x0C  
CLOCKCONFIG [15:8]  
RESERVED  
CLK_PDN  
DIS_CLK  
RESERVED  
RESERVED  
0x0000 RW  
0x0000 RW  
0x0000 RW  
0x0000 RW  
0x000A RW  
[7:0] DIS_DCLK CLK_SLEEP  
[15:8]  
DAC_INV_CLK  
RESERVED[15:8]  
REFADJ  
[7:0]  
RESERVED[7:6]  
BGDR  
DACAGAIN  
DACRANGE  
DACRSET  
[15:8] RESERVED  
[7:0] RESERVED  
[15:8]  
DAC_GAIN_CAL  
DAC_GAIN  
RESERVED  
[7:0]  
RESERVED  
DAC_GAIN_RNG  
[15:8] DAC_  
RSET_EN  
RESERVED  
RESERVED  
DAC_RSET_CAL  
DAC_RSET  
[7:0]  
0x0D  
CALCONFIG  
[15:8] RESERVED COMP_  
OFFSET_OF OFFSET_UF  
COMP_  
RSET_CAL_  
OF  
RSET_CAL_UF  
CAL_CLK_EN  
GAIN_CAL_ GAIN_CAL_UF  
OF  
CAL_RESET  
0x0000 RW  
[7:0] CAL_  
MODE  
CAL_MODE_  
EN  
COMP_CAL_RNG  
CAL_CLK_DIV  
0x0E  
0x1D  
0x1E  
COMPOFFSET [15:8] RESERVED  
COMP_OFFSET_CAL  
0x0000 RW  
0x0000  
[7:0]  
RAMUPDATE [15:8]  
[7:0]  
RESERVED  
CAL_FIN  
PATTERN  
TART_CAL  
UPDATE  
RUN  
RESERVED[15:8]  
RESERVED[7:1]  
PAT_STATUS [15:8]  
[7:0]  
RESERVED[15:8]  
BUF_READ  
0x0000 RW  
RESERVED[7:4]  
MEM_  
ACCESS  
0x1F  
0x20  
0x25  
0x27  
0x28  
0x29  
0x2B  
0x2C  
0x2D  
PAT_TYPE  
[15:8]  
[7:0]  
RESERVED[15:8]  
0x0000 RW  
0x000E RW  
0x0000 RW  
0x0000 RW  
0x0111 RW  
0x8000 RW  
0x0101 RW  
0x0003 RW  
0x0000 RW  
RESERVED[7:1]  
PATTERN_RPT  
PATTERN_DLY [15:8]  
[7:0]  
PATTERN_DELAY[15:8]  
PATTERN_DELAY[7:0]  
DAC_DIG_OFFSET[15:8]  
DACDOF  
[15:8]  
[7:0]  
DAC_DIG_OFFSET[7:5]  
PRESTORE_SEL  
RESERVED  
WAV_CONFIG [15:8]  
[7:0]  
RESERVED  
RESERVED  
RESERVED  
CH_ADD  
WAVE_SEL  
PAT_  
TIMEBASE  
[15:8]  
[7:0]  
RESERVED  
HOLD  
START_DELAY_BASE  
PAT_PERIOD_BASE  
PAT_PERIOD [15:8]  
[7:0]  
PATTERN_PERIOD[15:8]  
PATTERN_PERIOD[7:0]  
RESERVED  
DAC_PAT  
[15:8]  
[7:0]  
DAC_REPEAT_CYCLE  
DOUT_START[15:8]  
DOUT_START[7:0]  
RESERVED[15:8]  
DOUT_START [15:8]  
[7:0]  
DOUT_  
CONFIG  
[15:8]  
[7:0]  
RESERVED[7:6]  
DOUT_VAL  
DOUT_  
MODE  
DOUT_STOP  
0x31  
0x35  
0x37  
DAC_CST  
[15:8]  
[7:0]  
DAC_CONST[15:8]  
0x0000 RW  
0x0000 RW  
0x0000 RW  
DAC_CONST[7:5]  
RESERVED  
RESERVED  
DAC_DGAIN  
[15:8]  
[7:0]  
DAC_DIG_GAIN[15:8]  
DAC_DIG_GAIN[7:5]  
SAW_CONFIG [15:8]  
[7:0]  
RESERVED  
SAW_STEP  
RESERVED  
SAW_TYPE  
0x38 to RESERVED  
0x3D  
RESERVED  
0x3E  
DDS_TW32  
[15:8]  
[7:0]  
DDSTW_MSB[15:8]  
DDSTW_MSB[7:0]  
0x0000 RW  
Rev. 0 | Page 26 of 36  
 
Data Sheet  
AD9102  
0x3F  
0x43  
0x44  
DDS_TW1  
[15:8]  
[7:0]  
DDSTW_LSB  
RESERVED  
0x0000 RW  
0x0000 RW  
0x0000 RW  
DDS_PW  
[15:8]  
[7:0]  
DDS_PHASE[15:8]  
DDS_PHASE[7:0]  
RESERVED[15:8]  
TRIG_TW_SEL [15:8]  
[7:0]  
RESERVED[7:2]  
TRIG_DELAY_  
EN  
RESERVED  
0x45  
0x47  
DDS_CONFIG [15:8]  
[7:0]  
RESERVED  
0x0000 RW  
0x0000 RW  
RESERVED  
RESERVED  
RESERVED  
DDS_COS_EN  
DDS_MSB_ PHASE_MEM_  
TW_MEM_EN  
EN  
EN  
TW_RAM_  
CONFIG  
[15:8]  
RESERVED  
[7:0]  
TW_MEM_SHIFT  
0x5C  
0x5D  
0x5E  
0x5F  
0x60  
START_DELAY [15:8]  
START_DELAY[15:8]  
START_DELAY[7:0]  
START_ADDR[15:8]  
0x0000 RW  
0x0000 RW  
0x0000 RW  
0x0001 RW  
0x0000 R  
[7:0]  
START_ADDR [15:8]  
[7:0]  
START_ADDR[7:5]  
STOP_ADDR[7:5]  
RESERVED  
RESERVED  
STOP_ADDR  
[15:8]  
[7:0]  
STOP_ADDR[15:8]  
DDS_CYC  
[15:8]  
[7:0]  
DDS_CYC[15:8]  
DDS_CYC[7:0]  
CFG_ERROR  
[15:8]  
[7:0]  
ERROR_CLEAR  
RESERVED  
RESERVED  
DOUT_START_ PAT_DLY_  
DOUT_START_ PERIOD_  
ODD_ADDR_  
SHORT_ERR ERR  
MEM_READ_  
ERR  
LG_ERR  
SHORT_ERR SHORT_ERR  
0x6000 SRAM_DATA [15:8]  
RESERVED  
SRAM_DATA[11:8]  
N/A  
RW  
to  
0x6FFF  
[7:0]  
SRAM_DATA[7:0]  
Rev. 0 | Page 27 of 36  
AD9102  
Data Sheet  
REGISTER DESCRIPTIONS  
SPI Control Register (SPICONFIG, Address 0x00)  
Table 15. Bit Descriptions for SPICONFIG  
Bits  
Bit Name  
Settings Description  
Reset Access  
15  
LSBFIRST  
LSB first selection.  
0x0  
0x0  
0x0  
RW  
RW  
RW  
0
1
MSB first per SPI standard (default).  
LSB first per SPI standard.  
Selects if SPI is using 3-wire or 4-wire interface.  
4-wire SPI.  
14  
13  
SPI3WIRE  
RESET  
0
1
3-wire SPI.  
Executes software reset of SPI and controllers, reloads default register values,  
except Register 0x00.  
0
1
Normal status.  
Reset whole register map, except 0x0000.  
12  
DOUBLESPI  
Double SPI data line.  
0x0  
RW  
0
1
The SPI port has only 1 data line and can be used as a 3-wire or 4-wire interface.  
The SPI port has two data lines both bi-directional defining a pseudo dual 3-  
CS  
wire interface where  
and SCLK are shared between the two ports. This mode  
is available only for RAM data read or write.  
Double drive ability for SPI output.  
Single SPI output drive ability.  
Two time drive ability on SPI output.  
Enable DOUT signal on SDO/SDI2/DOUT pin.  
SDO/SDI2 function input/output.  
DOUT function output.  
11  
10  
SPI_DRV  
0x0  
0x0  
RW  
RW  
0
1
DOUT_EN  
0
1
[9:6]  
5
RESERVED  
RW  
RW  
RW  
RW  
RW  
DOUT_ENM1  
SPI_DRVM1  
DOUBLESPIM1  
RESETM1  
Enable DOUT signal on SDO/SDI2/DOUT pin.  
Double drive ability for SPI output.  
Doube SPI data line.  
4
0x0  
0x0  
0x0  
2
Executes software reset of SPI and controllers, reloads default register values,  
except Register 0x00.  
1
0
SPI3WIREM1  
LSBFIRSTM1  
Selects whether SPI uses a 3-wire or 4-wire interface.  
LSB first selection.  
0x0  
0x0  
RW  
RW  
1 SPICONFIG[10:15] must always be set to the mirror of SPICONFIG[5:0] to allow easy recovery of the SPI operation when LSBFIRST bit is set incorrectly. (Bit 15 = Bit 0, Bit 14 = Bit 1,  
Bit 13 = Bit 2, Bit 12 = Bit 3, Bit 11 = Bit 4, and Bit 10 = Bit 5.)  
Power Status Register (POWERCONFIG, Address 0x01)  
Table 16. Bit Descriptions for POWERCONFIG  
Bits  
Bit Name  
Settings Description  
Reset Access  
[15:12] RESERVED  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
RW  
R
11  
10  
9
CLK_LDO_STAT  
Read-only flag indicating CLKVDD LDO is on.  
DIG1_LDO_STAT  
DIG2_LDO_STAT  
PDN_LDO_CLK  
PDN_LDO_DIG1  
PDN_LDO_DIG2  
REF_PDN  
Read-only flag indicating DVDD1 LDO is on.  
Read-only flag indicating DVDD2 LDO is on.  
Disable the CLKVDD LDO. An external supply is required.  
Disable the DVDD1 LDO. An external supply is required.  
Disable the DVDD2 LDO. An external supply is required.  
Power down on-chip REFIO.  
R
R
8
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
7
6
5
4
REF_EXT  
Always set to 0.  
3
DAC_SLEEP  
Disable DAC output current.  
2
RESERVED  
Disable DAC2 output current.  
1
RESERVED  
Disable DAC3 output current.  
0
RESERVED  
Disable DAC4 output current.  
Rev. 0 | Page 28 of 36  
 
 
Data Sheet  
AD9102  
Clock Control Register (CLOCKCONFIG, Address 0x02)  
Table 17. Bit Descriptions for CLOCKCONFIG  
Bits  
Bit Name  
Settings  
Description  
Reset  
Access  
RW  
[15:12] RESERVED  
0x0  
0x0  
0x0  
11  
10  
9
DIS_CLK  
Disable the analog clock to the DAC output of the clock distribution block.  
RW  
RESERVED  
RESERVED  
RESERVED  
DIS_DCLK  
CLK_SLEEP  
CLK_PDN  
RW  
Disable the analog clock to the DAC3 output of the clock distribution block. 0x0  
Disable the analog clock to the DAC4 output of the clock distribution block. 0x0  
RW  
8
RW  
7
Disable the clock to core digital block.  
Enables a very low power clock mode.  
0x0  
0x0  
0x0  
RW  
6
RW  
5
Disables and powers down the main clock receiver. No clocks are active in  
the part.  
RW  
4
EPS  
Enable Power Save. This enables a low power option for clock receiver but  
maintains low jitter performance on the DAC clock rising edge. The DAC  
clock falling edge is substantially degraded.  
0x0  
RW  
3
DAC_INV_CLK  
RESERVED  
Cannot use EPS while using this bit. Inverts the clock inside DAC Core 1  
allowing a 180° phase shift in DAC update timing.  
0x0  
0x0  
RW  
RW  
[2:0]  
Reference Resistor Register (REFADJ, Address 0x03)  
Table 18. Bit Descriptions for REFADJ  
Bits  
Bit Name  
RESERVED  
BGDR  
Settings  
Description  
Reset  
0x000  
0x00  
Access  
RW  
[15:6]  
[5:0]  
Adjusts the on-chip REFIO voltage level (see Figure 35).  
RW  
DAC Analog Gain Register (DACAGAIN, Address 0x07)  
Table19. Bit Descriptions for DACAGAIN  
Bits  
Bit Name  
Settings  
Description  
Reset  
0x0  
Access  
RW  
R
15  
RESERVED  
[14:8]  
7
DAC_GAIN_CAL  
RESERVED  
DAC analog gain calibration output; read only  
DAC analog gain control while not in calibration mode, twos complement  
0x00  
0x0  
RW  
RW  
[6:0]  
DAC_GAIN  
0x00  
DAC Analog Gain Range Register (DACRANGE, Address 0x08)  
Table20. Bit Descriptions for DACRANGE  
Bits  
Bit Name  
Settings  
Description  
Reset  
0x00  
0x0  
Access  
RW  
[15:2]  
[1:0]  
RESERVED  
DAC_GAIN_RNG  
DAC gain range control.  
RW  
Rev. 0 | Page 29 of 36  
AD9102  
Data Sheet  
FSADJ Register (DACRSET, Address 0x0C)  
Table 21. Bit Descriptions for DACRSET  
Bits  
Bit Name  
Settings Description  
Reset  
Access  
15  
DAC_RSET_EN  
To write, enable the internal RSET resistor for the DAC. To read, enable RSET  
0x0  
RW  
for DAC 1 during calibration mode.  
[14:13] RESERVED  
0x0  
RW  
R
[12:8]  
DAC_RSET_CAL  
Digital control for the value of the RSET resistor for the DAC after  
calibration; read only.  
0x00  
[7:5]  
[4:0]  
RESERVED  
DAC_RSET  
0x0  
RW  
RW  
Digital control to set the value of the RSET resistor in the DAC .  
0x0A  
Calibration Register (CALCONFIG, Address 0x0D)  
Table 22. Bit Descriptions for CALCONFIG  
Bits  
15  
14  
13  
12  
11  
10  
9
Bit Name  
Settings Description  
Reset  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
Access  
RW  
R
RESERVED  
COMP_OFFSET_OF  
COMP_OFFSET_UF  
RSET_CAL_OF  
RSET_CAL_UF  
GAIN_CAL_OF  
GAIN_CAL_UF  
CAL_RESET  
Compensation offset calibration value overflow.  
Compensation offset calibration value underflow.  
RSET calibration value overflow.  
R
R
RSET calibration value underflow.  
R
Gain calibration value overflow.  
R
Gain calibration value underflow.  
R
8
Pulse this bit high and low to reset the calibration results.  
Read-only flag indicating calibration is being used.  
Enables the gain calibration circuitry.  
RW  
R
7
CAL_MODE  
6
CAL_MODE_EN  
COMP_CAL_RNG  
CAL_CLK_EN  
CAL_CLK_DIV  
RW  
RW  
RW  
RW  
[5:4]  
3
Offset calibration range.  
Enables the calibration clock to the calibration circuitry.  
Sets divider from the DAC clock to the calibration clock.  
[2:0]  
Comp Offset Register (COMPOFFSET, Address 0x0E)  
Table 23. Bit Descriptions for COMPOFFSET  
Bits  
Bit Name  
Settings Description  
Reset  
0x0  
Access  
RW  
15  
RESERVED  
[14:8] COMP_OFFSET_CA  
L
The result of the offset calibration for the comparator.  
0x00  
R
[7:2]  
1
RESERVED  
CAL_FIN  
0x00  
0x0  
RW  
R
Read-only flag indicating calibration is completed.  
Start a calibration cycle.  
0
START_CAL  
0x0  
RW  
Update Pattern Register (RAMUPDATE, Address 0x1D)  
Table 24. Bit Descriptions for RAMUPDATE  
Bits  
[15:1] RESERVED  
UPDATE  
Bit Name  
Settings Description  
Reset  
0x0000  
0x0  
Access  
RW  
0
Update all SPI settings with a new configuration (self-clearing).  
RW  
Rev. 0 | Page 30 of 36  
Data Sheet  
AD9102  
Command/Status Register (PAT_STATUS, Address 0x1E)  
Table 25. Bit Descriptions for PAT_STATUS  
Bits  
Bit Name  
Settings Description  
Reset  
Access  
RW  
RW  
RW  
R
[15:3] RESERVED  
0x000  
0x0  
3
2
1
0
BUF_READ  
MEM_ACCESS  
PATTERN  
RUN  
Read back from updated buffer.  
Memory SPI access enable.  
0x0  
Status of pattern being played, read only.  
Allows the pattern generation, and stop pattern after trigger.  
0x0  
0x0  
RW  
Command/Status Register (PAT_TYPE, Address 0x1F)  
Table 26. Bit Descriptions for PAT_TYPE  
Bits  
[15:1] RESERVED  
PATTERN_RPT  
Bit Name  
Settings Description  
Reset  
Access  
0x0000 RW  
0x0  
0
Setting this bit allows the pattern to repeat a number of times defined in  
RW  
Register 0x002A and Register 0x002B.  
Pattern continuously runs.  
Pattern repeats the number of times defined in Register 0x002A and  
Register 0x002B.  
0
1
Trigger Start to Real Pattern Delay Register (PATTERN_DLY, Address 0x20)  
Table 27. Bit Descriptions for PATTERN_DLY  
Bits  
Bit Name  
Settings Description  
Time between when the TRIGGER pin is low and the pattern starts in number  
of DAC clock cycles + 1.  
Reset  
Access  
[15:0] PATTERN_DELAY  
0x000E RW  
DAC Digital Offset Register (DACDOF, Address 0x25)  
Table 28. Bit Descriptions for DACDOF  
Bits  
[15:4] DAC_DIG_OFFSET  
[3:0] RESERVED  
Bit Name  
Settings Description  
Reset  
Access  
DAC digital offset.  
0x0000 RW  
0x0  
RW  
Wave Select Register (WAV_CONFIG, Address 0x27)  
Table 29. Bit Descriptions for WAV_CONFIG  
Bits  
Bit Name  
Settings Description  
Reset  
0x0  
Access  
RW  
[15:10] RESERVED  
[9:8]  
[17:6]  
[5:4]  
RESERVED  
0x1  
RW  
RESERVED  
0x0  
RW  
PRESTORE_SEL  
0x0  
RW  
0
1
2
3
Constant value held into DAC constant value MSB/LSB register.  
Sawtooth at the frequency defined in the DAC sawtooth configuration register.  
Pseudorandom sequence.  
DDS output.  
3
RESERVED  
CH_ADD  
0x0  
0x0  
0x1  
RW  
RW  
RW  
2
0
Normal operation for the DAC.  
[1:0]  
WAVE_SEL  
0
1
2
3
Waveform read from RAM between START_ADDR and STOP_ADDR.  
Prestored waveform.  
Prestored waveform using START_DELAY and PATTERN_PERIOD.  
Prestored waveform modulated by waveform from RAM.  
Rev. 0 | Page 31 of 36  
AD9102  
Data Sheet  
DAC Time Control Register (PAT_TIMEBASE, Address 0x28)  
Table 30. Bit Descriptions for PAT_TIMEBASE  
Bits  
Bit Name  
Settings Description  
Reset  
0x0  
Access  
RW  
[15:12] RESERVED  
[11:8]  
[7:4]  
[3:0]  
HOLD  
The number of times the DAC value holds the sample (0 = DAC holds for  
1 sample).  
0x1  
RW  
PAT_PERIOD_BASE  
START_DELAY_BASE  
The number of DAC clock periods per PATTERN_PERIOD LSB (0 =  
PATTERN_PERIOD LSB = 1 DAC clock period).  
0x1  
0x1  
RW  
RW  
The number of DAC clock periods per START_DELAY × LSB (0 =  
START_DELAY × LSB = 1 DAC clock period).  
Pattern Period Register (PAT_PERIOD, Address 0x29)  
Table 31. Bit Descriptions for PAT_PERIOD  
Bits  
Bit Name  
Settings Description  
Reset  
Access  
[15:0]  
PATTERN_PERIOD  
Pattern period register.  
0x8000 RW  
DAC Pattern Repeat Cycles Register (DAC_PAT, Address 0x2B)  
Table 32. Bit Descriptions for DAC_PAT  
Bits  
Bit Name  
Settings Description  
Reset  
0x01  
0x01  
Access  
[15:8]  
[7:0]  
RESERVED  
RW  
RW  
DAC_REPEAT_CYCLE  
The number of DAC pattern repeat cycles + 1.  
TRIGGER  
Start to DOUT Signal Register (DOUT_START, Address 0x2C)  
Table 33. Bit Descriptions for DOUT_START  
Bits  
Bit Name  
Settings Description  
Time between when the  
the number of DAC clock cycles.  
Reset  
Access  
[15:0]  
DOUT_START  
TRIGGER  
0x0003 RW  
pin is low and DOUT signal is high in  
DOUT CONFIG Register (DOUT_CONFIG, Address 0x2D)  
Table 34. Bit Descriptions for DOUT_CONFIG  
Bits  
[15:6]  
5
Bit Name  
RESERVED  
DOUT_VAL  
Settings Description  
Reset  
0x000  
0x0  
Access  
RW  
RW  
Manually sets the DOUT signal value; it is valid only when DOUT_MODE  
= 0 (manual mode).  
4
DOUT_MODE  
DOUT_STOP  
Set different enable signal mode.  
DOUT pin is output from SDO/SDI2/DOUT pin and manually controlled  
by Bit 5, DOUT_EN in Register 0x00 must be set to use this feature.  
DOUT pin is output from SDO/SDI2/DOUT. The pin is controlled by  
DOUT_START and DOUT_STOP. DOUT_EN in Register 0x00 must be set to  
use this feature.  
0x0  
RW  
0x0  
0x1  
[3:0]  
Time between pattern end and DOUT signal low in number of DAC clock 0x0  
cycles.  
RW  
DAC Constant Value Register (DAC_CST, Address 0x31)  
Table 35. Bit Descriptions for DAC_CST  
Bits  
Bit Name  
Settings Description  
Reset  
Access  
[15:4]  
[3:0]  
DAC_CONST  
RESERVED  
Most significant byte of DAC constant value  
0x0000 RW  
0x0 RW  
Rev. 0 | Page 32 of 36  
Data Sheet  
AD9102  
DAC Digital Gain Register (DAC_DGAIN, Address 0x35)  
Table 36. Bit Descriptions for DAC_DGAIN  
Bits  
Bit Name  
Settings  
Description  
Reset  
Access  
RW  
[15:4]  
[3:0]  
DAC_DIG_GAIN  
RESERVED  
DAC digital gain. Range +2 to −2.  
0x000  
0x0  
RW  
DAC Sawtooth Config Register (SAW_CONFIG, Address 0x37)  
Table 37. Bit Descriptions for SAW_CONFIG  
Bits  
Bit Name  
RESERVED  
SAW_STEP  
SAW_TYPE  
Settings  
Description  
Reset  
0x01  
0x01  
0x0  
Access  
RW  
[15:8]  
[7:2]  
[1:0]  
Number of samples per step for the DAC.  
The type of sawtooth (positive, negative or triangle) for DAC.  
Ramp up sawtooth wave.  
Ramp down sawtooth wave.  
Triangle sawtooth wave.  
RW  
RW  
0
1
2
3
No wave, zero.  
DDS Tuning Word MSB Register (DDS_TW32, Address 0x3E)  
Table 38. Bit Descriptions for DDS_TW32  
Bits  
Bit Name  
Settings  
Description  
Reset  
Access  
[15:0]  
DDSTW_MSB  
DDS tuning word MSB.  
0x0000 RW  
DDS Tuning Word LSB Register (DDS_TW1, Address 0x3F)  
Table 39. Bit Descriptions for DDS_TW1  
Bits  
Bit Name  
Settings  
Description  
Reset  
0x00  
0x00  
Access  
[15:8]  
[7:0]  
DDSTW_LSB  
RESERVED  
DDS tuning word LSB.  
RW  
RW  
DDS Phase Offset Register (DDS_PW, Address 0x43)  
Table 40. Bit Descriptions for DDS1_PW  
Bits  
Bit Name  
Settings  
Description  
Reset  
Access  
[15:0]  
DDS_PHASE  
DDS phase offset.  
0x0000 RW  
Pattern Control 1 Register (TRIG_TW_SEL, Address 0x44)  
Table 41. Bit Descriptions for TRIG_TW_SEL  
Bits  
[15:2]  
1
Bit Name  
Settings  
Description  
Reset  
Access  
RESERVED  
0x0000 RW  
TRIG_DELAY_EN  
Enable start delay as trigger delay for all 4 channels.  
Delay repeats for all patterns.  
Delay is only at the start of first pattern.  
0x0  
RW  
0
1
0
RESERVED  
0x0  
RW  
Rev. 0 | Page 33 of 36  
AD9102  
Data Sheet  
Pattern Control 2 Register (DDS_CONFIG, Address 0x45)  
Table 42. Bit Descriptions for DDS_CONFIG  
Bits  
[15:4]  
3
Bit Name  
Settings  
Description  
Reset  
0x0  
Access  
RW  
RESERVED  
DDS_COS_EN  
DDS_MSB_EN  
Enables DDS cosine output of DDS instead of sine wave.  
0x0  
RW  
2
Selects the SRAM address counter clock as CLKP/CLKN when set to 0x0,  
DDS MSB when set to 0x1.  
0x0  
RW  
1
0
PHASE_MEM_EN  
TW_MEM_EN  
0x1  
0x0  
0x1  
Selects the SRAM as source of DDS phase offset input.  
Selects the DDS_PW as the source of DDS offset.  
0x0  
0x0  
RW  
RW  
Selects the SRAM and DDS_TW registers as configured in the  
TW_RAM_CONFIG register as the source of DDS tuning word input.  
0x0  
Selects the DDS_TW registers as the source for DS tuning words  
TW_RAM_CONFIG Register (TW_RAM_CONFIG, Address 0x47)  
Table 43. Bit Descriptions for TW_RAM_CONFIG  
Bits  
Bit Name  
Settings  
Description  
Reset  
0x000  
0x00  
Access  
RW  
[15:5]  
[4:0]  
RESERVED  
TW_MEM_SHIFT  
TW_MEM_EN1 is set. This register controls the right shift bit when memory  
data merge to DDS1TW.  
RW  
0x00  
0x01  
0x02  
0x03  
0x04  
0x05  
0x06  
0x07  
0x08  
0x09  
0x0A  
0x0B  
0x0C  
0x0D  
0x0E  
0x0F  
0x10  
x
DDSTW = {RAM[13:0],10'b0}  
DDSTW = {DDSTW[23],RAM[13:0],9'b0}  
DDSTW = {DDSTW[23:22],RAM[13:0],8'b0}  
DDSTW = {DDSTW[23:21],RAM[13:0],7'b0}  
DDSTW = {DDSTW[23:20],RAM[13:0],6'b0}  
DDSTW = {DDSTW[23:19],RAM[13:0],5'b0}  
DDSTW = {DDSTW[23:18],RAM[13:0],4'b0}  
DDSTW = {DDSTW[23:17],RAM[13:0],3'b0}  
DDSTW = {DDSTW[23:16],RAM[13:0],2'b0}  
DDSTW = {DDSTW[23:15],RAM[13:0],1'b0}  
DDSTW = {DDSTW[23:14],RAM[13:0]}  
DDSTW = {DDSTW[23:13],RAM[13:1]}  
DDSTW = {DDSTW[23:12],RAM[13:2]}  
DDSTW = {DDSTW[23:11],RAM[13:3]}  
DDSTW = {DDSTW[23:10],RAM[13:4]}  
DDSTW = {DDSTW[23:9],RAM[13:5]}  
DDSTW = {DDSTW[23:8],RAM[13:6]}  
Reserved  
Start Delay Register (START_DLY, Address 0x5C)  
Table 44. Bit Descriptions for START_DLY  
Bits  
Bit Name  
Settings  
Description  
Reset  
Access  
[15:0]  
START_DELAY  
Start delay of DAC.  
0x0000 RW  
Start Address Register (START_ADDR, Address 0x5D)  
Table 45. Bit Descriptions for START_ADDR  
Bits  
Bit Name  
Settings Description  
Reset  
0x000  
0x0  
Access  
[15:4]  
[3:0]  
START_ADDR  
RESERVED  
RAM address where DAC starts to read waveform.  
RW  
RW  
Rev. 0 | Page 34 of 36  
Data Sheet  
AD9102  
Stop Address Register (STOP_ADDR, Address 0x5E)  
Table 46. Bit Descriptions for STOP_ADDR  
Bits  
Bit Name  
Settings Description  
Reset  
Access  
RW  
[15:4]  
[3:0]  
STOP_ADDR  
RESERVED  
RAM address where DAC stops to read waveform.  
0x000  
0x0  
RW  
DDS Cycles Register (DDS_ CYC, Address 0x5F)  
Table 47. Bit Descriptions for DDS_CYC  
Bits  
Bit Name  
Settings Description  
Number of sine wave cycles when a DDS prestored waveform with start and  
stop delays is selected for the DAC output.  
Reset  
Access  
[15:0]  
DDS_CYC  
0x0001 RW  
Configuration Error Register (CFG_ERROR, Address 0x60)  
Table 48. Bit Descriptions for CFG_ERROR  
Bits  
Bit Name  
Settings Description  
Reset  
0x0  
Access  
15  
ERROR_CLEAR  
RESERVED  
Write this bit to clear all errors.  
R
R
R
[14:6]  
5
0x000  
0x0  
DOUT_START_LG_ERR  
When the DOUT_START value is larger than the pattern delay,  
this error is toggled.  
4
2
2
1
0
PAT_DLY_SHORT_ERR  
DOUT_START_SHORT_ERR  
PERIOD_SHORT_ERR  
ODD_ADDR_ERR  
When the pattern delay value is smaller than the default value,  
this error is toggled.  
0x0  
0x0  
0x0  
0x0  
0x0  
R
R
R
R
R
When the DOUT_START value is smaller than the default value,  
this error is toggled.  
When the period register setting value is smaller than the  
pattern play cycle, this error is toggled.  
When the memory pattern play is not of even length in trigger  
delay mode, this error flag is toggled.  
MEM_READ_ERR  
When there is a memory read conflict, this error flag is toggled.  
Rev. 0 | Page 35 of 36  
AD9102  
Data Sheet  
OUTLINE DIMENSIONS  
5.10  
5.00 SQ  
4.90  
0.30  
0.25  
0.18  
PIN 1  
INDICATOR  
PIN 1  
INDICATOR  
25  
32  
24  
1
0.50  
BSC  
*
3.75  
EXPOSED  
PAD  
3.60 SQ  
3.55  
17  
8
16  
9
0.50  
0.40  
0.30  
0.25 MIN  
TOP VIEW  
BOTTOM VIEW  
FOR PROPER CONNECTION OF  
THE EXPOSED PAD, REFER TO  
THE PIN CONFIGURATION AND  
FUNCTION DESCRIPTIONS  
0.80  
0.75  
0.70  
0.05 MAX  
0.02 NOM  
SECTION OF THIS DATA SHEET.  
COPLANARITY  
0.08  
0.20 REF  
SEATING  
PLANE  
*
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5  
WITH EXCEPTION TO EXPOSED PAD DIMENSION.  
Figure 54. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]  
5 mm × 5 mm Body, Very Very Thin Quad  
(CP-32-12)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model1  
Temperature Range  
Package Description  
32-Lead LFCSP_WQ  
32-Lead LFCSP_WQ  
Evaluation Board  
Package Option  
AD9102BCPZ  
AD9102BCPZRL7  
AD9102-EBZ  
−40°C to +85°C  
−40°C to +85°C  
CP-32-12  
CP-32-12  
1 Z = RoHS Compliant Part.  
©2013 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D11220-0-1/13(0)  
Rev. 0 | Page 36 of 36  
 
 
 

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明