AD9106-EBZ [ADI]
Quad, Low Power, 12-Bit, 180 MSPS, Digital-to-Analog Converter and Waveform Generator; 四，低功耗， 12位， 180 MSPS ，数位类比转换器和波形发生器
| 型号： | AD9106-EBZ |
| 厂家： | 
ADI |
| 描述： | Quad, Low Power, 12-Bit, 180 MSPS, Digital-to-Analog Converter and Waveform Generator |
| 文件： | 总48页 (文件大小：851K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad, Low Power, 12-Bit, 180 MSPS, Digital-to-
Analog Converter and Waveform Generator
Data Sheet
AD9106
FEATURES
GENERAL DESCRIPTION
Highly integrated quad DAC
On-chip 4096 × 12-bit pattern memory
On-chip DDS
Power dissipation at 3.3 V, 4 mA output
315 mW at 180 MSPS
Sleep mode: < 5 mW at 3.3 V
Supply voltage: 1.8 V to 3.3 V
SFDR to Nyquist
86 dBc at 1 MHz output
85 dBc at 10 MHz output
Phase noise at 1 kHz offset, 180 MSPS, 8 mA: −140 dBc/Hz
Differential current outputs: 8 mA maximum at 3.3 V
Small footprint 32-lead, 5 mm × 5 mm with 3.5 mm ×
3.6 mm exposed paddle LFCSP
The AD9106 TxDAC® and waveform generator is a high perform-
ance quad DAC integrating on-chip pattern memory for complex
waveform generation with a direct digital synthesizer (DDS). The
DDS is a 12-bit output, up to 180 MHz master clock sinewave
generator with a 24-bit tuning word allowing 10.8 Hz/LSB
frequency resolution. The DDS has a single frequency output
for all four DACs and independent programmable phase shift
outputs for each of the four DACs.
SRAM data can include directly generated stored waveforms,
amplitude modulation patterns applied to DDS outputs, or
DDS frequency tuning words.
An internal pattern control state machine allows the user to
program the pattern period for all four DACs as well as the start
delay within the pattern period for the signal output on each
DAC channel.
Pb-free package
APPLICATIONS
An SPI interface is used to configure the digital waveform
generator and load patterns into the SRAM.
Medical instrumentation
Ultrasound transducer excitation
Portable instrumentation
There are gain adjustment factors and offset adjustments
applied to the digital signals on their way into the four DACs.
Signal generators, arbitrary waveform generators
The AD9106 offers exceptional ac and dc performance and
supports DAC sampling rates up to 180 MSPS. The flexible
power supply operating range of 1.8 V to 3.3 V and low power
dissipation of the AD9106 make it well suited for portable and low
power applications.
Rev. A
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9106
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Current Outputs ........................................................... 22
Setting IOUTFSx, DAC Gain .......................................................... 22
Automatic IOUTFSx Calibration ................................................... 23
Clock Input.................................................................................. 23
DAC Output Clock Edge........................................................... 24
Generating Signal Patterns........................................................ 24
Pattern Generator Programming ............................................. 25
DACx Input Data Paths............................................................. 25
DOUT Function......................................................................... 26
Direct Digital Synthesizer (DDS)............................................. 26
SRAM........................................................................................... 27
Sawtooth Generator ................................................................... 27
Pseudo-Random Signal Generator .......................................... 27
DC Constant ............................................................................... 27
Power Supply Notes ................................................................... 27
Power-Down Capabilities.......................................................... 27
Applications Information .............................................................. 28
Signal Generation Examples..................................................... 28
Register Map ................................................................................... 30
Register Descriptions................................................................. 33
Outline Dimensions....................................................................... 48
Ordering Guide .......................................................................... 48
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
DC Specifications (3.3 V)............................................................ 4
DC Specifications (1.8 V)............................................................ 5
Digital Timing Specifications (3.3 V)........................................ 6
Digital Timing Specifications (1.8 V)........................................ 6
Input/Output Signal Specifications............................................ 7
AC Specifications (3.3 V) ............................................................ 8
AC Specifications (1.8 V) ............................................................ 8
Power Supply Voltage Inputs and Power Dissipation.............. 9
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 20
SPI Port ........................................................................................ 21
DAC Transfer Function ............................................................. 22
REVISION HISTORY
2/13—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Features Section............................................................ 1
Changes to Figure 1.......................................................................... 3
Deleted Figure 20; Renumbered Sequentially ............................ 16
Changes to Figure 31...................................................................... 20
Changes to Table 13........................................................................ 22
Deleted Recommendations When Using an External
Reference Section............................................................................ 23
11/12—Revision 0: Initial Version
Rev. A | Page 2 of 48
Data Sheet
AD9106
FUNCTIONAL BLOCK DIAGRAM
1V
AD9106
10kΩ
SPI
INTERFACE
AGND
STOP ADDR
START ADDR
START DLY
R
R
SET2
16kΩ
SET1
16kΩ
DAC1 TO DAC2
TRIGGER
I
REF
100µA
GAIN1 OFFSET1
TIMERS + STATE MACHINES
ADDRESS 1, 2
IOUTP1
IOUTN1
AVDD1
IOUTP2
IOUTN2
DAC1
DAC1
GAIN2 OFFSET2
GAIN3 OFFSET3
DAC2
DAC3
DAC2
DAC3
BAND
GAP
DPRAM
IOUTP3
IOUTN3
AVDD2
IOUTP4
IOUTN4
DAC4
GAIN4 OFFSET4
PHASE2
ADDRESS 3, 4
DAC4
R
SET4
16kΩ
DAC3 TO DAC4
TIMERS + STATE MACHINES
PHASE1
DDS1
DDS2
START DLY
START ADDR
TUNING WORD
DAC CLOCK
R
SET3
16kΩ
STOP ADDR
DDS
1.8V
LDO
CLOCK
DIST
DDS3
DDS4
1.8V
LDOs
PHASE4
PHASE3
Figure 1.
Rev. A | Page 3 of 48
AD9106
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2; IOUTFS = 4 mA, maximum sample rate,
unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
RESOLUTION
12
Bits
ACCURACY at 3.3 V
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
±±.4
±±.5
LSB
LSB
DAC OUTPUTS
Offset Error
±.±±±25
% of FSR
% of FSR
mA
Gain Error Internal Reference—No Automatic IOUTFS Calibration
Full-Scale Output Current1 at 3.3 V
Output Resistance
−1.±
2
+1.±
8
4
2±±
MΩ
Output Compliance Voltage
Crosstalk, DAC to DAC (fOUT = 1± MHz)
Crosstalk, DAC to DAC (fOUT = 6± MHz)
−±.5
+1.±
V
96
82
dBC
dBc
DAC TEMPERATURE DRIFT
Gain with Internal Reference
Internal Reference Voltage
REFERENCE OUTPUT
±251
±119
ppm/°C
ppm/°C
Internal Reference Voltage with AVDD = 3.3 V
Output Resistance
±.8
±.1
1.±
1±
1.2
V
kΩ
REFERENCE INPUT
Voltage Compliance
1.25
V
Input Resistance External, Reference Mode
DAC MATCHING
1
MΩ
Gain Matching—No Automatic IOUTFS Calibration
±±.75
% of FSR
1 Based on use of 8 kΩ external xRSET resistors.
Rev. A | Page 4 of 48
Data Sheet
AD9106
DC SPECIFICATIONS (1.8 V)
TMIN to TMAX, AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO = 1.8 V, IOUTFS = 4 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
RESOLUTION
12
Bits
ACCURACY at 1.8 V
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
DAC OUTPUTS
±±.4
±±.4
LSB
LSB
Offset Error
±.±±±25
% of FSR
% of FSR
mA
Gain Error Internal Reference—No Automatic IOUTFS Calibration
Full-Scale Output Current1 at 1.8 V
Output Resistance
−1.±
2
+1.±
4
4
2±±
MΩ
Output Compliance Voltage
Crosstalk, DAC to DAC (fOUT = 3± MHz)
Crosstalk, DAC to DAC (fOUT = 6± MHz)
DAC TEMPERATURE DRIFT
Gain
−±.5
+1.±
V
94
78
dB
dB
±228
±131
ppm/°C
ppm/°C
Reference Voltage
REFERENCE OUTPUT
Internal Reference Voltage with AVDD = 1.8 V
Output Resistance
±.8
±.1
1.±
1±
1.2
V
kΩ
REFERENCE INPUT
Voltage Compliance
1.25
V
Input Resistance External, Reference Mode
DAC MATCHING
1
MΩ
Gain Matching—No Automatic IOUTFS Calibration
1 Based on use of 8 kΩ external xRSET resistors.
±±.75
% of FSR
Rev. A | Page 5 of 48
AD9106
Data Sheet
DIGITAL TIMING SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2; IOUTFS = 4 mA, maximum sample rate,
unless otherwise noted.
Table 3.
Parameter
Min
18±
8±
Typ
Max
Unit
DAC CLOCK INPUT (CLKIN)
Maximum Clock Rate
MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time SDIO to SCLK
Hold Time SDIO to SCLK
Output Data Valid SCLK to SDO or SDIO
Setup Time CS to SCLK
MHz
ns
ns
ns
ns
6.25
6.25
4.±
5.±
6.2
ns
ns
4.±
DIGITAL TIMING SPECIFICATIONS (1.8 V)
TMIN to TMAX, AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO = 1.8 V, IOUTFS = 4 mA, maximum sample rate, unless
otherwise noted.
Table 4.
Parameter
Min
18±
8±
Typ
Max
Unit
DAC CLOCK INPUT (CLKIN)
Maximum Clock Rate
MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time SDIO to SCLK
Hold Time SDIO to SCLK
Output Data Valid SCLK to SDO or SDIO
Setup Time CS to SCLK
MHz
ns
ns
ns
ns
6.25
6.25
4.±
5.±
8.8
ns
ns
4.±
Rev. A | Page 6 of 48
Data Sheet
AD9106
INPUT/OUTPUT SIGNAL SPECIFICATIONS
Table 5.
Parameter
Test Conditions/ Comments
Min
Typ
Max
Unit
CMOS INPUT LOGIC LEVEL (SCLK, CS, SDIO, SDO/SDI2/DOUT, RESET,
TRIGGER)
Input VIN Logic High
DVDD = 1.8 V
DVDD = 3.3 V
DVDD = 1.8 V
DVDD = 3.3 V
1.53
2.475
V
V
V
V
Input VIN Logic Low
±.27
±.825
CMOS OUTPUT LOGIC LEVEL (SDIO, SDO/SDI2/DOUT)
Output VOUT Logic High
DVDD = 1.8 V
DVDD = 3.3 V
DVDD = 1.8 V
DVDD = 3.3 V
1.79
3.28
V
V
V
V
Output VOUT Logic Low
±.25
±.625
DAC CLOCK INPUT (CLKP, CLKN)
Minimum Peak-to-Peak Differential Input Voltage, VCLKP/VCLKN
Maximum Voltage at VCLKP or VCLKN
Minimum Voltage at VCLKP or VCLKN
15±
mV
V
V
VDVDD
VDGND
±.9
Common-Mode Voltage Generated on Chip
V
Rev. A | Page 7 of 48
AD9106
Data Sheet
AC SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V; internal CLDO, DLDO1, and DLDO2; IOUTFS = 4 mA, maximum sample rate,
unless otherwise noted.
Table 6.
Parameter
Min
Typ
Max
Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR)
f
f
DAC = 18± MSPS, fOUT = 1± MHz
DAC = 18± MSPS, fOUT = 5± MHz
86
73
dBc
dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)
f
f
DAC = 18± MSPS, fOUT = 1± MHz
DAC = 18± MSPS, fOUT = 5± MHz
92
77
dBc
dBc
NSD
f
DAC = 18± MSPS, fOUT = 5± MHz
−167
−135
dBm/Hz
dBc/Hz
PHASE NOISE at 1 kHz FROM CARRIER
f
DAC = 18± MSPS, fOUT = 1± MHz
DYNAMIC PERFORMANCE
Output Settling Time, Full Scale Output Step (to ±.1%)1
Trigger to Output Delay, fDAC = 18± MSPS2
Rise Time, Full-Scale Swing1
31.2
96
3.25
3.26
ns
ns
ns
ns
Fall Time, Full-Scale Swing1
1 Based on the 85 Ω resistors from DAC output terminals to ground.
2 Start delay = ± fDAC clock cycles.
AC SPECIFICATIONS (1.8 V)
TMIN to TMAX, AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO = 1.8 V, IOUTFS = 4 mA, maximum sample rate, unless
otherwise noted.
Table 7.
Parameter
Min
Typ
Max
Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR)
f
f
DAC = 18± MSPS, fOUT = 1± MHz
DAC = 18± MSPS, fOUT = 5± MHz
83
74
dBc
dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)
f
f
DAC = 18± MSPS, fOUT = 1± MHz
DAC = 18± MSPS, fOUT = 5± MHz
91
83
dBc
dBc
NSD
fDAC = 18± MSPS, fOUT = 5± MHz
PHASE NOISE at 1 kHz FROM CARRIER
DAC = 18± MSPS, fOUT = 1± MHz
−163
−135
dBm/Hz
dBc/Hz
f
DYNAMIC PERFORMANCE
Output Settling Time (to ±.1%)1
Trigger to Output Delay, fDAC = 18± MSPS2
Rise Time1
31.2
96
3.25
3.26
ns
ns
ns
ns
Fall Time1
1 Based on the 85 Ω resistors from DAC output terminals to ground.
2 Start delay = ± fDAC clock cycles.
Rev. A | Page 8 of 48
Data Sheet
AD9106
POWER SUPPLY VOLTAGE INPUTS AND POWER DISSIPATION
Table 8.
Parameter
Test Conditions/Comments
Min Typ
Max Unit
ANALOG SUPPLY VOLTAGES
AVDD1, AVDD2
CLKVDD
1.7
1.7
1.7
3.6
3.6
1.9
V
V
V
CLDO
On-chip LDO not in use
On-chip LDO not in use
DIGITAL SUPPLY VOLTAGES
DVDD
1.7
1.7
3.6
1.9
V
V
DLDO1, DLDO2
POWER CONSUMPTION
AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1,
and DLDO2
fDAC = 18± MSPS, Pure CW Sine Wave
12.5 MHz (DDS only), all four DACs
315.25
mW
mA
IAVDD
28.51
IDVDD
DDS Only
RAM Only
DDS and RAM Only
ICLKVDD
CW sine wave output
6±.3
27.1
39.75
6.72
4.73
mA
mA
mA
mA
mW
5±% duty cycle FS pulse output
5±% duty cycle sine wave output
Power-Down Mode
REF_PDN = ±, DACs sleep, CLK power down, external CLK, and
supplies on
POWER CONSUMPTION
AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1.8 V, CLKVDD = CLDO =
1.8 V
fDAC = 18± MSPS, Pure CW Sine Wave
12.5 MHz (DDS only)
167
mW
mA
mA
IAVDD
28.14
±.151
IDVDD
IDLDO2
DDS Only
RAM Only
CW sine wave output
53.75
17.78
35.4
mA
mA
mA
5±% duty cycle FS pulse output
DDS and RAM Only—5±% Duty Cycle Sine
Wave Output
IDLDO1
4.±
mA
mA
mA
mW
ICLKVDD
±.±±96
6.6
ICLDO
Power-Down Mode
REF_PDN = ±, DACs sleep, CLK power down, external CLK, and
supplies on
1.49
Rev. A | Page 9 of 48
AD9106
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 9.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a standard circuit board for surface-mount
packages. θJC is measured from the solder side (bottom) of the
package.
Parameter
Rating
AVDD1, AVDD2, DVDD to AGND,
DGND, CLKGND
CLKVDD to AGND, DGND, CLKGND
CLDO, DLDO1, DLDO2 to AGND,
DGND, CLKGND
AGND to DGND, CLKGND
DGND to AGND, CLKGND
CLKGND to AGND, DGND
CS, SDIO, SCLK, SDO/SDI2/DOUT,
RESET, TRIGGER to DGND
−±.3 V to +3.9 V
−±.3 V to +3.9 V
−±.3 V to +2.2 V
Table 10. Thermal Resistance
Package Type
θJA
θJB
θJC
Unit
οC/W
−±.3 V to +±.3V
−±.3 V to +±.3 V
−±.3 V to +±.3 V
−±.3 V to DVDD + ±.3 V
32-Lead LFCSP with
Exposed Paddle
3±.18 6.59
3.84
ESD CAUTION
CLKP, CLKN to CLKGND
REFIO to AGND
IOUTP1, IOUTN1, IOUTP2, IOUTN2,
IOUTP3, IOUTN3, IOUTP4, IOUTN4 to
AGND
−±.3 V to CLKVDD + ±.3 V
−1.± V to AVDD + ±.3 V
−±.3 V to DVDD + ±.3 V
FSADJ1, FSADJ2/CAL_SENSE, F4DJ3,
FSADJ4 to AGND
Junction Temperature
Storage Temperature
−±.3 V to AVDD + ±.3 V
125 οC
−65 οC to +15± οC
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 1± of 48
Data Sheet
AD9106
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCLK
SDIO
DGND
DLDO2
DVDD
1
2
3
4
5
6
7
8
24 FSADJ2/CAL_SENSE
23
22 CLDO
21 CLKP
CLKVDD
AD9106
TOP VIEW
20
19
CLKN
CLKGND
(Not to Scale)
DLDO1
SDO/SDI2/DOUT
CS
18 REFIO
17 FSADJ4
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.
Figure 2. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. Mnemonic Description
SPI Clock Input.
1
2
3
4
SCLK
SDIO
DGND
DLDO2
SPI Data Input/Output. Primary bidirectional data line for the SPI port.
Digital Ground.
1.8 V Internal Digital LDO1 Output. When the internal digital LDO1 is enabled, this pin should be bypassed
with a ±.1 µF capacitor.
5
6
7
DVDD
3.3 V External Digital Power Supply. DVDD defines the level of the digital interface of the AD91±6 (SPI
interface).
1.8 V Internal Digital LDO2 Outputs. When the internal digital LDO2 is enabled, this pin should be bypassed
with a ±.1 µFcapacitor.
DLDO1
SDO/SDI2/DOUT
Digital I/O Pin.
In 4-wire SPI mode, this pin outputs the data from the SPI.
In double SPI mode, this pin is a second data input line, SDI2, for the SPI port used to write to the SRAM.
In data output mode, this terminal is a programmable pulse output.
8
CS
SPI Port Chip Select, Active Low.
9
RESET
IOUTP4
IOUTN4
AVDD2
IOUTN3
IOUTP3
AGND
FSADJ3
FSADJ4
REFIO
Active Low Reset Pin. Resets registers to their default values.
DAC4 Current Output, Positive Side.
DAC4 Current Output, Negative Side.
1.8 V to 3.3 V Power Supply Input for DAC3 and DAC4.
DAC3 Current Output, Negative Side.
DAC3 Current Output, Positive Side.
Analog Ground.
External Full-Scale Current Output Adjust for DAC3.
External Full-Scale Current Output Adjust for DAC4.
DAC Voltage Reference Input/Output.
Clock Ground.
1±
11
12
13
14
15
16
17
18
19
2±
21
22
CLKGND
CLKN
CLKP
Clock Input, Negative Side.
Clock Input, Positive Side.
Clock Power Supply Output (Internal Regulator in Use), Clock Power Supply Input (Internal Regulator
Bypassed).
CLDO
23
24
25
CLKVDD
Clock Power Supply Input.
FSADJ2/CAL_SENSE External Full-Scale Current Output Adjust for DAC2 or Sense Input for Automatic IOUTFS Calibration.
FSADJ1
External Full-Scale Current Output Adjust for DAC1 or Full-Scale Current Output Adjust Reference for
Automatic IOUTFS Calibration.
26
27
AGND
IOUTP1
Analog Ground.
DAC1 Current Output, Positive Side.
Rev. A | Page 11 of 48
AD9106
Data Sheet
Pin No. Mnemonic
Description
28
29
3±
31
32
IOUTN1
AVDD1
IOUTN2
IOUTP2
TRIGGER
EPAD
DAC1 Current Output, Negative Side.
1.8 V to 3.3 V Power Supply Input for DAC1 and DAC2.
DAC2 Current Output, Negative Side.
DAC2 Current Output, Positive Side.
Pattern Trigger Input.
Exposed Pad. The exposed pad must be connected to DGND.
Rev. A | Page 12 of 48
Data Sheet
AD9106
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, internal CLDO, DLDO1, and DLDO2.
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
8mA
SFDR
THIRD (dBc)
2mA
4mA
SECOND (dBc)
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
F
(MHz)
F
(MHz)
OUT
OUT
Figure 3. SFDR, 2nd and 3rd Harmonics at IOUTFS = 8 mA vs. FOUT
Figure 6. SFDR at Three IOUTFS vs. FOUT
–50
–55
–60
–65
–70
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
SFDR
–75
–40°C
–80
–85
–90
+85°C
+25°C
10
SECOND (dBc)
THIRD (dBc)
–95
–100
0
10
20
30
40
50
60
70
0
20
30
40
50
60
70
F
(MHz)
F
(MHz)
OUT
OUT
Figure 4. SFDR, 2nd and 3rd Harmonics at IOUTFS = 4 mA vs. FOUT
Figure 7. SFDR at Three Temperatures vs. FOUT
–50
–55
–60
–65
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
100MHz
180MHz
50MHz
SFDR
–70
–75
–80
–85
SECOND (dBc)
–90
THIRD (dBc)
–95
–100
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
F
(MHz)
F
(MHz)
OUT
OUT
Figure 5. SFDR, 2nd and 3rd Harmonics at IOUTFS = 2 mA vs. FOUT
Figure 8. SFDR at Three FDAC vs. FOUT
Rev. A | Page 13 of 48
AD9106
Data Sheet
MKR3 41.73MHz
–90.031dBm
–60
–65
–70
–75
–80
–85
–90
–95
–100
REF –5dBm
ATTEN 18dB
1
DAC4
DAC2
DAC3
DAC1
2
3
0
10
20
30
40
(MHz)
50
60
70
80
F
OUT
START 0Hz
VBW 5.6kHz
X-AXIS
STOP 80MHz
SWEEP 3.076s (601PTS)
MARKER TRACE TYPE
AMPLITUDE
1
2
3
(1)
(1)
(1)
FREQ
FREQ
FREQ
13.87MHz –11.13dBm
27.87MHz –88.70dBm
41.73MHz –90.03dBm
Figure 12. IMD vs. FOUT, All Four DACs
Figure 9. Output Spectrum FOUT = 13.87 MHz
–130
–135
–140
–145
–150
–155
–160
–165
–170
–60
–65
–70
–75
–80
–85
–90
–95
–100
100MHz
180MHz
50MHz
8mA
4mA
2mA
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
(MHz)
50
60
70
80
F
(MHz)
F
OUT
OUT
Figure 10. IMD vs. FOUT, Three FDAC Values
Figure 13. NSD vs. FOUT, Three IOUTFS Values
–60
–65
–70
–75
–80
–85
–90
–95
–100
–130
–135
–140
–145
–150
–155
–160
–165
–170
8mA
2mA
4mA
–40°C
+25°C
+85°C
0
10
20
30
40
(MHz)
50
60
70
80
0
10
20
30
40
50
60
70
80
90
F
F
(MHz)
OUT
OUT
Figure 11. IMD vs. FOUT, Three IOUTFS Values
Figure 14. NSD vs. FOUT at Three Temperatures
Rev. A | Page 14 of 48
Data Sheet
AD9106
0.4
0.3
0.2
0.1
0
–80
–100
–120
–140
–160
–180
F
F
F
= 175MHz, 10MHz
= 175MHz, 10.9375MHz
= 175MHz, 20MHz
S
S
S
–0.1
–0.2
2mA
4mA
8mA
–0.3
0
500 1000 1500 2000 2500 3000 3500 4000 4500
100
1k
10k
100k
1M
10M
CODE
OFFSET (Hz)
Figure 15. DNL, Three IOUTFS Values
Figure 17. Phase Noise
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
2mA
4mA
8mA
0
500 1000 1500 2000 2500 3000 3500 4000 4500
CODE
Figure 16. INL, Three IOUTFS Values
Rev. A | Page 15 of 48
AD9106
Data Sheet
AVDD = 1.8 V, DVDD = DLDO1 = DLDO2 = 1 . 8 V, CLKVDD = CLDO = 1.8 V.
–50
–55
–60
–65
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
+85°C
–70
SFDR
–75
–80
–40°C
+25°C
THIRD (dBc)
–85
–90
SECOND (dBc)
–95
–100
0
10
20
30
40
50
60
70
0
10
20
30
40
(MHz)
50
60
70
F
(MHz)
F
OUT
OUT
Figure 18. SFDR, 2nd and 3rd Harmonics at IOUTFS = 4 mA vs. FOUT
Figure 21. SFDR at Three Temperatures vs. FOUT
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–50
–55
–60
–65
180MHz
50MHz
SFDR
180MHz
–70
–75
–80
SECOND (dBc)
–85
–90
THIRD (dBc)
–95
–100
0
10
20
30
F
40
50
60
70
0
10
20
30
F
40
50
60
70
(MHz)
(MHz)
OUT
OUT
Figure 22. SFDR at Three FDAC vs. FOUT
Figure 19. SFDR, 2nd and 3rd Harmonics at IOUTFS = 2 mA vs. FOUT
MKR3 41.73MHz
–88.255dBm
–50
–55
–60
–65
REF –5dBm
ATTEN 18dB
1
2mA
–70
–75
–80
4mA
–85
–90
–95
3
2
–100
0
10
20
30
40
50
60
70
F
(MHz)
OUT
START 0Hz
MARKER TRACE TYPE
VBW 5.6kHz
X-AXIS
13.87MHz –11.13dBm
27.87MHz –89.05dBm
41.73MHz –88.25dBm
STOP 80MHz
SWEEP 3.076s (601PTS)
AMPLITUDE
1
2
3
(1)
(1)
(1)
FREQ
FREQ
FREQ
Figure 20. SFDR at Two IOUTFS vs. FOUT
Figure 23. Output Spectrum FOUT = 13.87 MHz
Rev. A | Page 16 of 48
Data Sheet
AD9106
–60
–65
–70
–130
–135
–140
–145
–150
–155
–160
–165
–170
100MHz
180MHz
–75
50MHz
–80
–85
4mA
–90
2mA
–95
–100
0
10
20
30
40
(MHz)
50
60
70
80
0
10
20
30
40
50
60
70
80
90
F
F
(MHz)
OUT
OUT
Figure 27. NSD vs. FOUT, Two IOUTFS Values
Figure 24. IMD vs. FOUT, Three FOUT Values
–60
–65
–70
–75
–80
–85
–90
–95
–100
–130
–135
–140
–145
–150
–155
–160
–165
–170
4mA
+85°C
+25°C
2mA
–40°C
0
10
20
30
40
(MHz)
50
60
70
80
0
10
20
30
40
50
60
70
80
90
F
F
(MHz)
OUT
OUT
Figure 25. IMD vs. FOUT, Two IOUTFS Values
Figure 28. NSD vs. FOUT at Three Temperatures
–60
–65
–70
–75
–80
–85
–90
–95
–100
0.5
0.4
0.3
0.2
0.1
0
2mA
4mA
DAC4
DAC3
DAC2
DAC1
–0.1
–0.2
0
10
20
30
40
(MHz)
50
60
70
80
0
500 1000 1500 2000 2500 3000 3500 4000 4500
CODE
F
OUT
Figure 26. IMD vs. FOUT, All Four DACs
Figure 29. DNL, Three IOUTFS Values
Rev. A | Page 17 of 48
AD9106
Data Sheet
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
2mA
4mA
0
500 1000 1500 2000 2500 3000 3500 4000 4500
CODE
Figure 30. INL, Two IOUTFS Values
Rev. A | Page 18 of 48
Data Sheet
AD9106
TERMINOLOGY
Power Supply Rejection
Linearity Error (Integral Nonlinearity or INL)
INL is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero to full scale.
Power supply rejection is the maximum change in the full-scale
output as the supplies are varied from nominal to minimum
and maximum specified voltages.
Settling Time
Differential Nonlinearity (DNL)
Settling time is the time required for the output to reach and
remain within a specified error band about its final value,
measured from the start of the output transition.
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
Glitch Impulse
A digital-to-analog converter is monotonic if the output either
increases or remains constant as the digital input increases.
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in picovolt-seconds (pV-s).
Offset Error
Offset error is the deviation of the output current from the ideal of
zero. For IOUTPx, 0 mA output is expected when the inputs are all
0s. For IOUTNz, 0 mA output is expected when all inputs are set to 1.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the output signal and the peak spurious signal
over the specified bandwidth.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the output when all inputs
are set to 1, minus the output when all inputs are set to 0. The
ideal gain is calculated using the measured VREF. Therefore,
the gain error does not include effects of the reference.
Noise Spectral Density (NSD)
Noise spectral density is the average noise power normalized to
a 1 Hz bandwidth, with the DAC converting and producing an
output tone.
Output Compliance Voltage
Output compliance voltage is the range of allowable voltage
at the output of a current output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from
the ambient (25°C) value to the value at either TMIN or TMAX
.
For offset and gain drift, the drift is reported in ppm of full-
scale range (FSR) per °C. For reference drift, the drift is
reported in ppm per °C.
Rev. A | Page 19 of 48
AD9106
Data Sheet
THEORY OF OPERATION
1V
AD9106
10kΩ
SPI
INTERFACE
AGND
STOP ADDR
START ADDR
START DLY
R
R
SET1
16kΩ
SET2
16kΩ
DAC1 TO DAC2
TRIGGER
I
REF
100µA
GAIN1 OFFSET1
TIMERS + STATE MACHINES
ADDRESS 1, 2
IOUTP1
IOUTN1
AVDD1
IOUTP2
IOUTN2
DAC1
DAC1
GAIN2 OFFSET2
GAIN3 OFFSET3
DAC2
DAC3
DAC2
DAC3
BAND
GAP
DPRAM
IOUTP3
IOUTN3
AVDD2
IOUTP4
IOUTN4
DAC4
GAIN4 OFFSET4
PHASE2
ADDRESS 3, 4
DAC4
R
16kΩ
SET4
DAC3 TO DAC4
TIMERS + STATE MACHINES
PHASE1
DDS1
DDS2
START DLY
START ADDR
TUNING WORD
DAC CLOCK
R
16kΩ
SET3
STOP ADDR
DDS
1.8V
LDO
CLOCK
DIST
DDS3
DDS4
1.8V
LDOs
PHASE4
PHASE3
Figure 31. AD9106 Block Diagram
Figure 31 is a block diagram of the AD9106. The AD9106 has
four 12-bit current output DACs.
be connected to DVDD, with the on-chip LDOs disabled. All
three supplies are provided externally in this case. This also
applies to CLKVDD and CLDO if CLKVDD = 1.8 V.
The DACs use a single common voltage reference. An on-chip
band gap reference is provided. Optionally, an off-chip voltage
reference may be used. Full-scale DAC output current, also
known as gain, is governed by the current, IREF. IREF is the
current that flows through each IREF resistor. Each DAC has its
own IREF set resistor. These resistors may be on or off chip at
the discretion of the user. When on-chip RSET resistors are in
use DAC gain accuracy can be improved by employing the
product’s built in automatic gain calibration capability. Auto-
matic calibration may be used with the on-chip reference or
an external REFIO voltage. A procedure for automatic gain
calibration is presented in this section.
Digital signals input to the four DACs are generated by on-chip
digital waveform generation resources. Twelve-bit samples are
input to each DAC at the CLKP/CLKN sample rate from a
dedicated digital data path. Each DAC’s data path includes gain
and offset corrections and a digital waveform source selection
multiplexer. Waveform sources are SRAM, direct digital
synthesizer (DDS), DDS output amplitude modulated by SRAM
data, a sawtooth generator, dc constant, and a pseudo-random
sequence generator. The waveforms output by the source
selection multiplexer have programmable pattern character-
istics. The waveforms can be set up to be continuous,
continuous pulsed (fixed pattern period and start delay within
each pattern period), or finite pulsed (a set number of pattern
periods are output, then the pattern stops).
The power supply rails for the AD9106 are AVDD for analog
circuits, CLKVDD/CLDO for clock input receiver and
DVDD/DLDO1/DLDO2 for digital I/O and for the on-chip
digital data path. AVDD, DVDD, and CLKVDD can range from
1.8 V to 3.3 V nominal. DLDO1, DLDO2, and CLDO run at
1.8 V. If DVDD = 1.8 V, then DLDO1 and DLDO2 should both
Pulsed waveforms (finite or continuous) have a programmed
pattern period and start delay. The waveform is present in each
Rev. A | Page 2± of 48
Data Sheet
AD9106
pulse period following the global (applies to all four DACs)
programmed pattern period start and each DAC’s start delay.
W
When the first bit of this command byte is a logic low (R
bit = 0), the SPI command is a write operation. In this case,
SDIO remains an input (see Figure 32).
An SPI port enables loading of data into SRAM and program-
ming of all the control registers inside the device.
COMMAND CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
SPI PORT
The AD9106 provides a flexible, synchronous serial communi-
cations (SPI) port that allows easy interfacing to ASICs, FPGAs,
and industry standard microcontrollers. The interface allows
read/write access to all registers that configure the AD9106 and
to the on-chip SRAM. Its data rate can be up to the SCLK clock
speed shown in Table 3 and Table 4.
Figure 32. Serial Register Interface Timing, MSB First Write, 3-Wire SPI
W
When the first bit of this command byte is a logic high (R
bit = 1), the SPI command is a read operation. In this case, data
is driven out of the SPI port as shown in Figure 33 and Figure 34.
The SPI interface operates as a standard synchronous serial
CS
CS
communication port.
is a low true chip select. When
CS
The SPI communication finishes after the
pin goes high.
goes true, SPI address and data transfer begins. The first bit
coming from the SPI master on SDIO is a read/write indicator
(high for read, low for write). The next 15-bits are the initial
register address. The SPI port automatically increments the
COMMAND CYCLE
DATA TRANSFER CYCLE
CS
SCLK
CS
register address if
stays low beyond the first data word
allowing writes to or reads from a set of contiguous addresses.
SDIO
Table 12. Command Word
Figure 33. Serial Register Interface Timing, MSB First Read, 3-Wire SPI
MSB
DB15
RW
LSB
DB14 DB13 DB12
A14 A13 A12
…
DB2 DB1 DB0
…
A2
A1
A±
WRITE
READ
CS
SCLK
SDIO
SDO/
SDI2/
DOUT
Figure 34. Serial Register Interface Timing, MSB First Read, 4-Wire SPI
Rev. A | Page 21 of 48
AD9106
Data Sheet
Writing to On-Chip SRAM
I
OUTFSx = 32 × IIREFx
where:
REFx = VREFIO/xRSET
(3)
The AD9106 includes an internal 4096 × 12 SRAM. The SRAM
address space is 0x6000 to 0x6FFF of the AD9106 SPI address map.
I
(4)
Double SPI for Write for SRAM
IREFx is the current that flows through each IREFx resistor. Each
DAC has its own IREF set resistor. IREF resistors may be on or off
chip at the users’ discretion. When on-chip xRSET resistors are
in use, DAC gain accuracy can be improved by employing the
product’s built in automatic gain calibration capability.
The time to write data to the entire SRAM can be halved using
the SPI access mode shown in Figure 35. The SDO/SDI2/
DOUT line becomes a second serial data input line, doubling
the achievable update rate of the on-chip SRAM. SDO/SDI2/
DOUT is write-only in this mode. The entire SRAM can be
written in (2 + 2 × 4096) × 8/(2 × FSCLK)seconds.
SET WAVEFORM ADDRESS
ANALOG CURRENT OUTPUTS
Optimum linearity and noise performance of DAC outputs
can be achieved when they are connected differentially to an
amplifier or a transformer. In these configurations, common-
mode signals at the DAC outputs are rejected.
TO BE READ/WRITTEN
WAVEFORM DATA TO BE WRITTEN
CS
SCLK
The output compliance voltage specifications shown in
Table 1 and Table 2 must be adhered to for the performance
specifications in these tables to be met.
SDIO
WAVEFORM PATTERN
ADDRESS1 = N
WAVEFORM
PATTERN DATA
SETTING IOUTFSx, DAC GAIN
As expressed in Equation 3 and Equation 4, DAC gain (IOUTFSx
is a function of the reference voltage at the REFIO terminal and
xRSET for each DAC.
)
SDO/
SDI2/
DOUT
WAVEFORM PATTERN
ADDRESS2 = M
WAVEFORM
PATTERN DATA
Voltage Reference
Figure 35. Double SPI Write of SRAM Data
The AD9106 contains an internal 1.0 V nominal band gap
reference. The internal reference may be used. Alternatively,
it can be replaced by a more accurate off-chip reference. An
external reference can provide tighter reference voltage
tolerances and/or lower temperature drift than the on-chip
band gap.
Configuration Register Update Procedure
Most SPI accessible registers are double buffered. An active
register set controls operation of the AD9106 during pattern
generation. A set of shadow registers stores updated register
values. Register updates can be written at any time and when
the configuration update is complete, a 1 is written to the
UPDATE bit in the RAMUPDATE register. The UPDATE bit
arms the register set for transfer from shadow registers to active
registers. The AD9106 will perform this transfer automatically
the next time the pattern generator is off. This procedure does
not apply to the 4K × 12 SRAM. Refer to the SRAM section for
the SRAM update procedure.
By default, the on-chip reference is powered up and ready to be
used. When using the on-chip reference, the REFIO terminal
needs to be decoupled to AGND using a 0.1 μF capacitor as
shown in Figure 36.
AD9106
V
1.0V
BG
DACx
DAC TRANSFER FUNCTION
REFIO
+
–
FSADJx
The AD9106 DACs provide four differential current outputs:
IOUTP1/IOUTN1, IOUTP2/IOUTN2, IOUTP3/IOUTN3, and
IOUTP4/IOUTN4.
CURRENT
SCALING
x32
0.1µF
I
OUTFSx
xR
SET
I
The DAC output current equations are as follows:
REFx
AVSS
IOUTPx= IOUTFSx × xDAC INPUT CODE/212
IOUTNx = IOUTFSx × ((212 − 1) − xDAC INPUT CODE)/212
(2)
(1)
Figure 36. On-Chip Reference with External xRSET Resistor
Table 13 summarizes reference connections and programming.
Table 13. Reference Operation
where:
xDAC INPUT CODE = 0 to 212 − 1.
OUTFSx = full-scale current or DAC gain set independently for
each DAC.
Reference Mode
REFIO Pin
Internal
Connect ±.1 µF capacitor
Connect off-chip reference
I
External
Rev. A | Page 22 of 48
Data Sheet
AD9106
Programming Internal VREFIO
chosen by the CAL_CLK_DIV bits of Register 0x0D. Each
calibration cycle is between 4 and 512 DAC clock cycles,
depending on the value of CAL_CLK_DIV[2:0]. The frequency
of the calibration clock should be less than 500 kHz.
The internal REFIO voltage level is programmable.
When the internal voltage reference is in use, the BGDR field in
the lower six bits in Register 0x03 adjusts the VREFIO level. This
adds or subtracts up to 20% from the nominal band gap voltage
on REFIO. The voltage across the FSADJx resistors tracks this
change. As a result, IREFx varies by the same amount. Figure 37
shows VREFIO vs. BGDR code for an on-chip reference with a
default voltage (BGDR = 0x00) of 1.04 V.
To perform an automatic calibration, follow these steps:
1. Set the calibration ranges in Registers 0x08[7:0] and
0x0D[5:4] to their minimum values to allow best
calibration.
2. Enable the calibration clock bit, CAL_CLK_EN, in
Register 0x0D.
1.30
3. Set the divider ratio for the calibration clock by setting
CAL_CLK_DIV[2:0] bits in Register 0x0D. The default is
512.
4. Set the CAL_MODE_EN bit in Register 0x0D to Logic 1.
5. Set the START_CAL bit in Register 0x000E to Logic 1. This
begins the calibration of the comparator, xRSET and gain.
6. The CAL_MODE flag in Register 0x000D will go to
Logic 1 while the part is calibrating. The CAL_FIN flag in
Register 0x0E will go to Logic 1 when the calibration is
complete.
7. Set the START_CAL bit in Register 0x0E to Logic 0.
8. After calibration, verify that the overflow and underflow
flags in Register 0x0D are not set (Bits[14:8]). If they are,
change the corresponding calibration range to the next
larger range and begin again at Step 5.
9. If no flag is set, read the DACx_RSET_CAL and
DACx_AGAIN_CAL values in the DACxRSET[12:8] and
DACxGAIN[14:8] registers, respectively, and write them
into their corresponding DACxRSET and DACxAGAIN
registers.
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0
8
16
24
32
40
48
56
CODE
Figure 37. Typical VREF Voltage vs. BGDR
xRSET Resistors
xRSET in Equation 4 for each DAC can be an internal resistor or
a board level resistor of the users choosing connected to the
appropriate FSADJx terminal.
To make use of on-chip xRSET resistors, Bit15 of Register 0x0C,
Register 0x0B, Register 0x0A, and Register 0x09 for DAC1,
DAC2, DAC3, and DAC4, respectively, are set to Logic 1.
Bits[4:0] of Register 0x0C, Register 0x0B, Register 0x0A, and
Register 0x09 are used to manually program values for the on-chip
xRSET associated with DAC1, DAC2, DAC3, and DAC4,
respectively.
10. Reset the CAL_MODE_EN bit and the calibration clock bit
CAL_CLK_EN in Register 0x0D to Logic 0 to disable the
calibration clock.
11. Set the CAL_MODE_EN bit in Register 0x0D to Logic 0.
This sets the RSET and gain control muxes towards the
regular registers.
12. Disable the calibration clock bit, CAL_CLK_EN, in
Register 0x0D.
AUTOMATIC IOUTFSX CALIBRATION
Many applications require tight DAC gain control. The AD9106
provides an automatic IOUTFSx calibration procedure used with
on-chip xRSET resistors only. The voltage reference VREFIO can be
the on-chip reference or an off-chip reference. The automatic
calibration procedure does a fine adjustment of each internal
To reset the calibration, pulse the CAL_RESET bit in Register 0x0D
RESET
to Logic 1 and Logic 0, pulse the
in the SPICONFIG register.
pin, or pulse the RESET bit
CLOCK INPUT
xRSET value and each current IREFx
.
For optimum DAC performance, the AD9106 clock input signal
pair (CLKP/CLKN) should be a very low jitter, fast rise time
differential signal. The clock receiver generates its own common-
mode voltage requiring these two inputs to be ac-coupled.
When using automatic calibration the following board-level
connections are required:
1. Connect FSADJ1 and FSADJ2/CAL_SENSE together.
2. A resistor should be installed between FSADJ2/
CAL_SENSE and ground. The value of this resistor should
be RCAL_SENSE = 32 × VREFIO/IOUTFS where IOUTFS is the target
full-scale current for all four DACs.
Figure 38 shows the recommended interface to a number of
Analog Devices, Inc., LVDS clock drivers that work well with the
AD9106. A 100 Ω termination resistor and two 0.1 µF coupling
capacitors are used. Figure 40 shows an interface to an Analog
Devices differential PECL driver. Figure 41 shows a single-ended-
to-differential converter using a balun driving CLKP/CLKN, the
preferred methods for clocking the AD9106.
Automatic calibration uses an internal clock. This calibration
clock is equal to the DAC clock divided by the division factor
Rev. A | Page 23 of 48
AD9106
Data Sheet
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
AD9516/AD9518
GENERATING SIGNAL PATTERNS
The AD9106 can generate three types of signal patterns under
control of its programmable pattern generator.
0.1µF
0.1µF
CLK+
CLK
CLKP
100Ω
AD9106
LVDS DRIVER
CLK
•
•
•
Continuous waveforms
0.1µF
0.1µF
CLK–
CLKN
Periodic pulse train waveforms that repeat indefinitely
Periodic pulse train waveforms that repeat a finite number
of times
50Ω*
50Ω*
*50Ω RESISTORS ARE OPTIONAL.
Run Bit
Figure 38. Differential LVDS Clock Input
Setting the RUN bit in the PAT_STATUS register to 1 arms the
AD9106 for pattern generation. Clearing this bit shuts down the
pattern generator as shown in Figure 45.
In applications where the analog output signals are at low
frequencies, it is acceptable to drive the AD9106 clock input
with a single-ended CMOS signal. Figure 39 shows such an
interface. CLKP is driven directly from a CMOS gate, and the
CLKN pin is bypassed to ground with a 0.1 μF capacitor in
parallel with a 39 kΩ resistor. The optional resistor is a series
termination.
Trigger Terminal
A falling edge on the trigger terminal starts the generation of a
pattern. If RUN is set, the falling edge of trigger starts pattern
generation. As shown in Figure 43, the pattern generator state
goes to “pattern on” a number of CLKP/CLKN clock cycles
following the falling edge of trigger. This delay is programmed
in the PATTERN_DELAY bit field.
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
0.1µF
AD9516/AD9518
CLK+
CLK
50Ω
CMOS DRIVER
CLK
CLKP
The rising edge on the trigger terminal is a request for the
termination of pattern generation (see Figure 44).
OPTIONAL
100Ω
AD9106
CLKN
0.1µF
Pattern Bit (Read Only)
0.1µF
39kΩ
The read-only PATTERN bit in the PAT_STATUS register
indicates, when set to 1, that the pattern generator is in the
“pattern on” state. A 0 indicates that the pattern generator is in
the “pattern off ” state.
Figure 39. Single-Ended 1.8 V CMOS Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515/
0.1µF
AD9516/AD9518
0.1µF
CLK+
CLK–
CLK
CLKP
100Ω
AD9106
PECL DRIVER
0.1µF
0.1µF
CLKN
CLK
240Ω
240Ω
50Ω*
50Ω*
*50Ω RESISTORS ARE OPTIONAL.
Figure 40. Differential PECL Sample Clock
®
Mini-Circuits
ADT1-1WT, 1:1Z
0.1µF
0.1µF
XFMR
CLK+
CLKP
50Ω
AD9106
0.1µF
CLKN
SCHOTTKY
DIODES:
HSM2812
Figure 41. Transformer Coupled Clock
DAC OUTPUT CLOCK EDGE
Each of the four DACs can be configured independently to
output samples on the rising or falling edge of the CLKP/CLKN
clock input by configuring the DACx_INV_CLK bits in the
CLOCKCONFIG register. This functionality sets the DAC
output timing resolution at 1/(2 × FCLKP/CLKN).
Rev. A | Page 24 of 48
Data Sheet
AD9106
Pattern Types
Setting Waveform Start Delay Base
The waveform start delay base is programmed in the
•
Continuous waveforms are output by some or all DACx for
START_DELAY_BASE field of the PAT_TIMEBASE register.
Each DACx has a START_DLYx register described in
the DACX Input Data Paths section. The start delay base
determines how many CLKP/CLKN clock cycles there are
per START_DELAYx LSB.
the duration of the pattern on state of the pattern
generator. Continuous waveforms ignore pattern periods.
Periodic pulse trains that repeat indefinitely are waveforms
that are output once during each pattern period. Pattern
periods occur one after the other as long as the pattern
generator is in the pattern on state.
Periodic pulse trains that repeat a finite number of times
are just like those that repeat indefinitely except that the
waveforms are output during a finite number of
consecutive pattern periods.
•
RUN BIT
•
tDLY = PATTERN_DELAY VALUE + 1
tSU
PATTERN
STARTS
TRIGGER
TRIGGER
CLKP/
CLKN
PATTERN
EXECUTED
PATTERN
EXECUTED
PATTERN
EXECUTED
PATTERN_PERIOD
PATTERN
GENERATOR
STATE
PATTERN
GENERTAOR OFF
PATTERN
GENERTAOR ON
START_DLY1
DAC1
Figure 43. Trigger Initiated Pattern Start with Pattern Delay
tSU
DATA @
STOP_ADDR.1
DATA @
START_ADDR.1
TRIGGER
START_DLY2
DAC2
DATA @
STOP_ADDR.2
DATA @
START_ADDR.2
CLKP/
CLKN
START_DLY3
PATTERN
GENERATOR
STATE
DAC3
PATTERN ON
PATTERN OFF
PATTERN
STOPS
DATA @
STOP_ADDR.3
DATA @
START_ADDR.3
START_DLY4
DAC4
Figure 44. Trigger Rising Edge Initiated Pattern Stop
DATA @
STOP_ADDR.4
DATA @
START_ADDR.4
Figure 42. Periodic Pulse Trains output on all DACx
RUN
BIT
PATTERN GENERATOR PROGRAMMING
Figure 44 shows periodic pulse train waveforms as seen at
the output to each of the four DACx. The four waveforms are
generated in each pattern period. Each has its own start delay
(START_DLYx), a delay between the start of each pattern
period and the start of the waveform. The four DACx
waveforms are the same digital signal stored in SRAM and
multiplied by the DACx digital gain factor. The SRAM data
is read using each DACx address counter simultaneously.
CLKP/
CLKN
PATTERN
GENERATOR
STATE
PATTERN ON
PATTERN OFF
PATTERN
STOPS
Figure 45. RUN Bit Driven Pattern Stop
DACx INPUT DATA PATHS
Setting Pattern Period
Each of the four DACx has its own digital data path. Timing
in the DACx data paths is governed by the pattern generator.
Each DACx data path includes a waveform selector, a waveform
repeat controller, RAM output and DDS output multiplier
(RAM output can amplitude modulate DDS output), DDSx
cycle counter, DACx digital gain multiplier, and a DACx digital
offset summer.
Two register bit fields are used to set the pattern period. The
PAT_PERIOD_BASE field in the PAT_TIMEBASE register sets
the number of CLKP/N clock per PATTERN_PERIOD LSB.
The PATTERN_PERIOD is programmed in the PAT_PERIOD
register. The longest pattern period available is 65535 ×
16/FCLKP/CLKN
.
Rev. A | Page 25 of 48
AD9106
Data Sheet
Manually Controlled DOUT
DACx Digital Gain Multiplier
If DOUT_MODE = 0 in the DOUT_CONFIG register, DOUT can
be turned on or off using the DOUT_VAL bit of that same register.
On its way into each DACx, the samples are multiplied by a
12-bit gain factor that has a range of 2.0. These gain values are
programmed in the DACx_DGAIN registers.
Pattern Generator Controlled DOUT
DACx Digital Offset Summer
Figure 46 depicts the rising edge of a pattern generator
controlled DOUT pulse. Figure 47 shows the falling edge.
Pattern generator controlled DOUT is set by setting
DOUT_MODE = 1. Then, the start delay is programmed in the
DOUT_START_DLY register and the stop delay is programmed
into the DOUT_STOP field of the DOUT_CONFIG register.
DACx input samples are summed with a 12-bit dc offset
value as well. The dc offset values are programmed in the
DACxDOF registers.
DACx Waveform Selectors
Waveform selector inputs are
DOUT goes high DOUT_START[15:0] CLKP/CLKN cycles
after the falling edge of the signal input to the trigger terminal.
DOUT stays high as long as a pattern is being generated. DOUT
goes low DOUT_STOP[3:0] CLKP/CLKN cycles after the clock
edge that causes pattern generation to stop.
•
•
•
•
•
•
DACx sawtooth generator output
DACx pseudo random sequence generator output
DACx dc constant generator output
DACx pulsed, phase shifted DDS sine wave output
RAM output
DACx pulsed, phase shifted DDS sine wave output
amplitude modulated by ram output
DOUT DELAY=
DOUT_START[15:0] CLKP/CLKN CYCLES
tSU
Waveform selection for each DACx is made by programming
the WAVEx_yCONFIG registers.
TRIGGER
DACx Pattern Period Repeat Controller
CLKP/
CLKN
The PATTERN_RPT bit in the PAT_TYPE register controls
whether the pattern output auto repeats (periodic pulse train
repeats indefinitely) or repeats a number of consecutive times
defined by the DACx_REPEAT_CYCLE fields. The latter are
periodic pulse trains that repeat a finite number of times.
DOUT
Figure 46. DOUT Start Sequence
PATTERN
STOPS
DACx, Number of DDS Cycles
Each DACx input data path establishes the pulse width of the
sine wave output from the single common DDS in number
of sine wave cycles. The cycle counts are programmed in
DDS_CYCx registers.
PATTERN
GENERATOR
STATE
PATTERN ON
PATTERN OFF
CLKP/CLKN
DACx DDS Phase Shift
DOUT DELAY = DOUT_STOP[3:0]
CLKP/CLKN CYCLES
Each DACx input data path shifts the phase of the output of the
single common DDS. The phase shift is programmed using the
DDSx_PHASE fields.
DOUT
Figure 47. DOUT Stop Sequence
DIRECT DIGITAL SYNTHESIZER (DDS)
DOUT FUNCTION
The direct digital synthesizer generates a sine wave that can be
output on any of the four DACx. The DDS is a global shared
signal resource. It can generate one sinusoid at a frequency
determined by its tuning word input. The tuning word is 24 bits
wide. The resolution of DDS tuning is FCLKP/CLKN/224. The DDS
output frequency is DDS_TW × FCLKP/CLKN/224.
In applications where AD9106 DACs drive high voltage
amplifiers, such as in ultrasound transducer array element
driver signal chains, it can be useful to turn on and off each
amplifier at precise times relative to the waveform generated by
each AD9106 DAC. The SDO/SDI2/DOUT terminal, can be
configured to provide this function. One amplifier on/off strobe
can be provided for all four DACs.
The DDS tuning word is programmed using one of two
methods. For a fixed frequency, DDSTW_MSB and
DDSTW_LSB are programmed with a constant. When the
frequency of the DDS needs to change within each pattern
period, a sequence of values stored in SRAM is combined with
a selection of DDSTW_MSB bits to form the tuning word.
The SPI interface needs to be configured in 3-wire mode (see
Figure 32 and Figure 33). This is accomplished by setting the
SPI3WIRE or SPI3WIREM bits in the SPICONFIG register.
When SPID_RV or SPI_DRVM of the SPICONFIG register is
set to Logic 1, the SDO/SDI2/DOUT terminal provides the
DOUT function.
Rev. A | Page 26 of 48
Data Sheet
AD9106
SRAM
POSITIVE
SAWTOOTH
The AD9106 4K × 12 SRAM can contain signal samples,
amplitude modulation patterns, lists of DDS tuning words, or
lists of DDS output phase offset words. Data is written to and
read from the memory via the SPI port as long as the SRAM is
not actively engaged in pattern generation (RUN = 0). To write
to SRAM, set up the PAT_STATUS register as follows:
NEGATIVE
SAWTOOTH
TRIANGLE
WAVE
•
•
•
BUF_READ = 0
MEM_ACCESS = 1
RUN = 0
Figure 48. Sawtooth Patterns
PSEUDO-RANDOM SIGNAL GENERATOR
To read data from SRAM, set up the PAT_STATUS as follows:
The pseudo-random noise generator generates a noise signal on
each DACx output if “Pseudo-Random Sequence” is selected in
any of the PRESTORE_SELx fields in the WAV4_3CONFIG or
WAV2_1 CONFIG registers. The pseudo-random noise signals
are generated as continuous waveforms only.
•
•
•
BUF_READ = 1
MEM_ACCESS = 1
RUN = 0
The SPI port address space for SRAM is location 0x6000
through 0x6FFF.
DC CONSTANT
A programmable dc current between 0.0 and IOUTFSx can be
generated on each DACx if the “Constant Value” in selected in
any of the PRESTORE_SELx fields of the WAV4_3CONFIG
or WAV2_1 CONFIG registers. DC constant currents are
generated as continuous waveforms only. The dc current level is
programmed by writing to the DACx_CONST field in the
appropriate DACx_CST register.
SRAM can be accessed using any of the SPI operating modes
shown in Figure 32 through Figure 35. Using the SPI modes of
operation shown in Figure 33 and Figure 34, the entire SRAM
can be written in (2 + 2 × 4096) × 8/FSCLK seconds. The SRAM is
a shared signal generation resource. Data from this one 4K × 12
memory can be used to generate signals for all four DAC.
When the PAT_STATUS register RUN bit = 1 (pattern
generation enabled), each DACx data path has its own
SRAM address counter. Each address counter has its own
START_ADDRx and STOP_ADDRx. During each pattern
period, data is read from RAM after the START_DELAYx
period and while the each address counter is incrementing.
SRAM is read simultaneously by all four DACx data paths.
POWER SUPPLY NOTES
The AD9106 supply rails are specified in Table 9. The AD9106
includes three on-chip linear regulators. The supply rails driven
by these regulators are run at 1.8 V. Two usage rules for these
regulators follow.
•
When CLKVDD is 2.5 V or higher, the 1.8 V on-chip
CLDO regulator may be used. If CLKVDD = 1.8 V, then
the CLDO regulator must be disabled by setting the
PDN_LDO_CLK bit in the POWERCONFIG register.
CLKVDD and CLDO are connected together.
Incrementing Pattern Generation Mode SRAM Address
Counters
Each of the SRAM address counters can be programmed to be
incremented by CLKP/CLKN (default) or by the rising edge of
the DDSx MSB. DDSx[11:0] are the DDS output samples for a
given DACx. The DDS_MSB_ENx bits in the DDSx_CONFIG
register make this selection.
•
When DVDD is 2.5 V or higher, the 1.8 V on-chip DLDO1
and DLDO2 regulators may be used. If DVVD is 1.8 V, t h e
DLDO1 and DLDO2 regulators must be disabled by setting
the PDN_LDO_DIG1 and PDN_LDO_DIG2 bits in the
POWERCONFIG register. DVDD, DLDO1, and DLDO2
are connected together.
As an example, DDSx MSB could be used to clock the address
counter when generating a chirp waveform from the DDS using
a list of tuning words in SRAM. Each frequency setting dwells
for one DDS output sinewave cycle.
POWER-DOWN CAPABILITIES
SAWTOOTH GENERATOR
The POWERCONFIG register allows the user to place the
AD9106 in a reduced power dissipation configuration while the
CLKP/CLKN input is running and the power supplies are on.
DAC1, DAC2, DAC3, and DAC4 can all be put to sleep by setting
the DACx_SLEEP bits in the POWERCONFIG register.
There is a separate sawtooth signal generator for each DACx.
When the sawtooth is selected in any of the PRESTORE_SELx
fields in the WAV4_3CONFIG or WAV2_1 CONFIG registers,
the appropriate sawtooth generator is connected to the desired
DACx digital data path.
Clocking of the waveform generator and the DACs can be turned
off by setting the CLK_PDN bit in the CLOCKCONFIG register.
Taking these actions places the AD9106 in the power-down mode
specified in Table 8.
Sawtooth types, shown in Figure 48, are selected using the
SAW_TYPEx fields in the SAWx_yCONFIG registers. The
number of samples per sawtooth waveform step is programmed
in each SAW_STEPx field.
Rev. A | Page 27 of 48
AD9106
Data Sheet
APPLICATIONS INFORMATION
SIGNAL GENERATION EXAMPLES
PATTERN_PERIOD
START_DLY1 #CYCLES1
AD9106 waveform and pattern generation examples are
provided in this section.
DAC1
Figure 49 shows a different waveform being generated by each
DACx. The waveforms are all stored in the 4K × 12 SRAM in
different segments. DACx path address counters access the
SRAM simultaneously. Each waveform is repeated once during
each pattern period. In each pattern period a start delay is
executed, then the pattern is read from SRAM.
START_DLY2 #CYCLES2
DAC2
#CYCLES3
START_DLY3
TRIGGER
PATTERN
PATTERN
EXECUTED
PATTERN
EXECUTED
DAC3
DAC4
EXECUTED
#CYCLES4
START_DLY4
PATTERN_PERIOD
START_DLY1
DAC1
DATA @
STOP_ADDR1
DATA @
START_ADDR1
Figure 50. Pulsed Sine Waves in Pattern Periods
START_DLY2
DAC2
Figure 51 shows a pulsed sinewave generated by DAC1 and each
of the three available sawtooth wave shapes generated by DAC2,
DAC3, and DAC4 in successive pattern periods with start delay.
PATTERN_PERIOD
DATA @
STOP_ADDR2
DATA @
START_ADDR2
START_DLY3
DAC3
START_DLY1 #CYCLES1
DATA @
STOP_ADDR3
DATA @
START_ADDR3
DAC1
START_DLY4
DAC4
START_DLY2
DATA @
STOP_ADDR4
DATA @
START_ADDR4
Figure 49. Pattern Using Different Waveforms Stored in SRAM
DAC2
Figure 50 shows pulsed sine waves generated by each DACx.
The DDS generates a sine wave at a programmed frequency.
Each DACx channel is programmed with a start delay and a
number of sine wave cycles to output.
START_DLY3
DAC3
START_DLY4
DAC4
Figure 51. Pulsed SineWaves and Sawtooth Waveforms in Pattern Periods
Rev. A | Page 28 of 48
Data Sheet
AD9106
START_DLY1
Figure 52 shows all DACx outputting sine waves modulated by
an amplitude envelope. The sine wave is generated by the DDS
and the amplitude envelope is stored in SRAM. Different start
delays and digital gain multipliers are applied by each DACx
input data path.
DAC1
DAC2
DAC3
START_DLY2
PATTERN_PERIOD
START_DLY1
START_DLY3
DAC1
DATA @
START_ADDR1
DATA @
STOP_ADDR1
START_DLY2
DAC2
START_DLY4
DATA @
START_ADDR2
START_DLY3
DATA @
STOP_ADDR2
DAC4
Figure 53. Waveforms with Start Delays
DAC3
DATA @
START_ADDR3
DATA @
STOP_ADDR3
DAC1
DAC2
DAC3
START_DLY4
DAC4
DATA @
START_ADDR4
DATA @
STOP_ADDR4
Figure 52. DDS Output Amplitude Modulated by RAM Envelope
Figure 53 and Figure 54 show the four DACs generating
continuous waveforms. One with start delays, one without.
DAC4
Figure 54. Waveforms Without Start Delays
Rev. A | Page 29 of 48
AD9106
Data Sheet
REGISTER MAP
Table 14. Register Summary
Addr Register
(Hex) Name
W
R
Bits Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
LSBFIRST
SPI3WIRE
RESET
DOUBLESPI
SPI_DRV
DOUT_EN
RESERVED[3:2]
±x±± SPICONFIG
[15:8]
[7:±]
±x±±
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RESERVED[1:±]
DOUT_ENM
SPI_DRVM
REF_EXT
EPS
DOUBLESPIM
RESETM
SPI3WIREM
LSBFIRSTM
RESERVED
CLK_LDO_STAT
DAC1_SLEEP
DIG1_LDO_STAT
DAC2_SLEEP
DIG2_LDO_STAT PDN_LDO_CLK
±x±1 POWERCONFIG [15:8]
[7:±]
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
PDN_LDO_DIG1 PDN_LDO_DIG2 REF_PDN
RESERVED[15:12]
DAC3_SLEEP
DAC4_SLEEP
DIS_CLK1
DIS_CLK2
DIS_CLK3
DIS_CLK4
±x±2 CLOCKCONFIG [15:8]
[7:±]
DIS_DCLK
CLK_SLEEP
CLK_PDN
DAC1_INV_CLK
DAC2_INV_CLK
DAC3_INV_CLK
DAC4_INV_CLK
RESERVED[9:2]
±x±3 REFADJ
[15:8]
[7:±]
RESERVED[1:±]
BGDR
RESERVED
RESERVED
DAC4_GAIN_CAL
DAC4_GAIN
±x±4 DAC4AGAIN
±x±5 DAC3AGAIN
±x±6 DAC2AGAIN
±x±7 DAC1AGAIN
±x±8 DACxRANGE
±x±9 DAC4RSET
±x±A DAC3RSET
±x±B DAC2RSET
±x±C DAC1RSET
±x±D CALCONFIG
[15:8]
[7:±]
RESERVED
RESERVED
DAC3_GAIN_CAL
DAC3_GAIN
[15:8]
[7:±]
RESERVED
RESERVED
DAC2_GAIN_CAL
DAC2_GAIN
[15:8]
[7:±]
RESERVED
RESERVED
DAC1_GAIN_CAL
DAC1_GAIN
[15:8]
[7:±]
RESERVED
[15:8]
[7:±]
DAC4_GAIN_RNG
DAC4_RSET_EN
DAC3_GAIN_RNG
DAC2_GAIN_RNG
DAC1_GAIN_RNG
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DAC4_RSET_CAL
DAC4_RSET
[15:8]
[7:±]
±x
±±±A
DAC3_RSET_EN
DAC2_RSET_EN
DAC1_RSET_EN
RESERVED
DAC3_RSET_CAL
DAC3_RSET
[15:8]
[7:±]
±x
±±±A
DAC2_RSET_CAL
DAC2_RSET
[15:8]
[7:±]
±x
±±±A
DAC1_RSET_CAL
DAC1_RSET
[15:8]
[7:±]
±x
±±±A
COMP_OFFSET
_OF
COMP_OFFSET
_UF
RSET_CAL_OF
RSET_CAL_UF
GAIN_CAL_OF
GAIN_CAL_UF
CAL_CLK_DIV
CAL_RESET
[15:8]
[7:±]
±x±±
CAL_MODE
RESERVED
CAL_MODE_EN
COMP_CAL_RNG
CAL_CLK_EN
COMP_OFFSET_CAL
±x±E COMPOFFSET
±x1D RAMUPDATE
±x1E PAT_STATUS
±x1F PAT_TYPE
[15:8]
[7:±]
±x±±
±x±±
±x±±
±x±±
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
RESERVED
CAL_FIN
START_CAL
RAMUPDATE
RUN
RESERVED[14:7]
RESERVED[6:±]
RESERVED[12:5]
BUF_READ
RESERVED[14:7]
RESERVED[6:±]
[15:8]
[7:±]
[15:8]
[7:±]
RESERVED[3:±]
MEM_ACCESS
PATTERN
[15:8]
[7:±]
PATTERN_RPT
PATTERN_DELAY[15:8]
PATTERN_DELAY[7:±]
±x2± PATTERN_DLY [15:8]
[7:±]
±x
±±±E
DAC4_DIG_OFFSET[11:4]
DAC3_DIG_OFFSET[11:4]
DAC2_DIG_OFFSET[11:4]
DAC1_DIG_OFFSET[11:4]
±x22 DAC4DOF
±x23 DAC3DOF
±x24 DAC2DOF
±x25 DAC1DOF
[15:8]
[7:±]
±x±±
±x±±
±x±±
±x±±
±±±±
±x±±
DAC4_DIG_OFFSET[3:±]
DAC3_DIG_OFFSET[3:±]
DAC2_DIG_OFFSET[3:±]
DAC1_DIG_OFFSET[3:±]
RESERVED
[15:8]
[7:±]
RESERVED
RESERVED
RESERVED
[15:8]
[7:±]
[15:8]
[7:±]
RESERVED
PRESTORE_SEL4
PRESTORE_SEL3
RESERVED
RESERVED
WAVE_SEL4
±x26 WAV4_3CONFIG [15:8]
[7:±]
RESERVED
WAVE_SEL3
RESERVED
RESERVED
PRESTORE_SEL2
PRESTORE_SEL1
MASK_DAC4
MASK_DAC3
CH2_ADD
CH1_ADD
WAVE_SEL2
WAVE_SEL1
±x27 WAV2_1CONFIG [15:8]
[7:±]
Rev. A | Page 3± of 48
Data Sheet
AD9106
Addr Register
(Hex) Name
W
R
Bits Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
RESERVED
HOLD
±x28 PAT_TIMEBASE [15:8]
[7:±]
±x±111
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
PAT_PERIOD_BASE
START_DELAY_BASE
PATTERN_PERIOD[15:8]
PATTERN_PERIOD[7:±]
±x29 PAT_PERIOD
±x2A DAC4_3PATx
±x2B DAC2_1PATx
[15:8]
[7:±]
±x8±±±
±x±1±1
±x±1±1
±x±±±3
±x±±
DAC4_REPEAT_CYCLE
DAC3_REPEAT_CYCLE
[15:8]
[7:±]
DAC2_REPEAT_CYCLE
DAC1_REPEAT_CYCLE
[15:8]
[7:±]
DOUT_START[15:8]
DOUT_START[7:±]
±x2C DOUT_START
_DLY
[15:8]
[7:±]
RESERVED[9:2]
±x2D DOUT_CONFIG [15:8]
[7:±]
RESERVED[1:±]
DOUT_VAL
DOUT_MODE
DOUT_STOP
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
DAC4_CONST[11:4]
DAC3_CONST[11:4]
DAC2_CONST[11:4]
DAC1_CONST[11:4]
DAC4_DIG_GAIN[11:4]
DAC3_DIG_GAIN[11:4]
DAC2_DIG_GAIN[11:4]
DAC1_DIG_GAIN[11:4]
±x2E DAC4_CST
±x2F DAC3_CST
±x3± DAC2_CST
±x31 DAC1_CST
±x32 DAC4_DGAIN
±x33 DAC3_DGAIN
±x34 DAC2_DGAIN
±x35 DAC1_DGAIN
[15:8]
[7:±]
±x±±
DAC4_CONST[3:±]
DAC3_CONST[3:±]
DAC2_CONST[3:±]
DAC1_CONST[3:±]
DAC4_DIG_GAIN[3:±]
DAC3_DIG_GAIN[3:±]
DAC2_DIG_GAIN[3:±]
DAC1_DIG_GAIN[3:±]
[15:8]
[7:±]
±x±±
[15:8]
[7:±]
±x±±
[15:8]
[7:±]
±x±±
[15:8]
[7:±]
±x±±
[15:8]
[7:±]
±x±±
[15:8]
[7:±]
±x±±
[15:8]
[7:±]
±x±±
SAW_STEP4
SAW_STEP3
SAW_TYPE4
SAW_TYPE3
±x36 SAW4_3CONFIG [15:8]
[7:±]
±x±±
SAW_STEP2
SAW_STEP1
SAW_TYPE2
SAW_TYPE1
±x37 SAW2_1CONFIG [15:8]
[7:±]
±x±±
RESERVED
±x38 RESERVED
to
±x3D
DDSTW_MSB[15:8]
DDSTW_MSB[7:±]
±x3E DDS_TW32
±x3F DDS_TW1
±x4± DDS4_PW
±x41 DDS3_PW
±x42 DDS2_PW
±x43 DDS1_PW
±x44 TRIG_TW_SEL
[15:8]
[7:±]
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
DDSTW_LSB
RESERVED
[15:8]
[7:±]
DDS4_PHASE[15:8]
DDS4_PHASE[7:±]
[15:8]
[7:±]
DDS3_PHASE[15:8]
DDS3_PHASE[7:±]
[15:8]
[7:±]
DDS2_PHASE[15:8]
DDS2_PHASE[7:±]
[15:8]
[7:±]
DDS1_PHASE[15:8]
DDS1_PHASE[7:±]
[15:8]
[7:±]
RESERVED[13:6]
[15:8]
[7:±]
RESERVED[5:±]
TRIG_DELAY_EN RESERVED
RESERVED
DDS_COS_EN4 DDS_MSB_EN4
DDS_COS_EN2 DDS_MSB_EN2
RESERVED
RESERVED
DDS_COS_EN3
DDS_COS_EN1
DDS_MSB_EN3
DDS_MSB_EN1
±x45 DDSx_CONFIG [15:8]
[7:±]
RESERVED
RESERVED
TW_MEM_SHIFT
TW_MEM_EN
RESERVED
RESERVED
±x47 TW_RAM
_CONFIG
[15:8]
[7:±]
Rev. A | Page 31 of 48
AD9106
Data Sheet
Addr Register
(Hex) Name
W
R
Bits Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
START_DELAY4[15:8]
±x5± START_DLY4
[15:8]
±x±±
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
START_DELAY4[7:±]
START_ADDR4[11:4]
[7:±]
±x51 START_ADDR4 [15:8]
[7:±]
±x±±
START_ADDR4[3:±]
STOP_ADDR4[3:±]
RESERVED
STOP_ADDR4[11:4]
±x52 STOP_ADDR4
±x53 DDS_CYC4
±x54 START_DLY3
[15:8]
[7:±]
±x±±
RESERVED
DDS_CYC4[15:8]
DDS_CYC4[7:±]
[15:8]
[7:±]
±x±±±1
±x±±
START_DELAY3[15:8]
START_DELAY3[7:±]
[15:8]
[7:±]
START_ADDR3[11:4]
±x55 START_ADDR3 [15:8]
[7:±]
±x±±
START_ADDR3[3:±]
STOP_ADDR3[3:±]
RESERVED
RESERVED
STOP_ADDR3[11:4]
±x56 STOP_ADDR3
±x57 DDS_CYC3
±±58 START_DLY2
[15:8]
[7:±]
±x±±
DDS_CYC3[15:8]
DDS_CYC3[7:±]
[15:8]
[7:±]
±x±±±1
±x±±
START_DELAY2[15:8]
START_DELAY2[7:±]
[15:8]
[7:±]
START_ADDR2[11:4]
±x59 START_ADDR2 [15:8]
[7:±]
±x±±
START_ADDR2[3:±]
STOP_ADDR2[3:±]
RESERVED
RESERVED
STOP_ADDR2[11:4]
±x5A STOP_ADDR2
±x5B DDS_CYC2
±x5C START_DLY1
[15:8]
[7:±]
±x±±
DDS_CYC2[15:8]
DDS_CYC2[7:±]
[15:8]
[7:±]
±x±±±1
±x±±
START_DELAY1[15:8]
START_DELAY1[7:±]
[15:8]
[7:±]
START_ADDR1[11:4]
±x5D START_ADDR1 [15:8]
[7:±]
±x±±
START_ADDR1[3:±]
STOP_ADDR1[3:±]
RESERVED
RESERVED
STOP_ADDR1[11:4]
±x5E STOP_ADDR1
±±5F DDS_CYC1
±±6± CFG_ERROR
[15:8]
[7:±]
±x±±
DDS_CYC1[15:8]
DDS_CYC1[7:±]
[15:8]
[7:±]
±x±±±1
±x±±
ERROR_CLEAR
CFG_ERROR[1:±]
CFG_ERROR[8:2]
DOUT_START_LG PAT_DLY_SHORT DOUT_START
[15:8]
[7:±]
PERIOD
_SHORT_ERR
ODD_ADDR
_ERR
MEM_READ
_ERR
_ERR
_ERR
_SHORT_ERR
RESERVED
SRAM_DATA[11:8]
N/A
±x6±±± SRAM_DATA
to
±x6FFF
[15:8]
[7:±]
W
R
SRAM_DATA[7:±]
Rev. A | Page 32 of 48
Data Sheet
AD9106
REGISTER DESCRIPTIONS
SPI Control Register (SPICONFIG, Address 0x00)
Table 15. Bit Descriptions for SPICONFIG
Bits
Bit Field Name
Settings
Description
Reset
Access
15
LSBFIRST
LSB first selection.
±
±
±
RW
±
1
MSB first per SPI standard (default).
LSB first per SPI standard.
Selects if SPI is using 3-wire or 4-wire interface.
4-wire SPI.
14
13
SPI3WIRE
RESET
RW
RW
±
1
3-wire SPI.
Executes software reset of SPI and controllers, reloads default register
values, except for Register ±x±±.
±
1
Normal status.
Resets whole register map, except for Register ±x±±.
Double SPI data line.
12
DOUBLESPI
±
RW
±
1
The SPI port has only 1 data line and can be used as a 3-wire or 4-wire
interface.
The SPI port has 2 data lines: both bidirectional defining a pseudo dual
3-wire interface where CS and SCLK are shared between the two ports.
This mode is only available for RAM data read or write.
11
1±
SPI_DRV
Double-drive ability for SPI output.
Single SPI output drive ability.
Two-time drive ability on SPI output.
±
±
RW
RW
±
1
DOUT_EN
RESERVED
Enables DOUT signal on SDO/SDI2/DOUT pin.
SDO/SDI2 function input/output.
DOUT function output.
±
1
[9:6]
RW
RW
RW
RW
RW
5
4
3
2
DOUT_ENM1
F
Enable DOUT signal on SDO/SDI2/DOUT pin.
Double-drive ability for SPI output.
Double SPI data line.
SPI_DRVM1
DOUBLESPIM1
RESETM1
±
±
±
Executes software reset of SPI and controllers, reloads default register
values, except for Register ±x±±.
1
±
SPI3WIREM1
LSBFIRSTM1
Selects if SPI is using 3-wire or 4-wire interface.
LSB first selection.
±
±
RW
RW
1 SPICONFIG[1±:15] should always be set to the mirror of SPICONFIG[5:±] to allow easy recovery of the SPI operation when the LSBFIRST bit is set incorrectly. Bit[15] =
Bit[±], Bit[14] = Bit[1], Bit[13] = Bit[2], Bit[12] = Bit[3], Bit[11] = Bit[4] and Bit[1±] = Bit[5].
Rev. A | Page 33 of 48
AD9106
Data Sheet
Power Status Register (POWERCONFIG, Address 0x01)
Table 16. Bit Descriptions for POWERCONFIG
Bits
Bit Field Name
Settings
Description
Reset
Access
RW
R
[15:12] RESERVED
±x±±
11
1±
9
CLK_LDO_STAT
Read-only flag indicating CLKVDD_1P8 LDO is on.
Read-only flag indicating DVDD1 LDO is on.
±
±
±
±
±
±
±
DIG1_LDO_STAT
DIG2_LDO_STAT
PDN_LDO_CLK
PDN_LDO_DIG1
PDN_LDO_DIG2
REF_PDN
R
Read-only flag indicating DVDD2 LDO is on.
R
8
Disables the CLKVDD_1P8 LDO. An external supply is required.
Disables the DVDD1 LDO. An external supply is required.
Disables the DVDD2 LDO. An external supply is required.
RW
RW
RW
RW
7
6
5
Disables 1± kΩ resistor that creates REFIO voltage. User can drive with
external voltage or provide external BG resistor.
4
3
2
1
±
REF_EXT
Power down main BG reference including DAC bias.
Disables DAC1 output current.
±
±
±
±
±
RW
RW
RW
RW
RW
DAC1_SLEEP
DAC2_SLEEP
DAC3_SLEEP
DAC4_SLEEP
Disables DAC2 output current.
Disables DAC3 output current.
Disables DAC4 output current.
Clock Control Register (CLOCKCONFIG, Address 0x02)
Table 17. Bit Descriptions for CLOCKCONFIG
Bits
Bit Field Name
Settings
Description
Reset
Access
RW
[15:12] RESERVED
±x±±±
11
1±
9
DIS_CLK1
DIS_CLK2
DIS_CLK3
DIS_CLK4
DIS_DCLK
CLK_SLEEP
CLK_PDN
Disables the analog clock to DAC1 out of the clock distribution block.
Disables the analog clock to DAC2 out of the clock distribution block.
Disables the analog clock to DAC3 out of the clock distribution block.
Disables the analog clock to DAC4 out of the clock distribution block.
Disables the clock to core digital block.
±
±
±
±
±
±
±
RW
RW
RW
8
RW
7
RW
6
Enables a very low power clock mode.
RW
5
Disables and powers down main clock receiver. No clocks will be active in
the part.
RW
4
EPS
Enables Power Save (EPS) enables a low power option for the clock
receiver, but maintains low jitter performance on DAC clock rising edge.
The DAC clock falling edge is substantially degraded.
±
RW
3
2
1
±
DAC1_INV_CLK
DAC2_INV_CLK
DAC3_INV_CLK
DAC4_INV_CLK
Cannot use EPS while using this bit. Inverts the clock inside DAC Core 1
allowing 18±° phase shift in DAC1 update timing.
±
±
±
±
RW
RW
RW
RW
Cannot use EPS while using this bit. Inverts the clock inside DAC Core 2
allowing 18±° phase shift in DAC2 update timing.
Cannot use EPS while using this bit. Inverts the clock inside DAC Core 3
allowing 18±° phase shift in DAC3 update timing.
Cannot use EPS while using this bit. Inverts the clock inside DAC Core 4
allowing 18±° phase shift in DAC4 update timing.
Reference Resistor Register (REFADJ, Address 0x03)
Table 18. Bit Descriptions for REFADJ
Bits
Bit Field Name
RESERVED
BGDR
Settings
Description
Reset
Access
RW
[15:6]
[5:±]
±x±±±
±x±±
Adjusts the BG 1± kΩ resistor (nominal) to 8 kΩ to 12 kΩ, changes BG
voltage from 8±± mV to 1.2 V, respectively.
RW
Rev. A | Page 34 of 48
Data Sheet
AD9106
DAC4 Analog Gain Register (DAC4AGAIN, Address 0x04)
Table 19. Bit Descriptions for DAC4AGAIN
Bits
Bit Field Name
Settings
Description
Reset
±
Access
RW
R
15
RESERVED
[14:8]
7
DAC4_GAIN_CAL
RESERVED
DAC4 analog gain calibration output—read only.
±x±±
±
RW
RW
[6:±]
DAC4_GAIN
DAC4 analog gain control while not in calibration mode—twos
complement.
±x±±
DAC3 Analog Gain Register (DAC3AGAIN, Address 0x05)
Table 20. Bit Descriptions for DAC3AGAIN
Bits
Bit Field Name
Settings
Description
Reset
±
Access
RW
R
15
RESERVED
[14:8]
7
DAC3_GAIN_CAL
RESERVED
DAC3 analog gain calibration output—read only.
±x±±
±
RW
RW
[6:±]
DAC3_GAIN
DAC3 analog gain control while not in calibration mode—twos
complement.
±x±±
DAC2 Analog Gain Register (DAC2AGAIN, Address 0x06)
Table 21. Bit Descriptions for DAC2AGAIN
Bits
Bit Field Name
Settings
Description
Reset
±
Access
RW
R
15
RESERVED
[14:8]
7
DAC2_GAIN_CAL
RESERVED
DAC2 analog gain calibration output—read only.
±x±±
±
RW
RW
[6:±]
DAC2_GAIN
DAC2 analog gain control while not in calibration mode—twos
complement.
±x±±
DAC1 Analog Gain Register (DAC1AGAIN, Address 0x07)
Table 22. Bit Descriptions for DAC1AGAIN
Bits
Bit Field Name
Settings
Description
Reset
±
Access
RW
R
15
RESERVED
[14:8]
7
DAC1_GAIN_CAL
RESERVED
DAC1 analog gain calibration output—read only.
±x±±
±
RW
RW
[6:±]
DAC1_GAIN
DAC1 analog gain control while not in calibration mode—twos
complement.
±x±±
DAC Analog Gain Range Register (DACxRANGE, Address 0x08)
Table 23. Bit Descriptions for DACxRANGE
Bits
Bit Field Name
Settings
Description
Reset
±x±±
±x±
Access
RW
[15:8]
[7:6]
[5:4]
[3:2]
[1:±]
RESERVED
DAC4_GAIN_RNG
DAC3_GAIN_RNG
DAC2_GAIN_RNG
DAC1_GAIN_RNG
DAC4 gain range control.
DAC3 gain range control.
DAC2 gain range control.
DAC1 gain range control.
RW
±x±
RW
±x±
RW
±x±
RW
Rev. A | Page 35 of 48
AD9106
Data Sheet
FSADJ4 Register (DAC4RSET, Address 0x09)
Table 24. Bit Descriptions for DAC4RSET
Bits
Bit Field Name
Settings
Description
Reset
Access
15
DAC4_RSET_EN
For write, enable the internal RSET resistor for DAC4; for read, RSET for
DAC4 is enabled during calibration mode.
±x±±
RW
[14:13] RESERVED
±x±±
±x±±
±x±±
±x±A
RW
R
[12:8]
[7:5]
[4:±]
DAC4_RSET_CAL
Digital control value of RSET resistor for DAC4 after calibration—read only.
Digital control to set the value of RSET resistor in DAC4.
RESERVED
RW
RW
DAC4_RSET
FSADJ3 Register (DAC3RSET, Address 0x0A)
Table 25. Bit Descriptions for DAC3RSET
Bits
Bit Field Name
Settings
Description
Reset
Access
15
DAC3_RSET_EN
For write, enable the internal RSET resistor for DAC3; for read, RSET for
DAC3 is enabled during calibration mode.
±
RW
[14:13] RESERVED
±x±
RW
R
[12:8]
[7:5]
[4:±]
DAC3_RSET_CAL
Digital control value of RSET resistor for DAC3 after calibration—read only.
Digital control to set the value of RSET resistor in DAC3.
±x±±
±x±
RESERVED
RW
RW
DAC3_RSET
±x±A
FSADJ2 Register (DAC2RSET, Address 0x0B)
Table 26. Bit Descriptions for DAC2RSET
Bits
Bit Field Name
Settings
Description
Reset
Access
15
DAC2_RSET_EN
For write, enable the internal RSET resistor for DAC2; for read, RSET for
DAC2 is enabled during calibration mode.
±
RW
[14:13] RESERVED
±x±
RW
R
[12:8]
[7:5]
[4:±]
DAC2_RSET_CAL
Digital control value of RSET resistor for DAC2 after calibration—read only.
Digital control to set the value of RSET resistor in DAC2.
±x±±
±x±
RESERVED
RW
RW
DAC2_RSET
±xA
FSADJ1 Register (DAC1RSET, Address 0x0C)
Table 27. Bit Descriptions for DAC1RSET
Bits
Bit Field Name
Settings
Description
Reset
Access
15
DAC1_RSET_EN
For write, enable the internal RSET resistor for DAC1; for read, RSET for DAC1
is enabled during calibration mode.
±x±±
RW
[14:13] RESERVED
±x±±
±x±±
±x±
RW
R
[12:8]
[7:5]
[4:±]
DAC1_RSET_CAL
Digital control value of RSET resistor for DAC1 after calibration—read only.
Digital control to set the value of RSET resistor in DAC1.
RESERVED
RW
RW
DAC1_RSET
±x±A
Rev. A | Page 36 of 48
Data Sheet
AD9106
Calibration Register (CALCONFIG, Address 0x0D)
Table 28. Bit Descriptions for CALCONFIG
Bits
15
14
13
12
11
1±
9
Bit Field Name
Settings
Description
Reset
Access
RW
R
RESERVED
±
COMP_OFFSET_OF
COMP_OFFSET_UF
RSET_CAL_OF
RSET_CAL_UF
GAIN_CAL_OF
GAIN_CAL_UF
CAL_RESET
Compensation offset calibration value overflow.
Compensation offset calibration value underflow.
RSET calibration value overflow.
±
±
R
±
R
RSET calibration value underflow.
±
R
Gain calibration value overflow.
±
R
Gain calibration value underflow.
±
R
8
71
61
Pulse this bit high and low to reset the calibration results.
Read-only flag indicating calibration is being used.
Enables the gain calibration circuitry.
±
RW
R
CAL_MODE
±
CAL_MODE_EN
COMP_CAL_RNG
CAL_CLK_EN
±
RW
RW
RW
RW
[5:4]
3
Offset calibration range.
±x±
±
Enables the calibration clock to calibration circuitry.
Sets divider from DAC clock to calibration clock.
[2:±]
CAL_CLK_DIV
±x±
1 Change of location
Comp Offset Register (COMPOFFSET, Address 0x0E)
Table 29. Bit Descriptions for COMPOFFSET
Bits
Bit Field Name
Settings
Description
Reset
±x±±
±x±±
±x±±
±x±±
±x±±
Access
RW
R
15
RESERVED
[14:8]
[7:2]
1
COMP_OFFSET_CAL
RESERVED
The result of the offset calibration for the comparator.
RW
R
CAL_FIN
Read-only flag indicating calibration is completed.
Start a calibration cycle.
±
START_CAL
RW
Update Pattern Register (RAMUPDATE, Address 0x1D)
Table 30. Bit Descriptions for RAMUPDATE
Bits
[15:1]
±
Bit Name
Settings
Description
Reset
±x±±
±
Access
RW
RESERVED
RAMPUPDATE
Update all SPI setting with new configuration (self clearing).
RW
Command/Status Register (PAT_STATUS, Address 0x1E)
Table 31. Bit Descriptions for PAT_STATUS
Bits
Bit Field Name
RESERVED
BUF_READ
MEM_ACCESS
PAT TERN
Settings
Description
Reset
Access
RW
RW
RW
R
[15:4]
±x±±±
3
2
1
±
Read back from updated buffer.
±
±
±
±
Memory SPI access enable.
Status of pattern being played, read only.
Allows the pattern generation and stop pattern after trigger.
RUN
RW
Rev. A | Page 37 of 48
AD9106
Data Sheet
Command/Status Register (PAT_TYPE, Address 0x1F)
Table 32. Bit Descriptions for PAT_TYPE
Bits
[15:1]
±
Bit Field Name
Settings
Description
Reset
±x±±±±
±
Access
RW
RESERVED
PATTERN_RPT
Setting this bit allows the pattern to repeat the number of times
defined in DAC4_3PATx and DAC2_1PATx.
RW
±
1
Pattern continuously runs.
Pattern repeats the number of times defined in DAC4_3PATx and
DAC2_1PATx.
Trigger Start to Real Pattern Delay Register (PATTERN_DLY, Address 0x20)
Table 33. Bit Descriptions for PATTERN_DLY
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
PATTERN_DELAY
Time between trigger low and pattern start in number of DAC clock
cycles + 1.
±x±±±E RW
DAC4 Digital Offset Register (DAC4DOF, Address 0x22)
Table 34. Bit Descriptions for DAC4DOF
Bits
Bit Field Name
DAC4_DIG_OFFSET
RESERVED
Settings
Description
Reset
±x±±±
±x±±
Access
[15:4]
[3:±]
DAC4 digital offset.
RW
RW
DAC3 Digital Offset Register (DAC3DOF, Address 0x23)
Table 35. Bit Descriptions for DAC3DOF
Bits
Bit Field Name
DAC3_DIG_OFFSET
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
DAC3 digital offset.
RW
DAC2 Digital Offset Register (DAC2DOF, Address 0x24)
Table 36. Bit Descriptions for DAC2DOF
Bits
Bit Field Name
DAC2_DIG_OFFSET
RESERVED
Settings
Description
Reset
±x±±±
±x±±
Access
RW
[15:4]
[3:±]
DAC2 digital offset.
RW
DAC1 Digital Offset Register (DAC1DOF, Address 0x25)
Table 37. Bit Descriptions for DAC1DOF
Bits
Bit Field Name
DAC1_DIG_OFFSET
RESERVED
Settings
Description
Reset
±x±±±
±x±±
Access
RW
[15:4]
[3:±]
DAC1 digital offset.
RW
Rev. A | Page 38 of 48
Data Sheet
AD9106
Wave3/Wave4 Select Register (WAV4_3CONFIG, Address 0x26)
Table 38. Bit Descriptions for WAV4_3CONFIG
Bits
Bit Field Name
Settings
Description
Reset
Access
RW
[15:14] RESERVED
±x±±
±x±±
[13:12] PRESTORE_SEL4
RW
±
1
Constant value held into DAC4 constant value MSB/LSB register.
Sawtooth defined in DAC4 sawtooth configuration register
(SAW4_3CONFIG).
2
3
Pseudo-random sequence.
DDS4 output.
[11:1±] RESERVED
±x±±
±x1
RW
RW
[9:8]
WAVE_SEL4
±
1
2
3
Waveform read from RAM between START_ADDR4 and STOP_ADDR4.
Prestored waveform.
Prestored waveform using START_DELAY4 and PATTERN_PERIOD.
Prestored waveform modulated by waveform from RAM.
[7:6]
[5:4]
RESERVED
±x±±
±x±±
RW
RW
PRESTORE_SEL3
±
1
Constant value held into DAC3 constant value MSB/LSB register.
Sawtooth defined in DAC3 sawtooth configuration register
(SAW4_3CONFIG).
2
3
Pseudo-random sequence.
DDS3 output.
[3:2]
[1:±]
RESERVED
±x±±
±x1
RW
RW
WAVE_SEL3
±
1
2
3
Waveform read from RAM between START_ADDR3 and STOP_ADDR3.
Prestored waveform.
Prestored waveform using START_DELAY3 and PATTERN_PERIOD.
Prestored waveform modulated by waveform from RAM.
Wave1/Wave2 Select Register (WAV2_1CONFIG, Address 0x27)
Table 39. Bit Descriptions for WAV2_1CONFIG
Bits
Bit Field Name
Settings
Description
Reset
±x±
Access
RW
[15:14] RESERVED
[13:12] PRESTORE_SEL2
±x±
RW
±
1
Constant value held into DAC2 constant value MSB/LSB register.
Sawtooth defined in DAC2 sawtooth configuration register
(SAW2_1CONFIG).
2
3
Pseudo-random sequence.
DDS2 output.
11
1±
MASK_DAC4
CH2_ADD
Mask DAC4 to DAC4_CONST value.
±
±
RW
RW
Add DAC2 and DAC4, output at DAC2.
Normal operation for DAC2/DAC4.
Add DAC2 and DAC4, output from DAC2.
±
1
[9:8]
[7:6]
WAVE_SEL2
RESERVED
±x1
±x±
RW
RW
±
1
2
3
Waveform read from RAM between START_ADDR2 and STOP_ADDR2.
Prestored waveform.
Prestored waveform using START_DELAY2 and PATTERN_PERIOD.
Prestored waveform modulated by waveform from RAM.
Rev. A | Page 39 of 48
AD9106
Data Sheet
Bits
Bit Field Name
Settings
Description
Reset
Access
[5:4]
PRESTORE_SEL1
±x±
RW
±
1
Constant value held into DAC1 constant value MSB/LSB register.
Sawtooth defined in DAC1 sawtooth configuration register
(SAW2_1CONFIG).
2
3
Pseudo-random sequence.
DDS1 output.
3
2
MASK_DAC3
CH1_ADD
Mask DAC3 to DAC3_CONST value.
±
±
RW
RW
Add DAC1 and DAC3, output at DAC1.
Normal operation for DAC1/DAC3.
Add DAC1 and DAC3, and output at DAC1. In this start_delay case, DAC3
output remains unchanged.
±
1
[1:±]
WAVE_SEL1
±x1
RW
±
1
2
3
Waveform read from RAM between START_ADDR1 and STOP_ADDR1.
Prestored waveform.
Prestored waveform using START_DELAY1 and PATTERN_PERIOD.
Prestored waveform modulated by waveform from RAM.
DAC Time Control Register (PAT_TIMEBASE, Address 0x28)
Table 40. Bit Descriptions for PAT_TIMEBASE
Bits
Bit Field Name
Settings
Description
Reset
±x±±
±x1
Access
RW
[15:12] RESERVED
[11:8]
[7:4]
[3:±]
HOLD
Number of times the DAC value holds the sample (± = DAC holds for 1
sample).
RW
PAT_PERIOD_BASE
START_DELAY_BASE
Number of DAC clock period per PATTERN_PERIOD LSB
(± = PATTERN_PERIOD LSB = 1 DAC clock period).
±x1
±x1
RW
RW
Number of DAC clock period per START_DELAYx LSB
(± = START_DELAYx LSB = 1 DAC clock period).
Pattern Period Register (PAT_PERIOD, Address 0x029)
Table 41. Bit Descriptions for PAT_PERIOD
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
PATTERN_PERIOD
Pattern period register.
±x8±±± RW
DAC3/DAC4 Pattern Repeat Cycles Register (DAC4_3PATx, Address 0x2A)
Table 42. Bit Descriptions for DAC4_3PATx
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:8]
[7:±]
DAC4_REPEAT_CYCLE
DAC3_REPEAT_CYCLE
±x±1
±x±1
RW
RW
Number of DAC4 pattern repeat cycles + 1, (± repeat 1 pattern).
Number of DAC3 pattern repeat cycles + 1, (± repeat 1 pattern).
DAC1/DAC2 Pattern Repeat Cycles Register (DAC2_1PATx, Address 0x2B)
Table 43. Bit Descriptions for DAC2_1PATx
Bits
[15:8]
[7:±]
Bit Field Name
DAC2_REPEAT_CYCLE
DAC1_REPEAT_CYCLE
Settings
Description
Reset
±x±1
±x±1
Access
RW
Number of DAC2 pattern repeat cycles + 1, (± repeat 1 pattern).
Number of DAC1 pattern repeat cycles + 1, (± repeat 1 pattern).
RW
Rev. A | Page 4± of 48
Data Sheet
AD9106
Trigger Start to DOUT Signal Register (DOUT_START_DLY, Address 0x2C)
Table 44. Bit Descriptions for DOUT_START_DLY
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
DOUT_START
Time between trigger low and DOUT signal high in number of DAC
clock cycles.
±x±±±3 RW
DOUT CONFIG Register (DOUT_CONFIG, Address 0x2D)
Table 45. Bit Descriptions for DOUT_CONFIG
Bits
[15:6]
5
Bit Field Name
Settings
Description
Reset
Access
RESERVED
±x±±±± RW
DOUT_VAL
Manually sets DOUT signal value, only valid when DOUT_MODE = ±
(manual mode).
±
±
RW
RW
4
DOUT_MODE
DOUT_STOP
Sets different enable signal mode.
±x±
±x1
DOUT pin is output from SDO/SDI2/DOUT pin and is manually controlled
by Bit 5, DOUT_EN in Register ±x±± which must be set to use this feature.
DOUT pin is output from SDO/SDI2/DOUT. The pin is controlled by
DOUT_START and DOUT_STOP. DOUT_EN in Register ±x±± must be set to
use this feature.
[3:±]
Time between pattern end and DOUT signal low in number of DAC clock
cycles.
±x±
RW
DAC4 Constant Value Register (DAC4_CST, Address 0x2E)
Table 46. Bit Descriptions for DAC4_CST
Bits
Bit Field Name
DAC4_CONST
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
Most significant byte of DAC4 constant value.
RW
DAC3 Constant Value Register (DAC3_CST, Address 0x2F)
Table 47. Bit Descriptions for DAC3_CST
Bits
Bit Field Name
DAC3_CONST
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
Most significant byte of DAC3 constant value.
RW
DAC2 Constant Value Register (DAC2_CST, Address 0x30)
Table 48. Bit Descriptions for DAC2_CST
Bits
Bit Field Name
DAC2_CONST
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
Most significant byte of DAC2 constant value.
RW
DAC1 Constant Value Register (DAC1_CST, Address 0x31)
Table 49. Bit Descriptions for DAC1_CST
Bits
Bit Field Name
DAC1_CONST
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
Most significant byte of DAC1 constant value.
RW
Rev. A | Page 41 of 48
AD9106
Data Sheet
DAC4 Digital Gain Register (DAC4_DGAIN, Address 0x32)
Table 50. Bit Descriptions for DAC4_DGAIN
Bits
Bit Field Name
DAC4_DIG_GAIN
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
DAC4 digital gain range of +2 to −2.
RW
DAC3 Digital Gain Register (DAC3_DGAIN, Address 0x33)
Table 51. Bit Descriptions for DAC3_DGAIN
Bits
Bit Field Name
DAC3_DIG_GAIN
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
DAC3 digital gain. Range of +2 to −2.
RW
DAC2 Digital Gain Register (DAC2_DGAIN, Address 0x34)
Table 52. Bit Descriptions for DAC2_DGAIN
Bits
Bit Field Name
DAC2_DIG_GAIN
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
DAC2 digital gain. Range of +2 to −2.
RW
DAC1 Digital Gain Register (DAC1_DGAIN, Address 0x35)
Table 53. Bit Descriptions for DAC1_DGAIN
Bits
Bit Field Name
DAC1_DIG_GAIN
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
DAC1 digital gain. Range of +2 to −2.
RW
DAC3/4 Sawtooth Configuration Register (SAW4_3CONFIG, Address 0x36)
Table 54. Bit Descriptions for SAW4_3CONFIG
Bits
Bit Field Name
Settings
Description
Reset
±x±1
±x±
Access
RW
[15:1±] SAW_STEP4
Number of samples per step for DAC4.
[9:8]
SAW_TYPE4
The type of sawtooth (positive, negative, or triangle) for DAC4.
Ramp up saw wave.
Ramp down saw wave.
Triangle saw wave.
No wave, zero.
RW
±
1
2
3
[7:2]
[1:±]
SAW_STEP3
SAW_TYPE3
Number of samples per step for DAC3.
±x±1
±x±
RW
RW
The type of sawtooth (positive, negative, or triangle) for DAC3.
Ramp up saw wave.
Ramp down saw wave.
Triangle saw wave.
No wave, zero.
±
1
2
3
DAC1/2 Sawtooth Configuration Register (SAW2_1CONFIG, Address 0x37)
Table 55. Bit Descriptions for SAW2_1CONFIG
Bits
[15:1±] SAW_STEP2
[9:8] SAW_TYPE2
Bit Field Name
Settings
Description
Reset
±x±1
±x±
Access
RW
Number of samples per step for DAC2.
The type of sawtooth (positive, negative, or triangle) for DAC2.
Ramp up saw wave.
Ramp down saw wave.
Triangle saw wave.
No wave, zero.
RW
±
1
2
3
Rev. A | Page 42 of 48
Data Sheet
AD9106
Bits
[7:2]
[1:±]
Bit Field Name
Settings
Description
Reset
Access
RW
SAW_STEP1
SAW_TYPE1
Number of samples per step for DAC1.
±x±1
±x±
The type of sawtooth (positive, negative, or triangle) for DAC1.
Ramp up saw wave.
Ramp down saw wave.
Triangle saw wave.
No wave, zero.
RW
±
1
2
3
DDS Tuning Word MSB Register (DDS_TW32, Address 0x3E)
Table 56. Bit Descriptions for DDS_TW32
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
DDSTW_MSB
DDS tuning word MSB.
±x±±±± RW
DDS Tuning word LSB Register (DDS_TW1, Address 0x3F)
Table 57. Bit Descriptions for DDS_TW1
Bits
Bit Field Name
DDSTW_LSB
RESERVED
Settings
Description
Reset
Access
[15:8]
[7:±]
DDS tuning word LSB.
±x±±
±x±±
RW
RW
DDS4 Phase Offset Register (DDS4_PW, Address 0x40)
Table 58. Bit Descriptions for DDS4_PW
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
DDS4_PHASE
DDS4 phase offset.
±x±±±± RW
DDS3 Phase Offset Register (DDS3_PW, Address 0x41)
Table 59. Bit Descriptions for DDS3_PW
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
DDS3_PHASE
DDS3 phase offset.
±x±±±± RW
DDS2 Phase Offset Register (DDS2_PW, Address 0x42)
Table 60. Bit Descriptions for DDS2_PW
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
DDS2_PHASE
DDS2 phase offset.
±x±±±± RW
DDS1 Phase Offset Register (DDS1_PW, Address 0x43)
Table 61. Bit Descriptions for DDS1_PW
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
DDS1_PHASE
DDS1 phase offset.
±x±±±± RW
Rev. A | Page 43 of 48
AD9106
Data Sheet
Pattern Control 1 Register (TRIG_TW_SEL, Address 0x44)
Table 62. Bit Descriptions for TRIG_TW_SEL
Bits
[15:2]
1
Bit Field Name
Settings
Description
Reset
±x±±±±
±
Access
RW
RESERVED
TRIG_DELAY_EN
Enable start delay as trigger delay for all four channels.
Delay repeats for all patterns.
Delay is only at the start of first pattern.
RW
±
1
±
RESERVED
±
RW
Pattern Control 2 Register (DDSx_CONFIG, Address 0x45)
Table 63. Bit Descriptions for DDSx_CONFIG
Bits
Bit Field Name
DDS_COS_EN4
DDS_MSB_EN4
Settings
Description
Reset
Access
RW
15
Enable DDS4 cosine output of DDS instead of sine wave.
±
±
14
Enable the clock for the RAM address. Increment is coming from the
DDS4 MSB. Default is coming from DAC clock.
RW
13
12
11
1±
RESERVED
±
±
±
±
RW
RW
RW
RW
RESERVED
DDS_COS_EN3
DDS_MSB_EN3
Enable DDS3 cosine output of DDS instead of sine wave.
Enable the clock for the RAM address. Increment is coming from the
DDS3 MSB. Default is coming from DAC clock.
9
PHASE_MEM_EN3
Enable DDS3 phase offset input coming from RAM reading
START_ADDR3. Since phase word is 8 bits and RAM data is 14 bits, only
8 MSB of RAM are taken into account. Default is coming from SPI map,
DDS3_PHASE.
±
RW
8
7
6
RESERVED
±
±
±
RW
RW
RW
DDS_COS_EN2
DDS_MSB_EN2
Enable DDS2 cosine output of DDS instead of sine wave.
Enable the clock for the RAM address. Increment is coming from the
DDS2 MSB. Default is coming from DAC clock.
5
4
3
2
RESERVED
±
±
±
±
RW
RW
RW
RW
RESERVED
DDS_COS_EN1
DDS_MSB_EN1
Enable DDS1 cosine output of DDS instead of sine wave.
Enable the clock for the RAM address. Increment is coming from the
DDS1 MSB. Default is coming from DAC clock.
1
±
RESERVED
±
±
RW
RW
TW_MEM_EN
Enable DDS tuning word input coming from RAM reading using
START_ADDR1. Since tuning word is 24 bits and RAM data is 14 bits,
1± bits are set to ±s depending on the value of the TW_MEM_SHIFT bits in
the TW_RAM_CONFIG register. Default is coming from SPI map, DDSTW.
TW_RAM_CONFIG Register (TW_RAM_CONFIG, Address 0x47)
Table 64. Bit Descriptions for TW_RAM_CONFIG
Bits
Bit Field Name
Settings
Description
Reset
±x±±±
±x±±
Access
RW
[15:5]
[4:±]
RESERVED
TW_MEM_SHIFT
TW_MEM_EN1 must be set = 1 to use this bit field.
DDS1TW = {RAM[11:±],12'b±}
RW
±x±±
±x±1
±x±2
±x±3
±x±4
±x±5
±x±6
DDS1TW = {DDS1TW[23],RAM[11:±],11'b±}
DDS1TW = {DDS1TW[23:22],RAM[11:±],1±'b±}
DDS1TW = {DDS1TW[23:21],RAM[11:±],9'b±}
DDS1TW = {DDS1TW[23:2±],RAM[11:±],8'b±}
DDS1TW = {DDS1TW[23:19],RAM[11:±],7'b±}
DDS1TW = {DDS1TW[23:18],RAM[11:±],6'b±}
Rev. A | Page 44 of 48
Data Sheet
AD9106
Bits
Bit Field Name
Settings
±x±7
±x±8
±x±9
±x±A
±x±B
±x±C
±x±D
±x±E
±x±F
±x1±
x
Description
Reset
Access
DDS1TW = {DDS1TW[23:17],RAM[11:±],5'b±}
DDS1TW = {DDS1TW[23:16],RAM[11:±],3'b±}
DDS1TW = {DDS1TW[23:15],RAM[11:±],4'b±}
DDS1TW = {DDS1TW[23:14],RAM[11:±],2’b±}
DDS1TW = {DDS1TW[23:13],RAM[11:±],1’b±}
DDS1TW = {DDS1TW[23:12],RAM[11:±]}
DDS1TW = {DDS1TW[23:11],RAM[11:1]}
DDS1TW = {DDS1TW[23:1±],RAM[11:2]}
DDS1TW = {DDS1TW[23:9],RAM[11:3]}
DDS1TW = {DDS1TW[23:8],RAM[11:4]}
Reserved
Start Delay4 Register (START_DLY4, Address 0x50)
Table 65. Bit Descriptions for START_DLY4
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
START_DELAY4
Start delay of DAC4.
±x±±±±
RW
Start Address4 Register (START_ADDR4, Address 0x51)
Table 66. Bit Descriptions for START_ADDR4
Bits
Bit Field Name
START_ADDR4
RESERVED
Settings
Description
Reset
±x±±±
±x±±
Access
RW
[15:4]
[3:±]
RAM address where DAC4 starts to read waveform.
RW
Stop Address4 Register (STOP_ADDR4, Address 0x52)
Table 67. Bit Descriptions for STOP_ADDR4
Bits
Bit Field Name
STOP_ADDR4
RESERVED
Settings
Description
Reset
±x±±±
±x±±
Access
RW
[15:4]
[3:±]
RAM address where DAC4 stops to read waveform.
RW
DDS Cycle4 Register (DDS_CYC4, Address 0x53)
Table 68. Bit Descriptions for DDS_CYC4
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
DDS_CYC4
Number of sine wave cycles when DDS prestored waveform with
start and stop delays is selected for DAC4 output.
±x±±±1
RW
Start Delay3 Register (START_DLY3, Address 0x54)
Table 69. Bit Descriptions for START_DLY3
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
START_DELAY3
Start delay of DAC3.
±x±±±±
RW
Start Address3 Register (START_ADDR3, Address 0x55)
Table 70. Bit Descriptions for START_ADDR3
Bits
Bit Field Name
START_ADDR3
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
RAM address where DAC3 starts to read waveform.
RW
Rev. A | Page 45 of 48
AD9106
Data Sheet
Stop Address3 Register (STOP_ADDR3, Address 0x56)
Table 71. Bit Descriptions for STOP_ADDR3
Bits
Bit Field Name
STOP_ADDR3
RESERVED
Settings
Description
Reset
Access
[15:4]
[3:±]
RAM address where DAC3 stops to read waveform.
±x±±±±
±x±
RW
RW
DDS Cycles3 Register (DDS_CYC3, Address 0x57)
Table 72. Bit Descriptions for DDS_CYC3
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
DDS_CYC3
Number of sine wave cycles when DDS prestored waveform with start and ±x±±±1 RW
stop delays is selected for DAC3 output.
Start Delay2 Register (START_DLY2, Address 0x58)
Table 73. Bit Descriptions for START_DLY2
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
START_DELAY2
Start delay of DAC2.
±x±±±± RW
Start Address2 Register (START_ADDR2, Address 0x59)
Table 74. Bit Descriptions for START_ADDR2
Bits
Bit Field Name
START_ADDR2
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
[15:4]
[3:±]
RAM address where DAC2 starts to read waveform.
RW
RW
Stop Address2 Register (STOP_ADDR2, Address 0x5A)
Table 75. Bit Descriptions for STOP_ADDR2
Bits
Bit Field Name
STOP_ADDR2
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
RAM address where DAC2 stops to read waveform.
RW
DDS Cycle2 Register (DDS_CYC2, Address 0x5B)
Table 76. Bit Descriptions for DDS_CYC2
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
DDS_CYC2
Number of sine wave cycles when DDS prestored waveform with
start and stop delays is selected for DAC2 output.
±x±±±1
RW
Start Delay1 Register (START_DLY1, Address 0x5C)
Table 77. Bit Descriptions for START_DLY1
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
START_DELAY1
Start delay of DAC1.
±x±±±±
RW
Rev. A | Page 46 of 48
Data Sheet
AD9106
Start Address1 Register (START_ADDR1, Address 0x5D)
Table 78. Bit Descriptions for START_ADDR1
Bits
Bit Field Name
START_ADDR1
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
RAM address where DAC1 starts to read waveform.
RW
Stop Address1 Register (STOP_ADDR1, Address 0x5E)
Table 79. Bit Descriptions for STOP_ADDR1
Bits
Bit Field Name
STOP_ADDR1
RESERVED
Settings
Description
Reset
±x±±±
±x±
Access
RW
[15:4]
[3:±]
RAM address where DAC1 stops to read waveform.
RW
DDS Cycle1 Register (DDS_CYC1, Address 0x5F)
Table 80. Bit Descriptions for DDS_CYC1
Bits
Bit Field Name
Settings
Description
Reset
Access
[15:±]
DDS_CYC1
Number of sine wave cycles when DDS prestored waveform with
start and stop delays is selected for DAC1 output.
±x±±±1
RW
CFG Error Register (CFG_ERROR, Address 0x60)
Table 81. Bit Descriptions for CFG_ERROR
Bits
Bit Field Name
Settings
Description
Reset
±
Access
15
ERROR_CLEAR
Writing this bit clears all errors.
R
R
R
[14:6]
5
CFG_ERROR
±x±±
±
DOUT_START_LG_ERR
When DOUT_START is larger than pattern delay, this error
is toggled.
4
3
2
1
±
PAT_DLY_SHORT_ERR
DOUT_START_SHORT_ERR
PERIOD_SHORT_ERR
ODD_ADDR_ERR
When pattern delay value is smaller than default value,
this error is toggled.
±
±
±
±
±
R
R
R
R
R
When DOUT_START value is smaller than default value,
this error is toggled.
When period register setting value is smaller than pattern
play cycle, this error is toggled.
When memory pattern play is not even in length in trigger
delay mode, this error flag is toggled.
MEM_READ_ERR
When there is a memory read conflict, this error flag is
toggled.
Rev. A | Page 47 of 48
AD9106
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
32
24
1
0.50
BSC
*
3.75
EXPOSED
PAD
3.60 SQ
3.55
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 55. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
F
Temperature Range
Package Description
32-Lead LFCSP_WQ
32-Lead LFCSP_WQ
Evaluation Board
Package Option
AD91±6BCPZ
AD91±6BCPZRL7
AD91±6-EBZ
−4±°C to +85°C
−4±°C to +85°C
CP-32-12
CP-32-12
1 Z = RoHS Compliant Part.
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11121-0-2/13(A)
Rev. A | Page 48 of 48
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