AD9142A_技术文档

Dual, 16-Bit, 1600 MSPS, TxDAC+

Digital-to-Analog Converter

Data Sheet

AD9142A

FEATURES

GENERAL DESCRIPTION

Supports input data rate up to 575 MHz

Very small inherent latency variation: <2 DAC clock cycles

Proprietary low spurious and distortion design

6-carrier GSM ACLR = 79 dBc at 200 MHz IF

SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF

Flexible 16-bit LVDS interface

The AD9142A is a dual, 16-bit, high dynamic range digital-to-

analog converter (DAC) that provides a sample rate of 1600 MSPS,

permitting a multicarrier generation up to the Nyquist frequency.

The AD9142A TxDAC+® includes features optimized for direct

conversion transmit applications, including complex digital mod-

ulation, input signal power detection, and gain, phase, and offset

compensation. The DAC outputs are optimized to interface seam-

lessly with analog quadrature modulators, such as the ADL537x

F-MOD series and the ADRF670x series from Analog Devices,

Inc. A 3-wire serial port interface provides for the programming/

readback of many internal parameters. Full-scale output current

can be programmed over a range of 9 mA to 33 mA. The

Supports word and byte load

Data interface DLL

Sample error detection and parity

Multiple chip synchronization

Fixed latency and data generator latency compensation

Selectable 2×, 4×, 8× interpolation filter

Low power architecture

AD9142A is available in a 72-lead LFCSP.

f_S/4 power saving coarse mixer

Input signal power detection

PRODUCT HIGHLIGHTS

1. Wide signal bandwidth (BW) enables emerging wideband

and multiband wireless applications.

Emergency stop for downstream analog circuitry

protection

2. Advanced low spurious and distortion design techniques

provide high quality synthesis of wideband signals from

baseband to high intermediate frequencies.

3. Very small inherent latency variation simplifies both software

and hardware design in the system. It allows easy multichip

synchronization for most applications.

4. New low power architecture improves power efficiency

(mW/MHz/channel) by 30%.

5. Input signal power and FIFO error detection simplify

designs for downstream analog circuitry protection.

6. Programmable transmit enable function allows easy design

balance between power consumption and wakeup time.

FIFO error detection

On-chip numeric control oscillator allows carrier placement

anywhere in the DAC Nyquist bandwidth

Transmit enable function for extra power saving

High performance, low noise PLL clock multiplier

Digital gain and phase adjustment for sideband suppression

Digital inverse sinc filter

Low power: 1.8 W at 1.6 GSPS, 1.5 W at 1.25 GSPS, full

operating conditions

72-lead LFCSP

APPLICATIONS

Wireless communications: 3G/4G and MC-GSM base stations,

wideband repeaters, software defined radios

Wideband communications: point-to-point, LMDS/MMDS

Transmit diversity/MIMO

Instrumentation

Automated test equipment

Rev. A

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AD9142A* Product Page Quick Links

Last Content Update: 11/01/2016

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Data Sheet

• AD9142A: Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-

Analog Converter Data Sheet

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AD9142A

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Datapath Configuration ............................................................ 35

Digital Quadrature Gain and Phase Adjustment................... 35

DC Offset Adjustment............................................................... 35

Inverse Sinc Filter....................................................................... 36

Input Signal Power Detection and Protection........................ 36

Transmit Enable Function......................................................... 37

Digital Function Configuration ............................................... 37

Multidevice Synchronization and Fixed Latency....................... 38

Very Small Inherent Latency Variation................................... 38

Further Reducing the Latency Variation................................. 38

Synchronization Implementation ............................................ 39

Synchronization Procedures ..................................................... 39

Interrupt Request Operation ........................................................ 40

Interrupt Working Mechanism ................................................ 40

Interrupt Service Routine.......................................................... 40

Temperature Sensor ....................................................................... 41

DAC Input Clock Configurations................................................ 42

Driving the DACCLK and REFCLK Inputs ........................... 42

Direct Clocking .......................................................................... 42

Clock Multiplication .................................................................. 42

PLL Settings ................................................................................ 43

Configuring the VCO Tuning Band ........................................ 43

Automatic VCO Band Select .................................................... 43

Manual VCO Band Select ......................................................... 43

PLL Enable Sequence................................................................. 43

Analog Outputs............................................................................... 44

Transmit DAC Operation.......................................................... 44

Interfacing to Modulators ......................................................... 45

Reducing LO Leakage and Unwanted Sidebands .................. 46

Example Start-Up Routine ............................................................ 47

Device Configuration and Start-Up Sequence 1.................... 47

Device Configuration and Start-Up Sequence 2.................... 47

Device Configuration Register Map and Description............... 49

SPI Configure Register .............................................................. 52

Power-Down Control Register................................................. 52

Interrupt Enable0 Register........................................................ 52

Interrupt Enable1 Register........................................................ 53

Interrupt Flag0 Register............................................................. 53

Interrupt Flag1 Register............................................................. 53

Interrupt Select0 Register.......................................................... 54

Applications....................................................................................... 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 4

Functional Block Diagram .............................................................. 5

Specifications..................................................................................... 6

DC Specifications ......................................................................... 6

Digital Specifications ................................................................... 8

DAC Latency Specifications........................................................ 9

Latency Variation Specifications ................................................ 9

AC Specifications........................................................................ 10

Operating Speed Specifications................................................ 10

Absolute Maximum Ratings ..................................................... 11

Thermal Resistance .................................................................... 11

ESD Caution................................................................................ 11

Pin Configuration and Function Descriptions........................... 12

Typical Performance Characteristics ........................................... 15

Terminology .................................................................................... 20

Serial Port Operation ..................................................................... 21

Data Format ................................................................................ 21

Serial Port Pin Descriptions...................................................... 21

Serial Port Options..................................................................... 21

Data Interface.................................................................................. 23

LVDS Input Data Ports.............................................................. 23

Word Interface Mode................................................................. 23

Byte Interface Mode ................................................................... 23

Data Interface Configuration Options .................................... 23

DLL Interface Mode................................................................... 23

Parity ............................................................................................ 26

SED Operation............................................................................ 26

SED Example............................................................................... 27

Delay Line Interface Mode........................................................ 27

FIFO Operation .............................................................................. 29

Resetting the FIFO ..................................................................... 30

Serial Port Initiated FIFO Reset ............................................... 30

Frame Initiated FIFO Reset....................................................... 30

Digital Datapath.............................................................................. 32

Interpolation Filters ................................................................... 32

Digital Modulation..................................................................... 34

Rev. A | Page 2 of 72

Data Sheet

AD9142A

Interrupt Select1 Register...........................................................54

Frame Mode Register..................................................................54

Data Control 0 Register..............................................................55

Data Control 1 Register..............................................................55

Data Control 2 Register..............................................................55

Data Control 3 Register..............................................................55

Data Status 0 Register .................................................................55

DAC Clock Receiver Control Register.....................................56

Ref Clock Receiver Control Register........................................56

PLL Control 0 Register...............................................................56

PLL Control 2 Register...............................................................57

PLL Control 3 Register...............................................................57

PLL Status 0 Register ..................................................................57

PLL Status 1 Register ..................................................................58

IDAC FS Adjust LSB Register....................................................58

IDAC FS Adjust MSB Register ..................................................58

QDAC FS Adjust LSB Register..................................................58

QDAC FS Adjust MSB Register ................................................58

Die Temperature Sensor Control Register...............................59

Die Temperature LSB Register ..................................................59

Die Temperature MSB Register.................................................59

Chip ID Register..........................................................................59

Interrupt Configuation Register ...............................................59

Sync Control Register.................................................................60

Frame Reset Control Register....................................................60

FIFO Level Configuration Register ..........................................60

FIFO Level Readback Register ..................................................61

FIFO Control Register................................................................61

Data Format Select Register.......................................................61

Datapath Control Register .........................................................61

Interpolation Control Register..................................................62

Over Threshold Control 0 Register ..........................................62

Over Threshold Control 1 Register ..........................................62

Over Threshold Control 2 Register ..........................................62

Input Power Readback LSB Register ........................................62

Input Power Readback MSB Register.......................................63

NCO Control Register................................................................63

NCO Frequency Tuning Word 0 Register ...............................63

NCO Frequency Tuning Word 1 Register ...............................63

NCO Frequency Tuning Word 2 Register ...............................63

NCO Frequency Tuning Word 3 Register ...............................64

NCO Phase Offset 0 Register ....................................................64

NCO Phase Offset 1 Register ....................................................64

IQ Phase Adjust 0 Register ........................................................64

IQ Phase Adjust 1 Register ........................................................64

Power Down Data Input 0 Register..........................................65

IDAC DC Offset 0 Register .......................................................65

IDAC DC Offset 1 Register .......................................................65

QDAC DC Offset 0 Register......................................................65

QDAC DC Offset 1 Register......................................................65

IDAC Gain Adjust Register .......................................................65

QDAC Gain Adjust Register......................................................66

Gain Step Control 0 Register.....................................................66

Gain Step Control 1 Register.....................................................66

Tx Enable Control Register .......................................................66

DAC Output Control Register ..................................................67

DLL Cell Enable 0 Register........................................................67

DLL Cell Enable 1 Register........................................................67

SED Control Register .................................................................67

SED Pattern I0 Low Bits Register..............................................68

SED Pattern I0 High Bits Register ............................................68

SED Pattern Q0 Low Bits Register............................................68

SED Pattern Q0 High Bits Register ..........................................68

SED Pattern I1 Low Bits Register..............................................68

SED Pattern I1 High Bits Register ............................................68

SED Pattern Q1 Low Bits Register............................................68

SED Pattern Q1 High Bits Register ..........................................69

Parity Control Register...............................................................69

Parity Error Rising Edge Register.............................................69

Parity Error Falling Edge Register ............................................69

Version Register ..........................................................................69

DAC Latency and System Skews...................................................70

DAC Latency Variations.............................................................70

FIFO Latency Variation..............................................................70

Clock Generation Latency Variation........................................71

Correcting System Skews...........................................................71

Packaging and Ordering Information..........................................72

Outline Dimensions ...................................................................72

Ordering Guide ...........................................................................72

Rev. A | Page 3 of 72

AD9142A

Data Sheet

REVISION HISTORY

5/14—Rev. 0 to Rev. A

Change to Table 25 ......................................................................... 51

Changes to Table 103...................................................................... 69

12/13—Revision 0: Initial Version

Rev. A | Page 4 of 72

Data Sheet

AD9142A

FUNCTIONAL BLOCK DIAGRAM

INPUT POWER

DETECTION

AD9142A

DLL

13-TAP

DCIP/DCIN

D15P/D15N

16

IOUT1P

IOUT1N

COMPLEX

MODULATION

DAC 1

16-BIT

NCO

HB1

2×

HB2

2×

HB3

2×

DAC CLK

16

D0P/D0N

f_DAC/4

MOD

FRAMEP/PARITYP

FRAMEN/PARITYN

IOUT2P

IOUT2N

DAC 2

16-BIT

REF

VREF

AND

10

BIAS

FSADJ

INTERNAL CLOCK TIMING AND CONTROL LOGIC

DACCLKP

DACCLKN

PROGRAMMING

REGISTERS

SERIAL

INPUT/OUTPUT

PORT

CLK

RCVR

POWER-ON

RESET

MULTICHIP

SYNCHRONIZATION

DAC_CLK

REFP/SYNCP

REFN/SYNCN

CLOCK

MULTIPLIER

REF

RCVR

SYNC

Figure 1.

Rev. A | Page 5 of 72

AD9142A

Data Sheet

SPECIFICATIONS

DC SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I_OUTFS= 20 mA, maximum sample rate, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

RESOLUTION

16

Bits

ACCURACY

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

MAIN DAC OUTPUTS

Offset Error

2.1

3.7

LSB

−0.001

−3.2

0

+0.001 % FSR

Gain Error

With internal reference

+2

19.8

+4.7

20.6

+1.0

% FSR

mA

V

Full-Scale Output Current

Output Compliance Range

Output Resistance

Gain DAC Monotonicity

Settling Time to Within 0.5 LSB

MAIN DAC TEMPERATURE DRIFT

Offset

Based on a 10 kΩ external resistor between FSADJ and AVSS 19.06

−1.0

10

MΩ

Guaranteed

20

ns

0.04

100

30

ppm/°C

Gain

Reference Voltage

REFERENCE

Internal Reference Voltage

Output Resistance

ANALOG SUPPLY VOLTAGES

AVDD33

1.17

1.19

V

kΩ

5

3.13

1.7

3.3

1.8

3.47

1.9

V

CVDD18

DIGITAL SUPPLY VOLTAGES

DVDD18

DVDD18 Variation over Operating

Conditions¹

1.7

−2.5%

1.8

1.9

+2.5%

V

POWER CONSUMPTION

2× Mode

NCO OFF

NCO ON

2× Mode

NCO OFF

NCO ON

4× Mode

NCO OFF

NCO ON

4× Mode

NCO OFF

NCO ON

4× Mode

NCO OFF

NCO ON

4× Mode

NCO OFF

NCO ON

f_DAC= 737.28 MSPS

f_DAC= 983.04 MSPS

f_DAC= 737.28 MSPS

f_DAC= 983.04 MSPS

f_DAC= 1228.8 MSPS

f_DAC= 1474.56 MSPS

925

1217

mW

1135

1520

mW

852

1144

mW

1040

1425

mW

1230

1725

mW

1405

1990

mW

Rev. A | Page 6 of 72

Data Sheet

AD9142A

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

8× Mode

f_DAC= 1600 MSPS

NCO OFF

NCO ON

Phase-Lock Loop (PLL)

Inverse Sinc

Reduced Power Mode (Power-Down)

AVDD33

1350

1984

70

mW

mA

°C

f_DAC= 1474.56 MSPS

113

96.6

1.5

42.3

8.6

CVDD18

DVDD18

OPERATING RANGE

−40

+25

+85

¹This term specifies the maximum allowable variation of DVDD18 over operating conditions compared with the DVDD18 presented to the device at the time the data

interface DLL is enabled.

Rev. A | Page 7 of 72

AD9142A

Data Sheet

DIGITAL SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I_OUTFS= 20 mA, maximum sample rate, unless otherwise noted.

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

0.6

Unit

CMOS INPUT LOGIC LEVEL

Input

Logic High

Logic Low

DVDD18 = 1.8 V

1.2

V

CMOS OUTPUT LOGIC LEVEL

Output

Logic High

Logic Low

DVDD18 = 1.8 V

1.4

V

0.4

LVDS RECEIVER INPUTS

Input Voltage Range

Input Differential Threshold

Input Differential Hysteresis

Receiver Differential Input Impedance

DLL SPEED RANGE

Data, frame signal, and DCI inputs

V_IAor V_IB

V_IDTH

V_IDTHHto V_IDTHL

R_IN

825

−175

1675

+175

mV

Ω

20

100

250

575

MHz

MSPS

DAC UPDATE RATE

1600

575

DAC Adjusted Update Rate

DAC CLOCK INPUT (DACCLKP, DACCLKN)

Differential Peak-to-Peak Voltage

Common-Mode Voltage

REFCLK/SYNCCLK INPUT (REFP/SYNCP, REFN/SYNCN)

Differential Peak-to-Peak Voltage

Common-Mode Voltage

Input Clock Frequency

SERIAL PORT INTERFACE

Maximum Clock Rate

Minimum Pulse Width

High

2× interpolation

100

500

1.25

2000

mV

V

Self biased input, ac-coupled

500

1.25

2000

450

mV

V

MHz

1.03 GHz ≤ f_VCO≤ 2.07 GHz

SCLK

40

MHz

t_PWH

t_PWL

t_DS

12.5

ns

Low

SDIO to SCLK Setup Time

SDIO to SCLK Hold Time

CS to SCLK Setup Time

CS to SCLK Hold Time

SDIO to SCLK Delay

1.5

t_DH

0.68

2.38

9.6

t_DCSB

t_DV

1.4

Wait time for valid output from

SDIO

11

SDIO High-Z to CS

Time for SDIO to relinquish the

output bus

8.5

ns

SDIO LOGIC LEVEL

Voltage Input High

Voltage Input Low

Voltage Output High

Voltage Output Low

V_IH

V_IL

I_IH

1.2

1.8

0

V

0.5

2

0.45

With 2 mA loading

1.36

0

I_IL

Rev. A | Page 8 of 72

Data Sheet

AD9142A

DAC LATENCY SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I_OUTFS= 20 mA, FIFO level is set to 4 (half of the FIFO depth), unless

otherwise noted.

Table 3.

Parameter

Test Conditions/Comments

Min Typ Max Unit

WORD INTERFACE MODE

2× Interpolation

4× Interpolation

8× Interpolation

BYTE INTERFACE MODE

2× Interpolation

4× Interpolation

8× Interpolation

INDIVIDUAL FUNCTION BLOCKS

Modulation

Fine/coarse modulation, inverse sinc, gain/phase compensation off

134

244

481

DACCLK cycles

Fine/coarse modulation, inverse sinc, gain/phase compensation off

145

271

506

DACCLK cycles

Fine

Coarse

Inverse Sinc

Phase Compensation

Gain Compensation

17

10

20

12

16

DACCLK cycles

LATENCY VARIATION SPECIFICATIONS

Table 4.

Parameter

DAC LATENCY VARIATION¹

Min

Typ

Max

Unit

SYNC Off

SYNC On

1

0

2

1

DACCLK cycles

¹DAC latency is defined as the elapsed time from a data sample clocked at the input to the AD9142A until the analog output begins to change.

Rev. A | Page 9 of 72

AD9142A

Data Sheet

AC SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I_OUTFS= 20 mA, maximum sample rate, unless otherwise noted.

Table 5.

Parameter

Test Conditions/Comments

−14 dBFS single tone

f_OUT= 200 MHz

Min Typ

Max Unit

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_DAC= 737.28 MSPS

BW = 125 MHz

85

80

dBc

BW = 270 MHz

f_DAC= 983.04 MSPS

BW = 360 MHz

f_DAC= 1228.8 MSPS

BW = 200 MHz

f_OUT= 200 MHz

f_OUT= 280 MHz

85

dBc

85

75

dBc

BW = 500 MHz

f_DAC= 1474.56 MSPS

BW = 737 MHz

BW = 400 MHz

f_OUT= 10 MHz

85

80

dBc

f_OUT= 280 MHz

−12 dBFS each tone

f_OUT= 200 MHz

f_OUT= 280 MHz

f_OUT= 10 MHz

f_OUT= 280 MHz

Eight-tone, 500 kHz tone spacing

f_OUT= 200 MHz

f_OUT= 280 MHz

f_OUT= 10 MHz

f_OUT= 280 MHz

Single carrier

f_OUT= 200 MHz

f_OUT= 20 MHz

f_OUT= 280 MHz

f_OUT= 20 MHz

f_OUT= 280 MHz

Single carrier

TWO-TONE INTERMODULATION DISTORTION (IMD)

f_DAC= 737.28 MSPS

f_DAC= 983.04 MSPS

f_DAC= 1228.8 MSPS

f_DAC= 1474.56 MSPS

80

82

80

85

79

dBc

NOISE SPECTRAL DENSITY (NSD)

f_DAC= 737.28 MSPS

f_DAC= 983.04 MSPS

f_DAC= 1228.8 MSPS

f_DAC= 1474.56 MSPS

−160

−161.5

−164.5

−166

−162.5

dBm/Hz

W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR)

f_DAC= 983.04 MSPS

f_DAC= 1228.8 MSPS

81

83

80

81

80

dBc

f_DAC= 1474.56 MSPS

W-CDMA SECOND (ACLR)

f_DAC= 983.04 MSPS

f_DAC= 1228.8 MSPS

f_OUT= 200 MHz

f_OUT= 20 MHz

f_OUT= 280 MHz

f_OUT= 20 MHz

85

86

85

dBc

f_DAC= 1474.56 MSPS

f_OUT= 280 MHz

OPERATING SPEED SPECIFICATIONS

Table 6.

DVDD18, CVDD18 = 1.9 V 5%

or 1.8 V ꢀ%

DVDD18, CVDD18 = 1.8 V 5%

DVDD18, CVDD18 = 1.9 V ꢀ%

Interpolation f_DCI(MSPS)

f_DAC(MSPS)

Maximum

f_DCI(MSPS)

Maximum

f_DAC(MSPS)

Maximum

f_DCI(MSPS)

Maximum

f_DAC(MSPS)

Maximum

Factor

Maximum

2×

4×

8×

575

350

175

1150

1400

575

375

187.5

1150

1500

575

400

200

1150

1600

Rev. A | Page 10 of 72

Data Sheet

AD9142A

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 7.

The exposed pad (EPAD) must be soldered to the ground plane

(AVSS) for the 72-lead LFCSP. The EPAD provides an electrical,

thermal, and mechanical connection to the board.

Parameter

Rating

AVDD33 to GND

DVDD18, CVDD18 to GND

FSADJ, VREF, IOUT1P, IOUT1N, IOUT2P,

IOUT2N to GND

D15P to D0P, D15N to D0N,

FRAMEP/PARITYP, FRAMEN/PARITYN,

DCIP, DCIN to GND

DACCLKP, DACCLKN, REFP, SYNCP,

REFN, SYNCN to GND

−0.3 V to +3.6 V

−0.3 V to +2.1 V

−0.3 V to AVDD33 + 0.3 V

Typical θ_JA, θ_JB, and θ_JCvalues are specified for a 4-layer board in

still air. Airflow increases heat dissipation, effectively reducing

−0.3 V to DVDD18 + 0.3 V

θ_JAand θ_JB.

Table 8. Thermal Resistance

−0.3 V to CVDD18 + 0.3 V

−0.3 V to DVDD18 + 0.3 V

Package θ_JAθ_JB

θ_JC

Unit Conditions

72-Lead LFCSP 20.7 10.9 1.1

°C/W EPAD soldered

to ground plane

RESET, IRQ1, IRQ2, CS, SCLK, SDIO

to GND

Junction Temperature

Storage Temperature Range

125°C

−65°C to +150°C

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. A | Page 11 of 72

AD9142A

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CVDD18

REFP/SYNCP

REFN/SYNCN

CVDD18

1

2

3

4

5

6

7

8

9

54 CS

53 SCLK

52 SDIO

51 IRQ1

50 IRQ2

49 DVDD18

48 DVDD18

47 D0N

46 D0P

45 D1N

44 D1P

43 DVDD18

42 D2N

RESET

TXEN

DVDD18

FRAMEP/PARITYP

FRAMEN/PARITYN

AD9142A

TOP VIEW

(Not to Scale)

D15P 10

D15N 11

DVDD18 12

D14P 13

D14N 14

D13P 15

D13N 16

D12P 17

D12N 18

41 D2P

40 D3N

39 D3P

38 D4N

37 D4P

NOTES

1. EXPOSED PAD (EPAD) MUST BE SOLDERED TO THE GROUND

PLANE (AVSS, DVSS, CVSS). THE EPAD PROVIDES AN ELECTRI-

CAL, THERMAL, AND MECHANICAL CONNECTION TO THE BOARD.

Figure 2. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

CVDD18

REFP/SYNCP

REFN/SYNCN

CVDD18

RESET

Description

1

2

3

4

5

6

1.8 V PLL Supply. CVDD18 supplies the clock receivers, clock multiplier, and clock distribution.

PLL Reference Clock/Synchronization Clock Input, Positive.

PLL Reference Clock/Synchronization Clock Input, Negative.

1.8 V PLL Supply. CVDD18 supplies the clock receivers, clock multiplier, and clock distribution.

Reset, Active Low. CMOS levels with respect to DVDD18. Recommended reset pulse length is 1 µs.

TXEN

Active High Transmit Path Enable. CMOS levels with respect to DVDD18. A low level on this pin triggers

three selectable actions in the DAC. See Table 87 for details.

7

DVDD18

1.8 V Digital Supply. Pin 7 supplies power to the digital core, digital data ports, serial port input/output

pins, RESET, IRQ1, and IRQ2.

8

9

10

11

12

FRAMEP/PARITYP

FRAMEN/PARITYN

D15P

D15N

DVDD18

Frame/Parity Input, Positive.

Frame/Parity Input, Negative.

Data Bit 15 (MSB), Positive.

Data Bit 15 (MSB), Negative.

1.8 V Digital Supply. Pin 12 supplies the power to the digital core and digital data ports, serial port

input/output pins, RESET, IRQ1, and IRQ2.

13

14

15

16

17

18

19

D14P

D14N

D13P

D13N

D12P

D12N

DVDD18

Data Bit 14, Positive.

Data Bit 14, Negative.

Data Bit 13, Positive.

Data Bit 13, Negative.

Data Bit 12, Positive.

Data Bit 12, Negative.

1.8 V Digital Supply. Pin 19 supplies power to the digital core, digital data ports, serial port input/output

pins, RESET, IRQ1, and IRQ2.

20

21

22

23

D11P

D11N

D10P

D10N

Data Bit 11, Positive.

Data Bit 11, Negative.

Data Bit 10, Positive.

Data Bit 10, Negative.

Rev. A | Page 12 of 72

Data Sheet

AD9142A

Pin No.

24

25

26

27

28

29

30

31

32

33

34

35

Mnemonic

Description

D9P

D9N

D8P

D8N

DCIP

DCIN

D7P

D7N

D6P

D6N

D5P

D5N

DVDD18

Data Bit 9, Positive.

Data Bit 9, Negative.

Data Bit 8, Positive.

Data Bit 8, Negative.

Data Clock Input, Positive.

Data Clock Input, Negative.

Data Bit 7, Positive.

Data Bit 7, Negative.

Data Bit 6, Positive.

Data Bit 6, Negative.

Data Bit 5, Positive.

Data Bit 5, Negative.

36

1.8 V Digital Supply. Pin 36 supplies power to the digital core, digital data ports, serial port input/output

pins, RESET, IRQ1, and IRQ2.

37

38

39

40

41

42

43

D4P

D4N

D3P

D3N

D2P

D2N

DVDD18

Data Bit 4, Positive.

Data Bit 4, Negative.

Data Bit 3, Positive.

Data Bit 3, Negative.

Data Bit 2, Positive.

Data Bit 2, Negative.

1.8 V Digital Supply. Pin 43 supplies power to the digital core, digital data ports, serial port input/output

pins, RESET, IRQ1, and IRQ2.

44

45

46

47

48

D1P

D1N

D0P

D0N

Data Bit 1, Positive.

Data Bit 1, Negative.

Data Bit 0, Positive.

Data Bit 0, Negative.

DVDD18

1.8 V Digital Supply. Pin 48 supplies power to the digital core, digital data ports, serial port input/output

pins, RESET, IRQ1, and IRQ2.

49

50

51

DVDD18

IRQ2

1.8 V Digital Supply. Pin 49 supplies power to the digital core, digital data ports, serial port input/output

pins, RESET, IRQ1, and IRQ2.

Second Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18

through a 10 kΩ resistor.

First Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through

a 10 kΩ resistor.

IRQ1

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

SDIO

SCLK

CS

Serial Port Data Input/Output. CMOS levels with respect to DVDD18.

Serial Port Clock Input. CMOS levels with respect to DVDD18.

Serial Port Chip Select. Active low (CMOS levels with respect to DVDD18).

3.3 V Analog Supply.

QDAC Positive Current Output.

QDAC Negative Current Output.

AVDD33

IOUT2P

IOUT2N

AVDD33

CVDD18

DACCLKN

DACCLKP

CVDD18

AVDD33

IOUT1N

IOUT1P

AVDD33

FSADJ

3.3 V Analog Supply.

1.8 V Clock Supply. Supplies clock receivers and clock distribution.

DAC Clock Input, Negative.

DAC Clock Input, Positive.

1.8 V Clock Supply. Supplies clock receivers and clock distribution.

3.3 V Analog Supply.

IDAC Negative Current Output.

IDAC Positive Current Output.

3.3 V Analog Supply.

Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to GND.

Voltage Reference. Nominally 1.2 V output. Decouple VREF to GND.

VREF

Rev. A | Page 13 of 72

AD9142A

Data Sheet

Pin No.

71

72

Mnemonic

Description

CVDD18

EPAD

1.8 V Clock Supply. Pin 71 supplies the clock receivers, clock multiplier, and clock distribution.

1.8 V Clock Supply. Pin 72 supplies the clock receivers, clock multiplier, and clock distribution.

Exposed Pad. The exposed pad (EPAD) must be soldered to the ground plane (AVSS, DVSS, CVSS). The

EPAD provides an electrical, thermal, and mechanical connection to the board.

Rev. A | Page 14 of 72

Data Sheet

AD9142A

TYPICAL PERFORMANCE CHARACTERISTICS

0

–60

–65

BW = 80MHz, –6dBFS

BW = 80MHz, –12dBFS

BW = 300MHz, –6dBFS

BW = 300MHz, –12dBFS

f_DAC= 737.28MHz

f_DAC= 983.04MHz

f_DAC= 1228.8MHz

–10

f_DAC= 1474.56MHz

–20

–30

–40

–50

–60

–70

–80

–90

–70

–75

–80

–85

–85 MEANS ≤ –85

< –85

0

100

200

300

400

500

600

700

800

0

20

40

60

80

100 120 140 160 180 200

f_OUT(MHz)

Figure 3. Single Tone (0 dBFS) SFDR vs. f_OUTin the First Nyquist Zone over f_DAC

Figure 6. In-Band, Single Tone SFDR (Excluding Second Harmonic) vs. f_OUTin

80 MHz and 300 MHz Bandwidths, f_DAC= 737.28 MHz

0

–60

BW = 80MHz, –6dBFS

BW = 80MHz, –12dBFS

BW = 300MHz, –6dBFS

0dBFS

–6dBFS

–12dBFS

–16dBFS

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–65

–70

BW = 300MHz, –12dBFS

–75

–80

–85

–85 MEANS ≤ –85

< –85

0

100

200

300

400

500

600

700

800

0

50

100

150

200

250

300

f_OUT(MHz)

Figure 4. Single Tone Second Harmonic vs. f_OUTin the First Nyquist Zone

over Digital Back Off, f_DAC= 1474.56 MHz

Figure 7. In-Band, Single Tone SFDR (Excluding Second Harmonic) vs. f_OUTin

80 MHz and 300 MHz BW, f_DAC= 983.04 MHz

0

–60

BW = 80MHz, –6dBFS

BW = 80MHz, –12dBFS

BW = 300MHz, –6dBFS

0dBFS

–6dBFS

–12dBFS

–16dBFS

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–65

–70

BW = 300MHz, –12dBFS

–75

–80

–85

–85 MEANS ≤ –85

< –85

0

100

200

300

400

500

600

700

800

0

50

100

150

200

250

300

350

f_OUT(MHz)

Figure 5. Single Tone Third Harmonic vs. f_OUTin the First Nyquist Zone

over Digital Back Off, f_DAC= 1474.56 MHz

Figure 8. In-Band, Single Tone SFDR (Excluding Second Harmonic) vs. f_OUTin

80 MHz and 300 MHz Bandwidths, f_DAC= 1228.8 MHz

Rev. A | Page 15 of 72

AD9142A

Data Sheet

–60

–65

–70

–75

–80

–85

0

–20

BW = 80MHz, –6dBFS

BW = 80MHz, –12dBFS

BW = 300MHz, –6dBFS

BW = 300MHz, –12dBFS

0.6MHz TONE SPACING

16MHz TONE SPACING

35MHz TONE SPACING

–40

–60

–80

–100

–120

–85 MEANS ≤ –85

< –85

0

50

100

150

200

250

300

350

0

100

200

300

400

500

600

700

800

f_OUT(MHz)

Figure 9. In-Band, Single Tone SFDR (Excluding Second Harmonic) vs. f_OUTin

80 MHz and 300 MHz Bandwidths, f_DAC= 1474.56 MHz

Figure 12. Two Tone, Third IMD vs. f_OUTover Tone Spacing,

f_DAC= 1474.56 MHz

0

–152

f_DAC= 737.28MHz

f_DAC= 983.04MHz

f_DAC= 1228.8MHz

f_DAC= 1474.56MHz

f_DAC= 737.28MHz

f_DAC= 983.04MHz

f_DAC= 1228.8MHz

f_DAC= 1474.56MHz

–10

–154

–156

–158

–160

–162

–164

–166

–168

–20

–30

–40

–50

–60

–70

–80

–90

0

100

200

300

400

500

600

700

800

0

100

200

300

400

500

600

700

800

f_OUT(MHz)

Figure 10. Two Tone, Third IMD vs. f_OUTover f_DAC

Figure 13. Single Tone (0 dBFS) NSD vs. f_OUTover f_DAC

–152

–154

–156

–158

–160

–162

–164

–166

–168

0

–20

0dBFS

–6dBFS

–9dBFS

–6dBFS

–12dBFS

–16dBFS

–40

–60

–80

–100

–120

0

100

200

300

400

500

600

700

800

0

100

200

300

400

500

600

700

800

f_OUT(MHz)

Figure 14. Single Tone NSD vs. f_OUTover Digital Back Off,

f_DAC= 1474.56 MHz

Figure 11. Two Tone, Third IMD vs. f_OUTover Digital Back Off,

_DAC= 1474.56 MHz

f

Rev. A | Page 16 of 72

Data Sheet

AD9142A

–150

–60

–65

–70

–75

–80

–85

–90

737.2MHz

f_DAC= 1474.56MHz, PLL OFF, 0dBFS

f_DAC= 1474.56MHz, PLL ON, 0dBFS

f_DAC= 1228.8MHz, PLL OFF, 0dBFS

f_DAC= 1228.8MHz, PLL ON, 0dBFS

983.04MHz

1228.8MHz

1474.56MHz

–152

–154

–156

–158

–160

–162

–164

–166

–168

–170

0

100

200

300

400

500

600

700

800

0

100

200

300

400

500

600

700

800

f_OUT(MHz)

Figure 15. 1C WCDMA NSD vs. f_OUT, over f_DAC

Figure 18. 1C WCDMA, Second Adjacent ACLR vs. f_OUT, PLL On and Off

–150

–152

–154

–156

–158

–160

–162

–164

–166

–168

PLL OFF

PLL ON

0

100

200

300

400

500

600

700

800

f_OUT(MHz)

Figure 16. Single Tone NSD vs. f_OUT, f_DAC= 1474.28 MHz, PLL On and Off

Figure 19. Two Tone, Third IMD Performance,

IF = 280 MHz, f_DAC= 1474.28 MHz

–60

f_DAC= 1474.56MHz, PLL OFF, 0dBFS

f_DAC= 1474.56MHz, PLL ON, 0dBFS

f_DAC= 1228.8MHz, PLL OFF, 0dBFS

f_DAC= 1228.8MHz, PLL ON, 0dBFS

–65

–70

–75

–80

–85

0

100

200

300

400

500

600

700

800

f_OUT(MHz)

Figure 17. 1C WCDMA, First Adjacent ACLR vs. f_OUT, PLL On and Off

Figure 20. 1C WCDMA ACLR Performance, IF = 280 MHz, f_DAC= 1474.28 MHz

Rev. A | Page 17 of 72

AD9142A

Data Sheet

1600

1400

1200

1000

800

2×

4×

8×

600

400

200

400

600

800

1000

1200

1400

1600

f_DAC(MHz)

Figure 21. Single Tone f_DAC= 1474.56 MHz,

f_OUT= 280 MHz, −14 dBFS

Figure 24. Total Power Baseline Consumption vs. f_DACover Interpolation

600

2×

4×

8×

500

400

300

200

100

0

200

400

600

800

1000

1200

1400

1600

f_DAC(MHz)

Figure 22. 4C WCDMA ACLR Performance,

IF = 280 MHz, f_DAC= 1474.28 MHz

Figure 25. DVDD18 Supply Current vs. f_DACover Interpolation

350

NCO

INVERSE SINC

DIGITAL GAIN AND PHASE

f_S/4 MODULATION

300

250

200

150

100

50

0

200

400

600

800

1000

1200

1400

1600

f_DAC(MHz)

Figure 23. Single Tone SFDR f_DAC= 1474.56 MHz,

4× Interpolation, f_OUT= 10 MHz, −14 dBFS

Figure 26. DVDD18 Supply Current vs. f_DACover Digital Functions

Rev. A | Page 18 of 72

Data Sheet

AD9142A

250

CVDD18, PLL ON

CVDD18, PLL OFF

AVDD33

200

150

100

50

200

400

600

800

1000

1200

1400

1600

f_DAC(MHz)

Figure 27. CVDD18, AVDD33 Supply Current vs. f_DAC

Rev. A | Page 19 of 72

AD9142A

Data Sheet

TERMINOLOGY

Integral Nonlinearity (INL)

Settling Time

INL is the maximum deviation of the actual analog output from

the ideal output, determined by a straight line drawn from zero

scale to full scale.

Settling time is the time required for the output to reach and

remain within a specified error band around its final value,

measured from the start of the output transition.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input code.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the peak amplitude

of the output signal and the peak spurious signal within the dc

to Nyquist frequency of the DAC. Typically, the interpolation

filters reject energy in this band. This specification, therefore,

defines how well the interpolation filters work and the effect of

other parasitic coupling paths on the DAC output.

Offset Error

Offset error is the deviation of the output current from the ideal

of 0 mA. For IOUT1P, 0 mA output is expected when all inputs

are set to 0. For IOUT1N, 0 mA output is expected when all

inputs are set to 1.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal

to the rms sum of all other spectral components below the Nyquist

frequency, excluding the first six harmonics and dc. The value

for SNR is expressed in decibels.

Gain Error

Gain error is the difference between the actual and ideal output

span. The actual span is determined by the difference between

the output when all inputs are set to 1 and the output when all

inputs are set to 0.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of

Output Compliance Range

f

_DATA(interpolation rate), a digital filter can be constructed that

The output compliance range is the range of allowable voltage

at the output of a current output DAC. Operation beyond the

maximum compliance limits can cause either output stage

saturation or breakdown, resulting in nonlinear performance.

has a sharp transition band near f_DATA/2. Images that typically

appear around f_DAC(output data rate) can be greatly suppressed.

Adjacent Channel Leakage Ratio (ACLR)

ACLR is the ratio in decibels relative to the carrier (dBc) between

the measured power within a channel relative to its adjacent

channel.

Temperature Drift

Temperature drift is specified as the maximum change from

the ambient (25°C) value to the value at either T_MINor T_MAX

.

For offset and gain drift, the drift is reported in ppm of full-

scale range (FSR) per degree Celsius. For reference drift, the

drift is reported in ppm per degree Celsius.

Complex Image Rejection

In a traditional two-part upconversion, two images are created

around the second IF frequency. These images have the effect

of wasting transmitter power and system bandwidth. By placing

the real part of a second complex modulator in series with the

first complex modulator, either the upper or lower frequency

image near the second IF can be rejected.

Power Supply Rejection (PSR)

PSR is the maximum change in the full-scale output as the

supplies are varied from minimum to maximum specified

voltages.

Rev. A | Page 20 of 72

Data Sheet

AD9142A

SERIAL PORT OPERATION

The serial port is a flexible, synchronous serial communications

port that allows easy interfacing to many industry standard micro-

controllers and microprocessors. The serial I/O is compatible

with most synchronous transfer formats, including both the

Motorola® SPI and Intel® SSR protocols. The interface allows

read/write access to all registers that configure the AD9142A.

MSB-first or LSB-first transfer formats are supported. The serial

port interface is a 3-wire only interface. The input and output

share a single pin input/output (SDIO).

A14 to A0 (Bit 14 to Bit 0 of the instruction word) determine

the register that is accessed during the data transfer portion of

the communication cycle. For multibyte transfers, A14 is the

starting address; the device generates the remaining register

addresses based on the SPI_LSB_FIRST bit.

SERIAL PORT PIN DESCRIPTIONS

Serial Clock (SCLK)

The serial clock pin synchronizes data to and from the device

and runs the internal state machines. The maximum frequency

of SCLK is 40 MHz. All data input is registered on the rising edge

of SCLK. All data is driven out on the falling edge of SCLK.

54

53

52

CS

SPI

PORT

SCLK

SDIO

CS

Chip Select (

)

Figure 28. Serial Port Interface Pins

CS

is an active low input that starts and gates a communication

cycle. It allows more than one device to be used on the same serial

There are two phases to a communication cycle with the AD9142A.

Phase 1 is the instruction cycle (the writing of an instruction

byte into the device), coincident with the first 16 SCLK rising

edges. The instruction word provides the serial port controller

with information regarding the data transfer cycle, Phase 2, of

the communication cycle. The Phase 1 instruction word defines

whether the upcoming data transfer is a read or write, along with

the starting register address for the next data transfer in the

cycle.

communications line. The SDIO pins enter a high impedance

CS

state when the

input is high. During the communication

CS

cycle,

should stay low.

Serial Data I/O (SDIO)

The SDIO pin is a bidirectional data line.

SERIAL PORT OPTIONS

The serial port can support both MSB-first and LSB-first data

formats. This functionality is controlled by the SPI_LSB_FIRST bit

(Register 0x00, Bit 6). The default is MSB first (LSB_FIRST = 0).

CS

A logic high on the

pin, followed by a logic low, resets the

serial port timing to the initial state of the instruction cycle.

From this state, the next 16 rising SCLK edges represent the

instruction bits of the current I/O operation.

When SPI_LSB_FIRST = 0 (MSB first), the instruction and data

bits must be written from MSB to LSB. Multibyte data transfers

in MSB-first format start with an instruction word that includes the

register address of the most significant data byte. Subsequent data

bytes must follow from high address to low address. In MSB-first

mode, the serial port internal word address generator decrements

for each data byte of the multibyte communication cycle.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the device and

the system controller. Phase 2 of the communication cycle is a

transfer of one data byte. Registers change immediately upon

writing to the last bit of each transfer byte, except for the frequency

tuning word and NCO phase offsets, which change only when

the frequency tuning word (FTW) update bit is set.

When SPI_LSB_FIRST = 1 (LSB first), the instruction and data

bits must be written from LSB to MSB. Multibyte data transfers

in LSB-first format start with an instruction word that includes the

register address of the least significant data byte. Subsequent data

bytes must follow from low address to high address. In LSB-first

mode, the serial port internal word address generator increments

for each data byte of the multibyte communication cycle.

DATA FORMAT

The instruction byte contains the information shown in Table 10.

Table 10. Serial Port Instruction Word

I15 (MSB)

I[14:0]

R/W

A[14:0]

If the MSB-first mode is active, the serial port controller data

address decrements from the data address written toward 0x00

for multibyte I/O operations. If the LSB-first mode is active, the

serial port controller data address increments from the data

address written toward 0xFF for multibyte I/O operations.

W

R/ (Bit 15 of the instruction word) determines whether a read

or a write data transfer occurs after the instruction word write.

Logic 1 indicates a read operation and Logic 0 indicates a write

operation.

Rev. A | Page 21 of 72

AD9142A

Data Sheet

t_DCSB

t_SCLK

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CS

t_PWH

t_PWL

SCLK

t_DS

t_DH

SDIO

R/W A14 A13

A3 A2 A1 A0 D7 D6 D5

D3 D2 D1 D0

0 0 0 0

N

SDIO

INSTRUCTION BIT 15 INSTRUCTION BIT 14

Figure 29. Serial Register Interface Timing, MSB First

Figure 31. Timing Diagram for Serial Port Register Write

CS

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CS

SCLK

t_DV

SDIO

DATA BIT n

DATA BIT n – 1

SDIO

A0 A1 A2

A12 A13 A14 R/W D0₀D1₀D2₀

D4_ND5_ND6_ND7_N

Figure 32. Timing Diagram for Serial Port Register Read

Figure 30. Serial Register Interface Timing, LSB First

Rev. A | Page 22 of 72

Data Sheet

AD9142A

DATA INTERFACE

LVDS INPUT DATA PORTS

Table 12. Data Interface Configuration Options

Register 0xꢀ6

Description

The AD9142A has a 16-bit LVDS bus that accepts 16-bit I and

Q data either in word (16-bit) or byte (8-bit) formats. In the

word interface mode, the data is sent over the entire 16-bit data

bus. In the byte interface mode, the data is sent over the lower

8-bit (D7 to D0) LVDS bus. Table 11 lists the pin assignment of

the bus and the SPI register configuration for each mode.

DATA_FORMAT (Bit 7)

Select between binary and twos

complement formats.

Indicate I/Q data pairing on data input.

This allows the I and Q data that is

received to be paired in various ways.

Swaps the bit order of the data input

port. Remaps the input data from

D[15:0] to D[0:15].

DATA_PAIRING (Bit 6)

DATA_BUS_INVERT (Bit 5)

Table 11. LVDS Input Data Modes

Interface Mode Pin Assignment SPI Register Configuration

Word

Byte

D15 to D0

D7 to D0

Register 0x26, Bit 0 = 0

Register 0x26, Bit 0 = 1

DLL INTERFACE MODE

A source synchronous LVDS interface is used between the data

host and AD9142A to achieve high data rates while simplifying

the interface. The FPGA or ASIC feeds the AD9142A with 16-bit

input data. Along with the input data, the FPGA or ASIC

provides a DDR (double data rate) data clock input (DCI).

WORD INTERFACE MODE

In word interface mode, the digital clock input (DCI) signal is a

reference bit that generates a double data rate (DDR) data

sampling clock. Time align the DCI signal with the data. The

IDAC data follows the rising edge of the DCI, and the QDAC

data follows the falling edge of the DCI, as shown in Figure 33.

WORD INTERFACE MODE

A delay locked loop (DLL) circuit designed to operate with DCI

clock rates between 250 and 575 MHz is used to generate a phase-

shifted version of the DCI, called DSC (data sampling clock), to

register the input data on both the rising and falling edges.

I

Q

I

Q

1

INPUT DATA[15:0]

0

1

As shown in Figure 35, the DCI clock edges must be coincident

with the data bit transitions with minimum skew and jitter. The

nominal sampling point of the input data occurs in the middle

of the DCI clock edges because this point corresponds to the

center of the data eye. This is also equivalent to a nominal phase

shift of 90°of the DCI clock.

DCI

Figure 33. Timing Diagram for Word Interface Mode

BYTE INTERFACE MODE

In byte interface mode, the required sequence of the input data

stream is I[15:8], I[7:0], Q[15:8], Q[7:0]. A frame signal is

required to align the order of input data bytes properly. Time

align both the DCI signal and frame signal with the data. The

rising edge of the frame indicates the start of the sequence. The

frame can be either a one shot or periodical signal as long as its

first rising edge is correctly captured by the device. For a one

shot frame, the frame pulse must be held at high for at least one

DCI cycle. For a periodical frame, the frequency needs to be

The data timing requirements are defined by a data valid

window (DVW) that is dependent on the data clock input skew,

input data jitter, and the variations of the DLL delay line across

delay settings. The DVW is defined as

DVW = t_{DATA PERIOD}− t_{DATA SKEW}– t_{DATA JITTER}

The available margin for data interface timing is given by

t

_MARGIN= DVW − (t_S+ t_H)

f

_DCI/(2 × n)

The difference between the setup and hold times, which is also

called the keep out window, or KOW, is the area where data

transitions should not happen. The timing margin allows

tuning of the DLL delay setting by the user, see Figure 36.

where n is a positive integer, that is, 1, 2, 3, …

Figure 34 is an example of signal timing in byte mode.

BYTE INTERFACE MODE

From the figure, it can be seen that the ideal location for the

DSC signal is 90° out of phase from the DCI input. However,

due to skew of the DCI relative to the data, it may be necessary

to change the DSC phase offset to sample the data at the center

of its eye diagram. The sampling instance can be varied in discrete

increments by offsetting the nominal DLL phase shift value of

90° via Register 0x0A, Bits[3:0]. This register is a signed value.

The MSB is the sign and the LSBs are the magnitude. The

following equation defines the phase offset relationship:

I

Q

0[7:0]

INPUT DATA[7:0]

0[15:8]

0[7:0]

0[15:8]

DCI

FRAME

Figure 34. Timing Diagram for Byte Interface Mode

DATA INTERFACE CONFIGURATION OPTIONS

To provide more flexibility for the data interface, some

additional options are listed in Table 12.

Phase Offset = 90° n × 11.25°, |n| < 7

where n is the DLL phase offset setting.

Rev. A | Page 23 of 72

AD9142A

Data Sheet

Figure 35 shows the DSC setup and hold times with respect to

the DCI signal and data signals.

Table 13. DLL Phase Setup and Hold Times (Guaranteed)

Data Port Setup and Hold Times (ps)

at DLL Phase

Frequency,

f_DCI(MHz)

DATA

Time (ps)

−3

0

+3

307

368

491

t_S

t_H

t_S

t_H

t_S

t_H

−125

834

−70

753

−81

601

−385

1120

−305

967

−695

1417

−534

1207

−402

928

DCI

DSC

t_S

t_H

−245

762

Figure 35. LVDS Data Port Setup and Hold Times

Table 13 lists the values that are guaranteed over the operating

conditions. These values were taken with a 50% duty cycle and a

DCI swing of 450 mV p-p. For best performance, the duty cycle

variation should be kept below 5%, and the DCI input should

be as high as possible, up to 1200 mV p-p.

t_{DATA JITTER}

t_H

t_S

INPUT DATA

DATA EYE

t_{DATA PERIOD}

DCI

DATA SAMPLE CLOCK

t_{DATA JITTER}

t_HAND t_S

DLL PHASE

DELAY

t_{DCI SKEW}

INPUT DATA

DATA EYE

t_{DATA PERIOD}

DCI

DATA SAMPLE CLOCK

Figure 36. LVDS Data Port Timing Requirements

Rev. A | Page 24 of 72

Data Sheet

AD9142A

Table 14. DLL Phase Setup and Hold Times (Typical)

Data Port Setup and Hold Times (ps) at DLL Phase

Frequency, Time

f_DCI¹(MHz)

(ps)

−6

−5

−196 −312 −416 −530 −658

579 707 825 947 1067

−172 −264 −364 −464 −556

537 646 757 878 977

−166 −256 −341 −426 −515

500 598 703 803 897

−114 −190 −271 −358 −447

563 647 740 832

−180 −252 −328 −409

524 607 682 762

−150 −225 −315 −391

504 569 641 718

−161 −243 −303 −384

503 546 604 674

−110 −170 −229 −297

−4

−3

−ꢀ

−1

0

+1

+ꢀ

+3

+4

+5

+6

250

t_S

−93

468

−87

451

−82

422

−46

405

−23

383

−7

−770

1188

−653

1092

−622

1000

−538

914

−878

1315

−756

1218

−715

1105

−612

1000

−574

930

−983

1442

−859

1311

−809

1203

−706

1100

−654

1011

−595

941

−1093

1570

−956

1423

−900

1303

−806

1200

−731

1097

−661

1025

−643

965

−1193

1697

−1053

1537

−1001

1411

−891

1292

−819

1186

−726

1106

−713

1039

−641

966

−1289

1777

−1151

1653

−1097

1522

−966

1380

−889

1277

−786

1187

−771

1110

−704

1032

−622

983

−1412

1876

−1251

1728

−1184

1612

−1044

1476

−959

1358

−853

1264

−833

1178

−752

1097

−672

1042

−640

988

t_H

t_S

275

300

325

350

375

400

425

450

475

500

525

550

575

t_H

t_S

t_H

t_S

t_H

t_S

483

−92

451

−82

466

−98

445

−52

408

−34

406

−51

399

−28

354

−52

356

−39

340

−28

348

−491

844

t_H

t_S

−461

783

−526

863

t_H

t_S

401

−46

385

4

−448

748

−513

826

−578

890

t_H

t_S

−394

692

−449

762

−517

829

−579

900

t_H

t_S

358

11

465

−92

457

−95

451

−77

399

524

−147 −209 −269

516 573 637

−147 −198 −255

499 556 613

−128 −183 −233

445 500 555

595

625

−324

693

−386

731

−446

792

−509

852

−564

917

t_H

t_S

354

−15

355

9

−313

675

−366

727

−425

779

−480

815

−530

873

−585

930

t_H

t_S

−288

615

−333

668

−390

726

−438

783

−495

825

−545

881

−594

934

t_H

t_S

313

−7

−100 −147 −187 −237

−285

592

−335

645

−387

692

−436

746

−483

799

−530

850

−581

909

t_H

t_S

311

−5

395

−74

378

−66

379

438

−107 −147 −192

423 468 510

−102 −143 −181

414 453 496

489

537

−249

560

−302

610

−352

659

−397

710

−440

756

−486

810

−529

865

t_H

t_S

300

8

−245

544

−280

599

−336

654

−366

708

−406

759

−443

806

−488

847

t_H

312

¹Table 14 shows characterization data for selected f_DCIfrequencies. Other frequencies are possible, and Table 14 can be used to estimate performance.

Table 14 shows the typical times for various DCI clock frequencies

that are required to calculate the data valid margin. The amount

of margin that is available for tuning of the DSC sampling point

can be determined using Table 14.

Register 0x0D optimizes the DLL stability over the operating

frequency range. Table 15 shows the recommended setting.

Table 15. DLL Configuration Options

DCI Speed

≥350 MHz

<350 MHz

Register 0x0D

Maximizing the opening of the eye in both the DCI and data signals

improves the reliability of the data port interface. Differential

controlled impedance traces of equal length (that is, delay) should

be used between the host processor and the AD9142A input. To

ensure coincident transitions with the data bits, the DCI signal

should be implemented as an additional data line with an

alternating (010101…) bit sequence from the same output

drivers used for the data.

0x06

0x86

The status of the DLL can be polled by reading the data status

register at Address 0x0E. Bit 0 indicates that the DLL is running

and attempting lock, and Bit 7 is set to when the DLL has

locked. Bit 2 is 1 when a valid data clock in is detected. The

warning bits in Register 0x0E[6:4] can be used as indicators that

the DAC may be operating in a non ideal location in the delay

line. Note that these bits are read at the SPI port speed, which is

much slower than the actual speed of the DLL. This means they

can only show a snapshot of what is happening as opposed to

giving real-time feedback.

The DCI signal is ac-coupled by default; thus, removing the DCI

signal may cause DAC output chatter due to randomness on the

DCI input. To avoid this, it is recommended that the DAC output is

disabled whenever the DCI signal is not present. To do this,

program the DAC output current power down bit in Register 0x01,

Bit 7 and Bit 6 to 1. When the DCI signal is again present, the DAC

output can be enabled by setting Register 0x01, Bit 7 and Bit 6 to 0.

Rev. A | Page 25 of 72

AD9142A

Data Sheet

DLL Configuration Example 1

Use the parity bit to validate the interface timing. As described

previously, the host provides a parity bit with the data samples,

as well as configures the AD9142A to generate an IRQ. The user

can then sweep the sampling instance of the AD9142A input

registers to determine at what point a sampling error occurs.

The sampling instance can be varied in discrete increments by

offsetting the nominal DLL phase shift value of 90° via Register

0x0A[3:0].

In the following DLL configuration example, f_DCI= 500 MHz,

DLL is enabled, and DLL phase offset = 0.

1. 0x5E → 0xFE /* Turn off LSB delay cell*/

2. 0x0D → 0x06 /* Select DLL configure

options */

3. 0x0A → 0xC0 /* Enable DLL and duty cycle

correction. Set DLL phase offset to 0 */

SED OPERATION

4. Read 0x0E[7:4] /* Expect 1000b if the DLL

is locked */

The AD9142A provides on-chip sample error detection (SED)

circuitry that simplifies verification of the input data interface.

The SED compares the input data samples captured at the digital

input pins with a set of comparison values. The comparison values

are loaded into registers through the SPI port. Differences between

the captured values and the comparison values are detected.

Options are available for customizing SED test sequencing and

error handling.

DLL Configuration Example 2

In the following DLL configuration example, f_DCI= 300 MHz,

DLL is enable, and DLL phase offset = 0.

1. 0x5E → 0xFE /* Turn off LSB delay cell*/

2. 0x0D → 0x86 /* Select DLL configure

options */

3. 0x0A → 0xC0 /* Enable DLL and duty cycle

The SED circuitry allows the application to test a short user

defined pattern to confirm that the high speed source

synchronous data bus is correctly implemented and meets the

timing requirement. Unlike the parity bit, the SED circuitry is

expected to be used during initial system calibration, before the

AD9142A is in use in the application. The SED circuitry

operates on a data set made up of user defined input words,

denoted as I0, Q0, I1, and Q1. The user defined pattern consists

of sequential data word samples (I0 is sampled on the rising

edge of DCI, Q0 is sampled on the following falling edge of

DCI, I1 is sampled on the following DCI rising edge, and Q1 is

sampled on the following DCI falling edge). The user loads this

data pattern in the byte format into Register 0x61 through

Register 0x68.

correction. Set DLL phase offset to 0 */

4. Read 0x0E[7:4] /* Expect 1000b if the DLL

is locked */

PARITY

The data interface can be continuously monitored by enabling

the parity bit feature in Register 0x6A, Bit 7 and configuring the

frame/parity bit as parity by setting Register 0x09 to 0x21. In

this case, the host sends a parity bit along with each data

sample. This bit is set according to the following formulas,

where n is the data sample that is being checked.

For even parity,

XOR[FRM(n), D0(n), D1(n), D2(n), ..., D15(n)] = 0

For odd parity,

The depth of the user defined pattern is selectable via Bit 4 in

the SED_CTRL register (0x60), with the default, 0, meaning a

depth of two (using I0 and Q0), and a 1 meaning a depth of four

(using I0, Q0, I1, and Q1, and requiring the use of frame signal

input to define I0 to the SED state machine). To properly align

the input samples using a depth of four, I0 is indicated by

asserting the frame signal for a minimum of two complete input

samples as shown in Figure 37. The frame signal can be issued

once at the start of the data transmission, or it can be asserted

repeatedly at intervals coinciding with the S0 word.

XOR[FRM(n), D0(n), D1(n), D2(n), ..., D15(n)] = 1

The parity bit is calculated over 17 bits (including the

frame/parity bit).

If a parity error occurs, the parity error counter (Register 0x6B

or Register 0x6C) is incremented. Parity errors on the bits

sampled by the rising edge of DCI increments the rising edge

parity counter (Register 0x6B) and set the PARERRRIS bit

(Register 0x6A, Bit 0). Parity errors on the bits sampled by the

falling edge of DCI will increment the falling edge parity counter

(Register 0x6C) and set the PARERRFAL bit (Register 0x6A, Bit 1).

The parity counter continues to accumulate until it is cleared or

until it reaches a maximum value of 255. The count can be

cleared by writing a 1 to Register 0x6A, Bit 5.

FRAME

I

Q

I

Q

I

0

DATA[15:0]

0

1

Figure 37. Timing Diagram of Extended FRAME Signal Required to Align

Input Data for SED

To trigger an IRQ when a parity error occurs, write a 1 to

Register 0x04, Bit 7. This IRQ triggers if there is either a rising

edge or falling edge parity error. The status of the IRQ can be

The SED has three flag bits (Register 0x60, Bit 0, Bit 1, and Bit 2)

that indicate the results of the input sample comparisons. The

sample error detected bit (Register 0x60, Bit 0) is set when an

error is detected and remains set until cleared.

IRQx

observed via Register 0x06, Bit 7 or by using the selected

pin. Clear the IRQ by writing a 1 to Register 0x06, Bit 7.

Rev. A | Page 26 of 72

Data Sheet

AD9142A

The autosample error detection (AED) mode is an autoclear

mode that has two effects: it activates the compare fail bit and

the compare pass bit (Register 0x60, Bit 1 and Bit 2). The

compare pass bit sets if the last comparison indicated that the

sample was error free. The compare fail bit sets if an error is

detected. The compare fail bit is automatically cleared by the

reception of eight consecutive error-free comparisons, when

autoclear mode is enabled.

DELAY LINE INTERFACE MODE

The DLL is designed to help ease the interface timing require-

ments in very high speed data rate applications. The DLL has

a minimum supported interface speed of 250 MHz, as shown

in Table 2. For interface rates lower than this speed, use the

interface delay line. In this mode, the DLL is powered off and a

four-tap delay line is provided for the user to adjust the timing

between the data bus and the DCI. Table 16 specifies the setup

and hold times for each delay tap.

The sample error flag can be configured to trigger an IRQ when

active, if needed. This is done by enabling the appropriate bit in

the event flag register (Register 4, Bit 6).

Table 16. Delay Line Setup and Hold Times (Guaranteed)

Delay Setting

Register 0x5E[7:0]

Register 0x5F[ꢀ:0]

t_S(ns)¹

t_H(ns)

|t_S+ t_H| (ns)

0

1

ꢀ

3

SED EXAMPLE

Normal Operation

0x00

0x60

−0.81

1.96

1.15

0x80

0x67

−0.97

2.20

1.23

0xF0

0x67

−1.13

2.53

1.40

0xFE

0x67

−1.28

2.79

1.51

The following example illustrates the AD9142A SED

configuration sequence for continuously monitoring the input

data and assertion of an IRQ when a single error is detected:

¹The negative sign indicates the direction of the setup time. The setup time is

defined as positive when it is on the left side of the clock edge and negative

when it is on the right side of the clock edge.

1. Write to the following registers to enable the SED and load

the comparison values with a 4-deep user pattern.

Comparison values can be chosen arbitrarily; however,

choosing values that require frequent bit toggling provides

the most robust test.

There is a fixed 1.38 ns delay on the DCI signal when the delay line

is enabled. Each tap adds a nominal delay of 200 ps to the fixed

delay. To achieve the best timing margin, that is, to center the

setup and hold window in the middle of the data eye, the user

may need to add a delay on the data bus with respect to the DCI

in the data source. Figure 38 is an example of calculating the

optimal external delay.

a. Register 0x61[7:0] → I0[7:0]

b. Register 0x62[7:0] → I0[15:8]

c. Register 0x63[7:0] → Q0[7:0]

d. Register 0x64[7:0] → Q0[15:8]

e. Register 0x65[7:0] → I1[7:0]

Register 0x0D, Bit 4 configures the DCI signal coupling settings

for optimal interface performance over the operating frequency

range. It is recommended that this bit be set to 1 (dc-coupled

DCI) in the delay line interface mode.

f. Register 0x66[7:0] → I1[15:8]

g. Register 0x67[7:0] → Q1[7:0]

h. Register 0x68[7:0] → Q1[15:8]

2. Enable SED.

a. Register 0x60 → 0xD0

b. Register 0x60 → 0x90

IRQx

3. Enable the SED error detect flag to assert the

a. Register 0x04[6] = 1

pin.

4. Set up frame parity as the frame signal.

a. Register 0x09 = 0x12

5. Begin transmitting the input data pattern (frame signal) is

also required because the depth of the pattern is 4).

t_DELAY= 0.63ns

t_{DATA PERIOD}= 2.5ns

INPUT DATA [15:0]

WITH OPTIMIZED DELAY

DATA EYE

|t_S| = 1.25ns

|t_H| = 2.51ns

DCI = 200MHz

NO DATA TRANSITION

Figure 38. Example of Interfacing Timing in the Delay Line Interface Mode

Rev. A | Page 27 of 72

AD9142A

Data Sheet

Interface Timing Requirements

SPI Sequence to Enable Delay Line Interface Mode

The following example shows how to calculate the optimal

delay at the data source to achieve the best sampling timing in

the delay line interface mode:

Use the following SPI sequence to enable the delay line interface

mode:

1. 0x5E → 0x00 /* Configure the delay

setting */

•

f

_DCI= 200 MHz

2. 0x5F → 0x60

Delay setting = 0

3. 0x0D → 0x16 /* DC couple DCI */

The shadow area in Figure 38 is the interface setup and hold

time window set to 0. To optimize the interface timing, this

window must be placed in the middle of the data transitions.

Because the input is double data rate, the available data period

is 2.5 ns. Therefore, the optimal data bus delay, with respect to

the DCI at the data source, can be calculated as

4. 0x0A → 0x00 /* Turn off DLL and duty

cycle correction */

t_DATAPERIOD

(|t_S| + | t_H|)

t_DELAY

=

−

=1.38−1.25 = 0.13 ns

2

Rev. A | Page 28 of 72

Data Sheet

AD9142A

FIFO OPERATION

As is described in the Data Interface section, the AD9142A

adopts source synchronous clocking in the data receiver. The

nature of source synchronous clocking is the creation of a

separate clock domain at the receiving device. In the DAC, it is

the DAC clock domain, that is, the DACCLK. Therefore, there

are two clock domains inside of the DAC: the DCI and the

DACCLK. Often, these two clock domains are not synchronous,

requiring an additional stage to adjust the timing for proper data

transfer. In the AD9142A, a FIFO stage is inserted between the

DCI and DACCLK domains to transfer the received data into

the core clock domain (DACCLK) of the DAC.

every time a new word is loaded into the FIFO. Meanwhile, data

is read from the FIFO register, which is determined by the read

pointer, and fed into the digital datapath. The value of the read

pointer is incremented every time data is read into the datapath

from the FIFO. The FIFO pointers are incremented at the data

rate, which is the DACCLK rate divided by the interpolation rate.

Valid data is transmitted through the FIFO as long as the FIFO

does not overflow (full) or underflow (empty). An overflow or

underflow condition occurs when the write pointer and read

pointer point to the same FIFO slot. This simultaneous access of

data leads to unreliable data transfer through the FIFO and must be

avoided.

The AD9142A contains a 2-channel, 16-bit wide, 8-word deep

FIFO. The FIFO acts as a buffer that absorbs timing variations

between the two clock domains. The timing budget between the

two clock domains in the system is significantly relaxed due to

the depth of the FIFO.

Normally, data is written to and read from the FIFO at the same

rate to maintain a constant FIFO depth. If data is written to the

FIFO faster than data is read, the FIFO depth increases. If data

is read from the FIFO faster than data is written to it, the FIFO

depth decreases. For optimal timing margin, maintain the FIFO

depth near half full (a difference of four between the write pointer

and read pointer values). The FIFO depth represents the FIFO

pipeline delay and is part of the overall latency of the AD9142A.

Figure 39 shows the block diagram of the datapath through the

FIFO. The input data is latched into the device, formatted, and

then written into the FIFO register, which is determined by the

FIFO write pointer. The value of the write pointer is incremented

FIFO WRITE CLOCK

FIFO READ CLOCK

DACCLK

I DAC

÷INT

FIFO

I[15:0]

FIFO SLOT 0

I DATA PATH

FIFO SLOT 1

FIFO SLOT 2

FIFO SLOT 3

FIFO SLOT 4

FIFO SLOT 5

FIFO SLOT 6

FIFO SLOT 7

RETIMED DCI

DCI

READ

POINTER

DATA

RECEIVER

DATA

FORMAT

LATCHED

DATA[15:0]

INPUT DATA[15:0]

FRAME

I/Q[31:0]

Q[15:0]

WRITE

POINTER

Q DATA PATH

Q DAC

RESET

LOGIC

SPI FIFO RESET

REG 0x25[0]

FIFO LEVEL

FIFO LEVEL REQUEST

REGISTER 0x23

Figure 39. Block Diagram of FIFO

Rev. A | Page 29 of 72

AD9142A

Data Sheet

RESETTING THE FIFO

SERIAL PORT INITIATED FIFO RESET

Upon power-on of the device, the read and write pointers start

to roll around the FIFO from an arbitrary slot; consequently, the

FIFO depth is unknown. To avoid a concurrent read and write

to the same FIFO address and to assure a fixed pipeline delay

from power-on to power-on, it is important to reset the FIFO

pointers to a known state each time the device powers on or

wakes up. This state is specified in the requested FIFO level

(FIFO depth and FIFO level are used interchangeably in this

data sheet), which consists of two sections: the integer FIFO

level and the fractional FIFO level.

A SPI initiated FIFO reset is the most common method to reset

the FIFO. To initialize the FIFO level through the serial port,

toggle FIFO_SPI_RESET_REQUEST (Register 0x25[0]) from

0 to 1 and back to 0. When the write to this register is complete,

the FIFO level is initialized to the requested FIFO level and the

readback of FIFO_SPI_RESET_ACK (Register 0x25[1]) is set

to 1. The FIFO level readback, in the same format as the FIFO

level request, should be within 1 DACCLK cycle of the

requested level. For example, if the requested value is 0x40 in

4× interpolation, the readback value should be one of the

following: 0x33, 0x40, or 0x41. The range of 1 DACCLK cycle

indicates the default DAC latency uncertainty from power-on

to power-on without turning on synchronization.

The integer FIFO level represents the difference of the states

between the read and write points in the unit of an input data

period (1/f_DATA). The fractional FIFO level represents the

difference of the FIFO pointers that is smaller than the input

data period. The resolution of the fractional FIFO level is the

input data period divided by the interpolation ratio and, thus, it

is equal to one DACCLK cycle.

The recommended procedure for a serial port FIFO reset is as

follows:

1. Configure the DAC in the desired interpolation mode

(Register 0x28[1:0]).

The exact FIFO level, that is, the FIFO latency, can be calculated

by

2. Ensure that the DACCLK and DCI are running and stable

at the clock inputs.

3. Program Register 0x23 to the customized value, if the

desired value is not 0x40.

4. Request the FIFO level reset by setting Register 0x25[0] to 1.

5. Verify that the device acknowledges the request by setting

Register 0x25[1] to 1.

6. Remove the request by setting Register 0x25[0] to 0.

7. Verify that the device drops the acknowledge signal by

setting Register 0x25[1] to 0.

8. Read back Register 0x24 multiple times to verify that the

actual FIFO level is set to the requested level and that the

readback values are stable. By design, the readback is

within 1 DACCLK around the requested level.

FIFO Latency = Integer Level + Fractional Level

Because the FIFO has eight data slots, there are eight possible

FIFO integer levels. The maximum supported interpolation rate

in the AD9142A is 8× interpolation. Therefore, there are eight

possible FIFO fractional levels. Two 3-bit registers in Register 0x23

are assigned to represent the two FIFO levels, as follows:

•

Bits[6:4] represent the FIFO integer level

Bits[2:0] represent the FIFO fractional level.

For example, if the interpolation rate is 4× and the total FIFO

depth is 4.5 input data periods, set the FIFO_LEVEL_CONFIG

(Register 0x23) to 0x42 (4 here means four data cycles and 2

means two DAC cycles, which is half of a data cycle). Note that

there are only four possible fractional levels in the case of 4×

interpolation. Table 17 shows additional examples of configuring

the FIFO level in various interpolation rate modes.

FRAME INITIATED FIFO RESET

The frame input has two functions. One function is to indicate

the beginning of a byte stream in the byte interface mode, as

discussed in the Data Interface section. The other function is

to initialize the FIFO level by asserting the frame signal high

for at least the time interval required to load complete data to

the I and Q DACs. This corresponds to one DCI period in word

interface mode and two DCI periods in byte interface mode.

Note that this requirement of the frame pulse length is longer

than that of the frame signal when it serves only to assemble the

byte stream. The device accepts either a continuous frame or a

one shot frame signal.

Table 17. Examples of FIFO Level Configuration

Interpolation Example FIFO Integer Level

Fractional Level

Rate

Level (1/f_DATA)

(Reg. 0xꢀ3[6:4]) (Reg. 0xꢀ3[ꢀ:0])

2×

4×

8×

3 + 1/2

4 + 1/4

4 + 3/8

3

4

1

3

By default, the FIFO level is 4.0. It can be programmed to any

allowed value from 0.0 to 7.x. The maximum allowed number

for x is the interpolation rate minus 1. For example, in 8×

interpolation, the maximum value allowed for x is 7.

In the continuous reset mode, the FIFO responds to every valid

frame pulse and resets itself. In the one shot reset mode, the

FIFO responds only to the first valid frame pulse after the

FRAME_RESET_MODE bits (Register 0x22[1:0]) are set.

Therefore, even with a continuous frame input, the FIFO resets

one time only; this prevents the FIFO from toggling between

the two states from periodic resets. The one shot frame reset

mode is the default and the recommended mode.

The following two ways are used to reset the FIFO and initialize

the FIFO level:

•

Serial port (SPI) initiated FIFO reset.

Frame initiated FIFO reset.

Rev. A | Page 30 of 72

Data Sheet

AD9142A

The recommended procedure for a frame initiated FIFO reset is

as follows:

Monitoring the FIFO Status

The real-time FIFO status can be monitored from the SPI

Register 0x24 and reflects the real-time FIFO depth after a FIFO

reset. Without timing drifts in the system, this readback does

not change from that which resulted from the FIFO reset. When

there is a timing drift or other abnormal clocking situation, the

FIFO level readback can change. However, as long as the FIFO

does not overflow or underflow, there is no error in data trans-

mission. Three status bits in Register 0x06, Bits[2:0], indicate if

there are FIFO underflows, overflows, or similar situations. The

status of the three bits can be latched and used to trigger

1. Configure the DAC in the desired interpolation mode

(Register 0x28[1:0]).

2. Ensure that the DACCLK and DCI are running and stable at

the clock inputs.

3. Ensure that the DLL is locked (if using DLL mode) or the

DCI clock is being sent properly (if using bypass mode).

Program Register 0x23 to the customized value, if the

desired value is not 0x40.

4. Configure the FRAME_RESET_MODE bits (Register 0x22,

IRQ1

IRQ2

hardware interrupts,

and

. To enable latching and

Bits [1:0]) to 00b.

5. Choose whether to use continuous or one shot mode by

writing 0 or 1 to EN_CON_FRAME_RESET (Register 0x22,

Bit 2).

interrupts, configure the corresponding bits in Register 0x03

and Register 0x04.

6. Toggle the frame input from 0 to 1 and back to 0. The pulse

width needs to be longer than the minimum requirement.

a. If the frame input is a continuous clock, turn on the

signal.

7. Read back Register 0x24 multiple times to verify that the

actual FIFO level is set to the requested level and the

readback values are stable. By design, the readback is

within 1 DACCLK around the requested level.

Rev. A | Page 31 of 72

AD9142A

Data Sheet

DIGITAL DATAPATH

INPUT

DIGITAL GAIN

AND PHASE

AND OFFSET

ADJUSTMENT

POWER

DETECTION

AND

COARSE AND

FINE

MODULATION

INV

SINC

HB1

HB2

HB3

PROTECTION

Figure 40. Block Diagram of Digital Datapath

0.02

The block diagram in Figure 40 shows the functionality of the

digital datapath. The digital processing includes

0

–0.02

–0.04

–0.06

–0.08

–0.10



An input power detection block

Three half-band interpolation filters

A quadrature modulator consisting of a fine resolution

NCO and an f_S/4 coarse modulation block

An inverse sinc filter



A gain and phase and offset adjustment block

The interpolation filters accept I and Q data streams and

process them as two independent data streams, whereas the

quadrature modulator and phase adjustment block accepts I

and Q data streams as a quadrature data stream. Therefore,

quadrature input data is required when digital modulation and

phase adjustment functions are used.

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45

FREQUENCY (Hz)

Figure 41. Pass-Band Detail of 2× Mode

10

0

INTERPOLATION FILTERS

The transmit path contains three interpolation filters. Each of

the three interpolation filters provides a 2× increase in output data

rate and a low-pass function. The half-band (HB) filters are cas-

caded to provide 4× or 8× interpolation ratios.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

The AD9142A provides three interpolation modes (see Table 6).

Each mode offers a different usable signal bandwidth in an

operating mode. Which mode to select depends on the required

signal bandwidth and the DAC update rate. Refer to Table 6 for

the maximum speed and signal bandwidth of each interpolation

mode.

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

The usable bandwidth is defined as the frequency band over

which the filters have a pass-band ripple of less than 0.001 dB

and a stop band rejection of greater than 85 dB.

FREQUENCY (Hz)

Figure 42. All-Band Response of 2× Mode

2× Interpolation Mode

Figure 41 and Figure 42 show the pass-band and all-band filter

response for 2× mode. Note that the transition from the

transition band to the stop band is much sharper than the tran-

sition from the pass band to the transition band. Therefore, when

the desired output signal moves out of the defined pass band,

the signal image, which is supposed to be suppressed by the stop

band, grows faster than the droop of the signal itself due to the

degraded pass-band flatness. In cases where the degraded image

rejection is acceptable or can be compensated by the analog

low-pass filter at the DAC output, it is possible to let the output

signal extend beyond the specified usable signal bandwidth.

Rev. A | Page 32 of 72

Data Sheet

AD9142A

10

0

4× Interpolation Mode

Figure 43 and Figure 44 show the pass-band and all-band filter

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

responses for 4× mode.

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

FREQUENCY (Hz)

Figure 46. All-Band Response of 8× Mode

Table 18. Half-Band Filter 1 Coefficient

Lower Coefficient

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45

FREQUENCY (Hz)

Upper Coefficient

H(55)

H(54)

H(53)

H(52)

H(51)

H(50)

H(49)

H(48)

H(47)

H(46)

H(45)

H(44)

H(43)

H(42)

H(41)

H(40)

H(39)

H(38)

H(37)

H(36)

H(35)

H(34)

H(33)

H(32)

H(31)

H(30)

H(29)

Integer Value

Figure 43. Pass-Band Detail of 4× Mode

H(1)

H(2)

H(3)

H(4)

H(5)

H(6)

H(7)

H(8)

−4

0

+13

0

−32

0

+69

0

−134

0

+239

0

−401

0

+642

0

−994

0

+1512

0

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

H(9)

H(10)

H(11)

H(12)

H(13)

H(14)

H(15)

H(16)

H(17)

H(18)

H(19)

H(20)

H(21)

H(22)

H(23)

H(24)

H(25)

H(26)

H(27)

H(28)

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

FREQUENCY (Hz)

Figure 44. All-Band Response of 4× Mode

8× Interpolation Mode

Figure 45 and Figure 46 show the pass-band and all-band filter

responses for 8× mode. The maximum DAC update rate is 1.6 GHz,

and the maximum input data rate that is supported in this mode is

200 MHz (1.6 GHz/8).

−2307

0

+3665

0

−6638

0

+20,754

+32,768

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45

FREQUENCY (Hz)

Figure 45. Pass-Band Detail of 8× Mode

Rev. A | Page 33 of 72

AD9142A

Data Sheet

I DATA OUT

I DATA IN

Table 19. Half-Band Filter 2 Coefficient

Lower Coefficient

Upper Coefficient

Integer Value

H(1)

H(2)

H(3)

H(4)

H(5)

H(6)

H(7)

H(8)

H(9)

H(10)

H(11)

H(12)

H(23)

H(22)

H(21)

H(20)

H(19)

H(18)

H(17)

H(16)

−2

0

+17

0

−75

0

+238

0

−660

0

+2530

+4096

FTW[31:0]

COSINE

~

SINE

NCO

PHASE[15:0]

Q DATA IN

Q DATA OUT

Figure 47. NCO Modulator Block Diagram

H(15)

H(14)

H(13)

The NCO modulator mixes the carrier signal generated by the

NCO with the I and Q signals. The NCO produces a quadrature

carrier signal to translate the input signal to a new center frequency.

A complex carrier signal is a pair of sinusoidal waveforms of the

same frequency, offset 90° from each other. The frequency of the

complex carrier signal is set via NCO_FTW3 to NCO_FTW0 in

Register 0x31 through Register 0x34.

Table 20. Half-Band Filter 3 Coefficient

Lower Coefficient

Upper Coefficient

Integer Value

The NCO operating frequency, f_NCO, is always equal to f_DAC, the

DACCLK frequency. The frequency of the complex carrier

H(1)

H(2)

H(3)

H(4)

H(5)

H(6)

H(11)

H(10)

H(9)

H(8)

H(7)

+29

0

−214

0

+1209

+2048

signal can be set from dc up to 0.ꢀ ꢁ f_NCO

.

The frequency tuning word (FTW) is in twos complement

format. It can be calculated as

f_DAC

2

f_DAC

2



 f_CARRIER



DIGITAL MODULATION

f_CARRIER

2³²





f_CARRIER 0



The AD9142A provides two modes to modulate the baseband

quadrature signal to the desired DAC output frequency.

FTW 





f_DAC

f_CARRIER

) (2³²)



f_CARRIER 0





Coarse (f_S/4) modulation

Fine (NCO) modulation

FTW  (1

f_DAC

The generated quadrature carrier signal is mixed with the I and

Q data. The quadrature products are then summed into the I

and Q data paths, as shown in Figure 47.

f_S/4 Modulation

The f_S/4 modulation is a convenient and low power modulation

mode to translate the input baseband frequency to a fixed f_S/4

IF frequency, f_Sbeing the DAC sampling rate. When modulation

frequencies other than this frequency are required, the NCO

modulation mode must be used.

Updating the Frequency Tuning Word

The frequency tuning word registers are not updated immediately

upon writing, as are other configuration registers. Similar to

FIFO reset, the NCO update can be triggered in two ways.

NCO Modulation



SPI initiated update

Frame initiated update

The NCO modulation mode makes use of a numerically

controlled oscillator (NCO), a phase shifter, and a complex

modulator to provide a means for modulating the signal by a

programmable carrier signal. A block diagram of the digital

modulator is shown in Figure 47. The NCO modulation allows

the DAC output signal to be placed anywhere in the output

spectrum with very fine frequency resolution.

Rev. A | Page 34 of 72

Data Sheet

AD9142A

Quadrature Gain Adjustment

SPI Initiated Update

Ordinarily, the I and Q channels have the same gain or signal

magnitude. The quadrature gain adjustment is used to balance the

gain between the I and Q channels. The digital gain of the I and Q

channels can be adjusted independently through two 6-bit registers,

IDAC_GAIN_ADJ (Register 0x3F[5:0]) and QDAC_GAIN_ADJ

(Register 0x40[5:0]). The range of the adjustment is [0, 2] or [−∞,

6 dB] with a step size of 2⁻⁵(−30 dB). The default setting is 0x20,

corresponding to a gain equal to 1 or 0 dB.

In the SPI initiated update method, the user simply toggles

Register 0x30[0] (NCO_SPI_UPDATE_REQ) after configuring

the NCO settings. The NCO is updated on the rising edge (from

0 to 1) in this bit. Register 0x30[1] (NCO_SPI_UPDATE_ACK)

goes high when the NCO is updated. A falling edge (from 1 to

0) in Register 0x30[0] clears Bit 1 of Register 0x30 and prepares

the NCO for the next update operation. This update method is

recommended when there is no requirement to align the DAC

output from multiple devices because SPI writes to multiple

devices are asynchronous.

Quadrature Phase Adjustment

Under normal circumstances, I and Q channels have an angle of

precisely 90° between them. The quadrature phase adjustment is

used to change the angle between the I and Q channels.

IQ_PHASE_ADJ_MSB and IQ_PHASE_ADJ_LSB (Register 0x37,

Bits [7:0] and Register 0x38, Bits [4:0]) provide an adjustment

range of 14° with a resolution of 0.0035°. If the original angle is

precisely 90°, setting IQ_PHASE_ADJ_MSB and

IQ_PHASE_ADJ_LSB to 0x0FFF adds approximately 14°

between I and QDAC outputs, creating an angle of 104° between

the channels. Likewise, if the original angle is precisely 90°,

setting IQ_PHASE_ADJ_MSB and IQ_PHASE_ADJ_LSB to

0x1000 adds approximately −14° between the I and QDAC

outputs, creating an angle of 76° between the channels.

Frame Initiated Update

When the DAC output from multiple devices must be well aligned

with NCO turned on, the frame initiated update is recommended.

In this method, the NCOs from multiple devices are updated at

the same time upon the rising edge of the frame signal. To use this

update method, the FRAME_RESET_MODE (Register 0x22[1:0])

must be set in NCO only or FIFO and NCO, depending on

whether a FIFO reset is needed at the same time. The second

step is to ensure that the reset mode is in one shot mode

(EN_CON_FRAME_RESET, Register 0x22[2] = 0). When this

is completed, the NCO waits for a valid frame pulse and updates

the FTW accordingly. The user can verify if the frame pulse is

correctly received by reading Register 0x30[6] (NCO_FRAME_

UPDATE_ACK) wherein a 1 indicates a complete update

operation. See the FIFO Operation section for information to

generate a valid frame pulse.

DC OFFSET ADJUSTMENT

The dc value of the I datapath and the Q datapath can be

controlled independently by adjusting the values in the two

IDAC dc offset 16-bit registers, IDAC_DC_OFFSET_LSB,

IDAC_DC_OFFSET_MSB, QDAC_DC_OFFSET_LSB,

and QDAC_DC_OFFSET_MSB (Register 0x3B through

Register 0x3E). These values are added directly to the datapath

values. Take care not to overrange the transmitted values.

DATAPATH CONFIGURATION

Configuring the AD9142A datapath starts with the following

four parameters:

•

The application requirements of the input data rate

The interpolation ratio

The output signal center frequency

The output signal bandwidth

As shown in Figure 48, the DAC offset current varies as a function

of the I/QDAC dc offset values. Figure 48 shows the nominal

current of the positive node of the DAC output, I_OUTP, when the

digital inputs are fixed at midscale (0x0000, twos complement data

format) and the DAC offset value is swept from 0x0000 to

0xFFFF. Because I_OUTPand I_OUTNare complementary current

outputs, the sum of I_OUTPand I_OUTNis always 20 mA.

Given these four parameters, the first step to configure the datapath

is to verify that the device supports the desired input data rate,

the DAC sampling rate, and the bandwidth requirements. After this

verification, the modes of the interpolation filters can be chosen. If

the output signal center frequency is different from the baseband

input center frequency, additional frequency offset requirements

are determined and applied with on-chip digital modulation.

20

0

15

10

5

DIGITAL QUADRATURE GAIN AND PHASE

ADJUSTMENT

10

15

The digital quadrature gain and phase adjustment function enables

compensation of the gain and phase imbalance of the I and Q

paths caused by analog mismatches between DAC I/Q outputs,

quadrature modulator I/Q baseband inputs, and DAC/modulator

interface I/Q paths. The undesired imbalances cause unwanted

sideband signal to appear at the quadrature modulator output

with significant energy. Tuning the quadrature gain and phase

adjust values optimizes image rejection in single sideband radios.

0

20

0x0000

0x4000

0x8000

0xC000

0xFFFF

DAC OFFSET VALUE

Figure 48. DAC Output Currents vs. DAC Offset Value

Rev. A | Page 35 of 72

AD9142A

Data Sheet

INVERSE SINC FILTER

INPUT SIGNAL POWER DETECTION AND

PROTECTION

The AD9142A provides a digital inverse sinc filter to

compensate for the DAC roll-off over frequency. The inverse sinc

(sinc⁻¹) filter is a seven-tap FIR filter. Figure 49 shows the

frequency response of sin(x)/x roll-off, the inverse sinc filter,

and their composite response. The composite response has less

The input signal power detection and protection function detects

the average power of the DAC input signal and prevents overrange

signals from being passed to the next stage. An overrange DAC

output signal can cause destructive breakdown on power sensitive

devices, such as power amplifiers. The power detection and

protection feature of the AD9142A detects overrange signals in

the DAC. When an overrange signal is detected, the protection

function either attenuates or mutes the signal to protect the

downstream devices from abnormal power surges in the signal.

than ±±.±0 dꢀ pass-band ripple up to a frequency of ±.4 × f_DAC

.

To provide the necessary peaking at the upper end of the pass

band, the inverse sinc filter has an intrinsic insertion loss of about

3.8 dꢀ. The loss of the digital gain can be offset by increasing the

quadrature gain adjustment setting on both the I and Q data paths

to minimize the impact on the output signal-to-noise ratio. How-

ever, care is needed to ensure that the additional digital gain does

not cause signal saturation, especially at high output frequencies.

The sinc⁻¹filter is disabled by default; it can be enabled by setting

the INVSINC_ENAꢀLE bit to 1 in Register ±x27[7]).

1

Figure 0± shows the block diagram of the power detection and

protection function. The protection block is at the very last stage of

the data path and the detection block uses a separate path from

the data path. The design of the detection block guarantees that

the worst-case latency of power detecting is shorter than that of

the data path. This ensures that the protection circuit initiates

before the overrange signal reaches the analog DAC core.

0

–1

–2

–3

–4

–5

The sum of I²and Q²is calculated as a representation of the

input signal power. Only the upper six MSꢀs, D[10:1±], of data

samples are used in the calculation; consequently, samples whose

power is 36 dꢀ below the full-scale peak power are not detected.

The calculated sample power numbers accumulate through a

moving average filter. Its output is the average of the input

signal power in a certain number of data clock cycles. The length

of the filter is configurable through the

SAMPLE_WINDOW_LENGTH (Register ±x2ꢀ[3:±]). To

determine whether the input average power is over range,

the device averages the power of the samples in the filter

and compares the average power with a user defined

threshold, THRESHOLD_LEVEL_REQUEST_LSꢀ and

THRESHOLD_LEVEL_REQUEST_MSꢀ (Register ±x29[7:±]

and Register ±x2A[4:±]). When the output of the averaging filter

is larger than the threshold, the DAC output is either attenuated or

muted.

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

FREQUENCY (Hz)

Figure 49. Responses of sin(x)/x Roll Off (Blue), the Sinc⁻¹Filter (Red), and

Composite of Both (Black)

Table 21. Inverse Sinc Filter

Lower Coefficient

Upper Coefficient

Integer Value

H(1)

H(2)

H(3)

H(4)

H(7)

H(6)

H(5)

−1

+4

−16

+192

The appropriate filter length and average power threshold for

effective protection are application dependent. It is recommended

that experiments be performed with real-world vectors to

determine the values of these parameters.

POWER

SIGNAL

PROCESSING

ENGINE

PROTECTION

(ATTENUATE

OR MUTE)

DAC

CORE

FIFO

POWER DETECTION

AVG POWER

2

+ Q

I

REG 0x2C[7:0] AND

REG 0x2D[4:0]

AVERAGING

FILTER

FILTER LENGTH USER DEFINED THRESHOLD

SETTINGS

REG 0x2B[3:0]

REG 0x29[7:0] AND

REG 0x2A[4:0]

Figure 50. Block Diagram of Input Signal Power Detection and Protection Function

Rev. A | Page 36 of 72

Data Sheet

AD9142A

DIGITAL FUNCTION CONFIGURATION

TRANSMIT ENABLE FUNCTION

Each of the digital gain and phase adjust functions and the

inverse sinc filter can be enabled and adjusted independently.

The pipeline latencies these blocks add into the data path are

different between enabled and disabled. If fixed DAC pipeline

latency is desired during operation, leave these functions always

on or always off after initial configuration.

The transmit enable (TXEN) function provides the user with a

hardware switch of the DAC output. The function accepts a

CMOS signal via Pin 6 (TXEN). When this signal is detected

high, the transmit path is enabled and the DAC transmits the

data normally. When this signal is detected low, one of the three

actions related to the DAC output is triggered. This can be

configured in Register 0x43.

The digital dc adjust function is always on. The default value is

0; that is, there is no additional dc offset. The pipeline latency that

this block adds is a constant, no matter the value of the dc

offset.

1. The DAC output is gradually attenuated from full scale gain

to 0. The attenuation step size is set in Register 0x42[5:0].

2. The DAC is put in sleep mode and the output current is

turned off. Other areas of the DAC are still running in this

mode.

3. The DAC is put in power-down mode. In this mode, not

only the DAC output current is turned off but the rest of

the DAC is powered down. This minimizes the power

consumption of the DAC when the data is not transmitting

but it takes a bit longer than the first two modes to start to

retransmit data due to the device power-up time.

There is also a latency difference between using and not using

the input signal power detection and protection function.

Therefore, to keep the overall latency fixed, leave this function

always on or always off after the initial configuration.

The TXEN function also provides a gain ramp-up function that

lets the user turn on the DAC output gradually when the TXEN

signal switches from low to high. The ramp-up gain step can be

configured using Register 0x41[5:0].

Rev. A | Page 37 of 72

AD9142A

Data Sheet

MULTIDEVICE SYNCHRONIZATION AND FIXED LATENCY

The better the alignment of the DCI signals, the smaller is the

overall skew between two DAC outputs.

A DAC introduces a variation of pipeline latency to a system.

The latency variation causes the phase of a DAC output to vary

from power-on to power-on. Therefore, the output from

different DAC devices may not be perfectly aligned even with

well aligned clocks and digital inputs. The skew between

multiple DAC outputs varies from power-on to power-on.

FURTHER REDUCING THE LATENCY VARIATION

For applications that require finer synchronization accuracy

(DAC latency variation < 2 DAC clock cycles), the AD9142A

has a provision for enabling multiple devices to be synchronized

to each other within a single DAC clock cycle.

In applications such as transmit diversity or digital predistortion,

where deterministic latency is desired, the variation of the

pipeline latency must be minimized. Deterministic latency in

this data sheet is defined as a fixed time delay from the digital

input to the analog output in a DAC from power-on to power-on.

Multiple DAC devices are considered synchronized to each other

when each DAC in this group has the same constant latency

from power-on to power-on. Three conditions must be identical in

all of the ready-to-sync devices before these devices are

considered synchronized:

To further reduce the latency variation in the DAC, the

synchronization machine needs to be turned on and two

external clocks (frame and sync) need to be generated in the

system and fed to all the DAC devices.

Set Up and Hold Timing Requirement

The sync clock (f_SYNC) serves as a reference clock in the system

to reset the clock generation circuitry in multiple AD9142A

devices simultaneously. Inside the DAC, the sync clock is

sampled by the DACCLK to generate a reference point for

aligning the internal clocks, so there is a setup and hold timing

requirement between the sync clock and the DAC clock.

•

The phase of DAC internal clocks

The FIFO level

The alignment of the input data

If the user adopts the continuous frame reset mode, that is, the

FIFO and sync engine periodically reset, the timing requirements

between the sync clock and the DAC clock must be met.

Otherwise, the device can lose lock and corrupt the output. In

the one shot frame reset mode, it is still recommended that this

timing be met at the time when the sync routine is run because

not meeting the timing can degrade the sync alignment

accuracy by one DAC cycle, as shown in Table 22.

VERY SMALL INHERENT LATENCY VARIATION

The innovative architecture of the AD9142A minimizes the

inherent latency variation. The worst-case variation in the

AD9142A is two DAC clock cycles. For example, in the case of a

1.5 GHz sample rate, the variation is less than 1.4 ns in any

scenario. Therefore, without turning on the synchronization

engine, the DAC outputs from multiple AD9142A devices are

guaranteed to be aligned within two DAC clock cycles, regardless

of the timing between the DCI and the DACCLK. No additional

clocks are required to achieve this accuracy. The user must reset

the FIFO in each DAC device through the SPI at startup.

Therefore, the AD9142A can decrease the complexity of system

design in multitransmit channel applications.

For users who want to synchronize the device in a one-shot

manner and continue to monitor the synchronization status,

the AD9142A provides a sync monitoring mode. It provides a

continuous sync and frame clock to synchronize the part once

and ignore the clock cycles after the first valid frame pulse is

detected. In this way, the user can monitor the sync status

without periodically resynchronizing the device; to engage the

sync monitoring mode, set Register 0x22[1:0] (FRAME_RESET_

MODE) to 11b.

Note the alignment of the DCI signals in the design. The DCI is

used as a reference in the AD9142A design to align the FIFO

and the phase of internal clocks in multiple devices. The

achieved DAC output alignment depends on how well the DCI

signals are aligned at the input of each device. The following

equation is the expression of the worst-case DAC output

alignment accuracy in the case of DCI signal mismatches.

Table 22. Sync Clock and DAC Clock Setup and Hold Times

Falling Edge Sync Timing (default)

Max (ps)

t_S(ns)

t_H(ns)¹

324

−92

t

_{SK (OUT)}= t_{SK (DCI)}+ 2/f_DAC

where:

_{SK (OUT)}is the worst-case skew between the DAC output from

two AD9142A devices.

_{SK (DCI)}is the skew between two DCI signals at the DCI input of

the two AD9142A devices.

_DACis the DACCLK frequency.

|t_S+ t_H| (ns)

232

¹The negative sign indicates the direction of the setup time. The setup time is

defined as positive when it is on the left side of the clock edge and negative

when it is on the right side of the clock edge.

t

f

Rev. A | Page 38 of 72

Data Sheet

AD9142A

Synchronization Procedure for PLL Off

SYNCHRONIZATION IMPLEMENTATION

1. Configure the DAC interpolation mode and, if NCO is

used, configure the NCO FTW.

2. Set up the DAC data interface according to the procedure

outlined in the Data Interface section and verify that the

DLL is locked.

The AD9142A lets the user choose either the rising or falling

edge of the DAC clock to sample the sync clock, which makes it

easier to meet the timing requirements. Ensure that the sync

clock, f_SYNC, is 1/8 × f_DATAor slower by a factor of 2n, n being an

integer (1, 2, 3…). Note that there is a limit on how slow the

sync clock can be received because of the ac coupling nature of

the sync clock receiver. Choose an appropriate value of the ac

coupling capacitors to ensure that the signal swing meets the

data sheet specification, as listed in Table 2.

3. Choose the appropriate mode in the FRAME_RESET_MODE

bits (Register 0x22[1:0]).

a. If NCO is not used, choose FIFO only mode.

b. If NCO is used, it must be synchronized. FIFO and

NCO mode can then be used.

The frame clock resets the FIFO in multiple AD9142A devices.

The frame can be either a one shot or continuous clock. In either

case, the pulse width of the frame must be longer than one DCI

cycle in the word interface mode and two DCI cycles in the byte

4. Configure Bit 2 in Register 0x22 for continuous or one shot

reset mode. One shot reset mode is recommended.

5. Ensure that the DACCLK, DCI, and sync clock to all of the

AD9142A devices are running and stable.

6. Enable the sync engine by writing 1 to Register 0x21[0].

7. Send a valid frame pulse(s) to all of the AD9142A devices.

8. Verify that the frame pulse is received by each device by

reading back Register 0x22[3]. All the readback values are 1.

At this point, the devices should be synchronized.

interface mode. When the frame is a continuous clock, f_FRAME

,

ensure that it is 1/8 × f_DATAor slower by a factor of 2n, n being

an integer (1, 2, 3…). Table 23 lists the requirements of the

frame clock in various conditions. Byte interface mode is not

supported when the frame signal is used in synchronization.

Table 23. Frame Clock Speed and Pulse Width Requirement

Synchronization Procedure for PLL On

Maximum

Note that, because the sync clock and PLL reference clock share

the same clock and the maximum sync clock rate is f_DATA/8, the

same limit also applies to the reference clock. Therefore, only

2× interpolation is supported for synchronization with PLL on.

Sync Clock Speed

Minimum Pulse Width

One Shot

N/A¹

For both one shot and continuous

sync clocks, word interface mode =

one DCI cycle and byte interface

mode = two DCI cycles.

Continuous f_DATA/8

1. Set up the PLL according to the procedure in the Clock

Multiplication section and ensure that the PLL is locked.

2. Configure the DAC interpolation mode and, if NCO is

used, configure the NCO FTW.

3. Set up the DAC data interface according to the procedure

in the Data Interface section and verify that the DLL is

locked.

¹N/A means not applicable.

SYNCHRONIZATION PROCEDURES

When the sync accuracy of an application is less precise than

two DAC clock cycles, it is recommended to turn off the synchro-

nization machine because there are no additional steps required,

other than the regular start-up procedure sequence.

4. Choose the appropriate mode in the FRAME_RESET_MODE

bits (Register 0x22[1:0])

For applications that require more precise sync accuracy than

two DAC clock cycles, it is recommended that the procedure in

the Synchronization Procedure for PLL Off or Synchronization

Procedure for PLL On sections be followed to set up the system

and configure the device. For more information about the

details of the synchronization scheme in the AD9142A and

using the synchronization function to correct system skews and

drifts, see the DAC Latency and System Skews section.

a. If NCO is not used, choose the FIFO only mode.

b. If NCO is used, it must be synchronized. FIFO and

NCO mode can then be used.

5. Configure Bit 2 in Register 0x22 for continuous or one shot

reset mode. One shot reset mode is recommended.

6. Ensure that DACCLK, DCI, and sync clock to all of the

AD9142A devices are running.

7. Enable the sync engine by writing 1 to Register 0x21[0].

8. Send a valid frame pulse(s) to all of the AD9142A devices.

9. Verify that the frame pulse is received by each device by

reading back Register 0x22[3]. All the readback values are 1.

At this point, the devices should be synchronized.

Rev. A | Page 39 of 72

AD9142A

Data Sheet

INTERRUPT REQUEST OPERATION

The AD9142A provides an interrupt request output signal on

method is by writing 1 to the corresponding event flag bit. The

second method is to use a hardware or software reset to clear the

INTERRUPT_SOURCE signal.

IRQ2

Pin 50 and Pin 51 (

IRQ1

and

, respectively) that can be used

to notify an external host processor of significant device events.

Upon assertion of the interrupt, query the device to determine

IRQ2

IRQ1

circuitry.

The

Any one or multiple event flags can be enabled to trigger the

IRQ1 IRQ2

circuitry works in the same way as the

IRQ1

the precise event that occurred. The

pin is an open-drain,

IRQ1

active low output. Pull the

pin high external to the device.

and

pins. The user can select one or both hardware

This pin can be tied to the interrupt pins of other devices with

open-drain outputs to wire-OR these pins together.

interrupt pins for the enabled event flags. Register 0x07 and

Register 0x08 determine the pin to which each event flag is

IRQ1

routed. Set Register 0x07 and Register 0x08 to 0 for

IRQ2

and set

Ten event flags provide visibility into the device. These flags are

located in the two event flag registers, Register 0x05 and

Register 0x06. The behavior of each event flag is independently

selected in the interrupt enable registers, Register 0x03 and

Register 0x04. When the flag interrupt enable is active, the event

flag latches and triggers an external interrupt. When the flag

interrupt is disabled, the event flag monitors the source signal,

these registers to 1 for

.

INTERRUPT SERVICE ROUTINE

Interrupt request management starts by selecting the set of

event flags that require host intervention or monitoring. Enable

the events that require host action so that the host is notified

when they occur. For events requiring host intervention upon

IRQ1

IRQ2

but the

and

pins remain inactive.

IRQx

request:

activation, run the following routine to clear an interrupt

INTERRUPT WORKING MECHANISM

Figure 51 shows the interrupt related circuitry and how the event

1. Read the status of the event flag bits that are being

monitored.

IRQx

flag signals propagate to the

output. The INTERRUPT_

ENABLE signal represents one bit from the interrupt enable

register. The EVENT_FLAG_SOURCE signal represents one bit

from the event flag register. The EVENT_FLAG_SOURCE signal

represents one of the device signals that can be monitored, such as

the PLL_LOCK signal from the PLL phase detector or the

FIFO_WARNING_1 signal from the FIFO controller.

2. Set the interrupt enable bit low so that the unlatched

EVENT_FLAG_SOURCE signal can be monitored directly.

3. Perform any actions that may be required to clear the

EVENT_FLAG_SOURCE signal. In many cases, no

specific actions may be required.

4. Read the event flag to verify that the actions taken have

When an interrupt enable bit is set high, the corresponding event

flag bit reflects a positively tripped version of the EVENT_FLAG_

SOURCE signal; that is, the event flag bit is latched on the rising

edge of the EVENT_FLAG_SOURCE signal. This signal also

cleared the EVENT_FLAG_SOURCE signal.

5. Clear the interrupt by writing 1 to the event flag bit.

6. Set the interrupt enable bits of the events to be monitored.

Note that some EVENT_FLAG_SOURCE signals are latched

signals. These signals are cleared by writing to the correspon-

ding event flag bit. For more information about each of the

event flags, see the Device Configuration Register Map section.

IRQ

asserts the external

pins.

When an interrupt enable bit is set low, the event flag bit reflects

the present status of the EVENT_FLAG_SOURCE signal, and

IRQ

the event flag has no effect on the external

pins.

Clear the latched version of an event flag (the INTERRUPT_

SOURCE signal) in one of two ways. The recommended

0

1

EVENT_FLAG

IRQ

INTERRUPT_

SOURCE

INTERRUPT_ENABLE

OTHER

INTERRUPT

SOURCES

EVENT_FLAG_SOURCE

WRITE_1_TO_EVENT_FLAG

DEVICE_RESET

IRQ

Figure 51. Simplified Schematic of

Circuitry

Rev. A | Page 40 of 72

Data Sheet

AD9142A

TEMPERATURE SENSOR

The AD9142A has a diode-based temperature sensor for

measuring the temperature of the die. The temperature reading

is accessed using Register 0x1D and Register 0x1E. The

temperature of the die can be calculated as

Estimates of the ambient temperature can be made if the power

dissipation of the device is known. For example, if the device

power dissipation is 800 mW and the measured die temperature

is 50°C, then the ambient temperature can be calculated as

T_A= T_DIE– P_D× θ_JA= 50 – 0.8 × 20.7 = 33.4°C

( DieTemp[15:0]− 41,237)

T_DIE

=

where:

106

T_Ais the ambient temperature in degrees Celsius.

where T_DIEis the die temperature in degrees Celsius.

T

_DIEis the die temperature in degrees Celsius.

P_Dis power consumption of the device.

_JAis the thermal resistance from junction to ambient of the

The temperature accuracy is 7°C typical over the +85°C to

−40°C range with one point temperature calibration against a

known temperature. A typical plot of the die temperature code

readback vs. die temperature is shown in Figure 52.

θ

AD9142A as shown in Table 8.

To use the temperature sensor, it must be enabled by setting

Register 0x1C[0] to 1. In addition, to obtain accurate readings,

set the die temperature control register (Register 0x1C) to 0x03.

51000

49000

47000

45000

43000

41000

39000

37000

35000

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE (°C)

Figure 52. Die Temperature Code Readback vs. Die Temperature

Rev. A | Page 41 of 72

AD9142A

Data Sheet

DAC INPUT CLOCK CONFIGURATIONS

The AD9142A DAC sample clock (DACCLK) can be sourced

directly or by clock multiplying. Clock multiplying employs the

on-chip PLL that accepts a reference clock operating at a

submultiple of the desired DACCLK rate. The PLL then

multiplies the reference clock up to the desired DACCLK

frequency, which can then be used to generate all of the internal

clocks required by the DAC. The clock multiplier provides a

high quality clock that meets the performance requirements of

most applications. Using the on-chip clock multiplier removes

the burden of generating and distributing the high speed DACCLK.

DIRECT CLOCKING

Direct clocking with a low noise clock produces the lowest noise

spectral density at the DAC outputs. To select the differential

CLK inputs as the source for the DAC sampling clock, set the

PLL enable bit (Register 0x12[7]) to 0. This powers down the

internal PLL clock multiplier and selects the input from the

DACCLKP and DACCLKN pins as the source for the internal

DAC sampling clock. The REFCLKx input can remain floating.

The device also has clock duty cycle correction circuitry and

differential input level correction circuitry. Enabling these circuits

can provide improved performance in some cases. The control

bits for these functions are in Register 0x10 and Register 0x11.

The second mode bypasses the clock multiplier circuitry and lets

DACCLK be sourced directly to the DAC core. This mode lets the

user source a very high quality clock directly to the DAC core.

CLOCK MULTIPLICATION

DRIVING THE DACCLK AND REFCLK INPUTS

The on-chip PLL clock multiplier circuit generates the DAC

sample rate clock from a lower frequency reference clock. When

the PLL enable bit (Register 0x12[7]) is set to 1, the clock

multiplication circuit generates the DAC sampling clock from

the lower rate REFx/SYNCx input and the DACCLKx input is

left floating. The functional diagram of the clock multiplier is

shown in Figure 54.

The DACCLKx and REFx/SYNCx differential inputs share

similar clock receiver input circuitry. Figure 53 shows a simplified

circuit diagram of the input. The on-chip clock receiver has a

differential input impedance of about 10 kΩ. It is self biased to a

common-mode voltage of about 1.25 V. The inputs can be

driven by differential PECL or LVDS drivers with ac coupling

between the clock source and the receiver.

The clock multiplier circuit operates such that the VCO outputs

a frequency, f_VCO, equal to the REFx/SYNCx input signal

frequency multiplied by N1 × N0. N1 is the divide ratio of the

loop divider; N0 is the divide ratio of the VCO divider.

RECOMMENDED

EXTERNAL

CIRCUITRY

AD9142A

DACCLKP/

REFP/SYNCP

1~100nF

5kΩ

f

_VCO= f_REFCLK× (N1 × N0)

The DAC sample clock frequency, f_DACCLK, is equal to

_DACCLK= f_REFCLK× N1

100Ω

1.25V

5kΩ

1~100nF

f

DACCLKN/

REFN/SYNCN

The output frequency of the VCO must be chosen to keep f_VCO

in the optimal operating range of 1.03 GHz to 2.07 GHz. It is

important to select a frequency of the reference clock and values

of N1 and N0 so that the desired DACCLK frequency can be

synthesized and the VCO output frequency is in the correct range.

Figure 53. Clock Receiver Input Simplified Equivalent Circuit

The minimum input drive level to the differential clock input is

100 mV p-p differential. The optimal performance is achieved

when the clock input signal is between 800 mV p-p differential

and 1.6 V p-p differential. Whether using the on-chip clock

multiplier or sourcing the DACCLK directly, the input clock

signal to the device must have low jitter and fast edge rates to

optimize the DAC noise performance.

VCO CONTROL

VOLTAGE

ADC

PLL CHARGE

REG 0x16[3:0]

PUMP CURRENT PLL LOOP BW

REFP/SYNCP

(PIN 2)

REG 0x14[4:0]

REG 0x14[7:5]

PHASE

FREQUENCY

DETECTION

CHARGE

PUMP

ON-CHIP

LOOP FILTER

VCO

(1GHz~2.1GHz)

REFN/SYNCN

(PIN 3)

LOOP DIVIDER

REG 0x15[1:0]

VCO DIVIDER

REG 0x15[3:2]

DIVIDE BY

2, 4, 8, OR 16

DIVIDE BY

1, 2, OR 4

DACCLKN

(PIN 62)

DACCLK

DACCLKP

(PIN 61)

PLL ENABLE

REG 0x12[7]

Figure 54. PLL Clock Multiplication Circuit

Rev. A | Page 42 of 72

Data Sheet

AD9142A

61

57

53

49

45

41

37

33

29

25

21

17

13

9

PLL SETTINGS

The PLL circuitry requires three settings to be programmed to

their nominal values. The PLL values shown in Table 24 are the

recommended settings for these parameters.

Table 24. PLL Settings

Register

Address

Optimal Setting

(Binary)

PLL SPI Control Register

PLL Loop Bandwidth

PLL Charge Pump Current

PLL Cross Point Control Enable

0x14[7:5]

0x14[4:0]

0x15[4]

111

00111

0

5

1

950

1150

1350

1550

1750

1950

2150

CONFIGURING THE VCO TUNING BAND

VCO FREQUENCY (MHz)

The PLL VCO has a valid operating range from approximately

1.03 GHz to 2.07 GHz covered in 64 overlapping frequency

bands. For any desired VCO output frequency, there may be

several valid PLL band select values. The frequency bands of a

typical device are shown in Figure 55. Device-to-device

variations and operating temperature affect the actual band

frequency range. Therefore, it is required that the optimal PLL

band select value be determined for each individual device.

Figure 55. PLL Lock Range for a Typical Device

MANUAL VCO BAND SELECT

The device includes a manual band select mode (PLL auto

manual enable, Register 0x12[6] = 1) that lets the user select the

VCO tuning band. In manual mode, the VCO band is set

directly with the value written to the manual VCO band bits

(Register 0x12[5:0]).

PLL ENABLE SEQUENCE

AUTOMATIC VCO BAND SELECT

To enable the PLL in automatic or manual mode properly, the

following sequence must be followed:

The device has an automatic VCO band select feature on chip.

Using the automatic VCO band select feature is a simple and

reliable method of configuring the VCO frequency band. This

feature is enabled by starting the PLL in manual mode, and then

placing the PLL in autoband select mode by setting Register 0x12

to a value of 0xC0 and then to a value of 0x80. When these

values are written, the device executes an automated routine

that determines the optimal VCO band setting for the device.

Automatic Mode Sequence

4. Configure the loop divider and the VCO divider registers

for the desired divide ratios.

5. Set 00111b to PLL charge pump current and 111b to PLL loop

bandwidth for the best performance. Register 0x14 = 0xE7

(default).

The setting selected by the device ensures that the PLL remains

locked over the full −40°C to +85°C operating temperature

range of the device without further adjustment. The PLL

remains locked over the full temperature range even if the

temperature during initialization is at one of the temperature

extremes.

6. Set the PLL mode to manual using Register 0x12[6] = 1.

7. Enable the PLL using Register 0x12[7] = 1.

8. Set the PLL mode to automatic using Register 0x12[6] = 0.

Manual Mode

1. Configure the loop divider and the VCO divider registers

for the desired divide ratios.

2. Set 00111b to PLL charge pump current and 111 to PLL loop

bandwidth for the best performance. Register 0x14 = 0xE7

(default).

3. Select the desired band using Register 0x12[5:0].

4. Set the PLL mode to manual using Register 0x12[6] = 1.

5. Enable the PLL using Register 0x12[7] = 1.

Rev. A | Page 43 of 72

AD9142A

Data Sheet

ANALOG OUTPUTS

For nominal values of V_REF(1.2 V), R_SET(10 kΩ), and DAC gain

(512), the full-scale current of the DAC is typically 20 mA. The

DAC full-scale current can be adjusted from 8.64 mA to 31.68 mA

by setting the DAC gain parameter, as shown in Figure 57.

35

TRANSMIT DAC OPERATION

Figure 56 shows a simplified block diagram of the transmit path

DACs. The DAC core consists of a current source array, a switch

core, digital control logic, and full-scale output current control.

The DAC full-scale output current (I_OUTFS) is nominally 20 mA.

The output currents from the IOUT1P/IOUT2P and IOUT1N/

IOUT2N pins are complementary, meaning that the sum of the

two currents always equals the full-scale current of the DAC.

The digital input code to the DAC determines the effective

differential current delivered to the load.

30

25

20

15

10

5

I DAC FS ADJUST

REG 0x18, REG 0x19

1.2V

IOUT1P

IOUT1N

I DAC

5kΩ

VREF

CURRENT

SCALING

0.1µF

FSADJ

10kΩ

SET

IOUT2N

IOUT2P

0

R

Q DAC

0

200

400

600

800

1000

Q DAC FS ADJUST

REG 0x1A, REG 0x1B

DAC GAIN CODE

Figure 57. DAC Full-Scale Current vs. DAC Gain Code

Figure 56. Simplified Block Diagram of DAC Core

Transmit DAC Transfer Function

The DAC has a 1.2 V band gap reference with an output imped-

ance of 5 kΩ. The reference output voltage appears on the VREF

pin. When using the internal reference, decouple the VREF pin

to AVSS with a 0.1 μF capacitor. Use the internal reference only

for external circuits that draw dc currents of 2 μA or less. For

dynamic loads or static loads greater than 2 μA, buffer the VREF

pin. If desired, the internal reference can be overdriven by

applying an external reference (from 1.10 V to 1.30 V) to the

VREF pin.

The output currents from the IOUT1P/IOUT2P and IOUT1N/

IOUT2N pins are complementary, meaning that the sum of the

two currents always equals the full-scale current of the DAC. The

digital input code to the DAC determines the effective differen-

tial current delivered to the load. IOUT1P/IOUT2P provide

maximum output current when all bits are high. The output

currents vs. DACCODE for the DAC outputs is expressed as

DACCODE





(1)

(2)

I_OUTP



 I_OUTFS

2^N









A 10 kΩ external resistor, R_SET, must be connected from the

FSADJ pin to AVSS. This resistor, together with the reference

control amplifier, sets up the correct internal bias currents for

the DAC. Because the full-scale current is inversely proportional to

this resistor, the tolerance of R_SETis reflected in the full-scale

output amplitude.

I

_OUTN= I_OUTFS– I_OUTP

where DACCODE = 0 to 2^N− 1.

Transmit DAC Output Configurations

The optimum noise and distortion performance of the

AD9142A is realized when it is configured for differential

operation. The common-mode rejection of a transformer or

The full-scale current equation, where the DAC gain is

individually set for the Q and I DACs in Register 0x40 and

Register 0x44, respectively, is as follows:

differential amplifier significantly reduces the common-mode error

sources of the DAC outputs. These common-mode error sources

include even-order distortion products and noise. The

enhancement in distortion performance becomes more significant

as the frequency content of the reconstructed waveform

increases and/or its amplitude increases. This is due to the first-

order cancellation of various dynamic common-mode

distortion mechanisms, digital feedthrough, and noise.

V_REF

R_SET

3

16



















I_FS



 72 

 DAC gain







Rev. A | Page 44 of 72

Data Sheet

AD9142A

Figure 58 shows the most basic DAC output circuitry. A pair of

resistors, R_O, converts each of the complementary output currents

to a differential voltage output, V_OUT. Because the current

outputs of the DAC are high impedance, the differential driving

point impedance of the DAC outputs, R_OUT, is equal to 2 × R_O.

See Figure 59 for the output voltage waveforms.

AD9142A

ADL537x

67

IOUT1P

IBBP

RBIP

50Ω

RLI

100Ω

RBIN

50Ω

66

59

IOUT1N

IOUT2N

IBBN

V

+

IP

IOUT1P

QBBN

RBQN

R

O

50Ω

RLQ

100Ω

V

OUTI

–

RBQP

50Ω

58

R

V

IOUT2P

QBBP

IN

IOUT1N

Figure 60. Typical Interface Circuitry Between the AD9142A and the ADL537x

Family of Modulators

V

+

QP

IOUT2P

The baseband inputs of the ADL537x family require a dc bias

of 500 mV. The nominal midscale output current on each output of

the DAC is 10 mA (one-half the full-scale current). Therefore,

a single 50 Ω resistor to ground from each of the DAC outputs

results in the desired 500 mV dc common-mode bias for the

inputs to the ADL537x. The addition of the load resistor in

parallel with the modulator inputs reduces the signal level. The

peak-to-peak voltage swing of the transmitted signal is

R

O

V

OUTQ

–

R

V

QN

IOUT2N

Figure 58. Basic Transmit DAC Output Circuit

+V

PEAK

(2R_BR_L)

V_SIGNAL I_FS

V

CM

0

(2R_B R_L)

V

P

N

Baseband Filter Implementation

Most applications require a baseband anti-imaging filter between

the DAC and the modulator to filter out Nyquist images and

broadband DAC noise. The filter can be inserted between the

I-V resistors at the DAC output and the signal level setting resistor

across the modulator input. This configuration establishes the

input and output impedances for the filter.

V

OUT

–V

PEAK

Figure 61 shows a fifth-order, low-pass filter. A common-mode

choke is placed between the I-V resistors and the remainder of

the filter to remove the common-mode signal produced by the

DAC and to prevent the common-mode signal from being

converted to a differential signal, which can appear as unwanted

spurious signals in the output spectrum. Splitting the first filter

capacitor into two and grounding the center point creates a

common-mode low-pass filter, which provides additional

common-mode rejection of high frequency signals. A purely

differential filter can pass common-mode signals.

Figure 59. Output Voltage Waveforms

The common-mode signal voltage, V_CM, is calculated as

I_FS

2

V_CM



 R_O

The peak output voltage, V_PEAK, is calculated as

_PEAK= I_FS× R_O

V

In this circuit configuration, the single-ended peak voltage is

the same as the peak differential output voltage.

INTERFACING TO MODULATORS

For more details about interfacing the AD9142A DAC to an

IQ modulator, refer to the Circuits from the Lab™ Circuit Note

CN-0205, Interfacing the ADL5375 I/Q Modulator to the AD9122

Dual Channel, 1.2 GSPS High Speed DAC on the Analog Devices

website.

The AD9142A interfaces to the ADL537x family of modulators

with a minimal number of components. An example of the

recommended interface circuitry is shown in Figure 60.

22pF

50Ω

3pF

33nH

3.6pF

6pF

3pF

140Ω ADL537x

AD9142A

33nH

50Ω

22pF

Figure 61. DAC Modulator Interface with Fifth-Order, Low-Pass Filter

Rev. A | Page 45 of 72

AD9142A

Data Sheet

(Register 0x37 and Register 0x38) and the DAC FS adjust

REDUCING LO LEAKAGE AND UNWANTED

SIDEBANDS

registers (Register 0x18 through Register 0x1B) can be used to

calibrate the I and Q transmit paths to optimize sideband

suppression.

Analog quadrature modulators can introduce unwanted signals

at the local oscillator (LO) frequency due to dc offset voltages in

the I and Q baseband inputs, as well as feedthrough paths from

the LO input to the output. The LO feedthrough can be nulled

by applying the correct dc offset voltages at the DAC output

using the digital dc offset adjustments (Register 0x3B through

Register 0x3E).

For more information about suppressing LO leakage and

sideband image, refer to the AN-1039 Application Note,

Correcting Imperfections in IQ Modulators to Improve RF Signal

Fidelity and the AN-1100 Application Note, Wireless Transmitter

IQ Balance and Sideband Suppression from the Analog Devices

website.

Effective sideband suppression requires both gain and phase

matching of the I and Q signals. The I/Q phase adjust registers

Rev. A | Page 46 of 72

Data Sheet

AD9142A

EXAMPLE START-UP ROUTINE

To ensure reliable startup of the AD9142A, certain sequences

must be followed.

0x33 → 0xAA

0x34 → 0x2A

0x30 → 0x01

DEVICE CONFIGURATION AND START-UP

SEQUENCE 1

Read 0x30[1] /* Expect 1b if the NCO update is

complete */

1. Set f_DCI= 375 MHz, f_OUT= 250 MHz, and interpolation to 4×.

2. Disable the PLL.

3. Enable fine NCO and the inverse sinc filter.

/* Enable inverse sinc filter */

0x27 → 0xC0

4. Use the DLL-based interface mode with DLL phase offset = 0.

Derived NCO Settings

/* Power up DAC outputs */

The following NCO settings can be derived from the device

configuration:

0x01 → 0x00

DEVICE CONFIGURATION AND START-UP

SEQUENCE ꢀ

•

f

_DAC= 375 × 4 = 1500 MHz.

_CARRIER= f_OUT= 250 MHz.

1. Set f_DCI= 200 MHz and interpolation to 8×.

2. Enable the PLL, and set f_REF= 200 MHz.

3. Enable the inverse sinc filter.

FTW = f_CARRIER/f_DAC× 2³²= 0x2AAAAAAA.

Start-Up Sequence 1

4. Use the delay line-based interface mode with a delay

setting of 0.

1. Power up the device (no specific power supply sequence is

required).

2. Apply stable DAC clock.

3. Apply stable DCI clock.

4. Feed stable input data.

5. Issue hardware reset (optional).

Derived PLL Settings

The following PLL settings can be derived from the device

configuration:

•

f

_DAC= 200 × 8 = 1600 MHz.

_VCO= f_DAC= 1600 MHz (1.03 GHz < f_VCO< 2.07 GHz).

/* Device configuration register write sequence

*/

VCO divider = f_VCO/f_DAC= 1.

Loop divider = f_DAC/f_REF= 8.

0x00 → 0x20 /* Issue software reset */

0x20 → 0x01 /* Device startup configuration */

Start-Up Sequence 2

1. Power up the device (no specific power supply sequence is

required).

/* Configure data interface */

2. Apply stable DAC clock.

0x5E → 0xFE /* Turn off LSB delay cell */

3. Apply stable DCI clock.

4. Feed stable input data.

0x0A → 0xC0 /* Enable the DLL and duty cycle

correction. Set DLL phase offset to 0 */

5. Issue hardware reset (optional).

Read 0x0E[7:4] /* Expect 1000b if the DLL is

locked */

/* Device configuration register write sequence

*/

/* Configure interpolation filter */

0x28 → 0x02 /* 4× interpolation */

0x00 → 0x20 /* Issue software reset */

0x20 → 0x01 /* Device startup configuration */

/* Reset FIFO */

0x25 → 0x01

/* Configure PLL */

Read 0x25[1] /* Expect 1b if the FIFO reset is

complete */

0x14 → 0xE7 /* Configure PLL loop BW and charge

pump current */

Read 0x24 /* The readback should be one of the

three values: 0x33, 0x40, or 0x41 */

0x15 → 0xC2 /* Configure VCO divider and loop

divider */

0x12 → 0xC0 /*Enable the PLL */

0x12 → 0x80

/* Configure NCO */

0x27→ 0x40 /* Enable NCO */

0x31 → 0xAA

Wait 10ms for autoband selection to finish

Read 0x16[7] /* Expect 1b if the PLL is locked

*/

0x32 → 0xAA

Rev. A | Page 47 of 72

AD9142A

Data Sheet

/* Configure data interface */

/* Reset FIFO */

0x5E → 0x00 /* Configure the delay setting */

0x25 → 0x01

Read 0x25[1] /* Expect 1b if the FIFO reset is

complete */

0x5F → 0x60

Read 0x24 /* The readback should be one of the

three values: 0x37, 0x40, or 0x41 */

0x0D → 0x16 /* DC couple DCI */

0x0A → 0x00 /* Turn off DLL and duty cycle

correction */

/* Enable inverse sinc filter */

0x27 → 0x80

/* Configure interpolation filter */

0x28 → 0x03 /* 8× interpolation */

/* Power up DAC outputs */

0x01 → 0x00

Rev. A | Page 48 of 72

Data Sheet

AD9142A

DEVICE CONFIGURATION REGISTER MAP

Table 25. Device Configuration Register Map

Reg

Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit ꢀ

Reserved

Bit 1

Bit 0

Reset RW

0x00 Common

[7:0] Reserved

SPI_LSB_

FIRST

DEVICE_

RESET

0x00 RW

0x01 PD_CONTROL [7:0] PD_IDAC

PD_QDAC

PD_DATARCV

Reserved

PD_DEVICE

PD_DACCLK PD_FRAME 0xC0 RW

0x03 INTERRUPT_

ENABLE0

[7:0] Reserved

ENABLE_

SYNC_LOST SYNC_

LOCKED

ENABLE_

SYNC_DONE

ENABLE_PLL_ ENABLE_PLL_

ENABLE_

OVER_

THRESHOLD MUTED

ENABLE_

DACOUT_

0x00 RW

LOST

LOCKED

0x04 INTERRUPT_

ENABLE1

[7:0] ENABLE_

ENABLE_

ENABLE_DLL_ ENABLE_

Reserved

ENABLE_FIFO_ ENABLE_

ENABLE_

FIFO_

WARNING

0x00 RW

PARITY_FAIL SED_FAIL

[7:0] Reserved SYNC_LOST SYNC_

[7:0] PARITY_FAIL SED_FAIL

WARNING

DLL_LOCKED

SYNC_DONE

DLL_LOCKED

UNDERFLOW

FIFO_

OVERFLOW

0x05 INTERRUPT_

FLAG0

PLL_LOST

Reserved

PLL_LOCKED

OVER_

DACOUT_

0x00

R

LOCKED

THRESHOLD MUTED

0x06 INTERRUPT_

FLAG1

DLL_

FIFO_

UNDERFLOW

FIFO_

OVERFLOW

FIFO_

WARNING

0x07 IRQ_SEL0

[7:0] Reserved

SEL_SYNC_

LOST

SEL_SYNC_

LOCKED

SEL_SYNC_

DONE

SEL_PLL_LOST SEL_PLL_

LOCKED

SEL_OVER_

THRESHOLD

SEL_

DACOUT_

MUTED

0x00 RW

0x08 IRQ_SEL1

[7:0] SEL_PARITY_ SEL_SED_

SEL_DLL_

WARNING

SEL_DLL_

LOCKED

Reserved

SEL_FIFO_

UNDERFLOW

SEL_FIFO_

OVERFLOW

SEL_FIFO_

WARNING

0x00 RW

0x40 RW

FAIL

0x09 FRAME_

MODE

[7:0]

Reserved

PARUSAGE

FRMUSAGE

Reserved

FRAME_PIN_USAGE

0x0A DATA_CNTR_0 [7:0] DLL_ENABLE DUTY_

CORRECTION_

Reserved

DLL_PHASE_OFFSET

ENABLE

0x0B DATA_CNTR_1 [7:0] CLEAR_WARN

0x0C DATA_CNTR_2 [7:0]

Reserved

0x39 RW

0x64 RW

0x06 RW

0x0D DATA_CNTR_3 [7:0] LOW_DCI_EN

Reserved

DC_COUPLE_

LOW_EN

Reserved

0x0E DATA_STAT_0 [7:0] DLL_LOCK

DLL_WARN

Reserved

DLL_START_ DLL_END_

WARNING

Reserved

DCI_ON

DLL_

RUNNING

0x00 R

WARNING

0x10 DACCLK_

RECEIVER_

CTRL

[7:0] DACCLK_

DUTYCYCLE_

CORRECTION

DACCLK_

DACCLK_CROSSPOINT_LEVEL

REFCLK_CROSSPOINT_LEVEL

PLL_MANUAL_BAND

0xFF RW

0x5F RW

0x00 RW

CROSSPOINT_

CTRL_ENABLE

0x11 REFCLK_

RECEIVER_

CTRL

[7:0] DUTYCYCLE_ Reserved

CORRECTION

REFCLK_

CROSSPOINT_

CTRL_ENABLE

0x12 PLL_CTRL0

[7:0] PLL_ENABLE AUTO_

MANUAL_

SEL

0x14 PLL_CTRL2

0x15 PLL_CTRL3

[7:0]

PLL_LOOP_BW

DIGLOGIC_DIVIDER

PLL_CP_CURRENT

VCO_DIVIDER

0xE7 RW

0xC9 RW

Reserved

CROSSPOINT_

CTRL_EN

LOOP_DIVIDER

0x16 PLL_STATUS0 [7:0] PLL_LOCK

0x17 PLL_STATUS1 [7:0]

VCO_CTRL_VOLTAGE_READBACK

PLL_BAND_READBACK

IDAC_FULLSCALE_ADJUST_LSB

0x00

R

Reserved

0x18 IDAC_FS_

ADJ0

[7:0]

0xF9 RW

0x19 IDAC_FS_

ADJ1

[7:0]

Reserved

IDAC_FULLSCALE_ADJUST_ 0xE1 RW

MSB

0x1A QDAC_FS_ADJ0 [7:0]

0x1B QDAC_FS_ADJ1 [7:0]

QDAC_FULLSCALE_ADJUST_LSB

0xF9 RW

Reserved

QDAC_FULLSCALE_ADJUST_ 0x01 RW

MSB

0x1C DIE_TEMP_

SENSOR_CTRL

[7:0] Reserved

FS_CURRENT

REF_CURRENT

DIE_TEMP_ 0x02 RW

SENSOR_EN

0x1D DIE_TEMP_

LSB

[7:0]

DIE_TEMP_LSB

DIE_TEMP_MSB

0x00

0x0A

R

0x1E DIE_TEMP_

MSB

0x1F CHIP_ID

[7:0]

CHIP_ID

0x20 INTERRUPT_

CONFIG

INTERRUPT_CONFIGURATION

0x00 RW

0x12 RW

0x21 SYNC_CTRL

[7:0]

Reserved

SYNC_CLK_

EDGE_SEL

SYNC_

ENABLE

0x22 FRAME_RST_ [7:0]

CTRL

Reserved

ARM_FRAME EN_CON_

FRAME_RESET

FRAME_RESET_MODE

Rev. A | Page 49 of 72

AD9142A

Data Sheet

Reg

Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit ꢀ

Bit 1

Bit 0

Reset RW

0x23 FIFO_LEVEL_

CONFIG

[7:0] Reserved

INTEGER_FIFO_LEVEL_REQUEST

INTEGER_FIFO_LEVEL_READBACK

Reserved

FRACTIONAL_FIFO_LEVEL_REQUEST

0x40 RW

0x24 FIFO_LEVEL_ [7:0] Reserved

READBACK

Reserved

FRACTIONAL_FIFO_LEVEL_READBACK

0x00

R

0x25 FIFO_CTRL

[7:0]

FIFO_SPI_

RESET_ACK

FIFO_SPI_

RESET_

0x00 RW

REQUEST

0x26 DATA_

FORMAT

[7:0] DATA_

FORMAT

DATA_

PAIRING

DATA_BUS_

INVERT

Reserved

FS4_

DATA_BUS_ 0x00 RW

WIDTH

0x27 DATAPATH_

CTRL

[7:0] INVSINC_

ENABLE

NCO_ENABLE IQ_GAIN_ADJ_ IQ_PHASE_ADJ_ Reserved

NCO_

SEND_IDATA 0x00 RW

_TO_QDAC

DCOFFSET_

ENABLE

MODULATION_ SIDEBAND_

ENABLE SEL

INTERPOLATION_MODE

0x28 INTERPOLATION [7:0]

_CTRL

Reserved

0x00 RW

0x29 OVER_

THRESHOLD_

[7:0]

THRESHOLD_LEVEL_REQUEST_LSB

CTRL0

0x2A OVER_

[7:0]

Reserved

THRESHOLD_LEVEL_REQUEST_MSB

SAMPLE_WINDOW_LENGTH

0x00 RW

THRESHOLD_

CTRL1

0x2B OVER_

[7:0] ENABLE_

IQ_DATA_

Reserved

THRESHOLD_

PROTECTION SWAP

CTRL2

0x2C INPUT_

POWER_

[7:0]

INPUT_POWER_READBACK_LSB

0x00

R

READBACK_LSB

0x2D INPUT_POWER_ [7:0]

Reserved

INPUT_POWER_READBACK_MSB

READBACK_

MSB

0x30 NCO_CTRL

[7:0] Reserved

NCO_FRAME_ SPI_NCO_

UPDATE_ACK PHASE_RST_

ACK

SPI_NCO_

PHASE_

RST_REQ

Reserved

NCO_SPI_

UPDATE_ACK UPDATE_REQ

NCO_SPI_

0x00 RW

0x10 RW

0x31 NCO_FREQ_

TUNING_

[7:0]

NCO_FTW0

NCO_FTW1

NCO_FTW2

NCO_FTW3

WORD0

0x32 NCO_FREQ_

TUNING_

WORD1

0x33 NCO_FREQ_

TUNING_

WORD2

0x34 NCO_FREQ_

TUNING_

WORD3

0x35 NCO_PHASE_ [7:0]

OFFSET0

NCO_PHASE_OFFSET_LSB

NCO_PHASE_OFFSET_MSB

IQ_PHASE_ADJ_LSB

0x00 RW

0x20 RW

0x01 RW

0x36 NCO_PHASE_ [7:0]

OFFSET1

0x37 IQ_PHASE_

ADJ0

[7:0]

0x38 IQ_PHASE_

ADJ1

Reserved

IQ_PHASE_ADJ_MSB

0x39 LVDS_IN_

PWR_DOWN_0

PWR_DOWN_DATA_INPUT_BITS

IDAC_DC_OFFSET_LSB

0x3B IDAC_DC_

OFFSET0

0x3C IDAC_DC_

OFFSET1

IDAC_DC_OFFSET_MSB

QDAC_DC_OFFSET_LSB

QDAC_DC_OFFSET_MSB

0x3D QDAC_DC_

OFFSET0

0x3E QDAC_DC_

OFFSET1

0x3F IDAC_GAIN_

ADJ

Reserved

IDAC_GAIN_ADJ

0x40 QDAC_GAIN_ [7:0]

ADJ

Reserved

QDAC_GAIN_ADJ

RAMP_UP_STEP

0x41 GAIN_STEP_

CTRL0

Rev. A | Page 50 of 72

Data Sheet

AD9142A

Reg

Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit ꢀ

Bit 1

Bit 0

Reset RW

0x42 GAIN_STEP_

CTRL1

DAC_

RAMP_DOWN_STEP

0x41 RW

OUTPUT_OFF OUTPUT_

STATUS

0x43 TX_ENABLE_

CTRL

[7:0]

Reserved

TXENABLE_

GAINSTEP_EN

TXENABLE_

SLEEP_EN

TXENABLE_ 0x07 RW

POWER_

DOWN_EN

0x44

DAC_

OUTPUT_CTRL

[7:0] DAC_

OUTPUT_

CTRL_EN

Reserved

FIFO_

OVERTHRESHOLD Reserved

_SHUTDOWN_EN

FIFO_ERROR_ 0x8D RW

SHUTDOWN_

EN

WARNING_

SHUTDOWN_

EN

0x5E ENABLE_DLL_ [7:0]

DELAY_CELL0

DELAY_CELL_ENABLE [7:0]

0xFF

0x5F ENABLE_DLL_ [7:0]

DELAY_CELL1

Reserved

DELAY_CELL_ENABLE [10:8]

0x67 RW

0x00 RW

0x60 SED_CTRL

[7:0] SED_ENABLE SED_ERR_

CLEAR

AED_ENABLE SED_DEPTH

Reserved

AED_PASS

AED_FAIL

SED_FAIL

0x61 SED_PATT_

L_I0

[7:0]

SED_PATTERN_RISE_I0[7:0]

SED_PATTERN_RISE_I0[15:8]

SED_PATTERN_FALL_Q0[7:0]

SED_PATTERN_FALL_Q0[15:8]

SED_PATTERN_RISE_I1[7:0]

SED_PATTERN_RISE_I1[15:8]

SED_PATTERN_FALL_Q1[7:0]

SED_PATTERN_FALL_Q1[15:8]

Reserved

0x62 SED_PATT_

H_I0

0x63 SED_PATT_

L_Q0

0x64 SED_PATT_

H_Q0

0x65 SED_PATT_

L_I1

0x66 SED_PATT_

H_I1

0x67 SED_PATT_

L_Q1

0x68 SED_PATT_

H_Q1

0x6A PARITY_CTRL [7:0] PARITY_

ENABLE

PARITY_EVEN PARITY_ERR

CLEAR

PARERRFAL

PARERRIS

0x6B PARITY_ERR_ [7:0]

RISING

Parity Rising Edge Error Count

Parity Falling Edge Error Count

Version

0x00

0x0B

R

0x6C PARITY_ERR_ [7:0]

FALLING

0x7F Version

[7:0]

Rev. A | Page 51 of 72

AD9142A

Data Sheet

REGISTER DESCRIPTIONS

Defined reserved bits are those whose reset values are not 0x00. Access indicates the read and/or write nature of the register.

SPI CONFIGURE REGISTER

Address: 0x00, Reset: 0x00, Name: Common

Table 26. Bit Descriptions for Common

Bits

Bit Name

Settings Description

Serial port communication, MSB-first or LSB-first selection.

MSB first.

Reset

Access

6

SPI_LSB_FIRST

0

RW

0

1

LSB first.

5

DEVICE_RESET

The device resets when 1 is written to this bit. DEVICE_RESET is a self clear bit.

After the reset, the bit returns to 0 automatically. The readback is always 0.

0

RW

POWER-DOWN CONTROL REGISTER

Address: 0x01, Reset: 0xC0, Name: PD_CONTROL

Table 27. Bit Descriptions for PD_CONTROL

Bits

Bit Name

Settings Description

Reset

Access

7

PD_IDAC

The IDAC is powered down when PD_IDAC is set to 1. This bit powers down

1

RW

only the analog portion of the IDAC. The IDAC digital data path is not affected.

6

5

2

1

0

PD_QDAC

The QDAC is powered down when PD_QDAC is set to 1. This bit powers down

only the analog portion of the QDAC. The QDAC digital datapath is not affected.

1

0

RW

PD_DATARCV

PD_DEVICE

PD_DACCLK

PD_FRAME

The data interface circuitry is powered down when PD_DATARCV is set to 1.

This bit powers down the data interface and the write side of the FIFO.

The band gap circuitry is powered down when set to 1. This bit powers down

the entire chip.

The DAC clock powers down when PD_DEVICE is set to 1. This bit powers down the

DAC clocking path and, thus, the majority of the digital functions.

The frame receiver powers down when PD_FRAME is set to 1. The frame signal

is internally pulled low. Set to 1 when the frame is not used.

INTERRUPT ENABLE0 REGISTER

Address: 0x03, Reset: 0x00, Name: INTERRUPT_ENABLE0

Table 28. Bit Descriptions for INTERRUPT_ENABLE0

Bits

6

Bit Name

Settings

Description

Reset

Access

RW

ENABLE_SYNC_LOST

ENABLE_SYNC_LOCKED

ENABLE_SYNC_DONE

ENABLE_PLL_LOST

Enable interrupt for sync lost.

Enable interrupt for sync lock.

Enable interrupt for sync done.

Enable interrupt for PLL lost.

Enable interrupt for PLL locked.

Enable interrupt for overthreshold.

Enable interrupt for DACOUT muted.

0

5

RW

4

RW

3

RW

2

ENABLE_PLL_LOCKED

ENABLE_OVER_THRESHOLD

ENABLE_DACOUT_MUTED

RW

1

RW

0

RW

Rev. A | Page 52 of 72

Data Sheet

AD9142A

INTERRUPT ENABLE1 REGISTER

Address: 0x04, Reset: 0x00, Name: INTERRUPT_ENABLE1

Table 29. Bit Descriptions for INTERRUPT_ENABLE1

Bits

Bit Name

Settings

Description

Reset

Access

RW

7

ENABLE_PARITY_FAIL

ENABLE_SED_FAIL

Enable interrupt for parity failure.

Enable interrupt for SED failure.

Enable interrupt for DLL warning.

Enable interrupt for DLL locked.

Enable interrupt for FIFO underflow.

Enable interrupt for FIFO overflow.

Enable interrupt for FIFO warning.

0

6

RW

5

ENABLE_DLL_WARNING

ENABLE_DLL_LOCKED

ENABLE_FIFO_UNDERFLOW

ENABLE_FIFO_OVERFLOW

ENABLE_FIFO_WARNING

RW

4

RW

2

RW

1

RW

0

RW

INTERRUPT FLAG0 REGISTER

Address: 0x05, Reset: 0x00, Name: INTERRUPT_FLAG0

Table 30. Bit Descriptions for INTERRUPT_FLAG0

Bits

6

Bit Name

Settings

Description

Reset

Access

SYNC_LOST

SYNC_LOST is set to 1 when sync is lost.

0

R

5

SYNC_LOCKED

SYNC_DONE

PLL_LOST

SYNC_LOCKED is set to 1 when sync is locked.

SYNC_DONE is set to 1 when sync is done.

PLL_LOST is set to 1 when PLL loses lock.

4

3

2

PLL_LOCKED

OVER_THRESHOLD

DACOUT_MUTED

PLL_LOCKED is set to 1 when PLL is locked.

OVER_THRESHOLD is set to 1 when input power is overthreshold.

DACOUT_MUTED is set to 1 when the DAC output is muted (midscale dc).

1

0

INTERRUPT FLAG1 REGISTER

Address: 0x06, Reset: 0x00, Name: INTERRUPT_FLAG1

Table 31. Bit Descriptions for INTERRUPT_FLAG1

Bits

7

Bit Name

Settings

Description

Reset

Access

PARITY_FAIL

SED_FAIL

PARITY_FAIL is set to 1 when the parity check fails.

SED_FAIL is set to 1 when the SED comparison fails.

DLL_WARNING is set to 1 when the DLL raises a warning.

DLL_LOCKED is set to 1 when the DLL is locked.

0

R

6

5

DLL_WARNING

DLL_LOCKED

FIFO_UNDERFLOW

4

2

FIFO_UNDERFLOW is set to 1 when the FIFO read pointer

catches the FIFO write pointer.

1

0

FIFO_OVERFLOW

FIFO_WARNING

FIFO_OVERFLOW is set to 1 when the when the FIFO

read pointer catches the FIFO read pointer.

0

R

FIFO_WARNING is set to 1 when the FIFO is one slot from

empty (≤1) or full (≥6).

Rev. A | Page 53 of 72

AD9142A

Data Sheet

INTERRUPT SELECT0 REGISTER

Address: 0x07, Reset: 0x00, Name: IRQ_SEL0

Table 32. Bit Descriptions for IRQ_SEL0

Bits

Bit Name

Settings

Description

Reset

Access

6

SEL_SYNC_LOST

0

1

0

1

0

1

0

1

0

1

0

1

0

Selects the IRQ1 pin.

Selects the IRQ2 pin.

Selects the IRQ1 pin.

Selects the IRQ2 pin.

Selects the IRQ1 pin.

Selects the IRQ2 pin.

Selects the IRQ1 pin.

Selects the IRQ2 pin.

Selects the IRQ1 pin.

Selects the IRQ2 pin.

Selects the IRQ1 pin.

Selects the IRQ2 pin.

Selects the IRQ1 pin.

0

RW

5

4

3

2

1

0

SEL_SYNC_LOCKED

SEL_SYNC_DONE

0

RW

SEL_PLL_LOST

SEL_PLL_LOCKED

SEL_OVER_THRESHOLD

SEL_DACOUT_MUTED

INTERRUPT SELECT1 REGISTER

Address: 0x08, Reset: 0x00, Name: IRQ_SEL1

Table 33. Bit Descriptions for IRQ_SEL1

Bits

Bit Name

Settings

Description

Reset

Access

7

SEL_PARITY_FAIL

1

Selects the IRQ2 pin.

Selects the IRQ1 pin.

Selects the IRQ2 pin.

Selects the IRQ1 pin.

Selects the IRQ2 pin.

Selects the IRQ1 pin.

Selects the IRQ2 pin.

Selects the IRQ1 pin.

Selects the IRQ2 pin.

Selects the IRQ1 pin.

Selects the IRQ2 pin.

Selects the IRQ1 pin.

0

RW

0

1

0

1

0

1

0

1

0

1

0

6

SEL_SED_FAIL

0

RW

5

4

SEL_DLL_WARNING

SEL_DLL_LOCKED

0

RW

2

1

0

SEL_FIFO_UNDERFLOW

SEL_FIFO_OVERFLOW

SEL_FIFO_WARNING

0

RW

FRAME MODE REGISTER

Address: 0x09, Reset: 0x00, Name: FRAME_MODE

Table 34. Bit Descriptions for FRAME_MODE

Bits

5

Bit Name

Description

Reset

Access

PARUSAGE

Must set to 1 when parity is used

Must set to 1 when frame is used.

0

RW

4

FRMUSAGE

0

[1:0]

FRAME_PIN_USAGE

0 = no effect.

1 = parity.

0x0

2 = frame.

3 = reserved.

Rev. A | Page 54 of 72

Data Sheet

AD9142A

DATA CONTROL 0 REGISTER

Address: 0x0A, Reset: 0x40, Name: DATA_CNTR_0

Table 35. Bit Descriptions for DATA_CNTR_0

Bits

Bit Name

Description

Reset

Access

7

DLL_ENABLE

1 = enable DLL.

0 = disable DLL.

0

RW

6

DUTY_CORRECTION_ENABLE 1 = enable duty cycle correction.

0 = disable duty cycle correction.

1

RW

[3:0]

DLL_PHASE_OFFSET

Locked phase = 90° + n ×11.25°, where n is the 4 bit signed magnitude

number. Valid phase setting ranges from −6 to +6, 13 phases in total.

0x0

DATA CONTROL 1 REGISTER

Address: 0x0B, Reset: 0x39, Name: DATA_CNTR_1

Table 36. Bit Descriptions for DATA_CNTR_1

Bits Bit Name

Description

Reset

Access

RW

7

CLEAR_WARN

1= clears data receiver warning bits (Register 0x0E[6:4]).

Must write the default value for optimal performance.

0

[6:0] Reserved

0x39

RW

DATA CONTROL ꢀ REGISTER

Address: 0x0C, Reset: 0x64, Name: DATA_CNTR_2

Table 37. Bit Descriptions for DATA_CNTR_2

Bits Bit Name

Description

Reset

Access

[7:0] Reserved

Must write the default value for optimal performance.

0x64

RW

DATA CONTROL 3 REGISTER

Address: 0x0D, Reset: 0x06, Name: DATA_CNTR_3

Table 38. Bit Descriptions for DATA_CNTR_3

Bits Bit Name

Description

Reset

Access

7

LOW_DCI_EN

Set to 0 when DLL is enabled and DCI rate is ≥350 MHz.

Set to 1 when DLL is enabled and DCI rate is <350 MHz.

0

RW

4

DC_COUPLE_LOW_EN

Set to 0 when DLL is enabled and delay line is disabled.

Set to 1 when DLL is disabled and delay line is enabled.

It is recommended that DLL mode be used for a DCI rate faster than 250 MHz

and the delay line mode be used for DCI rate slower than 250 MHz.

0

RW

[3:0] Reserved

Must write the default value for optimal performance.

0x6

DATA STATUS 0 REGISTER

Address: 0x0E, Reset: 0x00, Name: DATA_STAT_0

Table 39. Bit Descriptions for DATA_STAT_0

Bits Bit Name

Description

Reset

Access

7

6

5

4

3

2

1

0

DLL_LOCK

1 = DLL lock.

0

R

DLL_WARN

1 = DLL near beginning/end of delay line.

1 = DLL at beginning of delay line.

1 = DLL at end of delay line.

Reserved.

DLL_START_WARNING

DLL_END_WARNING

Reserved

DCI_ON

1 = user has provided a clock >100 MHz.

Reserved.

Reserved

DLL_RUNNING

1 = closed loop DLL attempting to lock.

0 = delay fixed at middle of delay line.

Rev. A | Page 55 of 72

AD9142A

Data Sheet

DAC CLOCK RECEIVER CONTROL REGISTER

Address: 0x10, Reset: 0xFF, Name: DACCLK_RECEIVER_CTRL

Table 40. Bit Descriptions for DACCLK_RECEIVER_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

7

DACCLK_DUTYCYCLE_CORRECTION

Enables duty cycle correction at the DACCLK input. For

best performance, the default and recommended status

is turned on.

1

RW

6

5

Reserved

Must write the default value for optimal performance

1

RW

DACCLK_CROSSPOINT_CTRL_ENABLE

Enables crosspoint control at the DACCLK input. For best

performance, the default and recommended status is

turned on.

[4:0]

DACCLK_CROSSPOINT_LEVEL

A twos complement value. For best performance, it is

recommended to set DACCLK_CROSSPOINT_LEVEL to

the default value.

0x1F

RW

01111 Highest crosspoint.

11111 Lowest crosspoint.

REF CLOCK RECEIVER CONTROL REGISTER

Address: 0x11, Reset: 0x5F, Name: REFCLK_RECEIVER_CTRL

Table 41. Bit Descriptions for REFCLK_RECEIVER_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

7

DUTYCYCLE_CORRECTION

Enables duty cycle correction at the REFx/SYNCx input.

For best performance, the default and recommended

status is turned off.

0

RW

6

5

Reserved

Must write the default value for optimal performance

1

0

RW

REFCLK_CROSSPOINT_CTRL_ENABLE

Enables crosspoint control at the REFx/SYNCx input. For

best performance, the default and recommended status

is turned off.

[4:0]

REFCLK_CROSSPOINT_LEVEL

A twos complement value. For best performance, it is

recommended to set REFCLK_CROSSPOINT_LEVEL to

the default value.

0x1F

RW

01111 Highest crosspoint.

11111 Lowest crosspoint.

PLL CONTROL 0 REGISTER

Address: 0x12, Reset: 0x00, Name: PLL_CTRL0

Table 42. Bit Descriptions for PLL_CTRL0

Bits

Bit Name

Settings

Description

Reset

Access

RW

7

PLL_ENABLE

Enables PLL clock multiplier.

PLL band selection mode.

Automatic mode.

0

6

AUTO_MANUAL_SEL

RW

0

1

Manual mode.

[5:0]

PLL_MANUAL_BAND

PLL band setting in manual mode. 64 bands in total, covering a 1 GHz to 0x00

2.1 GHz VCO range.

RW

000000 Lowest band (1 GHz).

111111 Highest band (2.1 GHz).

Rev. A | Page 56 of 72

Data Sheet

AD9142A

PLL CONTROL ꢀ REGISTER

Address: 0x14, Reset: 0xE7, Name: PLL_CTRL2

Table 43. Bit Descriptions for PLL_CTRL2

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

PLL_LOOP_BW

Selects the PLL filter bandwidth. The default and recommended setting 0x7

is 111 for optimal PLL performance.

RW

0x00 Lowest setting.

0x1F Highest setting.

Sets nominal PLL charge pump current. The default and recommended

setting is 00111 for optimal PLL performance.

0x00 Lowest setting.

0x1F Highest setting.

[4:0]

PLL_CP_CURRENT

0x07

RW

PLL CONTROL 3 REGISTER

Address: 0x15, Reset: 0xC9, Name: PLL_CTRL3

Table 44. Bit Descriptions for PLL_CTRL3

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

DIGLOGIC_DIVIDER

REFCLK to PLL digital clock divide ratio. The PLL digital clock drives the

internal PLL logics. The divide ratio must be set to ensure that the PLL

digital clock is less than 75 MHz.

0x3

RW

00 f_REFCLK/f_DIG= 2.

01 f_REFCLK/f_DIG= 4.

10 f_REFCLK/f_DIG= 8.

11 f_REFCLK/f_DIG= 16.

4

CROSSPOINT_CTRL_EN

VCO_DIVIDER

Enable loop divider crosspoint control. The default and recommended

setting is set to 0 for optimal PLL performance.

0

RW

[3:2]

PLL VCO divider. This divider determines the ratio of the VCO frequency

to the DACCLK frequency.

0x2

00 f_VCO/f_DACCLK= 1.

01 f_VCO/f_DACCLK= 2.

10 f_VCO/f_DACCLK= 4.

11 f_VCO/f_DACCLK= 4.

[1:0]

LOOP_DIVIDER

PLL divider. This divider determines the ratio of the DACCLK frequency

to the REFCLK frequency.

00 f_DACCLK/f_REFCLK= 2.

0x1

RW

01 f_DACCLK/f_REFCLK= 4.

10 f_DACCLK/f_REFCLK= 8.

11 f_DACCLK/f_REFCLK= 16.

PLL STATUS 0 REGISTER

Address: 0x16, Reset: 0x00, Name: PLL_STATUS0

Table 45. Bit Descriptions for PLL_STATUS0

Bits

7

Bit Name

Settings Description

PLL clock multiplier output is stable.

Reset

0

Access

PLL_LOCK

R

[3:0]

VCO_CTRL_VOLTAGE_READBACK

VCO control voltage readback. A binary value.

1111 The highest VCO control voltage.

0x0

0111 The midvalue when a proper VCO band is selected. When

the PLL is locked, selecting a higher VCO band decreases this

value and selecting a lower VCO band increases this value.

0000 The lowest VCO control voltage.

Rev. A | Page 57 of 72

AD9142A

Data Sheet

PLL STATUS 1 REGISTER

Address: 0x17, Reset: 0x00, Name: PLL_STATUS1

Table 46. Bit Descriptions for PLL_STATUS1

Bits

Bit Name

Settings

Description

Reset

Access

[5:0]

PLL_BAND_READBACK

Indicates the VCO band currently selected.

0x00

R

IDAC FS ADJUST LSB REGISTER

Address: 0x18, Reset: 0xF9, Name: IDAC_FS_ADJ0

Table 47. Bit Descriptions for IDAC_FS_ADJ0

Bits

Bit Name

Settings Description

Reset

Access

[7:0]

IDAC_FULLSCALE_ADJUST_LSB

IDAC full-scale adjust, these bits, along with Bits[1:0] in

Register 0x19, set the full-scale current of the IDAC. The full-

scale current can be adjusted from 8.64 mA to 31.68 mA. The

default value (0x1F9) sets the full-scale current to 20 mA.

0xF9

RW

IDAC FS ADJUST MSB REGISTER

Address: 0x19, Reset: 0xE1, Name: IDAC_FS_ADJ1

Table 48. Bit Descriptions for IDAC_FS_ADJ1

Bits

[7:5]

[1:0]

Bit Name

Settings Description

Reset

0x7

Access

RW

Reserved

Set to default value for optimal performance.

IDAC_FULLSCALE_ADJUST_MSB

IDAC full-scale adjust, these bits, along with Bits[7:0] in

Register 0x18,the full-scale current of the IDAC. The full-scale

current can be adjusted from 8.64 mA to 31.68 mA. The

default value (0x1F9) sets the full-scale current to 20 mA.

0x1

RW

QDAC FS ADJUST LSB REGISTER

Address: 0x1A, Reset: 0xF9, Name: QDAC_FS_ADJ0

Table 49. Bit Descriptions for QDAC_FS_ADJ0

Bits

Bit Name

Settings Description

Reset

Access

[7:0]

QDAC_FULLSCALE_ADJUST_LSB

QDAC Full-Scale Adjust, these bits, along with Bits[1:0] in Register 0xF9

0x1B, set the full-scale current of the QDAC. The full-scale

current can be adjusted from 8.64 mA to 31.68 mA. The

default value (0x1F9) sets the full-scale current to 20 mA.

RW

QDAC FS ADJUST MSB REGISTER

Address: 0x1B, Reset: 0x01, Name: QDAC_FS_ADJ1

Table 50. Bit Descriptions for QDAC_FS_ADJ1

Bits Bit Name

Settings Description

Reset

Access

[1:0] QDAC_FULLSCALE_ADJUST_MSB

QDAC Full-Scale Adjust, these bits, along with Bits[7:0] in Register 0x1

RW

0x1A, set the full-scale current of the QDAC. The full-scale

current can be adjusted from 8.64 mA to 31.68 mA. The

default value (0x1F9) sets the full-scale current to 20 mA.

Rev. A | Page 58 of 72

Data Sheet

AD9142A

DIE TEMPERATURE SENSOR CONTROL REGISTER

Address: 0x1C, Reset: 0x02, Name: DIE_TEMP_SENSOR_CTRL

Table 51. Bit Descriptions for DIE_TEMP_SENSOR_CTRL

Bits Bit Name

Settings Description

Temperature sensor ADC full-scale current. Using the default

setting is recommended.

000 50 μA.

Reset Access

[6:4] FS_CURRENT

0x0

0x1

0x0

RW

001 62.5 μA.

…

110 125 μA.

111 137.5 μA.

[3:1] REF_CURRENT

Temperature sensor ADC reference current. Using the default

setting is recommended.

000 12.5 μA.

001 19 μA.

…

110 50 μA.

111 56.5 μA.

0

DIE_TEMP_SENSOR_EN

Enable the on-chip temperature sensor.

DIE TEMPERATURE LSB REGISTER

Address: 0x1D, Reset: 0x00, Name: DIE_TEMP_LSB

Table 52. Bit Descriptions for DIE_TEMP_LSB

Bits Bit Name

Settings Description

Reset Access

[7:0] DIE_TEMP_LSB

Die temperature, these bits, along with Bits[7:0] in Register 0x1E,

indicate the approximate die temperature. For more information, see

the Temperature Sensor section.

0x00

R

DIE TEMPERATURE MSB REGISTER

Address: 0x1E, Reset: 0x00, Name: DIE_TEMP_MSB

Table 53. Bit Descriptions for DIE_TEMP_MSB

Bits Bit Name

Settings Description

Reset

Access

[7:0] DIE_TEMP_MSB

Die temperature, these bits, along with Bits[7:0] in Register 0x1D,

indicate the approximate die temperature. For more information,

see the Temperature Sensor section.

0x00

R

CHIP ID REGISTER

Address: 0x1F, Reset: 0x0A, Name: CHIP_ID

Table 54. Bit Descriptions for CHIP_ID

Bits Bit Name

Settings Description

Reset Access

0x0A

[7:0] CHIP_ID

The AD9142A chip ID is 0x0A.

R

INTERRUPT CONFIGUATION REGISTER

Address: 0x20, Reset: 0x00, Name: INTERRUPT_CONFIG

Table 55. Bit Descriptions for INTERRUPT_CONFIG

Bits Bit Name

Settings Description

Reset Access

0x00 RW

[7:0] INTERRUPT_CONFIGURATION

0x00 Test mode.

0x01 Recommended mode (described in the Interrupt Request

Operation section).

Rev. A | Page 59 of 72

AD9142A

Data Sheet

SYNC CONTROL REGISTER

Address: 0x21, Reset: 0x00, Name: SYNC_CTRL

Table 56. Bit Descriptions for SYNC_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

1

SYNC_CLK_EDGE_SEL

Selects the sampling edge of the DACCLK on the sync clock.

SYNC CLK is sampled by the falling edges of DACCLK.

SYNC CLK is sampled by the rising edges of DACCLK.

Enables multichip synchronization.

0

RW

0

1

0

SYNC_ENABLE

0

RW

FRAME RESET CONTROL REGISTER

Address: 0x22, Reset: 0x12, Name: FRAME_RST_CTRL

Table 57. Bit Descriptions for FRAME_RST_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

3

ARM_FRAME

This bit is used to retrigger a frame reset in one shot mode (when Bit

2 is set to 0). Setting this bit to 1 requests the device to respond to

the next valid frame pulse.

0

RW

2

EN_CON_FRAME_RESET

FRAME_RESET_MODE

Frame reset mode selection.

Responds to the first valid frame pulse and resets the FIFO one time

only. This is the default and recommended mode.

Responds to every valid frame pulse and resets the FIFO

continuously.

0

RW

0

1

[1:0]

These bits determine what is to be reset when the device receives a

valid frame signal.

0x2

00 FIFO only.

01 NCO only.

10 FIFO and NCO.

11 None.

FIFO LEVEL CONFIGURATION REGISTER

Address: 0x23, Reset: 0x40, Name: FIFO_LEVEL_CONFIG

Table 58. Bit Descriptions for FIFO_LEVEL_CONFIG

Bits

Bit Name

Settings Description

Reset

Access

[6:4]

INTEGER_FIFO_LEVEL_REQUEST

These bits set the integer FIFO level. This is the difference

0x4

RW

between the read pointer and the write pointer values in

the unit of input data rate (f_DATA). The default and

recommended FIFO level is integer level = 4 and fractional

level = 0. See the FIFO Operation section for details.

000 0.

001 1.

…

111 7.

[2:0]

FRACTIONAL_FIFO_LEVEL_REQUEST

Set the fractional FIFO level. This is the difference between

0x0

RW

the read pointer and the write pointer values in the unit of

DACCLK rate (f_DAC). The maximum allowed setting value =

interpolation rate − 1. See the FIFO Operation section for

details.

000 0.

001 1.

Rev. A | Page 60 of 72

Data Sheet

AD9142A

FIFO LEVEL READBACK REGISTER

Address: 0x24, Reset: 0x00, Name: FIFO_LEVEL_READBACK

Table 59. Bit Descriptions for FIFO_LEVEL_READBACK

Bits

Bit Name

Settings Description

Reset

Access

[6:4]

INTEGER_FIFO_LEVEL_READBACK

The integer FIFO level read back. The difference between the

0x0

R

overall FIFO level request and readback should be within

two DACCLK cycles. See the FIFO Operation section for details.

[2:0]

FRACTIONAL_FIFO_LEVEL_READBACK

The fractional FIFO level read back. This value should be

used in combination with the readback in Bits[6:4].

0x0

R

FIFO CONTROL REGISTER

Address: 0x25, Reset: 0x00, Name: FIFO_CTRL

Table 60. Bit Descriptions for FIFO_CTRL

Bits

Bit Name

Settings Description

Reset

0x0

Access

R

1

FIFO_SPI_RESET_ACK

FIFO_SPI_RESET_REQUEST

Acknowledge a serial port initialized FIFO reset.

Initialize a FIFO reset via the serial port.

0

0x0

RW

DATA FORMAT SELECT REGISTER

Address: 0x26, Reset: 0x00, Name: DATA_FORMAT_SEL

Table 61. Bit Descriptions for DATA_FORMAT_SEL

Bits

Bit Name

Settings

Description

Reset

Access

7

DATA_FORMAT

Select binary or twos complement data format.

Input data in twos complement format.

Input data in binary format.

0x0

RW

0

1

6

5

DATA_PAIRING

Indicate I/Q data pairing on data input.

I samples are paired with the next Q samples.

I samples are paired with the prior Q samples.

0x0

RW

0

1

DATA_BUS_INVERT

Swap the bit order of the data input port. MSBs become the LSBs:

D[15:0] changes to D[0:15].

0

1

The order of the data bits corresponds to the pin descriptions in Table 9.

The order of the data bits is inverted.

0

DATA_BUS_WIDTH

Data interface mode. See the LVDS Input Data Ports section for

information about the operation of the different interface modes.

0x0

RW

0

1

Word interface mode; 16-bit interface bus width.

Byte interface mode; 8-bit interface bus width.

DATAPATH CONTROL REGISTER

Address: 0x27, Reset: 0x00, Name: DATAPATH_CTRL

Table 62. Bit Descriptions for DATAPATH_CTRL

Bits

7

Bit Name

Settings

Description

Reset

0x0

Access

RW

INVSINC_ENABLE

Enable the inverse sinc filter.

6

NCO_ENABLE

Enable the NCO.

RW

5

IQ_GAIN_ADJ_DCOFFSET_ENABLE

IQ_PHASE_ADJ_ENABLE

FS4_MODULATION_ENABLE

NCO_SIDEBAND_SEL

Enable digital IQ gain adjustment and dc offset.

Enable digital IQ phase adjustment.

Enable f_S/4 modulation function.

Selects the single-side NCO modulation image.

The NCO outputs the high-side image.

The NCO outputs the low-side image.

RW

4

RW

2

RW

1

RW

0

1

0

SEND_IDATA_TO_QDAC

Send the IDATA to the QDAC. When enabled, I data is sent

to both the IDAC and the QDAC. The Q data path still runs,

and the Q data is ignored.

0x0

RW

Rev. A | Page 61 of 72

AD9142A

Data Sheet

INTERPOLATION CONTROL REGISTER

Address: 0x28, Reset: 0x00, Name: INTERPOLATION_CTRL

Table 63. Bit Descriptions for INTERPOLATION_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

[1:0]

INTERPOLATION_MODE

Interpolation rate and mode selection.

00 2× Mode; use HB1 filter.

0x0

RW

10 4× mode; use HB1 and HB2 filters.

11 8× mode; use all three filters (HB1, HB2, and HB3).

OVER THRESHOLD CONTROL 0 REGISTER

Address: 0x29, Reset: 0x00, Name: OVER_THRESHOLD_CTRL0

Table 64. Bit Descriptions for OVER_THRESHOLD_CTRL0

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

THRESHOLD_LEVEL_REQUEST_LSB

These bits, along with Bits[4:0] in Register 0x2A, set the

minimum average input power (I²+ Q²) to trigger the

input power protection function.

0x0

RW

OVER THRESHOLD CONTROL 1 REGISTER

Address: 0x2A, Reset: 0x00, Name: OVER_THRESHOLD_CTRL1

Table 65. Bit Descriptions for OVER_THRESHOLD_CTRL1

Bits

Bit Name

Settings

Description

Reset

Access

[4:0]

THRESHOLD_LEVEL_REQUEST_MSB

These bits, along with Bits[7:0] in Register 0x29, set the

minimum average input power (I²+ Q²) to trigger the

input power protection function.

0x00

RW

OVER THRESHOLD CONTROL ꢀ REGISTER

Address: 0x2B, Reset: 0x00, Name: OVER_THRESHOLD_CTRL2

Table 66. Bit Descriptions for OVER_THRESHOLD_CTRL2

Bits Bit Name

Settings

Description

Reset

0x0

Access

RW

7

6

ENABLE_PROTECTION

IQ_DATA_SWAP

Enable input power protection.

Swap I and Q data in average power calculation.

Number of data input samples for power averaging.

0x0

RW

[3:0] SAMPLE_WINDOW_LENGTH

0x0

RW

0000 512 IQ data sample pairs.

0001 1024 IQ data sample pairs.

…

1010 2¹⁹IQ data sample pairs.

1011 to invalid.

1111

INPUT POWER READBACK LSB REGISTER

Address: 0x2C, Reset: 0x00, Name: INPUT_POWER_READBACK_LSB

Table 67. Bit Descriptions for INPUT_POWER_READBACK_LSB

Bits Bit Name

Settings

Description

Reset

Access

[7:0] INPUT_POWER_READBACK_LSB

These bits, along with Bits[4:0] in Register 0x2D, set the

input signal average power readback.

0x0

R

Rev. A | Page 62 of 72

Data Sheet

AD9142A

INPUT POWER READBACK MSB REGISTER

Address: 0x2D, Reset: 0x00, Name: INPUT_POWER_READBACK_MSB

Table 68. Bit Descriptions for INPUT_POWER_READBACK_MSB

Bits Bit Name

Settings

Description

Reset

0x00

Access

[4:0] INPUT_POWER_READBACK_MSB

These bits, along with Bits[7:0] in Register 0x2C, set the

input signal average power readback.

R

NCO CONTROL REGISTER

Address: 0x30, Reset: 0x00, Name: NCO_CTRL

Table 69. Bit Descriptions for NCO_CTRL

Bits Bit Name

Settings

Description

Reset

Access

6

5

4

1

0

NCO_FRAME_UPDATE_ACK

Frequency tuning word update request from frame.

NCO phase SPI reset acknowledge.

0x0

R

SPI_NCO_PHASE_RST_ACK

SPI_NCO_PHASE_RST_REQ

NCO_SPI_UPDATE_ACK

NCO_SPI_UPDATE_REQ

R

NCO phase SPI reset request.

RW

R

Frequency tuning word update acknowledge.

Frequency tuning word update request from SPI.

RW

NCO FREQUENCY TUNING WORD 0 REGISTER

Address: 0x31, Reset: 0x00, Name: NCO_FREQ_TUNING_WORD0

Table 70. Bit Descriptions for NCO_FREQ_TUNING_WORD0

Bits Bit Name

Settings

Description

Reset

Access

[7:0] NCO_FTW0

Bits[7:0] together with the bits in Register 0x32, Register 0x33, and

Register 0x34 form the 32-bit frequency tuning word that

0x00

RW

determines the frequency of the complex carrier generated by the

on-chip NCO. The frequency is not updated when the FTW registers are

written. The values are only updated when a serial port update or frame

update is initialized in Register 0x30. It is in twos complement format.

NCO FREQUENCY TUNING WORD 1 REGISTER

Address: 0x32, Reset: 0x00, Name: NCO_FREQ_TUNING_WORD1

Table 71. Bit Descriptions for NCO_FREQ_TUNING_WORD1

Bits Bit Name

Settings

Description

Reset

Access

[7:0] NCO_FTW1

Bits[7:0] together with the bits in Register 0x31, Register 0x33, and

Register 0x34 form the 32-bit frequency tuning word that

0x00

RW

determines the frequency of the complex carrier generated by the

on-chip NCO. The frequency is not updated when the FTW registers are

written. The values are only updated when a serial port update or frame

update is initialized in Register 0x30. It is in twos complement format.

NCO FREQUENCY TUNING WORD ꢀ REGISTER

Address: 0x33, Reset: 0x00, Name: NCO_FREQ_TUNING_WORD2

Table 72. Bit Descriptions for NCO_FREQ_TUNING_WORD2

Bits Bit Name

Settings

Description

Reset

Access

[7:0] NCO_FTW2

Bits[7:0] together with the bits in Register 0x31, Register 0x32, and

Register 0x34 form the 32-bit frequency tuning word that

0x00

RW

determines the frequency of the complex carrier generated by the

on-chip NCO. The frequency is not updated when the FTW registers are

written. The values are only updated when a serial port update or frame

update is initialized in Register 0x30. It is in twos complement format.

Rev. A | Page 63 of 72

AD9142A

Data Sheet

NCO FREQUENCY TUNING WORD 3 REGISTER

Address: 0x34, Reset: 0x10, Name: NCO_FREQ_TUNING_WORD3

Table 73. Bit Descriptions for NCO_FREQ_TUNING_WORD3

Bits Bit Name

Settings Description

Reset

Access

[7:0] NCO_FTW3

Bits[7:0] together with the bits in Register 0x31 through Register

0x10

RW

0x33 form the 32-bit frequency tuning word that determines the

frequency of the complex carrier generated by the on-chip NCO.

The frequency is not updated when the FTW registers are written. The

values are only updated when a serial port update or frame update is

initialized in Register 0x30. It is in twos complement format.

NCO PHASE OFFSET 0 REGISTER

Address: 0x35, Reset: 0x00, Name: NCO_PHASE_OFFSET0

Table 74. Bit Descriptions for NCO_PHASE_OFFSET0

Bits Bit Name

Settings Description

This register, together with Register 0x36, sets the initial phase of the

Reset

Access

[7:0] NCO_PHASE_OFFSET_LSB

0x00

RW

complex carrier signal upon reset. The phase offset spans from 0° to

360°. Each bit represents an offset of 0.0055°. This value is in twos

complement format.

NCO PHASE OFFSET 1 REGISTER

Address: 0x36, Reset: 0x00, Name: NCO_PHASE_OFFSET1

Table 75. Bit Descriptions for NCO_PHASE_OFFSET1

Bits Bit Name

Settings

Description

Reset

Access

[7:0] NCO_PHASE_OFFSET_MSB

This register, together with Register 0x35, sets the initial phase of the

complex carrier signal upon reset. The phase offset spans from 0° to 360°.

Each bit represents an offset of 0.0055°. This value is in twos

complement format.

0x00

RW

IQ PHASE ADJUST 0 REGISTER

Address: 0x37, Reset: 0x00, Name: IQ_PHASE_ADJ0

Table 76. Bit Descriptions for IQ_PHASE_ADJ0

Bits Bit Name

Settings

Description

Reset

Access

[7:0] IQ_PHASE_ADJ_LSB

Q phase adjust, Bits[7:0] along with Bits[4:0] in Register 0x38, is used to 0x00

insert a phase offset between the I and Q datapaths. It provides an

adjustment range of 14° with a step of 0.0035°. This value is in twos

complement. See the Quadrature Phase Adjustment section for more

information.

RW

IQ PHASE ADJUST 1 REGISTER

Address: 0x38, Reset: 0x00, Name: IQ_PHASE_ADJ1

Table 77. Bit Descriptions for IQ_PHASE_ADJ1

Bits Bit Name

Settings

Description

Reset

Access

[4:0] IQ_PHASE_ADJ_MSB

IQ phase adjust, Bits[4:0] along with Bits[7:0] in Register 0x37, is used

to insert a phase offset between the I and Q datapaths. It provides an

adjustment range of 14° with a step of 0.0035°. This value is in twos

complement. See the Quadrature Phase Adjustment section for more

information.

0x0

RW

Rev. A | Page 64 of 72

Data Sheet

AD9142A

POWER DOWN DATA INPUT 0 REGISTER

Address: 0x39, Reset: 0x00, Name: LVDS_IN_PWR_DOWN_0

Table 78. Bit Descriptions for LVDS_IN_PWR_DOWN_0

Bits Bit Name

Settings

Description

Reset Access

[3:0] PWR_DOWN_DATA_INPUT_BITS

Powers down data input D[3:0]. Each bit controls one data input 0x0

bit. These bits can be powered down individually.

RW

IDAC DC OFFSET 0 REGISTER

Address: 0x3B, Reset: 0x00, Name: IDAC_DC_OFFSET0

Table 79. Bit Descriptions for IDAC_DC_OFFSET0

Bits Bit Name

Settings

Description

Reset

Access

[7:0] IDAC_DC_OFFSET_LSB

DAC dc offset, Bits[7:0] along with Bits[7:0] in Register 0x3C, is a dc

value that is added directly to the sample values written to the DAC.

0x00

RW

IDAC DC OFFSET 1 REGISTER

Address: 0x3C, Reset: 0x00, Name: IDAC_DC_OFFSET1

Table 80. Bit Descriptions for IDAC_DC_OFFSET1

Bits Bit Name

Settings

Description

Reset

Access

[7:0] IDAC_DC_OFFSET_MSB

DAC dc offset, Bits[7:0] along with Bits[7:0] in Register 0x3B, is a dc

value that is added directly to the sample values written to the DAC.

0x00

RW

QDAC DC OFFSET 0 REGISTER

Address: 0x3D, Reset: 0x00, Name: QDAC_DC_OFFSET0

Table 81. Bit Descriptions for QDAC_DC_OFFSET0

Bits Bit Name

Settings

Description

Reset

Access

[7:0] QDAC_DC_OFFSET_LSB

QDAC dc offset, Bits[7:0] along with Bits[7:0] in Register 0x3E, is a dc

value that is added directly to the sample values written to the QDAC.

0x00

RW

QDAC DC OFFSET 1 REGISTER

Address: 0x3E, Reset: 0x00, Name: QDAC_DC_OFFSET1

Table 82. Bit Descriptions for QDAC_DC_OFFSET1

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

QDAC_DC_OFFSET_MSB

QDAC dc offset, Bits[7:0] along with Bits[7:0] in Register 0x3D, is a dc

value that is added directly to the sample values written to the QDAC.

0x00

RW

IDAC GAIN ADJUST REGISTER

Address: 0x3F, Reset: 0x20, Name: IDAC_GAIN_ADJ

Table 83. Bit Descriptions for IDAC_GAIN_ADJ

Bits

Bit Name

Settings Description

Reset

Access

[5:0]

IDAC_GAIN_ADJ

This register is the 6-bit digital gain adjust on the I channel. The bit weighting is MSB

= 2⁰, LSB = 2⁻⁵, which yields a multiplier range of 0 to 2 or −∞to 6 dB. The default

0x20

RW

gain setting is 0x20, which maps to unity gain (0 dB).

Rev. A | Page 65 of 72

AD9142A

Data Sheet

QDAC GAIN ADJUST REGISTER

Address: 0x40, Reset: 0x20, Name: QDAC_GAIN_ADJ

Table 84. Bit Descriptions for QDAC_GAIN_ADJ

Bits

Bit Name

Settings Description

Reset

Access

[5:0]

QDAC_GAIN_ADJ

This register is the 6-bit digital gain adjust on the Q channel. The bit weighting 0x20

is MSB = 2⁰, LSB = 2⁻⁵, which yields a multiplier range of 0 to 2 or −∞ to 6 dB. The

default gain setting is 0x20, which maps to unity gain (0 dB).

RW

GAIN STEP CONTROL 0 REGISTER

Address: 0x41, Reset: 0x01, Name: GAIN_STEP_CTRL0

Table 85. Bit Descriptions for GAIN_STEP_CTRL0

Bits

Bit Name

Settings Description

Reset

Access

[5:0]

RAMP_UP_STEP

This register sets the step size of the increasing gain. The digital gain increases by the 0x01

configured amount in every four DAC cycles until the gain reaches the setting in

IDAC_GAIN_ADJ (Register 0x3F). The bit weighting is MSB = 2¹, LSB = 2⁻⁴. Note that

the value in this register must not be greater than the values in the IDAC_GAIN_ADJ.

RW

GAIN STEP CONTROL 1 REGISTER

Address: 0x42, Reset: 0x41, Name: GAIN_STEP_CTRL1

Table 86. Bit Descriptions for GAIN_STEP_CTRL1

Bits Bit Name

Settings Description

This bit allows for turning the DAC output on and off manually. The digital

Reset

Access

7

DAC_OUTPUT_OFF

0x0

RW

IQ gain function (Register 0x27, Bit 5) must be turned on for this bit to function.

6

DAC_OUTPUT_STATUS

This bit indicates the DAC output on/off status. When the DAC output is turned

off, this bit is 1. Upon power-up, this bit is 1. The digital IQ gain function

(Register 0x27, Bit 5) must be turned on for this bit to track the on/off status

0x1

R

[5:0] RAMP_DOWN_STEP

This register sets the step size of the decreasing gain. The digital gain

decreases by the configured amount in every four DAC cycles until the gain

reaches zero. The bit weighting is MSB = 2¹, LSB = 2⁻⁴. Note that the value in

this register must not be greater than the values in the IDAC_GAIN_ADJ

(Register 0x3F).

0x01

RW

TX ENABLE CONTROL REGISTER

Address: 0x43, Reset: 0x07, Name: TX_ENABLE_CTRL

Table 87. Bit Descriptions for TX_ENABLE_CTRL

Bits Bit Name

Settings

Description

Reset

Access

2

TXENABLE_GAINSTEP_EN

DAC output gradually turns on/off under the control of the

TXENABLE signal from the TXEN pin according to the settings

in Register 0x41 and Register 0x42.

1

RW

1

0

TXENABLE_SLEEP_EN

When set to 1, the device is put in sleep mode when the

TXENABLE signal from the TXEN pin is low.

1

RW

TXENABLE_POWER_DOWN_EN

When set to 1, the device is put in power down mode when

the TXENABLE signal from the TXEN pin is low.

Rev. A | Page 66 of 72

Data Sheet

AD9142A

DAC OUTPUT CONTROL REGISTER

Address: 0x44, Reset: 0x8D, Name: DAC_OUTPUT_CTRL

Table 88. Bit Descriptions for DAC_OUTPUT_CTRL

Bits Bit Name

Settings

Description

Reset

0x1

Access

7

DAC_OUTPUT_CTRL_EN

Enables the DAC output control. This bit needs to be set to 1

to enable the remaining bits in this register.

RW

3

FIFO_WARNING_SHUTDOWN_EN

When this bit and Bit 7 are both high, if a FIFO warning occurs, 0x1

the DAC output shuts down automatically. By default, this

function is on.

RW

2

0

OVERTHRESHOLD_SHUTDOWN_EN

FIFO_ERROR_SHUTDOWN_EN

The DAC output is turned off when the input average power is 0x1

greater than the predefined threshold.

RW

The DAC output is turned off when the FIFO reports warnings. 0x1

DLL CELL ENABLE 0 REGISTER

Address: 0x5E, Reset: 0xFF, Name: ENABLE_DLL_DELAY_CELL0

Table 89. Bit Descriptions for ENABLE_DLL_DELAY_CELL0

Bits

Bit Name

Description

Reset

Access

[7:0]

DELAY_CELL_ENABLE [7:0]

Set each bit to enable or disable the delay cell. Delay cell number

corresponds to bit number.

0xFF

RW

1 = enable delay cell (default).

0 = disable delay cell.

Different recommended values should be used in DLL mode and

delay line mode. See the Data Interface section.

DLL CELL ENABLE 1 REGISTER

Address: 0x5F, Reset: 0x67, Name: ENABLE_DLL_DELAY_CELL1

Table 90. Bit Descriptions for ENABLE_DLL_DELAY_CELL1

Bits

[7:3]

[2:0]

Bit Name

Description

Reset

Access

RW

Reserved

Must write the default value for optimal performance.

0x0C

DELAY_CELL_ENABLE [10:8]

Set each bit to enable or disable the delay cell. Delay cell numbers 0x7

are 10, 9, 8 corresponding to bits Bit, Bit 2, and Bit 0, respectively.

RW

1 = enable delay cell (default).

0 = disable delay cell.

SED CONTROL REGISTER

Address: 0x60, Reset: 0x00, Name: SED_CTRL

Table 91. Bit Descriptions for SED_CTRL

Bits

Bit Name

Description

Reset

Access

RW

7

SED_ENABLE

SED_ERR_CLEAR

Set to 1 to Enable the SED compare logic.

0

6

When set to 1, clears all SED reported error bits, Bit 2, Bit 1, and Bit

0.

RW

5

AED_ENABLE

When set to 1, enables the AED function (SED with auto clear after

eight passing sets).

0

RW

4

3

2

1

0

SED_DEPTH

Reserved

AED_PASS

AED_FAIL

SED_FAIL

0 = SED depth of two words, 1 = SED depth of four words.

Reserved.

0

RW

R

When AED = 1, it signals eight true compare cycles.

When AED = 1, it signals a mismatch in comparison.

RW

R

Signals that an SED mismatch in comparison occurred (with SED

or AED enabled).

R

Rev. A | Page 67 of 72

AD9142A

Data Sheet

SED PATTERN I0 LOW BITS REGISTER

Address: 0x61, Reset: 0x00, Name: SED_PATT_L_I0

Table 92. Bit Descriptions for SED_PATT_L_I0

Bits

Bit Name

Description

Reset

Access

[7:0]

SED_PATTERN_RISE_I0[7:0]

SED I0 rising edge low bits.

0x00

RW

SED PATTERN I0 HIGH BITS REGISTER

Address: 0x62, Reset: 0x00, Name: SED_PATT_H_I0

Table 93. Bit Descriptions for SED_PATT_H_I0

Bits

Bit Name

Description

Reset

Access

[7:0]

SED_PATTERN_RISE_I0[15:8]

SED I0 rising edge high bits.

0x00

RW

SED PATTERN Q0 LOW BITS REGISTER

Address: 0x63, Reset: 0x00, Name: SED_PATT_L_Q0

Table 94. Bit Descriptions for SED_PATT_L_Q0

Bits

Bit Name

Description

Reset

Access

[7:0]

SED_PATTERN_FALL_Q0[7:0]

SED Q0 falling edge low bits.

0x00

RW

SED PATTERN Q0 HIGH BITS REGISTER

Address: 0x64, Reset: 0x00, Name: SED_PATT_H_Q0

Table 95. Bit Descriptions for SED_PATT_H_Q0

Bits

Bit Name

Description

Reset

Access

[7:0]

SED_PATTERN_FALL_Q0[15:8]

SED Q0 falling edge high bits.

0x00

RW

SED PATTERN I1 LOW BITS REGISTER

Address: 0x65, Reset: 0x00, Name: SED_PATT_L_I1

Table 96. Bit Descriptions for SED_PATT_L_I1

Bits

Bit Name

Description

Reset

Access

[7:0]

SED_PATTERN_RISE_I1[7:0]

SED I1 rising edge low bits.

0x00

RW

SED PATTERN I1 HIGH BITS REGISTER

Address: 0x66, Reset: 0x00, Name: SED_PATT_H_I1

Table 97. Bit Descriptions for SED_PATT_H_I1

Bits

Bit Name

Description

Reset

Access

[2:0]

SED_PATTERN_RISE_I1[15:8]

SED I1 rising edge high bits.

0x00

RW

SED PATTERN Q1 LOW BITS REGISTER

Address: 0x67, Reset: 0x00, Name: SED_PATT_L_Q1

Table 98. Bit Descriptions for SED_PATT_L_Q1

Bits

Bit Name

Description

Reset

Access

[7:0]

SED_PATTERN_FALL_Q1[7:0]

SED Q1 falling edge low bits.

0x00

RW

Rev. A | Page 68 of 72

Data Sheet

AD9142A

SED PATTERN Q1 HIGH BITS REGISTER

Address: 0x68, Reset: 0x00, Name: SED_PATT_H_Q1

Table 99. Bit Descriptions for SED_PATT_H_Q1

Bits

Bit Name

Description

Reset

Access

[2:0]

SED_PATTERN_FALL_Q1[15:8]

SED Q1 falling edge high bits.

0x00

RW

PARITY CONTROL REGISTER

Address: 0x6A, Reset: 0x00, Name: PARITY_CTRL

Table 100. Bit Descriptions for PARITY_CTRL

Bits

7

Bit Name

Settings

Description

Reset

Access

RW

PARITY_ENABLE

PARITY_EVEN

1

0

1

Enable parity.

0

6

Odd parity.

Even parity.

RW

5

PARITY_ERR_CLEAR

Reserved

Set to 1 to clear parity error counters.

Reserved.

0

RW

R

[4:2]

1

0x0

0

PARERRFAL

When 1, signals a falling edge parity error was detected.

When 1, signals a rising edge parity error was detected.

R

0

PARERRRISE

0

R

PARITY ERROR RISING EDGE REGISTER

Address: 0x6B, Reset: 0x00, Name: PARITY_ERR_RISING

Table 101. Bit Descriptions for PARITY_ERR_RISING

Bits

Bit Name

Description

Reset

Access

[7:0]

Parity Rising Edge Error Count

Number of rising edge-based errors detected (S0 and S2). Clipped 0x00

to 256.

R

PARITY ERROR FALLING EDGE REGISTER

Address: 0x6C, Reset: 0x00, Name: PARITY_ERR_FALLING

Table 102. Bit Descriptions for PARITY_ERR_FALLING

Bits

Bit Name

Description

Reset

Access

[7:0]

Parity Falling Edge Error Count

Number of falling edge-based errors detected (S1 and S3).

Clipped to 256.

0x00

R

VERSION REGISTER

Address: 0x7F, Reset: 0x0B, Name: Version

Table 103. Bit Descriptions for Version

Bits

Bit Name

Settings Description

Reset

0x0B

Access

[7:0]

Version

Chip version.

R

Rev. A | Page 69 of 72

AD9142A

Data Sheet

DAC LATENCY AND SYSTEM SKEWS

DACCLK/8

DACCLK

DIV 2

DACCLK/4

DACCLK/2

FIFO

RdPtr

I AND

Q DAC

DATA

INTERFACE

OTHER DIGITAL

FUNCTIONALITIES

FIFO

HB1

HB2

HB3

FIFO

WrPtr

DCI

FIXED

LATENCY

VARYING

LATENCY

VARYING

LATENCY

FIXED

LATENCY

Figure 62. Breakdown of Pipeline Latencies

FIFO

DAC LATENCY VARIATIONS

DATA 0

DATA 1

DATA 0

DATA 1

FIFO

WrPtr

DACs, like any other devices with internal multiphase clocks,

have an inherent pipeline latency variation. Figure 62 shows the

delineation of pipeline latencies in the AD9142A. The

highlighted section, including the FIFO and the clock generation

circuitry, is where the pipeline latencies vary. Upon each power-

on, the status of both the FIFO and the clock generation state

machine is arbitrary. This leads to varying latency in these two

blocks.

FIFO

RdPtr

DATA 2

DATA 3

DATA 4

DATA 5

DATA 2

DATA 3

DATA 4

DATA 5

FIFO

RdPtr

FIFO

WrPtr

DATA 6

DATA 7

DATA 6

DATA 7

CASE 1:

LATENCY = 4 DCI CYCLES

CASE 2:

LATENCY = 6 DCI CYCLES

FIFO LATENCY VARIATION

There are eight data slots in the FIFO. The FIFO read and write

pointers circulate the FIFO from Slot 0 to Slot 7 and back to Slot 0.

The FIFO depth is defined as the number of FIFO slots that are

required for the read pointer to catch the write pointer. It is also

the time a particular piece of data stays in the FIFO from the

point that it is written into the FIFO to the point where it is read

out from the FIFO. Therefore, the latency of the FIFO is equivalent

to its depth.

Figure 63. Example of FIFO Latency Difference

Figure 64 shows two equivalent cases of FIFO latency of four data

cycles. Although neither the read nor the write pointer match

each other in these two cases, the FIFO depth is the same in both

cases. Also, note that the beginning slots of the data stream in the

two cases are not the same, but the read and write pointers point

to the same piece of data in both cases. This does not affect the

alignment accuracy of the DAC outputs as long as the data and

the DCIs are well aligned at multiple devices.

Figure 63 is an example of FIFO latency variation. The latency in

Case 2 is two data cycles longer than that in Case 1. If other

latencies are the same, the skew between the DAC outputs in

these two cases is, likewise, two data cycles. Therefore, to keep a

constant FIFO latency, the FIFO depth needs to be reset to a pre-

defined value. Theoretically, any value other than 0 is valid but

typically it is set to 4 to maximize the capacity of absorbing the

rate fluctuation between the read and write sides.

FIFO

DATA 0

DATA 1

DATA 5

DATA 6

FIFO

WrPtr

FIFO

DATA 2

DATA 3

DATA 4

DATA 5

DATA 7

DATA 0

DATA 1

DATA 2

RdPtr

LATENCY = 4 DCI CYCLES

FIFO

RdPtr

FIFO

WrPtr

DATA 6

DATA 7

DATA 3

DATA 4

Figure 64. Example of Equal FIFO Latencies

Rev. A | Page 70 of 72

Data Sheet

AD9142A

CLOCK GENERATION LATENCY VARIATION

CORRECTING SYSTEM SKEWS

The state machine of the clock generation circuitry is another

source of latency variations; this type of latency variation results

from inherent phase uncertainty of the static frequency dividers.

The divided down clock can be high or low at the rising edge of

the input clock, unless specifically forced to a known state. This

means that whenever there is interpolation (when slower clocks

must be internally generated by dividing down the DACCLK),

there is an inherent latency variation in the DAC. Figure 65 is an

example of this latency variation in 2× interpolation.

Generally, it is assumed that the input data and the DCI among

multiple devices are well aligned to each other. Depending on the

system design, the data and DCI being input into each DAC can

originate from various FPGAs or ASICs. Without synchronizing

the data sources, the output of one data source can be skewed

from that of another. The alignment between multiple data

sources can also drift over temperature.

Figure 66 shows an example of a 2-channel transmitter with two

data sources and two dual DACs. A constant but unknown phase

offset appears between the outputs of the DAC devices, even if

the DAC does not introduce any latency variations. The

multidevice synchronization in the AD9142A can be used to

compensate the skew due to misalignment of the data sources by

resetting the two sides of the FIFO independently through two

external reference clocks: the frame and the sync clock. The offset

between the two data sources is then absorbed by the FIFO and

clock generation block in the DAC. For more information about

using the multidevice synchronization function, refer to the

Synchronization Implementation section.

There are two phase possibilities in the DACCLK/2 clock. The

DACCLK/2 clock is used to read data from the FIFO and to drive

the interpolation filter. Regardless of which clock edge is used to

drive the digital circuit, there is a latency of one DAC clock cycle

between Case 1 and Case 2 (see Figure 65). Because the power-

on state arbitrarily falls in one of the two cases, the phase

uncertainty of the divider appears as a varying skew between two

DAC outputs.

DCI

HB1

HB2

HB3

FRAME

DAC

16-BIT DATA

DATA

GEN

DCI

DACCLK

FRAME

DAC

16-BIT DATA

DACCLK/2

(CASE 1)

DCI

FRAME

DAC

16-BIT DATA

DATA

DACCLK/2

(CASE 2)

GEN

DCI

FRAME

DAC

LATENCY VARIATION = 1 DACCLK CYCLE

16-BIT DATA

Figure 65. Latency Variation in 2× Interpolation from Clock Generation

2

4

MASTER

SYNC CLOCK

REF CLOCK

DATA SKEW

Figure 66. DAC Output Skew from Skewed Input Data and DCI

Rev. A | Page 71 of 72

AD9142A

Data Sheet

PACKAGING AND ORDERING INFORMATION

OUTLINE DIMENSIONS

10.10

10.00 SQ

9.90

0.60

0.42

0.24

0.30

0.23

0.18

0.60

0.42

0.24

PIN 1

INDICATOR

55

54

72

1

PIN 1

INDICATOR

9.85

0.50

BSC

9.75 SQ

9.65

6.15

6.00 SQ

5.85

EXPOSED

PAD

0.50

0.40

0.30

18

19

37

36

0.25 MIN

TOP VIEW

BOTTOM VIEW

8.50 REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

COPLANARITY

0.08

SEATING

PLANE

0.20 REF

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4

Figure 67. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

10 mm × 10 mm Body, Very Thin Quad

(CP-72-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

AD9142ABCPZ

AD9142ABCPZRL

AD9142A-M5372-EBZ

AD9142A-M5375-EBZ

Temperature Range

−40°C to +85°C

Package Description

Package Option

CP-72-7

72-Lead LFCSP_VQ

Evaluation Board Connected to ADL5372 Modulator

Evaluation Board Connected to ADL5375 Modulator

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D11901-0-5/14(A)

Rev. A | Page 72 of 72


型号：	AD9142A
厂家：	ADI
描述：	Multiple chip synchronization
文件：	总73页 (文件大小：1524K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9142A [ADI]

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AD9144

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