AD9200JRSRL_技术文档

Complete 10-Bit, 20 MSPS, 80 mW

CMOS A/D Converter

a

AD9200

FEATURES

A single clock input is used to control all internal conversion

cycles. The digital output data is presented in straight binary

output format. An out-of-range signal (OTR) indicates an over-

flow condition which can be used with the most significant bit

to determine low or high overflow.

CMOS 10-Bit, 20 MSPS Sampling A/D Converter

Pin-Compatible with AD876

Power Dissipation: 80 mW (3 V Supply)

Operation Between 2.7 V and 5.5 V Supply

Differential Nonlinearity: 0.5 LSB

Power-Down (Sleep) Mode

Three-State Outputs

Out-of-Range Indicator

Built-In Clamp Function (DC Restore)

Adjustable On-Chip Voltage Reference

IF Undersampling to 135 MHz

The AD9200 can operate with supply range from 2.7 V to

5.5 V, ideally suiting it for low power operation in high speed

portable applications.

The AD9200 is specified over the industrial (–40°C to +85°C)

and commercial (0°C to +70°C) temperature ranges.

PRODUCT HIGHLIGHTS

Low Power

PRODUCT DESCRIPTION

The AD9200 is a monolithic, single supply, 10-bit, 20 MSPS

analog-to-digital converter with an on-chip sample-and-hold

amplifier and voltage reference. The AD9200 uses a multistage

differential pipeline architecture at 20 MSPS data rates and

guarantees no missing codes over the full operating temperature

range.

The AD9200 consumes 80 mW on a 3 V supply (excluding the

reference power). In sleep mode, power is reduced to below

5 mW.

Very Small Package

The AD9200 is available in both a 28-lead SSOP and 48-lead

LQFP packages.

The input of the AD9200 has been designed to ease the devel-

opment of both imaging and communications systems. The user

can select a variety of input ranges and offsets and can drive the

input either single-ended or differentially.

Pin Compatible with AD876

The AD9200 is pin compatible with the AD876, allowing older

designs to migrate to lower supply voltages.

300 MHz On-Board Sample-and-Hold

The versatile SHA input can be configured for either single-

ended or differential inputs.

The sample-and-hold (SHA) amplifier is equally suited for both

multiplexed systems that switch full-scale voltage levels in suc-

cessive channels and sampling single-channel inputs at frequen-

cies up to and beyond the Nyquist rate. AC coupled input

signals can be shifted to a predetermined level, with an onboard

clamp circuit (AD9200ARS, AD9200KST). The dynamic per-

formance is excellent.

Out-of-Range Indicator

The OTR output bit indicates when the input signal is beyond

the AD9200’s input range.

Built-In Clamp Function

Allows dc restoration of video signals with AD9200ARS and

AD9200KST.

The AD9200 has an onboard programmable reference. An

external reference can also be chosen to suit the dc accuracy and

temperature drift requirements of the application.

FUNCTIONAL BLOCK DIAGRAM

CLAMP

IN

CLK

AVDD

DRVDD

CLAMP

STBY

SHA

GAIN

SHA

GAIN

SHA

GAIN

SHA

GAIN

SHA

MODE

AIN

REFTS

REFBS

A/D

THREE-

STATE

D/A

A/D

D/A

A/D

REFTF

REFBF

CORRECTION LOGIC

OUTPUT BUFFERS

OTR

VREF

D9

(MSB)

AD9200

1V

REFSENSE

D0

(LSB)

DRVSS

AVSS

REV. E

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(AVDD = +3 V, DRVDD = +3 V, F_S= 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input

AD9200–SPECIFICATIONS ^{Span from 0.5 V to 2.5 V, External Reference, T}_MINto T_MAXunless otherwise noted)

Parameter

Symbol Min

Typ Max

Units

Bits

Condition

RESOLUTION

CONVERSION RATE

10

F_S

20

MHz

DC ACCURACY

Differential Nonlinearity

Integral Nonlinearity

Offset Error

DNL

INL

E_ZS

±0.5 ±1

±0.75 ±2

LSB

% FSR

REFTS = 2.5 V, REFBS = 0.5 V

0.4

1.4

1.2

3.5

Gain Error

E_FS

REFERENCE VOLTAGES

Top Reference Voltage

REFTS

1

AVDD

V

Bottom Reference Voltage

Differential Reference Voltage

Reference Input Resistance¹

REFBS GND

AVDD – 1

V

2

10

4.2

V p-p

kΩ

REFTS, REFBS: MODE = AVDD

Between REFTF and REFBF: MODE = AVSS

ANALOG INPUT

Input Voltage Range

Input Capacitance

Aperture Delay

Aperture Uncertainty (Jitter)

Input Bandwidth (–3 dB)

Full Power (0 dB)

AIN

C_IN

t_AP

t_AJ

BW

REFBS

REFTS

V

REFBS Min = GND: REFTS Max = AVDD

Switched

1

4

2

pF

ns

ps

300

23

MHz

µA

DC Leakage Current

Input = ±FS

INTERNAL REFERENCE

Output Voltage (1 V Mode)

Output Voltage Tolerance (1 V Mode)

Output Voltage (2 V Mode)

Load Regulation (1 V Mode)

VREF

1

V

mV

V

REFSENSE = VREF

±10 ±25

2

0.5

REFSENSE = GND

1 mA Load Current

2

mV

POWER SUPPLY

Operating Voltage

AVDD

2.7

3

5.5

V

mA

mW

DRVDD 2.7

IAVDD

P_D

Supply Current

Power Consumption

Power-Down

26.6 33.3

80

4

AVDD = 3 V, MODE = AVSS

AVDD = DRVDD = 3 V, MODE = AVSS

STBY = AVDD, MODE and CLOCK =

AVSS

100

Gain Error Power Supply Rejection

PSRR

1

% FS

DYNAMIC PERFORMANCE (AIN = 0.5 dBFS)

Signal-to-Noise and Distortion

f = 3.58 MHz

f = 10 MHz

SINAD

54.5

57

54

dB

Effective Bits

f = 3.58 MHz

f = 10 MHz

9.1

8.6

Bits

Signal-to-Noise

f = 3.58 MHz

f = 10 MHz

SNR

55

57

56

dB

Total Harmonic Distortion

f = 3.58 MHz

f = 10 MHz

Spurious Free Dynamic Range

f = 3.58 MHz

f = 10 MHz

THD

SFDR

–59

–61

–66

–58

dB

–69

–61

dB

Two-Tone Intermodulation

Distortion

Differential Phase

Differential Gain

IMD

DP

DG

68

0.1

0.05

dB

f = 44.49 MHz and 45.52 MHz

Degree NTSC 40 IRE Mod Ramp

%

REV. E

–2–

AD9200

Parameter

Symbol

Min

Typ

Max

Units

Condition

DIGITAL INPUTS

High Input Voltage

Low Input Voltage

V_IH

V_IL

2.4

V

0.3

DIGITAL OUTPUTS

High-Z Leakage

Data Valid Delay

Data Enable Delay

Data High-Z Delay

I_OZ

t_OD

t_DEN

t_DHZ

–10

+10

µA

ns

Output = GND to VDD

C_L= 20 pF

25

13

LOGIC OUTPUT (with DRVDD = 3 V)

High Level Output Voltage (I_OH= 50 µA)

High Level Output Voltage (I_OH= 0.5 mA)

Low Level Output Voltage (I_OL= 1.6 mA)

Low Level Output Voltage (I_OL= 50 µA)

V_OH

V_OL

+2.95

+2.80

V

+0.4

+0.05

LOGIC OUTPUT (with DRVDD = 5 V)

High Level Output Voltage (I_OH= 50 µA)

High Level Output Voltage (I_OH= 0.5 mA)

Low Level Output Voltage (I_OL= 1.6 mA)

Low Level Output Voltage (I_OL= 50 µA)

V_OH

V_OL

+4.5

+2.4

V

+0.4

+0.1

CLOCKING

Clock Pulsewidth High

Clock Pulsewidth Low

Pipeline Latency

t_CH

t_CL

22.5

ns

Cycles

3

CLAMP²

Clamp Error Voltage

Clamp Pulsewidth

E_OC

t_CPW

±20

2

±40

mV

µs

CLAMPIN = 0.5 V–2.7 V, R_IN= 10 Ω

C_IN= 1 µF (Period = 63.5 µs)

NOTES

¹See Figures 1a and 1b.

²Available only in AD9200ARS and AD9200KST.

Specifications subject to change without notice.

REFTS

10k⍀

REFTS

AD9200

REFTF

REFBF

4.2k⍀

REFBS

MODE

0.4

؋

V

DD

REFBS

MODE

AV

DD

Figure 1a.

Figure 1b.

REV. E

–3–

AD9200

ABSOLUTE MAXIMUM RATINGS*

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum

ratings for extended periods may effect device reliability.

With

Respect

to

Parameter

Min

Max

Units

ORDERING GUIDE

AVDD

DRVDD

AVSS

AVDD

MODE

CLK

Digital Outputs

AIN

VREF

REFSENSE

REFTF, REFTB

REFTS, REFBS

Junction Temperature

Storage Temperature

Lead Temperature

10 sec

AVSS

DRVSS

DRVDD –6.5

AVSS

DRVSS

AVSS

–0.3

+6.5

+0.3

+6.5

AVDD + 0.3

DRVDD + 0.3 V

AVDD + 0.3

+150

V

Temperature Package

Package

Options*

Model

Range

Description

–0.3

AD9200JRS

AD9200ARS

AD9200JST

AD9200KST

0°C to +70°C

28-Lead SSOP

RS-28

ST-48

–40°C to +85°C 28-Lead SSOP

0°C to +70°C

48-Lead LQFP

V

°C

AD9200JRSRL 0°C to +70°C

28-Lead SSOP (Reel) RS-28

AD9200ARSRL –40°C to +85°C 28-Lead SSOP (Reel) RS-28

AD9200JSTRL 0°C to +70°C

AD9200KSTRL 0°C to +70°C

AD9200 SSOP-EVAL

48-Lead LQFP (Reel) ST-48

Evaluation Board

–65

+150

AD9200 LQFP-EVAL

Evaluation Board

*RS = Shrink Small Outline; ST = Thin Quad Flatpack.

+300

°C

AVDD

DRVDD

AVDD

AVSS

DRVSS

AVSS

a. D0–D9, OTR

b. Three-State, Standby, Clamp

c. CLK

AVDD

REFTF

REFBS

AVDD

AVSS

AVDD

REFTS

REFBF

AVSS

d. AIN

e. Reference

AVDD

AVSS

f. CLAMPIN

g. MODE

h. REFSENSE

i. VREF

Figure 2. Equivalent Circuits

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD9200 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. E

–4–

AD9200

PIN CONFIGURATIONS

28-Lead Shrink Small Outline (SSOP)

48-Lead Plastic Thin Quad Flatpack (LQFP)

AVDD

AIN

AVSS

DRVDD

D0

1

2

28

27

48 47 46 45 44 43 42 41 40 39 38 37

3

26 VREF

1

2

D0

D1

D2

D3

D4

NC

D5

D6

D7

D8

D9

36

35

34

33

32

31

30

29

28

27

26

25

NC

D1

REFBS

25

4

PIN 1

IDENTIFIER

REFBS

REFBF

NC

D2

REFBF

24

5

3

AD9200

TOP VIEW

(Not to Scale)

D3

6

23

22

21

20

19

18

17

16

15

MODE

REFTF

REFTS

4

5

D4

7

MODE

NC

AD9200

TOP VIEW

(Not to Scale)

6

8

D5

D6

D7

7

REFTF

REFTS

CLAMPIN

CLAMP

REFSENSE

NC

9

CLAMPIN

CLAMP

8

10

11

12

13

14

9

D8

D9

REFSENSE

STBY

10

11

12

OTR

THREE-STATE

CLK

DRVSS

13 14 15 16 17 18 19 20 21 22 23 24

NC = NO CONNECT

PIN FUNCTION DESCRIPTIONS

SSOP

Pin No.

LQFP

Pin No.

Name

Description

1

2

3

44

45

1

AVSS

DRVDD

D0

Analog Ground

Digital Driver Supply

Bit 0, Least Significant Bit

4

2

D1

Bit 1

5

3

D2

Bit 2

6

7

4

5

D3

D4

Bit 3

Bit 4

8

D5

Bit 5

9

D6

D7

D8

D9

OTR

DRVSS

CLK

THREE-STATE

STBY

REFSENSE

CLAMP

CLAMPIN

REFTS

REFTF

MODE

REFBF

REFBS

VREF

AIN

Bit 6

Bit 7

Bit 8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

10

11

12

16

17

22

23

24

26

27

28

29

30

32

34

35

38

39

42

Bit 9, Most Significant Bit

Out-of-Range Indicator

Digital Ground

Clock Input

HI: High Impedance State. LO: Normal Operation

HI: Power-Down Mode. LO: Normal Operation

Reference Select

HI: Enable Clamp Mode. LO: No Clamp

Clamp Reference Input

Top Reference

Top Reference Decoupling

Mode Select

Bottom Reference Decoupling

Bottom Reference

Internal Reference Output

Analog Input

AVDD

Analog Supply

REV. E

–5–

AD9200

DEFINITIONS OF SPECIFICATIONS

Offset Error

Integral Nonlinearity (INL)

The first transition should occur at a level 1 LSB above “zero.”

Offset is defined as the deviation of the actual first code transi-

tion from that point.

Integral nonlinearity refers to the deviation of each individual

code from a line drawn from “zero” through “full scale”. The

point used as “zero” occurs 1/2 LSB before the first code transi-

tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last

code transition. The deviation is measured from the center of

each particular code to the true straight line.

Gain Error

The first code transition should occur for an analog value 1 LSB

above nominal negative full scale. The last transition should

occur for an analog value 1 LSB below the nominal positive full

scale. Gain error is the deviation of the actual difference be-

tween first and last code transitions and the ideal difference

between the first and last code transitions.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. It is often

specified in terms of the resolution for which no missing codes

(NMC) are guaranteed.

Pipeline Delay (Latency)

The number of clock cycles between conversion initiation and

the associated output data being made available. New output

data is provided every rising edge.

(AVDD = +3 V, DRVDD = +3 V, F_S= 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input

Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted)

Typical Characterization Curves

60

1.0

–0.5 AMPLITUDE

55

–6.0 AMPLITUDE

50

45

0.5

0

–20.0 AMPLITUDE

40

35

30

25

–0.5

–1.0

20

1.00E+05

1.00E+06

1.00E+07

1.00E+08

0

128

256

384

512

640

768

896 1024

INPUT FREQUENCY – Hz

CODE OFFSET

Figure 5. SNR vs. Input Frequency

Figure 3. Typical DNL

60

55

50

45

40

35

30

1.0

0.5

–0.5 AMPLITUDE

–6.0 AMPLITUDE

0

–20.0 AMPLITUDE

–0.5

–1.0

25

20

1.00E+05

1.00E+06

1.00E+07

1.00E+08

0

128

256

384

512

640

768

896 1024

INPUT FREQUENCY – Hz

CODE OFFSET

Figure 6. SINAD vs. Input Frequency

Figure 4. Typical INL

REV. E

–6–

AD9200

–30

–35

–40

80.5

80.0

79.5

79.0

78.5

78.0

77.5

77.0

CLOCK = 20MHz

–20.0 AMPLITUDE

–6.0 AMPLITUDE

–45

–50

–55

–60

–65

–70

–0.5 AMPLITUDE

1.00E+06

–75

–80

1.00E+05

1.00E+07

1.00E+08

100E+06

100

0

2

4

6

8

10

12

14

16

18

20

INPUT FREQUENCY – Hz

CLOCK FREQUENCY – MHz

Figure 7. THD vs. Input Frequency

Figure 10. Power Consumption vs. Clock Frequency

(MODE = AVSS)

–70

–60

–50

–40

–30

–20

–10

1M

900k

800k

700k

600k

F

= 1MHz

IN

499856

500k

400k

300k

200k

100k

0

54383

N–1

54160

N+1

0

100E+03

1E+06

10E+06

N

CLOCK FREQUENCY – Hz

CODE

Figure 8. THD vs. Clock Frequency

Figure 11. Grounded Input Histogram

20

0

1.005

1.004

1.003

1.002

1.001

1.000

0.999

0.998

CLOCK = 20MHz

–20

–40

–60

–80

–100

–120

–140

–40

–20

0

20

40

60

80

0E+0 1E+6 2E+6 3E+6 4E+6 5E+6 6E+6 7E+6 8E+6 9E+6 10E+6

SINGLE TONE FREQUENCY DOMAIN

TEMPERATURE – °C

Figure 9. Voltage Reference Error vs. Temperature

Figure 12. Single-Tone Frequency Domain

REV. E

–7–

AD9200

0

–3

–6

–9

APPLYING THE AD9200

THEORY OF OPERATION

The AD9200 implements a pipelined multistage architecture to

achieve high sample rate with low power. The AD9200 distrib-

utes the conversion over several smaller A/D subblocks, refining

the conversion with progressively higher accuracy as it passes

the results from stage to stage. As a consequence of the distrib-

uted conversion, the AD9200 requires a small fraction of the

1023 comparators used in a traditional flash type A/D. A

sample-and-hold function within each of the stages permits the

first stage to operate on a new input sample while the second,

third and fourth stages operate on the three preceding samples.

–12

–15

–18

–21

–24

–27

1.0E+6

10.0E+6

100.0E+6

1.0E+9

OPERATIONAL MODES

FREQUENCY – Hz

The AD9200 is designed to allow optimal performance in a

wide variety of imaging, communications and instrumentation

applications, including pin compatibility with the AD876 A/D.

To realize this flexibility, internal switches on the AD9200 are

used to reconfigure the circuit into different modes. These modes

are selected by appropriate pin strapping. There are three parts

of the circuit affected by this modality: the voltage reference, the

reference buffer, and the analog input. The nature of the appli-

cation will determine which mode is appropriate: the descrip-

tions in the following sections, as well as the Table I should

assist in picking the desired mode.

Figure 13. Full Power Bandwidth

25

20

15

10

REFBS = 0.5V

REFTS = 2.5V

CLOCK = 20MHz

5

0

–5

–10

–15

–20

–25

0

0.5

1.0

1.5

2.0

2.5

3.0

INPUT VOLTAGE – V

Figure 14. Input Bias Current vs. Input Voltage

Table I. Mode Selection

Input

Connect

Input

Span

MODE

REFSENSE

Modes

REF

REFTS

REFBS

Figure

TOP/BOTTOM AIN

AIN

1 V

2 V

AVDD

Short REFSENSE, REFTS and VREF Together

AGND Short REFTS and VREF Together

AGND

18

19

CENTER SPAN AIN

AIN

1 V

2 V

AVDD/2 Short VREF and REFSENSE Together

AVDD/2 AGND No Connect

AVDD/2 Short VREF and REFSENSE Together

AVDD/2

AVDD/2 20

AVDD/2

Differential

AIN Is Input 1

1 V

AVDD/2

AVDD/2 29

REFTS and

REFBS Are

Shorted Together

for Input 2

2 V

AVDD/2 AGND

No Connect

AVDD/2

External Ref

AD876

AIN

2 V max AVDD

AVDD

Span = REFTS

21, 22

23

– REFBS (2 V max)

AGND

Short to

VREFTF

VREFBF

AIN

2 V

Float or AVDD

AVSS

No Connect

Short to

30

VREFTF

VREFBF

REV. E

–8–

AD9200

SUMMARY OF MODES

VOLTAGE REFERENCE

1 V Mode the internal reference may be set to 1 V by connect-

ing REFSENSE and VREF together.

AIN

A/D

CORE

SHA

REFTS

2 V Mode the internal reference my be set to 2 V by connecting

REFSENSE to analog ground

AD9200

External Divider Mode the internal reference may be set to a

point between 1 V and 2 V by adding external resistors. See

Figure 16f.

REFBS

Figure 15. AD9200 Equivalent Functional Input Circuit

In single-ended operation, the input spans the range,

REFBS ≤ AIN ≤ REFTS

External Reference Mode enables the user to apply an exter-

nal reference to REFTS, REFBS and VREF pins. This mode

is attained by tying REFSENSE to VDD.

where REFBS can be connected to GND and REFTS con-

nected to VREF. If the user requires a different reference range,

REFBS and REFTS can be driven to any voltage within the

power supply rails, so long as the difference between the two is

between 1 V and 2 V.

REFERENCE BUFFER

Center Span Mode midscale is set by shorting REFTS and

REFBS together and applying the midscale voltage to that point

The MODE pin is set to AVDD/2. The analog input will swing

about that midscale point.

In differential operation, REFTS and REFBS are shorted to-

gether, and the input span is set by VREF,

Top/Bottom Mode sets the input range between two points.

The two points are between 1 V and 2 V apart. The Top/Bottom

Mode is enabled by tying the MODE pin to AVDD.

(REFTS – VREF/2) ≤ AIN ≤ (REFTS + VREF/2)

where VREF is determined by the internal reference or brought

in externally by the user.

ANALOG INPUT

Differential Mode is attained by driving the AIN pin as one

differential input and shorting REFTS and REFBS together and

driving them as the second differential input. The MODE pin

is tied to AVDD/2. Preferred mode for optimal distortion

performance.

The best noise performance may be obtained by operating the

AD9200 with a 2 V input range. The best distortion perfor-

mance may be obtained by operating the AD9200 with a 1 V

input range.

Single-Ended is attained by driving the AIN pin while the

REFTS and REFBS pins are held at dc points. The MODE pin is

tied to AVDD.

REFERENCE OPERATION

The AD9200 can be configured in a variety of reference topolo-

gies. The simplest configuration is to use the AD9200’s onboard

bandgap reference, which provides a pin-strappable option to

generate either a 1 V or 2 V output. If the user desires a refer-

ence voltage other than those two, an external resistor divider

can be connected between VREF, REFSENSE and analog

ground to generate a potential anywhere between 1 V and 2 V.

Another alternative is to use an external reference for designs

requiring enhanced accuracy and/or drift performance. A

third alternative is to bring in top and bottom references,

bypassing VREF altogether.

Single-Ended/Clamped (AC Coupled) the input may be

clamped to some dc level by ac coupling the input. This is done

by tying the CLAMPIN to some dc point and applying a pulse

to the CLAMP pin. MODE pin is tied to AVDD.

SPECIAL

AD876 Mode enables users of the AD876 to drop the AD9200

into their socket. This mode is attained by floating or grounding

the MODE pin.

Figures 16d, 16e and 16f illustrate the reference and input ar-

chitecture of the AD9200. In tailoring a desired arrangement,

the user can select an input configuration to match drive circuit.

Then, moving to the reference modes at the bottom of the

figure, select a reference circuit to accommodate the offset and

amplitude of a full-scale signal.

INPUT AND REFERENCE OVERVIEW

Figure 16, a simplified model of the AD9200, highlights the

relationship between the analog input, AIN, and the reference

voltages, REFTS, REFBS and VREF. Like the voltages applied

to the resistor ladder in a flash A/D converter, REFTS and

REFBS define the maximum and minimum input voltages to

the A/D.

Table I outlines pin configurations to match user requirements.

The input stage is normally configured for single-ended opera-

tion, but allows for differential operation by shorting REFTS

and REFBS together to be used as the second input.

REV. E

–9–

AD9200

V*

+FS

–FS

MIDSCALE

AD9200

MODE

REFTF

AIN

AVDD/2

AD9200

SHA

AIN

MODE

(AVDD)

SHA

+F/S RANGE OBTAINED

FROM VREF PIN OR

EXTERNAL REF

0.1␮F

10k⍀

0.1␮F

10k⍀

REFTF

10k⍀

REFTS

REFBS

10k⍀

REFTS

REFBS

A2

0.1␮F

A/D

CORE

4.2k⍀

TOTAL

10␮F

A2

0.1␮F

A/D

CORE

4.2k⍀

TOTAL

10␮F

INTERNAL

REF

0.1␮F

10k⍀

–F/S RANGE OBTAINED

FROM VREF PIN OR

EXTERNAL REF

0.1␮F

10k⍀

REFBF

MIDSCALE OFFSET

VOLTAGE IS DERIVED

FROM INTERNAL OR

EXTERNAL REF

* MAXIMUM MAGNITUDE OF V IS DETERMINED

BY INTERNAL REFERENCE

a. Top/Bottom Mode

b. Center Span Mode

MAXIMUM MAGNITUDE OF V

IS DETERMINED BY INTERNAL

REFERENCE AND TURNS RATIO

V

AD9200

MODE

REFTF

AIN

AVDD/2

SHA

AVDD/2

0.1␮F

10k⍀

REFTS

REFBS

A2

0.1␮F

A/D

CORE

4.2k⍀

TOTAL

10␮F

INTERNAL

REF

0.1␮F

10k⍀

REFBF

c. Differential Mode

VREF

(2V)

VREF

(1V)

A1

1V

0.01␮F

1.0␮F

1V

10k⍀

REFSENSE

AVSS

0.1␮F

1.0␮F

REFSENSE

AVSS

AD9200

d. 1 V Reference

e. 2 V Reference

VREF

(= 1 + R /R

)

A

B

A1

1V

0.1␮F

1.0␮F

R

A

A1

VREF

1V

REFSENSE

AVDD

R

B

AD9200

AVSS

AD9200

INTERNAL 10K REF RESISTORS ARE

SWITCHED OPEN BY THE PRESENSE

OF R AND R

.

A

B

f. Variable Reference

(Between 1 V and 2 V)

g. Internal Reference Disable

(Power Reduction)

Figure 16.

–10–

REV. E

AD9200

The actual reference voltages used by the internal circuitry of

the AD9200 appear on REFTF and REFBF. For proper opera-

tion, it is necessary to add a capacitor network to decouple these

pins. The REFTF and REFBF should be decoupled for all

internal and external configurations as shown in Figure 17.

Figure 19 shows the single-ended configuration for 2 V p-p

operation. REFSENSE is connected to GND, resulting in a 2 V

reference output.

2V

AIN

AD9200

MODE

SHA

AVDD

0V

0.1␮F

REFTF

10k⍀

REFTF

10␮F

0.1␮F

AD9200

10k⍀

REFTS

REFBS

REFBF

A2

0.1␮F

A/D

CORE

4.2k⍀

TOTAL

10␮F

0.1␮F

10k⍀

Figure 17. Reference Decoupling Network

REFBF

VREF

Note: REFTF = reference top, force

REFBF = reference bottom, force

REFTS = reference top, sense

A1

1V

1.0␮F

0.1␮F

REF

SENSE

REFBS = reference bottom, sense

INTERNAL REFERENCE OPERATION

Figure 19. Internal Reference, 2 V p-p Input Span

(Top/Bottom Mode)

Figures 18, 19 and 20 show example hookups of the AD9200

internal reference in its most common configurations. (Figures

18 and 19 illustrate top/bottom mode while Figure 20 illustrates

center span mode). Figure 29 shows how to connect the AD9200

for 1 V p-p differential operation. Shorting the VREF pin

directly to the REFSENSE pin places the internal reference

amplifier, A1, in unity-gain mode and the resultant reference

output is 1 V. In Figure 18 REFBS is grounded to give an input

range from 0 V to 1 V. These modes can be chosen when the

supply is either +3 V or +5 V. The VREF pin must be bypassed to

AVSS (analog ground) with a 1.0 µF tantalum capacitor in

parallel with a low inductance, low ESR, 0.1 µF ceramic capacitor.

Figure 20 shows the single-ended configuration that gives the

good high frequency dynamic performance (SINAD, SFDR).

To optimize dynamic performance, center the common-mode

voltage of the analog input at approximately 1.5 V. Connect the

shorted REFTS and REFBS inputs to a low impedance 1.5V

source. In this configuration, the MODE pin is driven to a volt-

age at midsupply (AVDD/2).

Maximum reference drive is 1 mA. An external buffer is re-

quired for heavier loads.

1V

AIN

AD9200

2V

MODE

AIN

AD9200

SHA

AVDD

MODE

0V

AVDD/2

SHA

1V

0.1␮F

10k⍀

REFTF

0.1␮F

REFTF

10k⍀

REFTS

REFBS

10k⍀

REFTS

REFBS

A2

0.1␮F

A/D

CORE

4.2k⍀

TOTAL

10␮F

A2

+1.5V

0.1␮F

A/D

CORE

4.2k⍀

TOTAL

10␮F

0.1␮F

10k⍀

0.1␮F

10k⍀

REFBF

VREF

A1

VREF

1V

A1

REF

SENSE

1V

1.0␮F

0.1␮F

REF

SENSE

0.1␮F

1.0␮F

Figure 18. Internal Reference 1 V p-p Input Span

(Top/Bottom Mode)

Figure 20. Internal Reference 1 V p-p Input Span,

(Center Span Mode)

REV. E

–11–

AD9200

EXTERNAL REFERENCE OPERATION

4V

2V

VIN

Using an external reference may provide more flexibility and

improve drift and accuracy. Figures 21 through 23 show ex-

amples of how to use an external reference with the AD9200.

To use an external reference, the user must disable the internal

reference amplifier by connecting the REFSENSE pin to VDD.

The user then has the option of driving the VREF pin, or driv-

ing the REFTS and REFBS pins.

REFTS

REFTF

4V

2V

AD9200

10

F

0.1

F

REFBF

0.1

F

REFBS

VREF

The AD9200 contains an internal reference buffer (A2), that

simplifies the drive requirements of an external reference. The

external reference must simply be able to drive a 10 kΩ load.

REFSENSE

MODE

AVDD

Figure 21 shows an example of the user driving the top and bottom

references. REFTS is connected to a low impedance 2 V source

and REFBS is connected to a low impedance 1 V source. REFTS

and REFBS may be driven to any voltage within the supply as

long as the difference between them is between 1 V and 2 V.

Figure 23a. External Reference—2 V p-p Input Span

REFTS

+5V

C4

0.1

F

6

5

2V

8

AIN

7

AD9200

REFTF

SHA

1V

C3

0.1

REFT

C6

0.1

F

C2

10

AD9200

F

0.1␮F

10k⍀

REFTF

REFBS

10k⍀

REFTS

REFBS

C5

0.1

2V

1V

2

3

F

A2

0.1␮F

6

A/D

CORE

4.2k⍀

TOTAL

10␮F

REFBF

REFB

C1

0.1

4

F

REF

SENSE

0.1␮F

10k⍀

AVDD

MODE

REFBF

Figure 23b. Kelvin Connected Reference Using the AD9200

Figure 21. External Reference Mode—1 V p-p Input Span

STANDBY OPERATION

The ADC may be placed into a powered down (sleep) mode by

driving the STBY (standby) pin to logic high potential and

holding the clock at logic low. In this mode the typical power

drain is approximately 4 mW. If there is no connection to the

STBY pin, an internal pull-down circuit will keep the ADC in a

“wake-up” mode of operation.

Figure 22 shows an example of an external reference generating

2.5 V at the shorted REFTS and REFBS inputs. In this in-

stance, a REF43 2.5 V reference drives REFTS and REFBS. A

resistive divider generates a 1 V VREF signal that is buffered by

A3. A3 must be able to drive a 10 kΩ, capacitive load. Choose

this op amp based on noise and accuracy requirements.

The ADC will “wake up” in 400 ns (typ) after the standby pulse

goes low.

AD9200

3.0V

2.5V

2.0V

AIN

CLAMP OPERATION

AVDD

The AD9200ARS and AD9200KST parts feature an optional

clamp circuit for dc restoration of video or ac coupled signals.

Figure 24 shows the internal clamp circuitry and the external

control signals needed for clamp operation. To enable the

clamp, apply a logic high to the CLAMP pin. This will close

the switch SW1. The clamp amplifier will then servo the volt-

age at the AIN pin to be equal to the clamp voltage applied at

the CLAMPIN pin. After the desired clamp level is attained,

SW1 is opened by taking CLAMP back to a logic low. Ignoring

the droop caused by the input bias current, the input capacitor

CIN will hold the dc voltage at AIN constant until the next

clamp interval. The input resistor RIN has a minimum recom-

mended value of 10 Ω, to maintain the closed-loop stability of

the clamp amplifier.

REFTS

REFBS

0.1␮F

REFTF

10␮F

1.5k⍀

A3

0.1␮F

10␮F

VREF

MODE

1.0␮F

0.1␮F

REFBF

0.1␮F

1k⍀

+5V

AVDD

REFSENSE

REF43

0.1␮F

AVDD/2

Figure 22. External Reference Mode—1 V p-p Input

Span 2.5 V_CM

Figure 23a shows an example of the external references driving

the REFTF and REFBF pins that is compatible with the

AD876. REFTS is shorted to REFTF and driven by an external

4 V low impedance source. REFBS is shorted to REFBF and

driven by a 2 V source. The MODE pin is connected to GND

in this configuration.

The allowable voltage range that can be applied to CLAMPIN

depends on the operational limits of the internal clamp ampli-

fier. When operating off of 3 volt supplies, the recommended

clamp range is between 0.5 volts and 2.0 volts.

REV. E

–12–

AD9200

The input capacitor should be sized to allow sufficient acquisi-

tion time of the clamp voltage at AIN within the CLAMP inter-

val, but also be sized to minimize droop between clamping

intervals. Specifically, the acquisition time when the switch is

closed will equal:

back porch to truncate the SYNC below the AD9200’s mini-

mum input voltage. With a C_IN= 1 µF, and R_IN= 20 Ω, the

acquisition time needed to set the input dc level to one volt

with 1 mV accuracy is about 140 µs, assuming a full 1 volt V_C.

With a 1 µF input coupling capacitor, the droop across one

horizontal can be calculated:

V_C

T_ACQ= R_INC_INln

V_E

I

_BIAS= 10 µA, and t = 63.5 µs, so dV = 0.635 mV, which is less

than one LSB.

where V_Cis the voltage change required across C_IN, and V_Eis

the error voltage. V_Cis calculated by taking the difference be-

tween the initial input dc level at the start of the clamp interval

and the clamp voltage supplied at CLAMPIN. V_Eis a system-

dependent parameter, and equals the maximum tolerable devia-

tion from V_C. For example, if a 2-volt input level needs to be

clamped to 1 volt at the AD9200’s input within 10 millivolts,

then V_Cequals 2 – 1 or 1 volt, and V_Eequals 10 mV. Note that

once the proper clamp level is attained at the input, only a very

small voltage change will be required to correct for droop.

After the input capacitor is initially charged, the clamp pulse-

width only needs to be wide enough to correct small voltage

errors such as the droop. The fine scale settling characteristics

of the clamp circuitry are shown in Table II.

Depending on the required accuracy, a CLAMP pulsewidth of

1 µs–3 µs should work in most applications. The OFFSET val-

ues ignore the contribution of offset from the clamp amplifier;

they simply compare the output code with a “final value” mea-

sured with a much longer CLAMP pulse duration.

The voltage droop is calculated with the following equation:

Table II.

I_BIAS

C_IN

dV =

t

( )

CLAMP

OFFSET

10 µs

5 µs

4 µs

3 µs

2 µs

1 µs

<1 LSB

5 LSBs

7 LSBs

11 LSBs

19 LSBs

42 LSBs

where t = time between clamping intervals.

The bias current of the AD9200 will depend on the sampling

rate, F_S. The switched capacitor input AIN appears resistive

over time, with an input resistance equal to 1/C_SF_S. Given a

sampling rate of 20 MSPS and an input capacitance of 1 pF, the

input resistance is 50 kΩ. This input resistance is equivalently

terminated at the midscale voltage of the input range. The worst

case bias current will thus result when the input signal is at the

extremes of the input range, that is, the furthest distance from

the midscale voltage level. For a 1-volt input range, the maxi-

mum bias current will be ±0.5 volts divided by 50 kΩ, which is

±10 µA.

AD9200

CLAMP IN

CLAMP

SW1

If droop is a critical parameter, then the minimum value of C_IN

should be calculated first based on the droop requirement.

Acquisition time—the width of the CLAMP pulse—can be

adjusted accordingly once the minimum capacitor value is cho-

sen. A tradeoff will often need to be made between droop and

acquisition time, or error voltage V_E.

CIN

RIN

AIN

TO

SHA

Figure 24a. Clamp Operation

Clamp Circuit Example

A single supply video amplifier outputs a level-shifted video

signal between 2 and 3 volts with the following parameters:

AIN

0.1

F

REFTF

REFTS

horizontal period = 63.56 µs,

horizontal sync interval = 10.9 µs,

horizontal sync pulse = 4.7 µs,

sync amplitude = 0.3 volts,

10

F

0.1 F

AD9200

REFBF

REFBS

video amplitude of 0.7 volts,

reference black level = 2.3 volts

AVDD

2

MODE

CLAMP

The video signal must be dc restored from a 2- to 3-volt range

down to a 1- to 2-volt range. Configuring the AD9200 for a

one volt input span with an input range from 1 to 2 volts (see

Figure 24), the CLAMPIN voltage can be set to 1 volt with an

external voltage or by direct connection to REFBS. The CLAMP

pulse may be applied during the SYNC pulse, or during the

SHORT TO REFBS

OR EXTERNAL DC

CLAMPIN

Figure 24b. Video Clamp Circuit

REV. E

–13–

AD9200

DRIVING THE ANALOG INPUT

In many cases, particularly in single-supply operation, ac cou-

pling offers a convenient way of biasing the analog input signal

at the proper signal range. Figure 25 shows a typical configura-

tion for ac-coupling the analog input signal to the AD9200.

Maintaining the specifications outlined in the data sheet

requires careful selection of the component values. The most

important is the f_{–3 dB}high-pass corner frequency. It is a function of

R2 and the parallel combination of C1 and C2. The f_{–3 dB}point

can be approximated by the equation:

Figure 25 shows the equivalent analog input of the AD9200, a

sample-and-hold amplifier (switched capacitor input SHA).

Bringing CLK to a logic low level closes Switches 1 and 2 and

opens Switch 3. The input source connected to AIN must

charge capacitor CH during this time. When CLK transitions

from logic “low” to logic “high,” Switches 1 and 2 open, placing

the SHA in hold mode. Switch 3 then closes, forcing the output

of the op amp to equal the voltage stored on CH. When CLK

transitions from logic “high” to logic “low,” Switch 3 opens

first. Switches 1 and 2 close, placing the SHA in track mode.

f

_{–3 dB}= 1/(2 × pi × [R2] C_EQ)

where C_EQis the parallel combination of C1 and C2. Note that

C1 is typically a large electrolytic or tantalum capacitor that

becomes inductive at high frequencies. Adding a small ceramic

or polystyrene capacitor (on the order of 0.01 µF) that does not

become inductive until negligibly higher frequencies, maintains

a low impedance over a wide frequency range.

The structure of the input SHA places certain requirements on

the input drive source. The combination of the pin capacitance,

CP, and the hold capacitance, CH, is typically less than 5 pF.

The input source must be able to charge or discharge this ca-

pacitance to 10-bit accuracy in one half of a clock cycle. When

the SHA goes into track mode, the input source must charge or

discharge capacitor CH from the voltage already stored on CH

to the new voltage. In the worst case, a full-scale voltage step on

the input, the input source must provide the charging current

through the R_ON(50 Ω) of Switch 1 and quickly (within 1/2 CLK

period) settle. This situation corresponds to driving a low input

impedance. On the other hand, when the source voltage equals

the value previously stored on CH, the hold capacitor requires

no input current and the equivalent input impedance is ex-

tremely high.

NOTE: AC coupled input signals may also be shifted to a desired

level with the AD9200’s internal clamp. See Clamp Operation.

C1

R1

V

AIN

IN

R2

I

B

AD9200

C2

V

BIAS

Adding series resistance between the output of the source and

the AIN pin reduces the drive requirements placed on the

source. Figure 26 shows this configuration. The bandwidth of

the particular application limits the size of this resistor. To

maintain the performance outlined in the data sheet specifica-

tions, the resistor should be limited to 20 Ω or less. For applica-

tions with signal bandwidths less than 10 MHz, the user may

proportionally increase the size of the series resistor. Alterna-

tively, adding a shunt capacitance between the AIN pin and

analog ground can lower the ac load impedance. The value of

this capacitance will depend on the source resistance and the

required signal bandwidth.

Figure 27. AC Coupled Input

There are additional considerations when choosing the resistor

values. The ac-coupling capacitors integrate the switching tran-

sients present at the input of the AD9200 and cause a net dc

bias current, I_B, to flow into the input. The magnitude of the

bias current increases as the signal magnitude deviates from

V midscale and the clock frequency increases; i.e., minimum

bias current flow when AIN = V midscale. This bias current

will result in an offset error of (R1 + R2) × I_B. If it is necessary

to compensate this error, consider making R2 negligibly small or

modifying VBIAS to account for the resultant offset.

The input span of the AD9200 is a function of the reference

voltages. For more information regarding the input range, see

the Internal and External Reference sections of the data sheet.

In systems that must use dc coupling, use an op amp to level-

shift a ground-referenced signal to comply with the input re-

quirements of the AD9200. Figure 28 shows an AD8041 config-

ured in noninverting mode.

CH

+V

CC

AIN

0.1

F

S1

CP

SHA

S3

NC

AD9200

S2

7

0V

DC

1V p-p

(REFTS

REFBS)

CH

2

3

1

5

20

CP

AD8041

6

AIN

AD9200

4

MIDSCALE

OFFSET

NC

VOLTAGE

Figure 25. AD9200 Equivalent Input Structure

Figure 28. Bipolar Level Shift

<

20⍀

AIN

AD9200

V

S

Figure 26. Simple AD9200 Drive Configuration

REV. E

–14–

AD9200

DIFFERENTIAL INPUT OPERATION

The pipelined architecture of the AD9200 operates on both

rising and falling edges of the input clock. To minimize duty

cycle variations the recommended logic family to drive the clock

input is high speed or advanced CMOS (HC/HCT, AC/ACT)

logic. CMOS logic provides both symmetrical voltage threshold

levels and sufficient rise and fall times to support 20 MSPS

operation. The AD9200 is designed to support a conversion rate

of 20 MSPS; running the part at slightly faster clock rates may

be possible, although at reduced performance levels. Conversely,

some slight performance improvements might be realized by

clocking the AD9200 at slower clock rates.

The AD9200 will accept differential input signals. This function

may be used by shorting REFTS and REFBS and driving them

as one leg of the differential signal (the top leg is driven into

AIN). In the configuration below, the AD9200 is accepting a

1 V p-p signal. See Figure 29.

AD9200

2V

AIN

0.1␮F

1V

AVDD/2

REFTF

REFTS

0.1␮F

10␮F

0.1␮F

REFBS

VREF

S1

S2

ANALOG

INPUT

S4

REFBF

t_C

S3

1.0␮F

0.1␮F

t_CH

t_CL

REFSENSE

MODE

INPUT

CLOCK

AVDD/2

25ns

DATA

OUTPUT

Figure 29. Differential Input

AD876 MODE OF OPERATION

The AD9200 may be dropped into the AD876 socket. This will

allow AD876 users to take advantage of the reduced power

consumption realized when running the AD9200 on a 3.0 V

analog supply.

DATA 1

Figure 31. Timing Diagram

The power dissipated by the output buffers is largely propor-

tional to the clock frequency; running at reduced clock rates

provides a reduction in power consumption.

Figure 30 shows the pin functions of the AD876 and AD9200.

The grounded REFSENSE pin and floating MODE pin effec-

tively put the AD9200 in the external reference mode. The

external reference input for the AD876 will now be placed on

the reference pins of the AD9200.

DIGITAL INPUTS AND OUTPUTS

Each of the AD9200 digital control inputs, THREE-STATE

and STBY are reference to analog ground. The clock is also

referenced to analog ground.

The format of the digital output is straight binary (see Figure

32). A low power mode feature is provided such that for STBY

= HIGH and the clock disabled, the static power of the AD9200

will drop below 5 mW.

The clamp controls will be grounded by the AD876 socket. The

AD9200 has a 3 clock cycle delay compared to a 3.5 cycle delay

of the AD876.

4V

OTR

AIN

AD9200

2V

REFTS

4V

2V

REFTF

0.1␮F

10␮F

REFBF

0.1␮F

REFBS

NC

MODE

REFSENSE

AVDD

CLAMP

CLAMPIN

–FS+1LSB

+FS

OTR

VREF

0.1␮F

–FS

+FS–1LSB

Figure 32. Output Data Format

Figure 30. AD876 Mode

THREE-

STATE

t_DHZ

t_DEN

CLOCK INPUT

DATA

The AD9200 clock input is buffered internally with an inverter

powered from the AVDD pin. This feature allows the AD9200

to accommodate either +5 V or +3.3 V CMOS logic input sig-

nal swings with the input threshold for the CLK pin nominally

at AVDD/2.

(D0–D9)

HIGH

IMPEDANCE

Figure 33. Three-State Timing Diagram

REV. E

–15–

AD9200

APPLICATIONS

Figure 34 shows a simplified schematic of the AD9200 config-

ured in an IF sampling application. To reduce the complexity of

the digital demodulator in many quadrature demodulation ap-

plications, the IF frequency and/or sample rate are selected such

that the bandlimited IF signal aliases back into the center of the

ADC’s baseband region (i.e., F_S/4). For example, if an IF sig-

nal centered at 45 MHz is sampled at 20 MSPS, an image of

this IF signal will be aliased back to 5.0 MHz which corre-

sponds to one quarter of the sample rate (i.e., F_S/4). This

demodulation technique typically reduces the complexity of the

post digital demodulator ASIC which follows the ADC.

DIRECT IF DOWN CONVERSION USING THE AD9200

Sampling IF signals above an ADC’s baseband region (i.e., dc

to F_S/2) is becoming increasingly popular in communication

applications. This process is often referred to as Direct IF Down

Conversion or Undersampling. There are several potential ben-

efits in using the ADC to alias (i.e., or mix) down a narrowband

or wideband IF signal. First and foremost is the elimination of a

complete mixer stage with its associated amplifiers and filters,

reducing cost and power dissipation. Second is the ability to

apply various DSP techniques to perform such functions as

filtering, channel selection, quadrature demodulation, data

reduction, detection, etc. A detailed discussion on using this

technique in digital receivers can be found in Analog Devices

Application Notes AN-301 and AN-302.

To maximize its distortion performance, the AD9200 is config-

ured in the differential mode with a 1 V span using a transformer.

The center tap of the transformer is biased at midsupply via a

resistor divider. Preceding the AD9200 is a bandpass filter as

well as a 32 dB gain stage. A large gain stage may be required

to compensate for the high insertion losses of a SAW filter used

for image rejection. The gain stage will also provide adequate

isolation for the SAW filter from the charge “kick back” currents

associated with AD9200’s input stage.

In Direct IF Down Conversion applications, one exploits the

inherent sampling process of an ADC in which an IF signal

lying outside the baseband region can be aliased back into the

baseband region in a similar manner that a mixer will down-

convert an IF signal. Similar to the mixer topology, an image

rejection filter is required to limit other potential interfering

signals from also aliasing back into the ADC’s baseband region.

A tradeoff exists between the complexity of this image rejection

filter and the sample rate as well as dynamic range of the ADC.

The gain stage can be realized using one or two cascaded

AD8009 op amps amplifiers. The AD8009 is a low cost, 1 GHz,

current-feedback op amp having a 3rd order intercept character-

ized up to 250 MHz. A passive bandpass filter following the

AD8009 attenuates its dominant 2nd order distortion products

which would otherwise be aliased back into the AD9200’s

baseband region. Also, it reduces any out-of-band noise which

would also be aliased back due to the AD9200’s noise band-

width of 220+ MHz. Note, the bandpass filters specifications

are application dependent and will affect both the total distor-

tion and noise performance of this circuit.

The AD9200 is well suited for various narrowband IF sampling

applications. The AD9200’s low distortion input SHA has a

full-power bandwidth extending to 300 MHz thus encompassing

many popular IF frequencies. A DNL of ±0.5 LSB (typ) com-

bined with low thermal input referred noise allows the AD9200 in

the 2 V span to provide 60 dB of SNR for a baseband input sine

wave. Also, its low aperture jitter of 2 ps rms ensures minimum

SNR degradation at higher IF frequencies. In fact, the AD9200

is capable of still maintaining 56 dB of SNR at an IF of 135 MHz

with a 1 V (i.e., 4 dBm) input span. Note, although the AD9200

will typically yield a 3 to 4 dB improvement in SNR when con-

figured for the 2 V span, the 1 V span provides the optimum

full-scale distortion performance. Furthermore, the 1 V span

reduces the performance requirements of the input driver cir-

cuitry and thus may be more practical for system implementa-

tion purposes.

The distortion and noise performance of an ADC at the given

IF frequency is of particular concern when evaluating an ADC

for a narrowband IF sampling application. Both single-tone and

dual-tone SFDR vs. amplitude are very useful in an assessing an

ADC’s noise performance and noise contribution due to aper-

ture jitter. In any application, one is advised to test several units

of the same device under the same conditions to evaluate the

given applications sensitivity to that particular device.

G

= 20dB

G

= 12dB

L-C

1

2

SAW

FILTER

OUTPUT

MINI CIRCUITS

T4 - 6T

BANDPASS

FILTER

AD9200

50⍀

1:4

AIN

50⍀

200⍀

REFTS

REFBS

280⍀

22.1⍀

93.1⍀

VREF

REFSENSE

1.0␮F 0.1␮F

0.1␮F

1k⍀

AVDD

Figure 34. Simplified AD9200 IF Sampling Circuit

REV. E

–16–

AD9200

Figures 35–38 combine the dual-tone SFDR as well as single

tone SFDR and SNR performance at IF frequencies of 45 MHz,

70 MHz, 85 MHz and 135 MHz. Note, the SFDR vs. ampli-

tude data is referenced to dBFS while the single tone SNR data

is referenced to dBc. The performance characteristics in these

figures are representative of the AD9200 without the AD8009.

The AD9200 was operated in the differential mode (via trans-

former) with a 1 V span at 20 MSPS. The analog supply

(AVDD) and the digital supply (DRVDD) were set to +5 V and

3.3 V, respectively.

Although not presented, data was also taken with the insertion

of an AD8009 gain stage of 32 dB in the signal path. No

degradation in two-tone SFDR vs. amplitude was noted at an

IF of 45 MHz, 70 MHz and 85 MHz. However, at 135 MHz,

the AD8009 became the limiting factor in the distortion perfor-

mance until the two input tones were decreased to –15 dBFS

from their full-scale level of –6.5 dBFS. Note: the SNR perfor-

mance in each case degraded by approximately 0.5 dB due to

the AD8009’s in-band noise contribution.

90

SINGLE TONE SFDR

80

DUAL TONE SFDR

70

SINGLE TONE SFDR

DUAL TONE SFDR

60

50

40

50

40

30

SNR

CLK = 20MSPS

SINGLE TONE – 45.52MHz

DUAL TONE– F = 44.49MHz

1

20

10

0

20

10

0

CLK = 20MSPS

SINGLE TONE – 85.52MHz

DUAL TONE– F = 84.49MHz

1

– F = 45.52MHz

2

– F = 85.52MHz

2

–60

–50

–40

–30

–20

–10

0

–60

–50

–40

–30

–20

–10

0

INPUT POWER LEVEL – dBFS

Figure 35. SNR/SFDR for IF @ 45 MHz

Figure 37. SNR/SFDR for IF @ 85 MHz

90

SINGLE TONE SFDR

80

70

60

DUAL TONE SFDR

SINGLE TONE SFDR

70

DUAL TONE SFDR

60

50

40

50

40

30

20

10

SNR

20

10

0

CLK = 20MSPS

SINGLE TONE – 135.52MHz

DUAL TONE – F = 134.44MHz

CLK = 21.538MSPS

SINGLE TONE – 70.55MHz

1

DUAL TONE– F = 69.50MHz

1

– F = 135.52MHz

2

– F = 70.55MHz

2

0

–60

–50

–40

–30

–20

–10

0

–60

–50

–40

–30

–20

–10

0

INPUT POWER LEVEL – dBFS

Figure 36. SNR/SFDR for IF @ 70 MHz

Figure 38. SNR/SFDR for IF @ 135 MHz

REV. E

–17–

AD9200

R11

15k⍀

R10

5k⍀

+3–5A

R17

316⍀

+3–5A

TP14

5

6

R15

0.626V TO 4.8V

R7

1k⍀

7

2

3

AD822

U2

Q1

2N3906

TP16

5.49k⍀

4

XXXX

ADJ.

R8

10k⍀

1

AD822

U2

C7

0.1␮F

EXTT

8

D1

C11

0.1␮F

CW

C8

10/10V

C13

10/10V

C12

0.1␮F

AD1580

R19

178⍀

R9

1.5k⍀

+3–5A

CM

R13

11k⍀

R20

178⍀

TP17

R12

C29

10k⍀

0.1␮F

2

3

XXXX

4

ADJ.

EXTB

6

1

AD822

U3

C14

0.1␮F

C15

10/10V

7

R14

10k⍀

AD822

U3

Q2

2N3904

8

5

C10

0.1␮F

CW

R16

1k⍀

C9

10/10V

R18

316k⍀

+3–5A

TP11

J7

JP5

CLAMP

R37

1k⍀

DRVDD

R53

49.9⍀

B

JP17

JP18

1

S3

2

THREE-STATE

STBY

R38

1k⍀

3

1

A

S4

B

GND

3

A

R39

1k⍀

7

5

10

13

11

9

J8

RN1

22⍀

DRVDD

AVDD

27

25

J8

C16

0.1␮F

C19

0.1␮F

6

11

RN1

22⍀

3

2

J8

C18

10/10V

C17

12

10/10V

4

J8

RN1

22⍀

6

8

J8

28

AVDD

2

16

15

21

8

4

13

B

OTR

TP19

WHITE

U4

A

DRVDD

7

9

3

4

5

6

7

10

1

2

B

U4

VCCA

T/R

A

RN1

22⍀

U1

10

12

D5

J8

D6

D7

D8

D9

20

19

18

17

14

24

23

22

13

AD9200

13

2

15

OTR

5

14

J8

RN1

22⍀

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

15

16

17

18

19

20

21

22

23

24

3

4

5

6

7

8

9

10

11

12

B

A

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

16

18

DUTCLK

THREE-STATE

STBY

REFSENSE

CLAMP

CLK

THREE-STATE

J8

B 1

S2

2

+3–5D

DRVDD

C40

0.1␮F

VCCB

NC1

OE

1

16

STBY

3

1

J8

20

22

C20

0.1␮F

J8

REFSENSE

11

12

RN1

22⍀

A

GD2

GD3

CLAMP

GD1

CLAMPIN

REFTS

REFTF

MODE

REFBF

REFBS

VREF

AIN

CLAMPIN

REFTS

REFTF

MODE

REFBF

U4

GND

24

26

J8

GND GND

GND

CLK

74LVXC4245WM

JP21

1

WHITE

3

+3–5D

6

11

2

19

5

NC

39

J8

25

26

27

CLK

B

33

U5

VCCA

A

J8

REFBS

20

21

18

17

4

3

6

7

C42

0.1␮F

RN2

22⍀

28

29

J8

VREF

AIN

CLK_OUT

5

12

D0

D1

D2

D3

J8

23

AVSS

1

DRVSS

14

+

RN2

22⍀

C33

10/10V

30

31

J8

16

15

14

24

23

22

13

8

9

10

1

2

11

12

D4

13

4

32

34

J8

21

J8

+3–5D

VCCB

NC1

OE

RN2

22⍀

J8

T/R

GD2

GD3

C21

DRVDD

0.1␮F

NC 35

3

14

C41

GD1

U5

19 J8

36

0.1␮F

J8

GND

RN2

22⍀

74LVXC4245WM

3

NC 37

GND

38

40

J8

2

15

2

1

17

15

J8

RN2

22⍀

JP20

C43

0.1␮F

GND

16

1

GND

RN2

22⍀

Figure 39a. Evaluation Board Schematic

REV. E

–18–

AD9200

JP14

REFSENSE

EXTB

AVDD

JP1

JP2

JP10

R5

10k

AVDD

MODE

TP3

TP4

C3

0.1

F

TP1

JP15

JP16

REFBF

REFTF

C4

0.1

C5

10/10V

+

R6

10k

F

JP3

JP4

JP9

C6

0.1

F

VREF

AVDDCLK

JP22

TP5

B

1

GND

AVDD

EXTT

S5

GND

R35

4.99k

2

CLAMPIN

EXTT

3

JP11

TP6

A

R34

2k

JP6

CW

REFTS

GND

JP12

R36

4.99k

C36

0.1

C37

0.1

C38

0.1

C35

10/10V

U6

B

F

1

2

TP7

5

6

REFBS

EXTB

GND

JP7

JP13

TP12

2

C30

B

A

T1–1T

4

1

0.1

F

AIN

S7

S6

2

3

2

J1

A

3

2

J5

A

R51

49.9

S8

ADC_CLK

B

1

R1

TP8

49.9

R4

49.9

6

P

S

CLK

1

JP8

REFBS

CM

TP13

T1

R52

49.9

TP9

R2

100

U6

JP26

3

4

C1

0.1

DUTCLK

F

TP10

DCIN

A

3

R3

100

2

S1

C2

47/10V

1

B

TP29

TP20

TP21

TP22

L4

U6 DECOUPLING

AVDDCLK

+3–5D

J9

C31

10/10V

C32

0.1

F

14

U6

L1

L2

L3

74AHC14

PWR

U6

8

9

C28

0.1

J2

J3

J4

DRVDD

AVDD

F

C22

0.1

C23

10/10V

GND

U6

11

13

10

7

12

C24

0.1

C25

33/16V

+3–5A

C26

0.1

C27

10/10V

F

TP23 TP24 TP25 TP26 TP27 TP28

GND J6

GND J10

Figure 39b. Evaluation Board Schematic

REV. E

–19–

AD9200

Figure 40a. Evaluation Board, Component Signal (Not to Scale)

Figure 40b. Evaluation Board, Solder Signal (Not to Scale)

–20–

REV. E

AD9200

Figure 40c. Evaluation Board Power Plane (Not to Scale)

Figure 40d. Evaluation Board Ground Plane (Not to Scale)

–21–

REV. E

AD9200

Figure 40e. Evaluation Board Component Silk (Not to Scale)

Figure 40f. Evaluation Board Solder Silk (Not to Scale)

–22–

REV. E

AD9200

GROUNDING AND LAYOUT RULES

DIGITAL OUTPUTS

As is the case for any high performance device, proper ground-

ing and layout techniques are essential in achieving optimal

performance. The analog and digital grounds on the AD9200

have been separated to optimize the management of return

currents in a system. Grounds should be connected near the

ADC. It is recommended that a printed circuit board (PCB) of

at least four layers, employing a ground plane and power planes,

be used with the AD9200. The use of ground and power planes

offers distinct advantages:

Each of the on-chip buffers for the AD9200 output bits

(D0–D9) is powered from the DRVDD supply pins, separate

from AVDD. The output drivers are sized to handle a variety

of logic families while minimizing the amount of glitch energy

generated. In all cases, a fan-out of one is recommended to keep

the capacitive load on the output data bits below the specified

20 pF level.

For DRVDD = 5 V, the AD9200 output signal swing is compat-

ible with both high speed CMOS and TTL logic families. For

TTL, the AD9200 on-chip, output drivers were designed to

support several of the high speed TTL families (F, AS, S). For

applications where the clock rate is below 20 MSPS, other TTL

families may be appropriate. For interfacing with lower voltage

CMOS logic, the AD9200 sustains 20 MSPS operation with

DRVDD = 3 V. In all cases, check your logic family data sheets

for compatibility with the AD9200 Digital Specification table.

1. The minimization of the loop area encompassed by a signal

and its return path.

2. The minimization of the impedance associated with ground

and power paths.

3. The inherent distributed capacitor formed by the power plane,

PCB insulation and ground plane.

These characteristics result in both a reduction of electro-

magnetic interference (EMI) and an overall improvement in

performance.

THREE-STATE OUTPUTS

The digital outputs of the AD9200 can be placed in a high

impedance state by setting the THREE-STATE pin to HIGH.

This feature is provided to facilitate in-circuit testing or evaluation.

It is important to design a layout that prevents noise from cou-

pling onto the input signal. Digital signals should not be run in

parallel with the input signal traces and should be routed away

from the input circuitry. Separate analog and digital grounds

should be joined together directly under the AD9200 in a solid

ground plane. The power and ground return currents must be

carefully managed. A general rule of thumb for mixed signal

layouts dictates that the return currents from digital circuitry

should not pass through critical analog circuitry.

REV. E

–23–

AD9200

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

48-Lead Plastic Thin Quad Flatpack (LQFP)

(ST-48)

0.063 (1.60) MAX

0.354 (9.00) BSC

30 0 7

0.057 (1.45)

0.276 (7.0) BSC

0.030 (0.75)

0.018 (0.45)

18 0 4

0.053 (1.35)

37

36

48

1

SEATING

PLANE

TOP VIEW

(PINS DOWN)

0.006 (0.15)

12

13

25

24

0.002 (0.05)

0° MIN

0° – 7°

0.007 (0.18)

0.004 (0.09)

0.011 (0.27)

0.006 (0.17)

0.019 (0.5)

BSC

28-Lead Shrink Small Outline Package (SSOP)

(RS-28)

0.407 (10.34)

0.397 (10.08)

28

15

14

1

0.07 (1.79)

0.078 (1.98)

PIN 1

0.066 (1.67)

0.068 (1.73)

0.03 (0.762)

8°

0°

0.0256

(0.65)

BSC

0.015 (0.38)

0.010 (0.25)

0.022 (0.558)

0.008 (0.203)

0.002 (0.050)

SEATING

PLANE

0.009 (0.229)

0.005 (0.127)

REV. E

–24–


型号：	AD9200JRSRL
厂家：	ADI
描述：	Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter 完整的10位， 20 MSPS ， 80毫瓦的CMOS A / D转换器转换器
文件：	总24页 (文件大小：341K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9200JRSRL [ADI]

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