AD9203ARUZRL7 [ADI]
10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter; 10位， 40 MSPS ， 3 V ， 74毫瓦的A / D转换器
| 型号： | AD9203ARUZRL7 |
| 厂家： | 
ADI |
| 描述： | 10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter |
| 文件： | 总28页 (文件大小：1212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 40 MSPS, 3 V, 74 mW
A/D Converter
AD9203
FEATURES
FUNCTIONAL BLOCK DIAGRAM
CLK
AVDD
DRVDD
CMOS 10-Bit, 40 MSPS sampling A/D converter
Power dissipation: 74 mW (3 V supply, 40 MSPS)
17 mW (3 V supply, 5 MSPS)
Operation between 2.7 V and 3.6 V supply
Differential nonlinearity: −0.25 LSB
Power-down (standby) mode, 0.65 mW
ENOB: 9.55 @ fIN = 20 MHz
CLAMP
AD9203
STBY
CLAMPIN
AINP
AINN
A/D
SHA
GAIN
SHA
GAIN
3-STATE
A/D
D/A
A/D
D/A
REFTF
REFBF
CORRECTION LOGIC
OUTPUT BUFFERS
Out-of-range indicator
BANDGAP
REFERENCE
OTR
VREF
Adjustable on-chip voltage reference
IF undersampling up to fIN = 130 MHz
Input range: 1 V to 2 V p-p differential or single-ended
Adjustable power consumption
Internal clamp circuit
D9 (MSB)
10
+
–
REFSENSE
D0 (LSB)
0.5V
AVSS
PWRCON
DFS
DRVSS
Figure 1.
APPLICATIONS
CCD imaging
Video
Portable instrumentation
IF and baseband communications
Cable modems
Medical ultrasound
out-of-range signal (OTR) indicates an overflow condition that
can be used with the most significant bit to determine over- or
underrange.
GENERAL DESCRIPTION
The AD9203 is a monolithic low power, single supply, 10-bit,
40 MSPS analog-to-digital converter, with an on-chip voltage
reference. The AD9203 uses a multistage differential pipeline
architecture and guarantees no missing codes over the full
operating temperature range. Its input range may be adjusted
between 1 V and 2 V p-p.
The AD9203 can operate with a supply range from 2.7 V to 3.6
V, an attractive option for low power operation in high-speed
portable applications.
The AD9203 is specified over industrial (−40°C to +85°C)
temperature ranges and is available in a 28-lead TSSOP package.
The AD9203 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy
and temperature drift requirements of an application.
PRODUCT HIGHLIGHTS
Low Power—The AD9203 consumes 74 mW on a 3 V supply
operating at 40 MSPS. In standby mode, power is reduced to
0.65 mW.
High Performance—Maintains better than 9.55 ENOB at 40
MSPS input signal from dc to Nyquist.
Ver y Small Package—The AD9203 is available in a 28-lead
TSSOP.
Programmable Power—The AD9203 power can be further
reduced by using an external resistor at lower sample rates.
Built-In Clamp Function—Allows dc restoration of video
signals.
An external resistor can be used to reduce power consumption
when operating at lower sampling rates. This yields power
savings for users who do not require the maximum sample rate.
This feature is especially useful at sample rates far below 40
MSPS. Excellent performance is still achieved at reduced power.
For example, 9.7 ENOB performance may be realized with only
17 mW of power, using a 5 MHz clock.
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary or
twos complementary output format by using the DFS pin. An
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD9203
TABLE OF CONTENTS
Specifications..................................................................................... 3
Driving the Analog Input.......................................................... 13
Op Amp Selection Guide .......................................................... 14
Differential Mode of Operation ............................................... 15
Power Control............................................................................. 16
Interfacing to 5 V Systems ........................................................ 16
Clock Input and Considerations .............................................. 16
Digital Inputs and Outputs ....................................................... 16
Applications..................................................................................... 18
Direct IF Down Conversion ..................................................... 18
Ultrasound Applications ........................................................... 19
Evaluation Board ............................................................................ 20
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Terminology ...................................................................................... 7
Typical Performance Characteristics ............................................. 8
Operations ....................................................................................... 11
Theory of Operation .................................................................. 11
Operational Modes..................................................................... 11
Input and Reference Overview................................................. 12
Internal Reference Connection ................................................ 12
External Reference Operation .................................................. 13
Clamp Operation........................................................................ 13
REVISION HISTORY
8/04—Data sheet changed from Rev. A to Rev. B
Changes to Table 5.......................................................................... 16
4/01—Data sheet changed from Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to TPC 2............................................................................. 8
Added Figures 41 to 46 .................................................................. 23
7/99—Revision 0: Initial Version
Rev. B | Page 2 of 28
AD9203
SPECIFICATIONS
AVDD = 3 V, DRVDD = 3 V, FS = 40 MSPS, input span from 0.5 V to 2.5 V, internal 1 V reference, PWRCON = AVDD, 50% clock duty
cycle, TMIN to TMAX unless otherwise noted.
Table 1.
Parameter
Symbol Min
Typ
Max
Unit
Bits
Conditions
RESOLUTION
10
MAX CONVERSION RATE
FS
40
MSPS
Clock
Cycles
PIPELINE DELAY
5.5
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
Offset Error
DNL
INL
EZS
0.25 0.ꢀ LSB
0.ꢁ5 1.4 LSB
0.ꢁ 2.8
0.ꢀ 4.0
% FSR
Gain Error
EFS
% FSR
2
ANALOG INPUT
Input Voltage Range
Input Capacitance
AIN
CIN
1
V p-p
pF
1.4
Aperture Delay
TAP
TAJ
BW
2.0
1.2
390
0.3
ns
Aperture Uncertainty (Jitter)
Input Bandwidth (–3 dB)
Input Referred Noise
INTERNAL REFERENCE
Output Voltage (0.5 V Mode)
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Load Regulation
ps rms
MHz
mV
Switched, Single-Ended
VREF
VREF
0.5
1
5
V
V
mV
mV
REFSENSE = VREF
REFSENSE = GND
30
1.2
0.ꢁ5
1.0 mA Load
POWER SUPPLY
Operating Voltage
AVDD
2.ꢀ
3.0
3.ꢁ
V
DRVDD 2.ꢀ
IAVDD
IDRVDD
3.0
20.1
4.4
9.5
ꢀ4
3.ꢁ
22.0
ꢁ.0
14.0
84.0
V
Analog Supply Current
Digital Supply Current
mA
mA
mA
mW
fIN= 4.8 MHz, Output Bus Load = 10pF
fIN= 20 MHz, Output Bus Load = 20 pF
fIN= 4.8 MHz, Output Bus Load = 10pF
fIN= 20 MHz, Output Bus Load = 20 pF
Power Consumption
88.8
0.ꢁ5
0.04
108.0 mW
1.2 mW
0.25 % FS
Power-Down
PD
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE (AIN = 0.5 dBFS)
PSRR
1
Signal-to-Noise and Distortion
SINAD
f = 4.8 MHz
f = 20 MHz
59.ꢀ
59.3
dB
dB
5ꢀ.2
Effective Bits
f = 4.8 MHz
f = 20 MHz
Signal-to-Noise Ratio
ENOB
SNR
1
9.ꢁ
9.55
Bits
Bits
9.2
1
f = 4.8 MHz
ꢁ0.0
59.5
dB
dB
f = 20 MHz
5ꢀ.5
Total Harmonic Distortion
f = 4.8MHz
f = 20 MHz
THD
−ꢀꢁ.0
−ꢀ4.0
dB
−ꢁ5.0 dB
Spurious-Free Dynamic Range
f = 4.8 MHz1
f = 20 MHz
SFDR
80
ꢀ8
dB
dB
ꢁꢀ.8
Rev. B | Page 3 of 28
AD9203
Parameter
Symbol Min
Typ
ꢁ8
0.2
0.3
Max
Unit
dB
Degree
%
Conditions
Two-Tone Intermodulation Distortion
Differential Phase
Differential Gain
IMD
DP
DG
f = 44.49 MHz and 45.52 MHz
NTSC 40 IRE Ramp
DIGITAL INPUTS
High Input Voltage
Low Input Voltage
VIH
VIL
2.0
V
V
0.4
Clock Pulse Width High
Clock Pulse Width Low
Clock Period2
11.25
11.25
ns
ns
ns
25
DIGITAL OUTPUTS
High-Z Leakage
Data Valid Delay
Data Enable Delay
Data High-Z Delay
IOZ
5.0
µA
ns
ns
ns
Output = 0 to DRVDD
CL= 20 pF
CL= 20 pF
tOD
tDEN
tDHZ
5
ꢁ
ꢁ
CL= 20 pF
LOGIC OUTPUT (with DRVDD = 3 V)
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL= 1.ꢁ mA)
Low Level Output Voltage (IOL= 50 µA)
VOH
VOH
VOL
VOL
2.95
2.80
V
V
V
V
0.3
0.05
1 Differential Input (2 V p-p).
2 The AD9203 will convert at clock rates as low as 20 kHz.
N+1
N
N+2
N–1
N+3
ANALOG
INPUT
N+6
N+4
N+5
CLOCK
DATA
OUT
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
T
= 3ns MIN
7ns MAX
OD
(C
= 20pF)
LOAD
Figure 2. Timing Diagram
Rev. B | Page 4 of 28
AD9203
ABSOLUTE MAXIMUM RATINGS
Table 2.
With
Respect to Min
Parameter
AVDD
DRVDD
AVSS
AVDD
REFCOM
CLK
Max
Unit
V
V
V
V
V
V
V
V
AVSS
–0.3
–0.3
–0.3
–3.9
–0.3
–0.3
–0.3
+3.9
+3.9
+0.3
+3.9
DRVSS
DRVSS
DRVDD
AVSS
AVSS
DRVSS
AINN
+0.3
AVDD + 0.3
DRVDD + 0.3
AVDD + 0.3
Digital Outputs
AINP
AVSS
–0.3
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
VREF
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
150
V
V
V
V
V
V
V
V
V
°C
REFSENSE
REFTF, REFBF
STBY
CLAMP
CLAMPIN
PWRCON
DFS
3-STATE
Junction
Temperature
Storage
Temperature
Lead
Temperature
(10 s)
–ꢁ5
+150
300
°C
°C
THERMAL CHARACTERISTICS
28-Lead TSSOP
JA = 97.9°C/W
JC = 14.0°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 5 of 28
AD9203
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DRVSS
DRVDD
(LSB) D0
D1
1
28 AVDD
2
AVSS
AINN
AINP
27
26
25
3
4
5
D2
24 REFBF
VREF
6
D3
AD9203 23
TOP VIEW
(Not to Scale)
D4
7
REFTF
22
21
20
8
D5
PWRCON
CLAMPIN
9
D6
10
D7
19 CLAMP
D8 11
18 REFSENSE
12
13
14
STBY
(MSB) D9
OTR
17
16
15
3-STATE
CLK
DFS
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin
Name
DRVSS
DRVDD
D0
Description
1
2
3
Digital Ground.
Digital Supply.
Bit 0, Least Significant Bit.
4
D1
Bit 1.
5
D2
Bit 2.
ꢁ
D3
Bit 3.
ꢀ
D4
Bit 4.
8
D5
Bit 5.
9
Dꢁ
Bit ꢁ.
10
11
12
13
14
15
1ꢁ
1ꢀ
18
19
20
21
22
23
24
25
2ꢁ
2ꢀ
28
Dꢀ
D8
D9
OTR
DFS
CLK
3-STATE
STBY
REFSENSE
CLAMP
CLAMPIN
PWRCON
REFTF
VREF
REFBF
AINP
AINN
AVSS
AVDD
Bit ꢀ.
Bit 8.
Bit 9, Most Significant Bit.
Out-of-Range Indicator.
Data Format Select HI: Twos Complement; LO: Straight Binary.
Clock Input.
HI: High Impedance State Output; LO: Active Digital Output Drives.
HI: Power-Down Mode; LO: Normal Operation.
Reference Select.
HI: Enable Clamp; LO: Open Clamp.
Clamp Signal Input.
Power Control Input.
Top Reference Decoupling.
Reference In/Out.
Bottom Reference Decoupling.
Noninverting Analog Input.
Inverting Analog Input.
Analog Ground.
Analog Supply.
Rev. B | Page ꢁ of 28
AD9203
TERMINOLOGY
Integral Nonlinearity Error (INL)
Signal-To-Noise Ratio (SNR)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Differential Nonlinearity Error (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-bit resolution indicates that all 1024
codes respectively, must be present over all operating ranges.
Offset Error
First transition should occur for an analog value 1/2 LSB above
negative full scale. Offset error is defined as the deviation of the
actual transition from that point.
Gain Error
Signal-To-Noise and Distortion (S/N+D, SINAD) Ratio
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
The first code transition should occur at an analog value 1/2
LSB above negative full scale. The last transition should occur
for an analog value 1 1/2 LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the
number of bits. Using the following formula,
Power Supply Rejection
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Aperture Jitter
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
Pipeline Delay (Latency)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided on every rising edge.
Rev. B | Page ꢀ of 28
AD9203
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3 V, DRVDD = 3 V, FS = 40 MSPS, 1 V Internal Reference, PWRCON = AVDD, 50% Duty Cycle, unless otherwise noted.
61
59
57
55
53
51
49
47
85
80
75
70
65
60
55
50
45
40
35
2V SINGLE-ENDED INPUT
2V DIFFERENTIAL INPUT
1V DIFFERENTIAL
INPUT
1V SINGLE-
ENDED INPUT
1V DIFFERENTIAL INPUT
2V DIFFERENTIAL
INPUT
2V SINGLE-
ENDED INPUT
1V SINGLE-ENDED INPUT
0
20
40
60
80
100
120
0
20
40
60
80
100
120
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 4. SNR vs. Input Frequency and Configuration
Figure 7. SFDR vs. Input Frequency and Configuration
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
60
55
50
45
40
35
9.6
8.8
8.0
7.1
6.3
5.5
2V DIFFERENTIAL
INPUT
1V DIFFERENTIAL
INPUT
2V DIFFERENTIAL
INPUT
1V DIFFERENTIAL INPUT
1V SINGLE-
ENDED INPUT
1V SINGLE-
ENDED INPUT
2V SINGLE-
ENDED INPUT
2V SINGLE-
ENDED INPUT
0
20
40
60
80
100
120
0
20
40
60
80
100
120
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 5. SINAD vs. Input Frequency and Configuration
Figure 8. THD vs. Input Frequency and Configuration
–75
–70
–65
–60
–55
–50
–45
–40
–75
–65
–55
–45
–35
–0.5dB
–6.0dB
–0.5dB
–6.0dB
–20dB
–20dB
0
20
40
60
80
100
120
0
20
40
60
80
100
120
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 6. THD vs. Input Frequency and Amplitude
(Differential Input VREF = 0.5 V)
Figure 9. THD vs. Input Frequency and Amplitude
(Differential Input VREF = 1 V)
Rev. B | Page 8 of 28
AD9203
1.2E+07
1.0E+07
8.0E+06
6.0E+06
4.0E+06
2.0E+06
0.0E+00
1.0
0.8
10000000
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
4560
N–1
10310
N+1
N
0
100 200 300 400 500 600 700 800 900
1024
CODE
Figure 13. Typical DNL Performance
Figure 10. Grounded Input Histogram
80
85
70
65
60
55
50
45
10
0
SNR = 59.9dB
THD = –75dB
SFDR = 82dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–THD
SNR
40
0
10
20
30
40
50
60
0E+0
2.5E+6 5.0E+6 7.5E+6 10.0E+6 12.5E+6 15.0E+6 17.5E+6 20.0E+6
SAMPLE RATE (MSPS)
Figure 14. Single Tone Frequency Domain Performance (Input Frequency =
10 MHz, Sample Rate = 40 MSPS 2 V Differential Input, 8192 Point FFT)
Figure 11. SNR and THD vs. Sample Rate (fIN = 20 MHz)
80
1.0
0.8
75
0.6
–THD
0.4
70
65
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
60
SNR
55
50
2.5
3.0
3.5
4.0
0
100 200 300 400 500 600 700 800 900
1024
SUPPLY VOLTAGE (V)
Figure 12. Typical INL Performance
Figure 15. SNR and THD vs. Power Supply
(fIN = 20 MHz, Sample Rate = 40 MSPS)
Rev. B | Page 9 of 28
AD9203
0
–1
–2
–3
–4
–5
–6
–7
–8
0.2
0.1
0
0.5V
–0.1
–0.2
–0.3
–0.4
1V
–9
10
100
1000
–40
–20
0
20
40
60
80
100
INPUT FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 16. Full Power Bandwidth
Figure 18. Reference Voltage vs. Temperature
3500
3000
2500
2000
1500
1000
500
1V REFERENCE
0.5V REFERENCE
0
0
200
400
600
800
1000
OFF-TIME (ms)
Figure 17. Wake-Up Time vs. Off Time (VREF Decoupling = 10 µF)
Rev. B | Page 10 of 28
AD9203
OPERATIONS
THEORY OF OPERATION
OPERATIONAL MODES
The AD9203 implements a pipelined multistage architecture to
achieve high sample rates while consuming low power. It
distributes the conversion over several smaller A/D subblocks,
refining the conversion with progressively higher accuracy as it
passes the results from stage to stage. As a consequence of the
distributed conversion, the AD9203 requires a small fraction of
the 1023 comparators used in a traditional 10-bit flash-type
A/D. A sample-and-hold function within each of the stages
permits the first stage to operate on a new input sample while
the remaining stages operate on preceding samples.
The AD9203 may be connected in several input configurations,
as shown in Table 4.
The AD9203 may be driven differentially from a source that
keeps the signal peaks within the power supply rails.
Alternatively, the input may be driven into AINP or AINN from
a single-ended source. The input span will be 2 the
programmed reference voltage. One input will accept the signal,
while the opposite input will be set to midscale by connecting it
to the internal or an external reference. For example, a 2 V p-p
signal may be applied to AINP while a 1 V reference is applied
to AINN. The AD9203 will then accept a signal varying
between 2 V and 0 V. See Figure 19, Figure 20, and Figure 21 for
more details.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash A/D connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each one of the stages to facilitate digital
correction of flash errors. The last stage simply consists of a
flash A/D.
The single-ended (ac-coupled) input of the AD9203 may also be
clamped to ground by the internal clamp switch. This is
accomplished by connecting the CLAMP pin to AINN or AINP.
Digital output formats may be configured in binary and twos
complement. This is determined by the potential on the DFS
pin. If the pin is set to Logic 0, the data will be in straight binary
format. If the pin is asserted to Logic 1, the data will be in twos
complement format.
The input of the AD9203 incorporates a novel structure that
merges the input sample-and-hold amplifier (SHA) and the first
pipeline residue amplifier into a single, compact switched
capacitor circuit. This structure achieves considerable noise and
power savings over a conventional implementation that uses
separate amplifiers by eliminating one amplifier in the pipeline.
By matching the sampling network of the input SHA with the
first stage flash A/D, the AD9203 can sample inputs well
beyond the Nyquist frequency with no degradation in
Power consumption may be reduced by placing a resistor
between PWRCON and AVSS. This may be done to conserve
power when not encoding high-speed analog input frequencies
or sampling at the maximum conversion rate. See the
performance. Sampling occurs on the falling edge of the clock.
Power Control section for more information.
Table 4. Modes
Name
Figure Number
Advantages
1 V Differential
Figure 28 with VREF Connected to
REFSENSE
Differential Modes Yield the Best Dynamic Performance
2 V Differential
Figure 28 with REFSENSE Connected to
AGND
Differential Modes Yield the Best Dynamic Performance
1 V Single-Ended
2 V Single-Ended
Figure 20
Figure 19
Video and Applications Requiring Clamping Require Single-Ended Inputs
Video and Applications Requiring Clamping Require Single-Ended Inputs
Rev. B | Page 11 of 28
AD9203
INPUT AND REFERENCE OVERVIEW
Like the voltage applied to the top of the resistor ladder in a
flash A/D converter, the value VREF defines the maximum
input voltage to the A/D core. The minimum input voltage to
the A/D core is automatically defined to be −VREF.
Figure 19 illustrates the input configured with a 1 V reference.
This will set the single-ended input of the AD9203 in the 2 V
span (2 × VREF). This example shows the AINN input is tied to
the 1 V VREF. This will configure the AD9203 to accept a 2 V
input centered around 1 V.
2V
AINP
0V
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily
configure the inputs for either single-ended operation or
differential operation. The A/D’s input structure allows the dc
offset of the input signal to be varied independently of the input
span of the converter. Specifically, the input to the A/D core is
the difference of the voltages applied at the AINP and AINN
input pins. Therefore, the equation,
AINN
REFTF
2V
0.1µF
ADC
10µF
CORE
0.1µF
REFBF
1V
0.1µF
VREF
+
0.5V
10µF
0.1µF
–
V
CORE = AINP − AINN
(1)
LOGIC
defines the output of the differential input stage and provides
the input to the A/D core.
REFSENSE
AD9203
Figure 19. Internal Reference Set for a 2 V Span
The voltage, VCORE, must satisfy the condition,
−VREF ≤ VCORE ≤ VREF
Figure 20 illustrates the input configured with a 0.5 V reference.
This will set the single-ended input of the ADC in a 1 V span
(2 × VREF). The AINN input is tied to the 0.5 VREF. This will
configure the AD9203 to accept a 1 V input centered around
0.5 V.
(2)
where VREF is the voltage at the VREF pin.
The actual span (AINP − AINN) of the ADC is VREF.
1V
While an infinite combination of AINP and AINN inputs exist
that satisfy Equation 2, an additional limitation is placed on the
inputs by the power supply voltages of the AD9203. The power
supplies bound the valid operating range for AINP and AINN.
The condition,
AINP
0V
AINN
REFTF
1.75V
0.1µF
ADC
CORE
10µF
0.1µF
REFBF
1.25V
AVSS − 0.3 V < AINP < AVDD + 0.3 V
AVSS − 0.3 V < AINN < AVDD + 0.3 V
(3)
0.1µF
VREF
+
where AVSS is nominally 0 V and AVDD is nominally 3 V,
defines this requirement. The range of valid inputs for AINP
and AINN is any combination that satisfies both Equations 2
and 3.
0.5V
10µF
0.1µF
–
LOGIC
AD9203
REFSENSE
INTERNAL REFERENCE CONNECTION
Figure 20. Internal Reference Set for a 1 V Span
A comparator within the AD9203 will detect the potential of
the VREF pin. If REFSENSE is grounded, the reference
amplifier switch will connect to the resistor divider (see Figure
19). That will make VREF equal to 1 V. If resistors are placed
between VREF, REFSENSE and ground, the switch will be
connected to the REFSENSE position and the reference
amplitude will depend on the external programming resistors
(Figure 21). If REFSENSE is tied to VREF, the switch will also
connect to REFSENSE and the reference voltage will be 0.5 V
(Figure 20). REFTF and REFBF will drive the ADC conversion
core and establish its maximum and minimum span. The range
of the ADC will equal twice the voltage at the reference pin for
either an internal or external reference.
Figure 21 shows the reference programmed by external resistors
for 0.75 V. This will set the ADC to receive a 1.5 V span
centered about 0.75 V. The reference is programmed according
to the algorithm:
VREF = 0.5 V × [1 + (RA/RB)]
Rev. B | Page 12 of 28
AD9203
1.5V
0V
CLAMP OPERATION
AINP
AINN
The AD9203 contains an internal clamp. It may be used when
operating the input in a single-ended mode. This clamp is very
useful for clamping NTSC and PAL video signals to ground.
The clamp cannot be used in the differential input mode.
REFTF
1.875V
0.1µF
ADC
10µF
CORE
0.1µF
REFBF
1.125V
REFSENSE
AD9203
0.1µF
VREF
+
VREF
0.1µF
0.5V
AINN
10µF
–
ADC
CORE
C
IN
R
A
AINP
1V p-p
LOGIC
AD9203
0V DC
REFSENSE
50Ω TYP
R
B
CLAMPIN
CLAMP
Figure 21. Programmable Reference Configuration
SW1
EXTERNAL REFERENCE OPERATION
Figure 22 illustrates the use of an external reference. An
Figure 23. Clamp Configuration (VREF = 0.5 V)
external reference may be necessary for several reasons. Tighter
reference tolerance will enhance the accuracy of the ADC and
will allow lower temperature drift performance. When several
ADCs track one another, a single reference (internal or
external) will be necessary. The AD9203 will draw less power
when an external reference is used.
Figure 23 shows the internal clamp circuitry and the external
control signals needed for clamp operation. To enable the
clamp, apply a logic high 1 to the CLAMP pin. This will close
SW1, the internal switch. SW1 is opened by asserting the
CLAMP pin low 0. The capacitor holds the voltage across CIN
constant until the next interval. The charge on the capacitor will
leak off as a function of input bias current (see Figure 24).
When the REFSENSE pin is tied to AVDD, the internal
reference will be disabled, allowing the use of an external
reference.
250
200
150
100
50
The AD9203 contains an internal reference buffer. It will load
the external reference with an equivalent 10 kΩ load. The
internal buffer will generate positive and negative full-scale
references for the ADC core.
In Figure 22, an external reference is used to set the midscale set
point for single-ended use. At the same time, it sets the input
voltage span through a resistor divider. If the ADC is being
driven differentially through a transformer, the external
reference can set the center tap (common-mode voltage).
0
–50
3.0V
2.0V
1.0V
0
0.5
1.0
1.5
2.0
2.5
3.0
AINP
INPUT VOLTAGE (V)
5V
AD9203
Figure 24. Input Bias Current vs. Input Voltage (FS = 40 MSPS)
EXTERNAL
REF (2V)
AINN
10µF
0.1µF
0.1µF
1.5kΩ
1.5kΩ
DRIVING THE ANALOG INPUT
Figure 25 illustrates the equivalent analog input of the AD9203,
(a switched capacitor input). Bringing CLK to a logic high,
opens S3 and closes S1 and S2. The input source connected to
AIN and must charge Capacitor CH during this time. Bringing
CLK to a logic low opens S2, and then S1 opens followed by
closing S3. This puts the input in the hold mode.
A3
VREF
1V
0.1µF
REFSENSE
AVDD
Figure 22. External Reference Configuration
Rev. B | Page 13 of 28
AD9203
C1
R1
AD9203
V
AIN
IN
S1
R2
C
C
H
H
AD9203
C2
+
V
BIAS
C
C
P
AVDD/2
–
S2
S3
P
Figure 27. AC-Coupled Input
The f–3 dB point can be approximated by the equation:
−3dB = 1/(2π × [R2] CEQ)
Figure 25. Input Architecture
f
The structure of the input SHA places certain requirements on
the input drive source. The combination of the pin capacitance,
CP, and the hold capacitance, CH, is typically less than 5 pF. The
input source must be able to charge or discharge this
capacitance to 10-bit accuracy in one half of a clock cycle.
When the SHA goes into track mode, the input source must
charge or discharge capacitor CH from the voltage already stored
on CH to the new voltage. In the worst case, a full-scale voltage
step on the input source must provide the charging current
through the RON (100 Ω) of Switch 1 and quickly (within 1/2
CLK period) settle. This situation corresponds to driving a low
input impedance. Adding series resistance between the output
of the signal source and the AIN pin reduces the drive
requirements placed on the signal source. Figure 26 shows this
configuration. The bandwidth of the particular application
limits the size of this resistor. To maintain the performance
outlined in the data sheet specifications, the resistor should be
limited to 50 Ω or less. The series input resistor can be used to
isolate the driver from the AD9203’s switched capacitor input.
The external capacitor may be selected to limit the bandwidth
into the AD9203. Two input RC networks should be used to
balance differential input drive schemes (Figure 26).
where CEQ is the parallel combination of C1 and C2. Note that
C1 is typically a large electrolytic or tantalum capacitor that
becomes inductive at high frequencies. Add a small ceramic or
polystyrene capacitor (on the order of 0.01 µF) that is negligibly
inductive at higher frequencies while maintaining a low
impedance over a wide frequency range.
There are additional considerations when choosing the resistor
values for an ac-coupled input. The ac-coupling capacitors
integrate the switching transients present at the input of the
AD9203 and cause a net dc bias current, IB, to flow into the
input. The magnitude of the bias current increases as the signal
changes and as the clock frequency increases. This bias current
will result in an offset error of (R1 + R2) IB. If it is necessary to
compensate for this error, consider modifying VBIAS to
account for the resultant offset. In systems that must use dc
coupling, use an op amp to level shift ground-referenced signals
to comply with the input requirements of the AD9203.
OP AMP SELECTION GUIDE
Op amp selection for the AD9203 is highly application
dependent. In general, the performance requirements of any
given application can be characterized by either time domain or
frequency domain constraints. In either case, one should
carefully select an op amp that preserves the performance of the
A/D. This task becomes challenging when one considers the
AD9203’s high performance capabilities coupled with other
system level requirements such as power consumption and cost.
The input span of the AD9203 is a function of the reference
voltage. For more information regarding the input range, see
the Internal Reference Connection and External Reference
Operation sections of the data sheet.
<50Ω
AIN
V
S
AD9203
The ability to select the optimal op amp may be further
complicated by either limited power supply availability and/or
limited acceptable supplies for a desired op amp. Newer, high
performance op amps typically have input and output range
limitations in accordance with their lower supply voltages. As a
result, some op amps will be more appropriate in systems where
ac coupling is allowed. When dc coupling is required, the
headroom constraints of op amps (such as rail-to-rail op amps)
or ones where larger supplies can be used, should be
considered.
Figure 26. Simple AD9203 Drive Configuration
In many cases, particularly in single-supply operation, ac
coupling offers a convenient way of biasing the analog input
signal to the proper signal range. Figure 27 shows a typical
configuration for ac-coupling the analog input signal to the
AD9203. Maintaining the specifications outlined in the data
sheet requires careful selection of the component values. The
most important is the f–3 dB high-pass corner frequency. It is a
function of R2 and the parallel combination of C1 and C2.
The following section describes some op amps currently
available from Analog Devices. Please contact the factory or
local sales office for updates on Analog Devices latest amplifier
product offerings.
Rev. B | Page 14 of 28
AD9203
2V
1V
AD8051: f–3 dB = 110 MHz. Low cost. Best used for driving
single-ended ac-coupled configuration. Operates on a 3 V
power rail.
AINP
AINN
AD9203
AD8052: Dual Version of above amp.
VREF
10µF
0.1µF
AD8138 is a higher performance version of AD8131. Its gain is
REFSENSE
programmable and provides 14-bit performance.
Figure 29. Transformer Coupled Input
DIFFERENTIAL MODE OF OPERATION
Since not all applications have a signal preconditioned for
differential operation, there is often a need to perform a single-
ended-to-differential conversion. In systems that do not need a
dc input, an RF transformer with a center tap is one method to
generate differential inputs beyond 20 MHz for the AD9203.
This provides all the benefits of operating the A/D in the
differential mode without contributing additional noise or
distortion. An RF transformer also has the benefit of providing
electrical isolation between the signal source and the A/D.
The center tap of the transformer provides a convenient means
of level-shifting the input signal to a desired common-mode
voltage. Figure 30 illustrates the performance of the AD9203
over a wide range of common-mode levels.
Transformers with other turns ratios may also be selected to
optimize the performance of a given application. For example,
selecting a transformer with a higher impedance ratio, such as
minicircuits T16–6T with an impedance ratio of 16, effectively
steps up the signal amplitude, thus further reducing the driving
requirements of the signal source.
An improvement in THD and SFDR performance can be
realized by operating the AD9203 in differential mode. The
performance enhancement between the differential and single-
ended mode is greatest as the input frequency approaches and
goes beyond the Nyquist frequency (i.e., fIN > FS/2).
The AD9203 can be easily configured for either a 1 V p-p or 2 V
p-p input span by setting the internal reference. Other input
spans can be realized with two external gain setting resistors as
shown in Figure 21 of this data sheet. Figure 34 and Figure 35
demonstrate the SNR and SFDR performance over a wide range
of amplitudes required by most communication applications.
The AD8138 provides a convenient method of converting a
single-ended signal to a differential signal. This is an ideal
method for generating a direct coupled signal to the AD9203.
The AD8138 will accept a signal and shift it to an externally
provided common-mode level. The AD8138 configuration is
shown in Figure 28.
–80
1.0V REF
0.5V REF
–70
3V
3V
10µF
10µF
–60
–50
–40
–30
0.1µF
0.1µF
0.1µF
499Ω
10kΩ
28
AVDD DRVDD
AINP
2
6
499Ω
49.9Ω
8
2
5
25
26
20pF
DIGITAL
OUTPUTS
49.9Ω
AD9203
AD8138
AINN
AVSS DRVSS
27
523Ω
49.9Ω
4
1
3
0.1µF
20pF
1
10kΩ
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
499Ω
COMMON-MODE VOLTAGE (V)
Figure 30. THD vs. Common-Mode Voltage vs. THD
(AIN = 2 V Differential) (fIN = 5 MHz, fS = 40 MSPS)
Figure 28. AD8138 Driving an AD9203, a 10-Bit, 40 MSPS A/D Converter
Figure 29 shows the schematic of a suggested transformer
circuit. The circuit uses a Minicircuits RF transformer, model
number T4–1T, which has an impedance ratio of four (turns
ratio of 2).
Rev. B | Page 15 of 28
AD9203
–90
CLOCK INPUT AND CONSIDERATIONS
The AD9203 internal timing uses the two edges of the clock
input to generate a variety of internal timing signals. Sampling
occurs on the falling edge. The clock input to the AD9203
operating at 40 MSPS may have a duty cycle between 45% to
55% to meet this timing requirement since the minimum
specified tCH and tCL is 11.25 ns. For clock rates below 40 MSPS,
the duty cycle may deviate from this range to the extent that
both tCH and tCL are satisfied. See Figure 31 for dynamics vs.
duty cycle.
–80
–70
–60
–50
–40
THD
SNR
High-speed, high-resolution A/Ds are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fIN) due only to aperture jitter (tA) can be
calculated with the following equation:
40.0
42.5
45.0
47.5
50.0
52.5
55.0
57.5
60.0
DUTY CYCLE (%)
Figure 31. THD and SNR vs. Clock Duty Cycle
(fIN = 5 MHz Differential, Clock = 40 MSPS)
SNR degradation = 20 log10 [1/2π fIN tA]
In the equation, the rms aperture jitter, tA, represents the
rootsum square of all the jitter sources, which include the clock
input, analog input signal, and A/D aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
Table 5. Power Programming Resistance
Clock MSPS
1
Resistor Value (k)
50
Clock input should be treated as an analog signal in cases where
aperture jitter may affect the dynamic range of the AD9203.
Power supplies for clock drivers should be separated from the
A/D output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing or another method), it
should be retimed by the original clock at the last step.
5 to 10
15 to 20
>20
100
200
500
POWER CONTROL
Power consumed by the AD9203 may be reduced by placing a
resistor between the PWRCON pin and ground. This function
will be valuable to users who do not need the AD9203’s high
conversion rate, but do need even lower power consumption.
The external resistor sets the programming of the analog
current mirrors. Table 5 illustrates the relationship between
programmed power and performance.
The clock input is referred to the analog supply. Its logic
threshold is AVDD/2.
DIGITAL INPUTS AND OUTPUTS
Each of the AD9203 digital control inputs, 3-STATE, DFS, and
STBY are referenced to analog ground. CLK is also referenced
to analog ground. A low power mode feature is provided such
that for STBY = HIGH and the static power of the AD9203
drops to 0.65 mW.
At lower clock rates, less power is required within the analog
sections of the AD9203. Placing an external resistor on the
PWRCON pin will shunt control current away from some of the
current mirrors. This enables the ADC to convert low data rates
with extremely low power consumption.
Asserting the DFS pin high will invert the MSB pin, changing
the data to a twos complement format.
The AD9203 has an OTR (out of range) function. If the input
voltage is above or below full scale by 1 LSB, the OTR flag will
go high. See Figure 32.
INTERFACING TO 5 V SYSTEMS
The AD9203 can be integrated into 5 V systems. This is
accomplished by deriving a 3 V power supply from the existing
5 V analog power line through an AD3307-3 linear regulator.
Care must be maintained so that logic inputs do not exceed the
maximum rated values listed on the Specifications page.
Rev. B | Page 1ꢁ of 28
AD9203
OTR
OTR
DATA OUTPUTS
1
0
0
11111
11111
11111
11111
11111
11110
0
0
1
00000
00000
00000
00001
00000
00000
–FS
–FS + 1 LSB
+FS
+FS – 1 LSB
Figure 32. Output Data Format
G1 = 20dB
AD9203
G2 = 20dB
BANDPASS
FILTER
SAW FILTER
OUTPUT
MINI CIRCUITS
50Ω
T4-6T
1:4
50Ω
50Ω
AINP
200Ω
22.1Ω
200Ω
AINN
93.1Ω
AVDD/2
Figure 33. Simplified IF Sampling Circuit
Rev. B | Page 1ꢀ of 28
AD9203
APPLICATIONS
The distortion and noise performance of an ADC at the given
IF frequency is of particular concern when evaluating an ADC
for a narrowband IF sampling application. Both single tone and
dual tone SFDR vs. amplitude are very useful in assessing an
ADC’s dynamic and static nonlinearities. SNR vs. amplitude
performance at the given IF is useful in assessing the ADC’s
noise performance and noise contribution due to aperture jitter.
In any application, one is advised to test several units of the
same device under the same conditions to evaluate the given
applications sensitivity to that particular device. Figure 34 and
Figure 35 combine the dual tone SFDR as well as single tone
SFDR and SNR performances at IF frequencies of 70 MHz, and
130 MHz. Note, the SFDR vs. amplitude data is referenced to
dBFS while the single tone SNR data is referenced to dBc. The
performance characteristics in these figures are representative
of the AD9203 without any preceding gain stage. The AD9203
was operated in the differential mode (via transformer) with a
2 V span and a sample rate of 40 MSPS. The analog supply
(AVDD) and the digital supply (DRVDD) were set to 3.0 V.
DIRECT IF DOWN CONVERSION
Sampling IF signals above an ADC’s baseband region (i.e., dc to
FS/2) is becoming increasingly popular in communication
applications. This process is often referred to as direct IF down
conversion or undersampling. There are several potential
benefits in using the ADC to alias (or mix) down a narrow band
or wide band IF signal. First and foremost is the elimination of a
complete mixer stage with its associated amplifiers and filters,
reducing cost and power dissipation. Second is the ability to
apply various DSP techniques to perform such functions as
filtering, channel selection, quadrature demodulation, data
reduction, detection, etc. A detailed discussion on using this
technique in digital receivers can be found in Analog Devices
Application Notes AN-301 and AN-302.
In direct IF down conversion applications, one exploits the
inherent sampling process of an ADC in which an IF signal
lying outside the baseband region can be aliased back into the
baseband region in a manner similar to a mixer downconverting
an IF signal. Similar to the mixer topology, an image rejection
filter is required to limit other potential interfering signals from
also aliasing back into the ADC’s baseband region.
90
SFDR 2 TONE
80
70
SFDR 1 TONE
A trade-off exists between the complexity of this image
rejection filter and the ADC’s sample rate and dynamic range.
60
50
SNR
The AD9203 is well suited for various IF sampling applications.
Its low distortion input SHA has a full-power bandwidth
extending to 130 MHz, thus encompassing many popular IF
frequencies. Only the 2 V span should be used for
undersampling beyond 20 MHz. A DNL of 0.25 LSB
combined with low thermal input referred noise allows the
AD9203 in the 2 V span to provide >59 dB of SNR for a
baseband input sine wave. Also, its low aperture jitter of 1.2 ps
rms ensures minimum SNR degradation at higher IF
frequencies. In fact, the AD9203 is capable of still maintaining
58 dB of SNR at an IF of 70 MHz with a 2 V input span.
40
30
20
10
0
0
5
10
15
20
25
30
INPUT POWER LEVEL (dB FULL SCALE)
Figure 34. SNR/SFDR for IF @ 70 MHz (Clock = 40 MSPS)
80
70
60
50
40
30
20
10
0
SFDR 2 TONE
To maximize its distortion performance, the AD9203 should be
configured in the differential mode with a 2 V span using a
transformer. The center-tap of the transformer is biased to the
reference output of the AD9203. Preceding the AD9203 and
transformer is an optional bandpass filter as well as a gain stage.
A low Q passive bandpass filter can be inserted to reduce out of
band distortion and noise that lies within the AD9203’s 390
MHz bandwidth. A large gain stage(s) is often required to
compensate for the high insertion losses of a SAW filter used for
channel selection and image rejection. The gain stage will also
provide adequate isolation for the SAW filter from the charge
kick back currents associated with the AD9203’s switched
capacitor input stage.
SFDR 1 TONE
SNR
0
5
10
15
20
25
30
35
INPUT POWER LEVEL (dB FULL SCALE)
Figure 35. SNR/SFDR for IF @ 130 MHz (Clock = 40 MSPS)
Rev. B | Page 18 of 28
AD9203
AD9203 is powered from a 3 V supply rail while the high
ULTRASOUND APPLICATIONS
performance AD604 is powered from 5 V supply rails. An
AD8138 is used to drive the AD9203. This is implemented due
to the ability of differential drive techniques to cancel common-
mode noise and input anomalies.
The AD9203 provides excellent performance in 10-bit
ultrasound applications. This is demonstrated by its high SNR
with analog input frequencies up to and including Nyquist. The
presence of spurs near the base of a fundamental frequency bin
is demonstrated by Figure 37. Note that the spurs near the noise
floor are more than 80 dB below fIN. This is especially valuable
in Doppler ultrasound applications where low frequency shifts
from the fundamental are important.
The 74 mW power consumption gives the 40 MSPS AD9203 an
order of magnitude improvement over older generation
components.
10
FUND
CONDITIONED
TRANSDUCER
SIGNAL
SNR = 59.9dB
THD = –75dB
SFDR = 82dB
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
SINGLE-
3V
ANALOG
INPUT
ENDED
AD9203
ANALOG
AINP
AD604
AD8138
TGC
AMPLIFIER
AINN
GAIN
CONTROL
1.5V
3V
Figure 36. Ultrasound Connection for the AD9203
4.5E+6
4.7E+6
4.9E+6
5.1E+6
5.3E+6
5.5E+6
fIN
Figure 36 illustrates the AD604 variable gain amplifier
configured for time gain compensation (TGC). The low power
Figure 37. SFDR Performance Near the Fundamental Signal (8192 Point FFT,
fIN = 5 MHz, FS = 40 MSPS)
Rev. B | Page 19 of 28
AD9203
EVALUATION BOARD
for single-ended and differential operation as well as 1 V and
2 V spans. Refer to Figure 39.
The AD9203 evaluation board is shipped wired for 2 V
differential operation. The board should be connected to power
and test equipment as shown in Figure 38. It is easily configured
3V
3V
3V
3V
+
–
–
+
+
–
+
–
DRVDD
GND
+3-5D
AVDD
GND
AVEE
J1
ANALOG
INPUT
ANTI-
ALIASING
FILTER
SYNTHESIZER
1MHz 1.9V p-p
HP8644
OUTPUT
WORD
DSP
EQUIPMENT
AD9203
EVALUATION BOARD
J5
SYNTHESIZER
40MHz 1V p-p
HP8644
EXTERNAL
CLOCK
Figure 38. Evaluation Board Connection
Rev. B | Page 20 of 28
AD9203
Figure 39. Evaluation Board (Rev. C)
Rev. B | Page 21 of 28
AD9203
Figure 40. Evaluation Board (Rev. C)
Rev. B | Page 22 of 28
AD9203
Figure 41. Evaluation Board Component Side Assembly (Not to Scale)
Figure 42. Evaluation Board Component Side (Not to Scale)
Figure 43. Evaluation Board Solder Side Assembly (Not to Scale)
Rev. B | Page 23 of 28
AD9203
Figure 44. Evaluation Board Solder Side (Not to Scale)
Figure 45. Evaluation Board Ground Plane (Not to Scale)
Figure 46. Evaluation Board Power Plane (Not to Scale)
Rev. B | Page 24 of 28
AD9203
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 47. 28-Lead Thin Shrink Small Outline Package
(RU-28)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
RU-28
RU-28
RU-28
RU-28
AD9203ARU
AD9203ARURLꢀ
AD9203ARUZ1
AD9203ARUZRLꢀ1
AD9203-EB
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
28-Lead Thin Shrink Small Outline
28-Lead Thin Shrink Small Outline
28-Lead Thin Shrink Small Outline
28-Lead Thin Shrink Small Outline
Evaluation Board
1 Z = Pb-free part.
Rev. B | Page 25 of 28
AD9203
NOTES
Rev. B | Page 2ꢁ of 28
AD9203
NOTES
Rev. B | Page 2ꢀ of 28
AD9203
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00573–0–8/04(B)
Rev. B | Page 28 of 28
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