AD9222_技术文档

Octal, 12-Bit, 40/50 MSPS

Serial LVDS 1.8 V A/D Converter

AD9222

FEATURES

8 ADCs integrated into 1 package

93 mW ADC power per channel at 50 MSPS

SNR = 70 dB (to Nyquist)

ENOB = 11.3 bits

SFDR = 84 dBc

Excellent linearity

DNL = 0.3 LSB (typical)

INL = 0.4 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power reduced signal option, IEEE 1596.3 similar

Data and frame clock outputs

325 MHz full power analog bandwidth

2 V p-p input voltage range

1.8 V supply operation

Serial port control

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

FUNCTIONAL BLOCK DIAGRAM

AVDD

PDWN

DRVDD

DRGND

AD9222

12

VIN+A

VIN–A

D+A

D–A

SERIAL

LVDS

ADC

12

VIN+B

VIN–B

D+B

D–B

SERIAL

LVDS

VIN+C

VIN–C

D+C

D–C

SERIAL

LVDS

ADC

12

VIN+D

VIN–D

D+D

D–D

SERIAL

LVDS

ADC

VIN+E

VIN–E

SERIAL

LVDS

D+E

D–E

12

VIN+F

VIN–F

D+F

D–F

SERIAL

LVDS

VIN+G

VIN–G

D+G

D–G

SERIAL

LVDS

ADC

12

VIN+H

VIN–H

D+H

D–H

SERIAL

LVDS

APPLICATIONS

VREF

Medical imaging and nondestructive ultrasound

Portable ultrasound and digital beam forming systems

Quadrature radio receivers

Diversity radio receivers

FCO+

FCO–

SENSE

0.5V

DATA RATE

REFT

REFB

REF

SELECT

MULTIPLIER

SERIAL PORT

INTERFACE

DCO+

DCO–

Tape drives

Optical networking

Test equipment

SCLK/

DTP

RBIAS AGND CSB SDIO/

ODM

CLK+

CLK–

Figure 1.

GENERAL DESCRIPTION

The ADC contains several features designed to maximize

The AD9222 is an octal, 12-bit, 40/50 MSPS analog-to-digital

converter (ADC) with an on-chip sample-and-hold circuit that

is designed for low cost, low power, small size, and ease of use.

The product operates at a conversion rate of up to 50 MSPS and

is optimized for outstanding dynamic performance and low

power in applications where a small package size is critical.

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom user-

defined test patterns entered via the serial port interface (SPI®).

The AD9222 is available in a Pb-free, 64-lead LFCSP package. It is

specified over the industrial temperature range of −40°C to +85°C.

The ADC requires a single 1.8 V power supply and LVPECL-/

CMOS-/LVDS-compatible sample rate clock for full performance

operation. No external reference or driver components are

required for many applications.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight ADCs are contained in a small, space-

saving package; low power of 93 mW/channel at 50 MSPS.

2. Ease of Use. A data clock output (DCO) operates up to

300 MHz and supports double data rate operation (DDR).

3. User Flexibility. Serial port interface (SPI) control offers a wide

range of flexible features to meet specific system requirements.

The ADC automatically multiplies the sample rate clock for

the appropriate LVDS serial data rate. A data clock (DCO)

for capturing data on the output and a frame clock (FCO) for

signaling a new output byte are provided. Individual channel

power-down is supported and typically consumes less than

2 mW when all channels are disabled.

4. Pin-Compatible Family. This includes the AD9212 (10-bit),

and AD9252 (14-bit).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9222

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Diagrams.............................................................................. 7

Absolute Maximum Ratings............................................................ 9

Thermal Impedance..................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Equivalent Circuits......................................................................... 12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 18

Analog Input Considerations ................................................... 18

Clock Input Considerations...................................................... 21

Serial Port Interface (SPI).............................................................. 29

Hardware Interface..................................................................... 30

Memory Map .................................................................................. 32

Reading the Memory Map Table.............................................. 32

Reserved Locations .................................................................... 32

Default Values............................................................................. 32

Logic Levels................................................................................. 32

Evaluation Board ............................................................................ 36

Power Supplies............................................................................ 36

Input Signals................................................................................ 36

Output Signals ............................................................................ 36

Default Operation and Jumper Selection Settings................. 37

Alternative Analog Input Drive Configuration...................... 38

Outline Dimensions....................................................................... 55

Ordering Guide .......................................................................... 55

REVISION HISTORY

9/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 56

AD9222

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.

AD9222-40

Min Typ

AD9222-50

Min Typ

Parameter¹

Temperature

Max

Unit

RESOLUTION

12

Bits

ACCURACY

No Missing Codes

Offset Error

Offset Matching

Gain Error

Full

Guaranteed

±1

±3

±0.ꢀ

±0.3

Guaranteed

±1

±3

±1.5

±0.3

±±

±1.2

±0.ꢁ

±0.5

±1

±±

mV

±±

mV

±2.5

±0.ꢁ

% FS

Gain Matching

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error

Gain Error

Reference Voltage (1 V Mode)

REFERENCE

±0.25

±0.ꢀ

±0.3

±0.ꢀ

±0.65 LSB

±1

LSB

Full

±2

±1ꢁ

±21

±2

±1ꢁ

±21

ppm/°C

Output Voltage Error (VREF = 1 V)

Load Regulation @ 1.0 mA (VREF = 1 V)

Input Resistance

Full

±2

3

6

±30

±2

3

6

±30

mV

kΩ

ANALOG INPUTS

Differential Input Voltage Range (VREF = 1 V)

Common-Mode Voltage

Differential Input Capacitance

Analog Bandwidth, Full Power

POWER SUPPLY

Full

2

V p-p

V

pF

AVDD/2

ꢁ

325

AVDD/2

ꢁ

325

MHz

AVDD

DRVDD

IAVDD

IDRVDD

Full

1.ꢁ

1.±

33±

51

ꢁ00

2

1.9

3ꢀ±.5

53.6

ꢁ22

11

1.ꢁ

1.±

35ꢁ.5

53.5

ꢁꢀ0

2

1.9

V

36ꢁ.5 mA

56.2

ꢁ60

11

mA

mW

dB

Total Power Dissipation (Including Output Drivers)

Power-Down Dissipation

Standby Dissipation²

CROSSTALK

±3

±9

−90

CROSSTALK (Overrange Condition)³

dB

¹See the AN-±35 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

²Can be controlled via SPI.

³Overrange condition is specific with 6 dB of the full-scale input range.

Rev. 0 | Page 3 of 56

AD9222

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 2.

AD9222-40

Typ

AD9222-50

Typ

Parameter¹

Temperature Min

Max Min

Max Unit

dB

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 2.ꢀ MHz

Full

ꢁ0.3

ꢁ0.ꢀ

f_IN= 19.ꢁ MHz Full

69.5

ꢁ0.3

69.5

ꢁ0.3

dB

f_IN= 35 MHz

f_IN= ꢁ0 MHz

Full

69.9

6±.±

ꢁ0.0

69.0

dB

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) f_IN= 2.ꢀ MHz

ꢁ0.0

dB

f_IN= 19.ꢁ MHz Full

6±.ꢁ

ꢁ0.0

6±.5

ꢁ0.0

dB

f_IN= 35 MHz

f_IN= ꢁ0 MHz

f_IN= 2.ꢀ MHz

Full

69.5

6±.0

69.±

6±.5

dB

EFFECTIVE NUMBER OF BITS (ENOB)

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

WORST HARMONIC (Second or Third)

WORST OTHER (Excluding Second or Third)

11.3±

11.25 11.3±

11.32

11.ꢀ

11.25 11.3±

11.33

Bits

f_IN= 19.ꢁ MHz Full

f_IN= 35 MHz

f_IN= ꢁ0 MHz

f_IN= 2.ꢀ MHz

Full

11.1ꢀ

11.1ꢁ

±5

±0

ꢁ6

±5

±ꢀ

±3

ꢁꢁ

dBc

f_IN= 19.ꢁ MHz Full

ꢁ3

f_IN= 35 MHz

f_IN= ꢁ0 MHz

f_IN= 2.ꢀ MHz

Full

−±5

−±0

−ꢁ6

−92

−90

±0.0

−±5

−±ꢀ

−±3

−ꢁꢁ

−92

−90

±0.0

dBc

−ꢁ3 dBc

dBc

f_IN= 19.ꢁ MHz Full

−ꢁꢀ

−±0

f_IN= 35 MHz

f_IN= ꢁ0 MHz

f_IN= 2.ꢀ MHz

f_IN= 19.ꢁ MHz Full

f_IN= 35 MHz

f_IN= ꢁ0 MHz

Full

dBc

−±0 dBc

dBc

Full

dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)— f_IN1= 15 MHz, 25°C

dBc

AIN1 AND AIN2 = −ꢁ.0 dBFS

f_IN2= 16 MHz

f_IN1= ꢁ0 MHz, 25°C

f_IN2= ꢁ1 MHz

ꢁꢁ.0

dBc

¹See the AN-±35 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

Rev. 0 | Page ꢀ of 56

AD9222

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 3.

AD9222-40

Typ Max

AD9222-50

Typ Max

Parameter¹

Temperature

Min

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage²

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

Full

25°C

250

mV p-p

V

kΩ

pF

1.2

20

1.5

1.2

20

1.5

LOGIC INPUTS (PDWN, SCLK/DTP)

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

Input Capacitance

Full

25°C

1.2

0

3.6

0.3

1.2

3.6

0.3

V

kΩ

pF

30

0.5

30

0.5

LOGIC INPUT (CSB)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

0

3.6

0.3

3.6

0.3

V

Input Resistance

Input Capacitance

25°C

ꢁ0

0.5

ꢁ0

0.5

kΩ

pF

LOGIC INPUT (SDIO/ODM)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

0

DRVDD + 0.3 1.2

DRVDD + 0.3

0.3

V

0.3

0

Input Resistance

Input Capacitance

25°C

30

2

30

2

kΩ

pF

LOGIC OUTPUT (SDIO/ODM)³

Logic 1 Voltage (I_OH= ±00 μA)

Logic 0 Voltage (I_OL= 50 μA)

DIGITAL OUTPUTS (D+, D−), (ANSI-6ꢀꢀ)¹

Logic Compliance

Full

1.ꢁ9

0.05

1.ꢁ9

0.05

V

LVDS

Differential Output Voltage (V_OD

)

Full

2ꢀꢁ

1.125

ꢀ5ꢀ

1.3ꢁ5

2ꢀꢁ

1.125

ꢀ5ꢀ

1.3ꢁ5

mV

V

Output Offset Voltage (V_OS

)

Output Coding (Default)

Offset binary

DIGITAL OUTPUTS (D+, D−),

(Low Power, Reduced Signal Option)¹

Logic Compliance

LVDS

Differential Output Voltage (V_OD

)

Full

150

1.10

250

1.30

150

1.10

250

1.30

mV

V

Output Offset Voltage (V_OS

)

Output Coding (Default)

Offset binary

¹See the AN-±35 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

²This is specified for LVDS and LVPECL only.

³This is specified for 13 SDIO pins sharing the same connection.

Rev. 0 | Page 5 of 56

AD9222

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

AD9222-40

Typ

AD9222-50

Typ

Parameter¹

CLOCK²

Temp

Min

Max

Min

Max

Unit

Maximum Clock Rate

Minimum Clock Rate

Clock Pulse Width High (t_EH)

Clock Pulse Width Low (t_EL)

Full

ꢀ0

50

MSPS

ns

10

12.5

10.0

ns

OUTPUT PARAMETERS^{2, 3}

Propagation Delay (t_PD)

Full

1.5

2.3

3.1

1.5

2.3

3.1

ns

ps

ns

Rise Time (t_R) (20% to ±0%)

Fall Time (t_F) (20% to ±0%)

FCO Propagation Delay (t_FCO

300

2.3

300

2.3

)

ꢀ

DCO Propagation Delay (t_CPD

)

t_FCO

+

t_FCO

+

(t_SAMPLE/2ꢀ)

ꢀ

Full

(t_SAMPLE/2ꢀ) − 300 (t_SAMPLE/2ꢀ) (t_SAMPLE/2ꢀ) + 300 (t_SAMPLE/2ꢀ) − 300 (t_SAMPLE/2ꢀ) (t_SAMPLE/2ꢀ) + 300 ps

DCO to Data Delay (t_DATA

)

ꢀ

DCO to FCO Delay (t_FRAME

Data to Data Skew

)

±50

±200

±50

±200

ps

(t_DATA-MAX− t_DATA-MIN

)

Wake-Up Time (Standby)

25°C

Full

600

3ꢁ5

±

600

3ꢁ5

±

ns

μs

Wake-Up Time (Power Down)

Pipeline Latency

CLK

cycles

APERTURE

Aperture Delay (t_A)

25°C

ꢁ50

<1

1

ꢁ50

<1

1

ps

Aperture Uncertainty (Jitter)

Out-of-Range Recovery Time

ps rms

CLK

cycles

¹See the AN-±35 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

²Can be adjusted via the SPI interface.

³Measurements were made using a part soldered to FRꢀ material.

^ꢀt_SAMPLE/2ꢀ is based on the number of bits divided by 2 because the delays are based on half duty cycles.

Rev. 0 | Page 6 of 56

AD9222

TIMING DIAGRAMS

N – 1

AIN

t_A

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

t_PD

t_DATA

D–

D+

MSB

N – 8

D10

N – 8

D9

N – 8

D8

N – 8

D7

N – 8

D6

N – 8

D5

N – 8

D4

N – 8

D3

N – 8

D2

N – 8

D1

N – 8

D0

N – 8

MSB

N – 7

D10

N – 7

Figure 2. 12-Bit Data Serial Stream (Default)

N – 1

AIN

t_A

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

D–

t_PD

t_DATA

MSB

N – 8

D8

N – 8

D7

D6

D5

D4

D3

D2

D1

D0

MSB

D8

D7

D6

D5

N – 8 N – 8

N – 8 N – 8 N – 8 N – 8

N – 8 N – 8 N – 7 N – 7

N – 7 N – 7 N – 7

D+

Figure 3. 10-Bit Data Serial Stream

Rev. 0 | Page ꢁ of 56

AD9222

N – 1

AIN

t_A

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

t_PD

t_DATA

D–

D+

LSB

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

LSB

D0

(N – 8) (N – 8) (N – 8) (N – 8) (N – 8) (N – 8) (N – 8) (N – 8) (N – 8) (N – 8) (N – 8) (N – 8) (N – 7) (N – 7)

Figure 4. 12-Bit Data Serial Stream, LSB First

Rev. 0 | Page ± of 56

AD9222

ABSOLUTE MAXIMUM RATINGS

Table 5.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

With

Respect To

Parameter

ELECTRICAL

AVDD

DRVDD

AGND

Rating

AGND

−0.3 V to +2.0 V

−0.3 V to +0.3 V

−2.0 V to +2.0 V

−0.3 V to +2.0 V

DRGND

DRVDD

DRGND

AVDD

Digital Outputs

THERMAL IMPEDANCE

(D+, D−, DCO+,

DCO−, FCO+, FCO−)

CLK+, CLK−

VIN+, VIN−

SDIO/ODM

PDWN, SCLK/DTP, CSB

REFT, REFB, RBIAS

VREF, SENSE

Table 6.

Air Flow

Velocity (m/s)

AGND

−0.3 V to +3.9 V

−0.3 V to +2.0 V

−0.3 V to +3.9 V

−0.3 V to +2.0 V

1

θ_JA

θ_JB

θ_JC

0.0

1.0

2.5

1ꢁ.ꢁ°C/W

15.5°C/W

13.9°C/W

±.ꢁ°C/W

0.6°C/W

¹θ_JAfor a ꢀ-layer PCB with solid ground plane (simulated). Exposed pad

soldered to PCB.

ENVIRONMENTAL

Operating Temperature

Range (Ambient)

Maximum Junction

Temperature

−ꢀ0°C to +±5°C

150°C

ESD CAUTION

Lead Temperature

(Soldering, 10 sec)

300°C

Storage Temperature

Range (Ambient)

−65°C to +150°C

Rev. 0 | Page 9 of 56

AD9222

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

AVDD

VIN+G

VIN–G

AVDD

VIN–H

VIN+H

AVDD

CLK–

CLK+ 10

AVDD 11

AVDD 12

DRGND 13

DRVDD 14

D–H 15

1

2

3

4

5

6

7

8

9

48 AVDD

47 VIN+B

46 VIN–B

45 AVDD

44 VIN–A

43 VIN+A

42 AVDD

41 PDWN

40 CSB

39 SDIO/ODM

38 SCLK/DTP

37 AVDD

36 DRGND

35 DRVDD

34 D+A

EXPOSED PADDLE, PIN 0

(BOTTOM OF PACKAGE)

AD9222

TOP VIEW

(Not to Scale)

D+H 16

33 D–A

NC = NO CONNECT

Figure 5. 64-Lead LFCSP Top View

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

0

AGND

AVDD

Analog Ground (Exposed Paddle)

1.± V Analog Supply

1, ꢀ, ꢁ, ±, 11,

12, 3ꢁ, ꢀ2, ꢀ5,

ꢀ±, 51, 59, 62

13, 36

1ꢀ, 35

2

3

5

DRGND

DRVDD

VIN+G

VIN−G

VIN−H

VIN+H

CLK−

CLK+

D−H

D+H

D−G

D+G

D−F

D+F

D−E

D+E

DCO−

DCO+

FCO−

FCO+

D−D

Digital Output Driver Ground

1.± V Digital Output Driver Supply

ADC G Analog Input—True

ADC G Analog Input—Complement

ADC H Analog Input—Complement

ADC H Analog Input—True

6

9

Input Clock—Complement

Input Clock—True

10

15

16

1ꢁ

1±

19

20

21

22

23

2ꢀ

25

26

2ꢁ

2±

29

30

31

32

33

ADC H Digital Output—Complement

ADC H True Digital Output—True

ADC G Digital Output—Complement

ADC G True Digital Output—True

ADC F Digital Output—Complement

ADC F True Digital Output—True

ADC E Digital Output—Complement

ADC E True Digital Output—True

Data Clock Digital Output—Complement

Data Clock Digital Output—True

Frame Clock Digital Output—Complement

Frame Clock Digital Output—True

ADC D Digital Output—Complement

ADC D True Digital Output—True

ADC C Digital Output—Complement

ADC C True Digital Output

D+D

D−C

D+C

D−B

D+B

D−A

ADC B Digital Output—Complement

ADC B True Digital Output—True

ADC A Digital Output—Complement

Rev. 0 | Page 10 of 56

AD9222

Pin No.

3ꢀ

3±

39

ꢀ0

ꢀ1

ꢀ3

ꢀꢀ

ꢀ6

ꢀꢁ

ꢀ9

50

52

53

5ꢀ

55

56

5ꢁ

5±

60

61

63

6ꢀ

Mnemonic

D+A

SCLK/DTP

SDIO/ODM

CSB

PDWN

VIN+A

VIN−A

VIN−B

VIN+B

VIN+C

VIN−C

VIN−D

VIN+D

RBIAS

Description

ADC A True Digital Output—True

Serial Clock/Digital Test Pattern

Serial Data Input-Output/Output Driver Mode

Chip Select Bar

Power Down

ADC A Analog Input—True

ADC A Analog Input—Complement

ADC B Analog Input—Complement

ADC B Analog Input—True

ADC C Analog Input—True

ADC C Analog Input—Complement

ADC D Analog Input—Complement

ADC D Analog Input—True

External Resistor to Set the Internal ADC Core Bias Current

Reference Mode Selection

Voltage Reference Input/Output

Differential Reference (Negative)

Differential Reference (Positive)

ADC E Analog Input—True

ADC E Analog Input—Complement

ADC F Analog Input—Complement

ADC F Analog Input—True

SENSE

VREF

REFB

REFT

VIN+E

VIN−E

VIN−F

VIN+F

Rev. 0 | Page 11 of 56

AD9222

EQUIVALENT CIRCUITS

DRVDD

V

D–

D+

VIN

V

DRGND

Figure 9. Equivalent Digital Output Circuit

Figure 6. Equivalent Analog Input Circuit

10Ω

CLK

10kΩ

1.25V

1kΩ

SCLK/DTP OR PDWN

10Ω

CLK

30kΩ

Figure 7. Equivalent Clock Input Circuit

Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit

100Ω

RBIAS

350Ω

SDIO/ODM

30kΩ

Figure 11. Equivalent RBIAS Circuit

Figure 8. Equivalent SDIO/ODM Input Circuit

Rev. 0 | Page 12 of 56

AD9222

AVDD

70kΩ

1kΩ

CSB

VREF

6kΩ

Figure 12. Equivalent CSB Input Circuit

Figure 14. Equivalent VREF Circuit

1kΩ

SENSE

Figure 13. Equivalent SENSE Circuit

Rev. 0 | Page 13 of 56

AD9222

TYPICAL PERFORMANCE CHARACTERISTICS

0

–20

0

AIN = –0.5dBFS

SNR = 70.35dB

ENOB = 11.40 BITS

SFDR = 83.86dBc

AIN = –0.5dBFS

SNR = 70.79dB

ENOB = 11.47 BITS

–20

SFDR = 84.71dBc

–40

–60

–80

–100

–120

–100

–120

0

5

10

15

20

25

0

2

4

6

8

10

12

14

16

18

20

FREQUENCY (MHz)

Figure 18. Single-Tone 32k FFT with f_IN= 35 MHz, AD9222-50

Figure 15. Single-Tone 32k FFT with f_IN= 2.3 MHz, AD9222-40

0

AIN = –0.5dBFS

SNR = 70.02dB

ENOB = 11.45 BITS

AIN = –0.5dBFS

SNR = 70.32dB

ENOB = 11.39 BITS

–20

–40

SFDR = 86.3dBc

SFDR = 84.28dBc

–40

–60

–80

–60

–80

–100

–120

0

2

4

6

8

10

12

14

16

18

20

0

5

10

15

20

25

FREQUENCY (MHz)

Figure 16. Single-Tone 32k FFT with f_IN= 19.7 MHz, AD9222-40

Figure 19. Single-Tone 32k FFT with f_IN= 70 MHz, AD9222-50

0

AIN = –0.5dBFS

SNR = 70.72dB

ENOB = 11.45 BITS

AIN = –0.5dBFS

SNR = 69.25dB

ENOB = 11.21 BITS

–20

–40

SFDR = 85.79dBc

SFDR = 72.85dBc

–40

–60

–80

–100

–120

–100

–120

0

5

10

15

20

25

0

5

10

15

20

25

FREQUENCY (MHz)

Figure 17. Single-Tone 32k FFT with f_IN= 2.3 MHz, AD9222-50

Figure 20. Single-Tone 32k FFT with f_IN= 120 MHz, AD9222-50

Rev. 0 | Page 1ꢀ of 56

AD9222

100

95

90

85

80

75

70

65

60

100

90

80

70

60

50

40

30

20

10

0

F

= 35MHz

IN

SAMPLE

= 50MSPS

2V p-p, SFDR

80dB

REFERENCE

2V p-p, SNR

10

15

20

25

30

35

40

45

50

–60

–50

–40

–30

–20

–10

0

ENCODE (MSPS)

INPUT AMPLITUDE (dBFS)

Figure 21. SNR/SFDR vs. f_SAMPLE, f_IN= 2.61 MHz, AD9222-50

Figure 24. SNR/SFDR vs. Analog Input Level, f_IN= 35 MHz, AD9222-50

90

0

AIN1 AND AIN2 = –7dBFS

SFDR = 89.87dB

IMD2 = 96.07dBc

85

80

75

70

65

60

–20

–40

IMD3 = 90.16dBc

2V p-p, SFDR

–60

–80

2V p-p, SNR

–100

–120

10

15

20

25

30

35

40

45

50

0

2

4

6

8

10

12

14

16

18

20

ENCODE (MSPS)

FREQUENCY (MHz)

Figure 22. SNR/SFDR vs. f_SAMPLE, f_IN= 20.1 MHz, AD9222-50

Figure 25. Two-Tone 32k FFT with f_IN1= 15 MHz and f_IN2= 16 MHz,

AD9222-40

100

90

80

70

60

50

40

30

20

10

0

F

= 10.3MHz

AIN1 AND AIN2 = –7dBFS

SFDR = 77.24dB

IMD2 = 91.66dBc

IN

SAMPLE

= 50MSPS

–20

–40

IMD3 = 77.72dBc

2V p-p, SFDR

80dB

REFERENCE

–60

–80

2V p-p, SNR

–100

–120

–60

–50

–40

–30

–20

–10

0

2

4

6

8

10

12

14

16

18

20

INPUT AMPLITUDE (dBFS)

FREQUENCY (MHz)

Figure 23. SNR/SFDR vs. Analog Input Level, f_IN= 10.3 MHz, AD9222-50

Figure 26. Two-Tone 32k FFT with f_IN1= 70 MHz and f_IN2= 71 MHz,

AD9222-40

Rev. 0 | Page 15 of 56

AD9222

0

100

95

90

85

80

75

70

65

60

AIN1 AND AIN2 = –7dBFS

SFDR = 84.49dB

IMD2 = 85.83dBc

IMD3 = 84.54dBc

–20

–40

2V p-p, SFDR

2V p-p, SINAD

–60

–80

–100

–120

0

5

10

15

20

25

–40

–20

0

20

40

60

80

FREQUENCY (MHz)

TEMPERATURE (°C)

Figure 27. Two-Tone 32k FFT with f_IN1= 15 MHz and

f_IN2= 16 MHz, AD9222-50

Figure 30. SINAD/SFDR vs. Temperature, f_IN= 2.61 MHz, AD9222-50

90

85

0

–20

AIN1 AND AIN2 = –7dBFS

SFDR = 80.42dB

IMD2 = 83.92dBc

IMD3 = 80.60dBc

2V p-p, SFDR

80

–40

75

–60

2V p-p, SINAD

70

–80

65

–100

–120

60

–40

–20

0

20

40

60

80

0

5

10

15

20

25

TEMPERATURE (°C)

FREQUENCY (MHz)

Figure 31. SINAD/SFDR vs. Temperature, f_IN= 20.1 MHz, AD9222-50

Figure 28. Two-Tone 32k FFT with f_IN1= 70 MHz and

f_IN2= 71 MHz, AD9222-50

1.0

0.8

90

85

80

75

70

65

60

0.6

SFDR

SNR

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

1

10

100

1000

ANALOG INPUT FREQUENCY (MHz)

Figure 29. SNR/SFDR vs. f_IN, AD9222-50

Figure 32. INL, f_IN= 2.3 MHz, AD9222-50

Rev. 0 | Page 16 of 56

AD9222

0

–20

0.5

0.4

NPR = 60.3dB

NOTCH = 18.0MHz

NOTCH WIDTH = 3.0MHz

0.3

0.2

–40

0.1

–60

0

–0.1

–0.2

–0.3

–0.4

–0.5

–80

–100

–120

0

5

10

15

20

25

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

FREQUENCY (MHz)

Figure 36. Noise Power Ratio (NPR), AD9222-50

Figure 33. DNL, f_IN= 2.3 MHz, AD9222-50

–30

–35

–40

–45

–50

–55

–60

–65

–70

0

–1

–3dB BANDWIDTH = 325MHz

–2

–3

–4

–5

–6

–7

–8

–9

–10

–11

0

5

10

15

20

25

30

35

40

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

Figure 37. Full Power Bandwidth vs. Frequency, AD9222-50

Figure 34. CMRR vs. Frequency, AD9222-50

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

0.27 LSB rms

N – 3

N – 2

N – 1

N

N + 1

N + 2

N + 3

CODE

Figure 35. Input Referred Noise Histogram, AD9222-50

Rev. 0 | Page 1ꢁ of 56

AD9222

THEORY OF OPERATION

The AD9222 architecture consists of a pipelined ADC that is

divided into three sections: a 4-bit first stage followed by eight

1.5-bit stages and a final 3-bit flash. Each stage provides

sufficient overlap to correct for flash errors in the preceding

stages. The quantized outputs from each stage are combined

into a final 12-bit result in the digital correction logic. The

pipelined architecture permits the first stage to operate on a

new input sample while the remaining stages operate on preceding

samples. Sampling occurs on the rising edge of the clock.

The clock signal alternately switches the input circuit between

sample mode and hold mode (see Figure 38). When the input

circuit is switched into sample mode, the signal source must be

capable of charging the sample capacitors and settling within

one-half of a clock cycle. A small resistor in series with each

input can help reduce the peak transient current injected from

the output stage of the driving source. In addition, low-Q inductors

or ferrite beads can be placed on each leg of the input to reduce

the high differential capacitance seen at the analog inputs, thus

realizing the maximum bandwidth of the ADC. Such use of

low-Q inductors or ferrite beads is required when driving the

converter front end at high IF frequencies. Either a shunt capacitor

or two single-ended capacitors can be placed on the inputs to

provide a matching passive network. This ultimately creates a

low-pass filter at the input to limit any unwanted broadband

noise. See the AN-742 Application Note, the AN-827 Application

Note, and the Analog Dialogue article “Transformer-Coupled

Front-End for Wideband A/D Converters” for more information

on this subject. In general, the precise values depend on the

application.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The output staging block aligns the data, carries out the error

correction, and passes the data to the output buffers. The data is

then serialized and aligned to the frame and output clock.

ANALOG INPUT CONSIDERATIONS

The analog inputs of the AD9222 are not internally dc-biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that V_CM= AVDD/2 is recom-

mended for optimum performance, but the device can function

over a wider range with reasonable performance, as shown in

Figure 39 and Figure 40.

The analog input to the AD9222 is a differential switched-capacitor

circuit designed for processing differential input signals. The input

can support a wide common-mode range and maintain excellent

performance. An input common-mode voltage of midsupply

minimizes signal-dependent errors and provides optimum

performance.

H

C_PAR

H

VIN+

C_SAMPLE

S

C_SAMPLE

VIN–

H

C_PAR

H

Figure 38. Switched-Capacitor Input Circuit

Rev. 0 | Page 1± of 56

AD9222

90

85

80

75

70

65

60

90

85

80

75

70

65

60

SFDR (dBc)

SNR (dB)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

ANALOG INPUT COMMON-MODE VOLTAGE (V)

Figure 39. SNR/SFDR vs. Common-Mode Voltage,

f_IN= 2.3 MHz, AD9222-50

Figure 40. SNR/SFDR vs. Common-Mode Voltage,

f_IN= 35 MHz, AD9222-50

Rev. 0 | Page 19 of 56

AD9222

ADT1–1WT

1:1 Z RATIO

For best dynamic performance, the source impedances driving

VIN+ and VIN− should be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC. An internal reference

buffer creates the positive and negative reference voltages, REFT

and REFB, respectively, that define the span of the ADC core.

The output common-mode of the reference buffer is set to

midsupply, and the REFT and REFB voltages and span are

defined as

C

R

VIN+

VIN–

ADC

1

2Vp-p

49.9ꢀ

C

DIFF

C

AD9222

R

AVDD

1kꢀ

AGND

1kꢀ

0.1μF

1

C

IS OPTIONAL.

DIFF

Figure 41. Differential Transformer-Coupled Configuration

for Baseband Applications

REFT = 1/2 (AVDD + VREF)

REFB = 1/2 (AVDD − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

ADT1–1WT

1:1 Z RATIO

2Vp-p

16nH

16nH 0.1μF

33ꢀ

VIN+

It can be seen from these equations that the REFT and REFB

voltages are symmetrical about the midsupply voltage and, by

definition, the input span is twice the value of the VREF voltage.

65ꢀ

ADC

499ꢀ

16nH

2.2pF

1kꢀ

AD9222

33ꢀ

VIN–

AVDD

Maximum SNR performance is always achieved by setting the

ADC to the largest span in a differential configuration. In the

case of the AD9222, the largest input span available is 2 V p-p.

1kꢀ

0.1μF

Figure 42. Differential Transformer-Coupled Configuration for IF Applications

Differential Input Configurations

Single-Ended Input Configuration

There are several ways in which to drive the AD9222 either

actively or passively. In either case, the optimum performance is

achieved by driving the analog input differentially. One example

is by using the AD8334 differential driver. It provides excellent

performance and a flexible interface to the ADC (see Figure 44)

for baseband applications. This configuration is common for

medical ultrasound systems.

A single-ended input may provide adequate performance in

cost-sensitive applications. In this configuration, SFDR and

distortion performance degrade due to the large input common-

mode swing. If the application requires a single-ended input

configuration, ensure that the source impedances on each input

are well matched in order to achieve the best possible performance.

A full-scale input of 2 V p-p can still be applied to the ADC’s VIN+

pin while the VIN− pin is terminated. Figure 43 details a typical

single-ended input configuration.

However, the noise performance of most amplifiers is not

adequate to achieve the true performance of the AD9222. For

applications where SNR is a key parameter, differential transfor-

mer coupling is the recommended input configuration. Two

examples are shown in Figure 41 and Figure 42.

AVDD

C

R

VIN+

In any configuration, the value of the shunt capacitor, C, is

dependent on the input frequency and may need to be reduced

or removed.

0.1µF

AVDD

1kꢀ

2V p-p

49.9ꢀ

ADC

1

C

DIFF

AD9222

1kꢀ

25ꢀ

R

C

VIN–

0.1µF

1kꢀ

1

C

IS OPTIONAL.

DIFF

Figure 43. Single-Ended Input Configuration

0.1μF

LOP

VIP

0.1μF

187ꢀ

374ꢀ

R

VOH

VOL

0.1μF 120nH

INH

VIN+

1V p-p

AD8334

1.0kꢀ

22pF

ADC

AD9222

LNA

VGA

C

LMD

VIN–

VREF

0.1μF

187ꢀ

0.1μF

10μF

LON

VIN

274ꢀ

18nF

0.1μF

Figure 44. Differential Input Configuration Using the AD8334

Rev. 0 | Page 20 of 56

AD9222

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

CLK+ should be directly driven from a CMOS gate, and the

CLK− pin should be bypassed to ground with a 0.1 μF capacitor

in parallel with a 39 kΩ resistor (see Figure 48). Although the

CLK+ input circuit supply is AVDD (1.8 V), this input is

designed to withstand input voltages up to 3.3 V, making the

selection of the drive logic voltage very flexible.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9222 sample clock inputs

(CLK+ and CLK−) should be clocked with a differential signal.

This signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or capacitors. These pins are biased internally

and require no additional bias.

Figure 45 shows one preferred method for clocking the AD9222.

The low jitter clock source is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD9222 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD9222 and preserves the fast

rise and fall times of the signal, which are critical to low jitter

performance.

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

0.1µF

CLOCK

CLK

INPUT

OPTIONAL

100ꢀ

0.1µF

1

50ꢀ

CLK+

CMOS DRIVER

CLK

ADC

AD9222

0.1µF

CLK–

0.1µF

39kꢀ

1

50ꢀ RESISTOR IS OPTIONAL.

MIN-CIRCUITS

ADT1–1WT, 1:1Z

Figure 48. Single-Ended 1.8 V CMOS Sample Clock

0.1µF

XFMR

AD9510/AD9511/

AD9512/AD9513/

CLOCK

INPUT

CLK+

100ꢀ

ADC

AD9222

CLK–

50ꢀ

AD9514/AD9515

0.1µF

CLOCK

INPUT

CLK

OPTIONAL

100ꢀ

0.1µF

1

50ꢀ

SCHOTTKY

DIODES:

HSM2812

0.1µF

CLK+

CMOS DRIVER

CLK

ADC

AD9222

Figure 45. Transformer-Coupled Differential Clock

0.1µF

CLK–

If a low jitter clock is available, another option is to ac-couple a

differential PECL signal to the sample clock input pins as shown

in Figure 46. The AD9510/AD9511/AD9512/AD9513/AD9514/

AD9515 family of clock drivers offers excellent jitter performance.

1

50ꢀ RESISTOR IS OPTIONAL.

Figure 49. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle Considerations

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD9222 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9222. When the DCS is on, noise and distortion perfor-

mance are nearly flat for a wide range of duty cycles. However,

some applications may require the DCS function to be off. If so,

keep in mind that the dynamic range performance can be affected

when operated in this mode. See the Memory Map section for

more details on using this feature.

0.1µF

CLOCK

INPUT

CLK

PECL DRIVER

CLK

CLK+

ADC

AD9222

100ꢀ

0.1µF

CLOCK

INPUT

CLK–

1

240ꢀ

50ꢀ

1

50ꢀ RESISTORS ARE OPTIONAL.

Figure 46. Differential PECL Sample Clock

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

0.1µF

CLOCK

INPUT

CLK+

CLK

ADC

AD9222

100ꢀ

LVDS DRIVER

CLK

0.1µF

CLOCK

INPUT

CLK–

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately eight clock cycles

to allow the DLL to acquire and lock to the new rate.

1

50ꢀ

1

50ꢀ RESISTORS ARE OPTIONAL.

Figure 47. Differential LVDS Sample Clock

Rev. 0 | Page 21 of 56

AD9222

Clock Jitter Considerations

Power Dissipation and Power-Down Mode

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(f_A) due only to aperture jitter (t_J) can be calculated by

As shown in Figure 51, the power dissipated by the AD9222 is

proportional to its sample rate. The digital power dissipation

does not vary much because it is determined primarily by the

DRVDD supply and bias current of the LVDS output drivers.

SNR degradation = 20 × log 10 [1/2 × π × f_A× t_J]

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

0.800

0.750

0.700

0.650

0.600

0.550

0.500

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 50).

AVDD CURRENT

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9222.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another

type of source (by gating, dividing, or other methods), it should

be retimed by the original clock at the last step.

TOTAL POWER

DRVDD CURRENT

10

15

20

25

30

35

40

45

50

ENCODE (MSPS)

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs (visit www.analog.com).

Figure 51. Supply Current vs. f_SAMPLEfor f_IN= 10.3 MHz, AD9222- 50

130

RMS CLOCK JITTER REQUIREMENT

120

110

16 BITS

100

90

80

70

60

50

40

30

14 BITS

12 BITS

10 BITS

8 BITS

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

1

10

100

1000

ANALOG INPUT FREQUENCY (MHz)

Figure 50. Ideal SNR vs. Input Frequency and Jitter

Rev. 0 | Page 22 of 56

AD9222

By asserting the PDWN pin high, the AD9222 is placed in

power-down mode. In this state, the ADC typically dissipates

11 mW. During power-down, the LVDS output drivers are placed

in a high impedance state. The AD9222 returns to normal

operating mode when the PDWN pin is pulled low. This pin is

both 1.8 V and 3.3 V tolerant.

100 Ω termination resistor placed as close to the receiver as

possible. No far-end receiver termination and poor differential

trace routing may result in timing errors. It is recommended

that the trace length is no longer than 24 inches and that the

differential output traces are kept close together and at equal

lengths. An example of the FCO and data stream with proper

trace length and position can be found in Figure 52.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on REFT and REFB are

discharged when entering power-down mode and must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in the power-down

mode; shorter cycles result in proportionally shorter wake-up

times. With the recommended 0.1 ꢀF and 4.7 ꢀF decoupling

capacitors on REFT and REFB, it takes approximately 1 sec to

fully discharge the reference buffer decoupling capacitors and

375 ꢀs to restore full operation.

There are a number of other power-down options available

when using the SPI port interface. The user can individually

power down each channel or put the entire device into standby

mode. This allows the user to keep the internal PLL powered

when fast wake-up times (~600 ns) are required. See the

Memory Map section for more details on using these features.

5.0ns/DIV

CH1 500mV/DIV = FCO

CH2 500mV/DIV = DCO

CH3 500mV/DIV = DATA

Figure 52. LVDS Output Timing Example in ANSI Mode (Default), AD9222-50

An example of the LVDS output using the ANSI standard (default)

data eye and a time interval error (TIE) jitter histogram with

trace lengths less than 24 inches on regular FR-4 material is

shown in Figure 53. Figure 54 shows an example of when the

trace lengths exceed 24 inches on regular FR-4 material. Notice

that the TIE jitter histogram reflects the decrease of the data eye

opening as the edge deviates from the ideal position. It is up to

the user to determine if the waveforms meet the timing budget

of the design when the trace lengths exceed 24 inches. Additional

SPI options allow the user to further increase the internal ter-

mination (increasing the current) of all eight outputs in order to

drive longer trace lengths (see Figure 55). Even though this

produces sharper rise and fall times on the data edges and is less

prone to bit errors, the power dissipation of the DRVDD supply

increases when this option is used. Also notice in Figure 55 that

the histogram has improved.

Digital Outputs and Timing

The AD9222 differential outputs conform to the ANSI-644 LVDS

standard on default power-up. This can be changed to a low power,

reduced signal option similar to the IEEE 1596.3 standard using the

SDIO/ODM pin or via the SPI. This LVDS standard can further

reduce the overall power dissipation of the device by approximately

36 mW. See the SDIO/ODM Pin section or Table 15 in the

Memory Map section for more information. The LVDS driver

current is derived on-chip and sets the output current at each

output equal to a nominal 3.5 mA. A 100 Ω differential termination

resistor placed at the LVDS receiver inputs results in a nominal

350 mV swing at the receiver.

The AD9222 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs that have LVDS capability

for superior switching performance in noisy environments.

Single point-to-point net topologies are recommended with a

In cases that require increased driver strength to the DCO and

FCO outputs because of load mismatch, Register 15 allows the

user to increase the drive strength by 2×. To do this, set the

appropriate bit in Register 5. Note that this feature cannot be

used with Bit 4 and Bit 5 in Register 15. Bit 4 and Bit 5 will take

precedence over this feature. See the Memory Map section for

more details.

Rev. 0 | Page 23 of 56

AD9222

500

400

300

EYE: ALL BITS

ULS: 12071/12071

EYE: ALL BITS

ULS: 12072/12072

400

300

200

100

0

–100

–200

–300

–400

–500

–100

–200

–300

–400

–1.5ns

–1.0ns

–0.5ns

0ns

0.5ns

1.0ns

1.5ns

–1.5ns

–1.0ns

–0.5ns

0ns

0.5ns

1.0ns

1.5ns

90

80

70

60

50

40

30

20

10

80

70

60

50

40

30

20

10

0

–150ps

–100ps

–50ps

0ps

50ps

100ps

150ps

–150ps

–100ps

–50ps

0ps

50ps

100ps

150ps

Figure 55. Data Eye for LVDS Outputs in ANSI Mode with 100 Ω Termination

on and Trace Lengths Greater than 24 Inches on Standard FR-4, AD9222-50

Figure 53. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less

than 24 Inches on Standard FR-4, AD9222-50

The format of the output data is offset binary by default. An

example of the output coding format can be found in Table 8.

If it is desired to change the output data format to twos

complement, see the Memory Map section.

500

EYE: ALL BITS

ULS: 12067/12067

400

300

200

100

Table 8. Digital Output Coding

0

(VIN+) − (VIN−), Input

Digital Output Offset Binary

(D11 ... D0)

–100

–200

–300

–400

–500

Code Span = 2 V p-p (V)

ꢀ095

20ꢀ±

20ꢀꢁ

0

+1.00

1111 1111 1111

1000 0000 0000

0111 1111 1111

0000 0000 0000

0.00

−0.000ꢀ±±

−1.00

–1.5ns

–1.0ns

–0.5ns

0ns

0.5ns

1.0ns

1.5ns

Data from each ADC is serialized and provided on a separate

channel. The data rate for each serial stream is equal to 12 bits

times the sample clock rate, with a maximum of 600 Mbps

(12 bits × 50 MSPS = 600 Mbps). The lowest typical conversion

rate is 10 MSPS. However, if lower sample rates are required for

a specific application, the PLL can be set up for encode rates

lower than 10 MSPS via the SPI. This allows encode rates as low

as 5 MSPS. See the Memory Map section to enable this feature.

100

90

80

70

60

50

40

30

20

10

0

–200ps

–100ps

0ps

100ps

200ps

Figure 54. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths

Greater than 24 Inches on Standard FR-4, AD9222-50

Rev. 0 | Page 2ꢀ of 56

AD9222

Two output clocks are provided to assist in capturing data from

the AD9222. The DCO is used to clock the output data and is

equal to six times the sampling clock (CLK) rate. Data is

clocked out of the AD9222 and must be captured on the rising

and falling edges of the DCO that supports double data rate

(DDR) capturing. The frame clock out (FCO) is used to signal

the start of a new output byte and is equal to the sampling clock

rate. See the timing diagram shown in Figure 2 for more

information.

Table 9. Flex Output Test Modes

Subject

to Data

Format

Output Test

Mode Bit

Sequence

Pattern Name

Off (default)

Digital Output Word 1

Digital Output Word 2

Select

0000

N/A

0001

Midscale short

1000 0000 (±-bit)

Same

Yes

10 0000 0000 (10-bit)

1000 0000 0000 (12-bit)

10 0000 0000 0000 (1ꢀ-bit)

0010

0011

0100

+Full-scale short

−Full-scale short

Checker board

1111 1111 (±-bit)

Same

Yes

No

11 1111 1111 (10-bit)

1111 1111 1111 (12-bit)

11 1111 1111 1111 (1ꢀ-bit)

0000 0000 (±-bit)

00 0000 0000 (10-bit)

0000 0000 0000 (12-bit)

00 0000 0000 0000 (1ꢀ-bit)

1010 1010 (±-bit)

0101 0101 (±-bit)

10 1010 1010 (10-bit)

1010 1010 1010 (12-bit)

10 1010 1010 1010 (1ꢀ-bit)

N/A

01 0101 0101 (10-bit)

0101 0101 0101 (12-bit)

01 0101 0101 0101 (1ꢀ-bit)

N/A

0101

0110

0111

PN sequence long¹

PN sequence short¹

One/zero word toggle

Yes

No

1111 1111 (±-bit)

0000 0000 (±-bit)

11 1111 1111 (10-bit)

1111 1111 1111 (12-bit)

11 1111 1111 1111 (1ꢀ-bit)

00 0000 0000 (10-bit)

0000 0000 0000 (12-bit)

00 0000 0000 0000 (1ꢀ-bit)

1000

1001

User input

One/zero bit toggle

Register 0x19 to Register 0x1A

1010 1010 (±-bit)

Register 0x1B to Register 0x1C

N/A

No

10 1010 1010 (10-bit)

1010 1010 1010 (12-bit)

10 1010 1010 1010 (1ꢀ-bit)

1010

1011

1100

1× sync

0000 1111 (±-bit)

N/A

No

00 0001 1111 (10-bit)

0000 0011 1111 (12-bit)

00 0000 0111 1111 (1ꢀ-bit)

One bit high

Mixed frequency

1000 0000 (±-bit)

10 0000 0000 (10-bit)

1000 0000 0000 (12-bit)

10 0000 0000 0000 (1ꢀ-bit)

1010 0011 (±-bit)

10 0110 0011 (10-bit)

1010 0011 0011 (12-bit)

10 1000 0110 0111 (1ꢀ-bit)

¹PN, or pseudorandom number, sequence is determined by the number of bits in the shift register. The long sequence is 23 bits and the short sequence is

9 bits. How the sequence is generated and utilized is described in the ITU O.150 standard. In general, the polynomial, X23 + X1± + 1 (long) and X9 + X5 + 1

(short), defines the pseudorandom sequence.

Rev. 0 | Page 25 of 56

AD9222

When using the serial port interface (SPI), the DCO phase can

be adjusted in 60° increments relative to the data edge. This

enables the user to refine system timing margins if required.

The default DCO timing, as shown in Figure 2, is 90° relative to

the output data edge.

Table 10. Output Driver Mode Pin Settings

Resulting

Selected ODM ODM Voltage

Normal

operation

Output Standard FCO and DCO

10 kΩ to AGND ANSI-6ꢀꢀ

ANSI-6ꢀꢀ

(default)

ODM

AVDD

Low power,

reduced signal

option

Low power,

reduced

signal

An 8-, 10-, and 14-bit serial stream can also be initiated from

the SPI. This allows the user to implement and test compatibility

to lower and higher resolution systems. When changing the

resolution to an 8- or 10-bit serial stream, the data stream is

shortened. See Figure 3 for the 10-bit example. However, when

using the 14-bit option, the data stream stuffs two 0s at the end

of the normal 14-bit serial data.

option

SCLK/DTP Pin

This pin is for applications that do not require SPI mode operation.

The serial clock/digital test pattern (SCLK/DTP) pin can enable

a single digital test pattern if this pin and the CSB pin are held

high during device power-up. When the DTP is tied to AVDD,

all the ADC channel outputs shift out the following pattern:

1000 0000 0000. The FCO and DCO outputs still work as usual

while all channels shift out the repeatable test pattern. This pattern

allows the user to perform timing alignment adjustments among

the FCO, DCO, and output data. For normal operation, this pin

should be tied to AGND through a 10 kΩ resistor. This pin is

both 1.8 V and 3.3 V tolerant.

When using the SPI, all of the data outputs can also be inverted

from their nominal state. This is not to be confused with

inverting the serial stream to an LSB-first mode. In default

mode, as shown in Figure 2, the MSB is represented first in the

data output serial stream. However, this can be inverted so that

the LSB is represented first in the data output serial stream (see

Figure 4).

There are 12 digital output test pattern options available that

can be initiated through the SPI. This is a useful feature when

validating receiver capture and timing. Refer to Table 9 for the

output bit sequencing options available. Some test patterns have

two serial sequential words and can be alternated in various

ways, depending on the test pattern chosen. It should be noted

that some patterns may not adhere to the data format select

option. In addition, customer user patterns can be assigned in

the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode

options can support 8- to 14-bit word lengths in order to verify

data capture to the receiver.

Table 11. Digital Test Pattern Pin Settings

Resulting

FCO and DCO

Selected DTP DTP Voltage

Normal

operation

DTP

D+ and D−

10 kΩ to AGND Normal

Normal operation

operation

AVDD

1000 0000 0000 Normal operation

Additional and custom test patterns can also be observed when

commanded from the SPI port. Consult the Memory Map

section to choose from the different options available.

Please consult the Memory Map section for information on how

to change these additional digital output timing features through

the serial port interface or SPI.

CSB Pin

The chip select bar (CSB) pin should be tied to AVDD for

applications that do not require SPI mode operation. By tying

CSB high, all SCLK and SDIO information is ignored. This pin

is both 1.8 V and 3.3 V tolerant.

SDIO/ODM Pin

This pin is for applications that do not require SPI mode operation.

The SDIO/ODM pin can enable a low power, reduced signal option

similar to the IEEE 1596.3 reduced range link output standard if

this pin and the CSB pin are tied to AVDD during device power-

up. This option should only be used when the digital output trace

lengths are less than 2 inches from the LVDS receiver. The FCO,

DCO, and outputs function normally, but the LVDS signal swing

of all channels is reduced from 350 mV p-p to 200 mV p-p. This

output mode allows the user to further lower the power on the

DRVDD supply. For applications where this pin is not used, it

should be tied low. In this case, the device pin can be left open,

and the 30 kΩ internal pull-down resistor pulls this pin low. This

pin is only 1.8 V tolerant. If applications require this pin to be

driven from a 3.3 V logic level, insert a 1 kΩ resistor in series

with this pin to limit the current.

RBIAS Pin

To set the internal core bias current of the ADC, place a resistor

(nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The

resistor current is derived on-chip and sets the ADC’s AVDD

current to a nominal 358 mA at 50 MSPS. Therefore, it is

imperative that at least a 1% tolerance on this resistor be used to

achieve consistent performance. If SFDR performance is not as

critical as power, simply adjust the ADC core current to achieve

a lower power. Figure 56 and Figure 57 show the relationship

between the dynamic range and power as the RBIAS resistance

is changed. Nominally, a 10.0 kΩ value is used, as indicated by

the dashed line.

Rev. 0 | Page 26 of 56

AD9222

90

85

80

75

70

65

60

Internal Reference Operation

A comparator within the AD9222 detects the potential at the

SENSE pin and configures the reference. If SENSE is grounded,

the reference amplifier switch is connected to the internal

resistor divider (see Figure 58), setting VREF to 1 V.

SFDR

The REFT and REFB pins establish their input span of the ADC

core from the reference configuration. The analog input full-

scale range of the ADC equals twice the voltage at the reference

pin for either an internal or an external reference configuration.

SNR

If the reference of the AD9222 is used to drive multiple

converters to improve gain matching, the loading of the refer-

ence by the other converters must be considered. Figure 60

depicts how the internal reference voltage is affected by loading.

0

5

10

15

(kꢀ)

20

25

R

BIAS

Figure 56. SNR/SFDR vs. RBIAS, F_IN= 10.3 MHz, AD9222-50

VIN+

1.0

VIN–

REFT

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.1µF

+

ADC

CORE

0.1µF

2.2µF

REFB

0.1µF

V

REF

1µF

0.1µF

0.5V

SELECT

LOGIC

SENSE

0

5

10

15

(kꢀ)

20

25

R

BIAS

Figure 58. Internal Reference Configuration

Figure 57. IAVDD vs. RBIAS, AD9222-50

VIN+

VIN–

Voltage Reference

A stable and accurate 0.5 V voltage reference is built into the

AD9222. This is gained up by a factor of 2 internally, setting

REFT

0.1µF

REFB

+

ADC

CORE

2.2µF

V_REFto 1.0 V, which results in a full-scale differential input span

of 2 V p-p. The V_REFis set internally by default; however, the

VREF pin can be driven externally with a 1.0 V reference to

achieve more accuracy.

EXTERNAL

REFERENCE

0.1µF

V

REF

1

1µF

0.1µF

0.5V

When applying the decoupling capacitors to the VREF, REFT,

and REFB pins, use ceramic low ESR capacitors. These capacitors

should be close to the ADC pins and on the same layer of the

PCB as the AD9222. The recommended capacitor values and

configurations for the AD9222 reference pin can be found in

Figure 58.

SELECT

LOGIC

AVDD

SENSE

1

OPTIONAL.

Figure 59. External Reference Operation

Table 12. Reference Settings

Resulting

Selected

Mode

SENSE

Voltage

Resulting

VREF (V)

Differential

Span (V p-p)

External

AVDD

N/A

2 × external

reference

Reference

Internal,

2 V p-p FSR

AGND to 0.2 V

1.0

2.0

Rev. 0 | Page 2ꢁ of 56

AD9222

0.02

0

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 61 shows the typical drift characteristics of the

internal reference in 1 V mode.

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

–0.14

–0.16

–0.18

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. The external

reference is loaded with an equivalent 6 kΩ load. An internal

reference buffer generates the positive and negative full-scale

references, REFT and REFB, for the ADC core. Therefore, the

external reference must be limited to a nominal of 1.0 V.

5

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

0

–5

Figure 61. Typical V_REFDrift, AD9222-50

–10

–15

–20

–25

–30

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

CURRENT LOAD (mA)

Figure 60. V_REFAccuracy vs. Load, AD9222-50

Rev. 0 | Page 2± of 56

AD9222

SERIAL PORT INTERFACE (SPI)

CSB remains low until the communication cycle is complete.

The AD9222 serial port interface allows the user to configure

the converter for specific functions or operations through a

structured register space provided inside the ADC. This gives

the user added flexibility and customization depending on the

application. Addresses are accessed via the serial port and can

be written to or read from via the port. Memory is organized

into bytes that can be further divided down into fields, as doc-

umented in the Memory Map section. Detailed operational

information can be found in the Analog Devices, Inc., user

manual Interfacing to High Speed ADCs via SPI.

However, if connected to a slow device, CSB can be brought

high between bytes, allowing older microcontrollers enough

time to transfer data into shift registers. CSB can be stalled

when transferring one, two, or three bytes of data. When W0

and W1 are set to 11, the device enters streaming mode and

continues to process data, either reading or writing, until the

CSB is taken high to end the communication cycle. This allows

complete memory transfers without having to provide additional

instructions. Regardless of the mode, if CSB is taken high in the

middle of any byte transfer, the SPI state machine is reset and

the device waits for a new instruction.

There are three pins that define the serial port interface, or SPI,

to this particular ADC. They are the SCLK, SDIO, and CSB

pins. The SCLK (serial clock) is used to synchronize the read

and write data presented to the ADC. The SDIO (serial data

input/output) is a dual-purpose pin that allows data to be sent

to and read from the internal ADC memory map registers. The

CSB (chip select bar) is an active low control that enables or

disables the read and write cycles (see Table 13).

In addition to the operation modes, the SPI port can be

configured to operate in different manners. For applications

that do not require a control port, the CSB line can be tied and

held high. This places the remainder of the SPI pins in their

secondary mode as defined in the Serial Port Interface (SPI)

section. CSB can also be tied low to enable 2-wire mode. When

CSB is tied low, SCLK and SDIO are the only pins required for

communication. Although the device is synchronized during

power-up, caution must be exercised when using this mode to

ensure that the serial port remains synchronized with the CSB

line. When operating in 2-wire mode, it is recommended to use

a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB

line, streaming mode can be entered but not exited.

Table 13. Serial Port Pins

Function

SCLK

Serial Clock. The serial shift clock in. SCLK is used to

synchronize serial interface reads and writes.

SDIO

CSB

Serial Data Input/Output. A dual-purpose pin. The

typical role for this pin is an input or output, depending

on the instruction sent and the relative position in the

timing frame.

Chip Select Bar (Active Low). This control gates the read

and write cycles.

In addition to word length, the instruction phase determines if

the serial frame is a read or write operation, allowing the serial

port to be used to both program the chip and read the contents

of the on-chip memory. If the instruction is a readback operation,

performing a readback causes the serial data input/output (SDIO)

pin to change direction from an input to an output at the

appropriate point in the serial frame.

The falling edge of the CSB in conjunction with the rising edge

of the SCLK determines the start of the framing sequence. During

an instruction phase, a 16-bit instruction is transmitted, followed

by one or more data bytes, which is determined by Bit Fields

W0 and W1. An example of the serial timing and its definitions

can be found in Figure 63 and Table 14. In normal operation,

CSB is used to signal to the device that SPI commands are to be

received and processed. When CSB is brought low, the device

processes SCLK and SDIO to process instructions. Normally,

Data can be sent in MSB- or LSB-first mode. MSB-first mode

is the default at power-up and can be changed by adjusting the

configuration register. For more information about this and

other features, see the user manual Interfacing to High Speed

ADCs via SPI.

Rev. 0 | Page 29 of 56

AD9222

This interface is flexible enough to be controlled by either serial

PROMS or PIC mirocontrollers. This provides the user an

alternative method, other than a full SPI controller, to program

the ADC (see the AN-812 Application Note).

HARDWARE INTERFACE

The pins described in Table 13 compose the physical interface

between the user’s programming device and the serial port of

the AD9222. The SCLK and CSB pins function as inputs when

using the SPI interface. The SDIO pin is bidirectional, functioning

as an input during write phases and as an output during readback.

If the user chooses not to use the SPI interface, these pins serve

a dual function and are associated with secondary functions

when the CSB is strapped to AVDD during device power-up.

See the Theory of Operation section for details on which pin-

strappable functions are supported on the SPI pins.

If multiple SDIO pins share a common connection, care should

be taken to ensure that proper V_OHlevels are met. Assuming the

same load as the AD9222, Figure 62 shows the number of SDIO

pins that can be connected together and the resulting V_OHlevel.

1.800

1.795

1.790

1.785

1.780

1.775

1.770

1.765

1.760

1.755

1.750

1.745

1.740

1.735

1.730

1.725

1.720

1.715

0

10

20

30

40

50

60

70

80

90

100

NUMBER OF SDIO PINS CONNECTED TOGETHER

Figure 62. SDIO Pin Loading

Rev. 0 | Page 30 of 56

AD9222

t_DS

t_HI

t_CLK

t_H

t_S

t_DH

t_LO

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

Figure 63. Serial Timing Details

Table 14. Serial Timing Definitions

Parameter

Timing (minimum, ns)

Description

t_DS

5

2

ꢀ0

5

Set-up time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the clock

t_DH

t_CLK

t_S

Set-up time between CSB and SCLK

t_H

2

Hold time between CSB and SCLK

t_HI

t_LO

t_{EN_SDIO}

16

1

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge (not shown in Figure 63)

t_{DIS_SDIO}

5

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge (not shown in Figure 63)

Rev. 0 | Page 31 of 56

AD9222

MEMORY MAP

READING THE MEMORY MAP TABLE

RESERVED LOCATIONS

Undefined memory locations should not be written to except

when writing the default values suggested in this data sheet.

Addresses that have values marked as 0 should be considered

reserved and have a 0 written into their registers during power-up.

Each row in the memory map table has eight address locations.

The memory map is roughly divided into three sections: chip

configuration register map (Address 0x00 to Address 0x02), device

index and transfer register map (Address 0x05 and Address 0xFF),

and program register map (Address 0x08 to Address 0x25).

DEFAULT VALUES

The left-hand column of the memory map indicates the register

address number in hexadecimal. The default value of this address is

shown in hexadecimal in the right-hand column. The Bit 7 (MSB)

column is the start of the default hexadecimal value given. For

example, Hexadecimal Address 0x09, Clock, has a hexadecimal

default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0,

Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001

in binary. This setting is the default for the duty cycle stabilizer in

the on condition. By writing a 0 to Bit 6 at this address, the duty

cycle stabilizer turns off. For more information on this and other

functions, consult the user manual Interfacing to High Speed

ADCs via SPI.

Coming out of reset, critical registers are preloaded with default

values. These values are indicated in Table 15, where an X refers

to an undefined feature.

LOGIC LEVELS

An explanation of various registers follows: “Bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly, “clear a bit” is synonymous with “bit is set to

Logic 0” or “writing Logic 0 for the bit.”

Rev. 0 | Page 32 of 56

AD9222

Table 15. Memory Map Register

Default

Value

(Hex)

Addr.

(Hex)

Bit 7

Bit 0

(LSB)

Default Notes/

Comments

Parameter Name (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Chip Configuration Registers

00

chip_port_config

0

LSB first

1 = on

Soft

reset

1

Soft

reset

LSB first

1 = on

0

0x1±

The nibbles

should be

0 = off

(default)

1 = on

0 = off

(default)

1 = on

0 = off

(default)

0 = off

(default)

mirrored so that

LSB- or MSB-first

mode registers

correctly

regardless of

shift mode.

01

02

chip_id

±-bit Chip ID Bits ꢁ:0

(AD9222 = 0x0ꢁ), (default)

Read

only

Default is unique

chip ID, different

for each device.

This is a read-

only register.

chip_grade

X

Child ID 6:ꢀ

X

Read

only

Child ID used to

differentiate

graded devices.

(identify device variants of Chip ID)

011 = 50 MSPS

001 = ꢀ0 MSPS

Device Index and Transfer Registers

0ꢀ

05

FF

device_index_2

device_index_1

device_update

X

Data

Channel

H

1 = on

(default)

0 = off

Data

Channel

G

Data

Channel

F

Data

Channel

E

0x0F

0x00

Bits are set to

determine which

on-chip device

receives the next

write command.

1 = on

(default) (default) (default)

0 = off

Clock

Channel

DCO

1 = on

0 = off

Clock

Channel

FCO

1 = on

0 = off

Data

Channel

D

Data

Channel

C

Data

Channel

B

Data

Channel

A

Bits are set to

determine which

on-chip device

receives the next

write command.

1 = on

(default) (default) (default) (default)

(default) (default) 0 = off

0 = off

X

SW

Synchronously

transfers data

from the master

shift register to

the slave.

transfer

1 = on

0 = off

(default)

ADC Functions

0±

modes

X

Internal power-down mode

000 = chip run (default)

001 = full power-down

010 = standby

0x00

0x01

Determines

various generic

modes of chip

operation.

011 = reset

09

clock

X

Duty

Turns the

cycle

internal duty

cycle stabilizer

on and off.

stabilizer

1 = on

(default)

0 = off

0D

test_io

User test mode

00 = off (default)

Reset PN Reset

long gen PN short Digital Outputs and Timing section

Output test mode—see Table 9 in the

0x00

When set, the

test data is

01 = on, single alternate 1 = on

gen

1 = on

0000 = off (default)

0001 = midscale short

0010 = +FS short

placed on the

output pins in

place of normal

data.

10 = on, single once

11 = on, alternate once

0 = off

(default) 0 = off

(default) 0011 = −FS short

0100 = checker board output

0101 = PN 23 sequence

0110 = PN 9

0111 = one/zero word toggle

1000 = user input

1001 = one/zero bit toggle

1010 = 1× sync

1011 = one bit high

1100 = mixed bit frequency

(format determined by output_mode)

Rev. 0 | Page 33 of 56

AD9222

Default

Value

(Hex)

Addr.

(Hex)

Bit 7

Parameter Name (MSB)

output_mode X

Bit 0

(LSB)

Default Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

1ꢀ

0 = LVDS

ANSI

(default)

1 = LVDS

low

X

Output

invert

1 = on

0 = off

(default)

00 = offset binary

(default)

0x00

Configures the

outputs and the

format of the

data.

01 = twos

complement

power,

(IEEE

1596.3

similar)

15

output_adjust

X

Output driver

termination

00 = none (default)

01 = 200 Ω

10 = 100 Ω

11 = 100 Ω

X

DCO and 0x00

FCO

2× Drive

Strength

1 = on

Determines

LVDS or other

output properties.

Primarily func-

tions to set the

LVDS span and

common-mode

levels in place of

an external

0 = off

(default)

resistor.

16

output_phase

X

0011 = output clock phase adjust

(0000 through 1010)

0x03

On devices that

utilize global

clock divide,

determines

which phase of

the divider

output is used to

supply the

output clock.

Internal latching

is unaffected.

(Default: 1±0° relative to DATA edge)

0000 = 0° relative to DATA edge

0001 = 60° relative to DATA edge

0010 = 120° relative to DATA edge

0011 = 1±0° relative to DATA edge

0100 = 2ꢀ0° relative to DATA edge

0101 = 300° relative to DATA edge

0110 = 360° relative to DATA edge

0111 = ꢀ20° relative to DATA edge

1000 = ꢀ±0° relative to DATA edge

1001 = 5ꢀ0° relative to DATA edge

1010 = 600° relative to DATA edge

1011 to 1111 = 660° relative to DATA edge

19

1A

1B

1C

21

user_patt1_lsb

user_patt1_msb

user_patt2_lsb

user_patt2_msb

serial_control

Bꢁ

B6

B1ꢀ

B6

B5

B13

B5

Bꢀ

B12

Bꢀ

B3

B2

B1

B9

B1

B9

B0

B±

B0

B±

0x00

User-defined

pattern, 1 LSB.

B15

Bꢁ

B11

B3

B10

B2

User-defined

pattern, 1 MSB.

User-defined

pattern, 2 LSB.

B15

B1ꢀ

X

B13

X

B12

X

B11

B10

User-defined

pattern, 2 MSB.

LSB first

1 = on

0 = off

<10

MSPS,

low

encode

rate

000 = 12 bits (default, normal bit

stream)

001 = ± bits

010 = 10 bits

011 = 12 bits

Serial stream

control. Default

causes MSB first

and the native

bit stream

(default)

mode

1 = on

0 = off

(default)

100 = 1ꢀ bits

(global).

22

serial_ch_stat

X

Channel

output

reset

Channel

power-

down

0x00

Used to power

down individual

sections of a

1 = on

0 = off

1 = on

0 = off

converter (local).

(default) (default)

Rev. 0 | Page 3ꢀ of 56

AD9222

Power and Ground Recommendations

Exposed Paddle Thermal Heat Slug Recommendations

When connecting power to the AD9222, it is recommended

that two separate 1.8 V supplies be used: one for analog (AVDD)

and one for digital (DRVDD). If only one supply is available, it

should be routed to the AVDD first and then tapped off and

isolated with a ferrite bead or a filter choke preceded by

decoupling capacitors for the DRVDD. The user can employ

several different decoupling capacitors to cover both high and

low frequencies. These should be located close to the point of

entry at the PC board level and close to the parts with minimal

trace length.

It is required that the exposed paddle on the underside of the

ADC is connected to analog ground (AGND) to achieve the

best electrical and thermal performance of the AD9222. An

exposed continuous copper plane on the PCB should mate to

the AD9222 exposed paddle, Pin 0. The copper plane should

have several vias to achieve the lowest possible resistive thermal

path for heat dissipation to flow through the bottom of the PCB.

These vias should be solder filled or plugged.

To maximize the coverage and adhesion between the ADC and

PCB, partition the continuous copper plane by overlaying a

silkscreen on the PCB into several uniform sections. This provides

several tie points between the two during the reflow process.

Using one continuous plane with no partitions only guarantees

one tie point between the ADC and PCB. See Figure 64 for a

PCB layout example. For detailed information on packaging

and the PCB layout of chip scale packages, see the AN-772

Application Note, A Design and Manufacturing Guide for the

Lead Frame Chip Scale Package (LFCSP), at www.analog.com.

A single PC board ground plane should be sufficient when

using the AD9222. With proper decoupling and smart parti-

tioning of the PC board’s analog, digital, and clock sections,

optimum performance is easily achieved.

SILKSCREEN PARTITION

PIN 1 INDICATOR

Figure 64. Typical PCB Layout

Rev. 0 | Page 35 of 56

AD9222

EVALUATION BOARD

The AD9222 evaluation board provides all of the support cir-

cuitry required to operate the ADC in its various modes and

configurations. The converter can be driven differentially through a

transformer (default) or through the AD8334 driver. The ADC

can also be driven in a single-ended fashion. Separate power pins

are provided to isolate the DUT from the AD8334 drive circuitry.

Each input configuration can be selected by proper connection

of various jumpers (see Figure 67 to Figure 71). Figure 65 shows

the typical bench characterization setup used to evaluate the ac

performance of the AD9222. It is critical that the signal sources

used for the analog input and clock have very low phase noise

(<1 ps rms jitter) to realize the optimum performance of the

converter. Proper filtering of the analog input signal to remove

harmonics and lower the integrated or broadband noise at the

input is also necessary to achieve the specified noise performance.

capability for AVDD_DUT and DRVDD_DUT; however, it is

recommended that separate supplies be used for both analog

and digital. To operate the evaluation board using the VGA

option, a separate 5.0 V analog supply is needed. The 5.0 V

supply, or AVDD_5 V, should have a 1 A current capability. To

operate the evaluation board using the SPI and alternate clock

options, a separate 3.3 V analog supply is needed in addition to

the other supplies. The 3.3 V supply, or AVDD_3.3 V, should

have a 1 A current capability as well.

INPUT SIGNALS

When connecting the clock and analog source, use clean signal

generators with low phase noise, such as Rohde & Schwarz SMHU

or HP8644 signal generators or the equivalent. Use a 1 m, shielded,

RG-58, 50 Ω coaxial cable for making connections to the evalu-

ation board. Enter the desired frequency and amplitude from the

ADC specifications tables. Typically, most Analog Devices

evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave

input for the clock. When connecting the analog input source, it

is recommended to use a multipole, narrow-band, band-pass

filter with 50 Ω terminations. Analog Devices uses TTE, Allen

Avionics, and K&L types of band-pass filters. The filter should

be connected directly to the evaluation board if possible.

See Figure 67 to Figure 77 for the complete schematics and

layout diagrams that demonstrate the routing and grounding

techniques that should be applied at the system level.

POWER SUPPLIES

This evaluation board comes with a wall-mountable switching

power supply that provides a 6 V, 2 A maximum output. Simply

connect the supply to the rated 100 V ac to 240 V ac wall outlet

at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter

jack that connects to the PCB at P701. Once on the PC board,

the 6 V supply is fused and conditioned before connecting to

three low dropout linear regulators that supply the proper bias

to each of the various sections on the board.

OUTPUT SIGNALS

The default setup uses the HSC-ADC-FPGA high speed

deserialization board to deserialize the digital output data and

convert it to parallel CMOS. These two channels interface

directly with the Analog Devices standard dual-channel FIFO

data capture board (HSC-ADC-EVALA-DC). Two of the eight

channels can then be evaluated at the same time. For more

information on channel settings on these boards and their

optional settings, visit www.analog.com/FIFO.

When operating the evaluation board in a nondefault condition,

L701 to L704 can be removed to disconnect the switching

power supply. This enables the user to bias each section of the

board individually. Use P702 to connect a different supply for

each section. At least one 1.8 V supply is needed with a 1 A current

WALL OUTLET

100V TO 240V AC

47Hz TO 63Hz

6V DC

2A MAX

5.0V

1.8V

3.3V

1.5V

3.3V

–

+

–

+

–

+

–

+

–

+

–

+

–

+

SWITCHING

POWER

SUPPLY

PC

RUNNING

ADC

ANALYZER

AND SPI

USER

ROHDE & SCHWARZ,

HSC-ADC-FPGA

HIGH SPEED

DESERIALIZATION

HSC-ADC-EVALA-DC

FIFO DATA

SMHU,

2V p-p SIGNAL

SYNTHESIZER

BAND-PASS

FILTER

XFMR

INPUT

CAPTURE

BOARD

AD9222

EVALUATION BOARD

BOARD

CHA TO CHH

12-BIT

SOFTWARE

2-CH

USB

CONNECTION

ROHDE & SCHWARZ,

SMHU,

12-BIT

PARALLEL

CMOS

CLK

SERIAL

LVDS

2V p-p SIGNAL

SYNTHESIZER

SPI

Figure 65. Evaluation Board Connection

Rev. 0 | Page 36 of 56

AD9222

50 Ω terminated and ac-coupled to handle single-ended

DEFAULT OPERATION AND JUMPER SELECTION

SETTINGS

sine wave types of inputs. The transformer converts the

single-ended input to a differential signal that is clipped

before entering the ADC clock inputs.

The following is a list of the default and optional settings or

modes allowed on the AD9222 Rev. A evaluation board.

A differential LVPECL clock can also be used to clock the

ADC input using the AD9515 (U401). Simply populate

R406 and R407 with 0 Ω resistors and remove R215 and

R216 to disconnect the default clock path inputs. In addition,

populate C205 and C206 with a 0.1 μF capacitor and remove

C409 and C410 to disconnect the default cloth path outputs.

The AD9515 has many pin-strappable options that are set

to a default working condition. Consult the AD9515 data

sheet for more information about these and other options.

•

POWER: Connect the switching power supply that is

supplied in the evaluation kit between a rated 100 V ac

to 240 V ac wall outlet at 47 Hz to 63 Hz and P701.

•

AIN: The evaluation board is set up for a transformer-

coupled analog input with optimum 50 Ω impedance

matching out to 150 MHz (see Figure 66). For more

bandwidth response, the differential capacitor across the

analog inputs can be changed or removed. The common

mode of the analog inputs is developed from the center

tap of the transformer or AVDD_DUT/2.

If using an oscillator, two oscillator footprint options are

also available (OSC401) to check the ADC performance.

J401 gives the user flexibility in using the enable pin, which

is common on most oscillators.

0

–2

–3dB CUTOFF = 150MHz

–4

–6

•

PDWN: To enable the power-down feature, simply short

J301 to the on position (AVDD) on the PDWN pin.

SCLK/DTP: To enable a digital test pattern on the digital

outputs of the ADC, use J304. If J304 is tied to AVDD during

device power-up, Test Pattern 1000 0000 0000 will be enabled.

See the SCLK/DTP Pin section for details.

–8

–10

–12

–14

–16

–18

•

SDIO/ODM: To enable the low power, reduced signal option

similar to the IEEE 1595.3 reduced range link LVDS output

standard, use J303. If J303 is tied to AVDD during device

power-up, it enables the LVDS outputs in a low power,

reduced signal option from the default ANSI standard.

This option changes the signal swing from 350 mV p-p to

200 mV p-p, which reduces the power of the DRVDD supply.

See the SDIO/ODM Pin section for more details.

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

Figure 66. Evaluation Board Full Power Bandwidth, AD9222-50

•

VREF: VREF is set to 1.0 V by tying the SENSE pin to

ground, R317. This causes the ADC to operate in 2.0 V p-p

full-scale range. A separate external reference option using

the ADR510 or ADR520 is also included on the evaluation

board. Simply populate R312 and R313 and remove C307.

Proper use of the VREF options is noted in the Voltage

Reference section.

•

CSB: To enable the SPI information on the SDIO and

SCLK pins that is to be processed, simply tie J302 low in

the always enable mode. To ignore the SDIO and SCLK

information, tie J302 to AVDD.

Non-SPI Mode: For users who wish to operate the DUT

without using SPI, simply remove Jumpers J302, J303, and

J304. This disconnects the CSB, SCLK/DTP, and SDIO/OMD

pins from the control bus, allowing the DUT to operate in

its simplest mode. Each of these pins has internal termination

and will float to its respective level.

•

RBIAS: RBIAS has a default setting of 10 kΩ (R301) to

ground and is used to set the ADC core bias current. To

further lower the core power (excluding the LVDS driver

supply) simply change the resistor setting. However,

performance of the ADC will degrade depending on the

resistor chosen. See RBIAS section for more information.

•

D+, D−: If an alternative data capture method to the setup

described in Figure 67 is used, optional receiver terminations,

R318, R320 to R328, can be installed next to the high speed

backplane connector.

CLOCK: The default clock input circuitry is derived from a

simple transformer-coupled circuit using a high bandwidth

1:1 impedance ratio transformer (T401) that adds a very

low amount of jitter to the clock path. The clock input is

Rev. 0 | Page 3ꢁ of 56

AD9222

•

Populate R101, R114, R127, R140, R201, R217, R233 and

R251 with 0 Ω resistors in the analog input path.

ALTERNATIVE ANALOG INPUT DRIVE

CONFIGURATION

The following is a brief description of the alternative analog

input drive configuration using the AD8334 dual VGA. If this

particular drive option is in use, some components may need to

be populated, in which case all the necessary components are

listed in Table 16. For more details on the AD8334 dual VGA,

including how it works and its optional pin settings, consult the

AD8334 data sheet.

Populate R106, R107, R119, R120, R132, R133, R144, R145,

R206, R207, R223, R224, R239, R240, R257 and R258 with

10 kΩ resistors to provide an input common-mode level to

the analog input.

•

Populate R105, R113, R118, R124, R131, R137, R151, and

R160, R205, R213, R221, R222, R255, R256 with 0 Ω resistors

in the analog input path.

To configure the analog input to drive the VGA instead of the

default transformer option, the following components need to

be removed and/or changed.

Currently, L505 to L520 and L605 to L620 are populated with 0 Ω

resistors to allow signal connection. This area allows the user to

design a filter if additional requirements are necessary.

•

Remove R102, R115, R128, R141, R202, R218, R234, R252,

T101, T102, T103, T104, T201, T202, T203, and T204 in

the default analog input path.

Rev. 0 | Page 3± of 56

AD9222

7 2 0 7 - 0 5 9 6

Figure 67. Evaluation Board Schematic, DUT Analog Inputs

Rev. 0 | Page 39 of 56

AD9222

7 3 0 7 - 0 5 9 6

Figure 68. Evaluation Board Schematic, DUT Analog Inputs (Continued)

Rev. 0 | Page ꢀ0 of 56

AD9222

7 4 0 7 - 9 6 0 5

2

R307

10kΩ

R306

100kΩ

AVDD_DUT

R302

DNP

R305

100kΩ

CW

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

0

VIN+C

VIN−C

AVDD

VIN−D

VIN+D

RBIAS

SENSE

VREF

REFB

REFT

AVDD

VIN+E

VIN−E

AVDD

VIN−F

VIN+F

SLUG

VIN_C

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

CHB

D+B

D−B

CHB

CHC

AVDD_DUT

VIN_D

D+C

D−C

CHC

CHD

GND

R301

10kΩ

VIN_D

D+D

D−D

CHD

FCO

VSENSE_DUT

VREF_DUT

FCO+

FCO−

DCO+

DCO−

D+E

FCO

DCO

AVDD_DUT

VIN_E

CHE

D−E

VIN_E

D+F

CHF

AVDD_DUT

D−F

CHF

CHG

VIN_F

D+G

D−G

CHG

Figure 69. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface

Rev. 0 | Page ꢀ1 of 56

AD9222

5

0 - 7 6 7 0 5 9

25

16

15

14

13

12

11

10

9

S0

S1

S2

S3

1

2

33

31

1

S4

3

S5

GND

VS

S6

S7

S8

8

S9

32

7

RSET

S10

VREF

6

Figure 70. Evaluation Board Schematic, Clock Circuitry

Rev. 0 | Page ꢀ2 of 56

AD9222

7 6 0 - 6 7 5 9

R524

10kΩ

R523

10kΩ

R513

187Ω

C512

10µF

C511

0.1µF

C533

10µF

C534

0.1µF

C535

10µF

C536

0.1µF

C510

10µF

C509

0.1µF

R512

10kΩ

R511

10kΩ

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VCM2

VCM1

EN34

NC

VCM3

VCM4

HILO

R504

10kΩ

R505

10kΩ

AVDD_5V

EN12

CLMP12

GAIN12

VPS1

VIN1

CLMP34

GAIN34

VPS4

VG34

VG12

AVDD_5V

VIN4

VIP1

VIP4

LOP1

LON1

COM1X

LMD1

INH1

LOP4

LON4

COM4X

LMD4

INH4

R509

274Ω

C505

0.1µF

COM1

COM2

COM4

COM3

C527

0.018µF

C526

22pF

L504

120nH

0.1µF

C525

R503

274Ω

R508

274Ω

R507

274Ω

C502

0.018µF

C521

0.018µF

C515

0.018µF

C503

22pF

L501

120nH

C520

22pF

C514

22pF

0.1µF

C501

L503

120nH

L502

120nH

0.1µF

C519

0.1µF

C513

AVDD_5V

CW

GND

VG34

VG12

Variable Gain Circuit

(0−1.0V DC)

Variable Gain Circuit

(0−1.0V DC)

VG34

VG12

External

Variable Gain Drive

External

Variable Gain Drive

Figure 71. Evaluation Board Schematic, Optional DUT Analog Input Drive

Rev. 0 | Page ꢀ3 of 56

AD9222

7 7 0 7 - 9 6 0 5

R613

187Ω

C612

10µF

C611

0.1µF

C633

10µF

C634

0.1µF

C635

10µF

C636

0.1µF

C610

10µF

C609

0.1µF

VCM2

NC

VCM3

VCM4

HILO

49

50

51

52

53

54

55

56

57

58

59

60

61

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VCM1

EN34

EN12

10kΩ

R604

R612

10kΩ

R611

10kΩ

R605

10kΩ

AVDD_5V

CLMP12

GAIN12

VPS1

CLMP34

GAIN34

VPS4

VG56

VG78

AVDD_5V

VIN1

VIN4

VIP1

VIP4

LOP1

LOP4

LON1

COM1X

LMD1

INH1

LON4

COM4X

LMD4

INH4

R609

274Ω

C605

0.1µF

62

63

COM1

COM2

COM4

COM3

64

C627

0.018µF

C626

22pF

L604

120nH

0.1µF

C625

R603

274Ω

R608

274Ω

R607

274Ω

C602

0.018µF

C621

0.018µF

C615

0.018µF

C603

22pF

L601

120nH

C620

22pF

C614

22pF

0.1µF

C601

L603

120nH

L602

120nH

0.1µF

C619

0.1µF

C613

AVDD_5V

CW

GND

VG78

VG56

Variable Gain Circuit

(0−1.0V DC)

Variable Gain Circuit

(0−1.0V DC)

VG78

VG56

External

Variable Gain Drive

External

Variable Gain Drive

Figure 72. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued)

Rev. 0 | Page ꢀꢀ of 56

AD9222

7 8 0 - 6 7 5 9

CR702

GREEN

C702

0.1µF

C703

0.1µF

GND

1

R709

0Ω

SDO_CHA

SDI_CHA

R708

R707

R706

0Ω

SCLK_CHA

CSB1_CHA

PICVCC

1

3

5

7

9

2

4

PICVCC

GP1

GP0

6

GP0

MCLR/GP3

8

MCLR/GP3

10

GND

CR701

2

OPTIONAL GREEN

Figure 73. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry

Rev. 0 | Page ꢀ5 of 56

AD9222

Figure 74. Evaluation Board Layout, Primary Side

Rev. 0 | Page ꢀ6 of 56

AD9222

Figure 75. Evaluation Board Layout, Ground Plane

Rev. 0 | Page ꢀꢁ of 56

AD9222

Figure 76. Evaluation Board Layout, Power Plane

Rev. 0 | Page ꢀ± of 56

AD9222

Figure 77. Evaluation Board Layout, Secondary Side (Mirrored Image)

Rev. 0 | Page ꢀ9 of 56

AD9222

Table 16. Evaluation Board Bill of Materials (BOM)¹

Qnty.

per

Item Board REFDES

Device

Pkg.

PCB

ꢀ02

Value

Mfg.

Mfg. Part Number

1

2

1

11±

AD9222-50EBZ

PCB

C101, C102, C10ꢁ, Capacitor

C10±, C109, C11ꢀ,

C115, C116, C121,

C122, C123, C12±,

C201, C202, C20ꢁ,

C20±, C209, C21ꢀ,

C215, C216, C221,

C222, C223, C22±,

C301, C302, C30ꢀ,

C305, C306, Cꢀ01,

Cꢀ02, Cꢀ03, Cꢀ09,

Cꢀ10, Cꢀ11, Cꢀ12,

Cꢀ13, Cꢀ1ꢀ, Cꢀ15,

Cꢀ16, Cꢀ1ꢁ, Cꢀ1±,

C501, C50ꢀ, C505,

C506, C50±, C509,

C511, C513, C51±,

C519, C522, C523,

C52ꢀ, C525, C52±,

C529, C530, C532,

C53ꢀ, C536, C53ꢁ,

C53±, C601, C60ꢀ,

C605, C606, C60±,

C609, C611, C613,

C616, C61ꢁ, C61±,

C619, C622, C623,

C62ꢀ, C625, C62±,

C629, C630, C632,

C63ꢀ, C636, Cꢁ01,

Cꢁ02, Cꢁ03, Cꢁ06,

Cꢁ0±, Cꢁ10, Cꢁ12,

Cꢁ23, Cꢁ2ꢀ, Cꢁ25,

Cꢁ26, Cꢁ2ꢁ, Cꢁ30,

Cꢁ31, Cꢁ32, Cꢁ33,

Cꢁ3ꢀ, Cꢁ35, Cꢁꢀ0,

Cꢁꢀ1, Cꢁꢀ2, Cꢁꢀ3,

Cꢁꢀꢀ, Cꢁꢀ5, Cꢁꢀ6,

Cꢁꢀꢁ, Cꢁꢀ±, Cꢁꢀ9,

Cꢁ50, Cꢁ51, Cꢁ52,

Cꢁ53

0.1 μF, ceramic, X5R,

10 V, 10% tol

Murata

GRM155Rꢁ1C10ꢀKA±±D

3

ꢀ

±

C10ꢀ, C111, C11±, Capacitor

C125, C20ꢀ, C211,

C21±, C225

C510, C512, C533, Capacitor

C535, C610, C612,

ꢀ02

±05

2.2 pF, ceramic, COG,

0.25 pF tol, 50 V

Murata

GRM1555C1H2R20CZ01D

GRM219R60J106KE19D

10 μF, 6.3 V ±10%

ceramic, X5R

C633, C635

5

6

ꢁ

1

ꢀ

±

C303

Capacitor

603

ꢀ02

ꢀ.ꢁ μF, ceramic, X5R,

6.3 V, 10% tol

1000 pF, ceramic, XꢁR,

25 V, 10% tol

0.01± μF, ceramic, XꢁR,

16 V, 10% tol

Murata

AVX

GRM1±±R60Jꢀꢁ5KE19D

GRM155Rꢁ1H102KA01D

0ꢀ02YC1±3KAT2A

C50ꢁ, C531, C60ꢁ, Capacitor

C631

C502, C515, C521, Capacitor

C52ꢁ, C602, C615,

C621, C62ꢁ

Rev. 0 | Page 50 of 56

AD9222

Qnty.

per

Item Board REFDES

Device

Pkg.

Value

Mfg.

Mfg. Part Number

±

C503, C51ꢀ, C520, Capacitor

C526, C603, C61ꢀ,

ꢀ02

22 pF, ceramic, NPO,

5% tol, 50 V

Murata

GRM1555C1H220JZ01D

C620, C626

9

1

9

Cꢁ0ꢀ

Capacitor

1206

603

10 μF, tantalum,

16 V, 20% tol

1 μF, ceramic, X5R,

6.3 V, 10% tol

Rohm

TCA1C106M±R

10

C30ꢁ, Cꢁ1ꢀ, Cꢁ15, Capacitor

Cꢁ16, Cꢁ1ꢁ, Cꢁ19,

Murata

GRM1±±R61C105KA93D

Cꢁ20, Cꢁ21, Cꢁ22

11

16

C5ꢀ0, C5ꢀ1, C5ꢀꢀ, Capacitor

C5ꢀ5, C5ꢀ±, C5ꢀ9,

C552, C553, C6ꢀ0,

C6ꢀ1, C6ꢀꢀ, C6ꢀ5,

C6ꢀ±, C6ꢀ9, C652,

C653

±05

0.1 μF, ceramic, XꢁR,

50 V, 10% tol

Murata

GRM21BRꢁ1H10ꢀKA01L

12

13

ꢀ

1

Cꢁ05, Cꢁ0ꢁ, Cꢁ09, Capacitor

Cꢁ11

603

10 μF, ceramic, X5R,

6.3 V, 20% tol

30 V, 20 mA, dual

Schottky

GRM1±±R60J106MEꢀꢁD

HSMS-2±12-TR1G

CRꢀ01

Diode

SOT-23

603

Agilent

Technologies

Panasonic

Micro

1ꢀ

15

2

1

CRꢁ01, CRꢁ02

Dꢁ02

LED

Diode

Green, ꢀV, 5 m candela

LNJ31ꢀG±TRA

SK33-TP

DO-21ꢀAB 3 A, 30 V, SMC

Commercial Co.

16

1ꢁ

1±

19

1

Dꢁ01

Diode

DO-21ꢀAA 5 A, 50 V, SMC

Micro

Commercial Co.

Tyco/Raychem

Murata

S2A-TP

1

Fꢁ01

Fuse

1210

2020

603

6.0 V, 2.2 A trip-current

resettable fuse

NANOSMDC110F-2

DLW5BSN191SQ2L

BLM1±BA100SN1D

1

FERꢁ01

Choke coil

Ferrite bead

10 μH, 5 A, 50 V, 190 Ω

@ 100 MHz

10 Ω, test frequency

100 MHz, 25% tol,

500 mA

2ꢀ

FB101, FB102,

FB103, FB10ꢀ,

FB105, FB106,

FB10ꢁ, FB10±,

FB109, FB110,

FB111, FB112,

FB201, FB202,

FB203, FB20ꢀ,

FB205, FB206,

FB20ꢁ, FB20±,

FB209, FB210,

FB211, FB212

Murata

20

21

23

ꢀ

6

1

JP501, JP502,

JP601, JP602

J301, J302, J303,

J30ꢀ, Jꢀ01, Jꢁ01

Connector

2-pin

3-pin

10-pin

100 mil header jumper,

2-pin

100 mil header jumper,

3-pin

100 mil header, male,

2 × 5 double row

straight

Samtec

TSW-102-0ꢁ-G-S

TSW-103-0ꢁ-G-S

TSW-105-0±-G-D

Jꢁ02

2ꢀ

25

±

Lꢁ01, Lꢁ02, Lꢁ03,

Lꢁ0ꢀ, Lꢁ05, Lꢁ06,

Lꢁ0ꢁ, Lꢁ0±

L501, L502, L503,

L50ꢀ, L601, L602,

L603, L60ꢀ

Ferrite bead

Inductor

1210

ꢀ02

10 μH, bead core 3.2 ×

2.5 × 1.6 SMD, 2 A

Murata

BLM31PG500SN1L

LQG15HNR12J02D

120 nH, test freq

100 MHz, 5% tol,

150 mA

Rev. 0 | Page 51 of 56

AD9222

Qnty.

per

Item Board REFDES

Device

Pkg.

Value

Mfg.

Mfg. Part Number

26

20

L505, L506, L50ꢁ,

L50±, L509, L510,

L511, L512, L513,

L51ꢀ, L515, L516,

L51ꢁ, L51±, L519,

L520, L605, L606,

L60ꢁ, L60±, L609,

L610, L611, L612,

L613, L61ꢀ, L615,

L616, L61ꢁ, L61±,

L619, L620

Resistor

±05

0 Ω, 1/± W, 5% tol

NIC

Components

Corp.

NRC0ꢀZ0TRF

2ꢁ

2±

29

1

9

1

OSCꢀ01

Oscillator

Connector

SMT

Clock oscillator,

50.00 MHz, 3.3 V,

±5% duty cycle

Side-mount SMA for

0.063" board thickness

Valphey Fisher

VFAC3H-L-50MHz

1ꢀ2-0ꢁ01-±51

6ꢀ69169-1

P101, P103, P105,

P10ꢁ, P201, P203,

P205, P20ꢁ, Pꢀ01

SMA

Johnson

Components

P301

HEADER

1ꢀ69169-1, right angle

2-pair, 25 mm, header

assembly

Tyco

30

31

1

Pꢁ01

Connector

Resistor

0.1", PCMT RAPCꢁ22, power

supply connector

Switchcraft

RAPCꢁ22X

21

R301, R30ꢁ, Rꢀ01,

Rꢀ02, Rꢀ10, Rꢀ13,

R50ꢀ, R505, R511,

R512, R523, R52ꢀ,

R60ꢀ, R605, R611,

R612, R623, R62ꢀ,

Rꢁ11, Rꢁ1ꢀ, Rꢁ15

ꢀ02

10 kΩ, 1/16 W,

5% tol

NIC

Components

Corp.

NRC0ꢀJ103TRF

32

1±

R103, R11ꢁ, R129,

R1ꢀ2, R203, R219,

R235, R253, R31ꢁ,

Rꢀ05, Rꢀ15, Rꢀ16,

Rꢀ1ꢁ, Rꢀ1±, Rꢁ06,

Rꢁ0ꢁ, Rꢁ0±, Rꢁ09

Resistor

ꢀ02

0 Ω, 1/16 W,

5% tol

NIC

Components

Corp.

NRC0ꢀZ0TRF

33

3ꢀ

35

±

R102, R115, R12±,

R1ꢀ1, R202, R21±,

R23ꢀ, R252

R10ꢀ, R116, R130,

R1ꢀ3, R20ꢀ, R220,

R236, R25ꢀ

R109, R111, R112,

R123, R125, R126,

R135, R13±, R139,

R1ꢀ±, R1ꢀ9, R150,

R211, R212, R21ꢀ,

R22±, R231, R232,

R2ꢀ6, R2ꢀ9, R250,

R262, R265, R266,

R319, Rꢁ10, Rꢁ12,

Rꢁ13

Resistor

ꢀ02

603

ꢀ02

6ꢀ.9 Ω, 1/16 W,

1% tol

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NRC0ꢀF6ꢀR9TRF

NRC06Z0TRF

±

0 Ω, 1/10 W,

5% tol

2±

1 kΩ, 1/16 W,

1% tol

NRC0ꢀF1001TRF

36

16

R10±, R110, R121,

R122, R13ꢀ, R136,

R1ꢀ6, R1ꢀꢁ, R209,

R210, R226, R22ꢁ,

R2ꢀ2, R2ꢀ5, R260,

R261

Resistor

ꢀ02

33 Ω, 1/16 W,

5% tol

NIC

Components

Corp.

NRC0ꢀJ330TRF

Rev. 0 | Page 52 of 56

AD9222

Qnty.

per

Item Board REFDES

Device

Pkg.

Value

Mfg.

Mfg. Part Number

3ꢁ

3±

39

±

3

1

R161, R162, R163,

R16ꢀ, R20±, R225,

R2ꢀ1, R259

Resistor

ꢀ02

ꢀ99 Ω, 1/16 W,

1% tol

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NRC0ꢀFꢀ990TRF

NRC0ꢀF1003TRF

NRC0ꢀFꢀ121TRF

R303, R305, R306

Resistor

ꢀ02

100 kΩ, 1/16 W,

1% tol

Rꢀ1ꢀ

ꢀ.12 kΩ, 1/16W,

1% tol

ꢀ0

ꢀ1

1

Rꢀ0ꢀ

R309

Resistor

ꢀ02

ꢀ9.9 Ω, 1/16 W,

0.5% tol

ꢀ.99 kΩ, 1/16 W,

5% tol

Susumu

RR0510R-ꢀ9R9-D

NRC0ꢀFꢀ991TRF

NIC

Components

Corp.

ꢀ2

ꢀ3

ꢀꢀ

ꢀ5

2

R310, R501, R535,

R601, R63ꢀ

Potentiometer

Resistor

3-lead

ꢀ02

10 kΩ, Cermet trimmer

potentiometer, 1± turn

top adjust, 10%, 1/2 W

ꢀꢁ0 kΩ, 1/16 W,

5% tol

COPAL

ELECTRONICS

CT9ꢀEW103

1

R30±

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NRC0ꢀJꢀꢁꢀTRF

NRC0ꢀJ393TRF

NRC0ꢀF1±ꢁ0TRF

ꢀ

R502, R536, R602,

R635

Resistor

ꢀ02

39 kΩ, 1/16 W,

5% tol

16

R513, R51ꢀ, R51±,

R519, R525, R526,

R530, R531, R613,

R61ꢀ, R61±, R619,

R625, R626, R630,

R631

Resistor

ꢀ02

1±ꢁ Ω, 1/16 W,

1% tol

ꢀ6

ꢀꢁ

ꢀ±

±

R515, R520, R52ꢁ,

R532, R615, R620,

R62ꢁ, R632

R503, R50ꢁ, R50±,

R509, R603, R60ꢁ,

R60±, R609

Rꢀ25,Rꢀ2ꢁ, Rꢀ29,

Rꢀ31, Rꢀ33, Rꢀ35,

Rꢀ36, Rꢀ39, Rꢀꢀ1,

Rꢀꢀ3, Rꢀꢀ5

Resistor

ꢀ02

201

3ꢁꢀ Ω, 1/16 W,

1% tol

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NRC0ꢀF3ꢁꢀ0TRF

NRC0ꢀF2ꢁꢀ0TRF

NRC02Z0TRF

±

2ꢁꢀ Ω, 1/16 W,

1% tol

11

0 Ω, 1/20 W,

5% tol

ꢀ9

50

51

52

53

5ꢀ

ꢀ

1

2

1

Rꢁ01

Resistor

Switch

ꢀ02

603

ꢀ02

SMD

ꢀ.ꢁ kΩ, 1/16 W,

1% tol

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NIC

Components

Corp.

NRC0ꢀJꢀꢁ2TRF

NRC0ꢀF2610TRF

NRC06F261OTRF

NRC0ꢀJ2ꢀ1TRF

NRC0ꢀF1000TRF

EVQ-PLDA15

Rꢁ02

261 Ω, 1/16 W,

1% tol

Rꢁ16

261 Ω, 1/16 W,

1% tol

Rꢀ20, Rꢀ21

Rꢀ22, Rꢀ23

Sꢁ01

2ꢀ0 Ω, 1/16 W,

5% tol

100 Ω, 1/16 W,

1% tol

LIGHT TOUCH,

100GE, 5 mm

Panasonic

Rev. 0 | Page 53 of 56

AD9222

Qnty.

per

Item Board REFDES

Device

Pkg.

Value

Mfg.

Mfg. Part Number

55

56

5ꢁ

9

2

T101, T102, T103,

T10ꢀ, T201, T202,

T203, T20ꢀ, Tꢀ01

Transformer

CD5ꢀ2

ADT1-1WT+,

1:1 impedance ratio

transformer

ADP33339AKC-1.±-RL,

1.5 A, 1.± V LDO

regulator

AD±33ꢀACPZ-REEL,

ultralow noise

Mini-Circuits

ADT1-1WT+

Uꢁ0ꢀ, Uꢁ0ꢁ

IC

SOT-223

CP-6ꢀ-3

Analog Devices

ADP3339AKCZ-1.±-RL

AD±33ꢀACPZ-REEL

U501, U601

precision dual VGA

5±

59

60

1

Uꢁ06

Uꢁ05

U301

IC

SOT-223

CP-6ꢀ-3

ADP33339AKC-5-RLꢁ

ADP33339AKC-3.3-RL

AD9222BCPZ-50, octal,

12-bit, 50 MSPS serial

LVDS 1.± V ADC

Analog Devices

ADP3339AKCZ-5-RLꢁ

ADP3339AKCZ-3.3-RL

AD9222BCPZ-50

61

1

U302

IC

SOT-23

ADR510ARTZ, 1.0 V,

precision low noise

shunt voltage

Analog Devices

ADR510ARTZ

reference

62

63

6ꢀ

65

1

Uꢀ01

Uꢁ02

Uꢁ03

Uꢁ01

IC

LFCSP

CP-32-2

SCꢁ0,

MAA06A

SCꢁ0,

MAA06A

±-SOIC

AD9515BCPZ, 1.6 GHz

clock distribution IC

NCꢁWZ0ꢁP6X_NL,

UHS dual buffer

NCꢁWZ16P6X_NL,

UHS dual buffer

Flash prog

Analog Devices

Fairchild

AD9515BCPZ

NCꢁWZ0ꢁP6X_NL

NCꢁWZ16P6X_NL

PIC12F629-I/SNG

Fairchild

Microchip

mem 1kx1ꢀ,

RAM size 6ꢀ × ±,

20 MHz speed, PIC12F

controller series

¹This BOM is RoHS compliant.

Rev. 0 | Page 5ꢀ of 56

AD9222

OUTLINE DIMENSIONS

0.30

0.25

0.18

9.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

64

49

1

48

PIN 1

INDICATOR

7.25

7.10 SQ

6.95

8.75

BSC SQ

TOP

VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.45

0.40

0.35

33

16

17

32

0.25 MIN

7.50

REF

0.80 MAX

0.65 TYP

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

SEATING

PLANE

0.50 BSC

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 78. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Octal

(CP-64-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

6ꢀ-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6ꢀ-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel

6ꢀ-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6ꢀ-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel

Evaluation Board

Package Option

CP-6ꢀ-3

AD9222BCPZ-ꢀ0¹

AD9222BCPZRLꢁ-ꢀ0¹

AD9222BCPZ-50¹

AD9222BCPZRLꢁ-50¹

AD9222-50EBZ

−ꢀ0°C to +±5°C

¹Z = Pb-free part.

Rev. 0 | Page 55 of 56

AD9222

NOTES

registered trademarks are the property of their respective owners.

D05967-0-9/06(0)

Rev. 0 | Page 56 of 56


型号：	AD9222
厂家：	ADI
描述：	Octal, 12-Bit, 40/50 MSPS Serial LVDS 1.8 V A/D Converter 八通道，12位， 40/50 MSPS串行LVDS 1.8 VA / D转换器转换器
文件：	总56页 (文件大小：2237K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9222 [ADI]

相关型号：

AD9222-50EBZ

AD9222-65EB1

AD9222-65EBZ

AD9222ABCPZ-40

AD9222ABCPZ-50

AD9222ABCPZ-65

AD9222ABCPZRL7-40

AD9222ABCPZRL7-50

AD9222ABCPZRL7-65

AD9222BCPZ-40

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AD9222BCPZ-65