AD9229ABCPZ-65_技术文档

Quad, 12-Bit, 50/65 MSPS,

Serial, LVDS, 3 V A/D Converter

AD9229

FUNCTIONAL BLOCK DIAGRAM

FEATURES

PDWN

DTP

DRVDD

DRGND

Four ADCs in 1 package

Serial LVDS digital output data rates

to 780 Mbps (ANSI-644)

Data and frame clock outputs

SNR = 69.5 dB (to Nyquist)

Excellent linearity

DNL = 0.3 LSB (typical)

INL = 0.4 LSB (typical)

400 MHz full power analog bandwidth

Power dissipation

1,350 mW at 65 MSPS

AD9229

VIN+A

VIN–A

12

D+A

D–A

SERIAL

PIPELINE

ADC

SHA

LVDS

VIN+B

VIN–B

D+B

D–B

SERIAL

LVDS

PIPELINE

ADC

SHA

VIN+C

VIN–C

D+C

D–C

SERIAL

LVDS

PIPELINE

ADC

VIN+D

VIN–D

D+D

D–D

SERIAL

LVDS

PIPELINE

ADC

985 mW at 50 MSPS

VREF

1 V p-p to 2 V p-p input voltage range

3.0 V supply operation

SENSE

FCO+

FCO–

0.5V

Power-down mode

Digital test pattern enable for timing alignments

DATA RATE

MULTIPLIER

REFT

REFB

REF

SELECT

DCO+

DCO–

APPLICATIONS

AGND LVDSBIAS

CLK

Digital beam-forming systems for ultrasound

Wireless and wired broadband communications

Communication test equipment

Figure 1.

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital

converter (ADC) with an on-chip sample-and-hold circuit that

is designed for low cost, low power, small size, and ease of use.

The product operates at up to a 65 MSPS conversion rate and is

optimized for outstanding dynamic performance in applications

where a small package size is critical.

1. Four ADCs are contained in a small, space-saving package.

2. A data clock out (DCO) is provided, which operates up to

390 MHz and supports double-data rate operation (DDR).

3. The outputs of each ADC are serialized LVDS with data

rates up to 780 Mbps (12 bits × 65 MSPS).

The ADC requires a single 3 V power supply and TTL-/CMOS-

compatible sample rate clock for full performance operation.

No external reference or driver components are required for

many applications.

4. The AD9229 operates from a single 3.0 V power supply.

5. Packaged in a Pb-free, 48-lead LFCSP package.

6. The internal clock duty cycle stabilizer maintains

performance over a wide range of input clock duty cycles.

The ADC automatically multiplies the sample rate clock for the

appropriate LVDS serial data rate. A data clock (DCO) for

capturing data on the output and a frame clock (FCO) trigger

for signaling a new output byte are provided. Power-down is

supported and typically consumes 3 mW when enabled.

Fabricated with an advanced CMOS process, the AD9229 is

available in a Pb-free, 48-lead LFCSP package. It is specified

over the industrial temperature range of –40°C to +85°C.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD9229

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Diagram ............................................................................... 7

Absolute Maximum Ratings............................................................ 8

Explanation of Test Levels........................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Equivalent Circuits......................................................................... 10

Typical Performance Characteristics ........................................... 11

Terminology.................................................................................... 16

Theory of Operation ...................................................................... 18

Analog Input Considerations ................................................... 18

Clock Input Considerations...................................................... 19

Evaluation Board ............................................................................ 24

Power Supplies............................................................................ 24

Input Signals................................................................................ 24

Output Signals ............................................................................ 24

Default Operation and Jumper Selection Settings................. 25

Alternate Analog Input Drive Configuration......................... 25

Outline Dimensions....................................................................... 39

Ordering Guide .......................................................................... 39

REVISION HISTORY

5/10—Rev. A to Rev. B

Change to Item 47 in Table 11 ...................................................... 38

Updated Outline Dimensions....................................................... 39

Change to Ordering Guide............................................................ 39

9/05—Rev. 0 to Rev. A

Change to Specifications.................................................................. 3

Changes to Differential Input Configurations Section.............. 19

Changes to Exposed Paddle Thermal Heat Slug

Recommendations Section........................................................ 23

Changes to Evaluation Board Section.......................................... 24

Changes to Table 11........................................................................ 36

3/05—Revision 0: Initial Version

Rev. B | Page 2 of 40

AD9229

SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless

otherwise noted.

Table 1.

AD9229-50

Typ

AD9229-65

Min Typ

Test

Parameter

Temperature Level Min

Max

Unit

RESOLUTION

12

Bits

ACCURACY

No Missing Codes

Offset Error

Offset Matching

Gain Error¹

Gain Matching¹

Full

2±°C

Full

2±°C

Full

VI

V

VI

V

VI

Guaranteed

±±

±0.3

±0.2

±0.3

±0.ꢀ

Guaranteed

±±

±0.3

±0.2

±0.3

±0.4

±2±

±2.±

±1.±

±2±

±2.±

±1.±

mV

% FS

LSB

Differential Nonlinearity (DNL)

±0.ꢀ

±1

±0.ꢁ

±1

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error

Full

V

±2

±12

±1ꢀ

±3

±12

±1ꢀ

ppm/°C

Gain Error¹

Reference Voltage, VREF = 1 V

REFERENCE

Output Voltage Error, VREF = 1 V

Load Regulation @ 1.0 mA, VREF = 1 V Full

Output Voltage Error, VREF = 0.± V

Load Regulation @ 0.± mA,

VREF = 0.± V

Full

VI

V

VI

V

±10

3

±ꢂ

0.2

±30

±1ꢁ

±10

3

±ꢂ

0.2

±30

±1ꢁ

mV

Full

Input Resistance

ANALOG INPUTS

Full

V

ꢁ

kΩ

Differential Input Voltage Range

VREF = 1 V

Differential Input Voltage Range

VREF = 0.± V

Full

VI

2

1

2

1

V p-p

Common Mode Voltage

Input Capacitance²

Analog Bandwidth, Full Power

POWER SUPPLY

AVDD

DRVDD

IAVDD

DRVDD

Full

V

1.±

ꢁ

400

1.±

ꢁ

400

V

pF

MHz

Full

IV

VI

V

2.ꢁ

3.0

300

2ꢂ

9ꢂ±

3

3.ꢀ

330

31

10ꢂ3

2.ꢁ

3.0

420

29

13±0

3

3.ꢀ

4±±

33

14ꢀ±

V

mA

mW

dB

Power Dissipation³

Power-Down Dissipation

CROSSTALK⁴

V

–9±

¹Gain error and gain temperature coefficients are based on the ADC only, with a fixed 1.0 V external reference and a 2 V p-p differential analog input.

²Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.

³Power dissipation measured with rated encode and 2.4 MHz analog input at –0.± dBFS.

⁴Typical specification over the first Nyquist zone.

Rev. B | Page 3 of 40

AD9229

AC SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless

otherwise noted.

Table 2.

AD9229-50

AD9229-65

Test

Level

Parameter

Temperature

Full

2±°C

Full

2±°C

Full

2±°C

Full

2±°C

Full

Min

Typ

ꢁ0.4

ꢀ9.ꢀ

Max

Min Typ

Max

Unit

dB

Bits

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 2.4 MHz

f_IN= 10.3 MHz

f_IN= 2± MHz

f_IN= 30 MHz

f_IN= ꢁ0 MHz

f_IN= 2.4 MHz

f_IN= 10.3 MHz

f_IN= 2± MHz

f_IN= 30 MHz

f_IN= ꢁ0 MHz

f_IN= 2.4 MHz

IV

V

VI

V

ꢀ9.±

ꢀ9.0 ꢁ0.2

ꢁ0.2

ꢀꢂ.ꢁ

ꢀꢂ.0 ꢀ9.±

ꢀꢁ.1

ꢀꢁ.2

ꢁ0.0

ꢀ9.4

SIGNAL-TO-NOISE RATIO (SINAD)

V

VI

V

ꢀ9.ꢂ

ꢀꢂ.4

ꢀꢁ.3 ꢀ9.0

ꢀꢀ.ꢁ

ꢀꢀ.ꢂ

11.3

EFFECTIVE NUMBER OF BITS

(ENOB)

V

11.3

f_IN= 10.3 MHz

f_IN= 2± MHz

f_IN= 30 MHz

f_IN= ꢁ0 MHz

2±°C

Full

2±°C

Full

V

11.3

11.2

11.3

Bits

dBc

VI

V

11.1

10.9 11.2

10.ꢂ

ꢂ±

10.ꢂ

ꢂ±

SPURIOUS-FREE DYNAMIC RANGE f_IN= 2.4 MHz

(SFDR)

V

f_IN= 10.3 MHz

f_IN= 2± MHz

f_IN= 30 MHz

f_IN= ꢁ0 MHz

2±°C

Full

2±°C

Full

2±°C

Full

2±°C

Full

2±°C

Full

V

ꢂ±

dBc

VI

V

ꢁꢀ

ꢁ3

ꢂ±

ꢁꢁ

ꢁꢂ

WORST HARMONIC

(Second or Third)

f_IN= 2.4 MHz

f_IN= 10.3 MHz

f_IN= 2± MHz

f_IN= 30 MHz

f_IN= ꢁ0 MHz

f_IN= 2.4 MHz

f_IN= 10.3 MHz

f_IN= 2± MHz

f_IN= 30 MHz

f_IN= ꢁ0 MHz

f_IN1= 1± MHz

V

VI

V

VI

V

–ꢂ±

–ꢁꢀ

–ꢂ±

–ꢁꢁ

–90

–ꢁ3

–ꢁꢂ

–90

–ꢂꢂ

WORST OTHER

(Excluding Second or Third)

–ꢂ1.ꢁ

–ꢂꢂ

–ꢂ3

–ꢁ3

–ꢁ9.ꢁ

2±°C

–ꢂ±

–ꢁ3

TWO-TONE INTERMODULATION

DISTORTION (IMD)

V

AIN1 and AIN2 = –ꢁ.0 dBFS

f_IN2= 1ꢀ MHz

f_IN1= ꢀ9 MHz

f_IN2= ꢁ0 MHz

2±°C

V

–ꢀꢂ.±

dBc

Rev. B | Page 4 of 40

AD9229

DIGITAL SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless

otherwise noted.

Table 3.

AD9229-50

Typ

AD9229-65

Typ

Test

Level

Parameter

Temperature

Min

Max

Min

Max Unit

CLOCK INPUT

Logic Compliance

TTL/CMOS

2.0

TTL/CMOS

2.0

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

Full

2±°C

IV

VI

V

0.ꢂ

±10

0.ꢂ

V

0.±

2

0.±

2

±10

μA

pF

LOGIC INPUTS (PDWN)

Logic 1 Voltage

Logic 0 Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

Full

2±°C

IV

V

2.0

V

μA

pF

0.ꢂ

±10

0.ꢂ

±10

0.±

2

0.±

2

DIGITAL OUTPUTS (D+, D–)

Logic Compliance

Differential Output Voltage

Output Offset Voltage

Output Coding

LVDS

2ꢀ0

1.1±

LVDS

2ꢀ0

1.1±

Full

VI

440

1.3±

440

1.3±

mV

V

1.2±

Offset

binary

1.2±

Offset

binary

Rev. B | Page ± of 40

AD9229

SWITCHING SPECIFICATIONS

AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless

otherwise noted.

Table 4.

AD9229-50

Typ

AD9229-65

Typ

Test

Temp Level

Parameter

Min

Max

Min

Max

Unit

CLOCK

Maximum Clock Rate

Full

VI

IV

VI

±0

ꢀ±

MSPS

ns

Minimum Clock Rate

10

Clock Pulse Width High

(t_EH)

ꢂ

10

ꢀ.2

ꢁ.ꢁ

Clock Pulse Width Low

(t_EL)

Full

VI

ns

OUTPUT PARAMETERS

Propagation Delay (t_PD

)

Full

VI

V

3.3

ꢀ.±

ꢁ.9

3.3

ꢀ.±

ꢁ.9

ns

ps

Rise Time (t_R)

(20% to ꢂ0%)

2±0

Fall Time (t_F)

(20% to ꢂ0%)

Full

V

2±0

ꢀ.±

2±0

ꢀ.±

ps

ns

ps

ms

FCO Propagation Delay

(t_FCO

DCO Propagation Delay

(t_CPD

DCO-to-Data Delay (t_DATA

V

)

V

t_FCO

(t_SAMPLE/24)

+

t_FCO+

(t_SAMPLE/24)

)

IV

(t_SAMPLE/24) –

2±0

(t_SAMPLE/24)

(t_SAMPLE/24) +

2±0

(t_SAMPLE/24) –

2±0

(t_SAMPLE/24)

(t_SAMPLE/24) +

2±0

DCO-to-FCO Delay (t_FRAME

Data-to-Data Skew

)

(t_SAMPLE/24) –

2±0

(t_SAMPLE/24)

±100

(t_SAMPLE/24) +

2±0

(t_SAMPLE/24) –

2±0

(t_SAMPLE/24)

±100

(t_SAMPLE/24) +

2±0

±2±0

(t_DATA-MAX– t_DATA-MIN

)

Wake-Up Time

2±°C

Full

V

4

Pipeline Latency

IV

10

CLK

cycles

APERTURE

Aperture Delay (t_A)

2±°C

V

1.ꢂ

<1

1.ꢂ

<1

ns

Aperture Uncertainty

(Jitter)

ps

rms

OUT-OF-RANGE RECOVERY

TIME

2±°C

V

2

CLK

cycles

Rev. B | Page ꢀ of 40

AD9229

TIMING DIAGRAM

N – 1

AIN

N

t_A

t_EH

t_EL

CLK

t_CPD

DCO–

DCO+

t_FCO

t_FRAME

FCO–

FCO+

t_DATA

D6

t_PD

D–

D+

MSB D10 D9

D8

D7

D5

D4

D3

D2

D1

D0 MSB D10

(N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 9) (N – 9)

Figure 2. Timing Diagram

Rev. B | Page ꢁ of 40

AD9229

ABSOLUTE MAXIMUM RATINGS

Table 5.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

With

Respect To

Parameter

ELECTRICAL

AVDD

DRVDD

AGND

AVDD

Digital Outputs (D+, D–,

DCO+, DCO–, FCO+, FCO–)

Rating

AGND

–0.3 V to +3.9 V

–0.3 V to +0.3 V

–3.9 V to +3.9 V

–0.3 V to DRVDD

DRGND

DRVDD

DRGND

EXPLANATION OF TEST LEVELS

I. 100% production tested.

LVDSBIAS

CLK

DRGND

AGND

–0.3 V to DRVDD

–0.3 V to AVDD

II. 100% production tested at 25°C and guaranteed by design

and characterization at specified temperatures.

VIN+, VIN–

PDWN, DTP

REFT, REFB

VREF, SENSE

ENVIRONMENTAL

Operating Temperature

Range (Ambient)

Maximum Junction

Temperature

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization

testing.

–40°C to +ꢂ±°C

1±0°C

V. Parameter is a typical value only.

VI. 100% production tested at 25°C and guaranteed by design

and characterization for industrial temperature range.

Lead Temperature

(Soldering, 10 sec)

300°C

Storage Temperature Range

(Ambient)

Thermal Impedance¹

–ꢀ±°C to +1±0°C

2±°C/W

¹θ_JAfor a 4-layer PCB with a solid ground plane in still air.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. B | Page ꢂ of 40

AD9229

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

DRGND

DRVDD

NC

1

2

3

4

5

6

7

8

9

36 DRGND

35 DRVDD

34 LVDSBIAS

33 AGND

32 AVDD

31 AGND

30 CLK

EXPOSED PADDLE, PIN 0

(Bottom of Package)

DTP

AVDD

AGND

PDWN

AVDD

AGND

AD9229

TOP VIEW

(Not to Scale)

29 AVDD

28 AGND

27 VIN+D

26 VIN–D

25 AGND

VIN+A 10

VIN–A 11

AGND 12

NC = NO CONNECT

Figure 3. LFCSP Top View

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

Pin No.

Mnemonic

Description

±, ꢂ, 1ꢀ, 21,

29, 32

AVDD

Analog Supply

2ꢀ

VIN–D

ADC D Analog Input—

Complement

ꢀ, 9, 12, 1±, 22, AGND

2±, 2ꢂ, 31, 33

Analog Ground

2ꢁ

30

34

VIN+D

CLK

LVDSBIAS

ADC D Analog Input—True

Input Clock

LVDS Output Current Set

Resistor Pin

ADC D Complement Digital

Output

ADC D True Digital Output

ADC C Complement Digital

Output

ADC C True Digital Output

ADC B Complement Digital

Output

ADC B True Digital Output

ADC A Complement Digital

Output

ADC A True Digital Output

Frame Clock Indicator—

Complement Output

Frame Clock Indicator—True

Output

Data Clock Output—

Complement

Data Clock Output—True

2, 3±

1, 3ꢀ

0

DRVDD

DRGND

AGND

Digital Output Supply

Digital Ground

Exposed Paddle/Thermal Heat

Slug (Located on Bottom of

Package)

No Connect

Digital Test Pattern Enable

Power-Down Selection (AVDD =

Power Down)

ADC A Analog Input—True

ADC A Analog Input—

Complement

ADC B Analog Input—

Complement

ADC B Analog Input—True

Reference Mode Selection

Voltage Reference Input/Output

Differential Reference (Bottom)

Differential Reference (Top)

ADC C Analog Input—True

3ꢁ

D–D

3ꢂ

39

D+D

D–C

3

4

ꢁ

NC

DTP

PDWN

40

41

D+C

D–B

10

11

VIN+A

VIN–A

42

43

D+B

D–A

13

VIN–B

44

4±

D+A

FCO–

14

1ꢁ

1ꢂ

19

20

23

24

VIN+B

SENSE

VREF

REFB

REFT

4ꢀ

4ꢁ

4ꢂ

FCO+

DCO–

DCO+

VIN+C

VIN–C

ADC C Analog Input—

Complement

Rev. B | Page 9 of 40

AD9229

EQUIVALENT CIRCUITS

AVDD

DRVDD

VIN+, VIN–

V

D–

D+

V

AGND

DRGND

Figure 4. Equivalent Analog Input Circuit

Figure 7. Equivalent Digital Output Circuit

AVDD

DTP

375Ω

100kΩ

CLK

170Ω

AGND

Figure 5. Equivalent Clock Input Circuit

Figure 8. Equivalent DTP Input Circuit

AVDD

PDWN

375Ω

AGND

Figure 6. Equivalent Digital Input Circuit

Rev. B | Page 10 of 40

AD9229

TYPICAL PERFORMANCE CHARACTERISTICS

0

AIN = –0.5dBFS

SNR = 70.4dB

AIN = –0.5dBFS

SNR = 68.1dB

ENOB = 11.4 BITS

SFDR = 85.8dBC

ENOB = 11.0 BITS

SFDR = 77.0dBC

–20

–40

–60

–80

–40

–60

–80

–100

–120

–100

–120

0

4.1

8.1

12.2

16.3

20.3

24.4

28.4

32.5

0

4.1

8.1

12.2

16.3

20.3

24.4

28.4

32.5

FREQUENCY (MHz)

Figure 9. Single-Tone 32k FFT with f_IN= 2.4 MHz, f_SAMPLE= 65 MSPS

Figure 12. Single-Tone 32k FFT with f_IN= 120 MHz, f_SAMPLE= 65 MSPS

0

90

1V p-p, SFDR (dBc)

AIN = –0.5dBFS

SNR = 69.6dB

ENOB = 11.3 BITS

SFDR = 82.4dBC

–20

85

2V p-p, SFDR (dBc)

–40

80

75

–60

–80

2V p-p, SNR (dB)

70

–100

–120

65

1V p-p, SNR (dB)

AIN = –0.5dBFS

40 45 50

60

10

0

4.1

8.1

12.2

16.3

20.3

24.4

28.4

32.5

15

20

25

30

35

FREQUENCY (MHz)

ENCODE (MSPS)

Figure 10. Single-Tone 32k FFT with f_IN= 30 MHz, f_SAMPLE= 65 MSPS

Figure 13. SNR/SFDR vs. f_SAMPLE, f_IN= 10.3 MHz, f_SAMPLE= 50 MSPS

0

90

1V p-p, SFDR (dBc)

AIN = –0.5dBFS

SNR = 68.5dB

ENOB = 11.1 BITS

SFDR = 81.3dBC

–20

85

–40

80

75

70

2V p-p, SFDR (dBc)

–60

–80

2V p-p, SNR (dB)

1V p-p, SNR (dB)

–100

–120

65

60

AIN = –0.5dBFS

40 45 50

0

4.1

8.1

12.2

16.3

20.3

24.4

28.4

32.5

10

15

20

25

30

35

FREQUENCY (MHz)

ENCODE (MSPS)

Figure 11. Single-Tone 32k FFT with f_IN= 70 MHz, f_SAMPLE= 65 MSPS

Figure 14. SNR/SFDR vs. f_SAMPLE, f_IN= 25 MHz, f_SAMPLE= 50 MSPS

Rev. B | Page 11 of 40

AD9229

95

90

1V p-p, SFDR (dBc)

2V p-p, SFDR (dBc)

80

70

60

50

90

1V p-p, SFDR (dBc)

85

80

40

30

80 dB REFERENCE

75

70

2V p-p, SNR (dB)

20

2V p-p, SNR (dB)

65

60

1V p-p, SNR (dB)

10

0

AIN = –0.5dBFS

50 55 60

10 15

20

25

30

35

40

45

65

–60

–50

–40

–30

–20

–10

0

ENCODE (MSPS)

ANALOG INPUT LEVEL (dBFS)

Figure 15. SNR/SFDR vs. f_SAMPLE, f_IN= 10.3 MHz, f_SAMPLE= 65 MSPS

Figure 18. SNR/SFDR vs. Analog Input Level,

f_IN=25 MHz, f_SAMPLE= 50 MSPS

85

90

2V p-p, SFDR (dBc)

1V p-p, SFDR (dBc)

80

70

60

50

80

1V p-p, SFDR (dBc)

75

40

30

80 dB REFERENCE

2V p-p, SNR (dB)

70

20

65

2V p-p, SNR (dB)

1V p-p, SNR (dB)

10

0

AIN = –0.5dBFS

50 55 60

60

10 15

20

25

30

35

40

45

65

–60

–50

–40

–30

–20

–10

ENCODE (MSPS)

ANALOG INPUT LEVEL (dBFS)

Figure 16. SNR/SFDR vs. f_SAMPLE, f_IN= 30 MHz, f_SAMPLE= 65 MSPS

Figure 19. SNR/SFDR vs. Analog Input Level,

f_IN= 10.3 MHz, f_SAMPLE= 65 MSPS

90

2V p-p, SFDR (dBc)

80

2V p-p, SFDR (dBc)

80

70

60

50

70

1V p-p, SFDR (dBc)

60

50

40

30

40

80 dB REFERENCE

30

20

2V p-p, SNR (dB)

1V p-p, SNR (dB)

10

0

–60

–50

–40

–30

–20

–10

–50

–40

–30

–20

–10

0

ANALOG INPUT LEVEL (dBFS)

Figure 20. SNR/SFDR vs. Analog Input Level,

f_IN= 30 MHz, f_SAMPLE= 65 MSPS

Figure 17. SNR/SFDR vs. Analog Input Level,

f_IN= 10.3 MHz, f_SAMPLE= 50 MSPS

Rev. B | Page 12 of 40

AD9229

90

80

70

85

80

75

70

SFDR (dBc)

2V p-p, SFDR (dBc)

60

50

40

80 dB REFERENCE

SNR (dB)

65

60

30

20

1V p-p, SFDR (dBc)

55

10

0

50

45

1

10

100

1000

–60 –56 –52 –48 –44 –40 –36 –32 –28 –23 –19 –15 –10 –7

FREQUENCY (MHz)

ANALOG INPUT LEVEL (dBFS)

Figure 21. SNR/SFDR vs. f_IN, f_SAMPLE= 65 MHz

Figure 24. Two-Tone SFDR vs. Analog Input Level, f_IN1= 15 MHz and

f_IN2= 16 MHz, f_SAMPLE= 65 MSPS

0

80

AIN1 AND AIN2= –7.0dBFS

SFDR = 73.0dBc

IMD2 = 80.5dBc

IMD3 = 73.0dBc

70

–20

–40

–60

–80

2V p-p, SFDR (dBc)

60

50

40

80 dB REFERENCE

1V p-p, SFDR (dBc)

30

20

–100

–120

10

0

4.1

8.1

12.2

16.3

20.3

24.4

28.4

32.5

–60 –56 –52 –48 –44 –40 –36 –32 –28 –23 –19 –15 –10 –7

FREQUENCY (MHz)

ANALOG INPUT LEVEL (dBFS)

Figure 22. Two-Tone 32k FFT with f_IN1= 15 MHz and f_IN2= 16 MHz,

f_SAMPLE= 65 MSPS

Figure 25. Two-Tone SFDR vs. Analog Input Level, f_IN1= 69 MHz and

f_IN2= 70 MHz, f_SAMPLE= 65 MSPS

0

90

AIN1 AND AIN2= –7.0dBFS

SFDR = 68.5dBc

1V p-p, SFDR (dBc)

IMD2 = 77.0dBc

IMD3 = 68.5dBc

–20

85

2V p-p, SFDR (dBc)

–40

80

75

–60

–80

2V p-p, SINAD (dB)

70

–100

–120

65

1V p-p, SINAD (dB)

60

–40

0

4.1

8.1

12.2

16.3

20.3

24.4

28.4

32.5

–20

0

20

40

60

80

FREQUENCY (MHz)

TEMPERATURE (°C)

Figure 23. Two-Tone 32k FFT with f_IN1= 69 MHz and f_IN2= 70 MHz,

f_SAMPLE= 65 MSPS

Figure 26. SINAD/SFDR vs. Temperature, f_IN10.3 MHz, f_SAMPLE= 65 MSPS

Rev. B | Page 13 of 40

AD9229

–40

–50

–60

15

10

5

0

–5

–10

–70

–80

–15

–20

0

5

10

15

20

25

30

–40

–20

0

20

40

60

80

FREQUENCY (MHz)

TEMPERATURE (°C)

Figure 30. CMRR vs. Frequency, f_SAMPLE= 65 MSPS

Figure 27. Gain Error vs. Temperature

10

9

0.5

0.36LSB rms

0.4

0.3

0.2

0.1

0

8

7

6

5

4

–0.1

3

–0.2

–0.3

2

1

0

–0.4

–0.5

N – 3

N – 2

N – 1

N

N + 1

N + 2

N + 3

0

512

1024 1536

2048 2560

CODE

3072 3584

4095

CODE

Figure 28. Typical INL, f_IN= 2.4 MHz, f_SAMPLE= 65 MSPS

Figure 31. Input Referred Noise Histogram, f_SAMPLE= 65 MSPS

0.5

0

NPR = 60.8dB

NOTCH = 18MHz

NOTCH WIDTH = 3MHz

0.4

0.3

0.2

0.1

0

–20

–40

–60

–80

–0.1

–0.2

–0.3

–100

–120

–0.4

–0.5

0

512

1024 1536

2048 2560

CODE

3072 3584

4095

0

4.1

8.1

12.2

16.3

20.3

24.4

28.4

32.5

FREQUENCY (MHz)

Figure 29. Typical DNL, f_IN= 2.4 MHz, f_SAMPLE= 65 MSPS

Figure 32. Noise Power Ratio (NPR), f_SAMPLE= 65 MSPS

Rev. B | Page 14 of 40

AD9229

0

–1

–2

–3

–4

–5

–6

–7

–8

0

50

100 150

350 400 450 500

200 250 300

FREQUENCY (MHz)

Figure 33. Full Power Bandwidth vs. Frequency, f_SAMPLE= 65 MSPS

Rev. B | Page 1± of 40

AD9229

TERMINOLOGY

Analog Bandwidth

Full Power Bandwidth

Analog bandwidth is the analog input frequency at which the

spectral power of the fundamental frequency (as determined by

the FFT analysis) is reduced by 3 dB from full scale.

Full power bandwidth is the measured –3 dB point at the analog

front-end input relative to the frequency measured.

Gain Error

Aperture Delay

The largest gain error is specified and is considered the

difference between the measured and ideal full-scale input

voltage range.

Aperture delay is a measure of the sample-and-hold amplifier

(SHA) performance and is measured from the 50% point rising

edge of the clock input to the time at which the input signal is

held for conversion.

Gain Matching

Expressed as a percentage of FSR and computed using the

following equation:

Aperture Uncertainty (Jitter)

Aperture jitter is the variation in aperture delay for successive

samples and can be manifested as frequency-dependent noise

on the ADC input.

FSR ^max− FSR ^min

FSR ^max+ FSR ^min

Gain Matching =

×100%

⎛

⎜

⎝

⎞

⎟

⎠

2

Clock Pulse Width and Duty Cycle

where FSR_MAXis the most positive gain error of the ADCs, and

FSR_MINis the most negative gain error of the ADCs.

Pulse width high is the minimum amount of time that the clock

pulse should be left in the Logic 1 state to achieve rated

performance. Pulse width low is the minimum time the clock

pulse should be left in the low state. At a given clock rate, these

specifications define an acceptable clock duty cycle.

Input-Referred Noise

Input-referred noise is a measure of the wideband noise

generated by the ADC core. Histograms of the output codes are

created while a dc signal is applied to the ADC input. Input-

referred noise is calculated using the standard deviation of the

histograms and presented in terms of LSB rms.

Common Mode Rejection Ratio (CMRR)

CMRR is defined as the amount of rejection on the differential

analog inputs when a common signal is applied. Typically

expressed as 20 log (differential gain/common-mode gain).

Integral Nonlinearity (INL)

INL refers to the deviation of each individual code from a line

drawn from negative full scale through positive full scale. The

point used as negative full scale occurs 0.5 LSB before the first

code transition. Positive full scale is defined as a level 1.5 LSB

beyond the last code transition. The deviation is measured from

the middle of each code to the true straight line.

Crosstalk

Crosstalk is defined as the measure of any feedthrough coupling

onto the quiet channel when all other channels are driven by a

full-scale signal.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to

the converter to generate a full-scale response. Peak differential

voltage is computed by observing the voltage on a pin and

subtracting the voltage from a second pin that is 180° out of

phase.

Noise Power Ratio (NPR)

NPR is the full-scale rms noise power injected into the ADC vs.

the rejected band of interest (notch depth measured).

Offset Error

The largest offset error is specified and is considered the

difference between the measured and ideal voltage at the analog

input that produces the midscale code at the outputs.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Guaranteed

no missing codes to an n-bit resolution indicates that all 2ⁿ

codes, respectively, must be present over all operating ranges.

Offset Matching

Expressed in millivolts and computed using the following

equation:

Effective Number of Bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the

number of bits. Using the following formula, it is possible to

obtain a measure of performance expressed as N, the effective

number of bits:

Offset Matching = OFF_MAX− OFF_MIN

where OFF_MAXis the most positive offset error, and OFF_MINis

the most negative offset error.

N = (SINAD – 1.76)/6.02

Rev. B | Page 1ꢀ of 40

AD9229

Out-of-Range Recovery Time

Signal-to-Noise Ratio (SNR)

Out-of-range recovery time is the time it takes for the ADC to

reacquire the analog input after a transient from 10% above

positive full scale to 10% above negative full scale, or from 10%

below negative full scale to 10% below positive full scale.

SNR is the ratio of the rms value of the measured input signal to

the rms sum of all other spectral components below the Nyquist

frequency, excluding the first six harmonics and dc. The value

for SNR is expressed in decibels.

Output Propagation Delay

Spurious-Free Dynamic Range (SFDR)

The delay between the clock logic threshold and the time when

all bits are within valid logic levels.

SFDR is the difference in decibels between the rms amplitude of

the input signal and the peak spurious signal.

Second and Third Harmonic Distortion

The ratio of the rms signal amplitude to the rms value of the

second or third harmonic component, reported in decibels

relative to the carrier.

Temperature Drift

The temperature drift for offset error and gain error specifies

the maximum change from the initial (25°C) value to the value

at T_MINor T_MAX

.

Signal-to Noise and Distortion (SINAD) Ratio

Two-Tone SFDR

SINAD is the ratio of the rms value of the measured input

signal to the rms sum of all other spectral components below

the Nyquist frequency, including harmonics but excluding dc.

The value for SINAD is expressed in decibels.

The ratio of the rms value of either input tone to the rms value

of the peak spurious component. The peak spurious component

may or may not be an IMD product. It may be reported in

decibels relative to the carrier (that is, degrades as signal levels

are lowered) or in decibels relative to full scale (always related

back to converter full scale).

Rev. B | Page 1ꢁ of 40

AD9229

THEORY OF OPERATION

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current required from the output

stage of the driving source. Also, a small shunt capacitor can

be placed across the inputs to provide dynamic charging

currents. This passive network creates a low-pass filter at the

ADC’s input; therefore, the precise values are dependent on

the application.

The AD9229 architecture consists of a front-end switched capa-

citor sample-and-hold amplifier (SHA) followed by a pipelined

ADC. The pipelined ADC is divided into three sections: a 4-bit

first stage followed by eight 1.5-bit stages and a final 3-bit flash.

Each stage provides sufficient overlap to correct for flash errors

in the preceding stages. The quantized outputs from each stage

are combined into a final 12-bit result in the digital correction

logic. The pipelined architecture permits the first stage to

operate on a new input sample while the remaining stages

operate on preceding samples. Sampling occurs on the rising

edge of the clock.

The analog inputs of the AD9229 are not internally dc-biased.

In ac-coupled applications, the user must provide this bias

externally. For optimum performance, set the device so that

V

_CM= AVDD/2; however, the device can function over a wider

range with reasonable performance (see Figure 35 and Figure 36).

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

90

2V p-p, SFDR (dBc)

85

1V p-p, SFDR (dBc)

80

75

The input stage contains a differential SHA that can be config-

ured as ac- or dc-coupled in differential or single-ended modes.

The output staging block aligns the data, carries out the error

correction, and passes the data to the output buffers. The data is

then serialized and aligned to the frame and output clock.

2V p-p, SNR (dB)

70

65

60

1V p-p, SNR (dB)

0

0.5

1.0

1.5

2.0

2.5

3.0

ANALOG INPUT CONSIDERATIONS

ANALOG INPUT COMMON-MODE VOLTAGE (V)

The analog input to the AD9229 is a differential switched-

capacitor SHA that has been designed for optimum perfor-

mance while processing a differential input signal. The SHA

input can support a wide common-mode range and maintain

excellent performance. An input common-mode voltage of

midsupply minimizes signal-dependent errors and provides

optimum performance.

Figure 35. SNR/SFDR vs. Common-Mode Voltage, f_IN= 2.4 MHz,

f_SAMPLE= 65 MSPS

90

2V p-p, SFDR (dBc)

85

80

1V p-p, SFDR (dBc)

75

2V p-p, SNR (dB)

H

70

65

1V p-p, SNR (dB)

S

60

55

50

VIN+

VIN–

C

PAR

45

40

S

0

0.5

1.0

1.5

2.0

2.5

3.0

ANALOG INPUT COMMON-MODE VOLTAGE (V)

C

PAR

Figure 36. SNR/SFDR vs. Common-Mode Voltage, f_IN= 30 MHz,

f_SAMPLE= 65 MSPS

S

H

For best dynamic performance, the source impedances driving

VIN+ and VIN− should be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC.

Figure 34. Switched-Capacitor SHA Input

The clock signal alternately switches the SHA between sample

mode and hold mode (see Figure 34). When the SHA is

switched into sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

Rev. B | Page 18 of 40

AD9229

An internal reference buffer creates the positive and negative

reference voltages, REFT and REFB, respectively, that defines

the span of the ADC core. The output common-mode of the

reference buffer is set to midsupply, and the REFT and REFB

voltages and span are defined as

AVDD

VIN+

R

2Vp-p

49.9Ω

AD9229

C

AVDD

1kΩ

VIN–

AGND

REFT = 1/2 (AVDD + VREF)

REFB = 1/2 (AVDD − VREF)

1kΩ

0.1μF

Span = 2 × (REFT − REFB) = 2 × VREF

Figure 38. Differential Transformer—Coupled Configuration

It can be seen from the equations above that the REFT and

REFB voltages are symmetrical about the midsupply voltage

and, by definition, the input span is twice the value of the

VREF voltage.

Single-Ended Input Configuration

A single-ended input can provide adequate performance in

cost-sensitive applications. In this configuration, SFDR and

distortion performance degrade due to the large input

common-mode swing. However, if the source impedances

on each input are matched, there should be little effect on

SNR performance. Figure 39 details a typical single-ended

input configuration.

The internal voltage reference can be pin-strapped to fixed

values of 0.5 V or 1.0 V or adjusted within the same range, as

discussed in the Internal Reference Connection section.

Maximum SNR performance is achieved by setting the AD9229

to the largest input span of 2 V p-p.

10μF

The SHA should be driven from a source that keeps the signal

peaks within the allowable range for the selected reference

voltage. The minimum and maximum common-mode input

levels are defined in Figure 35 and Figure 36.

AVDD

1kΩ

R

VIN+

0.1μF

AVDD

1kΩ

2V p-p

49.9Ω

AD9229

C

Differential Input Configurations

R

Optimum performance is achieved by driving the AD9229 in a

differential input configuration. For ultrasound applications,

the AD8332 differential driver provides excellent performance

and a flexible interface to the ADC (see Figure 37).

VIN–

AGND

10μF

0.1μF

1kΩ

Figure 39. Single-Ended Input Configuration

0.1μF

AVDD

CLOCK INPUT CONSIDERATIONS

LOP

VIP

AVDD

VIN+

0.1μF

1.0kΩ

187Ω

374Ω

R

0.1μF 120nH

VOH

VOL

INH

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals and, as a result, may be sensi-

tive to clock duty cycle. Typically, a 10% tolerance is required on

the clock duty cycle to maintain dynamic performance charac-

teristics. The AD9229 has a self-contained clock duty cycle

stabilizer that retimes the nonsampling edge, providing an

internal clock signal with a nominal 50% duty cycle. This allows

a wide range of clock input duty cycles without affecting the

performance of the AD9229.

1V p-p

22p

AD8332

LNA

VGA

C

AD9229

LMD

VIN–

VREF

AGND

0.1μF

187nH

0.1μF

10μF

LON

VIN

274Ω

18nF

0.1μF

Figure 37. Differential Input Configuration Using the AD8332

However, the noise performance of most amplifiers is not

adequate to achieve the true performance of the AD9229. For

applications where SNR is a key parameter, differential transfor-

mer coupling is the recommended input configuration. An

example of this is shown in Figure 38.

An on-board phase-locked loop (PLL) multiplies the input

clock rate for the purpose of shifting the serial data out. The

stability criteria for the PLL limits the minimum sample clock

rate of the ADC to 10 MSPS. Assuming steady state operation of

the input clock, any sudden change in the sampling rate could

create an out-of-lock condition leading to invalid outputs at the

DCO, FCO, and data out pins.

In any configuration, the value of the shunt capacitor, C, is

dependent on the input frequency and may need to be reduced

or removed.

Rev. B | Page 19 of 40

AD9229

1400

1300

500

450

400

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given full-scale

input frequency (f_A) due only to aperture jitter (t_A) can be

calculated with the following equation:

I

AVDD

350

300

1200

1100

1000

SNR degradation = 20 × log 10 [1/2 × π × f_A× t_A]

TOTAL POWER

In the equation, the rms aperture jitter, t_A, represents the root

sum square of all jitter sources, which include the clock input,

analog input signal, and ADC aperture jitter specification.

Applications that require undersampling are particularly

sensitive to jitter.

250

200

150

100

900

800

I

DRVDD

50

0

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the

AD9229. Power supplies for clock drivers should be separated

from the ADC output driver supplies to avoid modulating the

clock signal with digital noise. Low jitter, crystal-controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or other

methods), it should be retimed by the original clock at the

last step.

10

20

30

40

50

60

ENCODE (MSPS)

Figure 41. Supply Current vs. f_SAMPLEfor f_IN= 10.3 MHz, f_SAMPLE= 65 MSPS

By asserting the PDWN pin high, the AD9229 is placed in

power-down mode. In this state, the ADC typically dissipates

3 mW. During power-down, the LVDS output drivers are placed

in a high impedance state. Reasserting the PDWN pin low

returns the AD9229 to normal operating mode.

Power Dissipation and Power-Down Mode

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on REFT and REFB are

discharged when entering standby mode and then must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in the power-down

mode; shorter cycles result in proportionally shorter wake-up

times. With the recommended 0.1 μF and 10 μF decoupling

capacitors on REFT and REFB, it takes approximately 1 sec to

fully discharge the reference buffer decoupling capacitors and

4 ms to restore full operation.

As shown in Figure 40 and Figure 41, the power dissipated by

the AD9229 is proportional to its sample rate. The digital power

dissipation does not vary much because it is determined

primarily by the DRVDD supply and bias current of the LVDS

output drivers.

1200

350

300

250

1100

I

AVDD

1000

900

200

150

100

Digital Outputs

TOTAL POWER

The AD9229’s differential outputs conform to the ANSI-644

LVDS standard. To set the LVDS bias current, place a resistor

(RSET is nominally equal to 4.0 kΩ) to ground at the

800

LVDSBIAS pin. The RSET resistor current is derived on-chip

and sets the output current at each output equal to a nominal

3.5 mA. A 100 Ω differential termination resistor placed at the

LVDS receiver inputs results in a nominal 350 mV swing at the

receiver. To adjust the differential signal swing, simply change

the resistor to a different value, as shown in Table 7.

700

600

50

0

I

DRVDD

10

15

20

25

30

35

40

45

50

ENCODE (MSPS)

Figure 40. Supply Current vs. f_SAMPLEfor f_IN= 10.3 MHz, f_SAMPLE= 50 MSPS

Table 7. LVDSBIAS Pin Configuration

RSET

Differential Output Swing

3.ꢁ kΩ

3ꢁ± mV p-p

4.0 kΩ (default)

4.3 kΩ

3±0 mV p-p

32± mV p-p

Rev. B | Page 20 of 40

AD9229

Table 9. Digital Test Pattern Pin Settings

The AD9229’s LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs that have LVDS capa-

bility for superior switching performance in noisy environ-

ments. Single point-to-point net topologies are recommended

with a 100 Ω termination resistor placed as close to the receiver

as possible. It is recommended to keep the trace length no

longer than 12 inches and to keep differential output traces

close together and at equal lengths.

Resulting

FCO and DCO

Selected DTP

DTP Voltage D+ and D–

Normal

operation

AGND

Normal

operation

Normal

operation

DTP1

AVDD/3

2 × AVDD/3

AVDD

1000 0000 0000

1010 1010 1010

N/A

Normal

operation

DTP2

Normal

operation

Restricted

N/A

The format of the output data is offset binary. An example of

the output coding format can be found in Table 8.

Voltage Reference

A stable and accurate 0.5 V voltage reference is built into the

AD9229. The input range can be adjusted by varying the refer-

ence voltage applied to the AD9229, using either the internal

reference or an externally applied reference voltage. The input

span of the ADC tracks reference voltage changes linearly.

Table 8. Digital Output Coding

(VIN+) − (VIN−),

Input Span =

Code 2 V p-p (V)

(VIN+) − (VIN−),

Input Span =

1 V p-p (V)

Digital Output

Offset Binary

(D11 ... D0)

409±

204ꢂ

204ꢁ

0

1.000

0

0.±00

1111 1111 1111

1000 0000 0000

0111 1111 1111

0000 0000 0000

0

When applying the decoupling capacitors to the VREF, REFT,

and REFB pins, use ceramic, low ESR capacitors. These

capacitors should be close to the ADC pins and on the same

layer of the PCB as the AD9229. The recommended capacitor

values and configurations for the AD9229 reference pin can be

found in Figure 42 and Figure 43.

−0.0004ꢂꢂ

−1.00

−0.000244

−0.±000

Timing

Data from each ADC is serialized and provided on a separate

channel. The data rate for each serial stream is equal to 12 bits

times the sample clock rate, with a maximum of 780 bps (12 bits

× 65 MSPS = 780 bps). The lowest typical conversion rate is

10 MSPS.

Table 10. Reference Settings

Resulting

Differential

Span (V p-p)

SENSE

Voltage

Resulting

VREF (V)

Selected Mode

External Reference

AVDD

N/A

2 × external

reference

Two output clocks are provided to assist in capturing data from

the AD9229. The DCO is used to clock the output data and is

equal to six times the sampling clock (CLK) rate. Data is

clocked out of the AD9229 and can be captured on the rising

and falling edges of the DCO that supports double-data rate

(DDR) capturing. The frame clock out (FCO) is used to signal

the start of a new output byte and is equal to the sampling clock

rate. See the timing diagram shown in Figure 2 for more

information.

Internal, 1 V p-p FSR

Programmable

VREF

0.±

1.0

0.2 V to

VREF

0.± × (1 +

R2/R1)

2 × VREF

Internal, 2 V p-p FSR

AGND to

0.2 V

1.0

2.0

Internal Reference Connection

A comparator within the AD9229 detects the potential at the

SENSE pin and configures the reference into four possible states

(summarized in Table 10). If SENSE is grounded, the reference

amplifier switch is connected to the internal resistor divider (see

Figure 42), setting VREF to 1 V. Connecting the SENSE pin to

the VREF pin switches the amplifier output to the SENSE pin,

configuring the internal op amp circuit as a voltage follower and

providing a 0.5 V reference output. If an external resistor

divider is connected as shown in Figure 43, the switch is again

set to the SENSE pin. This puts the reference amplifier in a

noninverting mode and defines the VREF output as

DTP Pin

The digital test pattern (DTP) pin can be enabled for two types

of test patterns, as summarized in Table 9. When the DTP is

tied to AVDD/3, all the ADC channel outputs shift out the

following pattern: 1000 0000 0000. When the DTP is tied to 2 ×

AVDD/3, all the ADC channel outputs shift out the following

pattern: 1010 1010 1010. The FCO and DCO outputs still work

as usual while all channels shift out the test pattern. This

pattern allows the user to perform timing alignment

adjustments between the FCO, DCO, and the output data. For

normal operation, this pin should be tied to AGND.

R2

R1

⎛

⎝

⎞

⎟

⎠

VREF = 0.5× 1 +

⎜

In all reference configurations, REFT and REFB establish their

input span of the ADC core. The analog input full-scale range

of the ADC equals twice the voltage at the reference pin for

either an internal or an external reference configuration.

Rev. B | Page 21 of 40

AD9229

External Reference Operation

VIN+

VIN–

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 45 shows the typical drift characteristics of the

internal reference.

REFT

0.1μF

REFB

+

ADC

CORE

10μF

0.10

0.08

0.06

0.04

0.1μF

VREF

0.1μF

10μF

0.5V

SELECT

LOGIC

SENSE

VREF = 0.5V

0.02

0

–0.02

–0.04

VREF = 1.0V

Figure 42. Internal Reference Configuration

–0.06

–0.08

–0.10

VIN+

VIN–

–40

–25

–10

5

20

35

50

65

80

REFT

TEMPERATURE (°C)

0.1μF

REFB

Figure 45. Typical VREF Drift

+

ADC

CORE

10μF

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. The external

reference is loaded with an equivalent 7 kΩ load. An internal

reference buffer generates the positive and negative full-scale

references, REFT and REFB, for the ADC core. Therefore, the

external reference must be limited to a maximum of 1 V.

0.1μF

VREF

+

10μF

0.1μF

0.5V

SELECT

LOGIC

R2

SENSE

R1

Power and Ground Recommendations

When connecting power to the AD9229, it is recommended

that two separate 3.0 V supplies be used: one for analog

(AVDD) and one for digital (DRVDD). If only one supply is

available, it should be routed to the AVDD first and tapped off

and isolated with a ferrite bead or filter choke with decoupling

capacitors proceeding. The user can employ several different

decoupling capacitors to cover both high and low frequencies.

These should be located close to the point of entry at the PC

board level and close to the parts with minimal trace length.

Figure 43. Programmable Reference Configuration

If the internal reference of the AD9229 is used to drive multiple

converters to improve gain matching, the loading of the refer-

ence by the other converters must be considered. Figure 44

depicts how the internal reference voltage is affected by loading.

0.05

A single PC board ground plane should be sufficient when

using the AD9229. With proper decoupling and smart parti-

tioning of the PC board’s analog, digital, and clock sections,

optimum performance is easily achieved.

0

–0.05

VREF = 0.5V

–0.10

–0.15

–0.20

VREF = 1.0V

–0.25

–0.30

–0.35

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

I

(mA)

LOAD

Figure 44. VREF Accuracy vs. Load

Rev. B | Page 22 of 40

AD9229

SILKSCREEN PARTITION

PIN 1 INDICATOR

Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance of the AD9229. A

continuous exposed copper plane on the PCB should mate to

the AD9229 exposed paddle, Pin 0. The copper plane should

have several vias to achieve the lowest possible resistive thermal

path for heat dissipation to flow through the bottom of the PCB.

These vias should be solder or epoxy filled (plugged).

Figure 46. Typical PCB Layout

To maximize the solder coverage and adhesion between the

ADC and PCB, overlay a silkscreen to partition the continuous

copper plane on the PCB into several uniform sections. This

provides several tie points between the two during the reflow

process. Using one continuous plane with no silkscreen

partitions only guarantees one tie point between the ADC and

PCB. See Figure 46 for a PCB layout example. For detailed

information on packaging and the PCB layout of chip scale

packages, visit www.analog.com.

Rev. B | Page 23 of 40

AD9229

EVALUATION BOARD

power supply. This enables the user to individually bias each

section of the board. Use P501 to connect a different supply for

each section. At least one 3.0 V supply is needed with a 1 A

current capability for AVDD_DUT and DRVDD_DUT;

however, it is recommended that separate supplies be used for

both analog and digital. To operate the evaluation board using

the VGA option, a separate 5.0 V analog supply is needed in

addition to the other 3.0 V supplies. The 5.0 V supply, or

AVDD_VGA, should have a 1 A current capability as well.

The AD9229 evaluation board provides all of the support cir-

cuitry required to operate the ADC in its various modes and

configurations. The converter can be driven differentially

through a transformer (default) or through the AD8332 driver.

The ADC can also be driven in a single-ended fashion. Separate

power pins are provided to isolate the DUT from the AD8332

drive circuitry. Each input configuration can be selected by

proper connection of various jumpers (see Figure 48 to Figure 52).

Figure 47 shows the typical bench characterization setup used

to evaluate the ac performance of the AD9229. It is critical that

the signal sources used for the analog input and clock have very

low phase noise (<1 ps rms jitter) to realize the ultimate

performance of the converter. Proper filtering of the analog

input signal to remove harmonics and lower the integrated or

broadband noise at the input is also necessary to achieve the

specified noise performance.

INPUT SIGNALS

When connecting the clock and analog source, use clean signal

generators with low phase noise, such as Rohde & Schwarz SMHU

or HP8644 signal generators or the equivalent. Use 1 m long,

shielded, RG-58, 50 Ω coaxial cable for making connections to

the evaluation board. Dial in the desired frequency and amplitude

within the ADC’s specifications tables. Typically, most ADI

evaluation boards can accept a ~2.8 V p-p or 13 dBm sine wave

input for the clock. When connecting the analog input source, it

is recommended to use a multipole, narrow-band band-pass

filter with 50 Ω terminations. ADI uses TTE, Allen Avionics,

and K&L types of band-pass filters. The filter should be

connected directly to the evaluation board if possible.

See Figure 47 to Figure 57 for complete schematics and layout

plots that demonstrate the routing and grounding techniques

that should be applied at the system level.

POWER SUPPLIES

This evaluation board comes with a wall mountable switching

power supply that provides a 6 V, 2 A maximum output. Simply

connect the supply to the rated 100 V to 240 V ac wall outlet at

47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack

that connects to the PCB at P503. Once on the PC board, the

6 V supply is fused and conditioned before connecting to three

low dropout linear regulators that supply the proper bias to each

of the various sections on the board.

OUTPUT SIGNALS

The default setup uses the HSC-ADC-FPGA high speed

deserialization board, which deserializes the digital output data

and converts it to parallel CMOS. These two channels interface

directly with ADI’s standard dual-channel FIFO data capture

board (HSC-ADC-EVALA-DC). Two of the four channels can

then be evaluated at the same time. For more information on

channel settings on these boards and their optional settings,

visit www.analog.com/FIFO.

When operating the evaluation board in a nondefault condition,

L504 to L506 can be removed to disconnect the switching

WALL OUTLET

100V TO 240V AC

47Hz TO 63Hz

6V DC

2Amax

5.0V

3.0V

–

+

–

+

–

+

SWITCHING

POWER

SUPPLY

HSC-ADC-FPGA

HIGH SPEED

DESERIALIZATION

BOARD

HSC-ADC-EVALA-DC

FIFO DATA

PC

RUNNING

ADC

CAPTURE

BOARD

ROHDE & SCHWARZ,

ANALYZER

SMHU,

2V p-p SIGNAL

SYNTHESIZER

BAND-PASS

FILTER

XFMR

INPUT

CHA–CHD

12-BIT

SERIAL

LVDS

2 CH

12-BIT

PARALLEL

CMOS

AD9229

USB

CONNECTION

EVALUATION BOARD

ROHDE & SCHWARZ,

SMHU,

CLK

2V p-p SIGNAL

SYNTHESIZER

Figure 47. Evaluation Board Connections

Rev. B | Page 24 of 40

AD9229

DEFAULT OPERATION AND JUMPER SELECTION

SETTINGS

•

DTP: To enable one of the two digital test patterns on

digital outputs of the ADC, use JP202. If Pins 2 and 3 on

JP202 are tied together (1.0 V source), this enables test

pattern 1000 0000 0000. If Pins 1 and 2 on JP202 are tied

together (2.0 V source), this enables test pattern 1010 1010

1010. See the DTP Pin section for more details.

The following is a list of the default and optional settings or

modes allowed on the AD9229 Rev C evaluation board.

•

POWER: Connect the switching power supply that is

supplied in the evaluation kit between a rated 100 V to

240 V ac wall outlet at 47 Hz to 63 Hz and P503.

•

LVDSBIAS: To change the level of the LVDS output level

swing, simply change the value of R204. Other recom-

mended values can be found in the Digital Outputs

section.

AIN: The evaluation board is set up for a transformer

coupled analog input with optimum 50 Ω impedance

matching out to 400 MHz. For more bandwidth response,

the 2.2 pF differential capacitor across the analog inputs

could be changed or removed. The common mode of the

analog inputs is developed from the center tap of the

transformer or AVDD_DUT/2.

D+, D–: If an alternate data capture method to the setup

described in Figure 47 is used, optional receiver

terminations, R205 to R210, can be installed next to the

high speed backplane connector.

ALTERNATE ANALOG INPUT DRIVE

CONFIGURATION

•

VREF: VREF is set to 1.0 V by tying the SENSE pin to

ground, R224. This causes the ADC to operate in 2.0 V p-p

full-scale range. A number of other VREF options are

available on the evaluation board, including 1.0 V p-p full-

scale range, a variable range that the user can set by

choosing R219 and R220 as well as a separate external

reference option using the ADR510 or ADR520. Simply

populate R218 and R222 and remove C208. To use these

optional VREF modes, switch the jumper setting on R221

to R224. Proper use of the VREF options is noted in the

Voltage Reference section.

The following is a brief description of the alternate analog input

drive configuration using the AD8332 dual VGA. This parti-

cular drive option may need to be populated, in which case all

the necessary components are listed in Table 11. This table lists

the necessary settings to properly configure the evaluation

board for this option. For more details on the AD8332 dual

VGA, how it works, and its optional pin settings, consult the

AD8332 data sheet.

To configure the analog input to drive the VGA instead of the

default transformer option, the following components need to

be removed and/or changed.

•

CLOCK: The clock input circuitry is derived from a simple

logic circuit using a high speed inverter that adds a very

low amount of jitter to the clock path. The clock input is

50 Ω terminated and ac-coupled to handle sine wave

type inputs. If using an oscillator, two oscillator footprint

options are also available (OSC200-201) to check the

ADC’s performance. J203 and J204 give the user flexibility

in using the enable pin, which is common on most

oscillators.

1. Remove R102, R115, R128, R141, T101, T102, T103, and

T1044 in the default analog input path.

2. Populate R101, R114, R127, and R140 with 0 Ω resistors in

the analog input path.

3. Populate R106, R107, R119, R120, R132, R133, R144, and

R145 with 10 kΩ resistors to provide an input common-

mode level to the analog input.

•

PWDN: To enable the power-down feature, simply short

JP201 to AVDD on the PWDN pin.

4. Populate R105, R113, R118, R124, R131, R137, R151, and

R43 with 0 Ω resistors in the analog input path.

5. Currently L305 to L312 and L405 to L412 are populated

with 0 Ω resistors to allow signal connection. This area

allows the user to design a filter if additional requirements

are necessary.

Rev. B | Page 2± of 40

AD9229

R105

0Ω

DNP

AVDD_DUT

CH_A

VGA INPUT

CONNECTION

R106

1kΩ

R152

DNP

FB102

10

P102

DNP

C101

INH1

R108

R104

T101

0.1μF

33Ω

0Ω

6

1

2

3

VIN_A

A

IN

CHANNEL A

P101

R101

0Ω

DNP

R160

499Ω

C103

DNP

C104

2.2pF

R109

1kΩ

5

4

C102

0.1μF

FB101

10

CM1

A_IN

FB103

10

R110

33Ω

R103

0Ω

R102

65Ω

VIN_A

CH_A

CM1

R111

1kΩ

R113

0Ω

DNP

C105

DNP

R107

1kΩ

DNP

R156

DNP

C106

DNP

AVDD_DUT

R112

1kΩ

C107

0.1μF

VGA INPUT

R118

CONNECTION

0Ω

AVDD_DUT

DNP

INH2

CH_B

R119

1kΩ

R153

DNP

CHANNEL B

P103

R114

0Ω

FB105

10

DNP

FB104 C108

R121

T102

10

0.1μF

33Ω

6

DNP

1

2

3

A_IN

VIN_B

R161

499Ω

C110

DNP

C111

2.2pF

R123

1kΩ

5

4

P104

DNP

C109

0.1μF

R115

65Ω

CM2

R116

0Ω

FB106

10

R122

33Ω

A

IN

R117

VIN_B

CH_B

CM2

R125

1kΩ

0Ω

R124

0Ω

DNP

C112

DNP

R120

1kΩ

DNP

R157

DNP

C113

DNP

AVDD_DUT

R126

1kΩ

C114

0.1μF

ANALOG INPUTS

R131

0Ω

DNP

AVDD_DUT

CH_C

VGA INPUT

CONNECTION

R132

1kΩ

R154

DNP

FB108

10

P106

DNP

C115

INH3

R134

R130

T103

0.1μF

33Ω

0Ω

6

1

2

3

VIN_C

A

IN

CHANNEL C

P105

R127

0Ω

DNP

R162

499Ω

C117

DNP

C118

2.2pF

R135

1kΩ

5

4

C116

0.1μF

FB107

10

CM3

A_IN

FB109

10

R136

33Ω

R129

0Ω

R128

65Ω

VIN_C

CH_C

CM3

R138

1kΩ

R137

0Ω

DNP

C119

DNP

R133

1kΩ

DNP

R158

DNP

C120

DNP

AVDD_DUT

R139

1kΩ

C121

0.1μF

VGA INPUT

R151

CONNECTION

0Ω

AVDD_DUT

DNP

INH4

CH_D

R144

1kΩ

R155

DNP

CHANNEL D

P107

R140

0Ω

FB111

10

DNP

FB110 C122

R146

T104

10

0.1μF

33Ω

6

DNP

1

2

3

A_IN

VIN_D

R163

499Ω

C124

DNP

C125

2.2pF

R148

1kΩ

5

4

P108

DNP

C123

0.1μF

R141

65Ω

CM4

R143

0Ω

FB112

10

R147

33Ω

A

IN

R142

VIN_D

CH_D

CM4

R149

1kΩ

0Ω

R43

0Ω

DNP

C126

DNP

R145

1kΩ

DNP

R159

DNP

C127

DNP

AVDD_DUT

R150

1kΩ

C128

0.1μF

DNP : DO NOT POPULATE

Figure 48. Evaluation Board Schematic, DUT Analog Inputs

Rev. B | Page 2ꢀ of 40

AD9229

U201

36

35

34

33

32

31

30

29

28

27

26

25

1

2

DRGND

DRVDD

DRGND

DRVDD

LVDSBIAS

AGND

GND

DRVDD_DUT

GND

DRVDD_DUT

DIGITAL TEST

PATTERN

ENABLE

AVDD_DUT

3

DNC

DTP

4

GND

AVDD_DUT

R204

4.0kΩ

R201

10kΩ

5

PIN 1 TO PIN 2 = 1010 1010 1010

PIN 2 TO PIN 3 = 1000 0000 0000

AVDD

AGND

PDWN

AVDD

AGND

VIN +A

VIN –A

AGND

AVDD

AVDD_DUT

GND

2

6

1

3

AGND

GND

DUTCLK

JP202

GND

R202

10kΩ

AD9229

7

PWDN ENABLE

JP201

CLK

8

AVDD

AVDD_DUT

GND

AVDD_DUT

GND

AVDD_DUT

R228

10kΩ

R203

10kΩ

9

AGND

10

11

12

VIN +D

VIN –D

AGND

VIN_A

VIN_D

OPTIONAL CLOCK OSCILLATOR

VIN_A

GND

VIN_D

GND

DIGITAL OUTPUTS

P202

GNDCD10

R205

AVDD_DUT

JP203

60

40

59

39

JP204

C10

C9

C8

C7

C6

C5

D10

D9

D8

D7

D6

D5

DCO

FCO

CHA

CHB

CHC

CHD

DNP

GNDCD9

50

49

48

47

46

45

AVDD_VGA

OSC200

EOH

R206

C203

FCO

CHA

CHB

CHC

CHD

1

4

2

3

0.1μF

DNP

GNDCD8

GND

58

38

VCC

OUTPUT

R207

C202

10μF

REFERENCE

DECOUPLING

C209

0.1μF

DNP

GNDCD7

CBELV3I66MT

C204

C201

57

37

R208

0.1μF

OSC201

NC/ENB

DNP

GNDCD6

1

7

8

GND

OUTPUT

56

36

55

35

R209

14

VCC

DNP

GNDCD5

C210

0.1μF

R225

CX3600C-65

DNP

0Ω

R210

DNP

GNDCD4

CLOCK CIRCUIT

U202

AVDD_DUT

54

34

C4

C3

C2

C1

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

D4

D3

D2

D1

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

44

43

42

41

20

19

18

17

16

15

14

13

12

11

R212

GNDCD3

GNDCD2

GNDCD1

GNDAB10

GNDAB9

GNDAB8

GNDAB7

GNDAB6

GNDAB5

GNDAB4

GNDAB3

GNDAB2

GNDAB1

R229

R214

22Ω

U202

P201

ENCODE

1kΩ

0Ω

53

33

1

2

3

4

DUTCLK

INPUT

R230

R211 R231

C205

0.1μF

R213

49.9Ω

AVDD_DUT:14AVDD_DUT:14

GND:7

0Ω

1kΩ

0Ω

DNP

52

32

DNP

51

31

30

10

29

9

EXTERNAL REFERENCE CIRCUIT

28

8

AVDD_DUT

REFERENCE CIRCUIT

VREF SELECT

VREF = 1V = DEFAULT

U203

ADR510/ADR520

27

7

R218

0Ω

VREF_DUT

R215

2kΩ

R221

0Ω

DNP

VREF = 0.5V

TRIM/NC

1NV VOUT

26

6

R222

C206

0.1μF

0Ω

AVDD_DUT

VREF = EXTERNAL

VREF = 0.5V (1 + R219/R220)

VREF = 1V

R219

DNP

25

5

R216

10kΩ

C207

0.1μF

C208

10μF

R223

0Ω

24

4

R217

470kΩ

CW

R220

DNP

R224

0Ω

23

3

VSENSE_DUT

22

2

REMOVE C208 WHEN

USING EXTERNAL VREF

21

1

1469169-1

R205-R210

DNP : DO NOT POPULATE

OPTIONAL OUTPUT

TERMINATIONS

Figure 49. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface

Rev. B | Page 2ꢁ of 40

AD9229

CH_D

CH_C

EXT VG

JP301

1

2

R320

DNP

R321

DNP

POPULATE L305 TO L312

WITH 0Ω RESISTORS OR

DESIGN YOUR OWN FILTER

VG

GND

C303

DNP

C304

DNP

L306

DNP L307

DNP

L308

DNP

L305

DNP

C305

DNP

C306

DNP

L310

DNP L311

DNP

L312

DNP

L309

DNP

R318

DNP

R319

DNP

R302

10kΩ

VG

C310

0.1μF

CW

C307

0.1μF

C309

R303

39kΩ

0.1μF

R305

374Ω

R308

374Ω

C308

0.1μF

R304

187Ω

R306

187Ω

R307

R309

187Ω

AVDD_VGA

187Ω

C311

1nF

C312

0.1μF

R310

100kΩ

AVDD_VGA

DNP

AVDD_VGA

R312

10Ω

U301

AVDD_VGA

25

26

27

28

29

30

31

32

16

ENBV

ENBL

HILO

VCM1

VIN1

RCLMP

R311

10kΩ

DNP

R311

10kΩ

DNP

15

14

13

12

11

10

9

VG

GAIN

MODE

VCM2

VIN2

AD8332

VIP1

VIP2

C313

0.1μF

C314

0.1μF

COM1

LOP1

COM2

LOP2

C315

0.1μF

C316

0.1μF

R314

10kΩ

C317

10μF

C318

0.1μF

R315

274Ω

R316

274Ω

C319

0.1μF

C320

10μF

R317

10kΩ

DNP

C321

18nF

C322

18nF

C325

0.1μF

C326

0.1μF

C323

22pF

C324

22pF

L313

120nH

L314

120nH

C327

0.1μF

C328

0.1μF

DNP : DO NOT POPULATE

INH4

INH3

Figure 50. Evaluation Board Schematic, Optional DUT Analog Input Drive

Rev. B | Page 2ꢂ of 40

AD9229

CH_B

CH_A

R417

R418

POPULATE L405 TO L412

WITH 0Ω RESISTORS OR

DESIGN YOUR OWN FILTER

DNP

C403

DNP

C404

DNP

L406

DNP L407

DNP

L408

DNP

L405

DNP

C405

DNP

C406

DNP

L410

DNP L411

DNP

L412

DNP

L409

DNP

R415

DNP

R416

DNP

C410

0.1μF

C407

0.1μF

C409

0.1μF

R404

374Ω

R407

374Ω

C408

0.1μF

R403

187Ω

R405

187Ω

R406

187Ω

R408

187Ω

C411

1nF

C412

0.1μF

R409

100kΩ

DNP

AVDD_VGA

R402

10kΩ

U401

AVDD_VGA

25

26

27

28

29

30

31

32

16

ENBV

ENBL

HILO

VCM1

VIN1

RCLMP

R401

10kΩ

DNP

R409

10kΩ

DNP

15

14

13

12

11

10

9

VG

GAIN

MODE

VCM2

VIN2

AD8332

VIP1

VIP2

C413

0.1μF

C414

0.1μF

COM1

LOP1

COM2

LOP2

C415

0.1μF

C416

0.1μF

R411

10kΩ

C417

10μF

C418

0.1μF

R412

274Ω

R413

274Ω

C419

0.1μF

C420

10μF

R414

10kΩ

DNP

C423

18nF

C424

18nF

C421

0.1μF

C422

0.1μF

C425

22pF

C426

22pF

L413

120pH

L414

120nH

C427

0.1μF

C428

0.1μF

DNP : DO NOT POPULATE

INH2

INH1

Figure 51. Evaluation Board Schematic, Optional DUT Analog Input Drive Continued

Rev. B | Page 29 of 40

AD9229

D502

SHOT_RECT

3A

POWER SUPPLY INPUT

6V

2A MAX

FER501

F501

CHOKE_COIL DO-214AB

PWR_IN

4

1

3

2

P503

SMDC110F

1

R500

374Ω

D501

S2A_RECT

2A

C501

10μF

CR500

2

3

DO-214AA

U501

ADP33339AKC-3

L504

10μH

3

2

4

PWR_IN

INPUT

OUTPUT1

DUT_AVDD

C502

1μF

C503

1μF

OUTPUT4

GND

1

U502

ADP33339AKC-5

L506

10μH

3

2

4

PWR_IN

VGA_AVDD

INPUT

OUTPUT1

C514

1μF

C515

1μF

OUTPUT4

GND

1

U503

ADP33339AKC-3

INPUT OUTPUT1

L505

10μH

3

2

4

PWR_IN

DUT_DRVDD

C506

C507

1μF

OUTPUT4

1μF

GND

1

OPTIONAL POWER INPUT

P501

DNP

L503

10μH

1

2

3

4

5

6

VGA_AVDD

DUT_AVDD

DUT_DRVDD

P1

P2

P3

P4

P5

P6

AVDD_VGA 5.0V

AVDD_DUT 3.0V

DRVDD_DUT 3.0V

C516

10μF

C517

0.1μF

L502

10μH

C508

10μF

C509

0.1μF

L501

10μH

C504

10μF

C505

0.1μF

DNP : DO NOT POPULATE

Figure 52. Evaluation Board Schematic, Power Supply Inputs

Rev. B | Page 30 of 40

AD9229

DECOUPLING CAPACITORS

DRVDD_DUT

C613

C614

0.1μF

AVDD_VGA

C617

C618

0.1μF

C619

0.1μF

C620

0.1μF

C625

0.1μF

C628

0.1μF

AVDD_DUT

C627

0.1μF

C630

0.1μF

C631

0.1μF

C621

0.1μF

C632

0.1μF

H1 H2

H3 H4

UNUSED GATES

U202

5

6

GND

MOUNTING HOLES

CONNECTED TO GROUND

AVDD_DUT : 14

GND : 7

U202

8

9

AVDD_DUT : 14

GND : 7

U202

10

11

13

AVDD_DUT : 14

GND : 7

U202

12

AVDD_DUT : 14

GND : 7

DNP : DO NOT POPULATE

Figure 53. Evaluation Board Schematic, Decoupling and Miscellaneous

Rev. B | Page 31 of 40

AD9229

Figure 54. Evaluation Board Layout, Primary Side

Rev. B | Page 32 of 40

AD9229

Figure 55. Evaluation Board Layout, Ground Plane

Rev. B | Page 33 of 40

AD9229

Figure 56. Evaluation Board Layout, Power Plane

Rev. B | Page 34 of 40

AD9229

Figure 57. Evaluation Board Layout, Secondary Side (Mirrored Image)

Rev. B | Page 3± of 40

AD9229

Table 11. Evaluation Board Bill of Materials (BOM)

Qnty.

per

Board

Item

REFDES

Device

Pkg.

PCB

402

Value

Mfg.

Mfg. Part Number

1

2

1

±9

AD9229LFCSP_REVC

PCB

0.1 ꢃF, ceramic,

X±R, 10 V, 10% tol

C32ꢁ, C32ꢂ, Cꢀ30, Cꢀ2ꢂ, Capacitor

Cꢀ29, Cꢀ31, Cꢀ32, C101,

C102, C10ꢁ, C10ꢂ, C109,

C114, C11±, C11ꢀ, C121,

C122, C123, C12ꢂ, C201,

C203, C204, C20±, C20ꢀ,

C20ꢁ, C313, C314, C31±,

C312, C31ꢂ, C319, C412,

C31ꢀ, C32±,C32ꢀ, C413,

C414, C41±, C41ꢂ, C419,

C41ꢀ, C421, C422, C42ꢁ,

C42ꢂ, C±0±, C±09, C±1ꢁ,

Cꢀ13, Cꢀ14, Cꢀ1ꢁ, Cꢀ1ꢂ,

Cꢀ19, Cꢀ20, Cꢀ21, Cꢀ2±,

C209, C210, Cꢀ2ꢁ

Panasonic

ECJ-0EB1A104K

3

4

9

C104, C111, C11ꢂ, C12±

Capacitor

402

ꢂ0±

2.2 pF, ceramic,

COG, 0.2± pF tol,

±0 V

10 ꢃF, ꢀ.3 V ±10%

ceramic X±R

Murata

AVX

GRM1±±±C1H2R2GZ01B

0ꢂ0±ꢀD10ꢀKAT2A

C202, C20ꢂ, C31ꢁ, C320, Capacitor

C41ꢁ, C420, C±04, C±0ꢂ,

C±1ꢀ

±

ꢂ

2

4

1

ꢀ

1

C30ꢁ, C30ꢂ, C309, C310, Capacitor

C40ꢁ, C40ꢂ, C409, C410

ꢀ03

402

120ꢀ

ꢀ03

0.1 ꢃF, ceramic,

XꢁR, 1ꢀ V, 10% tol

1000 pF, ceramic,

XꢁR, 2± V, 10% tol

0.01ꢂ ꢃF, ceramic,

XꢁR, 1ꢀ V, 10% tol

22 pF, ceramic,

NPO, ±% tol, ±0 V

10 ꢃF, tantalum,

1ꢀ V, 10% tol

1 ꢃF, ceramic, X±R,

ꢀ.3 V, 10% tol

Kemet

C0ꢀ03C104K4RACTU

C0402C102K3RACTU

0402YC1ꢂ3KAT2A

C0402C220J±GACTU

T491B10ꢀK01ꢀAS

ECJ-1VB0J10±K

ꢀ

C311, C411

Capacitor

Kemet

ꢁ

C321, C322, C423, C424

C323, C324, C42±, C42ꢀ

C±01

AVX

ꢂ

Kemet

9

Kemet

10

11

12

C±02, C±03, C±0ꢀ, C±0ꢁ, Capacitor

C±14, C±1±

Panasonic

CR±00

LED

Green, 4 V, ± m

candela

LNJ314GꢂTRA

D±02

Diode

DO-214AB 3 A, 30 V, SMC

Micro

SK33MSCT

Commercial

Co.

13

14

1

D±01

Diode

Fuse

DO-214AA 2 A, ±0 V, SMC

Micro

Commercial

Co.

S2A

F±01

1210

ꢀ.0 V, 2.2 A trip

current resettable

fuse

Tyco/Raychem NANOSMDC110F-2

1±

1ꢀ

1

FER±01

Ferrite

bead

Ferrite

bead

2020

ꢀ03

10 ꢃH, ± A, ±0 V,

190 Ω @ 100 MHz

10 Ω, test freq

100 MHz, 2±% tol,

±00 mA

Murata

DLW±BSN191SQ2L

BLM1ꢂBA100SN1

12

FB101, FB102, FB103,

FB104, FB10±, FB10ꢀ,

FB10ꢁ, FB10ꢂ, FB109,

FB110, FB111, FB112

1ꢁ

1ꢂ

2

3

JP201, JP301

Connector

2-pin

3-pin

100 mil header

jumper, 2-pin

100 mil header

jumper, 3-pin

Samtec

TSW-102-0ꢁ-G-S

TSW-103-0ꢁ-G-S

JP204, JP203, JP202

Rev. B | Page 3ꢀ of 40

AD9229

Qnty.

per

Board

Item

REFDES

Device

Pkg.

Value

Mfg.

Mfg. Part Number

19

ꢀ

L±01, L±02, L±03, L±04,

L±0±, L±0ꢀ

Ferrite

bead

1210

10 ꢃH, bead core

3.2 × 2.± × 1.ꢀ SMD, ECG

2 A

120 nH, test freq

100 MHz, ±% tol,

1±0 mA

Panasonic -

EXC-CL322±U1

LQG1±HNR12J02B

ERJ-ꢀGEY0R00V

20

21

4

L313, L314, L413, L414

Inductor

Resistor

402

ꢂ0±

Murata

12

L30±, L30ꢀ, L30ꢁ, L30ꢂ,

L309, L310, L40±, L40ꢀ,

L40ꢁ, L40ꢂ, L409, L410,

L311, L312, L411, L412

0 Ω, 1/ꢂ W, ±% tol

Panasonic

22

23

1

±

OSC200

Oscillator

SMT

SMA

Clock oscillator,

ꢀꢀ.ꢀꢀ MHz, 3.3 V

Sidemount SMA

for 0.0ꢀ3" board

thickness

CTS REEVES

CB3LV-3C-ꢀꢀMꢀꢀꢀꢀ-T

142-0ꢁ11-ꢂ21

P201, P101, P103, P10±,

P10ꢁ

Connector

Johnson

Components

24

1

P202

Connector

HEADER

14ꢀ91ꢀ9-1, right

angle 2-pair,

2± mm, header

assembly

Tyco

14ꢀ91ꢀ9-1

2±

2ꢀ

1

P±03

Connector

Resistor

0.1", PCMT

402

RAPCꢁ22, power

supply connector

10 kΩ, 1/1ꢀ W, ±%

tol

Switchcraft

SC11±3

10

R201, R202, R22ꢂ, R203,

R312, R314, R31ꢁ, R402,

R411, R414

Yageo

America

9C04021A1002JLHF3

2ꢁ

2ꢂ

ꢁ

4

R22±, R129, R142, R224

R102, R11±, R12ꢂ, R141

R104, R11ꢀ, R130, R143

R111, R112, R12±, R12ꢀ,

R13ꢂ, R139, R149, R1±0,

R211, R212, R109, R123,

R13±, R14ꢂ

Resistor

402

0 Ω, 1/1ꢀ W, ±% tol

Yageo

America

Panasonic

9C04021A0R00JLHF3

ERJ-2RKFꢀ4R9X

ꢀ4.9 Ω, 1/1ꢀ W,

1% tol

0 Ω, 1/10 W, ±% tol

29

30

4

14

Resistor

ꢀ03

402

Panasonic

ERJ-3GEY0R00V

ERJ-2RKF1001X

1 kΩ, 1/1ꢀ W, 1% tol Panasonic

31

32

33

34

3±

3ꢀ

3ꢁ

ꢂ

4

1

2

R10ꢂ, R110, R121, R122,

R134, R13ꢀ, R14ꢀ, R14ꢁ

R1ꢀ0, R1ꢀ1, R1ꢀ2, R1ꢀ3

Resistor

402

3-lead

33 Ω, 1/1ꢀ W, ±%

tol

499 Ω, 1/1ꢀ W,

1% tol

2 kΩ, 1/1ꢀ W, ±% tol Yageo

America

4.02 kΩ, 1/1ꢀ W,

1% tol

49.9 Ω, 1/1ꢀ W,

0.±% tol

22 Ω, 1/1ꢀ W,

±% tol

10 kΩ, Cermet

trimmer

Yageo

America

Panasonic

9C04021A33R0JLHF3

ERJ-2RKF4990X

R21±

9C04021A2001JLHF3

ERJ-2RKF4021X

R204

Panasonic

R213

Susumu

RR0±10R-49R9-D

9C04021A22R0JLHF3

CT-94W-103

R214

Yageo

America

BC

R21ꢀ,R302

Potentiom

eter

Components

potentiometer,

1ꢂ turn top adjust,

10%, ½ W

3ꢂ

39

40

1

ꢂ

R21ꢁ

R303

Resistor

402

4ꢁ0 kΩ, 1/1ꢀ W,

±% tol

39 kΩ, 1/1ꢀ W,

±% tol

1ꢂꢁ Ω, 1/1ꢀ W,

1% tol

Yageo

America

Susumu

9C04021A4ꢁ03JLHF3

RR0±10P-393-D

R304, R30ꢀ, R30ꢁ, R309,

R403, R40±, R40ꢀ, R40ꢂ,

Panasonic

ERJ-2RKF1ꢂꢁ0X

Rev. B | Page 3ꢁ of 40

AD9229

Qnty.

per

Board

Item

REFDES

Device

Pkg.

Value

Mfg.

Mfg. Part Number

41

4

R30±, R30ꢂ, R404, R40ꢁ,

R±00

R31±, R31ꢀ, R412, R413

Resistor

402

3ꢁ4 Ω, 1/1ꢀ W,

1% tol

2ꢁ4 Ω, 1/1ꢀ W,

1% tol

ADT1-1WT, 1:1

impedance ratio

transformer

Panasonic

ERJ-2RKF3ꢁ40X

42

43

Resistor

402

Panasonic

ERJ-2RKF2ꢁ40X

ADT1-1WT

T101, T102, T103, T104

Transforme CD±42

r

Mini-Circuits

44

4±

2

U±01, U±03

U301, U401

IC

SOT-223

ADP33339AKC-3,

1.± A, 3.0 V LDO

regulator

ADꢂ332ACP,

ultralow noise

precision dual VGA

ADI

ADP33339AKC-3

ADꢂ332ACP

LFCSP, CP-

32

4ꢀ

4ꢁ

1

U±02

U201

IC

SOT-223

LFCSP, CP-

4ꢂ-1

ADP33339AKC-±

AD9229-ꢀ±, quad

12-bit, ꢀ± MSPS

ADI

ADP33339AKC-±

AD9229ABCPZ-ꢀ±

serial LVDS 3 V ADC

4ꢂ

1

U203

IC

SOT-23

ADR±10AR, 1.0 V,

precision low noise

shunt voltage

reference

ꢁ4VHC04MTC, hex

inverter

ADI

ADR±10AR

49

±0

1

4

U202

TSSOP

Fairchild

Richco

ꢁ4VHC04MTC

MP101-104

Part of

assembly

CBSB-14-01A-RT,

ꢁ/ꢂ" height,

CBSB-14-01A-RT

standoffs for circuit

board support

±1

±2

4

MP10±-10ꢂ

MP109-112

Part of

assembly

Part of

assembly

SNT-100-BK-G-H,

100 mil jumpers

±-330ꢂ0ꢂ-3, pin

sockets, closed end

for OSC200

Samtec

AMP

SNT-100-BK-G-H

±-330ꢂ0ꢂ-3

Rev. B | Page 3ꢂ of 40

AD9229

OUTLINE DIMENSIONS

7.10

7.00 SQ

6.90

0.30

0.23

0.18

0.60 MAX

PIN 1

INDICATOR

37

36

48

1

PIN 1

INDICATOR

0.50

REF

6.85

*

5.55

5.50 SQ

5.45

6.75 SQ

6.65

EXPOSED

PAD

(BOTTOM VIEW)

25

24

12

13

0.50

0.40

0.30

0.22 MIN

TOP VIEW

5.50 REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.08

0.20 REF

*

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

WITH EXCEPTION TO EXPOSED PAD DIMENSION.

Figure 58. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

7 mm × 7 mm Body, Very Thin Quad

(CP-48-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

–40°C to +ꢂ±°C

Package Description

Package Option

CP-4ꢂ-ꢂ

AD9229ABCPZ-ꢀ±

AD9229ABCPZRLꢁ-ꢀ±

AD9229ABCPZ-±0

AD9229ABCPZRLꢁ-±0

4ꢂ-Lead LFCSP_VQ

¹Z = RoHS Compliant Part.

Rev. B | Page 39 of 40

AD9229

NOTES

registered trademarks are the property of their respective owners.

D04418–0–5/10(B)

Rev. B | Page 40 of 40


型号：	AD9229ABCPZ-65
厂家：	ADI
描述：	Quad, 12-Bit, 50/65 MSPS, Serial, LVDS, 3 V A/D Converter 四通道，12位， 50/65 MSPS ，串行， LVDS ， 3 VA / D转换器转换器模数转换器 PC
文件：	总40页 (文件大小：789K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9229ABCPZ-65 [ADI]

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