AD9236BRU-80EB [ADI]
12-Bit, 80 MSPS, 3V A/D Converter; 12位， 80 MSPS ， 3V A / D转换器
| 型号： | AD9236BRU-80EB |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 80 MSPS, 3V A/D Converter |
| 文件： | 总36页 (文件大小：1883K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 80 MSPS, 3 V A/D Converter
AD9236
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AVDD
DRVDD
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70.4 dBc to Nyquist
AD9236
SFDR = 87.8 dBc to Nyquist
Low power: 366 mW
VIN+
VIN–
8-STAGE
MDAC1
A/D
3
SHA
1 1/2-BIT PIPELINE
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = 0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
4
16
A/D
REFT
REFB
CORRECTION LOGIC
OTR
12
OUTPUT BUFFERS
D11 (MSB)
D0 (LSB)
VREF
APPLICATIONS
SENSE
CLOCK
0.5V
MODE
SELECT
DUTY CYCLE
STABILIZER
High end medical imaging equipment
IF sampling in communications receivers:
WCDMA, CDMA-One, CDMA-2000
Battery-powered instruments
Hand-held scopemeters
REF
SELECT
AGND
CLK
PDWN MODE DGND
03066-0-001
Figure 1. Functional Block Diagram
Low cost digital oscilloscopes
DTV subsystems
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9236 is available in a 28-lead TSSOP and a 32-lead LFCSP
and is specified over the industrial temperature range
(–40°C to +85°C).
GENERAL DESCRIPTION
The AD9236 is a monolithic, single 3 V supply, 12-bit, 80 MSPS
analog-to-digital converter featuring a high performance sam-
ple-and-hold amplifier (SHA) and voltage reference. The
AD9236 uses a multistage differential pipelined architecture
with output error correction logic to provide 12-bit accuracy at
80 MSPS and guarantee no missing codes over the full operat-
ing temperature range.
PRODUCT HIGHLIGHTS
1. The AD9236 operates from a single 3 V power supply and
features a separate digital output driver supply to accommo-
date 2.5 V and 3.3 V logic families.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9236 is
suitable for applications in communications, imaging, and
medical ultrasound.
2. Operating at 80 MSPS, the AD9236 consumes a low 366 mW.
3. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz, and can be configured for
single-ended or differential operation.
4. The AD9236 is pin compatible with the AD9215, AD9235,
and AD9245. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
5. The DCS maintains overall ADC performance over a wide
range of clock pulsewidths.
A single-ended clock input is used to control all internal con-
version cycles. A duty cycle stabilizer (DCS) compensates for
wide variations in the clock duty cycle while maintaining excel-
lent overall ADC performance. The digital output data is
6. The OTR output bit indicates when the signal is beyond the
selected input range.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD9236
TABLE OF CONTENTS
AD9236–DC Specifications ............................................................ 3
Analog Input and Reference Overview ................................... 14
Clock Input Considerations...................................................... 15
Jitter Considerations .................................................................. 16
Power Dissipation and Standby Mode .................................... 16
Digital Outputs ........................................................................... 16
Timing ......................................................................................... 17
Voltage Reference ....................................................................... 17
Internal Reference Connection ................................................ 17
External Reference Operation .................................................. 18
Operational Mode Selection..................................................... 18
Evaluation Board........................................................................ 18
Outline Dimensions....................................................................... 33
Ordering Guide .......................................................................... 33
AD9236–AC Specifications............................................................. 4
AD9236–Digital Specifications....................................................... 5
AD9236–Switching Specifications ................................................. 6
Explanation of Test Levels........................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Definitions of Specifications ........................................................... 8
Pin Configurations and Functional Descriptions ........................ 9
Equivalent Circuits......................................................................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 14
REVISION HISTORY
Revision A
10/03—Data Sheet Changed from REV. 0 to REV. A
Changes to Figure 30 ..................................................................... 15
Changes to Figure 33 ..................................................................... 17
Changes to Figure 40...................................................................... 22
Changes to Figure 49...................................................................... 28
Changes to Figure 50...................................................................... 29
Changes to Table 11........................................................................ 32
Changes to ORDERING GUIDE ................................................ 33
Rev. A | Page 2 of 36
AD9236
AD9236–DC SPECIFICATIONS
Table 1. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference, unless
otherwise noted
AD9236BRU/AD9236BCP
Parameter
Temp
Test Level
Unit
Min
Typ
Max
RESOLUTION
Full
VI
12
Bits
ACCURACY
No Missing Codes
Offset Error1
Gain Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error1
Gain Error
Gain Error1
Full
Full
25°C
Full
Full
Full
VI
VI
V
VI
VI
VI
Guaranteed
0.30
0.10
0.30
0.40
1.30
% FSR
% FSR
% FSR
LSB
4.34
0.65
1.20
0.35
LSB
Full
Full
Full
V
V
V
6
12
18
ppm/°C
ppm/°C
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
VREF = 0.5 V
Full
VI
V
V
2
0.8
1
35
mV
mV
mV
mV
25°C
25°C
25°C
V
0.1
25°C
25°C
V
V
0.55
0.28
LSB rms
LSB rms
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
Full
Full
Full
Full
IV
IV
V
1
2
7
7
V p-p
V p-p
pF
V
kΩ
AVDD
DRVDD
Full
Full
IV
IV
2.7
2.25
3.0
2.5
3.6
3.6
V
V
Supply Current
IAVDD4
Full
25°C
25°C
VI
V
V
122
8
0.01
137
mA
mA
% FSR
IDRVDD4
PSRR
POWER CONSUMPTION
Low Frequency Input4
Standby Power5
25°C
25°C
V
V
366
1.0
mW
mW
1 With a 1.0 V internal reference.
2 Measured at fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.
4 Measured at AC Specifications conditions without output drivers.
5 Measured with a dc input, CLK pin inactive (i.e., set to AVDD or AGND).
Rev. A | Page 3 of 36
AD9236
AD9236–AC SPECIFICATIONS
Table 2. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference,
AIN = –0.5 dBFS, DCS Off, unless otherwise noted
AD9236BRU/AD9236BCP
Parameter
Temp
Test Level
Unit
Min
Typ
Max
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 2.4 MHz
Full
VI
V
V
IV
V
V
68.6
dB
dB
dB
dB
dB
dB
25°C
25°C
Full
25°C
25°C
70.9
70.4
fIN = 40 MHz
fIN = 70 MHz
67.8
70.1
69.0
fIN = 100 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz
Full
VI
V
V
IV
V
V
68.4
67.4
dB
dB
dB
dB
dB
dB
25°C
25°C
Full
25°C
25°C
70.8
70.2
fIN = 40 MHz
fIN = 70 MHz
69.8
68.0
fIN = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
Full
VI
V
V
IV
V
V
11.1
10.9
Bits
Bits
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
11.5
11.4
fIN = 40 MHz
fIN = 70 MHz
11.3
11.0
fIN = 100 MHz
WORST SECOND OR THIRD
fIN = 2.4 MHz
Full
VI
V
V
VI
V
V
–75.6
–73.2
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
–91.3
–87.8
fIN = 40 MHz
fIN = 70 MHz
–81.4
–76.4
fIN = 100 MHz
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
Full
VI
V
V
IV
V
V
75.6
73.2
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
91.3
87.8
fIN = 40 MHz
fIN = 70 MHz
81.4
76.4
fIN = 100 MHz
Rev. A | Page 4 of 36
AD9236
AD9236–DIGITAL SPECIFICATIONS
Table 3. AVDD = 3 V, DRVDD = 2.5 V, 1.0 V External Reference, unless otherwise noted
AD9236BRU/AD9236BCP
Parameter
Temp
Test Level
Unit
Min
Typ
Max
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Full
Full
Full
Full
Full
IV
IV
IV
IV
V
2.0
V
V
µA
µA
pF
0.8
+10
+10
–10
–10
Input Capacitance
2
DIGITAL OUTPUTS (D0–D11, OTR)1
DRVDD = 3.3 V
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOH = 1.6 mA)
Low Level Output Voltage (IOH = 50 µA)
DRVDD = 2.5 V
Full
Full
Full
Full
IV
IV
IV
IV
3.29
3.25
V
V
V
V
0.2
0.05
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOH = 1.6 mA)
Low Level Output Voltage (IOH = 50 µA)
Full
Full
Full
Full
IV
IV
IV
IV
2.49
2.45
V
V
V
V
0.2
0.05
1 Output voltage levels measured with 5 pF load on each output.
Rev. A | Page 5 of 36
AD9236
AD9236–SWITCHING SPECIFICATIONS
Table 4. AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted
AD9236BRU/AD9236BCP
Parameter
Temp
Test Level
Unit
Min
Typ
Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
Full
Full
Full
Full
Full
VI
V
V
V
V
80
MSPS
MSPS
ns
ns
ns
1
12.5
4.0
4.0
CLK Pulsewidth High1
CLK Pulsewidth Low1
DATA OUTPUT PARAMETERS
Output Propagation Delay (tPD)2
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time3
Full
Full
Full
Full
Full
Full
V
V
V
V
V
V
3.5
7
1.0
0.3
7
ns
Cycles
ns
ps rms
ms
OUT OF RANGE RECOVERY TIME
2
Cycles
1 With duty cycle stabilizer (DCS) enabled.
2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
3 Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
N+1
N
N+2
N+8
N–1
N+3
tA
ANALOG
INPUT
N+7
N+4
N+6
N+5
CLK
DATA
OUT
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
tPD = 6.0ns MAX
2.0ns MIN
03066-0-002
Figure 2. Timing Diagram
EXPLANATION OF TEST LEVELS
Test Level Definitions
I
100% production tested.
II
100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
III
IV
V
VI
100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Rev. A | Page 6 of 36
AD9236
ABSOLUTE MAXIMUM RATINGS
Table 5. AD9236 Absolute Maximum Ratings
THERMAL RESISTANCE
Parameter
ELECTRICAL
AVDD
DRVDD
AGND
AVDD
D0–D11
CLK, MODE AGND
VIN+, VIN–
VREF
With Respect to Min Max
Unit
θJA is specified for the worst-case conditions on a 4-layer board
in still air, in accordance with EIA/JESD51-1.
AGND
DGND
DGND
DRVDD
DGND
–0.3 +3.9
–0.3 +3.9
–0.3 +0.3
–3.9 +3.9
–0.3 DRVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
V
V
V
V
V
V
V
V
V
V
V
Table 6. Thermal Resistance
Package Type
Unit
θJA
θJC
RU-28
CP-32
67.7
32.5
°C/W
°C/W
32.71
AGND
AGND
AGND
AGND
AGND
Airflow increases heat dissipation effectively, reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θJA. It is recommended that the exposed paddle be soldered
to the ground plane for the LFCSP package. There is an
increased reliability of the solder joints, and maximum thermal
capability of the package is achieved with the exposed paddle
soldered to the customer board.
SENSE
REFT, REFB
PDWN
ENVIRONMENTAL
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
–65 +125
–40 +85
°C
°C
300
150
°C
°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 7 of 36
AD9236
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)—The analog
input frequency at which the spectral power of the fundamental
frequency (as determined by the FFT analysis) is reduced by 3 dB.
Effective Number of Bits (ENOB)—The effective number of
bits for a sine wave input at a given input frequency can be cal-
culated directly from its measured SINAD using the following
formula:
Aperture Delay (tA)—The delay between the 50% point of the
rising edge of the clock and the instant at which the analog
input is sampled.
(
SINAD −1.76
)
ENOB =
6.02
Signal-to-Noise Ratio (SNR)1 —The ratio of the rms input
signal amplitude to the rms value of the sum of all other spec-
tral components below the Nyquist frequency, excluding the
first six harmonics and dc.
Aperture Uncertainty (Jitter, tJ)—The sample-to-sample varia-
tion in aperture delay.
Integral Nonlinearity (INL)—The deviation of each individual
code from a line drawn from negative full scale through positive
full scale. The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
Spurious Free Dynamic Range (SFDR)1—The difference in dB
between the rms input signal amplitude and the peak spurious
signal. The peak spurious component may or may not be a
harmonic.
Two-Tone SFDR1—The ratio of the rms value of either input
tone to the rms value of the peak spurious component. The
peak spurious component may or may not be an IMD product.
Differential Nonlinearity (DNL, No Missing Codes)—An
ideal ADC exhibits code transitions that are exactly 1 LSB apart.
DNL is the deviation from this ideal value. Guaranteed no miss-
ing codes to 12-bit resolution indicates that all 4096 codes must
be present over all operating ranges.
Clock Pulsewidth and Duty Cycle—Pulsewidth high is the
minimum amount of time that the clock pulse should be left in
the Logic 1 state to achieve rated performance. Pulsewidth low
is the minimum time the clock pulse should be left in the low
state. At a given clock rate, these specifications define an accept-
able clock duty cycle.
Offset Error—The major carry transition should occur for an
analog value 1/2 LSB below VIN+ = VIN–. Offset error is
defined as the deviation of the actual transition from that point.
Minimum Conversion Rate—The clock rate at which the SNR
of the lowest analog signal frequency drops by no more than
3 dB below the guaranteed limit.
Gain Error—The first code transition should occur at an
analog value 1/2 LSB above negative full scale. The last transi-
tion should occur at an analog value 1 1/2 LSB below positive
full scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal difference
between first and last code transitions.
Maximum Conversion Rate—The clock rate at which para-
metric testing is performed.
Output Propagation Delay (tPD)—The delay between the clock
rising edge and the time when all bits are within valid logic
levels.
Temperature Drift—The temperature drift for offset error and
gain error specifies the maximum change from the initial
(25°C) value to the value at TMIN or TMAX
.
Out-of-Range Recovery Time—The time it takes for the ADC
to reacquire the analog input after a transition from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale
Power Supply Rejection Ratio—The change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
Total Harmonic Distortion (THD)1—The ratio of the rms
input signal amplitude to the rms value of the sum of the first
six harmonic components.
1 AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Signal-to-Noise and Distortion (SINAD)1—The ratio of the
rms input signal amplitude to the rms value of the sum of all
other spectral components below the Nyquist frequency, includ-
ing harmonics but excluding dc.
Rev. A | Page 8 of 36
AD9236
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
OTR
MODE
SENSE
VREF
REFB
REFT
AVDD
AGND
VIN+
1
2
3
4
5
6
7
8
9
28 D11 (MSB)
27 D10
26 D9
DNC 1
CLK 2
DNC 3
PDWN 4
DNC 5
DNC 6
24 VREF
23 SENSE
22 MODE
21 OTR
20 D11 (MSB)
19 D10
25 D8
24 DRVDD
23 DGND
22 D7
AD9236
CSP
AD9236
TOP VIEW
TOP VIEW
(Not to Scale)
21 D6
(Not to Scale)
20 D5
(LSB) D0 7
D1 8
18 D9
17 D8
VIN– 10
AGND 11
AVDD 12
CLK 13
19 D4
18 D3
17 D2
16 D1
PDWN 14
15 D0 (LSB)
03066-0-022
03066-0-021
Figure 4. 32-Lead LFCSP
Figure 3. 28-Lead TSSOP
Table 8. Pin Function Descriptions—
32-Lead LFCSP (CP Package)
Table 7. Pin Function Descriptions—
28-Lead TSSOP (RU Package)
Pin No.
Mnemonic
DNC
Description
Pin No.
Mnemonic
OTR
MODE
Description
1, 3, 5, 6
Do Not Connect
1
2
Out-of-Range Indicator
Data Format Select and DCS
Mode Selection
2
4
CLK
PDWN
D0 (LSB) to
D11 (MSB)
Clock Input Pin
Power-Down Function Select
Data Output Bits
7–14,
17–20
3
4
5
6
7, 12
8, 11
9
10
13
14
SENSE
VREF
REFB
REFT
AVDD
AGND
VIN+
VIN–
CLK
PDWN
D0 (LSB) to
D11 (MSB)
Reference Mode Selection
Voltage Reference Input/Output
Differential Reference (–)
Differential Reference (+)
Analog Power Supply
Analog Ground
Analog Input Pin (+)
Analog Input Pin (–)
Clock Input Pin
Power-Down Function Select
Data Output Bits
15
16
21
22
DGND
DRVDD
OTR
Digital Output Ground
Digital Output Driver Supply
Out-of-Range Indicator
Data Format Select and DCS
Mode Selection
MODE
23
24
25
26
27, 32
28, 31
29
SENSE
VREF
REFB
REFT
AVDD
AGND
VIN+
VIN–
Reference Mode Selection
Voltage Reference Input/Output
Differential Reference (–)
Differential Reference (+)
Analog Power Supply
Analog Ground
15–22,
25–28
23
24
DGND
DRVDD
Digital Output Ground
Digital Output Driver Supply
Analog Input Pin (+)
Analog Input Pin (–)
30
Rev. A | Page 9 of 36
AD9236
EQUIVALENT CIRCUITS
AVDD
DRVDD
D11-D0,
OTR
VIN+, VIN–
03600-0-005
03600-0-003
Figure 7. Equivalent Digital Output Circuit
Figure 5. Equivalent Analog Input Circuit
AVDD
AVDD
CLK,
MODE
PDWN
20kΩ
03600-0-004
03600-0-006
Figure 6. Equivalent MODE Input Circuit
Figure 8. Equivalent Digital Input Circuit
Rev. A | Page 10 of 36
AD9236
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, DCS Disabled, TA = 25°C, 2 V p-p Differential Input, AIN = –0.5 dBFS,
VREF = 1.0 V External, unless otherwise noted
0
–10
100
90
80
70
60
50
40
AIN = –0.5dBFS
SNR = 71.0dBc
ENOB = 11.5 BITS
SFDR = 93.6dBc
SFDR (dBFS)
–20
–30
SFDR (dBc)
–40
SFDR = 90dB
–50
REFERENCE LINE
–60
–70
SNR (dBFS)
–80
SNR (dBc)
–90
–100
–110
–120
0
0
0
5
10
15
20
25
30
35
40
40
40
–30
–25
–20
–15
–10
–5
0
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
03066-0-031
03066-0-048
Figure 9. Single Tone 8K FFT @ 2.5 MHz
Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz
0
–10
100
AIN = –0.5dBFS
SFDR (dBFS)
SNR = 70.6dBc
ENOB = 11.4 BITS
SFDR = 87.8dBc
–20
90
–30
SFDR (dBc)
–40
80
SFDR = 90dB
REFERENCE LINE
–50
–60
70
–70
SNR (dBFS)
SNR (dBc)
–80
60
–90
–100
–110
–120
50
40
5
10
15
20
25
30
35
–30
–25
–20
–15
–10
–5
0
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
03066-0-032
03066-0-049
Figure 10. Single Tone 8K FFT @ 39 MHz
Figure 13. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz
0
–10
100
AIN = –0.5dBFS
SNR = 70.1dBc
ENOB = 11.3 BITS
SFDR = 81.9dBc
SFDR (DIFF)
–20
90
–30
–40
SFDR (SE)
80
–50
SNR (DIFF)
–60
–70
70
–80
SNR (SE)
–90
60
–100
–110
–120
50
5
10
15
20
25
30
35
0
20
40
60
80
100
FREQUENCY (MHz)
SAMPLE RATE (MSPS)
03066-0-033
03066-0-042
Figure 11. Single Tone 8K FFT @ 70 MHz
Figure 14. SNR/SFDR vs. Sample Rate @ 10 MHz
Rev. A | Page 11 of 36
AD9236
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
SFDR (dBFS)
AIN = –6.5dBFS
SNR = 71.3dBFS
SFDR = 92.5dBc
100
90
80
70
60
50
40
SFDR (dBc)
SNR (dBFS)
SNR (dBc)
SFDR = 90dB
REFERENCE LINE
–120
0
–30
–27
–24
–21
–18
–15
–12
–9
–6
5
10
15
20
25
30
35
40
INPUT AMPLITUDE (dBFS)
FREQUENCY (MHz)
03066-0-039
03066-0-036
Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz
Figure 15. Two-Tone 8K FFT @ 30 MHz and 31 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
100
AIN = –6.5dBFS
SNR = 71.0dBFS
SFDR = 79.3dBc
SFDR (dBFS)
90
SFDR (dBc)
80
70
SNR (dBFS)
60
SFDR = 90dB
REFERENCE LINE
SNR(dBc)
50
–120
0
40
5
10
15
20
25
30
35
40
–30
–27
–24
–21
–18
–15
–12
–9
–6
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
03066-0-037
03066-0-040
Figure 16. Two-Tone 8K FFT @ 69 MHz and 70 MHz
Figure 19. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
0
1024
2048
3072
4096
0
1024
2048
3072
4096
CODE
CODE
03066-0-038
03066-0-041
Figure 17. Typical INL
Figure 20. Typical DNL
Rev. A | Page 12 of 36
AD9236
72.0
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
100
95
90
85
80
75
70
–40°C
–40°C
+85°C
+25°C
+25°C
+85°C
0
25
50
75
100
125
0
25
50
75
100
125
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
03066-0-045
03066-0-047
Figure 21. SNR vs. Input Frequency
Figure 24. SFDR vs. Input Frequency
95
0
SFDR (DCS ON)
–10
90
85
80
75
70
65
60
55
–20
–30
SFDR (DCS OFF)
–40
–50
SNR (DCS OFF)
–60
–70
–80
–90
SNR (DCS ON)
–100
–110
–120
30
35
40
45
50
55
60
65
70
0
7.68
15.36
FREQUENCY (MHz)
23.04
30.72
DUTY CYCLE (%)
03066-0-046
03066-0-061
Figure 22. SNR/SFDR vs. Clock Duty Cycle
Figure 25. 32K FFT WCDMA Carrier @ FIN =76.8 MHz:
Sample Rate = 61.44 MSPS
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
7.68
15.36
23.04
30.72
FREQUENCY (MHz)
03066-0-060
Figure 23.32K FFT CDMA-2000 Carrier @ FIN = 46.08 MHz:
Sample Rate = 61.44 MSPS
Rev. A | Page 13 of 36
AD9236
THEORY OF OPERATION
The AD9236 architecture consists of a front-end sample-and-
hold amplifier (SHA) followed by a pipelined switched capaci-
tor ADC. The pipelined ADC is divided into three sections,
consisting of a 4-bit first stage followed by eight 1.5-bit stages
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined into a final 12-bit result
in the digital correction logic. The pipelined architecture per-
mits the first stage to operate on a new input sample, while the
remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the clock.
Referring to Figure 27, the clock signal alternately switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s
input; therefore, the precise values are dependant upon the
application. In IF undersampling applications, any shunt capaci-
tors should be reduced or removed. In combination with the
driving source impedance, they would limit the input
bandwidth.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
H
T
T
5pF
5pF
VIN+
VIN–
C
C
PAR
PAR
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output-
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
T
T
H
03066-0-012
Figure 27. Switched-Capacitor SHA Input
ANALOG INPUT AND REFERENCE OVERVIEW
The analog input to the AD9236 is a differential switched
capacitor SHA that has been designed for optimum perform-
ance while processing a differential input signal. The SHA input
can support a wide common-mode range (VCM) and maintain
excellent performance, as shown in Figure 26. An input com-
mon-mode voltage of midsupply minimizes signal-dependant
errors and provides optimum performance.
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, that define the
span of the ADC core. The output common mode of the refer-
ence buffer is set to midsupply, and the REFT and REFB volt-
ages and span are defined as follows:
100
95
SFDR (2.5MHz)
90
85
1
2
1
REFT =
REFB =
AVDD +VREF
( )
SFDR (39MHz)
80
(
AVDD −VREF
)
75
2
SNR (2.5MHz)
Span = 2×
(
REFT − REFB
)
= 2×VREF
70
SNR (39MHz)
65
60
55
50
It can be seen from the equations above that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by defi-
nition, the input span is twice the value of the VREF voltage.
0.5
1.0
1.5
2.0
2.5
3.0
The internal voltage reference can be pin strapped to fixed val-
ues of 0.5 V or 1.0 V, or adjusted within the same range as dis-
cussed in the Internal Reference Connection section. Maximum
SNR performance is achieved with the AD9236 set to the largest
COMMON-MODE LEVEL (V)
03066-0-016
Figure 26. SNR, SFDR vs. Common-Mode Level
Rev. A | Page 14 of 36
AD9236
input span of 2 V p-p. The relative SNR degradation is 3 dB
when changing from 2 V p-p mode to 1 V p-p mode.
AVDD
VIN+
33Ω
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference volt-
age. The minimum and maximum common-mode input levels
are defined as
2V p-p
49.9Ω
10pF
33Ω
AD9236
VIN–
AGND
1kΩ
1kΩ
VREF
0.1µF
VCMMIN
=
03600-0-014
2
Figure 29. Differential Transformer-Coupled Configuration
(
AVDD +VREF
)
VCMMAX
=
2
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
The minimum common-mode input level allows the AD9236 to
accommodate ground referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source may be applied to VIN+ or VIN–.
In this configuration, one input accepts the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9236 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
may degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a deg-
radation in SFDR and distortion performance due to the large
input common-mode swing (see Figure 14). However, if the
source impedances on each input are matched, there should be
little effect on SNR performance. Figure 30 details a typical sin-
gle-ended input configuration.
Differential Input Configurations
1kΩ
AVDD
VIN+
33
Ω
As previously detailed, optimum performance is achieved while
driving the AD9236 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen Key filter
topology to provide band limiting of the input signal.
0.33µF
1k
2V p-p
49.9
Ω
Ω
20pF
33
AD9236
1k
Ω
Ω
Ω
+
VIN–
AGND
10
µF
0.1
µ
F
1k
03600-A-015
Figure 30. Single-Ended Input Configuration
CLOCK INPUT CONSIDERATIONS
1V p-p
49.9Ω
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be sensi-
tive to clock duty cycle. Commonly a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance char-
acteristics. The AD9236 contains a clock duty cycle stabilizer
(DCS) that retimes the nonsampling edge, providing an internal
clock signal with a nominal 50% duty cycle. This allows a wide
range of clock input duty cycles without affecting the perform-
ance of the AD9236. As shown in Figure 22, noise and distor-
tion performance is nearly flat for a 30% to 70% duty cycle with
the DCS on.
499Ω
AVDD
VIN+
33Ω
499Ω
523Ω
20pF
AD8138
499Ω
AD9236
1kΩ
1kΩ
33Ω
VIN–
AGND
0.1µF
03066-0-013
Figure 28. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9236. This is especially true in IF
undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The value of the shunt capacitor is dependent
on the input frequency and source impedance and should be
reduced or removed. An example is shown in Figure 29.
The duty cycle stabilizer uses a delay-locked loop (DLL) to cre-
ate the nonsampling edge. As a result, any changes to the sam-
pling frequency require approximately 100 clock cycles to allow
the DLL to acquire and lock to the new rate.
Rev. A | Page 15 of 36
AD9236
425
400
375
350
325
300
140
120
100
80
JITTER CONSIDERATIONS
ANALOG CURRENT
TOTAL POWER
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input fre-
quency (fINPUT) due only to aperture jitter (tJ) can be calculated
with the following equation:
SNR= 20log
2πfINPUT ×tJ
60
40
In the equation, the rms aperture jitter represents the root-mean
square of all jitter sources, which include the clock input, analog
input signal, and ADC aperture jitter specification. IF under-
sampling applications are particularly sensitive to jitter (see
Figure 31).
20
DIGITAL CURRENT
0
10
20
30
40
50
60
70
80
90
100
SAMPLE RATE (MSPS)
03066-0-044
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9236. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other meth-
ods), it should be retimed by the original clock at the last step.
Figure 32. Power and Current vs. Sample Rate @ 2.5 MHz
Reducing the capacitive load presented to the output drivers
can minimize digital power consumption. The data in Figure 32
was taken with the same operating conditions as the Typical
Performance Characteristics, and with a 5 pF load on each
output driver.
By asserting the PDWN pin high, the AD9236 is placed in
standby mode. In this state, the ADC typically dissipates
1 mW if the CLK and analog inputs are static. During
standby, the output drivers are placed in a high impedance
state. Reasserting the PDWN pin low returns the AD9236
to its normal operational mode.
75
70
0.2ps
65
60
55
50
45
40
MEASURED
SNR
0.5ps
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 µF and 10 µF decoupling capacitors on REFT
and REFB, it takes approximately 1 second to fully discharge the
reference buffer decoupling capacitors and 7 ms to restore full
operation.
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
1
10
100
1000
INPUT FREQUENCY (MHz)
03066-0-043
Figure 31. SNR vs. Input Frequency and Jitter
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 32, the power dissipated by the AD9236 is
proportional to its sample rate. The digital power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The maximum DRVDD current
(IDRVDD) can be calculated as
DIGITAL OUTPUTS
The AD9236 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
IDRVDD = VDRVDD ×CLOAD × fCLK ×N
where N is the number of output bits, 12 in the case of the
AD9236. This maximum current occurs when every output bit
switches on every clock cycle, i.e., a full-scale square wave at the
Nyquist frequency, fCLK/2. In practice, the DRVDD current will
be established by the average number of output bits switching,
which will be determined by the sample rate and the character-
istics of the analog input signal.
As detailed in Table 10, the data format can be selected for
either offset binary or twos complement.
Rev. A | Page 16 of 36
AD9236
TIMING
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
The AD9236 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propaga-
tion delay (tPD) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
VIN+
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9236. These transients can degrade the converter’s dynamic
performance.
VIN–
REFT
0.1µF
+
ADC
0.1µF
REFB
0.1µF
10µF
CORE
The lowest typical conversion rate of the AD9236 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
VREF
0.1µF
+
10µF
VOLTAGE REFERENCE
SELECT
LOGIC
A stable and accurate 0.5 V voltage reference is built into the
AD9236. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9236 using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly. The
various reference modes are summarized in Table 9 and
described in the following sections.
SENSE
0.5V
AD9236
03066-A-017
Figure 33. Internal Reference Configuration
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap (com-
mon-mode voltage).
If the internal reference of the AD9236 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 34
depicts how the internal reference voltage is affected by loading.
INTERNAL REFERENCE CONNECTION
A comparator within the AD9236 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 9. If SENSE is grounded,
the reference amplifier switch is connected to the internal resis-
tor divider (see Figure 33), setting VREF to 1 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a 0.5 V ref-
erence output. If a resistor divider is connected as shown in
Figure 35, the switch is again set to the SENSE pin. This puts the
reference amplifier in a noninverting mode with the VREF out-
put defined as follows:
0.05
0
–0.05
0.5V ERROR (%)
–0.10
1.0V ERROR (%)
–0.15
–0.20
–0.25
R2
R1
VREF = 0.5× 1+
0
0.5
1.0
1.5
LOAD (mA)
2.0
2.5
3.0
03066-0-019
Figure 34. VREF Accuracy vs. Load
Table 9. Reference Configuration Summary
Internal Switch
Position
Resulting Differential
Span (V p-p)
Selected Mode
SENSE Voltage
AVDD
VREF
Resulting VREF (V)
External Reference
Internal Fixed Reference
Programmable Reference
N/A
SENSE
SENSE
N/A
0.5
2 × External Reference
1.0
2 × VREF
0.2 V to VREF
R2
R1
(See Figure 35)
0.5 × 1 +
Internal Fixed Reference
AGND to 0.2 V
Internal Divider
1.0
2.0
Rev. A | Page 17 of 36
AD9236
OPERATIONAL MODE SELECTION
VIN+
VIN–
As discussed earlier, the AD9236 can output data in either offset
binary or twos complement format. There is also a provision for
enabling or disabling the clock duty cycle stabilizer (DCS). The
MODE pin is a multilevel input that controls the data format
and DCS state. The input threshold values and corresponding
mode selections are outlined in Table 10.
REFT
0.1µF
0.1µF
REFB
0.1µF
+
ADC
10µF
CORE
VREF
+
Table 10. Mode Selection
10µF
0.1µF
SELECT
LOGIC
Duty Cycle
R2
MODE Voltage
AVDD
Data Format
Stabilizer
Disabled
Enabled
Enabled
Disabled
SENSE
Twos Complement
Twos Complement
Offset Binary
2/3 AVDD
R1
0.5V
1/3 AVDD
AGND (Default)
Offset Binary
AD9236
03066-0-018
EVALUATION BOARD
Figure 35. Programmable Reference Configuration
The AD9236 evaluation board provides all of the support cir-
cuitry required to operate the ADC in its various modes and
configurations. Complete schematics and layout plots follow
and demonstrate the proper routing and grounding techniques
that should be applied at the system level.
EXTERNAL REFERENCE OPERATION
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift char-
acteristics. When multiple ADCs track one another, a single
reference (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. Figure 36 shows the typi-
cal drift characteristics of the internal reference in both 1.0 V
and 0.5 V modes.
It is critical that signal sources with very low phase noise (< 1 ps
rms jitter) be used to realize the ultimate performance of the
converter. Proper filtering of the input signal, to remove har-
monics and lower the integrated noise at the input, is also nec-
essary to achieve the specified noise performance.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1.0 V.
TSSOP Evaluation Board
Figure 37 shows the typical bench setup used to evaluate the ac
performance of the AD9236. The AD9236 can be driven single-
ended or differentially through an AD8138 driver or a trans-
former. Separate power pins are provided to isolate the DUT
from the support circuitry. Each input configuration can be
selected by proper connection of various jumpers (refer to the
schematics).
1.0
0.9
0.8
0.7
0.6
The AUXCLK input should be selected in applications requiring
the lowest jitter and SNR performance (i.e., IF undersampling
characterization). It allows the user to apply a clock input signal
that is 4× the target sample rate of the AD9236. A low jitter,
differential divide-by-4 counter, the MC100LVEL33D, provides
a 1× clock output that is subsequently returned back to the CLK
input via JP9. For example, a 260 MHz signal (sinusoid) will be
divided down to a 65 MHz signal for clocking the ADC. Note
that R1 must be removed with the AUXCLK interface. Lower
jitter is often achieved with this interface since many RF signal
generators display improved phase noise at higher output fre-
quencies and the slew rate of the sinusoidal output signal is 4×
that of a 1× signal of equal amplitude.
V
= 1.0V
0.5
0.4
0.3
0.2
0.1
0
REF
V
= 0.5V
REF
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
03066-0-011
Figure 36. Typical VREF Drift
Rev. A | Page 18 of 36
AD9236
An alternative differential analog input path using an AD8351
op amp is included in the layout but is not populated in produc-
tion. Designers interested in evaluating the op amp with the
ADC should remove C15, R12, and R3 and populate the op amp
circuit. The passive network between the AD8351 outputs and
the AD9236 allows the user to optimize the frequency response
of the op amp for their application.
LFCSP Evaluation Board
The typical bench setup used to evaluate the ac performance of
the AD9236 is similar to the TSSOP evaluation board connec-
tions (refer to the schematics for connection details). The
AD9236 can be driven single-ended or differentially through a
transformer. Separate power pins are provided to isolate the
DUT from the support circuitry. Each input configuration can
be selected by proper connection of various jumpers (refer to
the schematics).
3V
3V
3V
3V
–
+
–
+
–
+
–
+
AVDD GND DUT GND DUT
DVDD
J1
S4
AVDD
DRVDD
HP8644, 2V p-p
BAND-PASS
FILTER
REFIN
XFMR
INPUT
SIGNAL SYNTHESIZER
DATA
CAPTURE
AND
AD9236
EVALUATION BOARD
PROCESSING
CLOCK
10MHz
S1
HP8644, 2V p-p
DIVIDER
REFOUT
CLOCK
CLOCK SYNTHESIZER
03066-0-024
Figure 37. TSSOP Evaluation Board Connections
Rev. A | Page 19 of 36
AD9236
Figure 38. TSSOP Evaluation Board Schematic, DUT
Rev. A | Page 20 of 36
AD9236
T O C E R J S
N O L E A E
M
G H T R R I A N G A L D E H E E
1N5712
1 2 5 7 1 N
Figure 39. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering
Rev. A | Page 21 of 36
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Figure 40. TSSOP Evaluation Board Schematic, Analog Inputs
Rev. A | Page 22 of 36
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DACLK
DVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
MSB–DB11
DB10
DB19
CLOCK
DVDD
DCOM
NC3
C30
C31
27
26
25
24
23
22
21
20
19
18
17
16
15
0.1µF
0.01µF
C46
C29
0.01µF
0.1µF
DB8
AD9762
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC1
NC2
AVDD
TP18
WHT
S6
COMP2
IOUTA
IOUTB
ACOM
COMP1
FSADJ
REFIO
REFLO
SLEEP
U4
C56
R29
0.01µF
49.9Ω
C55
22pF
C51
0.01µF
R28
R30
49.9Ω
2kΩ
C54
C49
22pF
0.01µF
03066-0-010
Figure 41. TSSOP Evaluation Board Schematic, Optional D/A Converter
03066-0-025
Figure 42. TSSOP Evaluation Board Layout, Primary Side
Rev. A | Page 23 of 36
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03066-0-026
Figure 43. TSSOP Evaluation Board Layout, Secondary Side
03066-0-027
Figure 44. TSSOP Evaluation Board Layout, Ground Plane
Rev. A | Page 24 of 36
AD9236
03066-0-028
Figure 45. TSSOP Evaluation Board Layout, Power Plane
03066-0-029
Figure 46. TSSOP Evaluation Board Layout, Primary Silkscreen
Rev. A | Page 25 of 36
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03066-0-030
Figure 47. TSSOP Evaluation Board Layout, Secondary Silkscreen
Rev. A | Page 26 of 36
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P 2
0 V 5 .
5 V 2 .
P
L
V A M
V D
G N D
5 V 2 .
0 V 3 .
D D V D R
G N D
D D A V
D 8
D 9
D 1 0
D 1
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
8
D 0 7
D N C
6
D N C
5
D 1 1
O T
R
E
N W P D
4
D N C
3
M O D
S E S E N
E F V R
C L K
2
D N C
1
Figure 48. LFCSP Evaluation Board Schematic, Analog Inputs and DUT
Rev. A | Page 27 of 36
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Figure 49. LFCSP Evaluation Board Schematic, Digital Path
Rev. A | Page 28 of 36
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Figure 50. LFCSP Evaluation Board Schematic, Clock Input
Rev. A | Page 29 of 36
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03066-0-055
03066-0-053
Figure 53. LFCSP Evaluation Board Layout, Ground Plane
Figure 51. LFCSP Evaluation Board Layout, Primary Side
03066-0-054
03066-0-056
Figure 52. LFCSP Evaluation Board Layout, Secondary Side
Figure 54. LFCSP Evaluation Board Layout, Power Plane
Rev. A | Page 30 of 36
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03066-0-057
03066-0-058
Figure 55. LFCSP Evaluation Board Layout, Primary Silkscreen
Figure 56. LFCSP Evaluation Board Layout, Secondary Silkscreen
Rev. A | Page 31 of 36
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Table 11. LFCSP Evaluation Board Bill of Materials
Recommended
Package Value Vendor/Part Number
Supplied
by ADI
Item Qty. Omit1 Reference Designator
Device
C1, C5, C7, C8, C9, C11,
C12, C13, C15, C16, C31,
C33, C34, C36, C37, C41,
18
1
Chip Capacitor
0603
0.1 µF
C43, C47
C6, C18, C27, C17, C28,
C35, C45, C44
8
C2, C3, C4, C10, C20, C22,
C25, C29
C46, C24
8
2
3
Tantalum Capacitor
Chip Capacitor
TAJD
0603
10 µF
2
C14, C30, C32, C38, C39,
C40, C48, C49
8
0.001 µF
4
5
3
1
C19, C21, C23
C26
Chip Capacitor
Chip Capacitor
0603
0603
10 pF
10 pF
E31, E35, E43, E44, E50,
E51, E52, E53
9
2
1
6
Header
EHOLE
Jumper Blocks
2
E1, E45
J1, J2
L1
7
8
SMA Connector/50 Ω
Inductor
SMA
0603
1
10 nH Coilcraft/0603CS-10NXGBU
Wieland/25.602.2653.0,
z5-530-0625-0
9
P2
Terminal Block
TB6
10
1
5
P12
Header Dual 20-Pin RT Angle HEADER40
Digi-Key S2131-20-ND
R3, R12, R23, R28, RX
11
Chip Resistor
0603
0 Ω
R37, R22, R42, R16, R17,
R27
6
12
13
2
R4, R15
Chip Resistor
Chip Resistor
0603
0603
33 Ω
1 kΩ
R5, R6, R7, R8, R13, R20,
R21, R24, R25, R26, R30,
R31, R32, R36
14
14
15
2
1
R10, R11
R29
Chip Resistor
Chip Resistor
0603
0603
36 Ω
50 Ω
1
R19
Digi-Key
220 Ω
16
2
RP1, RP2
Resistor Pack
ADT1-1WT
R_742
CTS/742C163220JTR
17
18
19
20
21
22
23
24
25
26
27
28
1
1
1
1
1
T1
AWT1-1T
Mini-Circuits
U1
74LVTH162374 CMOS Register TSSOP-48
U4
AD9236BCP ADC (DUT)
74VCX86M
CSP-32
SOIC-14
PCB
Analog Devices, Inc.
Fairchild
X
U5
PCB
AD92XXBCP/PCB
AD8351 Op Amp
MACOM Transformer
Chip Resistor
Analog Devices, Inc.
Analog Devices, Inc.
X
X
1
1
5
3
2
1
1
U3
MSOP-8
T2
ETC1-1-13 1-1 TX MACOM/ETC1-1-13
R9, R1, R2, R38, R39
R18, R14, R35
R40, R41
0603
0603
0603
SELECT
25 Ω
Chip Resistor
Chip Resistor
10 kΩ
1.2 kΩ
100 Ω
R34
Chip Resistor
R33
Chip Resistor
Total 82 34
1 These items are included in the PCB design, but are omitted at assembly.
Rev. A | Page 32 of 36
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OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 57. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28)—Dimensions shown in millimeters
5.00
0.60 MAX
BSC SQ
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
3.25
4.75
TOP
BOTTOM
VIEW
BSC SQ
3.10 SQ
2.95
VIEW
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
12° MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 58. 32-Lead Frame Chip Scale Package [LFCSP] (CP-32-1)—Dimensions shown in millimeters
ORDERING GUIDE
AD9236 Products
AD9236BRU-80
AD9236BRURL7-80
AD9236BRUZ-801
AD9236BRUZRL7-801
AD9236BCP-802
AD9236BCPRL7-802
AD9236BCPZ-801, 2
AD9236BCPZRL7-801, 2
AD9236BRU-80EB
AD9236BCP-80EB2
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
Package Outline
Thin Shrink Small Outline (TSSOP)
Thin Shrink Small Outline (TSSOP)
Thin Shrink Small Outline (TSSOP)
Thin Shrink Small Outline (TSSOP)
Lead Frame Chip Scale (LFCSP)
Lead Frame Chip Scale (LFCSP)
Lead Frame Chip Scale (LFCSP)
Lead Frame Chip Scale (LFCSP)
TSSOP Evaluation Board
RU-28
RU-28
RU-28
RU-28
CP-32-1
CP-32-1
CP-32-1
CP-32-1
LFCSP Evaluation Board
1 Z = Lead Free.
2 It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and the maxi-
mum thermal capability of the package is achieved with the exposed paddle soldered to the customer board.
Rev. A | Page 33 of 36
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NOTES
Rev. A | Page 34 of 36
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NOTES
Rev. A | Page 35 of 36
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NOTES
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and regis-
tered trademarks are the property of their respective owners.
C03066-0-10/03(A)
Rev. A | Page 36 of 36
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