AD9237BCP-20EB [ADI]
12-Bit, 20 MSPS/40 MSPS/65 MSPS 3 V Low Power A/D Converter; 12位， 20 MSPS / 40 MSPS / 65 MSPS， 3 V低功耗A / D转换器
| 型号： | AD9237BCP-20EB |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 20 MSPS/40 MSPS/65 MSPS 3 V Low Power A/D Converter |
| 文件： | 总28页 (文件大小：1013K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 20 MSPS/40 MSPS/65 MSPS
3 V Low Power A/D Converter
AD9237
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Ultralow power
AVDD
DRVDD
85 mW at 20 MSPS
135 mW at 40 MSPS
190 mW at 65 MSPS
SNR = 66 dBc to Nyquist at 65 MSPS
SFDR = 80 dBc to Nyquist at 65 MSPS
DNL = 0.7 LSB
Differential input with 500 MHz bandwidth
Flexible analog input: 1 V p-p to 4 V p-p range
Offset binary, twos complement, or gray code data formats
Output enable pin
VIN+
VIN–
10-STAGE
SHA
1 1/2-BIT
PIPELINE
A/D
MDAC1
4
15
3
REFT
REFB
A/D
CORRECTION LOGIC
12
OE
MODE2
OUTPUT BUFFERS
OTR
D11
D0
AD9237
VREF
2-step power-down
Full power-down and sleep mode
Clock duty cycle stabilizer
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
SENSE
REF
SELECT
0.5V
AGND
CLK
PDWN
MODE
DGND
APPLICATIONS
Figure 1.
Ultrasound and medical imaging
Battery-powered instruments
Hand-held scope meters
Low cost digital oscilloscopes
Low power digital still cameras and copiers
Low power communications
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
1. Evaluation boards available for all speed grades.
The AD9237 is a family of monolithic, single 3 V supply, 12-bit,
20 MSPS/40 MSPS/65 MSPS analog-to-digital converters
(ADC). This family features a high performance sample-and-
hold amplifier (SHA) and voltage reference. The AD9237 uses a
multistage differential pipelined architecture with output error
correction logic to provide 12-bit accuracy at 20 MSPS/
40 MSPS/65 MSPS data rates and guarantees no missing codes
over the full operating temperature range.
2. Operating at 65 MSPS, the AD9237 consumes a low 190 mW
at 65 MSPS, 135 mW at 40 MSPS, and 85 mW at 20 MSPS.
3. Power scaling reduces the operating power further when
running at lower speeds.
4. The AD9237 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
5. The patented SHA input maintains excellent performance
for input frequencies beyond Nyquist and can be configured
for single-ended or differential operation.
6. The AD9237 is optimized for selectable and flexible input
ranges from 1 V p-p to 4 V p-p.
With significant power savings over previously available ADCs,
the AD9237 is suitable for applications in imaging and medical
ultrasound.
Fabricated on an advanced CMOS process, the AD9237 is
available in a 32-lead LFCSP and is specified over the industrial
temperature range (−40°C to +85°C).
7. An output enable pin allows for multiplexing of the outputs.
8. Two-step power-down supports a standby mode in addition
to a power-down mode.
9. The OTR output bit indicates when the signal is beyond the
selected input range.
10. The clock duty cycle stabilizer (DCS) maintains converter
performance over a wide range of clock pulse widths.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD9237
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .......................................................................................9
Equivalent Circuits......................................................................... 10
Typical Performance Characteristics ........................................... 11
Applying the AD9237 .................................................................... 16
Theory of Operation.................................................................. 16
Analog Input and Reference Overview................................... 16
Voltage Reference ....................................................................... 18
Clock Input Considerations...................................................... 19
Power Dissipation, Power Scaling, and Standby Mode......... 19
Digital Outputs ........................................................................... 21
LFCSP Evaluation Board........................................................... 22
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
AC Specifications.......................................................................... 4
Switching Specifications .............................................................. 5
Timing Diagram ............................................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
REVISION HISTORY
10/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD9237
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, −0.5 dBFS input, 1.0 V internal reference, TMIN to TMAX
,
unless otherwise noted.
Table 1.
AD9237BCP-20
Typ Max
AD9237BCP-40
Typ Max
AD9237BCP-65
Typ Max
Parameter
Min
Min
Min
Unit
RESOLUTION
12
12
12
Bits
ACCURACY
No Missing Codes Guaranteed
Offset Error
12
12
12
Bits
1.30
1.ꢀ9
2.10
0.ꢀ9
1.39
1.30
1.ꢀ9
2.10
0.ꢀ9
1.39
1.30
1.ꢀ9
2.29
+1.29
2.00
% FSR
% FSR
LSB
Gain Error1
0.ꢁ0
0.ꢁ0
0.ꢀ0
0.ꢁ9
0.ꢁ0
0.ꢀ0
1.09
0.ꢁ0
0.ꢀ0
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
−1.00
LSB
2
12
2
12
2
12
ppm/°C
ppm/°C
Gain Error1
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.9 V Mode)
Load Regulation @ 0.9 mA
Reference Input Resistance
INPUT REFERRED NOISE
VREF = 0.9 V
9
29
9
29
9
29
mV
mV
mV
mV
kΩ
0.8
2.9
0.1
0.8
2.9
0.1
0.8
2.9
0.1
ꢁ
ꢁ
ꢁ
1.39
0.ꢁ0
1.39
0.ꢁ0
1.39
0.ꢁ0
LSB rms
LSB rms
VREF = 1.0 V
ANALOG INPUT
Input Span
VREF = 0.9 V; MODE2 = 0 V
VREF = 1.0 V; MODE2 = 0 V
VREF = 0.9 V; MODE2 = AVDD
VREF = 1.0 V; MODE2 = AVDD
Input Capacitance3
POWER SUPPLIES
Supply Voltages
1
2
2
4
1
2
2
4
1
2
2
4
V p-p
V p-p
V p-p
V p-p
pF
ꢁ
ꢁ
ꢁ
AVDD
DRVDD
2.ꢁ
2.29
3.0
2.9
3.6
3.6
2.ꢁ
2.29
3.0
2.9
3.6
3.6
2.ꢁ
2.29
3.0
2.9
3.6
3.6
V
V
Supply Current
IAVDD2
IDRVDD2
30.9
3.0
49.9
4.9
64.9
9.9
mA
mA
PSRR
0.01
0.01
0.01
% FSR
POWER CONSUMPTION
DC Input4
Sine Wave Input2
Power-Down Mode
Standby Power
89
100
1
139
190
1
1ꢀ0
210
1
mW
mW
mW
mW
120
180
2ꢁ0
20
20
20
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2 Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 9 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
4 Measured with dc input at maximum clock rate.
Rev. 0 | Page 3 of 28
AD9237
DIGITAL SPECIFICATIONS
Table 2.
AD9237BCP-20
AD9237BCP-40
AD9237BCP-65
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
2.0
2.0
2.0
V
Low Level Input Voltage
0.8
0.8
0.8
V
High Level Input Current
Low Level Input Current
Input Capacitance
–10
–10
+10
+10
–10
–10
+10
+10
–10
–10
+10
+10
μA
μA
pF
2
2
2
LOGIC OUTPUTS1
DRVDD = 3.3 V
High-Level Output Voltage (IOH = 90 μA)
High-Level Output Voltage (IOH = 0.9 mA)
Low-Level Output Voltage (IOL = 1.6 mA)
Low-Level Output Voltage (IOL = 90 μA)
DRVDD = 2.9 V
3.2ꢀ
3.29
3.2ꢀ
3.29
3.2ꢀ
3.29
V
V
V
V
0.2
0.09
0.2
0.09
0.2
0.09
High-Level Output Voltage (IOH = 90 μA)
High-Level Output Voltage (IOH = 0.9 mA)
Low-Level Output Voltage (IOL = 1.6 mA)
Low-Level Output Voltage (IOL = 90 μA)
2.4ꢀ
2.49
2.4ꢀ
2.49
2.4ꢀ
2.49
V
V
V
V
0.2
0.09
0.2
0.09
0.2
0.09
1 Output voltage levels measured with 9 pF load on each output.
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, AIN = –0.5 dBFS, 1.0 V internal reference, TMIN to TMAX
,
unless otherwise noted.
Table 3.
AD9237BCP-20
AD9237BCP-40
AD9237BCP-65
Parameter
Min
Typ
Max Min
Typ
66.9
66.6
66.3
66.4
66.4
69.8
Max Min
Typ
Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 2.4 MHz
fINPUT = ꢀ.ꢁ MHz
fINPUT = 1ꢀ.6 MHz
fINPUT = 34.2 MHz
66.8
66.6
66.9
dBc
dBc
dBc
dBc
dBc
69.6
69.1
69.3
64.4
64.0
63.9
66.1
69.ꢀ
fINPUT = ꢁ0 MHz
66.0
SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD)
fINPUT = 2.4 MHz
fINPUT = ꢀ.ꢁ MHz
fINPUT = 1ꢀ.6 MHz
fINPUT = 34.2 MHz
66.ꢁ
66.9
66.3
dBc
dBc
dBc
dBc
dBc
69.8
69.2
fINPUT = ꢁ0 MHz
69.6
10.8
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = ꢀ.ꢁ MHz
fINPUT = 1ꢀ.6 MHz
Bits
Bits
Bits
10.ꢁ
fINPUT = 34.2 MHz
10.6
Rev. 0 | Page 4 of 28
AD9237
AD9237BCP-20
AD9237BCP-40
AD9237BCP-65
Parameter
Min
Typ
Max Min
Typ
Max Min
Typ
Max Unit
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fINPUT = 2.4 MHz
fINPUT = ꢀ.ꢁ MHz
fINPUT = 1ꢀ.6 MHz
fINPUT = 34.2 MHz
88.0
8ꢁ.9
83.9
82.4
ꢁꢁ.ꢀ
−83.9
89.9
dBc
dBc
dBc
dBc
dBc
ꢁ2.4
ꢁ2.2
6ꢀ.4
80.1
ꢁ4.ꢀ
fINPUT = ꢁ0 MHz
80.9
WORST HARMONIC (SECOND OR THIRD)
fINPUT = 2.4 MHz
fINPUT = ꢀ.ꢁ MHz
fINPUT = 1ꢀ.6 MHz
fINPUT = 34.2 MHz
−88.0
−ꢁ2.4 −8ꢁ.9
−89.9
dBc
dBc
dBc
dBc
dBc
−ꢁ2.2 −82.4
−ꢁꢁ.ꢀ
−6ꢀ.4 −80.1
−ꢁ4.ꢀ
fINPUT = ꢁ0 MHz
−80.9
WORST OTHER SPUR
fINPUT = 2.4 MHz
fINPUT = ꢀ.ꢁ MHz
fINPUT = 1ꢀ.6 MHz
fINPUT = 34.2 MHz
−ꢀ0
−ꢁ3.4 −ꢀ0
−ꢀ0
−ꢀ0
dBc
dBc
dBc
dBc
dBc
−ꢁ3.1 −ꢀ0
−ꢀ0
−ꢁ2.0 −ꢀ0
−ꢀ0
fINPUT = ꢁ0 MHz
−ꢀ0
SWITCHING SPECIFICATIONS
Table 4.
AD9237BCP-20
AD9237BCP-40
AD9237BCP-65
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
CLK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High1
CLK Pulse Width Low1
20
40
69
MSPS
MSPS
ns
ns
ns
1
1
1
90.0
19.0
19.0
29.0
8.8
8.8
19.4
6.2
6.2
DATA OUTPUT PARAMETERS
2
Output Delay (tPD
)
3.9
8
6
3.9
8
6
3.9
8
6
ns
Cycles
ns
Pipeline Delay (Latency)
Output Enable Time
Output Disable Time
3
3
3
ns
Aperture Delay (tA)
1.0
0.9
3.0
3.0
1
1.0
0.9
3.0
3.0
1
1.0
0.9
3.0
3.0
2
ns
ps rms
ms
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time (Sleep Mode)3
Wake-Up Time (Standby Mode)3
OUT-OF-RANGE RECOVERY TIME
μs
Cycles
1 With duty cycle stabilizer enabled.
2 Output delay is measured from CLK 90% transition to DATA 90% transition, with 9 pF load on each output.
3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
Rev. 0 | Page 9 of 28
AD9237
TIMING DIAGRAM
N+1
tA
N
N+2
N+8
N–1
N+3
ANALOG
INPUT
N+7
N+4
N+5
N+6
CLK
DATA
OUT
N–10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
tPD
Figure 2. Timing Diagram
Rev. 0 | Page 6 of 28
AD9237
ABSOLUTE MAXIMUM RATINGS
Table 5.
With
Respect to
Pin Name
ELECTRICAL
AVDD
DRVDD
AGND
Min
Max
Unit
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AGND
DGND
DGND
DRVDD
DGND
–0.3
–0.3
–0.3
–3.ꢀ
–0.3
+3.ꢀ
+3.ꢀ
+0.3
+3.ꢀ
V
V
V
V
V
AVDD
Digital
DRVDD + 0.3
Outputs, OE
Absolute maximum ratings are limiting values to be applied
individually and beyond which the serviceability of the circuit
may be impaired. Functional operability is not necessarily
implied. Exposure to absolute maximum rating conditions for
an extended period may affect device reliability.
CLK, MODE,
MODE2
VIN+, VIN–
VREF
SENSE
REFB, REFT
AGND
−0.3 AVDD + 0.3
V
AGND
AGND
AGND
AGND
AGND
–0.3
–0.3
–0.3
–0.3
–0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
V
V
V
V
V
PDWN
ENVIRONMENTAL1
Operating Temperature
Junction Temperature
Lead Temperature (10 sec)
Storage Temperature
–40
+89
190
300
°C
°C
°C
°C
–69
+190
1 Typical thermal impedances (32-lead LFCSP), θJA = 32.9°C/W, θJC = 32.ꢁ1°C/W.
These measurements were taken on a 4-layer board in still air, in accordance
with EIA/JESD91-1.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page ꢁ of 28
AD9237
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
MODE2
CLK
OE
PDWN
GC
DNC
D0 (LSB)
D1
1
2
3
4
5
6
7
8
24 VREF
23 SENSE
22 MODE
21 OTR
20 D11 (MSB)
19 D10
PIN 1
INDICATOR
AD9237
TOP VIEW
(Not to Scale)
18 D9
17 D8
DNC = DO NOT CONNECT
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin Number
Mnemonic
MODE2
CLK
OE
PDWN
GC
Description
1
2
3
4
9
6
SHA Gain Select and Power Scaling Control (see Table 8).
Clock Input Pin.
Output Enable Pin (Active Low).
Power-Down Function Selection (see Table ꢀ).
Gray Code Control (Active High).
Do Not Connect.
DNC
ꢁ to 14, 1ꢁ to 20 D0 (LSB) to D11 (MSB)
Data Output Bits.
19
16
DGND
DRVDD
Digital Output Ground.
Digital Output Driver Supply. Must be decoupled to DGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF in parallel with 10 μF.
21
OTR
Out-of-Range Indicator.
22
23
24
29
MODE
SENSE
VREF
REFB
REFT
Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection (see Table 10).
Reference Mode Selection (see Table ꢁ).
Voltage Reference Input/Output (see Table ꢁ).
Differential Reference (−). Must be decoupled to REFT with a minimum 10 μF capacitor.
Differential Reference (+).
26
2ꢁ, 32
AVDD
Analog Power Supply. Must be decoupled to AGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF in parallel with 10 μF.
28, 31
2ꢀ
30
AGND
VIN+
VIN−
Analog Ground.
Analog Input Pin (+).
Analog Input Pin (−).
Rev. 0 | Page 8 of 28
AD9237
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Signal-To-Noise and Distortion (SINAD)1
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
Aperture Delay (tA)
Effective Number of Bits (ENOB)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
The effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD using the following formula:
Aperture Jitter (tJ)
The sample-to-sample variation in aperture delay.
ENOB = (SINADdBFS − 1.76)/6.02
Signal-to-Noise Ratio (SNR)1
The ratio of the rms signal to the rms value of the sum of all
other spectral components below the Nyquist frequency,
excluding the first six harmonics and dc.
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used
as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSBs
beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
Spurious-Free Dynamic Range (SFDR)1
SFDR is the difference in dB between the rms amplitude of the
input signal and the rms value of the peak spurious signal. The
peak spurious signal may not be an harmonic.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes must be present over all operating ranges.
Two-Tone SFDR1
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Offset Error
Clock Pulse Width and Duty Cycle
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN–. Offset error is defined as the
deviation of the actual transition from that point.
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Gain Error
The first code transition should occur at an analog value
½ LSB above negative full scale. The last transition should occur
at an analog value 1½ LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
Output Propagation Delay (tPD)
at TMIN or TMAX
.
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
Power Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum
limit.
Out-of-Range Recovery Time
The time it takes the ADC to reacquire the analog input after a
transition from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
Total Harmonic Distortion (THD)1
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
1 AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. 0 | Page ꢀ of 28
AD9237
EQUIVALENT CIRCUITS
AVDD
DRVDD
VIN+, VIN–
D11–D0,
OTR
Figure 4. Equivalent Analog Input Circuit
Figure 6. Equivalent Digital Output Circuit
MODE,
MODE2,
GC, OE
375Ω
375Ω
CLK,
PDWN
70kΩ
Figure 5. Equivalent MODE, MODE2, GC, OE Input Circuit
Figure 7. Equivalent CLK, PDWN Input Circuit
Rev. 0 | Page 10 of 28
AD9237
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate with DCS disabled, TA = 25°C, 2 V p-p differential input, AIN = –0.5 dBFS,
VREF = 1.0 V internal, FFT length 16 K, unless otherwise noted.
0
90
85
80
75
70
65
60
SNR = 66.9dBc
SFDR = 87.0dBc
SFDR
–20
–40
–60
–80
SNR
–100
–120
0
0
0
2
4
6
8
10
10.0
12.5
15.0
17.5
20.0
FREQUENCY (MHz)
CLOCK FREQUENCY (MSPS)
Figure 8. AD9237-20 10 MHz FFT
Figure 11. AD9237-20 SNR/SFDR vs. Clock Frequency with fIN = 10 MHz
0
–20
90
SNR = 66.8dBc
SFDR = 83.1dBc
85
SFDR
–40
80
–60
75
–80
70
–100
–120
SNR
65
20
2
4
6
8
10
12
14
16
18
20
25
30
35
40
FREQUENCY (MHz)
CLOCK FREQUENCY (MSPS)
Figure 9. AD9237-40 20 MHz FFT
Figure 12. AD9237-40 SNR/SFDR vs. Clock Frequency with fIN = 20 MHz
0
–20
90
SNR = 66.0dBc
SFDR = 78.6dBc
85
SFDR
–40
80
–60
75
–80
70
SNR
–100
–120
65
60
5
10
15
20
25
30 32.5
40
45
50
55
60
65
FREQUENCY (MHz)
CLOCK FREQUENCY (MSPS)
Figure 10. AD9237-65 70 MHz FFT
Figure 13. AD9237-65 SNR/SFDR vs. Clock Frequency with fIN = 35 MHz
Rev. 0 | Page 11 of 28
AD9237
0
90
85
80
75
70
65
60
55
50
SFDR DCS
ENABLED
SNR = 65.6dBc
SFDR = 67.1dBc
–20
SFDR DCS
DISABLED
–40
–60
SNR DCS ENABLED
SNR DCS DISABLED
–80
–100
–120
0
5
10
15
20
25
30 32.5
30
35
40
45
50
55
60
65
70
FREQUENCY (MHz)
DUTY CYCLE (%)
Figure 14. AD9237-65 100 MHz FFT
Figure 17. SNR/SFDR vs. Clock Duty Cycle
90
80
70
60
50
40
30
90
80
70
60
50
40
30
SFDR dBFS 4V p-p
SFDR dBFS 2V p-p
SFDR dBFS 1V p-p
SFDR dBc 2V p-p
SFDR dBFS 2V p-p
SNR dBFS 2V p-p
SNR dBFS 4V p-p
SNR dBFS 2V p-p
SFDR dBc 1V p-p
SNR dBFS 1V p-p
SFDR dBc 4V p-p
SFDR dBc 2V p-p
SNR dBc 1V p-p
SNR dBc 2V p-p
SNR dBc 4V p-p
SNR dBc 2V p-p
–30
–25
–20
–15
–10
–5
0
–30
–25
–20
–15
–10
–5
0
INPUT AMPLITUDE (dBFS)
INPUT AMPLITUDE (dBFS)
Figure 15. AD9237-65 SNR/SFDR vs. Input Amplitude with fIN = 35 MHz
Figure 18. AD9237-65 SNR/SFDR vs. Input Amplitude with fIN = 35 MHz
100
100
SFDR dBFS 2V p-p
SFDR dBFS 2V p-p
90
90
SFDR dBc 2V p-p
80
SFDR dBc 2V p-p
80
SFDR dBFS 1V p-p
SFDR dBFS 1V p-p
SFDR dBc 1V p-p
SFDR dBc 1V p-p
70
70
60
60
SNR dBFS 2V p-p
SNR dBFS 2V p-p
SNR dBFS 1V p-p
SNR dBFS 1V p-p
50
50
40
40
SNR dBc 2V p-p
SNR dBc 2V p-p
SNR dBc 1V p-p
30
SNR dBc 1V p-p
30
–30
–25
–20
–15
–10
–5
0
–30
–25
–20
–15
–10
–5
0
INPUT AMPLITUDE (dBFS)
INPUT AMPLITUDE (dBFS)
Figure 16. AD9237-40 SNR/SFDR vs. Input Amplitude with fIN = 20 MHz
Figure 19. AD9237-20 SNR/SFDR vs. Input Amplitude with fIN = 10 MHz
Rev. 0 | Page 12 of 28
AD9237
0
–20
100
90
80
70
60
50
40
30
SNR = 67.0dBFS
SFDR = 87.8dBFS
SFDR dBFS
SNR dBFS
–40
–60
SFDR dBc
–80
–100
–120
SNR dBc
0
5
10
15
20
25
30 32.5
–30
–25
–20
–15
–10
–6.5
FREQUENCY (MHz)
INPUT AMPLITUDE (AIN)
Figure 20. AD9237-65 Two-Tone FFT, fIN1 = 45 MHz, fIN2 = 46 MHz
Figure 23. AD9237-65 Two-Tone SNR/SFDR , vs. Analog Input with
fIN1 = 45 MHz, fIN2 = 46 MHz
0
100
SNR = 67.2dBFS
SFDR = 88.3dBFS
90
–20
–40
SFDR dBFS
80
SNR dBFS
SFDR dBc
70
60
50
40
30
–60
–80
–100
–120
SNR dBc
0
5
10
15
20
–30
–25
–20
–15
–10
–6.5
FREQUENCY (MHz)
INPUT AMPLITUDE (AIN)
Figure 21. AD9237-40 Two-Tone FFT
fIN1 = 45 MHz, fIN2 = 46 MHz
Figure 24. AD9237-40 Two-Tone SNR/SFDR , vs. Analog Input with
fIN1 = 45 MHz, fIN2 = 46 MHz
0
–20
100
SNR = 66.9dBFS
SFDR = 84.1dBFS
90
SFDR dBFS
80
–40
SNR dBFS
SFDR dBc
70
60
50
40
30
–60
–80
–100
–120
SNR dBc
0
5
10
15
20
25
30
–30
–25
–20
–15
–10
–6.5
FREQUENCY (MHz)
INPUT AMPLITUDE (AIN)
Figure 22. AD9237-65 Two-Tone FFT, fIN1 = 69 MHz, fIN2 = 70 MHz
Figure 25. AD9237-65 Two-Tone SNR/SFDR vs. Analog Input with
fIN1 = 69 MHz, fIN2 = 70 MHz
Rev. 0 | Page 13 of 28
AD9237
0
100
90
80
70
60
50
40
30
SNR = 67.1dBFS
SFDR = 87.3dBFS
–20
SFDR dBFS
–40
SNR dBFS
SFDR dBc
–60
–80
–100
–120
SNR dBc
0
5
10
15
20
–30
–25
–20
–15
–10
–6.5
FREQUENCY (MHz)
INPUT AMPLITUDE (AIN)
Figure 26. AD9237-40 Two-Tone FFT
fIN1 = 69 MHz, fIN2 = 70 MHz
Figure 29. AD9237-40 Two-Tone SNR/SFDR vs. Analog Input with
fIN1 = 69 MHz, fIN2 = 70 MHz
90
85
80
75
70
65
60
55
90
85
SFDR
SFDR
80
75
70
SNR
SNR
65
60
55
0
25
50
75
100
125
0
25
50
75
100
125
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 27. AD9237-65 SNR/SFDR vs. Input Frequency
Figure 30. AD9237-40 SNR/SFDR vs. Input Frequency
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
0
512
1024
1536
2048
2560
3072
3584
4096
0
512
1024
1536
2048
2560
3072
3584
4096
CODE
CODE
Figure 28. Typical INL
Figure 31. Typical DNL
Rev. 0 | Page 14 of 28
AD9237
67.5
67.0
66.5
66.0
65.5
65.0
90
85
80
75
70
65
60
10.83
10.75
10.67
10.59
10.50
AD9237-20
SNR
AD9237-40
AD9237-65
SFDR
–40
–20
0
20
40
60
8085
10
20
30
40
50
60
70
TEMPERATURE (°C)
CLOCK FREQUENCY (MSPS)
Figure 32. AD9237 SINAD/ENOB vs. Clock Frequency with fIN = Nyquist
Figure 33. AD9237-65 SNR/SFDR vs. Temperature with fIN = 32.5MHz
Rev. 0 | Page 19 of 28
AD9237
APPLYING THE AD9237
90
80
70
60
50
40
30
THEORY OF OPERATION
2.5MHz SFDR
The AD9237 uses a calibrated, 11-stage pipeline architecture
with a patented input SHA implemented. Each stage of the
pipeline, excluding the last, consists of a low resolution flash
ADC connected to a switched capacitor digital-to-analog
converter (DAC) and an interstage residue amplifier (MDAC).
The MDAC magnifies the difference between the reconstructed
DAC output and the flash input for the next stage in the
pipeline. One bit of redundancy is used in each stage to facilitate
digital correction of flash errors. The last stage consists of a
flash ADC.
34.2MHz SFDR
2.5MHz SNR
34.2MHz SNR
The pipelined architecture permits the first stage to operate on a
new input sample, while the remaining stages operate on preceding
samples. While the converter captures a new input sample every
clock cycle, it takes eight clock cycles for the conversion to be
fully processed and to appear at the output, as shown in Figure 2.
0
0.5
1.0
1.5
2.0
2.5
3.0
INPUT COMMON-MODE LEVEL (V)
Figure 34. AD9237-65 SNR/SFDR vs. Input Common-Mode Level
In addition, a small shunt capacitor placed across the inputs
provides dynamic charging currents. This passive network
creates a low-pass filter at the ADC’s input; therefore, the
precise values are dependant on the application. In IF under-
sampling applications, the shunt capacitor(s) should be reduced
or removed depending on the input frequency. In combination
with the driving source impedance, the capacitors limit the
input bandwidth.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output-
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing adjustment of
the output voltage swing. During power-down and stand-by
operation, the output buffers go into a high impedance state.
H
The ADC samples the analog input on the rising edge of
the clock. System disturbances just prior to, or immediately
following, the rising edge of the clock and/or excessive clock
jitter can cause the SHA to acquire the wrong input value and
should be minimized.
T
T
T
5pF
5pF
VIN+
VIN–
C
C
PAR
ANALOG INPUT AND REFERENCE OVERVIEW
The analog input to the AD9237 is a differential switched
capacitor SHA that has been designed for optimum
PAR
performance while processing a differential input signal.
The SHA input can support a wide common-mode range
and maintain excellent performance, as shown in Figure 34.
An input common-mode voltage of midsupply minimizes
signal-dependant errors and provides optimum performance.
T
H
Figure 35. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched so that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
Figure 35 shows the clock signal alternately switching the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, that define the
span of the ADC core.
Rev. 0 | Page 16 of 28
AD9237
The output common mode of the reference buffer is set to mid-
supply, and the REFT and REFB voltages and input span are
defined as:
1kΩ
25Ω
AVDD
VIN+
1.2kΩ
1kΩ
0.1μF
0.1μF
49.9Ω
0.1μF
33Ω
+
15pF
33Ω
AD8351
–
2V p-p
AD9237
VIN–
0.1μF
REFT = ½(AVDD + VREF)
REFB = ½(AVDD − VREF)
25Ω
AGND
4 ×
(
REFT − REFB
)
4 × VREF
Span _ Factor
Span =
=
Figure 36. Differential Input Configuration Using the AD8351
Span _ Factor
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9237. This is especially true in IF
undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration, as shown in Figure 37.
The previous equations show that the REFT and REFB voltages
are symmetrical about the midsupply voltage, and the input
span is proportional to the value of the VREF voltage, see Table 7
for more details.
The internal voltage reference can be pin strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within this range as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved with the AD9237
set to an input span of 2 V p-p or greater. The relative SNR
degradation is 3 dB when changing from 2 V p-p mode to
1 V p-p mode.
AVDD
33Ω
VIN+
15pF
AD9237
2V p-p
49.9Ω
33Ω
VIN–
The SHA must be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as:
1kΩ
1kΩ
AGND
0.1μF
Figure 37. Differential Transformer-Coupled Configuration
VCMMIN = VREF/2
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can cause core
saturation, which leads to distortion.
VCMMAX = (AVDD + VREF)/2
The minimum common-mode input level allows the AD9237 to
accommodate ground-referenced inputs.
Single-Ended Input Configuration
Although optimum performance is achieved with a differential
input, a single-ended source can be driven into VIN+ or VIN–.
In this configuration, one input accepts the signal while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal can be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9237 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
may degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies and
in the lower speed grade models (AD9237-40 and AD9237-20).
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, there is
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance. Figure 38 details a typical single-
ended input configuration.
AVDD
1k
Ω
Ω
0.1μF
33
Ω
VIN+
1k
49.9
Ω
15pF
33
Differential Input Configurations
2V p-p
AD9237
VIN–
1k
Ω
Ω
Ω
As previously detailed, optimum performance is achieved while
driving the AD9237 in a differential input configuration. For
baseband applications, the AD8351 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8351 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal. Figure 36
details a typical configuration using the AD8351.
0.1
μ
F
1k
AGND
25Ω
Figure 38. Single-Ended Input Configuration
Rev. 0 | Page 1ꢁ of 28
AD9237
Table 7. Reference Configuration Summary
Selected Mode
SENSE Voltage
Resulting VREF (V)
Span Factor
Resulting Differential Span (V p-p)
4× External Reference
Span_ Factor
External Reference
AVDD
N/A
2
1
2
1
2
Internal Fixed Reference
Programmable Reference
VREF
0.9
1.0 V
4.0 V
0.2 V to VREF
0.9 × (1 + R2/R1)
(See Figure 40)
4×VREF
Span_ Factor
1
2
1
Internal Fixed Reference
AGND to 0.2 V
1.0
2.0 V
1.0 V
VOLTAGE REFERENCE
VIN+
VIN–
A stable and accurate 0.5 V voltage reference is built into
the AD9237. The input range can be adjusted by varying
the reference voltage applied to the AD9237, using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly.
REFT
0.1μF
+
ADC
CORE
10μF
0.1μF
REFB
0.1μF
VREF
+
10μF
0.1μF
0.5V
In all reference configurations, REFT and REFB drive the
A/D conversion core and, in conjunction with the span factor,
establish its input span. The input range of the ADC always
equals four times the voltage at the reference pin divided by
the span factor for either an internal or an external reference.
It is required to decouple REFT to REFB with 0.1 μF and 10 μF
decoupling capacitors, as shown in Figure 39.
SELECT
LOGIC
SENSE
AD9237
Figure 39. Internal Reference Configuration
Internal Reference Connection
VIN+
VIN–
A comparator within the AD9237 detects the potential at
the SENSE pin and configures the reference into one of four
possible states, which are summarized in Table 7. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider, setting VREF to 1 V (see Figure 39).
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected, as shown in Figure 40, then the switch is again set to
the SENSE pin. This puts the reference amplifier in a non-
inverting mode with the VREF output defined as
REFT
0.1μF
0.1μF
+
ADC
10μF
CORE
REFB
0.1μF
VREF
+
10μF
0.1μF
R2
SENSE
0.5V
SELECT
LOGIC
R1
R2
R1
⎛
⎝
⎞
⎟
⎠
VREF = 0.5× 1+
⎜
AD9237
Figure 40. Programmable Reference Configuration
Rev. 0 | Page 18 of 28
AD9237
CLOCK INPUT CONSIDERATIONS
External Reference Operation
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, can be
sensitive to clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics. The AD9237 contains a clock
duty cycle stabilizer (DCS) that retimes the nonsampling, or
falling edge, providing an internal clock signal with a nominal
50% duty cycle. This allows a wide range of clock input duty
cycles without affecting the performance of the AD9237. As
shown in Figure 17, noise and distortion performance are
nearly flat over a 30% range of duty cycle with the DCS enabled.
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. Figure 41 shows the typical drift characteristics
of the internal reference in both 1 V and 0.5 V modes. When
multiple ADCs track one another, a single reference (internal or
external) reduces gain matching errors.
When the SENSE pin is connected to AVDD, the internal
reference is disabled, allowing the use of an external reference.
An internal reference buffer loads the external reference with
an equivalent 7 kΩ load. The internal buffer still generates the
positive and negative full-scale references, REFT and REFB, for
the ADC core. The input span is always four times the value of
the reference voltage divided by the span factor; therefore, the
external reference must be limited to a maximum of 1 V.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 100 clock cycles to
allow the DLL to acquire and lock to the new rate.
0.7
0.6
0.5
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to rms aperture jitter (tJ) can
be calculated by
1V REFERENCE
0.4
⎡
⎢
⎤
⎥
1
SNRDegradation = 20log10
0.3
0.2
2πf
tJ
⎢
⎣
⎥
⎦
INPUT
In this equation, the rms aperture jitter represents the root-
sum-square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
0.5V REFERENCE
0.1
0
–40
–20
0
20
40
60
8085
TEMPERATURE (°C)
The clock input should be treated as an analog signal in
cases where aperture jitter can affect the dynamic range of the
AD9237. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (such as gating, dividing, or other
methods), then it should be retimed by the original clock at the
last step.
Figure 41. Typical VREF Drift
If the internal reference of the AD9237 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 42
shows how the internal reference voltage is affected by loading.
A 2 mA load is the maximum recommended load.
0.05
0
The lowest typical conversion rate of the AD9237 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
–0.05
0.5V ERROR (%)
POWER DISSIPATION, POWER SCALING, AND
STANDBY MODE
–0.10
As shown in Figure 43, the power dissipated by the AD9237 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
1V ERROR (%)
–0.15
–0.20
–0.25
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD (mA)
I
DRVDD =VDRVDD ×CLOAD × fCLK × N
Figure 42. VREF Accuracy vs. Load
where N is 12, the number of output bits.
Rev. 0 | Page 1ꢀ of 28
AD9237
190
170
150
130
110
90
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, fCLK/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the encode rate and the characteristics
of the analog input signal.
AD9237-65
190
170
150
AD9237-40
AD9237-20
70
10
20
30
40
50
60
65
130
SAMPLE RATE (MSPS)
AD9237-65
Figure 44. Total Power vs. Sample Rate with Power Scaling Enabled
110
AD9237-40
90
The MODE2 pin is a multilevel input that controls the span
factor and power scaling modes. The MODE2 pin is internally
pulled down to AGND by a 70 kΩ resistor. The input threshold
and corresponding mode selections are outlined in Table 8.
AD9237-20
70
10
20
30
40
50
60
65
SAMPLE RATE (MSPS)
Table 8. MODE2 Selection
Figure 43. Total Power vs. Sample Rate with fIN = 10 MHz
MODE2 Voltage
Span Factor
Power Scaling
Disabled
Enabled
Enabled
Disabled
AVDD
2/3 AVDD
1/3 AVDD
AGND (Default)
1
1
2
2
For the AD9237-20 speed grade, the digital power consumption
can represent as much as 10% of the total dissipation. Digital
power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in
Figure 43 was taken with a 5 pF load on each output driver.
The PDWN pin is a multilevel input that controls the power
states. The input threshold values and corresponding power
states are outlined in Table 9.
The AD9237 is designed to provide excellent performance with
minimum power. The analog circuitry is optimally biased so
that each speed grade provides excellent performance while
affording reduced power consumption. Each speed grade
dissipates a baseline power at low sample rates that increases
linearly with the clock frequency, as shown in Figure 43.
Table 9. PDWN Selection
PDWN Voltage Power State
Power (mW)
AVDD
1/3 AVDD
Power-Down Mode
Standby Mode
1
20
AGND (Default) Normal Operation
Based on speed grade
The power scaling feature provides an additional power savings
when enabled, as shown in Figure 44. The power scaling mode
cannot be enabled if the clock is varied during operation. This is
because the internal circuitry cannot quickly track a changing
clock, and the part does not have enough power to operate
properly.
By asserting the PDWN pin high, the AD9237 is placed in
power-down mode. In this state, the ADC typically dissipates
1 mW. During power-down, the output drivers are placed in a
high impedance state. Low power dissipation in power-down
mode is achieved by shutting down the reference, reference
buffer, biasing networks, clock, and duty cycle stabilizer
circuitry. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must
be recharged when returning to normal operation.
As a result, the wake-up time is related to the time spent
in power-down mode and shorter standby cycles result in
proportionally shorter wake-up times. With the recommended
0.1 μF and 10 μF decoupling capacitors on REFT and REFB, it
takes approximately 1 sec to fully discharge the reference buffer
decoupling capacitors and 3 ms to restore full operation.
Rev. 0 | Page 20 of 28
AD9237
By asserting the PDWN pin to AVDD/3, the AD9237 is placed
in standby mode. In this state, the ADC typically dissipates
20 mW. The output drivers are placed in a high impedance
state. The reference circuitry is enabled, allowing for a quick
start upon bringing the ADC into normal operating mode.
completed. By logically AND-ing OTR with the MSB and its
complement, overrange high or underrange low conditions can
be detected. Table 11 is a truth table for the overrange/ under-
range circuit in Figure 46, which uses NAND gates. Systems
requiring programmable gain condition of the AD9237 can,
after eight clock cycles, detect an out-of-range condition;
therefore, eliminating gain selection iterations. In addition,
OTR can be used for digital offset and gain calculation.
DIGITAL OUTPUTS
The AD9237 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that can affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
OTR DATA OUTPUTS
OTR
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
+FS – 1 LSB
+FS
–FS + 1/2 LSB
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9237;
these transients can detract from the converter’s dynamic
performance.
0
0
0
0000 0000 0001
0000 0000 0000
0000 0000 0000
As detailed in Table 10, the data format can be selected for
either offset binary, twos complement, or gray code.
–FS
–FS – 1/2 LSB
–FS – 1/2 LSB
Operational Mode Selection
Figure 45. OTR Relation to Input Voltage and Output Data
The AD9237 can output data in either offset binary, twos
complement, or gray code format. There is also a provision
for enabling or disabling the duty cycle stabilizer (DCS).
The MODE pin is a multilevel input that controls the data
format (except for gray code) and DCS state. The MODE pin
is internally pulled down to AGND by a 70 kΩ resistor. The
input threshold values and corresponding mode selections are
outlined in Table 10.
Table 11. Output Data Format
OTR
MSB
Analog Input Is
Within range
Within range
Underrange
Overrange
0
0
1
1
0
1
0
1
The gray code output format is obtained by connecting GC to
AVDD. When the part is in gray code mode, the MODE pin
controls the DCS function only. The GC pin is internally pulled
down to AGND by a 70 kΩ resistor.
MSB
OVER = 1
OTR
MSB
UNDER = 1
Table 10. MODE Selection
MODE Voltage
Data Format
Duty Cycle Stabilizer
Disabled
Enabled
Enabled
Disabled
Figure 46. Overrange/Underrange Logic
AVDD
2/3 AVDD
1/3 AVDD
AGND (Default)
Twos Complement
Twos Complement
Offset Binary
Digital Output Enable Function (OE)
The AD9237 has three-state ability. The OE pin is internally
pulled down to AGND by a 70 kΩ resistor. If the OE pin is low,
the output data drivers are enabled. If the OE pin is high, the
output data drivers are placed in a high impedance state. It is
not intended for rapid access to the data bus. Note that the
OE pin is referenced to the digital supplies (DRVDD) and
should not exceed that voltage.
Offset Binary
Out of Range (OTR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. The OTR pin is a digital
output that is updated along with the data output corresponding
to the particular sampled input voltage. Therefore, the OTR pin
has the same pipeline latency as the digital data. OTR is low
when the analog input voltage is within the analog input range,
and high when the analog input voltage exceeds the input range,
as shown in Figure 45. OTR remains high until the analog input
returns to within the input range and another conversion is
Timing
The AD9237 provides latched data outputs with a pipeline delay
of eight clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
Rev. 0 | Page 21 of 28
AD9237
An alternative differential analog input path using an
AD8351 op amp is included in the layout but is not populated
in production. Designers interested in evaluating the op amp
with the ADC should remove C15, R12, and R3 and populate
the op amp circuit. The passive network between the AD8351
outputs and the AD9237 allows the user to optimize the
frequency response of the op amp for the application.
LFCSP EVALUATION BOARD
The typical bench setup used to evaluate the ac performance of
the AD9237 is shown in Figure 47. The AD9237 can be driven
single-ended or differentially through a transformer. Separate
power pins are provided to isolate the DUT from the support
circuitry. Each input configuration can be selected by proper
connection of various jumpers (refer to the schematics).
3V
2.5V
–
2.5V
5V
+
+
+
+
–
–
–
AVDD GND DRVDD GND VDL
VAMP
P12
J1
HP8644, 2V p-p
SIGNAL SYNTHESIZER
BAND-PASS
FILTER
REFIN
10MHz
ANALOG
IN
DATA
CAPTURE
AND
AD9237
EVALUATION BOARD
PROCESSING
HP8644, 2V p-p
REFOUT CLOCK SYNTHESIZER
CLOCK
DIVIDER
J2
ENCODE
Figure 47. LFCSP Evaluation Board Connections
Rev. 0 | Page 22 of 28
AD9237
P 2
V A M P 0 V 5 .
6
5 V 2 .
V D L
G N
5
4
3
2
1
D
D
D R V D D
0 V 3 .
G N
A V D D 0 V 3 .
D
G N
D
E 4
E 9
G N
Ω 1 k
5
R 4
E 3
E 2
E 8
D 8
D 9
D 1
Ω 1 k
4
D 0
R 4
0
1
D 1
D N C
G C
E 7
D 1
A D 9 2 3 7
U 4
O T R
N
P D W
O E
Ω 1 k
R 4
E
M O D
S E N S E
V R E F
3
K
C L
E 5
2 E
E 6
2 E
M O D
A V D D
M O D
D
G N
6
E 2
E 2
E 2
4
3
E 3
E 3
7
8
2
0
E 3
E 3
Figure 48. LFCSP Evaluation Board Schematic, Analog Inputs, and DUT
Rev. 0 | Page 23 of 28
AD9237
U1
74LVTH162374
HEADER 40
2
4
1
2CLK
2D8
2OE
GND
DR
2
1
3
5
7
9
CLKLAT/DAC
ORX
GND
ORY
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
3
MSB
2Q8
2Q7
4
MSB
6
5
2D7
GND
6
D13X
GND
8
7
GND7
2D6
GND3
2Q6
8
GND
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
D12X
D11X
DRVDD
D10X
D9X
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2D5
2Q5
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VCC2
2D4
VCC1
2Q4
DRVDD
GND
2D3
2Q3
P12
GND4
2D2
GND2
2Q2
GND
D8X
2D1
2Q1
D7X
1D8
1Q8
D6X
1D7
1Q7
D5X
GND5
1D6
GND1
1Q6
GND
GND
D4X
1D5
1Q5
D3X
8
VCC3
1D4
VCC
1Q4
DRVDD
GND
ORY
DRVDD
D2X
7
6
1D3
1Q3
D1X
5
GND6
1D2
GND
1Q2
LSB
GND
4
GND
GND
D0X
3
1D1
1Q1
2
1CLK
1OE
GND
CLKLAT/DAC
1
R38
1kΩ
R39
1kΩ
VAMP
GND
GND
TO USE AMPLIFIER
POWER DOWN
VAMP
PLACE ALL COMPONENTS SHOWN HERE (RIGHT)
EXCEPT R40 OR R41
C44
C24
USE R40 OR R41
0.1μF
10μF
VAMP
GND
REMOVE R12, R3, R18, R42, C6, C18
GND
GND
R41
10kΩ
R40
10kΩ
C45
0.1μF
PWDN
RGP1
INHI
1
2
3
4
5
10 VOCM
U3
AD8351
R14
25Ω
9
8
7
6
VPOS
OPHI
C28
0.1μF
C27
R16
0Ω
AMP IN
0.1μF
AMPINB
AMPIN
AMP
INLO
RPG2
OPLO
COMM
C35
R17
0Ω
C17
0.1μF
R19
50Ω
R35
25Ω
0.1μF
R33
100Ω
GND
R34
1.2kΩ
GND
GND
Figure 49. LFCSP Evaluation Board Schematic, Digital Path
Rev. 0 | Page 24 of 28
AD9237
0 8 2 0 5 4 5 5 -
Figure 50. LFCSP Evaluation Board Schematic, Clock Input
Rev. 0 | Page 29 of 28
AD9237
Figure 51. LFCSP Evaluation Board Layout, Primary Side
Figure 54. LFCSP Evaluation Board Layout, Power Plane
Figure 55. LFCSP Evaluation Board Layout, Primary Silkscreen
Figure 56. LFCSP Evaluation Board Layout, Secondary Silkscreen
Figure 52. LFCSP Evaluation Board Layout, Secondary Side
Figure 53. LFCSP Evaluation Board Layout, Ground Plane
Rev. 0 | Page 26 of 28
AD9237
Table 12. LFCSP Evaluation Board Bill of Materials
Item Qty. Omit1 Reference Designator
Recommended Vendor/
Part Number
Supplied
by ADI
Device
Package
Value
1
18
C1, C9, Cꢁ, C8, Cꢀ, C11, C12,
C13, C19, C16, C31, C33, C34,
C36, C3ꢁ, C41, C43, C4ꢁ
Chip Capacitors
0603
0.1 μF
ꢀ
2
C6, C1ꢁ, C18, C2ꢁ, C28,
C39, C42, C44, C49
2
3
8
8
C2, C3, C4, C10, C20,
C22, C29, C2ꢀ
Tantalum Capacitors
Chip Capacitors
TAJD
0603
10 μF
C24, C46
C14, C30, C32,
0.001 μF
C38, C3ꢀ, C40, C48, C4ꢀ
4
9
1
1
C1ꢀ
Chip Capacitor
Chip Capacitors
0603
0603
19 pF
10 pF
C26
2
C21, C23
6
41
E2 to E36, E43, E44, E90 to E93 Headers
EHOLE
Jumper Blocks
S1031-02-ND
2
4
E1, E49
H1, H2, H3, H4
MTHOLE
SMA
ꢁ
8
ꢀ
2
1
1
J1, J2
L1
SMA Connectors/90 Ω
Inductor
0603
10 nH
0 Ω
Coilcraft/0603CS-10NXGBU
P2
Terminal Block
TB6
Wieland/29.602.2693.0,
z9-930-0629-0
10
11
1
9
P12
Header, Dual
HEADER40
0603
Digi-Key S2131-20-ND
20-Pin RT Angle
R3, R12, R23, R28, Rx
R16, R1ꢁ, R22, R2ꢁ, R3ꢁ, R42
R4, R19
Chip Resistors
6
12
13
2
Chip Resistors
Chip Resistors
0603
0603
33 Ω
1 kΩ
1ꢀ
R9 to R8, R13, R20, R21,
R24 to R26, R30 to R32, R36,
R43 to R4ꢁ
2
1
R38, R3ꢀ
R10, R11
R2ꢀ
14
19
2
1
Chip Resistors
Chip Resistors
0603
0603
36 Ω
90 Ω
R1ꢀ
16
2
RP1, RP2
Resistor Pack
ADT1-1WT
R_ꢁ42
220 Ω
Digi-Key
CTS/ꢁ42C163220JTR
1ꢁ
18
1
1
T1
AWT1-1T
TSSOP-48
Mini-Circuits
U1
ꢁ4LVTH1623ꢁ4
CMOS Register
1ꢀ
20
21
22
23
1
1
1
U4
U9
PCB
U3
T2
ADꢀ23ꢁBCP ADC (DUT) LFCSP-32
Analog Devices, Inc.
Fairchild
X
ꢁ4VCX86M
SOIC-14
PCB
ADꢀ2XXBCP/PCB
AD8391 Op Amp
Analog Devices, Inc.
Analog Devices, Inc.
X
X
1
1
MSOP-8
M/A-COM
ETC1-1-13 1-1 TX M/A-COM/ETC1-1-13
Transformer
24
29
26
2ꢁ
28
1
3
4
1
1
R2
Chip Resistor
Chip Resistors
Chip Resistors
Chip Resistor
Chip Resistor
0603
0603
0603
SELECT
29 Ω
R14, R18, R39
R1, Rꢀ, R40, R41
R34
10 kΩ
1.2 kΩ
100 Ω
R33
Total 118 40
1 These items are included in the PCB design but are omitted at assembly.
Rev. 0 | Page 2ꢁ of 28
AD9237
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
–40°C to +89°C
–40°C to +89°C
–40°C to +89°C
–40°C to +89°C
–40°C to +89°C
–40°C to +89°C
Package Description
Package Option
CP-32-2
CP-32-2
CP-32-2
CP-32-2
ADꢀ23ꢁBCPZ-201, 2
ADꢀ23ꢁBCPZRLꢁ-201, 2
ADꢀ23ꢁBCPZ-401, 2
ADꢀ23ꢁBCPZRLꢁ-401, 2
ADꢀ23ꢁBCPZ-691, 2
ADꢀ23ꢁBCPZRLꢁ-691, 2
ADꢀ23ꢁBCP-20EB
ADꢀ23ꢁBCP-40EB
ADꢀ23ꢁBCP-69EB
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
CP-32-2
CP-32-2
Evaluation Board
Evaluation Board
1 Z = Pb-free part.
2 It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of
the package is achieved with exposed paddle soldered to the customer board.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05455–0–10/05(0)
Rev. 0 | Page 28 of 28
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