AD9245_技术文档

14-Bit, 80 MSPS, 3 V A/D Converter

AD9245

FUNCTIONAL BLOCK DIAGRAM

FEATURES

AVDD

DRVDD

Single 3 V supply operation (2.7 V to 3.6 V)

SNR = 72.7 dBc to Nyquist

AD9245

SFDR = 87.6 dBc to Nyquist

Low power: 366 mW

VIN+

VIN–

8-STAGE

MDAC1

A/D

3

SHA

1 1/2-BIT PIPELINE

Differential input with 500 MHz bandwidth

On-chip reference and sample-and-hold

DNL = 0.5 LSB

Flexible analog input: 1 V p-p to 2 V p-p range

Offset binary or twos complement data format

Clock duty cycle stabilizer

4

16

A/D

REFT

REFB

CORRECTION LOGIC

OTR

14

OUTPUT BUFFERS

D13 (MSB)

D0 (LSB)

VREF

APPLICATIONS

SENSE

CLOCK

0.5V

MODE

SELECT

DUTY CYCLE

STABILIZER

High end medical imaging equipment

IF sampling in communications receivers:

WCDMA, CDMA-One, CDMA-2000, TDS-CDMA

Battery-powered instruments

REF

SELECT

AGND

CLK

PDWN MODE DGND

03583-B-001

Hand-held scopemeters

Low cost digital oscilloscopes

Figure 1. Functional Block Diagram

Power sensitive military applications

excellent overall ADC performance. The digital output data is

presented in straight binary or twos complement formats. An

out-of-range (OTR) signal indicates an overflow condition that

can be used with the most significant bit to determine low or

high overflow. Fabricated on an advanced CMOS process, the

AD9245 is available in a 32-lead LFCSP and is specified over

the industrial temperature range (–40°C to +85°C).

GENERAL DESCRIPTION

The AD9245 is a monolithic, single 3 V supply, 14-bit, 80 MSPS

analog-to-digital converter featuring a high performance

sample-and-hold amplifier (SHA) and voltage reference. The

AD9245 uses a multistage differential pipelined architecture

with output error correction logic to provide 14-bit accuracy at

80 MSPS and guarantee no missing codes over the full operat-

ing temperature range.

PRODUCT HIGHLIGHTS

1. The AD9245 operates from a single 3 V power supply and

features a separate digital output driver supply to accommo-

date 2.5 V and 3.3 V logic families.

The wide bandwidth, truly differential SHA allows a variety of

user-selectable input ranges and common modes, including

single-ended applications. It is suitable for multiplexed systems

that switch full-scale voltage levels in successive channels, and

for sampling single-channel inputs at frequencies well beyond

the Nyquist rate. Combined with power and cost savings over

previously available analog-to-digital converters, the AD9245 is

suitable for applications in communications, imaging, and

medical ultrasound.

2. Operating at 80 MSPS, the AD9245 consumes a low 366 mW.

3. The patented SHA input maintains excellent performance for

input frequencies up to 100 MHz, and can be configured for

single-ended or differential operation.

4. The AD9245 is pin compatible with the AD9215, AD9235,

and AD9236. This allows a simplified migration from 10 bits

to 14 bits and 20 MSPS to 80 MSPS.

5. The clock DCS maintains overall ADC performance over a

wide range of clock pulsewidths.

A single-ended clock input is used to control all internal con-

version cycles. A duty cycle stabilizer (DCS) compensates for

wide variations in the clock duty cycle while maintaining

6. The OTR output bit indicates when the signal is beyond the

selected input range.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

AD9245

TABLE OF CONTENTS

AD9245–DC Specifications ............................................................ 3

Analog Input and Reference Overview ................................... 14

Clock Input Considerations...................................................... 15

Jitter Considerations .................................................................. 16

Power Dissipation and Standby Mode .................................... 16

Digital Outputs ........................................................................... 16

Timing ......................................................................................... 17

Voltage Reference ....................................................................... 17

Internal Reference Connection ................................................ 17

External Reference Operation .................................................. 18

Operational Mode Selection..................................................... 18

Evaluation Board........................................................................ 18

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

AD9245–AC Specifications............................................................. 4

AD9245–Digital Specifications....................................................... 5

AD9245–Switching Specifications ................................................. 6

Explanation of Test Levels........................................................... 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Definitions of Specifications ........................................................... 8

Pin Configuration and Functional Descriptions.......................... 9

Equivalent Circuits......................................................................... 10

Typical Performance Characteristics ........................................... 11

Theory of Operation ...................................................................... 14

REVISION HISTORY

Revision B

10/03—Data Sheet Changed from REV. A to REV. B

Changes to Figure 33 ..................................................................... 17

5/03—Data Sheet Changed from REV. 0 to REV. A

Changes to Figure 30 .................................................................... 15

Changes to Figure 37 ..................................................................... 19

Changes to Figure 38..................................................................... 20

Changes to Figure 39...................................................................... 21

Changes to Table 10 ....................................................................... 24

Changes to the ORDERING GUIDE........................................... 25

Rev. B | Page 2 of 28

AD9245

AD9245–DC SPECIFICATIONS

Table 1. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference, unless

otherwise noted

AD9245BCP

Parameter

Temp

Test Level

Unit

Min

Typ

Max

RESOLUTION

Full

VI

14

Bits

ACCURACY

No Missing Codes

Offset Error¹

Gain Error

Gain Error¹

Differential Nonlinearity (DNL)²

Integral Nonlinearity (INL)²

TEMPERATURE DRIFT

Offset Error¹

Gain Error

Gain Error¹

Full

25°C

Full

VI

V

VI

Guaranteed

0.30

0.2ꢀ

0.70

0.5

1.2

% FSR

LSB

4.16

1.0

5.15

1.4

LSB

Full

V

10

12

17

ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode)

Load Regulation @ 1.0 mA

Output Voltage Error (0.5 V Mode)

Load Regulation @ 0.5 mA

INPUT REFERRED NOISE

VREF = 0.5 V

Full

VI

V

3

2

6

1

34

mV

25°C

V

25°C

V

1.ꢀ6

1.17

LSB rms

VREF = 1.0 V

ANALOG INPUT

Input Span, VREF = 0.5 V

Input Span, VREF = 1.0 V

Input Capacitance³

REFERENCE INPUT RESISTANCE

POWER SUPPLIES

Supply Voltage

Full

IV

V

1

2

7

V p-p

pF

V

kΩ

AVDD

DRVDD

Full

IV

2.7

2.25

3.0

2.5

3.6

V

Supply Current

IAVDD²

Full

25°C

VI

V

122

9

0.01

13ꢀ

mA

% FSR

IDRVDD²

PSRR

POWER CONSUMPTION

Low Frequency Input⁴

Standby Power⁵

25°C

V

366

1.0

mW

¹With a 1.0 V internal reference.

²Measured at the maximum clock rate, f_IN= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.

³Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.

⁴Measured at AC Specification conditions without output drivers.

⁵Standby power is measured with a dc input, CLK pin inactive (i.e., set to AVDD or AGND).

Rev. B | Page 3 of 2ꢀ

AD9245

AD9245–AC SPECIFICATIONS

Table 2. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference,

AIN = –0.5 dBFS, DCS Off, unless otherwise noted

AD9245BCP

Parameter

Temp

Test Level

Unit

Min

Typ

Max

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 2.4 MHz

Full

VI

V

IV

V

71.1

dB

25°C

Full

25°C

73.3

72.7

f_IN= 40 MHz

f_IN= 70 MHz

70.5

71.7

70.2

f_IN= 100 MHz

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

f_IN= 2.4 MHz

Full

VI

V

IV

V

70.7

69.9

dB

25°C

Full

25°C

73.2

72.5

f_IN= 40 MHz

f_IN= 70 MHz

71.2

69.6

f_IN= 100 MHz

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 2.4 MHz

Full

VI

V

IV

V

11.5

11.3

Bits

25°C

Full

25°C

11.9

11.ꢀ

f_IN= 40 MHz

f_IN= 70 MHz

11.5

11.3

f_IN= 100 MHz

WORST SECOND OR THIRD

f_IN= 2.4 MHz

Full

VI

V

IV

V

–76.5

–75.7

dBc

25°C

Full

25°C

–92.ꢀ

–ꢀ7.6

f_IN= 40 MHz

f_IN= 70 MHz

–ꢀ1.6

–79.0

f_IN= 100 MHz

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_IN= 2.4 MHz

Full

VI

V

IV

V

76.5

75.7

dBc

25°C

Full

25°C

92.ꢀ

ꢀ7.6

f_IN= 40 MHz

f_IN= 70 MHz

ꢀ1.6

79.0

f_IN= 100 MHz

Rev. B | Page 4 of 2ꢀ

AD9245

AD9245–DIGITAL SPECIFICATIONS

Table 3. AVDD = 3 V, DRVDD = 2.5 V, 1.0 V External Reference, unless otherwise noted

AD9245BCP

Typ

Temp

Test Level

Unit

Parameter

Min

Max

LOGIC INPUTS (CLK, PDWN)

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Full

IV

V

2.0

V

µA

pF

0.ꢀ

+10

–10

Input Capacitance

2

DIGITAL OUTPUT BITS (D0–D13, OTR)¹

DRVDD = 3.3 V

High Level Output Voltage (IOH = 50 µA)

High Level Output Voltage (IOH = 0.5 mA)

Low Level Output Voltage (IOH = 1.6 mA)

Low Level Output Voltage (IOH = 50 µA)

DRVDD = 2.5 V

Full

IV

3.29

3.25

V

0.2

0.05

High Level Output Voltage (IOH = 50 µA)

High Level Output Voltage (IOH = 0.5 mA)

Low Level Output Voltage (IOH = 1.6 mA)

Low Level Output Voltage (IOH = 50 µA)

Full

IV

2.49

2.45

V

0.2

0.05

¹Output voltage levels measured with 5 pF load on each output.

Rev. B | Page 5 of 2ꢀ

AD9245

AD9245–SWITCHING SPECIFICATIONS

Table 4. AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted

AD9245BCP

Typ

Parameter

Temp

Test Level

Unit

Min

Max

CLOCK INPUT PARAMETERS

Maximum Conversion Rate

Minimum Conversion Rate

CLK Period

Full

VI

V

ꢀ0

MSPS

ns

1

12.5

4.6

CLK Pulsewidth High¹

CLK Pulsewidth Low¹

DATA OUTPUT PARAMETERS

Output Propagation Delay (t_PD)²

Pipeline Delay (Latency)

Aperture Delay (t_A)

Aperture Uncertainty (Jitter, t_J)

Wake-Up Time³

Full

V

4.2

7

1

0.3

7

ns

Cycles

ns

ps rms

ms

OUT-OF-RANGE RECOVERY TIME

2

Cycles

¹With duty cycle stabilizer (DCS) enabled.

²Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

³Wake-up time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.

N+1

N

N+2

N+8

N–1

N+3

t_A

ANALOG

INPUT

N+7

N+4

N+6

N+5

CLK

DATA

OUT

N–9

N–8

N–7

N–6

N–5

N–4

N–3

N–2

N–1

N

t_PD= 6.0ns MAX

2.0ns MIN

03583-B-002

Figure 2. Timing Diagram

EXPLANATION OF TEST LEVELS

Test Level Definitions

I

100% production tested.

II

100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.

Sample tested only.

Parameter is guaranteed by design and characterization testing.

Parameter is a typical value only.

III

IV

V

VI

100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

Rev. B | Page 6 of 2ꢀ

AD9245

ABSOLUTE MAXIMUM RATINGS

Table 5. AD9245 Absolute Maximum Ratings

THERMAL RESISTANCE

Parameter

ELECTRICAL

AVDD

DRVDD

AGND

AVDD

D0–D13

CLK, MODE AGND

VIN+, VIN–

VREF

With Respect to Min Max

Unit

θ_JAis specified for the worst-case conditions on a 4-layer board

in still air, in accordance with EIA/JESD51-1.

AGND

DGND

DRVDD

DGND

–0.3 +3.9

–0.3 +0.3

–3.9 +3.9

–0.3 DRVDD + 0.3

–0.3 AVDD + 0.3

V

Table 6. Thermal Resistance

Package Type

Unit

θ_JA

θ_JC

CP-32

32.5

32.71

°C/W

Airflow increases heat dissipation, effectively reducing θ_JA.

Also, more metal directly in contact with the package leads

from metal traces, through holes, ground, and power planes

reduces the θ_JA. It is recommended that the exposed paddle be

soldered to the ground plane for the LFCSP package. There is an

increased reliability of the solder joints, and maximum thermal

capability of the package is achieved with the exposed paddle

soldered to the customer board.

AGND

SENSE

REFT, REFB

PDWN

ENVIRONMENTAL

Storage Temperature

Operating Temperature Range

–65 +125

–40 +ꢀ5

°C

Lead Temperature Range

(Soldering 10 sec)

Junction Temperature

300

150

°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. B | Page 7 of 2ꢀ

AD9245

DEFINITIONS OF SPECIFICATIONS

Analog Bandwidth (Full Power Bandwidth)—The analog

input frequency at which the spectral power of the fundamental

frequency (as determined by the FFT analysis) is reduced by 3 dB.

Effective Number of Bits (ENOB)—The effective number of

bits for a sine wave input at a given input frequency can be cal-

culated directly from its measured SINAD using the following

formula:

Aperture Delay (t_A)—The delay between the 50% point of the

rising edge of the clock and the instant at which the analog

input is sampled.

(

SINAD −1.76

)

ENOB =

6.02

Signal-to-Noise Ratio (SNR)¹—The ratio of the rms input

signal amplitude to the rms value of the sum of all other spec-

tral components below the Nyquist frequency, excluding the

first six harmonics and dc.

Aperture Uncertainty (Jitter, t_J)—The sample-to-sample varia-

tion in aperture delay.

Integral Nonlinearity (INL)—The deviation of each individual

code from a line drawn from negative full scale through positive

full scale. The point used as negative full scale occurs ½ LSB

before the first code transition. Positive full scale is defined as a

level 1½ LSB beyond the last code transition. The deviation is

measured from the middle of each particular code to the true

straight line.

Spurious-Free Dynamic Range (SFDR)¹—The difference in dB

between the rms input signal amplitude and the peak spurious

signal. The peak spurious component may or may not be a

harmonic.

Two-Tone SFDR¹—The ratio of the rms value of either input

tone to the rms value of the peak spurious component. The

peak spurious component may or may not be an IMD product.

Differential Nonlinearity (DNL, No Missing Codes)—An

ideal ADC exhibits code transitions that are exactly 1 LSB apart.

DNL is the deviation from this ideal value. Guaranteed no miss-

ing codes to 14-bit resolution indicates that all 16384 codes

must be present over all operating ranges.

Clock Pulsewidth and Duty Cycle—Pulsewidth high is the

minimum amount of time that the clock pulse should be left in

the Logic 1 state to achieve rated performance. Pulsewidth low

is the minimum time the clock pulse should be left in the

Logic 0 state. At a given clock rate, these specifications define an

acceptable clock duty cycle.

Offset Error—The major carry transition should occur for an

analog value ½ LSB below VIN+ = VIN–. Offset error is

defined as the deviation of the actual transition from that point.

Minimum Conversion Rate—The clock rate at which the SNR

of the lowest analog signal frequency drops by no more than

3 dB below the guaranteed limit.

Gain Error—The first code transition should occur at an

analog value ½ LSB above negative full scale. The last transition

should occur at an analog value 1½ LSB below the positive

full scale. Gain error is the deviation of the actual difference

between first and last code transitions and the ideal difference

between first and last code transitions.

Maximum Conversion Rate—The clock rate at which para-

metric testing is performed.

Output Propagation Delay (t_PD)—The delay between the clock

rising edge and the time when all bits are within valid logic

levels.

Temperature Drift—The temperature drift for offset error and

gain error specifies the maximum change from the initial

(25°C) value to the value at T_MINor T_MAX

.

Out-of-Range Recovery Time—The time it takes for the ADC

to reacquire the analog input after a transition from 10% above

positive full scale to 10% above negative full scale, or from 10%

below negative full scale to 10% below positive full scale.

Power Supply Rejection Ratio—The change in full scale from

the value with the supply at the minimum limit to the value

with the supply at its maximum limit.

Total Harmonic Distortion (THD)¹—The ratio of the rms

input signal amplitude to the rms value of the sum of the first

six harmonic components.

¹AC specifications may be reported in dBc (degrades as signal levels are

lowered) or in dBFS (always related back to converter full scale).

Signal-to-Noise and Distortion (SINAD)¹—The ratio of the

rms input signal amplitude to the rms value of the sum of all

other spectral components below the Nyquist frequency, includ-

ing harmonics but excluding dc.

Rev. B | Page ꢀ of 2ꢀ

AD9245

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

DNC 1

CLK 2

DNC 3

PDWN 4

(LSB) D0 5

D1 6

24 VREF

23 SENSE

22 MODE

21 OTR

20 D13 (MSB)

19 D12

AD9245

CSP

TOP VIEW

(Not to Scale)

D2 7

18 D11

D3 8

17 D10

03583-B-022

Figure 3. 32-Lead LFCSP

Table 7. Pin Function Descriptions—32-Lead LFCSP (CP Package)

Pin No.

Mnemonic

DNC

CLK

Description

1, 3

2

Do Not Connect

Clock Input Pin

4

PDWN

D0 (LSB) to D13 (MSB)

DGND

DRVDD

OTR

Power-Down Function Select

Data Output Bits

Digital Output Ground

Digital Output Driver Supply

Out-of-Range Indicator

5 to 14, 17 to 20

15

16

21

22

23

24

25

MODE

SENSE

VREF

REFB

REFT

AVDD

AGND

VIN+

Data Format Select and DCS Mode Selection (see Table 9)

Reference Mode Selection (see Table ꢀ)

Voltage Reference Input/Output

Differential Reference (–)

Differential Reference (+)

Analog Power Supply

26

27, 32

2ꢀ, 31

29

Analog Ground

Analog Input Pin (+)

30

VIN–

Analog Input Pin (–)

Rev. B | Page 9 of 2ꢀ

AD9245

EQUIVALENT CIRCUITS

AVDD

DRVDD

D13-D0,

OTR

VIN+, VIN–

03583-B-005

03583-B-003

Figure 6. Equivalent Digital Output Circuit

Figure 4. Equivalent Analog Input Circuit

AVDD

CLK,

MODE

PDWN

20kΩ

03583-B-004

03583-B-006

Figure 5. Equivalent MODE Input Circuit

Figure 7. Equivalent Digital Input Circuit

Rev. B | Page 10 of 2ꢀ

AD9245

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 3.0 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, DCS Disabled, T_A= 25°C, 2 V p-p Differential Input, AIN = –0.5 dBFS,

VREF = 1.0 V External, unless otherwise noted

0

–10

100

90

80

70

60

50

40

SFDR (dBFS)

AIN = –0.5dBFS

SNR = 73.2dBc

ENOB = 11.8 BITS

SFDR = 92.8 dBc

–20

SFDR (dBc)

–30

SNR (dBFS)

–40

–50

–60

SFDR = 90dBc

–70

REFERENCE LINE

–80

–90

SNR (dBc)

–100

–110

–120

0

5

10

15

20

25

30

35

40

–30

–25

–20

–15

–10

–5

0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

03583-B-032

03583-B-033

Figure 8. Single Tone 8K FFT @ 2.5 MHz

Figure 11. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz

0

–10

100

SFDR (dBFS)

AIN = –0.5dBFS

SNR = 72.7dBc

ENOB = 11.8 BITS

SFDR = 87.6 dBc

–20

90

SFDR (dBc)

–30

SNR (dBFS)

–40

80

70

60

50

40

–50

–60

SFDR = 90dBc

–70

REFERENCE LINE

–80

–90

SNR (dBc)

–100

–110

–120

5

10

15

20

25

30

35

40

–30

–25

–20

–15

–10

–5

0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

03583-B-023

03583-B-034

Figure 9. Single Tone 8K FFT @ 39 MHz

Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz

0

–10

100

AIN = –0.5dBFS

SNR = 71.7dBc

ENOB = 11.5 BITS

SFDR = 81.6 dBc

SFDR (DIFF)

–20

90

–30

SNR (DIFF)

SFDR (SE)

–40

80

70

–50

–60

–70

–80

SNR (SE)

–90

60

–100

–110

–120

50

5

10

15

20

25

30

35

40

0

20

40

60

80

100

FREQUENCY (MHz)

SAMPLE RATE (MSPS)

03583-B-024

03583-B-025

Figure 10. Single Tone 8K FFT @ 70 MHz

Figure 13. SNR/SFDR vs. Sample Rate @ 40 MHz

Rev. B | Page 11 of 2ꢀ

AD9245

100

90

80

70

60

50

40

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

SFDR (dBFS)

AIN = –6.5dBFS

SNR = 73.4dBFS

SFDR = 86.0dBFS

SFDR (dBc)

SNR (dBFS)

SFDR = 90dBc

REFERENCE LINE

SNR (dBc)

–120

0

–30

–27

–24

–21

–18

–15

–12

–9

–6

5

10

15

20

25

30

35

40

INPUT AMPLITUDE (dBFS)

FREQUENCY (MHz)

03583-B-031

03583-B-029

Figure 17. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz

Figure 14. Two-Tone 8K FFT @ 30 MHz and 31 MHz

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

100

SFDR (dBFS)

AIN = –6.5dBFS

SNR = 72.7dBFS

SFDR = 78.8dBFS

90

SFDR (dBc)

80

70

SNR (dBFS)

SFDR = 90dBc

60

50

40

REFERENCE LINE

SNR (dBc)

–12

–120

0

–30

–27

–24

–21

–18

–15

–9

–6

5

10

15

20

25

30

35

40

INPUT AMPLITUDE (dBFS)

FREQUENCY (MHz)

03583-B-027

03583-B-030

Figure 15. Two-Tone 8K FFT @ 69 MHz and 70 MHz

Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz

1.0

0.8

1.5

1.0

0.5

0

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

0

2048

4096

6144

8192 10240 12288 14336 16384

2048

4096

6144

8192 10240 12288 14336 16384

CODE

03583-B-028

03583-B-026

Figure 19. Typical DNL

Figure 16. Typical INL

Rev. B | Page 12 of 2ꢀ

AD9245

75

74

73

72

71

70

69

68

67

66

65

100

95

90

85

80

75

70

–40°C

+25°C

+85°C

–40

°

C

+25°C

+85°C

0

25

50

75

100

125

0

25

50

75

100

125

INPUT FREQUENCY (MHz)

03583-B-036

03583-B-038

Figure 20. SNR vs. Input Frequency

Figure 23. SFDR vs. Input Frequency

90

0

–10

SFDR (DCS ON)

88

86

84

82

80

78

76

74

72

70

–20

–30

–40

SFDR (DCS OFF)

–50

–60

–70

–80

–90

SNR (DCS OFF)

–100

–110

–120

SNR (DCS ON)

50 55

DUTY CYCLE (%)

30

35

40

45

60

65

70

0

9.6

19.2

28.8

38.4

FREQUENCY (MHz)

03583-B-037

03583-B-060

Figure 21. SNR/SFDR vs. Clock Duty Cycle

Figure 24. Two 32K FFT CDMA-2000 Carriers @

F_IN= 46.08 MHz; Sample Rate = 61.44 MSPS

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–110

–120

0

9.6

19.2

28.8

38.4

0

9.6

19.2

28.8

38.4

FREQUENCY (MHz)

03583-B-059

03583-B-061

Figure 22. 32K FFT WCDMA Carrier @ F_IN= 96 MHz; Sample Rate = 76.8 MSPS

Figure 25. Two 32K FFT WCDMA Carriers @

F_IN= 76.8 MHz; Sample Rate = 61.44 MSPS

Rev. B | Page 13 of 2ꢀ

AD9245

THEORY OF OPERATION

The AD9245 architecture consists of a front-end sample and

hold amplifier (SHA) followed by a pipelined switched capaci-

tor ADC. The pipelined ADC is divided into three sections,

consisting of a 4-bit first stage followed by eight 1.5-bit stages

and a final 3-bit flash. Each stage provides sufficient overlap to

correct for flash errors in the preceding stages. The quantized

outputs from each stage are combined into a final 14-bit result

in the digital correction logic. The pipelined architecture per-

mits the first stage to operate on a new input sample, while the

remaining stages operate on preceding samples. Sampling

occurs on the rising edge of the clock.

Referring to Figure 27, the clock signal alternately switches the

SHA between sample mode and hold mode. When the SHA is

switched into sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current required from the output

stage of the driving source. Also, a small shunt capacitor can be

placed across the inputs to provide dynamic charging currents.

This passive network creates a low-pass filter at the ADC’s

input; therefore, the precise values are dependent upon the

application. In IF undersampling applications, any shunt

capacitors should be reduced or removed. In combination with

the driving source impedance, they would limit the input

bandwidth.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

H

T

5pF

VIN+

VIN–

C

PAR

The input stage contains a differential SHA that can be ac-

coupled or dc-coupled in differential or single-ended modes.

The output-staging block aligns the data, carries out the error

correction, and passes the data to the output buffers. The output

buffers are powered from a separate supply, allowing adjustment

of the output voltage swing. During power-down, the output

buffers go into a high impedance state.

T

H

03583-B-012

Figure 27. Switched-Capacitor SHA Input

ANALOG INPUT AND REFERENCE OVERVIEW

The analog input to the AD9245 is a differential switched-

capacitor SHA that has been designed for optimum perform-

ance while processing a differential input signal. The SHA input

can support a wide common-mode range (VCM) and maintain

excellent performance, as shown in Figure 26. An input

common-mode voltage of midsupply minimizes signal-

dependent errors and provides optimum performance.

For best dynamic performance, the source impedances driving

VIN+ and VIN– should be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC.

An internal differential reference buffer creates positive and

negative reference voltages, REFT and REFB, that define the

span of the ADC core. The output common mode of the

reference buffer is set to midsupply, and the REFT and REFB

voltages and span are defined as follows:

100

95

SFDR (2.5MHz)

90

1

2

1

85

REFT =

REFB =

AVDD +VREF

( )

SFDR (39MHz)

80

(

AVDD −VREF

)

SNR (2.5MHz)

SNR (39MHz)

75

70

65

60

55

50

2

Span = 2×

(

REFT − REFB

)

= 2×VREF

It can be seen from the equations above that the REFT and

REFB voltages are symmetrical about the midsupply voltage, and,

by definition, the input span is twice the value of the VREF voltage.

0.5

1.0

1.5

2.0

2.5

3.0

The internal voltage reference can be pin strapped to fixed

values of 0.5 V or 1.0 V, or adjusted within the same range as

discussed in the Internal Reference Connection section.

Maximum SNR performance is achieved with the AD9245 set

COMMON-MODE LEVEL (V)

03583-B-039

Figure 26. SNR, SFDR vs. Common-Mode Level

Rev. B | Page 14 of 2ꢀ

AD9245

to the largest input span of 2 V p-p. The relative SNR degradation

is 3 dB when changing from 2 V p-p mode to 1 V p-p mode.

AVDD

VIN+

33Ω

The SHA may be driven from a source that keeps the signal

peaks within the allowable range for the selected reference volt-

age. The minimum and maximum common-mode input levels

are defined as

2V p-p

49.9Ω

10pF

33Ω

AD9245

VIN–

AGND

1kΩ

VREF

0.1µF

VCM_MIN

=

03583-B-014

2

Figure 29. Differential Transformer-Coupled Configuration

(

AVDD +VREF

)

VCM_MAX

=

2

The signal characteristics must be considered when selecting

a transformer. Most RF transformers saturate at frequencies

below a few MHz, and excessive signal power can also cause

core saturation, which leads to distortion.

The minimum common-mode input level allows the AD9245 to

accommodate ground referenced inputs.

Although optimum performance is achieved with a differential

input, a single-ended source may be applied to VIN+ or VIN–.

In this configuration, one input accepts the signal, while the

opposite input should be set to midscale by connecting it to an

appropriate reference. For example, a 2 V p-p signal may be

applied to VIN+ while a 1 V reference is applied to VIN–. The

AD9245 then accepts an input signal varying between 2 V and

0 V. In the single-ended configuration, distortion performance

may degrade significantly as compared to the differential case.

However, the effect is less noticeable at lower input frequencies.

Single-Ended Input Configuration

A single-ended input may provide adequate performance in

cost-sensitive applications. In this configuration, there is a

degradation in SFDR and distortion performance due to the

large input common-mode swing (see Figure 13). However, if

the source impedances on each input are matched, there should

be little effect on SNR performance. Figure 30 details a typical

single-ended input configuration.

1k

Ω

Differential Input Configurations

AVDD

VIN+

33

Ω

As previously detailed, optimum performance is achieved while

driving the AD9245 in a differential input configuration. For

baseband applications, the AD8138 differential driver provides

excellent performance and a flexible interface to the ADC. The

output common-mode voltage of the AD8138 is easily set to

AVDD/2, and the driver can be configured in a Sallen Key filter

topology to provide band limiting of the input signal.

0.33µF

1k

2V p-p

49.9

Ω

20pF

33

AD9245

1k

Ω

+

VIN–

AGND

10

µF

0.1

µ

F

1k

03583-B-015

Figure 30. Single-Ended Input Configuration

CLOCK INPUT CONSIDERATIONS

1V p-p

49.9Ω

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals, and as a result may be sensitive

to clock duty cycle. Commonly a 5% tolerance is required on the

clock duty cycle to maintain dynamic performance characteris-

tics. The AD9245 contains a clock duty cycle stabilizer (DCS) that

retimes the nonsampling edge, providing an internal clock signal

with a nominal 50% duty cycle. This allows a wide range of clock

input duty cycles without affecting the performance of the

AD9245. As shown in Figure 21, noise and distortion perform-

ance is nearly flat for a 30% to 70% duty cycle with the DCS on.

499Ω

AVDD

VIN+

33Ω

499Ω

523Ω

20pF

AD8138

499Ω

AD9245

1kΩ

33Ω

VIN–

AGND

0.1µF

03583-B-013

Figure 28. Differential Input Configuration Using the AD8138

At input frequencies in the second Nyquist zone and above, the

performance of most amplifiers is not adequate to achieve the

true performance of the AD9245. This is especially true in IF

undersampling applications where frequencies in the 70 MHz to

100 MHz range are being sampled. For these applications,

differential transformer coupling is the recommended input

configuration. The value of the shunt capacitor is dependent on

the input frequency and source impedance and should be

reduced or removed. An example is shown in Figure 29.

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately 100 clock cycles to

allow the DLL to acquire and lock to the new rate.

Rev. B | Page 15 of 2ꢀ

AD9245

425

400

375

350

325

300

140

120

100

80

JITTER CONSIDERATIONS

ANALOG CURRENT

TOTAL POWER

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given input fre-

quency (f_INPUT) due only to aperture jitter (t_J) can be calculated

with the following equation:

SNR= 20log

[

2πf_INPUT×t_J

]

60

In the equation, the rms aperture jitter represents the root-mean

square of all jitter sources, which include the clock input, analog

input signal, and ADC aperture jitter specification. IF undersam-

pling applications are particularly sensitive to jitter (see Figure 31).

40

20

DIGITAL CURRENT

0

10

20

30

40

50

60

70

80

90

100

SAMPLE RATE (MSPS)

03583-B-035

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the

AD9245. Power supplies for clock drivers should be separated

from the ADC output driver supplies to avoid modulating the

clock signal with digital noise. Low jitter, crystal controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or other meth-

ods), it should be retimed by the original clock at the last step.

Figure 32. Power and Current vs. Sample Rate @ 2.5 MHz

Reducing the capacitive load presented to the output drivers can

minimize digital power consumption. The data in Figure 32 was

taken with the same operating conditions as the Typical Per-

formance Characteristics, and with a 5 pF load on each output

driver.

By asserting the PDWN pin high, the AD9245 is placed in

standby mode. In this state, the ADC typically dissipates

1 mW if the CLK and analog inputs are static. During standby,

the output drivers are placed in a high impedance state.

Reasserting the PDWN pin low returns the AD9245 to its

normal operational mode.

75

0.2ps

70

65

MEASURED SNR

0.5ps

60

1.0ps

Low power dissipation in standby mode is achieved by shutting

down the reference, reference buffer, and biasing networks. The

decoupling capacitors on REFT and REFB are discharged when

entering standby mode and then must be recharged when

returning to normal operation. As a result, the wake-up time is

related to the time spent in standby mode, and shorter standby

cycles result in proportionally shorter wake-up times. With the

recommended 0.1 µF and 10 µF decoupling capacitors on REFT

and REFB, it takes approximately 1 second to fully discharge the

reference buffer decoupling capacitors and 7 ms to restore full

operation.

1.5ps

55

50

45

2.0ps

2.5ps

3.0ps

40

1

10

100

1000

INPUT FREQUENCY (MHz)

03583-B-041

Figure 31. SNR vs. Input Frequency and Jitter

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 32, the power dissipated by the AD9245 is

proportional to its sample rate. The digital power dissipation is

determined primarily by the strength of the digital drivers and

the load on each output bit. The maximum DRVDD current

(I_DRVDD) can be calculated as

DIGITAL OUTPUTS

The AD9245 output drivers can be configured to interface with

2.5 V or 3.3 V logic families by matching DRVDD to the digital

supply of the interfaced logic. The output drivers are sized to pro-

vide sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause current

glitches on the supplies that may affect converter performance.

Applications requiring the ADC to drive large capacitive loads or

large fanouts may require external buffers or latches.

I_DRVDD= V_DRVDD×C_LOAD× f_CLK×N

where N is the number of output bits, 14 in the case of the

AD9245. This maximum current occurs when every output bit

switches on every clock cycle, i.e., a full-scale square wave at the

Nyquist frequency, f_CLK/2. In practice, the DRVDD current will

be established by the average number of output bits switching,

which will be determined by the sample rate and the character-

istics of the analog input signal.

As detailed in Table 9, the data format can be selected for either

offset binary or twos complement.

Rev. B | Page 16 of 28

AD9245

TIMING

In all reference configurations, REFT and REFB drive the A/D

conversion core and establish its input span. The input range of

the ADC always equals twice the voltage at the reference pin for

either an internal or an external reference.

The AD9245 provides latched data outputs with a pipeline delay

of seven clock cycles. Data outputs are available one propaga-

tion delay (t_PD) after the rising edge of the clock signal. Refer to

Figure 2 for a detailed timing diagram.

VIN+

The length of the output data lines and the loads placed on

them should be minimized to reduce transients within the

AD9245. These transients can degrade the converter’s dynamic

performance.

VIN–

REFT

0.1µF

+

ADC

0.1µF

REFB

0.1µF

10µF

CORE

The lowest typical conversion rate of the AD9245 is 1 MSPS. At

clock rates below 1 MSPS, dynamic performance may degrade.

VREF

0.1µF

+

10µF

VOLTAGE REFERENCE

SELECT

LOGIC

A stable and accurate 0.5 V voltage reference is built into the

AD9245. The input range can be adjusted by varying the refer-

ence voltage applied to the AD9245 using either the internal

reference or an externally applied reference voltage. The input

span of the ADC tracks reference voltage changes linearly. The

various reference modes are summarized Table 8 and described

in the following sections.

SENSE

0.5V

AD9245

03583-B-017

Figure 33. Internal Reference Configuration

If the ADC is being driven differentially through a transformer,

the reference voltage can be used to bias the center tap (com-

mon-mode voltage).

If the internal reference of the AD9245 is used to drive multiple

converters to improve gain matching, the loading of the refer-

ence by the other converters must be considered. Figure 34

depicts how the internal reference voltage is affected by loading.

INTERNAL REFERENCE CONNECTION

A comparator within the AD9245 detects the potential at the

SENSE pin and configures the reference into one of four

possible states, which are summarized in Table 8. If SENSE is

grounded, the reference amplifier switch is connected to the

internal resistor divider (see Figure 33), setting VREF to 1 V.

Connecting the SENSE pin to VREF switches the reference

amplifier output to the SENSE pin, completing the loop and

providing a 0.5 V reference output. If a resistor divider is

connected as shown in Figure 35, the switch is again set to the

SENSE pin. This puts the reference amplifier in a noninverting

mode with the VREF output defined as follows:

0.05

0

–0.05

0.5V ERROR (%)

–0.10

1.0V ERROR (%)

–0.15

–0.20

–0.25

R2

R1











VREF = 0.5× 1+



0

0.5

1.0

1.5

LOAD (mA)

2.0

2.5

3.0

03583-B-019

Figure 34. VREF Accuracy vs. Load

Table 8. Reference Configuration Summary

Internal Switch

Position

Resulting Differential

Span (V p-p)

Selected Mode

SENSE Voltage

AVDD

VREF

Resulting VREF (V)

External Reference

Internal Fixed Reference

Programmable Reference

N/A

SENSE

N/A

0.5

2 × External Reference

1.0

2 × VREF

0.2 V to VREF

R2

R1











(See Figure 35)

0.5 × 1 +



Internal Fixed Reference

AGND to 0.2 V

Internal Divider

1.0

2.0

Rev. B | Page 17 of 2ꢀ

AD9245

OPERATIONAL MODE SELECTION

VIN+

VIN–

As discussed earlier, the AD9245 can output data in either offset

binary or twos complement format. There is also a provision for

enabling or disabling the clock duty cycle stabilizer (DCS). The

MODE pin is a multilevel input that controls the data format

and DCS state. The input threshold values and corresponding

mode selections are outlined in Table 9.

REFT

0.1µF

REFB

0.1µF

+

ADC

10µF

CORE

VREF

+

10µF

0.1µF

SELECT

LOGIC

Table 9. Mode Selection

R2

Duty Cycle

SENSE

MODE Voltage

AVDD

2/3 AVDD

1/3 AVDD

AGND (Default)

Data Format

Stabilizer

Disabled

Enabled

Disabled

Twos Complement

Offset Binary

R1

0.5V

AD9245

Offset Binary

03583-B-018

Figure 35. Programmable Reference Configuration

EVALUATION BOARD

The AD9245 evaluation board provides all of the support

circuitry required to operate the ADC in its various modes and

configurations. Complete schematics and layout plots follow

and demonstrate the proper routing and grounding techniques

that should be applied at the system level.

EXTERNAL REFERENCE OPERATION

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. When multiple ADCs track one another, a single

reference (internal or external) may be necessary to reduce gain

matching errors to an acceptable level. Figure 36 shows the typi-

cal drift characteristics of the internal reference in both 1.0 V

and 0.5 V modes.

It is critical that signal sources with very low phase noise (<1 ps

rms jitter) be used to realize the ultimate performance of the

converter. Proper filtering of the input signal, to remove

harmonics and lower the integrated noise at the input, is also

necessary to achieve the specified noise performance.

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7 kΩ load. The internal buffer still generates the positive and

negative full-scale references, REFT and REFB, for the ADC

core. The input span is always twice the value of the reference

voltage; therefore, the external reference must be limited to a

maximum of 1.0 V.

The AD9245 can be driven single-ended or differentially

through a transformer. Separate power pins are provided to

isolate the DUT from the support circuitry. Each input configu-

ration can be selected by proper connection of various jumpers

(refer to the schematics).

An alternative differential analog input path using an AD8351

op amp is included in the layout, but is not populated in pro-

duction. Designers interested in evaluating the op amp with the

ADC should remove C15, R12, and R3, and populate the op

amp circuit. The passive network between the AD8351 outputs

and the AD9245 allows the user to optimize the frequency

response of the op amp for the application.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

VREF = 1.0V

0.2

0.1

VREF = 0.5V

0

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80

TEMPERATURE (°C)

03583-B-040

Figure 36. Typical VREF Drift

Rev. B | Page 1ꢀ of 2ꢀ

AD9245

P 2

0 V 5 .

5 V 2 .

M P V A

V D

L

G N D

5 V 2 .

0 V 3 .

D D V D R

G N D

D D A V

D 1 0

D 1 1

D 1 2

D 1 3

O T

M O D

S E S E N

E F V R

D 3

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

8

D 2 7

D 1

6

D 0

5

R

E

N W P D

4

D N C

3

C L K

2

D N C

1

Figure 37. LFCSP Evaluation Board Schematic—Analog Inputs and DUT

Rev. B | Page 19 of 2ꢀ

AD9245

Figure 38. LFCSP Evaluation Board Schematic—Digital Path

Rev. B | Page 20 of 2ꢀ

AD9245

Figure 39. LFCSP Evaluation Board Schematic—Clock Input

Rev. B | Page 21 of 2ꢀ

AD9245

03583-B-055

03583-B-053

Figure 42. LFCSP Evaluation Board Layout, Ground Plane

Figure 40. LFCSP Evaluation Board Layout, Primary Side

03583-B-056

03583-B-054

Figure 43. LFCSP Evaluation Board Layout, Power Plane

Figure 41. LFCSP Evaluation Board Layout, Secondary Side

Rev. B | Page 22 of 2ꢀ

AD9245

03583-B-057

03583-B-058

Figure 44. LFCSP Evaluation Board Layout, Primary Silkscreen

Figure 45. LFCSP Evaluation Board Layout, Secondary Silkscreen

Rev. B | Page 23 of 2ꢀ

AD9245

Table 10. LFCSP Evaluation Board Bill of Materials

Recommended

Package Value Vendor/Part Number by ADI

Supplied

Item Qty. Omit¹Reference Designator

Device

C1, C5, C7, Cꢀ, C9, C11, C12,

1ꢀ

C13, C15, C16, C31, C33, C34,

C36, C37, C41, C43, C47

C6, C1ꢀ, C27, C17,

C2ꢀ, C35, C45, C44

C2, C3, C4, C10, C20, C22,

C25, C29

1

Chip Capacitor

0603

0.1 µF

ꢀ

2

ꢀ

2

3

Tantalum Capacitor

Chip Capacitor

TAJD

0603

10 µF

C46, C24

C14, C30, C32, C3ꢀ,

C39, C40, C4ꢀ, C49

0.001 µF

4

5

3

1

C19, C21, C23

C26

Chip Capacitor

0603

10 pF

E31, E35, E43, E44, E50, E51,

E52, E53

9

6

Header

EHOLE

Jumper Blocks

2

1

E1, E45

J1, J2

7

ꢀ

2

SMA Connector/50 Ω

Inductor

SMA

0603

Coilcraft/0603CS-

10NXGBU

L1

P2

10 nH

Wieland/25.602.2653.0,

z5-530-0625-0

9

1

Terminal Block

TB6

10

11

12

1

5

P12

Header Dual 20-Pin RT Angle HEADER40

Digi-Key S2131-20-ND

R3, R12, R23, R2ꢀ, Rx

R16, R17, R22, R27, R42, R37

R4, R15

Chip Resistor

0603

0 Ω

6

1

2

33 Ω

1 kΩ

R5, R6, R7, Rꢀ, R13, R20, R21,

R24, R25, R26, R30, R31, R32, Chip Resistor

R36

13

14

15

2

1

R10, R11

R29

Chip Resistor

0603

36 Ω

50 Ω

Chip Resistor

R19

Digi-Key

CTS/742C163220JTR

16

2

RP1, RP2

Resistor Pack

ADT1-1WT

R_742

220 Ω

17

1ꢀ

19

20

21

22

23

24

25

26

27

2ꢀ

1

T1

AWT1-1T

Mini-Circuits

U1

74LVTH162374 CMOS Register TSSOP-4ꢀ

U4

AD9245BCP ADC (DUT)

74VCXꢀ6M

CSP-32

SOIC-14

PCB

Analog Devices, Inc.

Fairchild

X

U5

PCB

AD92XXBCP/PCB

ADꢀ351 Op Amp

MACOM Transformer

Chip Resistor

Analog Devices, Inc.

X

1

5

3

2

1

U3

MSOP-ꢀ

T2

ETC1-1-13 1-1 TX MACOM/ETC1-1-13

R1, R2, R9, R3ꢀ, R39

R14, R1ꢀ, R35

R40, R41

0603

SELECT

25 Ω

Chip Resistor

10 kΩ

1.2 kΩ

100 Ω

R34

Chip Resistor

R33

Chip Resistor

Total ꢀ2 34

¹These items are included in the PCB design, but are omitted at assembly.

Rev. B | Page 24 of 2ꢀ

AD9245

OUTLINE DIMENSIONS

5.00

0.60 MAX

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

3.25

4.75

TOP

BOTTOM

VIEW

BSC SQ

3.10 SQ

2.95

VIEW

0.50

0.40

0.30

17

16

8

9

0.25 MIN

3.50 REF

0.80 MAX

12° MAX

0.65 TYP

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 46. 32-Lead Frame Chip Scale Package [LFCSP]

(CP-32-1)

Dimensions shown in millimeters

ORDERING GUIDE

AD9245 Products

AD9245BCP-ꢀ0¹

AD9245BCPRL7–ꢀ0¹

AD9245BCPZ-ꢀ0^{1, 2}

AD9245BCPZRL7-ꢀ0^{1, 2}

AD9245BCP-ꢀ0EB¹

Temperature Range

–40°C to +ꢀ5°C

Package Description

Package Outline

Lead Frame Chip Scale Package (LFCSP)

Evaluation Board

CP-32-1

¹It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and the maxi-

mum thermal capability of the package is achieved with the exposed paddle soldered to the customer board.

²Z = Lead Free.

Rev. B | Page 25 of 2ꢀ

AD9245

NOTES

Rev. B | Page 26 of 2ꢀ

AD9245

NOTES

Rev. B | Page 27 of 2ꢀ

AD9245

NOTES

tered trademarks are the property of their respective owners.

C03583-0-10/03(B)

Rev. B | Page 2ꢀ of 2ꢀ


型号：	AD9245
厂家：	ADI
描述：	14-Bit, 80 MSPS, 3 V A/D Converter 14位， 80 MSPS ， 3 V A / D转换器转换器
文件：	总28页 (文件大小：1338K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9245 [ADI]

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