AD9254BCPZRL7-1501 [ADI]
14-Bit, 150 MSPS, 1.8 V Analog-to-Digital Converter; 14位， 150 MSPS ， 1.8 V模拟数字转换器
| 型号： | AD9254BCPZRL7-1501 |
| 厂家： | 
ADI |
| 描述： | 14-Bit, 150 MSPS, 1.8 V Analog-to-Digital Converter |
| 文件： | 总40页 (文件大小：1684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Bit, 150 MSPS, 1.8 V
Analog-to-Digital Converter
AD9254
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AVDD
DRVDD
1.8 V analog supply operation
1.8 V to 3.3 V output supply
AD9254
SNR = 71.8 dBc (72.8 dBFS) to 70 MHz input
SFDR = 84 dBc to 70 MHz input
Low power: 430 mW @ 150 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = 0.4 LSB
VIN+
VIN–
8-STAGE
MDAC1
A/D
3
SHA
1 1/2-BIT PIPELINE
4
8
A/D
REFT
REFB
CORRECTION LOGIC
OR
15
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
OUTPUT BUFFERS
DCO
D13 (MSB)
D0 (LSB)
VREF
Data output clock
Serial port control
Built-in selectable digital test pattern generation
Programmable clock and data alignment
SENSE
SCLK/DFS
SDIO/DCS
CSB
CLOCK
DUTY CYCLE
STABILIZER
0.5V
MODE
SELECT
REF
SELECT
AGND
CLK+ CLK–
PDWN DRGND
APPLICATIONS
Figure 1.
Ultrasound equipment
IF sampling in communications receivers
CDMA2000, WCDMA, TD-SCDMA, and WiMax
Battery-powered instruments
Hand-held scopemeters
The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic.
Low cost digital oscilloscopes
Macro, micro, and pico cell infrastructure
GENERAL DESCRIPTION
The AD9254 is available in a 48-lead LFCSP_VQ and is specified
over the industrial temperature range (−40°C to +85°C).
The AD9254 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS
analog-to-digital converter (ADC), featuring a high performance
sample-and-hold amplifier (SHA) and on-chip voltage reference.
The product uses a multistage differential pipeline architecture
with output error correction logic to provide 14-bit accuracy at
150 MSPS data rates and guarantees no missing codes over the
full operating temperature range.
PRODUCT HIGHLIGHTS
1. The AD9254 operates from a single 1.8 V power supply
and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9254 is suitable for applications in communications,
imaging, and medical ultrasound.
2. The patented SHA input maintains excellent performance
for input frequencies up to 225 MHz.
3. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
4. A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.
A differential clock input controls all internal conversion cycles.
A duty cycle stabilizer (DCS) compensates for wide variations in
the clock duty cycle while maintaining excellent overall ADC
performance.
5. The AD9254 is pin-compatible with the AD9233, allowing
a simple migration from 12 bits to 14 bits.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD9254
TABLE OF CONTENTS
Features .............................................................................................. 1
Timing ......................................................................................... 20
Serial Port Interface (SPI).............................................................. 21
Configuration Using the SPI..................................................... 21
Hardware Interface..................................................................... 21
Configuration Without the SPI ................................................ 21
Memory Map .................................................................................. 22
Reading the Memory Map Register Table............................... 22
Memory Map Register Table..................................................... 23
Layout Considerations................................................................... 25
Power and Ground Recommendations................................... 25
CML ............................................................................................. 25
RBIAS........................................................................................... 25
Reference Decoupling................................................................ 25
Evaluation Board ............................................................................ 26
Power Supplies............................................................................ 26
Input Signals................................................................................ 26
Output Signals ............................................................................ 26
Default Operation and Jumper Selection Settings................. 27
Alternative Clock Configurations............................................ 27
Alternative Analog Input Drive Configuration...................... 27
Schematics................................................................................... 29
Evaluation Board Layout........................................................... 34
Bill of Materials........................................................................... 37
Outline Dimensions....................................................................... 40
Ordering Guide .......................................................................... 40
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Timing Diagram ........................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Equivalent Circuits........................................................................... 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 14
Analog Input Considerations.................................................... 14
Differential Input Configurations............................................ 15
Voltage Reference ....................................................................... 16
Clock Input Considerations...................................................... 17
Jitter Considerations .................................................................. 19
Power Dissipation and Standby Mode..................................... 19
Digital Outputs ........................................................................... 20
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
AD9254
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.
Table 1.
AD9254BCPZ-150
Parameter
Temperature
Unit
Min
Typ
Max
RESOLUTION
Full
14
Bits
ACCURACY
No Missing Codes
Offset Error
Gain Error
Full
Full
Full
2ꢂ°C
Full
2ꢂ°C
Full
Guaranteed
±0.3
±0.ꢁ
±0.ꢀ
±4.ꢂ
% FSR
% FSR
LSB
LSB
LSB
Differential Nonlinearity (DNL)1
±0.4
±1.0
±ꢂ.0
Integral Nonlinearity (INL)1
±1.ꢂ
LSB
TEMPERATURE DRIFT
Offset Error
Gain Error
Full
Full
±1ꢂ
±±ꢂ
ppm/°C
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
INPUT REFERRED NOISE
VREF = 1.0 V
Full
Full
±ꢂ
7
±3ꢂ
mV
mV
2ꢂ°C
1.3
LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance2
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Full
Full
Full
2
ꢀ
ꢁ
V p-p
pF
kΩ
Supply Voltage
AVDD
DRVDD
Full
Full
1.7
1.7
1.ꢀ
2.ꢂ
1.±
3.ꢁ
V
V
Supply Current
IAVDD1
Full
Full
Full
240
11
23
2ꢁ0
mA
mA
mA
IDRVDD1(DRVDD = 1.ꢀ V)
IDRVDD1 (DRVDD = 3.3 V)
POWER CONSUMPTION
DC Input
Full
Full
Full
Full
Full
430
4ꢂ0
ꢂ0ꢁ
40
470
mW
mW
mW
mW
mW
Sine Wave Input1 (DRVDD = 1.ꢀ V)
Sine Wave Input1 (DRVDD = 3.3 V)
Standby Power3
Power-Down Power
1.ꢀ
1 Measured with a low input frequency, full-scale sine wave, with approximately ꢂ pF loading on each output bit.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
3 Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).
Rev. 0 | Page 3 of 40
AD9254
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.
Table 2.
AD9254BCPZ-150
Parameter1
Temperature
Unit
Min
Typ
Max
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 2.4 MHz
fIN = 70 MHz
2ꢂ°C
2ꢂ°C
Full
2ꢂ°C
2ꢂ°C
72.0
71.ꢀ
dBc
dBc
dBc
dBc
dBc
70.0
fIN = 100 MHz
fIN = 170 MHz
71.ꢁ
70.ꢀ
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz
fIN = 70 MHz
2ꢂ°C
2ꢂ°C
Full
2ꢂ°C
2ꢂ°C
71.7
71.0
dBc
dBc
dBc
dBc
dBc
ꢁ±.0
fIN = 100 MHz
fIN = 170 MHz
70.ꢁ
ꢁ±.ꢀ
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
2ꢂ°C
2ꢂ°C
2ꢂ°C
2ꢂ°C
11.7
11.7
11.ꢁ
11.ꢂ
Bits
Bits
Bits
Bits
WORST SECOND OR THIRD HARMONIC
fIN = 2.4 MHz
fIN = 70 MHz
2ꢂ°C
2ꢂ°C
Full
2ꢂ°C
2ꢂ°C
dBc
dBc
dBc
dBc
dBc
−±0
−ꢀ4
−74
fIN = 100 MHz
fIN = 170 MHz
−ꢀ3
−ꢀ0
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 70 MHz
2ꢂ°C
2ꢂ°C
Full
2ꢂ°C
2ꢂ°C
dBc
dBc
dBc
dBc
dBc
±0
ꢀ4
74
fIN = 100 MHz
fIN = 170 MHz
ꢀ3
ꢀ0
WORST OTHER (HARMONIC OR SPUR)
fIN = 2.4 MHz
fIN = 70 MHz
2ꢂ°C
2ꢂ°C
Full
2ꢂ°C
2ꢂ°C
dBc
dBc
dBc
dBc
dBc
−±3
−±3
−ꢀꢂ
fIN = 100 MHz
fIN = 170 MHz
−±0
−±0
TWO-TONE SFDR
2ꢂ°C
2ꢂ°C
2ꢂ°C
dBFS
dBFS
MHz
fIN = 2± MHz (−7 dBFS ), 32 MHz (−7 dBFS )
fIN = 1ꢁ± MHz (−7 dBFS ), 172 MHz (−7 dBFS )
ANALOG INPUT BANDWIDTH
±0
±0
ꢁꢂ0
1 See Application Note AN-ꢀ3ꢂ, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. 0 | Page 4 of 40
AD9254
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.
Table 3.
AD9254BCPZ-150
Parameter
Temperature
Unit
Min
Typ
Max
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
CMOS/LVDS/LVPECL
1.2
Full
Full
Full
Full
V
0.2
AVDD − 0.3
1.1
ꢁ
V p-p
V
V
AVDD + 1.ꢁ
AVDD
Input Common-Mode Range
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Full
Full
Full
Full
Full
Full
1.2
0
3.ꢁ
0.ꢀ
V
V
μA
μA
kΩ
pF
−10
−10
ꢀ
+10
+10
12
10
4
Input Capacitance
LOGIC INPUTS (SCLK/DFS, OEB, PWDN)
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Full
Full
Full
Full
Full
Full
1.2
0
−ꢂ0
−10
3.ꢁ
0.ꢀ
−7ꢂ
+10
V
V
μA
μA
kΩ
pF
30
2
Input Capacitance
LOGIC INPUTS (CSB)
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Full
Full
Full
Full
Full
Full
1.2
0
−10
+40
3.ꢁ
0.ꢀ
+10
+13ꢂ
V
V
μA
μA
kΩ
pF
2ꢁ
2
Input Capacitance
LOGIC INPUTS (SDIO/DCS)
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Full
Full
Full
Full
Full
Full
1.2
0
−10
+40
DRVDD + 0.3
0.ꢀ
+10
V
V
μA
μA
kΩ
pF
+130
2ꢁ
ꢂ
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage (VOH, IOH = ꢂ0 μA)
High Level Output Voltage (VOH, IOH = 0.ꢂ mA)
Low Level Output Voltage (VOL, IOL = 1.ꢁ mA)
Low Level Output Voltage (VOL, IOL = ꢂ0 μA)
DRVDD = 1.ꢀ V
Full
Full
Full
Full
3.2±
3.2ꢂ
V
V
V
V
0.2
0.0ꢂ
High Level Output Voltage (VOH, IOH = ꢂ0 μA)
High Level Output Voltage (VOH, IOH = 0.ꢂ mA)
Low Level Output Voltage (VOL, IOL = 1.ꢁ mA)
Low Level Output Voltage (VOL, IOL = ꢂ0 μA)
Full
Full
Full
Full
1.7±
1.7ꢂ
V
V
V
V
0.2
0.0ꢂ
Rev. 0 | Page ꢂ of 40
AD9254
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4.
AD9254BCPZ-150
Parameter1
Temperature
Unit
Min
Typ
Max
CLOCK INPUT PARAMETERS
Conversion Rate, DCS Enabled
Conversion Rate, DCS Disabled
CLK Period
CLK Pulse Width High, DCS Enabled
CLK Pulse Width High, DCS Disabled
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)2
Full
Full
Full
Full
Full
20
10
ꢁ.7
2.0
3.0
1ꢂ0
1ꢂ0
MSPS
MSPS
ns
ns
ns
3.3
3.3
4.7
3.7
Full
Full
Full
Full
Full
Full
Full
Full
Full
3.1
3.±
4.4
2.±
3.ꢀ
12
0.ꢀ
0.1
3ꢂ0
3
4.ꢀ
ns
ns
ns
ns
Cycles
ns
ps rms
μs
DCO Propagation Delay (tDCO
)
Setup Time (tS)
Hold Time (tH)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time3
1.±
3.0
OUT-OF-RANGE RECOVERY TIME
SERIAL PORT INTERFACE4
Cycles
SCLK Period (tCLK
)
Full
Full
Full
Full
Full
Full
Full
40
1ꢁ
1ꢁ
ꢂ
2
ꢂ
ns
ns
ns
ns
ns
ns
ns
SCLK Pulse Width High Time (tHI)
SCLK Pulse Width Low Time (tLO)
SDIO to SCLK Setup Time (tDS)
SDIO to SCLK Hold Time (tDH)
CSB to SCLK Setup Time (tS)
CSB to SCLK Hold Time (tH)
2
1 See Application Note AN-ꢀ3ꢂ, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Output propagation delay is measured from CLK ꢂ0% transition to DATA ꢂ0% transition, with ꢂ pF load.
3 Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB.
4 See Figure ꢂ0 and the Serial Port Interface (SPI) section.
TIMING DIAGRAM
N + 2
N + 1
N + 3
N
N + 4
N + 8
tA
N + 5
N + 7
N + 6
tCLK
CLK+
CLK–
tPD
N – 12
DATA
DCO
N – 13
tS
N – 11
tH
N – 10
N – 9
tDCO
N – 8
N – 7
tCLK
N – 6
N – 5
N – 4
Figure 2. Timing Diagram
Rev. 0 | Page ꢁ of 40
AD9254
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
ELECTRICAL
AVDD to AGND
DRVDD to DGND
AGND to DGND
AVDD to DRVDD
D0 through D13 to DGND
DCO to DGND
OR to DGND
CLK+ to AGND
CLK− to AGND
VIN+ to AGND
VIN− to AGND
VREF to AGND
SENSE to AGND
REFT to AGND
REFB to AGND
SDIO/DCS to DGND
PDWN to AGND
CSB to AGND
SCLK/DFS to AGND
OEB to AGND
−0.3 V to +2.0 V
−0.3 V to +3.± V
−0.3 V to +0.3 V
−3.± V to +2.0 V
−0.3V to DRVDD + 0.3V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to +3.± V
THERMAL RESISTANCE
The exposed paddle must be soldered to the ground plane for
the LFCSP_VQ package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
−0.3 V to +3.± V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to +3.± V
Table 6. Thermal Resistance
Package Type
θJA
θJC
Unit
4ꢀ-lead LFCSP_VQ (CP-4ꢀ-3) 2ꢁ.4
2.4
°C/W
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal in direct contact with the package leads from
metal traces and through holes, ground, and power planes,
reduces the θJA.
−0.3 V to +3.± V
−0.3 V to +3.± V
−0.3 V to +3.± V
ENVIRONMENTAL
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering 10 Sec)
–ꢁꢂ°C to +12ꢂ°C
–40°C to +ꢀꢂ°C
300°C
ESD CAUTION
Junction Temperature
1ꢂ0°C
Rev. 0 | Page 7 of 40
AD9254
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36 PDWN
35 RBIAS
34 CML
D2
D3
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
D4
33 AVDD
32 AGND
31 VIN–
D5
D6
AD9254
D7
DRGND
DRVDD
D8
30 VIN+
TOP VIEW
(Not to Scale)
29 AGND
28 REFT
27
REFB
D9 10
D10 11
D11 12
26 VREF
25 SENSE
Figure 3. Pin Configuration
Table 7. Pin Function Description
Pin No.
Mnemonic
Description
0, 21, 23, 2±, 32,
37, 41
AGND
Analog Ground. (Pin 0 is the exposed thermal pad on the bottom of the package.)
4ꢂ, 4ꢁ, 1 to ꢁ,
± to 14
D0 (LSB) to D13 (MSB) Data Output Bits.
7, 1ꢁ, 47
ꢀ, 17, 4ꢀ
1ꢂ
DRGND
DRVDD
OR
Digital Output Ground.
Digital Output Driver Supply (1.ꢀ V to 3.3 V).
Out-of-Range Indicator.
1ꢀ
SDIO/DCS
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode). See Table 10.
1±
20
SCLK/DFS
CSB
AVDD
SENSE
VREF
REFB
REFT
VIN+
VIN–
Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
Serial Port Interface Chip Select (Active Low). See Table 10.
Analog Power Supply.
22, 24, 33, 40, 42
2ꢂ
2ꢁ
27
2ꢀ
30
31
34
3ꢂ
Reference Mode Selection. See Table ±.
Voltage Reference Input/Output.
Differential Reference (−).
Differential Reference (+).
Analog Input Pin (+).
Analog Input Pin (−).
Common-Mode Level Bias Output.
External Bias Resistor Connection. A 10 kΩ resistor must be connected between this pin and
analog ground (AGND).
CML
RBIAS
3ꢁ
3ꢀ
3±
43
44
PDWN
CLK+
CLK–
OEB
Power-Down Function Select.
Clock Input (+).
Clock Input (−).
Output Enable (Active Low).
Data Clock Output.
DCO
Rev. 0 | Page ꢀ of 40
AD9254
EQUIVALENT CIRCUITS
1kΩ
30kΩ
SCLK/DFS
OEB
VIN
PDWN
Figure 4. Equivalent Analog Input Circuit
Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit
AVDD
AVDD
26kΩ
1kΩ
1.2V
CSB
10kΩ
10kΩ
CLK+
CLK–
Figure 9. Equivalent CSB Input Circuit
Figure 5. Equivalent Clock Input Circuit
1kΩ
DRVDD
SENSE
1kΩ
SDIO/DCS
Figure 10. Equivalent Sense Circuit
Figure 6. Equivalent SDIO/DCS Input Circuit
DRVDD
AVDD
VREF
6kΩ
DRGND
Figure 11. Equivalent VREF Circuit
Figure 7. Equivalent Digital Output Circuit
Rev. 0 | Page ± of 40
AD9254
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V p-p differential input; AIN = −1.0 dBFS;
64k sample; TA = 25°C, unless otherwise noted.
0
0
150MSPS
150MSPS
2.3MHz @ –1dBFS
SNR = 72.0dBc (73.0dBFS)
ENOB = 11.7 BITS
SFDR = 90.0dBc
100.3MHz @ –1dBFS
SNR = 71.6dBc (72.6dBFS)
ENOB = 11.6 BITS
SFDR = 83dBc
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
18.75
37.50
56.25
75.00
0
18.75
37.50
FREQUENCY (MHz)
56.25
75.00
FREQUENCY (MHz)
Figure 12. AD9254 Single-Tone FFT with fIN = 2.3 MHz
Figure 15. AD9254 Single-Tone FFT with fIN = 100.3 MHz
0
–20
0
–20
150MSPS
150MSPS
140.3MHz @ –1dBFS
SNR = 71.5dBc (72.5dBFS)
ENOB = 11.5 BITS
SFDR = 81dBc
30.3MHz @ –1dBFS
SNR = 71.9dBc (72.9dBFS)
ENOB = 11.7 BITS
SFDR = 88dBc
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
18.75
37.50
56.25
75.00
0
18.75
37.50
56.25
75.00
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. AD9254 Single-Tone FFT with fIN = 30.3 MHz
Figure 16. AD9254 Single-Tone FFT with fIN = 140.3 MHz
0
–20
0
–20
150MSPS
150MSPS
70.3MHz @ –1dBFS
SNR = 71.8dBc (72.8dBFS)
ENOB = 11.7 BITS
SFDR = 84dBc
170.3MHz @ –1dBFS
SNR = 70.8dBc (71.8dBFS)
ENOB = 11.5 BITS
SFDR = 80dBc
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
18.75
37.50
56.25
75.00
0
18.75
37.50
56.25
75.00
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14. AD9254 Single-Tone FFT with fIN = 70.3 MHz
Figure 17. AD9254 Single-Tone FFT with fIN = 170.3 MHz
Rev. 0 | Page 10 of 40
AD9254
0
–20
120
100
80
60
40
20
0
150MSPS
250.3MHz @ –1dBFS
SNR = 69.3dBc (70.3dBFS)
ENOB = 11.3 BITS
SFDR = 79dBc
SFDR (dBFS)
SNR (dBFS)
–40
–60
–80
SFDR (dBc)
85dBc
REFERENCE LINE
–100
–120
SNR (dBc)
–50
0
18.75
37.50
FREQUENCY (MHz)
56.25
75.00
–90
–80
–70
–60
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
Figure 18. AD9254 Single-Tone FFT with fIN = 250.3 MHz
Figure 21. AD9254 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 2.4 MHz
0
–20
0
150MSPS
fIN1 = 29.1MHz @ –7dBFS
fIN2 = 32.1MHz @ –7dBFS
SFDR = 83.2dBc (90.2dBFS)
–20
SFDR (–dBc)
WoIMD3 = –83.9dBc (–90.9dBFS)
–40
–40
WORST IMD3 (dBc)
–60
–60
–80
–80
SFDR (–dBFS)
–100
–100
–120
WORST IMD3 (dBFS)
–120
0
18.75
37.50
56.25
75.00
–90
–78
–66
–54
–42
–30
–18
–6
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 19. AD9254 Two-Tone FFT with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz
Figure 22. AD9254 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz
90
90
SFDR +25°C
SFDR –40°C
SFDR –40°C
85
85
SFDR +25°C
80
80
SFDR +85°C
75
75
SNR –40°C
SFDR +85°C
70
70
SNR +25°C
SNR –40°C
65
65
SNR +25°C
SNR +85°C
SNR +85°C
350 400
60
60
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 20. AD9254 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 2 V p-p Full Scale
Figure 23. AD9254 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 1 V p-p Full Scale
Rev. 0 | Page 11 of 40
AD9254
2.0
1.5
0
150MSPS
fIN1 = 169.1MHz @ –7dBFS
fIN2 = 172.1MHz @ –7dBFS
SFDR = 83dBc (90dBFS)
WoIMD3 = –83dBc (90dBFS)
–20
1.0
–40
0.5
0
–60
–0.5
–1.0
–1.5
–2.0
–80
–100
–120
0
0
2048
4096
6144
8192 10240 12288 14336 16384
18.75
37.50
FREQUENCY (MHz)
56.25
75.00
OUTPUT CODE
Figure 24. AD9254 Two-Tone FFT with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz
Figure 27. AD9254 INL with fIN = 10.3 MHz
95
12000
10000
8000
6000
4000
2000
0
32768 SAMPLES
1.25 LSB rms
90
SFDR
85
80
75
SNR
70
65
N – 5 N – 4 N – 3 N – 2 N – 1
N
N + 1 N + 2 N + 3 N + 4 N + 5
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
CLOCK FREQUENCY (MSPS)
CODE
Figure 28. AD9254 Grounded Input Histogram
Figure 25. AD9254 Single-Tone SNR/SFDR vs. Clock Frequency (fCLK
with fIN = 2.4 MHz
)
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
OFFSET ERROR
–20
SFDR (–dBc)
–40
WORST IMD3 (dBc)
–60
–80
GAIN ERROR
SFDR (–dBFS)
–100
WORST IMD3 (dBFS)
–120
–90
–40
–20
0
20
40
60
80
–78
–66
–54
–42
–30
–18
–6
INPUT AMPLITUDE (dBFS)
TEMPERATURE (°C)
Figure 26. AD9254 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 169.1 MHz, fIN2 = 172.11 MHz
Figure 29. AD9254 Gain and Offset vs. Temperature
Rev. 0 | Page 12 of 40
AD9254
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
2048
4096
6144
8192 10240 12288 14336 16384
OTUPUT CODE
Figure 30. AD9254 DNL with fIN = 10.3 MHz
Rev. 0 | Page 13 of 40
AD9254
THEORY OF OPERATION
S
The AD9254 architecture consists of a front-end sample-and-
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 14-bit result in the digital correction logic. The pipeline
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding samples.
Sampling occurs on the rising edge of the clock.
C
H
S
S
C
C
S
VIN+
C
PIN, PAR
H
S
VIN–
C
C
H
PIN, PAR
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage consists only of a flash ADC.
S
Figure 31. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should match such that common-mode settling
errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
An internal differential reference buffer creates two reference
voltages used to define the input span of the ADC core. The
span of the ADC core is set by the buffer to be 2 × VREF. The
reference voltages are not available to the user. Two bypass points,
REFT and REFB, are brought out for decoupling to reduce the
noise contributed by the internal reference buffer. It is recom-
mended that REFT be decoupled to REFB by a 0.1 μF capacitor,
as described in the Layout Considerations section.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9254 is a differential switched
capacitor SHA that has been designed for optimum
performance while processing a differential input signal.
Input Common Mode
The analog inputs of the AD9254 are not internally dc-biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device such that VCM = 0.55 × AVDD is
recommended for optimum performance; however, the device
functions over a wider range with reasonable performance (see
Figure 30). An on-board common-mode voltage reference is
included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage
(typically 0.55 × AVDD). The CML pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Layout
Considerations section.
The clock signal alternately switches the SHA between sample
mode and hold mode (see Figure 31). When the SHA is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within one-half of a clock
cycle. A small resistor in series with each input can help reduce
the peak transient current required from the output stage of the
driving source.
A shunt capacitor can be placed across the inputs to provide
dynamic charging currents. This passive network creates a low-
pass filter at the ADC input; therefore, the precise values are
dependent upon the application.
In IF undersampling applications, any shunt capacitors should
be reduced. In combination with the driving source impedance,
these capacitors would limit the input bandwidth. For more
information, see Application Note AN-742, Frequency Domain
Response of Switched-Capacitor ADCs; Application Note AN-827,
A Resonant Approach to Interfacing Amplifiers to Switched-
Capacitor ADCs; and the Analog Dialogue article, “Transformer-
Coupled Front-End for Wideband A/D Converters.”
Rev. 0 | Page 14 of 40
AD9254
As an alternative to using a transformer-coupled input at
DIFFERENTIAL INPUT CONFIGURATIONS
frequencies in the second Nyquist zone, the AD8352 differential
driver can be used (see Figure 36).
Optimum performance is achieved by driving the AD9254 in a
differential input configuration. For baseband applications, the
AD8138 differential driver provides excellent performance and a
flexible interface to the ADC. The output common-mode voltage
of the AD8138 is easily set with the CML pin of the AD9254 (see
Figure 32), and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
In any configuration, the value of the shunt capacitor, C,
is dependent on the input frequency and source impedance and
may need to be reduced or removed. Table 8 displays recom-
mended values to set the RC network. However, these values are
dependent on the input signal and should only be used as a
starting guide.
1V p-p
49.9Ω
499Ω
Table 8. RC Network Recommended Values
R
R
VIN+
VIN–
Frequency Range (MHz)
R Series (Ω) C Differential (pF)
AVDD
499Ω
523Ω
0 to 70
70 to 200
200 to 300
>300
33
33
1ꢂ
1ꢂ
1ꢂ
ꢂ
ꢂ
C
AD9254
AD8138
0.1µF
CML
Open
499Ω
Single-Ended Input Configuration
Figure 32. Differential Input Configuration Using the AD8138
Although not recommended, it is possible to operate the
AD9254 in a single-ended input configuration, as long as the
input voltage swing is within the AVDD supply. Single-ended
operation can provide adequate performance in cost-sensitive
applications.
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration (see Figure 33). The CML voltage can be
connected to the center tap of the secondary winding of the
transformer to bias the analog input.
In this configuration, SFDR and distortion performance
degrade due to the large input common-mode swing. If the
source impedances on each input are matched, there should be
little effect on SNR performance. Figure 34 details a typical
single-ended input configuration.
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz, and excessive signal power can cause
core saturation, which leads to distortion.
R
VIN+
AVDD
10µF
1kΩ
49.9Ω
C
AD9254
R
2V p-p
VIN+
R
0.1µF
49.9Ω
CML
1kΩ
AVDD
VIN–
1V p-p
AD9254
C
1kΩ
R
VIN–
0.1µF
10µF
1kΩ
0.1µF
Figure 33. Differential Transformer-Coupled Configuration
Figure 34. Single-Ended Input Configuration
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9254. For applications
where SNR is a key parameter, transformer coupling is the
recommended input. For applications where SFDR is a key
parameter, differential double balun coupling is the recom-
mended input configuration (see Figure 35).
Rev. 0 | Page 1ꢂ of 40
AD9254
0.1µF
0.1µF
0.1µF
R
R
VIN+
2V p-p
25Ω
25Ω
P
A
S
S
P
C
AD9254
0.1µF
CML
VIN–
Figure 35. Differential Double Balun Input Configuration
V
CC
0.1µF
11
0.1µF
0Ω
16
1
8, 13
0.1µF
0.1µF
R
R
2
VIN+
200Ω
200Ω
AD8352
10
R
R
C
AD9254
D
G
C
D
3
4
5
CML
VIN–
14
0.1µF
0Ω
0.1µF
0.1µF
Figure 36. Differential Input Configuration Using the AD8352
Table 9. Reference Configuration Summary
Resulting Differential
Span (V p-p)
Selected Mode
SENSE Voltage
Resulting VREF (V)
External Reference
Internal Fixed Reference
Programmable Reference
AVDD
VREF
0.2 V to VREF
N/A
0.ꢂ
2 × external reference
1.0
2 × VREF
R2
R1
⎛
⎝
⎞
⎟
⎠
0.5× 1+
(see Figure 3ꢀ)
⎜
Internal Fixed Reference
AGND to 0.2 V
1.0
2.0
VOLTAGE REFERENCE
Connecting the SENSE pin to VREF switches the reference
amplifier input to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected external to the chip, as shown in Figure 38, the
switch sets to the SENSE pin. This puts the reference amplifier
in a noninverting mode with the VREF output defined as
A stable and accurate voltage reference is built into the AD9254.
The input range is adjustable by varying the reference voltage
applied to the AD9254, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in the following sections. The Reference
Decoupling section describes the best practices and require-
ments for PCB layout of the reference.
R2
R1
⎛
⎝
⎞
⎟
⎠
VREF = 0.5 1 +
⎜
If the SENSE pin is connected to AVDD, the reference amplifier
is disabled, and an external reference voltage can be applied to
the VREF pin (see the External Reference Operation section).
Internal Reference Connection
A comparator within the AD9254 detects the potential at the
SENSE pin and configures the reference into four possible
states, as summarized in Table 9. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 37), setting VREF to 1 V.
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
Rev. 0 | Page 1ꢁ of 40
AD9254
External Reference Operation
VIN+
VIN–
ADC
CORE
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift
characteristics. Figure 40 shows the typical drift characteristics
of the internal reference in both 1 V and 0.5 V modes.
10
REFT
0.1µF
REFB
VREF
0.1µF
0.1µF
SELECT
LOGIC
VREF = 1V
8
SENSE
6
4
2
0
VREF = 0.5V
0.5V
AD9254
Figure 37. Internal Reference Configuration
VIN+
ADC
CORE
VIN–
–20
0
20
40
60
–40
80
REFT
TEMPERATURE (°C)
Figure 40. Typical VREF Drift
0.1µF
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
resistor divider loads the external reference with an equivalent
6 kΩ load (see Figure 11). In addition, an internal buffer
generates the positive and negative full-scale references for the
ADC core. Therefore, the external reference must be limited to
a maximum of 1 V.
REFB
VREF
0.1µF
0.1µF
R2
SELECT
LOGIC
SENSE
0.5V
R1
AD9254
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9254 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally (see Figure 5) and require no external bias.
Figure 38. Programmable Reference Configuration
If the internal reference of the AD9254 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 39 depicts
how the internal reference voltage is affected by loading.
0
Clock Input Options
The AD9254 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal used, the jitter of the clock
source is of the most concern, as described in the Jitter
Considerations section.
VREF = 0.5V
–0.25
VREF = 1V
–0.50
Figure 41 shows one preferred method for clocking the
AD9254. A low jitter clock source is converted from single-
ended to a differential signal using an RF transformer. The
back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD9254 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9254,
while preserving the fast rise and fall times of the signal, which
are critical to a low jitter performance.
–0.75
–1.00
–1.25
0
0.5
1.0
1.5
2.0
LOAD CURRENT (mA)
Figure 39. VREF Accuracy vs. Load
Rev. 0 | Page 17 of 40
AD9254
VCC
MINI-CIRCUITS
ADT1–1WT, 1:1Z
OPTIONAL
100Ω
0.1µF
1
0.1µF
1kΩ
1kΩ
0.1µF
0.1µF
AD951x
CMOS DRIVER
CLOCK
INPUT
CLK+
XFMR
CLOCK
INPUT
CLK+
50Ω
ADC
AD9254
100Ω
ADC
AD9254
50Ω
0.1µF
CLK–
CLK–
SCHOTTKY
DIODES:
HMS2812
0.1µF
0.1µF
39kΩ
1
50Ω RESISTOR IS OPTIONAL.
Figure 41. Transformer Coupled Differential Clock
Figure 44. Single-Ended 1.8 V CMOS Sample Clock
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 42. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515 family of clock drivers offers
excellent jitter performance.
VCC
OPTIONAL
0.1µF
0.1µF
1
1kΩ
1kΩ
100Ω
AD951x
CMOS DRIVER
CLOCK
INPUT
CLK+
50Ω
ADC
AD9254
0.1µF
CLK–
1
50Ω RESISTOR IS OPTIONAL.
0.1µF
0.1µF
CLOCK
INPUT
CLK
CLK+
Figure 45. Single-Ended 3.3 V CMOS Sample Clock
ADC
AD9254
100Ω
AD951x
PECL DRIVER
Clock Duty Cycle
0.1µF
0.1µF
CLOCK
INPUT
CLK–
CLK
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5ꢀ tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
1
1
240Ω
240Ω
50Ω
50Ω
1
50Ω RESISTORS ARE OPTIONAL.
Figure 42. Differential PECL Sample Clock
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 43. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock
drivers offers excellent jitter performance.
The AD9254 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling, or falling edge, providing an internal clock
signal with a nominal 50ꢀ duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9254. Noise and distortion performance are nearly flat
for a wide range of duty cycles when the DCS is on, as shown in
Figure 28.
0.1µF
0.1µF
CLOCK
INPUT
CLK+
CLK
AD951x
ADC
AD9254
100Ω
LVDS DRIVER
0.1µF
Jitter in the rising edge of the input is still of paramount concern
and is not reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz nominally. The loop has a time constant associated
with it that needs to be considered in applications where the
clock rate can change dynamically. This requires a wait time
of 1.5 μs to 5 μs after a dynamic clock frequency increase (or
decrease) before the DCS loop is relocked to the input signal.
During the time period the loop is not locked, the DCS loop is
bypassed, and the internal device timing is dependent on the
duty cycle of the input clock signal. In such an application, it
may be appropriate to disable the duty cycle stabilizer. In all
other applications, enabling the DCS circuit is recommended
to maximize ac performance.
0.1µF
CLOCK
INPUT
CLK–
CLK
1
1
50Ω
50Ω
1
50Ω RESISTORS ARE OPTIONAL.
Figure 43. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
directly drive CLK+ from a CMOS gate, while bypassing the
CLK− pin to ground using a 0.1 μF capacitor in parallel with a
39 kΩ resistor (see Figure 44). CLK+ can be directly driven
from a CMOS gate. This input is designed to withstand input
voltages up to 3.6 V, making the selection of the drive logic
voltage very flexible. When driving CLK+ with a 1.8 V CMOS
signal, biasing the CLK− pin with a 0.1 μF capacitor in parallel
with a 39 kΩ resistor (see Figure 44) is required. The 39 kΩ
resistor is not required when driving CLK+ with a 3.3 V CMOS
signal (see Figure 45).
Rev. 0 | Page 1ꢀ of 40
AD9254
POWER DISSIPATION AND STANDBY MODE
The DCS can be enabled or disabled by setting the SDIO/DCS
pin when operating in the external pin mode (see Table 10), or
via the SPI, as described in Table 13.
The power dissipated by the AD9254 is proportional to its sample
rate (see Figure 47). The digital power dissipation is determined
primarily by the strength of the digital drivers and the load on each
output bit. Maximum DRVDD current (IDRVDD) can be calculated as
Table 10. Mode Selection (External Pin Mode)
Voltage at Pin
SCLK/DFS
SDIO/DCS
AGND
AVDD
Binary (default)
Twos complement
DCS disabled
DCS enabled
(default)
fCLK
2
IDRVDD = VDRVDD ×CLOAD
×
× N
where N is the number of output bits, 14 in the AD9254.
JITTER CONSIDERATIONS
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, fCLK/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load
presented to the output drivers can minimize digital power
consumption. The data in Figure 47 was taken under the same
operating conditions as the data for the Typical Performance
Characteristics section, with a 5 pF load on each output driver.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fIN) due to jitter (tJ) is calculated as follows:
SNR = −20 log (2π × fIN × tJ)
In the equation, the rms aperture jitter represents the root mean
square of all jitter sources, which include the clock input, analog
input signal, and ADC aperture jitter specification. IF under-
sampling applications are particularly sensitive to jitter, as
shown in Figure 46.
500
480
460
440
420
400
380
360
340
320
300
300
250
200
150
100
50
75
0.05ps
70
I (AVDD)
POWER
MEASURED
PERFORMANCE
65
60
55
50
45
40
0.20ps
0.5ps
1.0ps
1.50ps
2.00ps
2.50ps
3.00ps
I (DRVDD)
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
1
10
100
1000
CLOCK FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 47. AD9254 Power and Current vs. Clock Frequency fIN = 30 MHz
Figure 46. SNR vs. Input Frequency and Jitter
Power-Down Mode
Treat the clock input as an analog signal in cases where aperture
jitter can affect the dynamic range of the AD9254. Power supplies
for clock drivers should be separated from the ADC output
driver supplies to avoid modulating the clock signal with digital
noise. The power supplies should also not be shared with analog
input circuits, such as buffers, to avoid the clock modulating onto
the input signal or vice versa. Low jitter, crystal-controlled oscil-
lators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing, or other methods),
it should be retimed by the original clock at the last step.
By asserting the PDWN pin high, the AD9254 is placed in power-
down mode. In this state, the ADC typically dissipates 1.8 mW.
During power-down, the output drivers are placed in a high
impedance state. Reasserting the PDWN pin low returns the
AD9254 to its normal operational mode. This pin is both 1.8 V
and 3.3 V tolerant.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in power-down mode;
and shorter power-down cycles result in proportionally shorter
wake-up times. With the recommended 0.1 μF decoupling capaci-
tors on REFT and REFB, it takes approximately 0.25 ms to fully
discharge the reference buffer decoupling capacitors and 0.35 ms to
restore full operation.
Refer to Application Notes AN-501, Aperture Uncertainty and
ADC System Performance; and AN-756, Sampled Systems and
the Effects of Clock Phase Noise and Jitter, for more in-depth
information about jitter performance as it relates to ADCs.
Rev. 0 | Page 19 of 40
AD9254
Standby Mode
By logically AND’ing the OR bit with the MSB and its complement,
overrange high or underrange low conditions can be detected.
Table 11 is a truth table for the overrange/underrange circuit in
Figure 49, which uses NAND gates.
When using the SPI port interface, the user can place the ADC
in power-down or standby modes. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required (see the Memory Map section).
MSB
OVER = 1
OR
DIGITAL OUTPUTS
UNDER = 1
MSB
The AD9254 output drivers can be configured to interface with
1.8 V to 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
Figure 49. Overrange/Underrange Logic
Table 11. Overrange/Underrange Truth Table
OR
0
0
1
MSB
Analog Input Is:
Within range
Within range
Underrange
Overrange
0
1
0
1
1
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operat-
ing in the external pin mode (see Table 10). As detailed in the
Interfacing to High Speed ADCs via SPI user manual, the data
format can be selected for either offset binary, twos complement,
or Gray code when using the SPI control.
Digital Output Enable Function (OEB)
The AD9254 has three-state ability. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the
output data drivers are placed in a high impedance state. This is
not intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.
Out-of-Range (OR) Condition
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same
pipeline latency as the digital data.
TIMING
The lowest typical conversion rate of the AD9254 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
The AD9254 provides latched data outputs with a pipeline delay
of twelve clock cycles. Data outputs are available one propaga-
tion delay (tPD) after the rising edge of the clock signal.
+FS – 1 LSB
OR DATA OUTPUTS
1
0
0
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
OR
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9254. These transients can degrade the dynamic performance
of the converter.
–FS + 1/2 LSB
0
0
1
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
–FS
–FS – 1/2 LSB
+FS
Data Clock Output (DCO)
+FS – 1/2 LSB
Figure 48. OR Relation to Input Voltage and Output Data
The AD9254 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are valid
on the rising edge of DCO, unless the DCO clock polarity has been
changed via the SPI. See Figure 2 for a graphical timing
description.
OR is low when the analog input voltage is within the analog
input range and high when the analog input voltage exceeds the
input range, as shown in Figure 48. OR remains high until the
analog input returns to within the input range and another
conversion is completed.
Table 12. Output Data Format
Gray Code Mode
(SPI Accessible)
Input (V)
Condition (V)
< –VREF – 0.5 LSB
= –VREF
Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
OR
1
0
0
0
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
11 0000 0000 0000
11 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
10 0000 0000 0000
= 0
= +VREF – 1.0 LSB
> +VREF – 0.5 LSB
1
Rev. 0 | Page 20 of 40
AD9254
SERIAL PORT INTERFACE (SPI)
The AD9254 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
This provides the user added flexibility and customization
depending on the application. Addresses are accessed via the
serial port and may be written to or read from via the port.
Memory is organized into bytes that are further divided into
fields, as documented in the Memory Map section. For detailed
operational information, see the Interfacing to High Speed ADCs
via SPI user manual.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip as well as read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data
input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.
Data can be sent in MSB- or in LSB-first mode. MSB first is the
default on power-up and can be changed via the configuration
register. For more information, see the Interfacing to High Speed
ADCs via SPI user manual.
CONFIGURATION USING THE SPI
As summarized in Table 13, three pins define the SPI of this
ADC. The SCLK/DFS pin synchronizes the read and write data
presented to the ADC. The SDIO/DCS dual-purpose pin allows
data to be sent to and read from the internal ADC memory map
registers. The CSB pin is an active low control that enables or
disables the read and write cycles.
Table 14. SPI Timing Diagram Specifications
Name
Description
tDS
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
tDH
tCLK
tS
tH
Table 13. Serial Port Interface Pins
Pin Name Function
SCLK/DFS SCLK (serial clock) is the serial shift clock in. SCLK
synchronizes serial interface reads and writes.
SDIO/DCS SDIO (serial data input/output) is a dual-purpose
pin. The typical role for this pin is an input and
tHI
Minimum period that SCLK should be in a logic
high state
tLO
Minimum period that SCLK should be in a logic
low state
HARDWARE INTERFACE
output, depending on the instruction being sent
and the relative position in the timing frame.
The pins described in Table 13 comprise the physical interface
between the user’s programming device and the serial port of
the AD9254. The SCLK and CSB pins function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
CSB
CSB (chip select bar) is an active-low control that
gates the read and write cycles.
The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing. Figure 50 and
Table 14 provide examples of the serial timing and its definitions.
The SPI interface is flexible enough to be controlled by either
PROM or PIC microcontrollers. This provides the user with the
ability to use an alternate method to program the ADC. One
method is described in detail in Application Note AN-812,
Microcontroller-Based Serial Port Interface Boot Circuit.
Other modes involving the CSB are available. The CSB can be
held low indefinitely to permanently enable the device (this is
called streaming). The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in a high impedance mode. This mode
turns on any SPI pin secondary functions.
When the SPI interface is not used, some pins serve a dual
function. When strapped to AVDD or ground during device
power on, the pins are associated with a specific function.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase and the length is determined
by the W0 bit and the W1 bit. All data is composed of 8-bit
words. The first bit of each individual byte of serial data
indicates whether a read or write command is issued. This
allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS and SCLK/DFS pins serve as stand-alone
CMOS-compatible control pins. When the device is powered
up, it is assumed that the user intends to use the pins as static
control lines for the output data format and duty cycle stabilizer
(see Table 10). In this mode, the CSB chip select should be
connected to AVDD, which disables the serial port interface.
For more information, see the Interfacing to High Speed ADCs
via SPI user manual.
Rev. 0 | Page 21 of 40
AD9254
Default Values
MEMORY MAP
Coming out of reset, critical registers are loaded with default
values. The default values for the registers are shown in
Table 15.
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight address
locations. The memory map is roughly divided into three
sections: the chip configuration registers map (Address 0x00 to
Address 0x02), the device index and transfer registers map
(Address 0xFF), and the ADC functions map (Address 0x08 to
Address 0x18).
Logic Levels
An explanation of two registers follows:
•
“Bit is set” is synonymous with “Bit is set to Logic 1” or
“Writing Logic 1 for the bit.”
Table 15 displays the register address number in hexadecimal in
the first column. The last column displays the default value for
each hexadecimal address. The Bit 7 (MSB) column is the start
of the default hexadecimal value given. For example,
•
“Clear a bit” is synonymous with “Bit is set to Logic 0” or
“Writing Logic 0 for the bit.”
SPI-Accessible Features
Hexadecimal Address 0x14, output_phase, has a hexadecimal
default value of 0x00. This means Bit 3 = 0, Bit 2 = 0, Bit 1 = 1,
and Bit 0 = 1 or 0011 in binary. This setting is the default output
clock or DCO phase adjust option. The default value adjusts the
DCO phase 90° relative to the nominal DCO edge and 180°
relative to the data edge. For more information on this function,
consult the Interfacing to High Speed ADCs via SPI user manual.
A list of features accessible via the SPI and a brief description of
what the user can do with these features follows. These features
are described in detail in the Interfacing to High Speed ADCs via
SPI user manual.
•
•
•
•
•
Modes: Set either power-down or standby mode.
Clock: Access the DCS via the SPI.
Open Locations
Offset: Digitally adjust the converter offset.
Test I/O: Set test modes to have known data on output bits.
Locations marked as open are currently not supported for this
device. When required, these locations should be written with
0s. Writing to these locations is required only when part of an
address location is open (for example, Address 0x14). If the
entire address location is open (Address 0x13), then the address
location does not need to be written.
Output Mode: Setup outputs, vary the strength of the
output drivers.
•
•
Output Phase: Set the output clock polarity.
VREF: Set the reference voltage.
tDS
tHI
tCLK
tH
tS
tDH
tLO
CSB
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
Figure 50. Serial Port Interface Timing Diagram
Rev. 0 | Page 22 of 40
AD9254
MEMORY MAP REGISTER TABLE
Table 15. Memory Map Register
Default
Value
(Hex)
Addr.
Bit 7
Bit 0
(LSB)
Default Notes/
Comments
(Hex) Parameter Name (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Chip Configuration Registers
00
chip_port_config
0
LSB first
Soft
reset
1
1
Soft
reset
LSB first
0
0x1ꢀ
The nibbles
should be
0 = Off
0 = Off
mirrored. See
the Interfacing to
High Speed ADCs
via SPI user
(Default)
0 = Off
(Default)
0 = Off
(Default)
(Default)
1 = On
1 = On
1 = On
1 = On
manual.
01
02
chip_id
ꢀ-bit Chip ID Bits 7:0
(AD±2ꢂ4 = 0x00), (default)
Read
only
Default is unique
chip ID, different
for each device.
chip_grade
Open
Open
Open
Open
Open
Child ID
0 = 1ꢂ0
MSPS
Open
Open
Open
Open
Open
Read
only
Child ID used to
differentiate
speed grades.
Device Index and Transfer Registers
FF
device_update
Open
Open
Open
Open
SW
transfer
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
Global ADC Functions
0ꢀ modes
Open
Open
PDWN
Open
Open
Internal power-down mode
000—normal (power-up)
001—full power-down
010—standby
0x00
Determines
various generic
modes of chip
operation. See
the Power
0—Full
1—
Standby
011—normal (power-up)
Note: External PDWN pin
overrides this setting.
Dissipation and
Standby Mode
and the SPI-
Accessible
Features
sections.
0±
clock
Open
Open
Open
Open
Open
Open
Open
Duty
cycle
stabilizer
0—
disabled
1—
0x01
See the Clock
Duty Cycle
section and the
SPI-Accessible
Features section.
enabled
Rev. 0 | Page 23 of 40
AD9254
Default Default
Addr.
(Hex)
Bit 7
Parameter Name (MSB)
Flexible ADC Functions
Bit 0
(LSB)
Value
(Hex)
Notes/
Comments
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
10
offset
Digital Offset Adjust<5:0>
Offset in LSBs
0x00
Adjustable for
offset inherent
in the
converter. See
SPI-
Accessible
Features
section.
011111
011110
011101
…
000010
000001
000000
111111
111110
111101
...
+31
+30
+2±
+2
+1
0 (Default)
1
−2
−3
100001
100000
−31
−32
0D
test_io
PN23
PN±
Global Output Test Options
000—off
0x00
See the
0 = normal 0 = normal
(Default)
1 = reset
Interfacing to
High Speed
ADCs via SPI
user manual.
(Default)
1 = reset
001—midscale short
010—+FS short
011—−FS short
100—checker board output
101—PN 23 sequence
110—PN ±
111—one/zero word toggle
14
output_mode
Output Driver
Configuration
Open
Output
Disable
1—
Open Output
Data
Data Format Select
00—offset binary
(default)
01—twos
complement
10—Gray Code
0x00
Configures the
outputs and
the format of
the data.
Invert
1 =
invert
00 for DRVDD = 2.ꢂ V to
3.3 V
disabled
0—
10 for DRVDD = 1.ꢀ V
enabled1
1ꢁ
1ꢀ
output_phase
VREF
Output Clock
Polarity
1 = inverted
0 = normal
(Default)
Open
Open
Open
Open
Open Open
Open Open
Open
Open
0x00
0xC0
See the SPI-
Accessible
Features
section.
Internal Reference
Resistor Divider
Open
Open
Open
See the SPI-
Accessible
Features
section.
00—VREF = 1.2ꢂ V
01—VREF = 1.ꢂ V
10—VREF = 1.7ꢂ V
11—VREF = 2.00 V
(Default)
1 External output enable (OEB) pin must be high.
Rev. 0 | Page 24 of 40
AD9254
LAYOUT CONSIDERATIONS
POWER AND GROUND RECOMMENDATIONS
SILKSCREEN PARTITION
PIN 1 INDICATOR
When connecting power to the AD9254, it is recommended
that two separate supplies be used: one for analog (AVDD, 1.8 V
nominal) and one for digital (DRVDD, 1.8 V to 3.3 V nominal).
If only a single 1.8 V supply is available, it is routed to AVDD
first, then tapped off and isolated with a ferrite bead or filter
choke with decoupling capacitors proceeding connection to
DRVDD. The user can employ several different decoupling
capacitors to cover both high and low frequencies. These should
be located close to the point of entry at the PC board level and
close to the parts with minimal trace length.
Figure 51. Typical PCB Layout
CML
The CML pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 33.
A single PC board ground plane is sufficient when using the
AD9254. With proper decoupling and smart partitioning of
analog, digital, and clock sections of the PC board, optimum
performance is easily achieved.
RBIAS
The AD9254 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This resister sets the master current
reference of the ADC core and should have at least a 1ꢀ tolerance.
Exposed Paddle Thermal Heat Slug Recommendations
REFERENCE DECOUPLING
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9254. An
exposed, continuous copper plane on the PCB should mate to
the AD9254 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
The VREF pin should be externally decoupled to ground with a
low ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic low
ESR capacitor. In all reference configurations, REFT and REFB
are bypass points provided for reducing the noise contributed
by the internal reference buffer. It is recommended that an
external 0.1 μF ceramic capacitor be placed across REFT/REFB.
While placement of this 0.1 μF capacitor is not required, the SNR
performance degrades by approximately 0.1 dB without it. All
reference decoupling capacitors should be placed as close to the
ADC as possible with minimal trace lengths.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous plane by overlaying a silkscreen
on the PCB into several uniform sections. This provides several
tie points between the two during the reflow process. Using one
continuous plane with no partitions guarantees only one tie point
between the ADC and PCB. See Figure 51 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see Application Note AN-772,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package.
Rev. 0 | Page 2ꢂ of 40
AD9254
EVALUATION BOARD
The AD9254 evaluation board provides all of the support circuitry
required to operate the ADC in its various modes and configu-
rations. The converter can be driven differentially through a double
balun configuration (default) or through the AD8352 differential
driver. The ADC can also be driven in a single-ended fashion.
Separate power pins are provided to isolate the DUT from the
AD8352 drive circuitry. Each input configuration can be selected
by proper connection of various components (see Figure 53 to
Figure 63). Figure 52 shows the typical bench characterization
setup used to evaluate the ac performance of the AD9254.
When operating the evaluation board in a nondefault condition,
L501, L503, L504, L508, and L509 can be removed to disconnect
the switching power supply. This enables the user to individually
bias each section of the board. Use P501 to connect a different
supply for each section. At least one 1.8 V supply is needed with
a 1 A current capability for AVDD_DUT and DRVDD_DUT;
however, it is recommended that separate supplies be used for
analog and digital. To operate the evaluation board using the
AD8352 option, a separate 5.0 V supply (AMP_VDD) with a
1 A current capability is needed. To operate the evaluation
board using the alternate SPI options, a separate 3.3 V analog
supply is needed, in addition to the other supplies. The 3.3 V
supply (AVDD_3.3V) should have a 1 A current capability as
well. Solder Jumpers J501, J502, and J505 allow the user to
combine these supplies (see Figure 57 for more details).
It is critical that the signal sources used for the analog input and
clock have very low phase noise (<1 ps rms jitter) to realize the
optimum performance of the converter. Proper filtering of the
analog input signal to remove harmonics and lower the integrated
or broadband noise at the input is also necessary to achieve the
specified noise performance.
INPUT SIGNALS
When connecting the clock and analog source, use clean signal
generators with low phase noise, such as Rohde & Schwarz SMHU
or Agilent HP8644 signal generators or the equivalent. Use one
meter long, shielded, RG-58, 50 Ω coaxial cable for making
connections to the evaluation board. Enter the desired frequency
and amplitude for the ADC. Typically, most evaluation boards
from Analog Devices, Inc. can accept a ~2.8 V p-p or 13 dBm
sine wave input for the clock. When connecting the analog
input source, it is recommended to use a multipole, narrow-
band, band-pass filter with 50 Ω terminations. Analog Devices
uses TTE®, Allen Avionics, and K&L® types of band-pass filters.
Connect the filter directly to the evaluation board, if possible.
See Figure 53 to Figure 57 for the complete schematics and
layout diagrams that demonstrate the routing and grounding
techniques that should be applied at the system level.
POWER SUPPLIES
This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output.
Connect the supply to the rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter
jack that connects to the PCB at P500. Once on the PC board,
the 6 V supply is fused and conditioned before connecting to
five low dropout linear regulators that supply the proper bias to
each of the various sections on the board.
OUTPUT SIGNALS
The parallel CMOS outputs interface directly with the Analog
Devices standard single-channel FIFO data capture board
(HSC-ADC-EVALB-SC). For more information on the FIFO
boards and their optional settings, visit www.analog.com/FIFO.
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
6V DC
2A MAX
5.0V
1.8V
2.5V
3.3V
3.3V
3.3V
–
+
–
+
–
+
–
+
–
+
–
+
SWITCHING
POWER
SUPPLY
PC
RUNNING
ADC
ANALYZER
AND SPI
USER
ROHDE & SCHWARZ,
HSC-ADC-EVALB-SC
FIFO DATA
SMHU,
2V p-p SIGNAL
SYNTHESIZER
BAND-PASS
FILTER
AIN
CAPTURE
BOARD
AD9254
EVALUATION BOARD
14-BIT
SOFTWARE
PARALLEL
CMOS
USB
CONNECTION
ROHDE & SCHWARZ,
SMHU,
CLK
2V p-p SIGNAL
SYNTHESIZER
SPI
SPI
SPI
Figure 52. Evaluation Board Connection
Rev. 0 | Page 2ꢁ of 40
AD9254
SCLK/DFS
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
If the SPI port is in external pin mode, the SCLK/DFS pin sets the
data format of the outputs. If the pin is left floating, the pin is
internally pulled down, setting the default condition to binary.
Connecting JP2 Pin 2 and Pin 3 sets the format to twos comple-
ment. If the SPI port is in serial pin mode, connecting JP2 Pin 1
and Pin 2 connects the SCLK pin to the on-board SPI circuitry
(see the Serial Port Interface (SPI) section).
The following is a list of the default and optional settings or
modes allowed on the AD9254 Rev. A evaluation board.
POWER
Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P500.
SDIO/DCS
VIN
If the SPI port is in external pin mode, the SDIO/DCS pin acts
to set the duty cycle stabilizer. If the pin is left floating, the pin is
internally pulled up, setting the default condition to DCS enabled.
To disable the DCS, connect JP3 Pin 2 and Pin 3. If the SPI port
is in serial pin mode, connecting JP3 Pin 1 and Pin 2 connects the
SDIO pin to the on-board SPI circuitry (see the Serial Port
Interface (SPI) section).
The evaluation board is set up for a double balun configuration
analog input with optimum 50 Ω impedance matching out to
70 MHz. For more bandwidth response, the differential capacitor
across the analog inputs can be changed or removed (see Table 8).
The common mode of the analog inputs is developed from the
center tap of the transformer via the CML pin of the ADC (see
the Analog Input Considerations section).
ALTERNATIVE CLOCK CONFIGURATIONS
VREF
A differential LVPECL clock can also be used to clock the ADC
input using the AD9515 (U500). When using this drive option,
the components listed in Table 16 need to be populated. Consult
the AD9515 data sheet for further information.
VREF is set to 1.0 V by tying the SENSE pin to ground via
JP507 (Pin 1 and Pin 2). This causes the ADC to operate in
2.0 V p-p full-scale range. A separate external reference option
is also included on the evaluation board. Connect JP507
between Pin 2 and Pin 3, connect JP501, and provide an external
reference at E500. Proper use of the VREF options is detailed
in the Voltage Reference section.
To configure the analog input to drive the AD9515 instead of
the default transformer option, the following components need
to be added, removed, and/or changed.
1. Remove R507, R508, C532, and C533 in the default clock
path.
RBIAS
RBIAS requires a 10 kΩ resistor (R503) to ground and is used to
set the ADC core bias current.
2. Populate R505 with a 0 Ω resistor and C531 in the default
clock path.
CLOCK
3. Populate R511, R512, R513, R515 to R524, U500, R580,
R582, R583, R584, C536, C537, and R586.
The default clock input circuitry is derived from a simple
transformer-coupled circuit using a high bandwidth 1:1
impedance ratio transformer (T503) that adds a very low amount
of jitter to the clock path. The clock input is 50 Ω terminated
and ac-coupled to handle single-ended sine wave inputs. The
transformer converts the single-ended input to a differential
signal that is clipped before entering the ADC clock inputs.
If using an oscillator, two oscillator footprint options are also
available (OSC500) to check the performance of the ADC.
JP508 provides the user flexibility in using the enable pin, which
is common on most oscillators. Populate OSC500, R575, R587,
and R588 to use this option.
PDWN
ALTERNATIVE ANALOG INPUT DRIVE
CONFIGURATION
To enable the power-down feature, connect JP506, shorting the
PDWN pin to AVDD.
This section provides a brief description of the alternative
analog input drive configuration using the AD8352. When
using this particular drive option, some components need to be
populated, as listed in Table 16. For more details on the AD8352
differential driver, including how it works and its optional pin
settings, consult the AD8352 data sheet.
CSB
The CSB pin is internally pulled-up, setting the chip into
external pin mode, to ignore the SDIO and SCLK information.
To connect the control of the CSB pin to the SPI circuitry on the
evaluation board, connect JP1 Pin 1 and Pin 2. To set the chip
into serial pin mode, and enable the SPI information on the
SDIO and SCLK pins, tie JP1 low (connect Pin 2 and Pin 3) in
the always enabled mode.
Rev. 0 | Page 27 of 40
AD9254
Note that to terminate the input path, only one of the
following components should be populated: R9, R592, or
the combination of R590 and R591).
To configure the analog input to drive the AD8352 instead of
the default transformer option, the following components need
to be added, removed, and/or changed:
4. Populate C529 with a 5 pF capacitor in the analog input
path.
1. Remove C1 and C2 in the default analog input path.
2. Populate R3 and R4 with 200 Ω resistors in the analog
input path.
Currently, R561 and R562 are populated with 0 Ω resistors to
allow signal connection. This area allows the user to design a
filter if additional requirements are necessary.
3. Populate the optional amplifier input path with all
components except R594, R595, and C502.
Rev. 0 | Page 2ꢀ of 40
AD9254
SCHEMATICS
2 1 8 2 S M H S
2
0 4 C 0 R
2 1 8 2 S M H S
2
0 4 C 0 R
RC040
2
RC040 2
2
0 4 C 0 R
0 4 0 R 2 C
0 4 0 C 2 C
4 0 2 C C 0
4 0 2 C C 0
0 4 0 C 2 C
RC0603
RC060 3
RC060
3
RC060
3
Figure 53. Evaluation Board Schematic, DUT Analog Inputs
Rev. 0 | Page 2± of 40
AD9254
RC0603
Figure 54. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface
Rev. 0 | Page 30 of 40
AD9254
0 4 C 0 C 2
2 0 4 0 C C
0 4 C 0 C 2
0 2 0 4 C C
0 4 C 0 R 2
0 4 C 0 R 2
0 4 C 0 R 2
0 4 C 0 C 2
0 4 C 0 C 2
0 4 C 0 R 2
0
S 1
S 9
S 8
S 7
S 6
S 5
S 4
S 3
S 2
S 1
S 0
2 5
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
33
31
GND_PAD
GN D
8
7
E F V R
6
32
RSET
0 4 C 0 R 2
0 4 C 0 R 2
0 4 C 0 R 2
2 0 4
R C 0
0 2 0 4 C R
0 2 0 4 C R
RC060 3
0 4 C 0 R 2
0 4 C 0 C 2
0 4 C 0 C 2
RC060 3
RC060 3
Figure 55. Evaluation Board Schematic, DUT Clock Input
Rev. 0 | Page 31 of 40
AD9254
3 0 6
3 0 6
R C 0
R C 0
RC0603
3 0 6
R C 0
3 0 6
R C 0
3 0 6
R C 0
3 0 6
R C 0
SDO_CHA
3 0 6
3 0 6
3 0 6
R C 0
R C 0
R C 0
CSB1_CHA
SDI_CHA
SCLK_CHA
PICVCC 1
2
PICVCC
GP1
3
4
GP1
5
6
GP0
GP0
MCLR-GP3 7
9
8
MCLR-GP3
10
3 0 6 R C 0
Figure 56. Evaluation Board Schematic, SPI Circuitry
Rev. 0 | Page 32 of 40
AD9254
9
2
1
0
5 0 T P
5 1 T P
5 1 T P
5 1 T P
D
G N
D G N
1
1
D
G N
D
G N
D G N
1
1
1
CR500
1
2
Figure 57. Evaluation Board Schematic, Power Supply Inputs
Rev. 0 | Page 33 of 40
AD9254
EVALUATION BOARD LAYOUT
Figure 58. Evaluation Board Layout, Primary Side
Figure 59. Evaluation Board Layout, Secondary Side (Mirrored Image)
Rev. 0 | Page 34 of 40
AD9254
Figure 60. Evaluation Board Layout, Ground Plane
Figure 61. Evaluation Board Layout, Power Plane
Rev. 0 | Page 3ꢂ of 40
AD9254
Figure 62. Evaluation Board Layout, Silkscreen Primary Side
Figure 63. Evaluation Board Layout, Silkscreen Secondary Side (Mirrored Image)
Rev. 0 | Page 3ꢁ of 40
AD9254
BILL OF MATERIALS
Table 16. Evaluation Board Bill of Materials (BOM)
Omit
(DNP)
Item
Qty.
1
Reference Designator
Device
PCB
Package
Description
PCB
Supplier/Part Number
1
2
AD±24ꢁCE_REVA
ADI
24
C1, C2, Cꢂ0±, Cꢂ10, Cꢂ11, Cꢂ12,
Cꢂ14, Cꢂ1ꢂ, Cꢂ1ꢁ, Cꢂ17, Cꢂ2ꢀ,
Cꢂ30, Cꢂ32, Cꢂ33, Cꢂ3ꢀ, Cꢂ3±,
Cꢂ40, Cꢂ42, Cꢂ43, Cꢂ44, Cꢂ4ꢂ,
Cꢂ4ꢁ, Cꢂꢂ4, Cꢂꢂꢂ
Capacitor
0402
0.1 ꢃF
12
C3, Cꢂ00, Cꢂ02, Cꢂ03, Cꢂ04,
Cꢂ0ꢂ, Cꢂ31, Cꢂ34, Cꢂ3ꢂ, Cꢂ3ꢁ,
Cꢂ37, Cꢂꢂ7
3
4
ꢂ
1
2
Cꢂ01
Capacitor
Resistor
0402
0402
0402
0.3 pF
0 Ω
C4, Cꢂ
10
Cꢂ13, Cꢂ1ꢀ, Cꢂ1±, Cꢂ20, Cꢂ21,
Cꢂ22, Cꢂ23, Cꢂ24, Cꢂ2ꢂ, Cꢂ2ꢁ
Capacitor
1.0 ꢃF
ꢁ
1
Cꢂ27
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
120ꢁ
0402
ACASE
0ꢀ0ꢂ
0ꢁ03
10 ꢃF
20 pF
10 ꢃF
1.0 ꢃF
0.1 ꢃF
7
1
Cꢂ2±
ꢀ
ꢂ
Cꢂ4ꢀ, Cꢂ4±, Cꢂꢂ0, Cꢂꢂ1, Cꢂꢂ2
Cꢂꢂ3
±
1
10
1ꢂ
Cꢂꢂꢁ, Cꢂꢂꢀ, Cꢂꢂ±, Cꢂꢁ4, Cꢂꢁꢂ,
Cꢂꢁꢁ, Cꢂꢁ7, Cꢂꢁꢀ, Cꢂꢁ±, Cꢂ70,
Cꢂ72, Cꢂ73, Cꢂ74, Cꢂ7ꢂ, Cꢂ±±
11
12
1
1
CRꢂ00
LED
0ꢁ03
green
Panasonic
LNJ314GꢀTRA
Dꢂ02
Diode
SOT-23
30 V, 20 mA,
HSMS2ꢀ12
dual Schottky
2
1
Dꢂ00, Dꢂ01
Dꢂ03
13
14
1
1
Diode
Diode
DO-214AB
DO-214AA
3 A, 30 V, SMC
2 A, ꢂ0 V, SMC
AMB
Micro Commercial
Components SK33-
TPMSCT-ND
Dꢂ04
Micro Commercial
Components S2A-
TPMSTR-ND
1ꢂ
1ꢁ
Dꢂ0ꢂ
Fꢂ00
LED
LN14ꢁ1C
1210
Amber LED
1
1
Fuse
ꢁ.0 V, 2.2 A
Tyco, Raychem
NANOSMDC110F-2
trip current
resettable fuse
17
FERꢂ00
Choke
2020
Murata
DLWꢂBSN1±1SQ2
1ꢀ
1±
20
21
22
23
24
1
3
Jꢂ00
Jumper
Solder jumper
Solder jumper
Male header
Male, 2 × ꢂ
Jꢂ01, Jꢂ02, Jꢂ0ꢂ
Jꢂ03
Jumper
Samtec TSW-140-0ꢀ-G-T-RA
Samtec
1
Connector
Connector
Jumper
120 pin
10 pin
3 pin
1
Jꢂ04
3
4
1
JP1, JP2, JP3
JPꢂ00, JPꢂ01, JPꢂ02, JPꢂ0ꢁ
JPꢂ07
Male, straight
Male, straight
Male, straight
Samtec TSW-103-07-G-S
Samtec TSW-102-07-G-S
Samtec TSW-103-07-G-S
Jumper
2 pin
Jumper
3-pin
jumper
2
1
JPꢂ0ꢀ, JPꢂ0±
2ꢂ
10
Lꢂ00, Lꢂ01, Lꢂ02, Lꢂ03, Lꢂ04,
Lꢂ0ꢂ, Lꢂ0ꢁ, Lꢂ07, Lꢂ0ꢀ, Lꢂ0±
Ferrite Bead
3.2 mm ×
2.ꢂ mm ×
1.ꢁ mm
Digikey P±ꢀ11CT-ND
2ꢁ
27
OSCꢂ00
Pꢂ00
Oscillator
Connector
SMT
12ꢂ MHz or
10ꢂ MHz
CTS Reeves CB3LV-3C
Digikey CP-102A-ND
1
PJ-102A
DC power jack
Rev. 0 | Page 37 of 40
AD9254
Omit
(DNP)
Item
2ꢀ
Qty.
Reference Designator
Pꢂ01
Device
Package
10 pin
0402
Description
Male, straight
DNI
Supplier/Part Number
1
ꢁ
Connector
Resistor
Resistor
PTMICRO10
2±
R1, Rꢁ, Rꢂꢁ3, Rꢂꢁꢂ, Rꢂ74, Rꢂ77
R2, Rꢂ, Rꢂꢁ1, Rꢂꢁ2, Rꢂ71
R10, R11, R12, Rꢂ3ꢂ, Rꢂ3ꢁ, Rꢂ7ꢂ
R3, R4
30
ꢂ
2
0402
0 Ω
ꢁ
31
32
33
Resistor
Resistor
Resistor
0402
0ꢁ03
0402
2ꢂ Ω
DNI
DNI
ꢁ
ꢁ
R7, Rꢀ, R±, Rꢂ02, Rꢂ10, Rꢂ11
Rꢂ00, Rꢂ01, Rꢂ7ꢁ, Rꢂ7ꢀ, Rꢂ7±,
Rꢂꢀ1
34
3ꢂ
4
1
Rꢂ03, Rꢂ4ꢀ, Rꢂ4±, Rꢂꢂ0
Resistor
Resistor
0ꢁ03
0ꢁ03
10 kΩ
Rꢂ04
Rꢂ0ꢂ
4±.± Ω
1
3ꢁ
±
Rꢂ0ꢁ, Rꢂ0ꢀ, Rꢂ0±, Rꢂ12, Rꢂꢂ4,
Rꢂꢂꢂ, Rꢂꢂꢁ, Rꢂꢂ7, Rꢂꢁ0
Resistor
0ꢁ03
0 Ω
23
Rꢂ07, Rꢂ13, Rꢂ14, Rꢂ1ꢂ, Rꢂ1ꢁ,
Rꢂ17, Rꢂ1ꢀ, Rꢂ1±, Rꢂ20, Rꢂ21,
Rꢂ22, Rꢂ23, Rꢂ24, Rꢂ2ꢂ, Rꢂ2ꢁ,
Rꢂ27, Rꢂ2ꢀ, Rꢂ2±, Rꢂ30, Rꢂ31,
Rꢂ32, Rꢂ33, Rꢂ34,
37
3ꢀ
3±
40
41
42
43
44
4ꢂ
4ꢁ
47
4ꢀ
4±
ꢂ0
ꢂ1
ꢂ2
ꢂ3
4
1
Rꢂ4ꢂ, Rꢂ4ꢁ, Rꢂ47, Rꢂꢂꢀ
Rꢂꢂ1, Rꢂꢂ2, Rꢂꢂ3
Rꢂꢂ±
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Switch
0ꢁ03
4.7 kΩ
1 kΩ
3
2
0ꢁ03
0ꢁ03
2ꢁ1 Ω
33 Ω
Rꢂꢁꢁ, Rꢂꢁ7
Rꢂꢀ2, Rꢂꢀꢂ, Rꢂ±ꢀ
Rꢂꢀ3, Rꢂꢀ4
Rꢂꢀꢁ
0402
3
2
1
3
0402
100 Ω
240 Ω
4.12 kΩ
10 kΩ
2ꢁ1 Ω
2ꢂ Ω
0402
0402
Rꢂꢀ0, Rꢂꢀ7, Rꢂꢀꢀ
Rꢂꢀ±
0402
1
0ꢁ03
2
1
2
2
1
Rꢂ±0, Rꢂ±1
Rꢂ±2
0402
0402
DNI
Rꢂ±3, Rꢂ±ꢁ
Rꢂ±4, Rꢂ±ꢂ
Rꢂ±7
0402
0 Ω
0402
10 kΩ
4.3 kΩ
22 Ω
0402
1
2
RPꢂ00
RCA74204
RCA7420ꢀ
RPꢂ01, RPꢂ02
S1
22 Ω
1
Momentary
(normally
open)
Panasonic EVQ-PLDA1ꢂ
ꢂ4
2
Sꢂ00, Sꢂ01
Sꢂ02, Sꢂ03
Sꢂ04, Sꢂ0ꢂ
Connector
SMAEDGE
SMA edge
right angle
2
2
ꢂꢂ
ꢂꢁ
Connector
SMA200UP
SM-22
SMA RF ꢂ-pin
upright
2
1
Tꢂ00, Tꢂ01
T1
Transformer
M/A-Com ETC1-1-13
1
ꢂ7
Tꢂ03
Transformer
CDꢂ42
Mini-Circuits ADT1-1WT
1
1
Tꢂ02
ꢂꢀ
ꢂ±
Uꢂ00
IC
IC
32-pin
LFCSP _VQ
Clock
distribution
ADI AD±ꢂ1ꢂBCPZ
1
Uꢂ01
SOT-223
Voltage
ADI ADP333±AKCZ-ꢂ
regulator
Rev. 0 | Page 3ꢀ of 40
AD9254
Omit
(DNP)
Item
Qty.
Reference Designator
Device
Package
Description
Supplier/Part Number
ꢁ0
1
Uꢂ02
IC
SOT-223
Voltage
ADI ADP333±AKCZ-1.ꢀ
regulator
ꢁ1
ꢁ2
ꢁ3
1
2
Uꢂ03
IC
IC
IC
SOT-223
SOT-223
ꢀ-pin SOIC
Voltage
regulator
ADI ADP333±AKCZ-2.ꢂ
ADI ADP333±AKCZ-3.3
Microchip PIC12Fꢁ2±
Uꢂ04, Uꢂ0ꢂ
Uꢂ0ꢁ
Voltage
regulator
1
ꢀ-bit
microcontroller
ꢁ4
ꢁꢂ
ꢁꢁ
1
1
1
Uꢂ07
Uꢂ0ꢀ
Uꢂ0±
IC
IC
IC
SC70
SC70
Dual buffer
Dual buffer
Fairchild NC7WZ1ꢁ
Fairchild NC7WZ07
Fairchild 74VCX1ꢁ2244
4ꢀ-pin
TSSOP
Buffer/line
driver
ꢁ7
1
Uꢂ10
DUT
(AD±2ꢂ4)
4ꢀ-pin
LFCSP_VQ
ADC
ADI AD±2ꢂ4BCPZ
ADI ADꢀ3ꢂ2ACPZ
ꢁꢀ
1
Uꢂ11 (or Zꢂ00)
IC
1ꢁ-pin
LFCSP_VQ
Differential
amplifier
Total
12ꢀ
107
Rev. 0 | Page 3± of 40
AD9254
OUTLINE DIMENSIONS
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
PAD
(BOTTOM VIEW)
4.25
4.10 SQ
3.95
TOP
VIEW
6.75
BSC SQ
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 64. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad (CP-48-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD±2ꢂ4BCPZ-1ꢂ01, 2
AD±2ꢂ4BCPZRL7–1ꢂ01, 2
AD±2ꢂ4-1ꢂ0EBZ1
Temperature Range
–40°C to +ꢀꢂ°C
–40°C to +ꢀꢂ°C
Package Description
Package Option
4ꢀ-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
4ꢀ-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
CP-4ꢀ-3
CP-4ꢀ-3
1 Z = Pb-free part.
2 It is required that the exposed paddle be soldered to the AGND plane to achieve the best electrical and thermal performance.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06216-0-10/06(0)
Rev. 0 | Page 40 of 40
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