AD9259ABCPZ-50_技术文档

Quad, 14-Bit, 50 MSPS

Serial LVDS 1.8 V ADC

Data Sheet

AD9259

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

PDWN

AD9259

T/H

DRVDD

DRGND

4 ADCs integrated into 1 package

98 mW ADC power per channel at 50 MSPS

SNR = 73 dB (to Nyquist)

14

VIN + A

VIN – A

SERIAL

LVDS

D + A

D – A

PIPELINE

ADC

ENOB = 12 bits

SFDR = 84 dBc (to Nyquist)

Excellent linearity

DNL = 0.5 LSB (typical)

INL = 1.5 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power, reduced signal option (similar to IEEE 1596.3)

Data and frame clock outputs

315 MHz full-power analog bandwidth

2 V p-p input voltage range

14

VIN + B

VIN – B

PIPELINE

ADC

SERIAL

LVDS

D + B

D – B

T/H

VIN + C

VIN – C

SERIAL

LVDS

D + C

D – C

PIPELINE

ADC

14

VIN + D

VIN – D

SERIAL

LVDS

D + D

D – D

PIPELINE

ADC

VREF

FCO+

FCO–

SENSE

+

0.5V

–

DATA RATE

REFT

REFB

REF

SELECT

1.8 V supply operation

Serial port control

MULTIPLIER

SERIAL PORT

INTERFACE

DCO+

DCO–

Full-chip and individual-channel power-down modes

Flexible bit orientation

SCLK/DTP

RBIASAGND CSB SDIO/ODM

CLK+ CLK–

Figure 1.

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

The ADC automatically multiplies the sample rate clock for the

appropriate LVDS serial data rate. A data clock output (DCO) for

capturing data on the output and a frame clock output (FCO)

for signaling a new output byte are provided. Individual-channel

power-down is supported and typically consumes less than 2 mW

when all channels are disabled.

APPLICATIONS

Medical imaging and nondestructive ultrasound

Portable ultrasound and digital beam-forming systems

Quadrature radio receivers

Diversity radio receivers

Tape drives

Optical networking

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom user-

defined test patterns entered via the serial port interface (SPI).

Test equipment

GENERAL DESCRIPTION

The AD9259 is available in a RoHS-compliant, 48-lead LFCSP. It is

specified over the industrial temperature range of −40°C to +85°C.

The AD9259 is a quad, 14-bit, 50 MSPS analog-to-digital con-

verter (ADC) with an on-chip sample-and-hold circuit designed

for low cost, low power, small size, and ease of use. The product

operates at a conversion rate of up to 50 MSPS and is optimized for

outstanding dynamic performance and low power in applications

where a small package size is critical.

PRODUCT HIGHLIGHTS

1. Small Footprint. Four ADCs are contained in a small, space-

saving package.

2. Low power of 98 mW/channel at 50 MSPS.

3. Ease of Use. A data clock output (DCO) operates at

frequencies of up to 350 MHz and supports double data

rate (DDR) operation.

4. User Flexibility. The SPI control offers a wide range of flexible

features to meet specific system requirements.

5. Pin-Compatible Family. This includes the AD9287 (8-bit),

AD9219 (10-bit), and AD9228 (12-bit).

The ADC requires a single 1.8 V power supply and LVPECL-/

CMOS-/LVDS-compatible sample rate clock for full performance

operation. No external reference or driver components are

required for many applications.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD9259* PRODUCT PAGE QUICK LINKS

Last Content Update: 06/09/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

TOOLS AND SIMULATIONS

• Visual Analog

• AD9259 IBIS Models

EVALUATION KITS

REFERENCE MATERIALS

• AD9259 Evaluation Board

Technical Articles

DOCUMENTATION

Application Notes

• Matching An ADC To A Transformer

• MS-2210: Designing Power Supplies for High Speed ADC

• AN-1142: Techniques for High Speed ADC PCB Layout

• AN-282: Fundamentals of Sampled Data Systems

• AN-345: Grounding for Low-and-High-Frequency Circuits

DESIGN RESOURCES

• AD9259 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

• AN-501: Aperture Uncertainty and ADC System

Performance

• AN-715: A First Approach to IBIS Models: What They Are

and How They Are Generated

• AN-737: How ADIsimADC Models an ADC

DISCUSSIONS

View all AD9259 EngineerZone Discussions.

• AN-741: Little Known Characteristics of Phase Noise

• AN-742: Frequency Domain Response of Switched-

Capacitor ADCs

SAMPLE AND BUY

Visit the product page to see pricing options.

• AN-756: Sampled Systems and the Effects of Clock Phase

Noise and Jitter

• AN-807: Multicarrier WCDMA Feasibility

• AN-808: Multicarrier CDMA2000 Feasibility

TECHNICAL SUPPORT

Submit a technical question or find your regional support

number.

• AN-812: MicroController-Based Serial Port Interface (SPI)

Boot Circuit

• AN-827: A Resonant Approach to Interfacing Amplifiers to

Switched-Capacitor ADCs

DOCUMENT FEEDBACK

Submit feedback for this data sheet.

• AN-835: Understanding High Speed ADC Testing and

Evaluation

• AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

• AN-935: Designing an ADC Transformer-Coupled Front

End

Data Sheet

• AD9259: Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC

Data Sheet

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AD9259

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Analog Input Considerations ................................................... 19

Clock Input Considerations...................................................... 21

Serial Port Interface (SPI).............................................................. 29

Hardware Interface..................................................................... 29

Memory Map .................................................................................. 31

Reading the Memory Map Table.............................................. 31

Reserved Locations .................................................................... 31

Default Values............................................................................. 31

Logic Levels................................................................................. 31

Evaluation Board ............................................................................ 35

Power Supplies............................................................................ 35

Input Signals................................................................................ 35

Output Signals ............................................................................ 35

Default Operation and Jumper Selection Settings................. 36

Alternative Analog Input Drive Configuration...................... 37

Outline Dimensions....................................................................... 51

Ordering Guide .......................................................................... 51

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 7

Timing Diagrams.......................................................................... 8

Absolute Maximum Ratings.......................................................... 10

Thermal Impedance................................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Equivalent Circuits ......................................................................... 13

Typical Performance Characteristics ........................................... 15

Theory of Operation ...................................................................... 19

Rev. E | Page 2 of 52

Data Sheet

AD9259

REVISION HISTORY

Changes to Figure 2 to Figure 4...............................................................7

Changes to Figure 10...............................................................................12

Changes to Figure 15 to Figure 17, Figure 22, and Figure 31..........14

Changes to Figure 21 and Figure 22 Captions....................................15

Changes to Figure 41...............................................................................19

Changes to Clock Duty Cycle Considerations Section.....................20

Changes to Power Dissipation and Power-Down Mode Section...21

Changes to Figure 50 to Figure 52 Captions.......................................23

Change to Table 8.....................................................................................23

Changes to Table 9 Endnote ..................................................................24

Changes to Digital Outputs and Timing Section...............................25

Added Table 10.........................................................................................25

Changes to RBIAS Pin Section..............................................................26

Deleted Figure 53 and Figure 54...........................................................26

Changes to Figure 56...............................................................................27

Changes to Hardware Interface Section ..............................................28

Added Figure 57.......................................................................................29

Changes to Table 15.................................................................................29

Changes to Reading the Memory Map Table Section ......................30

Change to Output Signals Section........................................................34

Changes to Figure 60...............................................................................34

Changes to Default Operation and

12/11—Rev. D to Rev. E

Changes to Output Signals Section and Figure 60......................35

Change to Default Operation and Jumper Selection Settings

Section ..............................................................................................36

Change to Figure 63........................................................................39

Added Endnote 2 in Ordering Guide...........................................51

4/10—Rev. C to Rev. D

Changes to Table 16 ........................................................................33

Updated Outline Dimensions........................................................51

Changes to Ordering Guide...........................................................51

11/09—Rev. B to Rev. C

Added EPAD Note to Figure 5 ......................................................11

Changes to Input Signals Section and Figure 60.........................35

Updated Outline Dimensions........................................................51

Changes to Ordering Guide...........................................................51

7/07—Rev. A to Rev. B

Change to General Description.......................................................1

Changes to Figure 2 and Figure 4....................................................7

Changes to the Hardware Interface Section ................................29

Changes to Table 17 ........................................................................48

Jumper Selection Settings Section ...................................................35

Changes to Alternative Analog Input Drive

Configuration Section........................................................................36

Changes to Figure 63...............................................................................38

Changes to Table 17.................................................................................46

Changes to Ordering Guide...................................................................50

5/07—Rev. 0 to Rev. A

Changes to Effective Number of Bits (ENOB)..................................... 4

Changes to Logic Output (SDIO/ODM) .............................................. 5

Added Endnote 3 to Table 3..................................................................... 5

Change to Pipeline Latency ..................................................................... 6

6/06—Revision 0: Initial Version

Rev. E | Page 3 of 52

AD9259

Data Sheet

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.

Parameter¹

Temperature

Min

Typ

Max

Unit

RESOLUTION

14

Bits

ACCURACY

No Missing Codes

Offset Error

Offset Matching

Gain Error

Full

Guaranteed

±1

±2

±0.5

±0.3

±±

mV

±±

mV

±2

% FS

LSB

Gain Matching

±0.7

±1.0

±3.5

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error

Gain Error

Reference Voltage (1 V Mode)

REFERENCE

±0.5

±1.5

Full

±2

±17

±21

ppm/°C

Output Voltage Error (V_REF= 1 V)

Load Regulation at 1.0 mA (V_REF= 1 V)

Input Resistance

Full

±5

3

6

±30

mV

kΩ

ANALOG INPUTS

Differential Input Voltage (V_REF= 1 V)

Common-Mode Voltage

Differential Input Capacitance

Analog Bandwidth, Full Power

POWER SUPPLY

Full

2

V p-p

V

pF

AVDD/2

7

315

MHz

AVDD

DRVDD

I_AVDD

I_DRVDD

Full

1.7

1.±

1±5

32.5

392

2

1.9

192.5

34.7

409

4

V

mA

mW

dB

Total Power Dissipation (Including Output Drivers)

Power-Down Dissipation

Standby Dissipation²

CROSSTALK

72

−100

CROSSTALK (Overrange Condition)³

dB

¹See the AN-±35 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were

completed.

²Can be controlled via the SPI.

³Overrange condition is specific with 6 dB of the full-scale input range.

Rev. E | Page 4 of 52

Data Sheet

AD9259

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 2.

Parameter¹

Temperature

Min

Typ

Max

Unit

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 2.4 MHz

f_IN= 19.7 MHz

Full

73.5

73.0

72.±

dB

71.0

f_IN= 70 MHz

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

f_IN= 2.4 MHz

f_IN= 19.7 MHz

Full

72.7

72.2

72.0

dB

70.2

11.5

73

f_IN= 70 MHz

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 2.4 MHz

f_IN= 19.7 MHz

Full

11.92

11.±5

11.±

Bits

f_IN= 70 MHz

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_IN= 2.4 MHz

f_IN= 19.7 MHz

Full

±4

7±

dBc

f_IN= 70 MHz

WORST HARMONIC (Second or Third)

f_IN= 2.4 MHz

f_IN= 19.7 MHz

Full

−±±

−±4

−7±

dBc

−73

−±0

f_IN= 70 MHz

WORST OTHER (Excluding Second or Third)

f_IN= 2.4 MHz

f_IN= 19.7 MHz

Full

−90

−±±

dBc

f_IN= 70 MHz

TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1

AND AIN2 = −7.0 dBFS

f_IN1= 15 MHz, f_IN2= 16 MHz

f_IN1= 70 MHz, f_IN2= 71 MHz

25°C

±0.0

dBc

¹See the AN-±35 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were

completed.

Rev. E | Page 5 of 52

AD9259

Data Sheet

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 3.

Parameter¹

Temperature

Min

Typ

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage²

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

Full

25°C

250

mV p-p

V

kΩ

pF

1.2

20

1.5

LOGIC INPUTS (PDWN, SCLK/DTP)

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

Input Capacitance

Full

25°C

1.2

3.6

0.3

V

kΩ

pF

30

0.5

LOGIC INPUT (CSB)

Logic 1 Voltage

Logic 0 Voltage

Full

3.6

0.3

V

Input Resistance

Input Capacitance

25°C

70

0.5

kΩ

pF

LOGIC INPUT (SDIO/ODM)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

0

DRVDD + 0.3

0.3

V

Input Resistance

Input Capacitance

25°C

30

2

kΩ

pF

LOGIC OUTPUT (SDIO/ODM)³

Logic 1 Voltage (I_OH= ±00 μA)

Logic 0 Voltage (I_OL= 50 μA)

DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)

Logic Compliance

Full

1.79

V

0.05

LVDS

Differential Output Voltage (V_OD)

Output Offset Voltage (V_OS)

Output Coding (Default)

Full

247

1.125

454

1.375

mV

V

Offset binary

LVDS

DIGITAL OUTPUTS (D + x, D − x),

(Low Power, Reduced Signal Option)

Logic Compliance

Differential Output Voltage (V_OD)

Output Offset Voltage (V_OS)

Output Coding (Default)

Full

150

1.10

250

1.30

mV

V

Offset binary

¹See the AN-±35 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were

completed.

²This is specified for LVDS and LVPECL only.

³This is specified for 13 SDIO pins sharing the same connection.

Rev. E | Page 6 of 52

Data Sheet

AD9259

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

Parameter^{1, 2}

Temp

Min

Typ

Max

Unit

CLOCK³

Maximum Clock Rate

Minimum Clock Rate

Clock Pulse Width High (t_EH)

Clock Pulse Width Low (t_EL)

OUTPUT PARAMETERS³

Propagation Delay (t_PD)

Rise Time (t_R) (20% to ±0%)

Fall Time (t_F) (20% to ±0%)

FCO Propagation Delay (t_FCO

Full

50

MSPS

ns

10

ns

Full

2.0

2.7

3.5

ns

ps

ns

300

2.7

)

4

DCO Propagation Delay (t_CPD

t_FCO+

(t_SAMPLE/2±)

±50

4

DCO to Data Delay (t_DATA

)

Full

(t_SAMPLE/2±) − 300

(t_SAMPLE/2±) + 300

±150

ps

4

DCO to FCO Delay (t_FRAME

)

Data to Data Skew

(t_DATA-MAX− t_DATA-MIN

)

Wake-Up Time (Standby)

Wake-Up Time (Power-Down)

Pipeline Latency

25°C

Full

600

375

±

ns

μs

CLK

cycles

APERTURE

Aperture Delay (t_A)

Aperture Uncertainty (Jitter)

Out-of-Range Recovery Time

25°C

500

<1

2

ps

ps rms

CLK

cycles

¹See the AN-±35 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were

completed.

²Measured on standard FR-4 material.

³Can be adjusted via the SPI.

⁴t_SAMPLE/2± is based on the number of bits multiplied by 2; delays are based on half duty cycles.

Rev. E | Page 7 of 52

AD9259

Data Sheet

TIMING DIAGRAMS

N – 1

VIN ± x

t_A

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

t_PD

t_DATA

D – x

D + x

MSB

N – 9

D12

D11

D10

D9

D8

D7

D6

N – 9

D5

N – 9

D4

N – 9

D3

N – 9

D2

N – 9

D1

N – 9

D0

N – 9

MSB

N – 8

D12

N – 8

N – 9 N – 9 N – 9 N – 9 N – 9 N – 9

Figure 2. 14-Bit Data Serial Stream, MSB First (Default)

N – 1

VIN ± x

t_A

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

t_PD

t_DATA

D – x

D + x

MSB

N – 9

D10

N – 9

D9

N – 9

D8

N – 9

D7

N – 9

D6

N – 9

D5

N – 9

D4

N – 9

D3

N – 9

D2

N – 9

D1

N – 9

D0

N – 9

MSB

N – 8

D10

N – 8

Figure 3. 12-Bit Data Serial Stream, MSB First

Rev. E | Page 8 of 52

Data Sheet

AD9259

N – 1

VIN ± x

t_A

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

t_PD

t_DATA

D – x

D + x

LSB

N – 9

D0

D1

D2

D3

D4

D5

D6

N – 9

D7

N – 9

D8

N – 9

D9

N – 9

D10

N – 9

D11

N – 9

D12

N – 9

LSB

N – 8

D0

N – 8

N – 9 N – 9 N – 9 N – 9 N – 9 N – 9

Figure 4. 14-Bit Data Serial Stream, LSB First

Rev. E | Page 9 of 52

AD9259

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

Rating

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ELECTRICAL

AVDD to AGND

DRVDD to DRGND

AGND to DRGND

AVDD to DRVDD

Digital Outputs¹to DRGND

CLK+, CLK− to AGND

VIN + x, VIN – x to AGND

SDIO/ODM to AGND

PDWN, SCLK/DTP, CSB to AGND

REFT, REFB, RBIAS to AGND

VREF, SENSE to AGND

ENVIRONMENTAL

Operating Temperature

Range (Ambient)

Maximum Junction

Temperature

−0.3 V to +2.0 V

−0.3 V to +0.3 V

−2.0 V to +2.0 V

−0.3 V to +2.0 V

−0.3 V to +3.9 V

−0.3 V to +2.0 V

−0.3 V to +3.9 V

−0.3 V to +2.0 V

THERMAL IMPEDANCE

Table 6.

Air Flow Velocity (m/sec)

1

θ_JA

24

21

19

θ_JB

θ_JC

Unit

°C/W

0.0

1.0

2.5

12.6

1.2

−40°C to +±5°C

150°C

¹θ_JAfor a 4-layer PCB with solid ground plane (simulated). Exposed pad

soldered to PCB.

Lead Temperature

(Soldering, 10 sec)

300°C

ESD CAUTION

Storage Temperature

Range (Ambient)

−65°C to +150°C

¹Digital outputs include D + x, D − x, DCO+, DCO−, FCO+, FCO−.

Rev. E | Page 10 of 52

Data Sheet

AD9259

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

AVDD

VIN – D

VIN + D

AVDD

CLK–

1

2

36

35

34

33

32

31

30

29

28

27

26

25

AVDD

3

VIN – A

VIN + A

AVDD

EXPOSED PADDLE, PIN 0

(BOTTOM OF PACKAGE)

4

5

6

PDWN

AD9259

TOP VIEW

7

CSB

8

CLK+

SDIO/ODM

SCLK/DTP

AVDD

9

AVDD

DRGND

DRVDD

10

11

12

DRGND

DRVDD

NOTES

1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE

ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO

GROUND FOR PROPER OPERATIONAL.

ꢀ

Figure 5.Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

0

AGND

AVDD

Analog Ground (Exposed Paddle)

1.8 V Analog Supply

1, 2, 5, 6, 9, 10, 27, 32,

35, 36, 39, 45, 46

11, 26

12, 25

3

4

7

DRGND

DRVDD

VIN − D

VIN + D

CLK−

Digital Output Driver Ground

1.8 V Digital Output Driver Supply

ADC D Analog Input Complement

ADC D Analog Input True

Input Clock Complement

8

CLK+

Input Clock True

13

14

15

16

17

18

19

20

21

22

23

24

28

29

D − D

D + D

D − C

D + C

D − B

D + B

D − A

D + A

FCO−

FCO+

DCO−

DCO+

SCLK/DTP

SDIO/ODM

ADC D Digital Output Complement

ADC D Digital Output True

ADC C Digital Output Complement

ADC C Digital Output True

ADC B Digital Output Complement

ADC B Digital Output True

ADC A Digital Output Complement

ADC A Digital Output True

Frame Clock Output Complement

Frame Clock Output True

Data Clock Output Complement

Data Clock Output True

Serial Clock/Digital Test Pattern

Serial Data I/O/Output Driver Mode

Rev. E | Page 11 of 52

AD9259

Data Sheet

Pin No.

30

Mnemonic

CSB

Description

Chip Select Bar

31

33

34

37

3±

40

41

42

43

44

47

4±

PDWN

VIN + A

VIN − A

VIN − B

VIN + B

RBIAS

SENSE

VREF

REFB

Power-Down

ADC A Analog Input True

ADC A Analog Input Complement

ADC B Analog Input Complement

ADC B Analog Input True

External resistor sets the internal ADC core bias current

Reference Mode Selection

Voltage Reference Input/Output

Differential Reference (Negative)

Differential Reference (Positive)

ADC C Analog Input True

REFT

VIN + C

VIN − C

ADC C Analog Input Complement

Rev. E | Page 12 of 52

Data Sheet

AD9259

EQUIVALENT CIRCUITS

DRVDD

V

D–

D+

VIN ± x

V

DRGND

Figure 9. Equivalent Digital Output Circuit

Figure 6. Equivalent Analog Input Circuit

10Ω

CLK+

10kΩ

1.25V

1kΩ

SCLK/DTP

AND PDWN

10Ω

CLK–

30kΩ

Figure 7. Equivalent Clock Input Circuit

Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit

100Ω

RBIAS

350Ω

SDIO/ODM

30kΩ

Figure 11. Equivalent RBIAS Circuit

Figure 8. Equivalent SDIO/ODM Input Circuit

Rev. E | Page 13 of 52

AD9259

Data Sheet

AVDD

70kΩ

1kΩ

CSB

VREF

6kΩ

Figure 12. Equivalent CSB Input Circuit

Figure 14. Equivalent VREF Circuit

1kΩ

SENSE

Figure 13. Equivalent SENSE Circuit

Rev. E | Page 14 of 52

Data Sheet

AD9259

TYPICAL PERFORMANCE CHARACTERISTICS

0

–20

AIN = –0.5dBFS

SNR = 67.31dB

ENOB = 10.89 BITS

SFDR = 77.38dBc

AIN = –0.5dBFS

SNR = 73.8dB

ENOB = 11.97 BITS

SFDR = 83.4dBc

–20

–40

–60

–80

–60

–80

–100

–120

–100

–120

0

5

10

15

20

25

0

5

10

15

20

25

FREQUENCY (MHz)

Figure 15. Single-Tone 32k FFT with f_IN= 2.4 MHz, f_SAMPLE= 50 MSPS

Figure 18. Single-Tone 32k FFT with f_IN= 170 MHz, f_SAMPLE= 50 MSPS

0

AIN = –0.5dBFS

SNR = 66.87dB

ENOB = 10.82 BITS

AIN = –0.5dBFS

SNR = 72.94dB

ENOB = 11.82 BITS

–20

SFDR = 78.60dBc

SFDR = 74.97dBc

–40

–60

–80

–60

–80

–100

–120

–100

–120

0

5

10

15

20

25

0

5

10

15

20

25

FREQUENCY (MHz)

Figure 16. Single-Tone 32k FFT with f_IN= 70 MHz, f_SAMPLE= 50 MSPS

Figure 19. Single-Tone 32k FFT with f_IN= 190 MHz, f_SAMPLE= 50 MSPS

0

AIN = –0.5dBFS

SNR = 71.96dB

AIN = –0.5dBFS

SNR = 65.62dB

ENOB = 10.61 BITS

SFDR = 68.11dBc

ENOB = 11.66 BITS

–20

–40

–20

SFDR = 76.68dBc

–40

–60

–80

–100

–120

–100

–120

0

5

10

15

20

25

0

5

10

15

20

25

FREQUENCY (MHz)

Figure 17. Single-Tone 32k FFT with f_IN= 120 MHz, f_SAMPLE= 50 MSPS

Figure 20. Single-Tone 32k FFT with f_IN= 250 MHz, f_SAMPLE= 50 MSPS

Rev. E | Page 15 of 52

AD9259

Data Sheet

100

90

80

70

60

90

85

80

75

70

65

f_IN= 35MHz

f_SAMPLE= 50MSPS

2V p-p, SFDR

50

40

2V p-p, SNR

30

20

10

0

80dB

REFERENCE

60

10

–60

–50

–40

–30

–20

–10

0

15

20

25

30

35

40

45

50

ANALOG INPUT LEVEL (dBFS)

ENCODE (MSPS)

Figure 24. SNR/SFDR vs. Analog Input Level, f_IN= 35 MHz, f_SAMPLE= 50 MSPS

Figure 21. SNR/SFDR vs. Encode, f_IN= 10.3 MHz, f_SAMPLE= 50 MSPS

0

90

AIN1 AND AIN2 = –7dBFS

SFDR = 87.76dBc

IMD2 = 90.18dBc

–20

85

IMD3 = 87.27dBc

–40

2V p-p, SFDR

80

–60

–80

75

2V p-p, SNR

70

65

60

–100

–120

0

5

10

15

20

25

10

15

20

25

30

35

40

45

50

FREQUENCY (MHz)

ENCODE (MSPS)

Figure 25. Two-Tone 32k FFT with f_IN1= 15 MHz and f_IN2= 16 MHz,

_SAMPLE= 50 MSPS

Figure 22. SNR/SFDR vs. Encode, f_IN= 35 MHz, f_SAMPLE= 50 MSPS

f

100

0

–20

AIN1 AND AIN2 = –7dBFS

SFDR = 80.37dBc

IMD2 = 79.75dBc

f_IN= 10.3MHz

90

f_SAMPLE= 50MSPS

80

IMD3 = 84.50dBc

70

60

2V p-p, SFDR

–40

–60

50

40

2V p-p, SNR

–80

30

20

10

0

80dB

REFERENCE

–100

–120

–60

–50

–40

–30

–20

–10

0

5

10

15

20

25

ANALOG INPUT LEVEL (dBFS)

FREQUENCY (MHz)

Figure 23. SNR/SFDR vs. Analog Input Level, f_IN= 10.3 MHz, f_SAMPLE= 50 MSPS

Figure 26. Two-Tone 32k FFT with f_IN1= 70 MHz and f_IN2= 71 MHz,

_SAMPLE= 50 MSPS

f

Rev. E | Page 16 of 52

Data Sheet

AD9259

90

85

80

75

70

65

60

55

0.5

0.4

2V p-p, SFDR (dBc)

0.3

0.2

0.1

2V p-p, SNR (dB)

0

–0.1

–0.2

–0.3

–0.4

–0.5

50

1

10

100

1000

0

2000 4000 6000 8000 10000 12000 14000 16000

ANALOG INPUT FREQUENCY (MHz)

CODE

Figure 27. SNR/SFDR vs. Analog Input Frequency, f_SAMPLE= 50 MSPS

Figure 30. DNL, f_IN= 2.4 MHz, f_SAMPLE= 50 MSPS

90

–45.0

–45.5

–46.0

–46.5

–47.0

–47.5

–48.0

85

2V p-p, SFDR

80

75

70

65

60

2V p-p, SINAD

–40

–20

0

20

40

60

80

10

15

20

25

30

35

40

45

50

TEMPERATURE (°C)

FREQUENCY (MHz)

Figure 28. SINAD/SFDR vs. Temperature, f_IN= 10.3 MHz, f_SAMPLE= 50 MSPS

Figure 31. CMRR vs. Frequency, f_SAMPLE= 50 MSPS

1.2

2.0

1.5

1.006 LSB rms

1.0

0.8

0.6

0.4

0.2

0

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

N – 3

N – 2

N – 1

N

N + 1

N + 2

N + 3

0

2000 4000 6000 8000 10000 12000 14000 16000

CODE

Figure 29. INL, f_IN= 2.4 MHz, f_SAMPLE= 50 MSPS

Figure 32. Input-Referred Noise Histogram, f_SAMPLE= 50 MSPS

Rev. E | Page 17 of 52

AD9259

Data Sheet

0

–1

–2

–3

–4

–5

–6

–7

NPR = 63.89dB

NOTCH = 18.0MHz

NOTCH WIDTH = 3.0MHz

–20

–3dB CUTOFF = 315MHz

–40

–60

–80

–8

–100

–9

–120

0

–10

5

10

15

20

25

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

Figure 33. Noise Power Ratio (NPR), f_SAMPLE= 50 MSPS

Figure 34. Full-Power Bandwidth vs. Frequency, f_SAMPLE= 50 MSPS

Rev. E | Page 1± of 52

Data Sheet

AD9259

THEORY OF OPERATION

low-Q inductors or ferrite beads is required when driving the

The AD9259 architecture consists of a pipelined ADC divided into

three sections: a 4-bit first stage followed by eight 1.5-bit stages and

a final 3-bit flash. Each stage provides sufficient overlap to correct

for flash errors in the preceding stage. The quantized outputs from

each stage are combined into a final 14-bit result in the digital

correction logic. The pipelined architecture permits the first stage

to operate with a new input sample while the remaining stages

operate with preceding samples. Sampling occurs on the rising

edge of the clock.

converter front end at high IF frequencies. Either a shunt

capacitor or two single-ended capacitors can be placed on the

inputs to provide a matching passive network. This ultimately

creates a low-pass filter at the input to limit unwanted

broadband noise. See the AN-742 Application Note, the AN-827

Application Note, and the Analog Dialogue article “Transformer-

Coupled Front-End for Wideband A/D Converters” (Volume

39, April 2005) for more information at www.analog.com. In

general, the precise values depend on the application.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and an interstage residue amplifier (for example, a multiplying

digital-to-analog converter (MDAC)). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction of

flash errors. The last stage simply consists of a flash ADC.

The analog inputs of the AD9259 are not internally dc-biased.

Therefore, in ac-coupled applications, the user must provide

this bias externally. Setting the device so that V_CM= AVDD/2 is

recommended for optimum performance, but the device can

function over a wider range with reasonable performance, as

shown in Figure 36 and Figure 37.

90

f_IN= 2.3MHz

f_SAMPLE= 50MSPS

SFDR (dBc)

85

80

75

70

65

60

55

50

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. The data is then serialized

and aligned to the frame and data clocks.

ANALOG INPUT CONSIDERATIONS

SNR (dB)

The analog input to the AD9259 is a differential switched-

capacitor circuit designed for processing differential input

signals. This circuit can support a wide common-mode range

while maintaining excellent performance. By using an input

common-mode voltage of midsupply, users can minimize

signal-dependent errors and achieve optimum performance.

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

ANALOG INPUT COMMON-MODE VOLTAGE (V)

Figure 36. SNR/SFDR vs. Common-Mode Voltage,

f_IN= 2.3 MHz, f_SAMPLE= 50 MSPS

H

C

90

85

80

75

70

65

60

55

50

PAR

H

VIN + x

f_IN= 30MHz

f_SAMPLE= 50MSPS

C

SAMPLE

SFDR (dBc)

S

C

SAMPLE

VIN – x

H

C

PAR

SNR (dB)

H

Figure 35. Switched-Capacitor Input Circuit

The clock signal alternately switches the input circuit between

sample mode and hold mode (see Figure 35). When the input

circuit is switched to sample mode, the signal source must be

capable of charging the sample capacitors and settling within

one-half of a clock cycle. A small resistor in series with each

input can help reduce the peak transient current injected from

the output stage of the driving source. In addition, low-Q inductors

or ferrite beads can be placed on each leg of the input to reduce

high differential capacitance at the analog inputs and therefore

achieve the maximum bandwidth of the ADC. Such use of

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

ANALOG INPUT COMMON-MODE VOLTAGE (V)

Figure 37. SNR/SFDR vs. Common-Mode Voltage,

f_IN= 30 MHz, f_SAMPLE= 50 MSPS

Rev. E | Page 19 of 52

AD9259

Data Sheet

ADT1-1WT

1:1 Z RATIO

For best dynamic performance, the source impedances driving

VIN + x and VIN − x should be matched such that common-

mode settling errors are symmetrical. These errors are reduced

by the common-mode rejection of the ADC. An internal

reference buffer creates the positive and negative reference

voltages, REFT and REFB, respectively, that define the span of

the ADC core. The output common-mode of the reference buffer

is set to midsupply, and the REFT and REFB voltages and span

are defined as

C

R

VIN + x

ADC

AD9259

1

2Vp-p

49.9Ω

C

R

DIFF

AVDD

1kΩ

VIN – x

AGND

C

1kΩ

0.1μF

1

C

IS OPTIONAL.

DIFF

Figure 38. Differential Transformer-Coupled Configuration

for Baseband Applications

REFT = 1/2 (AVDD + VREF)

REFB = 1/2 (AVDD − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

ADT1-1WT

1:1 Z RATIO

2Vp-p

16nH

16nH 0.1μF

33Ω

VIN + x

65Ω

ADC

It can be seen from these equations that the REFT and REFB

voltages are symmetrical about the midsupply voltage and, by

definition, the input span is twice the value of the VREF voltage.

499Ω

16nH

2.2pF

1kΩ

AD9259

33Ω

VIN – x

AVDD

1kΩ

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. In the case of the

AD9259, the largest input span available is 2 V p-p.

0.1μF

1kΩ

Figure 39. Differential Transformer-Coupled Configuration

for IF Applications

Differential Input Configurations

Single-Ended Input Configuration

There are several ways to drive the AD9259 either actively or

passively; however, optimum performance is achieved by driving

the analog input differentially. For example, using the AD8332

differential driver to drive the AD9259 provides excellent perfor-

mance and a flexible interface to the ADC (see Figure 41) for

baseband applications. This configuration is commonly used

for medical ultrasound systems.

A single-ended input may provide adequate performance in cost-

sensitive applications. In this configuration, SFDR and distortion

performance degrade due to the large input common-mode swing.

If the application requires a single-ended input configuration,

ensure that the source impedances on each input are well matched

in order to achieve the best possible performance. A full-scale

input of 2 V p-p can be applied to the ADC’s VIN + x pin while

the VIN − x pin is terminated. Figure 40 details a typical single-

ended input configuration.

For applications where SNR is a key parameter, differential

transformer coupling is the recommended input configuration

(see Figure 38 and Figure 39), because the noise performance of

most amplifiers is not adequate to achieve the true performance

of the AD9259.

AVDD

C

R

VIN + x

0.1µF

AVDD

1kΩ

Regardless of the configuration, the value of the shunt capacitor,

C, is dependent on the input frequency and may need to be

reduced or removed.

2V p-p

49.9Ω

ADC

1

C

DIFF

AD9259

1kΩ

25Ω

R

C

VIN – x

0.1µF

1kΩ

1

C

IS OPTIONAL.

DIFF

Figure 40. Single-Ended Input Configuration

0.1μF

LOP

VIP

AVDD

10kΩ

33Ω

680nH

68pF

187Ω

VOH

VOL

0.1μF 120nH

INH

VIN + x

1V p-p

AD8332

10kΩ

AVDD

1kΩ

22pF

+

ADC

AD9259

LNA

VGA

10kΩ

33Ω

LMD

VIN – x

0.1μF

680nH

LPF

LON

VIN

274Ω

18nF

0.1μF

Figure 41. Differential Input Configuration Using the AD8332 with Two-Pole, 16 MHz Low-Pass Filter

Rev. E | Page 20 of 52

Data Sheet

AD9259

CLK+ input circuit supply is AVDD (1.8 V), this input is

designed to withstand input voltages of up to 3.3 V and

therefore offers several selections for the drive logic voltage.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9259 sample clock inputs

(CLK+ and CLK−) should be clocked with a differential signal.

This signal is typically ac-coupled to the CLK+ and CLK− pins

via a transformer or capacitors. These pins are biased internally

and require no additional biasing.

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

0.1µF

CLK+

CLK

OPTIONAL

100Ω

0.1µF

1

50Ω

CLK+

CMOS DRIVER

CLK

Figure 42 shows a preferred method for clocking the AD9259. The

low jitter clock source is converted from a single-ended signal

to a differential signal using an RF transformer. The back-to-

back Schottky diodes across the secondary transformer limit

clock excursions into the AD9259 to approximately 0.8 V p-p

differential. This helps prevent the large voltage swings of the

clock from feeding through to other portions of the AD9259,

and it preserves the fast rise and fall times of the signal, which

are critical to low jitter performance.

ADC

AD9259

0.1µF

CLK–

0.1µF

39kΩ

1

50Ω RESISTOR IS OPTIONAL.

Figure 45. Single-Ended 1.8 V CMOS Sample Clock

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

0.1µF

CLK+

CLK

OPTIONAL

100Ω

0.1µF

1

50Ω

®

Mini-Circuits

CLK+

CMOS DRIVER

CLK

ADT1-1WT, 1:1Z

ADC

AD9259

0.1µF

XFMR

CLK+

0.1µF

100Ω

ADC

AD9259

CLK–

50Ω

CLK–

0.1µF

1

50Ω RESISTOR IS OPTIONAL.

SCHOTTKY

DIODES:

HSM2812

0.1µF

Figure 46. Single-Ended 3.3 V CMOS Sample Clock

Figure 42. Transformer-Coupled Differential Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD9259 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9259. When the DCS is on, noise and distortion perfor-

mance are nearly flat for a wide range of duty cycles. However,

some applications may require the DCS function to be off. If so,

keep in mind that the dynamic range performance can be

affected when operated in this mode. See the Memory Map

section for more details on using this feature.

Another option is to ac-couple a differential PECL signal to the

sample clock input pins as shown in Figure 43. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515 of clock drivers

offers excellent jitter performance.

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

0.1µF

CLK+

CLK–

CLK

PECL DRIVER

CLK

CLK+

ADC

AD9259

100Ω

0.1µF

CLK–

1

240Ω

50Ω

1

50Ω RESISTORS ARE OPTIONAL.

Figure 43. Differential PECL Sample Clock

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

Jitter in the rising edge of the input is an important concern, and it

is not reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates of less than

20 MHz nominal. The loop has a time constant associated with

it that must be considered in applications where the clock rate

can change dynamically. This requires a wait time of 1.5 µs to

5 µs after a dynamic clock frequency increase (or decrease)

before the DCS loop is relocked to the input signal. During the

period that the loop is not locked, the DCS loop is bypassed and

the internal device timing is dependent on the duty cycle of the

input clock signal. In such applications, it may be appropriate to

disable the duty cycle stabilizer. In all other applications, enabling

the DCS circuit is recommended to maximize ac performance.

0.1µF

CLK+

CLK–

CLK+

CLK

ADC

AD9259

100Ω

LVDS DRIVER

CLK

0.1µF

CLK–

1

50Ω*

50Ω

1

50Ω RESISTORS ARE OPTIONAL

Figure 44. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

CLK+ should be driven directly from a CMOS gate, and the

CLK− pin should be bypassed to ground with a 0.1 μF capacitor

in parallel with a 39 kΩ resistor (see Figure 45). Although the

Rev. E | Page 21 of 52

AD9259

Data Sheet

Clock Jitter Considerations

Power Dissipation and Power-Down Mode

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency (f_A)

due only to aperture jitter (t_J) can be calculated by

As shown in Figure 48, the power dissipated by the AD9259 is

proportional to its sample rate. The digital power dissipation

does not vary significantly because it is determined primarily by

the DRVDD supply and bias current of the LVDS output drivers.

SNR Degradation = 20 × log 10(1/2 × π × f_A× t_J)

200

180

160

140

120

100

80

500

450

400

350

300

250

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter. IF undersampling applications

are particularly sensitive to jitter (see Figure 47).

AVDD CURRENT

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9259.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators are

the best clock sources. If the clock is generated from another

type of source (by gating, dividing, or another method), it

should be retimed by the original clock during the last step.

TOTAL POWER

60

40

DRVDD CURRENT

20

0

10

15

20

25

30

35

40

45

50

ENCODE (MSPS)

Refer to the AN-501 Application Note and to the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs at www.analog.com.

Figure 48. Supply Current vs. f_SAMPLEfor f_IN= 10.3 MHz, f_SAMPLE= 50 MSPS

130

RMS CLOCK JITTER REQUIREMENT

120

110

16 BITS

100

90

80

70

60

50

40

30

14 BITS

12 BITS

10 BITS

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

1

10

100

1000

ANALOG INPUT FREQUENCY (MHz)

Figure 47. Ideal SNR vs. Input Frequency and Jitter

Rev. E | Page 22 of 52

Data Sheet

AD9259

By asserting the PDWN pin high, the AD9259 is placed into

power-down mode. In this state, the ADC typically dissipates

3 mW. During power-down, the LVDS output drivers are placed

into a high impedance state. If any of the SPI features are changed

before the power-down feature is enabled, the chip continues to

function after PDWN is pulled low without requiring a reset. The

AD9259 returns to normal operating mode when the PDWN pin

is pulled low. This pin is both 1.8 V and 3.3 V tolerant.

placed as close to the receiver as possible. If there is no far-end

receiver termination or there is poor differential trace routing,

timing errors may result. To avoid such timing errors, it is

recommended that the trace length be less than 24 inches and

that the differential output traces be close together and at equal

lengths. An example of the FCO and data stream with proper

trace length and position is shown in Figure 49.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on REFT and REFB are

discharged when entering power-down mode and must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in the power-down

mode: shorter cycles result in proportionally shorter wake-up

times. With the recommended 0.1 μF and 2.2 μF decoupling

capacitors on REFT and REFB, approximately 1 sec is required

to fully discharge the reference buffer decoupling capacitors and

approximately 375 μs is required to restore full operation.

2.5ns/DIV

CH1 500mV/DIV = DCO

CH2 500mV/DIV = DATA

CH3 500mV/DIV = FCO

There are several other power-down options available when

using the SPI. The user can individually power down each

channel or put the entire device into standby mode. The latter

option allows the user to keep the internal PLL powered when

fast wake-up times (~600 ns) are required. See the Memory

Map section for more details on using these features.

Figure 49. LVDS Output Timing Example in ANSI-644 Mode (Default)

An example of the LVDS output using the ANSI-644 standard

(default) data eye and a time interval error (TIE) jitter histogram

with trace lengths less than 24 inches on standard FR-4 material is

shown in Figure 50. Figure 51 shows an example of trace lengths

exceeding 24 inches on standard FR-4 material. Notice that the

TIE jitter histogram reflects the decrease of the data eye opening

as the edge deviates from the ideal position. It is the user’s respon-

sibility to determine if the waveforms meet the timing budget of

the design when the trace lengths exceed 24 inches. Additional SPI

options allow the user to further increase the internal termination

(increasing the current) of all four outputs to drive longer trace

lengths (see Figure 52). Even though this produces sharper rise

and fall times on the data edges and is less prone to bit errors, the

power dissipation of the DRVDD supply increases when this

option is used. In addition, notice in Figure 52 that the histogram

is improved compared with that shown in Figure 51. See the

Memory Map section for more details.

Digital Outputs and Timing

The AD9259 differential outputs conform to the ANSI-644 LVDS

standard on default power-up. This can be changed to a low power,

reduced signal option (similar to the IEEE 1596.3 standard) via the

SDIO/ODM pin or SPI. The LVDS standard can further reduce the

overall power dissipation of the device by approximately 17 mW.

See the SDIO/ODM Pin section or Table 16 in the Memory Map

section for more information. The LVDS driver current is derived

on-chip and sets the output current at each output equal to a

nominal 3.5 mA. A 100 Ω differential termination resistor

placed at the LVDS receiver inputs results in a nominal

350 mV swing at the receiver.

The AD9259 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs for superior switching

performance in noisy environments. Single point-to-point net

topologies are recommended with a 100 Ω termination resistor

Rev. E | Page 23 of 52

AD9259

Data Sheet

EYE: ALL BITS

ULS: 9599/15599

ULS: 10000/15600

400

200

500

0

–200

–400

–500

–1.0ns

–0.5ns

0ns

0.5ns

1.0ns

–1.0ns

–0.5ns

0ns

0.5ns

1.0ns

100

50

0

50

0

–150ps –100ps

–50ps

0ps

50ps

100ps

150ps

–100ps

0ps

100ps

Figure 52. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Internal

Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4,

External 100 Ω Far Termination Only

Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only

EYE: ALL BITS

ULS: 9600/15600

200

The format of the output data is offset binary by default. An

example of the output coding format can be found in Table 8.

To change the output data format to twos complement, see the

Memory Map section.

0

Table 8. Digital Output Coding

(VIN + x) − (VIN − x),

Digital Output Offset Binary

(D13 ... D0)

Code

Input Span = 2 V p-p (V)

163±3 +1.00

11 1111 1111 1111

10 0000 0000 0000

01 1111 1111 1111

00 0000 0000 0000

–200

100

±192

±191

0

0.00

−0.000122

−1.00

–1.0ns

–0.5ns

0ns

0.5ns

1.0ns

Data from each ADC is serialized and provided on a separate

channel. The data rate for each serial stream is equal to 14 bits

times the sample clock rate, with a maximum of 700 Mbps

(14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion

rate is 10 MSPS. However, if lower sample rates are required for

a specific application, the PLL can be set up via the SPI to allow

encode rates as low as 5 MSPS. See the Memory Map section for

details on enabling this feature.

50

0

–150ps –100ps

–50ps

0ps

50ps

100ps

150ps

Figure 51. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only

Rev. E | Page 24 of 52

Data Sheet

AD9259

(DDR) capturing. The FCO is used to signal the start of a new

output byte and is equal to the sample clock rate. See the timing

diagram shown in Figure 2 for more information.

Two output clocks are provided to assist in capturing data from

the AD9259. The DCO is used to clock the output data and is

equal to seven times the sample clock (CLK) rate. Data is

clocked out of the AD9259 and must be captured on the rising

and falling edges of the DCO that supports double data rate

Table 9. Flexible Output Test Modes

Output Test Mode

Bit Sequence

Subject to Data

Format Select

Pattern Name

Off (default)

Midscale short

Digital Output Word 1

Digital Output Word 2

0000

0001

N/A

Same

N/A

Yes

1000 0000 (±-bit)

10 0000 0000 (10-bit)

1000 0000 0000 (12-bit)

10 0000 0000 0000 (14-bit)

0010

0011

0100

+Full-scale short

−Full-scale short

Checkerboard

1111 1111 (±-bit)

Same

Yes

No

11 1111 1111 (10-bit)

1111 1111 1111 (12-bit)

11 1111 1111 1111 (14-bit)

0000 0000 (±-bit)

00 0000 0000 (10-bit)

0000 0000 0000 (12-bit)

00 0000 0000 0000 (14-bit)

1010 1010 (±-bit)

0101 0101 (±-bit)

10 1010 1010 (10-bit)

1010 1010 1010 (12-bit)

10 1010 1010 1010 (14-bit)

01 0101 0101 (10-bit)

0101 0101 0101 (12-bit)

01 0101 0101 0101 (14-bit)

0101

0110

0111

PN sequence long¹

PN sequence short¹

One-/zero-word toggle

N/A

Yes

No

1111 1111 (±-bit)

0000 0000 (±-bit)

11 1111 1111 (10-bit)

1111 1111 1111 (12-bit)

11 1111 1111 1111 (14-bit)

00 0000 0000 (10-bit)

0000 0000 0000 (12-bit)

00 0000 0000 0000 (14-bit)

1000

1001

User input

1-/0-bit toggle

Register 0x19 to Register 0x1A

1010 1010 (±-bit)

10 1010 1010 (10-bit)

1010 1010 1010 (12-bit)

10 1010 1010 1010 (14-bit)

Register 0x1B to Register 0x1C

N/A

No

1010

1011

1100

1× sync

0000 1111 (±-bit)

N/A

No

00 0001 1111 (10-bit)

0000 0011 1111 (12-bit)

00 0000 0111 1111 (14-bit)

One bit high

Mixed frequency

1000 0000 (±-bit)

10 0000 0000 (10-bit)

1000 0000 0000 (12-bit)

10 0000 0000 0000 (14-bit)

1010 0011 (±-bit)

10 0110 0011 (10-bit)

1010 0011 0011 (12-bit)

10 1000 0110 0111 (14-bit)

¹All test mode options except PN sequence short and PN sequence long can support ±- to 14-bit word lengths in order to verify data capture to the receiver.

Rev. E | Page 25 of 52

AD9259

Data Sheet

When the SPI is used, the DCO phase can be adjusted in 60°

increments relative to the data edge. This enables the user to

refine system timing margins if required. The default DCO+

and DCO− timing, as shown in Figure 2, is 90° relative to the

output data edge.

Table 10. PN Sequence

Initial

First Three Output Samples

(MSB First)

Sequence

Value

PN Sequence Short

PN Sequence Long

0x0df

0x26e02±

0x37e4, 0x3533, 0x0063

0x191f, 0x35c2, 0x2359

An 8-, 10-, or 12-bit serial stream can also be initiated from the

SPI. This allows the user to implement and test compatibility with

lower resolution systems. When changing the resolution to an

8-, 10-, or 12-bit serial stream, the data stream is shortened. See

Figure 3 for a 12-bit example.

Consult the Memory Map section for information on how

to change these additional digital output timing features

through the SPI.

SDIO/ODM Pin

The SDIO/ODM pin is for use in applications that do not require

SPI mode operation. This pin can enable a low power, reduced

signal option (similar to the IEEE 1596.3 reduced range link

output standard) if it and the CSB pin are tied to AVDD during

device power-up. This option should only be used when the

digital output trace lengths are less than 2 inches from the LVDS

receiver. When this option is used, the FCO, DCO, and outputs

function normally, but the LVDS signal swing of all channels is

reduced from 350 mV p-p to 200 mV p-p, allowing the user to

further reduce the power on the DRVDD supply.

When the SPI is used, all of the data outputs can also be

inverted from their nominal state. This is not to be confused

with inverting the serial stream to an LSB-first mode. In default

mode, as shown in Figure 2, the MSB is first in the data output

serial stream. However, this can be inverted so that the LSB is

first in the data output serial stream (see Figure 4).

There are 12 digital output test pattern options available that

can be initiated through the SPI. This is a useful feature when

validating receiver capture and timing. Refer to Table 9 for the

output bit sequencing options available. Some test patterns have

two serial sequential words and can be alternated in various

ways, depending on the test pattern chosen. Note that some

patterns do not adhere to the data format select option. In

addition, custom user-defined test patterns can be assigned in

the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode

options except PN sequence short and PN sequence long can

support 8- to 14-bit word lengths to verify data capture to the

receiver.

For applications where this pin is not used, it should be tied low.

In this case, the device pin can be left open, and the 30 kΩ internal

pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant.

If applications require this pin to be driven from a 3.3 V logic level,

insert a 1 kΩ resistor in series with this pin to limit the current.

Table 11. Output Driver Mode Pin Settings

Resulting

Selected ODM ODM Voltage

Output Standard FCO and DCO

Normal

Operation

10 kΩ to AGND ANSI-644

ANSI-644

(default)

Low power,

reduced

signal option

The PN sequence short pattern produces a pseudorandom bit

sequence that repeats itself every 2⁹− 1 or 511 bits. A description

of the PN sequence and how it is generated can be found in

Section 5.1 of the ITU-T 0.150 (05/96) standard. The only

difference is that the starting value must be a specific value

instead of all 1s (see Table 10 for the initial values).

(default)

ODM

AVDD

Low power,

reduced

signal option

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 2²³− 1 or 8,388,607 bits. A

description of the PN sequence and how it is generated can be

found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The

only differences are that the starting value must be a specific

value instead of all 1s (see Table 10 for the initial values) and the

AD9259 inverts the bit stream with relation to the ITU standard.

Rev. E | Page 26 of 52

Data Sheet

AD9259

SCLK/DTP Pin

RBIAS Pin

The SCLK/DTP pin is for use in applications that do not require

SPI mode operation. This pin can enable a single digital test

pattern if it and the CSB pin are held high during device power-

up. When SCLK/DTP is tied to AVDD, the ADC channel

outputs shift out the following pattern: 10 0000 0000 0000. The

FCO and DCO function normally while all channels shift out the

repeatable test pattern. This pattern allows the user to perform

timing alignment adjustments among the FCO, DCO, and output

data. For normal operation, this pin should be tied to AGND

through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V tolerant.

To set the internal core bias current of the ADC, place a resistor

(nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The

resistor current is derived on-chip and sets the AVDD current of

the ADC to a nominal 185 mA at 50 MSPS. Therefore, it is

imperative that at least a 1% tolerance on this resistor be used to

achieve consistent performance.

Voltage Reference

A stable, accurate 0.5 V voltage reference is built into the

AD9259. This is gained up internally by a factor of 2, setting

V

_REFto 1.0 V, which results in a full-scale differential input span

of 2 V p-p. The V_REFis set internally by default; however, the

VREF pin can be driven externally with a 1.0 V reference to

improve accuracy.

Table 12. Digital Test Pattern Pin Settings

Resulting

Selected DTP DTP Voltage

D + x and D − x FCO and DCO

Normal

Operation

10 kΩ to AGND Normal Normal operation

operation

When applying the decoupling capacitors to the VREF, REFT,

and REFB pins, use ceramic low ESR capacitors. These capacitors

should be close to the ADC pins and on the same layer of the

PCB as the AD9259. The recommended capacitor values and

configurations for the AD9259 reference pin are shown in

Figure 53.

DTP

AVDD

10 0000 0000

0000

Normal operation

Additional and custom test patterns can also be observed when

commanded from the SPI port. Consult the Memory Map

section for information about the options available.

Table 13. Reference Settings

CSB Pin

Resulting

Differential

The CSB pin should be tied to AVDD for applications that do

not require SPI mode operation. By tying CSB high, all SCLK

and SDIO information is ignored. This pin is both 1.8 V and

3.3 V tolerant.

Selected Mode SENSE Voltage Resulting VREF (V) Span (V p-p)

External

AVDD

N/A

2 × external

reference

Reference

Internal,

AGND to 0.2 V

1.0

2.0

2 V p-p FSR

Rev. E | Page 27 of 52

AD9259

Data Sheet

External Reference Operation

Internal Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or to improve thermal drift

characteristics. Figure 56 shows the typical drift characteristics

of the internal reference in 1 V mode.

A comparator within the AD9259 detects the potential at the

SENSE pin and configures the reference. If SENSE is grounded,

the reference amplifier switch is connected to the internal

resistor divider (see Figure 53), setting VREF to 1 V.

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. The external

reference is loaded with an equivalent 6 kΩ load. An internal

reference buffer generates the positive and negative full-scale

references, REFT and REFB, for the ADC core. Therefore, the

external reference must be limited to a nominal 1.0 V.

The REFT and REFB pins establish the input span of the ADC

core from the reference configuration. The analog input full-

scale range of the ADC equals twice the voltage of the reference

pin for either an internal or an external reference configuration.

If the reference of the AD9259 is used to drive multiple

converters to improve gain matching, the loading of the refer-

ence by the other converters must be considered. Figure 55

depicts how the internal reference voltage is affected by loading.

5

0

–5

VIN + x

VIN – x

REFT

–10

–15

–20

–25

–30

0.1µF

+

ADC

CORE

0.1µF

2.2µF

REFB

0.1µF

VREF

0.1µF

1µF

0.5V

SELECT

LOGIC

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SENSE

CURRENT LOAD (mA)

Figure 55. V_REFAccuracy vs. Load

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

–0.14

–0.16

–0.18

Figure 53. Internal Reference Configuration

VIN + x

VIN – x

REFT

0.1µF

REFB

+

ADC

CORE

2.2µF

EXTERNAL

REFERENCE

0.1µF

VREF

1

1µF

0.1µF

0.5V

–40

–20

0

20

40

60

80

SELECT

LOGIC

AVDD

TEMPERATURE (°C)

Figure 56. Typical V_REFDrift

SENSE

1

OPTIONAL.

Figure 54. External Reference Operation

Rev. E | Page 2± of 52

Data Sheet

AD9259

SERIAL PORT INTERFACE (SPI)

The AD9259 serial port interface allows the user to configure

the converter for specific functions or operations through a

structured register space provided in the ADC. This may

provide the user with additional flexibility and customization,

depending on the application. Addresses are accessed via the

serial port and can be written to or read from via the port. Memory

is organized into bytes that can be further divided into fields, as

documented in the Memory Map section. Detailed operational

information can be found in the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI at www.analog.com.

In addition to the operation modes, the SPI port configuration

influences how the AD9259 operates. For applications that do

not require a control port, the CSB line can be tied and held high.

This places the remainder of the SPI pins into their secondary

modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin

sections. CSB can also be tied low to enable 2-wire mode. When

CSB is tied low, SCLK and SDIO are the only pins required for

communication. Although the device is synchronized during

power-up, the user should ensure that the serial port remains

synchronized with the CSB line when using this mode. When

operating in 2-wire mode, it is recommended to use a 1-, 2-,

or 3-byte transfer exclusively. Without an active CSB line,

streaming mode can be entered but not exited.

There are three pins that define the SPI: SCLK, SDIO, and CSB

(see Table 14). The SCLK pin is used to synchronize the read

and write data presented to the ADC. The SDIO pin is a dual-

purpose pin that allows data to be sent to and read from the

internal ADC memory map registers. The CSB pin is an active

low control that enables or disables the read and write cycles.

In addition to word length, the instruction phase determines if

the serial frame is a read or write operation, allowing the serial

port to be used to both program the chip and read the contents

of the on-chip memory. If the instruction is a readback operation,

performing a readback causes the SDIO pin to change from an

input to an output at the appropriate point in the serial frame.

Table 14. Serial Port Pins

Function

SCLK

Serial Clock. The serial shift clock input. SCLK is used to

synchronize serial interface reads and writes.

Serial Data Input/Output. A dual-purpose pin. The typical

role for this pin is as an input or output, depending on

the instruction sent and the relative position in the

timing frame.

Data can be sent in MSB- or LSB-first mode. MSB-first mode

is the default at power-up and can be changed by adjusting the

configuration register. For more information about this and

other features, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI at www.analog.com.

SDIO

CSB

Chip Select Bar (Active Low). This control gates the read

and write cycles.

HARDWARE INTERFACE

The pins described in Table 14 compose the physical interface

between the user’s programming device and the serial port of

the AD9259. The SCLK and CSB pins function as inputs when

using the SPI. The SDIO pin is bidirectional, functioning as an

input during write phases and as an output during readback.

The falling edge of the CSB in conjunction with the rising edge of

the SCLK determines the start of the framing sequence. During an

instruction phase, a 16-bit instruction is transmitted, followed by

one or more data bytes, which is determined by Bit Field W0 and

Bit Field W1. An example of the serial timing and its definitions

can be found in Figure 58 and Table 15. During normal operation,

CSB is used to signal to the device that SPI commands are to be

received and processed. When CSB is brought low, the device

processes SCLK and SDIO to obtain instructions. Normally,

CSB remains low until the communication cycle is complete.

However, if connected to a slow device, CSB can be brought

high between bytes, allowing older microcontrollers enough

time to transfer data into shift registers. CSB can be stalled

when transferring one, two, or three bytes of data. When W0

and W1 are set to 11, the device enters streaming mode and

continues to process data, either reading or writing, until

CSB is taken high to end the communication cycle. This allows

complete memory transfers without requiring additional instruc-

tions. Regardless of the mode, if CSB is taken high in the middle

of a byte transfer, the SPI state machine is reset and the device

waits for a new instruction.

If multiple SDIO pins share a common connection, care should

be taken to ensure that proper V_OHlevels are met. Assuming the

same load for each AD9259, Figure 57 shows the number of

SDIO pins that can be connected together and the resulting V_OH

level. This interface is flexible enough to be controlled by either

serial PROMS or PIC microcontrollers, providing the user with

an alternative method, other than a full SPI controller, to

program the ADC (see the AN-812 Application Note).

Rev. E | Page 29 of 52

AD9259

Data Sheet

1.800

1.795

1.790

1.785

1.780

1.775

1.770

1.765

1.760

1.755

1.750

1.745

1.740

1.735

1.730

1.725

1.720

If the user chooses not to use the SPI, these dual-function pins

serve their secondary functions when the CSB is strapped to

AVDD during device power-up. See the Theory of Operation

section for details on which pin-strappable functions are

supported on the SPI pins.

For users who wish to operate the ADC without using the

SPI, remove any connections from the CSB, SCLK/DTP, and

SDIO/ODM pins. By disconnecting these pins from the control

bus, the ADC can function in its most basic operation. Each

of these pins has an internal termination that floats to its

respective level.

1.715

0

10

20

30

40

50

60

70

80

90

100

NUMBER OF SDIO PINS CONNECTED TOGETHER

Figure 57. SDIO Pin Loading

t_DS

t_HI

t_CLK

t_H

t_S

t_DH

t_LO

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 58. Serial Timing Details

Table 15. Serial Timing Definitions

Parameter

Timing (Minimum, ns)

Description

t_DS

5

2

40

5

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the clock

t_DH

t_CLK

t_S

Setup time between CSB and SCLK

t_H

2

Hold time between CSB and SCLK

t_HI

t_LO

t_{EN_SDIO}

16

10

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge (not shown in Figure 58)

t_{DIS_SDIO}

10

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge (not shown in Figure 58)

Rev. E | Page 30 of 52

Data Sheet

AD9259

MEMORY MAP

READING THE MEMORY MAP TABLE

RESERVED LOCATIONS

Each row in the memory map register table (Table 16) has eight

address locations. The memory map is divided into three sections:

the chip configuration register map (Address 0x00 to Address 0x02),

the device index and transfer register map (Address 0x05 and

Address 0xFF), and the ADC functions register map (Address 0x08

to Address 0x22).

Undefined memory locations should not be written to except

when writing the default values suggested in this data sheet.

Addresses that have values marked as 0 should be considered

reserved and have a 0 written into their registers during power-up.

DEFAULT VALUES

When the AD9259 comes out of a reset, critical registers are

preloaded with default values. These values are indicated in

Table 16, where an X refers to an undefined feature.

The leftmost column of the memory map indicates the register

address number, and the default value is shown in the second

rightmost column. The (MSB) Bit 7 column is the start of the

default hexadecimal value given. For example, Address 0x09, the

clock register, has a default value of 0x01, meaning that Bit 7 = 0,

Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and

Bit 0 = 1, or 0000 0001 in binary. This setting is the default for

the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6

of this address followed by a 0x01 in Register 0xFF (transfer bit),

the duty cycle stabilizer turns off. It is important to follow each

writing sequence with a transfer bit to update the SPI registers. For

more information on this and other functions, consult the AN-877

Application Note, Interfacing to High Speed ADCs via SPI at

www.analog.com.

LOGIC LEVELS

An explanation of various registers follows: “Bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly, “clear a bit” is synonymous with “bit is set to

Logic 0” or “writing Logic 0 for the bit.”

Rev. E | Page 31 of 52

AD9259

Data Sheet

Table 16. Memory Map Register

Default

Value

(Hex)

Addr.

(MSB)

Bit 7

(LSB)

Bit 0

Default Notes/

Comments

(Hex) Register Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Chip Configuration Registers

00

chip_port_config

0

LSB first

1 = on

0 = off

Soft

reset

1 = on

0 = off

(default)

1

Soft

reset

1 = on

0 = off

(default)

LSB first

1 = on

0 = off

0

0x1±

The nibbles

should be

mirrored so that

LSB- or MSB-first

mode is set cor-

rectly regardless

of shift mode.

(default)

01

02

chip_id

±-bit Chip ID Bits [7:0]

(AD9259 = 0x04), (default)

0x04

Default is unique

chip ID. This is a

read-only

register.

chip_grade

X

Child ID [6:4]

X

Child ID used to

differentiate

graded devices.

This is a read-

only register.

(identify device variants of Chip ID)

100 = 50 MSPS

Device Index and Transfer Registers

Clock

channel

DCO

1 = on

0 = off

Clock

channel

FCO

1 = on

0 = off

Data

Channel

A

0x0F

0x00

Bits are set to

05

device_index_A

X

Channel Channel Channel

determine which

on-chip device

receives the next

write command.

D

1 = on

C

B

1 = on

(default) (default) (default) (default)

(default) (default) 0 = off

0 = off

FF

device_update

X

SW

Synchronously

transfers data

from the master

shift register to

the slave.

transfer

1 = on

0 = off

(default)

ADC Functions

0±

modes

X

Internal power-down mode

000 = chip run (default)

001 = full power-down

010 = standby

0x00

0x01

Determines

various generic

modes of chip

operation.

011 = reset

09

clock

X

Duty

Turns the

cycle

internal duty

cycle stabilizer

on and off.

stabilizer

1 = on

(default)

0 = off

Output test mode—see Table 9 in the

long gen PN short Digital Outputs and Timing section

0x00

When this reg-

ister is set, the

test data is placed

on the output

pins in place of

normal data.

0D

test_io

User test mode

00 = off (default)

Reset PN Reset

01 = on, single alternate 1 = on

gen

1 = on

0000 = off (default)

0001 = midscale short

0010 = +FS short

10 = on, single once

11 = on, alternate once

0 = off

(default) 0 = off

(default) 0011 = −FS short

0100 = checkerboard output

0101 = PN 23 sequence

0110 = PN 9 sequence

0111 = 1-/0-word toggle

1000 = user input

1001 = 1-/0-bit toggle

1010 = 1× sync

1011 = one bit high

1100 = mixed bit frequency

(format determined by output_mode)

Rev. E | Page 32 of 52

Data Sheet

AD9259

Default

Value

(Hex)

Addr.

(MSB)

Bit 7

(LSB)

Bit 0

Default Notes/

Comments

(Hex) Register Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

14

output_mode

X

0 = LVDS

ANSI-644

(default)

1 = LVDS

low power

(IEEE

X

Output

invert

1 = on

0 = off

(default)

00 = offset binary

(default)

01 = twos

0x00

Configures the

outputs and the

format of the

data.

complement

1596.3

similar)

15

output_adjust

X

Output driver

termination

00 = none (default)

01 = 200 Ω

10 = 100 Ω

11 = 100 Ω

X

0x00

Determines

LVDS or other

output properties.

Primarily func-

tions to set the

LVDS span and

common-mode

levels in place of

an external

resistor.

On devices that

utilize global

clock divide,

determines

which phase of

the divider

output is used to

supply the

output clock.

Internal latching

is unaffected.

16

output_phase

X

0011 = output clock phase adjust

(0000 through 1010)

0000 = 0° relative to data edge

0001 = 60° relative to data edge

0010 = 120° relative to data edge

0011 = 1±0° relative to data edge (default)

0101 = 300° relative to data edge

0110 = 360° relative to data edge

1000 = 4±0° relative to data edge

1001 = 540° relative to data edge

1010 = 600° relative to data edge

1011 to 1111 = 660° relative to data edge

0x03

19

1A

1B

1C

21

user_patt1_lsb

user_patt1_msb

user_patt2_lsb

user_patt2_msb

serial_control

B7

B6

B5

B4

B3

B2

B1

B9

B1

B9

B0

B±

B0

B±

0x00

User-defined

pattern, 1 LSB.

B15

B7

B14

B6

B13

B5

B12

B4

B11

B3

B10

B2

User-defined

pattern, 1 MSB.

User-defined

pattern, 2 LSB.

B15

B14

X

B13

X

B12

X

B11

B10

User-defined

pattern, 2 MSB.

LSB first

1 = on

0 = off

<10

MSPS,

low

encode

rate

000 = 14 bits (default, normal bit

stream)

001 = ± bits

010 = 10 bits

011 = 12 bits

Serial stream

control. Default

causes MSB first

and the native

bit stream

(default)

mode

1 = on

0 = off

(default)

100 = 14 bits

(global).

Used to power

down individual

sections of a

22

serial_ch_stat

X

Channel

output

reset

1 = on

0 = off

Channel

power-

down

1 = on

0 = off

0x00

converter (local).

(default) (default)

Rev. E | Page 33 of 52

AD9259

Data Sheet

Power and Ground Recommendations

Exposed Paddle Thermal Heat Slug Recommendations

When connecting power to the AD9259, it is recommended

that two separate 1.8 V supplies be used: one for analog (AVDD)

and one for digital (DRVDD). If only one supply is available, it

should be routed to the AVDD first and then tapped off and

isolated with a ferrite bead or a filter choke preceded by

decoupling capacitors for the DRVDD. The user can employ

several different decoupling capacitors to cover both high and

low frequencies. These should be located close to the point of

entry at the PC board level and close to the parts, with minimal

trace lengths.

It is required that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance of the AD9259. An

exposed continuous copper plane on the PCB should mate to

the AD9259 exposed paddle, Pin 0. The copper plane should

have several vias to achieve the lowest possible resistive thermal

path for heat dissipation to flow through the bottom of the PCB.

These vias should be solder-filled or plugged.

To maximize the coverage and adhesion between the ADC and

PCB, partition the continuous copper plane by overlaying a

silkscreen on the PCB into several uniform sections. This provides

several tie points between the ADC and PCB during the reflow

process, whereas using one continuous plane with no partitions

only guarantees one tie point. See Figure 59 for a PCB layout

example. For detailed information on packaging and the PCB

layout of chip scale packages, see the AN-772 Application Note,

A Design and Manufacturing Guide for the Lead Frame Chip

Scale Package (LFCSP) at www.analog.com.

A single PC board ground plane should be sufficient when

using the AD9259. With proper decoupling and smart parti-

tioning of the PC board’s analog, digital, and clock sections,

optimum performance can be easily achieved.

SILKSCREEN PARTITION

PIN 1 INDICATOR

Figure 59. Typical PCB Layout

Rev. E | Page 34 of 52

Data Sheet

AD9259

EVALUATION BOARD

board individually. Use P501 to connect a different supply for

each section. At least one 1.8 V supply is needed for AVDD_DUT

and DRVDD_DUT; however, it is recommended that separate

supplies be used for analog and digital signals and that each

supply have a current capability of 1 A. To operate the evaluation

board using the VGA option, a separate 5.0 V analog supply

(AVDD_5 V) is needed. To operate the evaluation board using

the SPI and alternate clock options, a separate 3.3 V analog

supply (AVDD_3.3 V) is needed in addition to the other

supplies.

The AD9259 evaluation board provides all of the support cir-

cuitry required to operate the ADC in its various modes and

configurations. The converter can be driven differentially using a

transformer (default) or a AD8332 driver. The ADC can also be

driven in a single-ended fashion. Separate power pins are provided

to isolate the DUT from the drive circuitry of the AD8332. Each

input configuration can be selected by changing the connection

of various jumpers (see Figure 62 to Figure 66). Figure 60 shows

the typical bench characterization setup used to evaluate the ac

performance of the AD9259. It is critical that the signal sources

used for the analog input and clock have very low phase noise

(<1 ps rms jitter) to realize the optimum performance of the

converter. Proper filtering of the analog input signal to remove

harmonics and lower the integrated or broadband noise at the

input is also necessary to achieve the specified noise performance.

INPUT SIGNALS

When connecting the clock and analog source to the evaluation

board, use clean signal generators with low phase noise, such as

Rohde & Schwarz SMA or HP8644 signal generators or the

equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial cable.

Enter the desired frequency and amplitude from the ADC speci-

fications tables. Typically, most Analog Devices, Inc., evaluation

boards can accept approximately 2.8 V p-p or 13 dBm sine wave

input for the clock. When connecting the analog input source, it

is recommended to use a multipole, narrow-band, band-pass

filter with 50 Ω terminations. Good choices of such band-pass

filters are available from TTE, Allen Avionics, and K&L

See Figure 62 to Figure 70 for the complete schematics and

layout diagrams demonstrating the routing and grounding

techniques that should be applied at the system level.

POWER SUPPLIES

This evaluation board has a wall-mountable switching power

supply that provides a 6 V, 2 A maximum output. Connect the

supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to

63 Hz. The other end of the supply is a 2.1 mm inner diameter

jack that connects to the PCB at P503. Once on the PC board,

the 6 V supply is fused and conditioned before connecting to

three low dropout linear regulators that supply the proper bias

to each of the various sections on the board.

Microwave, Inc. The filter should be connected directly to the

evaluation board if possible.

OUTPUT SIGNALS

The default setup uses the Analog Devices HSC-ADC-FIFO5-

INTZ to interface with the Analog Devices standard dual-

channel FIFO data capture board (HCS-ADC-EVALCZ). Two

of the eight channels can be evaluated at the same time. For

more information on the channel settings and optional settings

of these boards, visit www.analog.com/FIFO.

When operating the evaluation board in a nondefault condition,

L504 to L507 can be removed to disconnect the switching

power supply. This enables the user to bias each section of the

WALL OUTLET

100V TO 240V AC

47Hz TO 63Hz

6V DC

2A MAX

5.0V

1.8V

3.3V

–

+

–

+

–

+

–

+

–

+

SWITCHING

POWER

SUPPLY

PC

RUNNING

ADC

ROHDE & SCHWARZ,

ANALYZER

AND SPI

USER

INTERPOSER

BOARD

HSC-ADC-EVALCZ

FIFO DATA

CAPTURE

SMA,

2V p-p SIGNAL

SYNTHESIZER

BAND-PASS

FILTER

XFMR

INPUT

AD9259

EVALUATION BOARD

SOFTWARE

BOARD

CH A TO CH D

14-BIT

ROHDE & SCHWARZ,

SMA,

USB

CONNECTION

SERIAL

CLK

LVDS

2V p-p SIGNAL

SYNTHESIZER

SPI

Figure 60. Evaluation Board Connection

Rev. E | Page 35 of 52

AD9259

Data Sheet

A differential LVPECL clock can also be used to clock the

ADC input using the AD9515 (U202). Populate R225 and

R227 with 0 Ω resistors and remove R217 and R218 to

disconnect the default clock path inputs. In addition, populate

C207 and C208 with a 0.1 μF capacitor and remove C210 and

C211 to disconnect the default clock path outputs. The

AD9515 has many pin-strappable options that are set to a

default mode of operation. Consult the AD9515 data sheet

for more information about these and other options.

DEFAULT OPERATION AND JUMPER SELECTION

SETTINGS

The following is a list of the default and optional settings or

modes allowed on the AD9259 Rev. A evaluation board.



POWER: Connect the switching power supply that is

provided in the evaluation kit between a rated 100 V ac to

240 V ac wall outlet at 47 Hz to 63 Hz and P503.

AIN: The evaluation board is set up for a transformer-

coupled analog input with an optimum 50 Ω impedance

match of 200 MHz of bandwidth (see Figure 61). For more

bandwidth response, the differential capacitor across the

analog inputs can be changed or removed. The common

mode of the analog inputs is developed from the center

tap of the transformer or AVDD_DUT/2.

In addition, an on-board oscillator is available on the OSC201

and can act as the primary clock source. The setup is quick

and involves installing R212 with a 0 Ω resistor and setting

the enable jumper (J205) to the on position. If the user wishes

to employ a different oscillator, two oscillator footprint options

are available (OSC201) to check the ADC performance.

0



PDWN: To enable the power-down feature, short J201 to

AVDD on the PDWN pin.

–2

–3dB CUTOFF = 200MHz

–4

–6

SCLK/DTP: To enable the digital test pattern on the digital

outputs of the ADC, use J204. If J204 is tied to AVDD during

device power-up, Test Pattern 10 0000 0000 0000 is enabled.

See the SCLK/DTP Pin section for details.

–8

–10

–12

–14

–16



SDIO/ODM: To enable the low power, reduced signal option

(similar to the IEEE 1595.3 reduced range link LVDS output

standard), use J203. If J203 is tied to AVDD during device

power-up, it enables the LVDS outputs in a low power,

reduced signal option from the default ANSI-644 standard.

This option changes the signal swing from 350 mV p-p to

200 mV p-p, reducing the power of the DRVDD supply. See

the SDIO/ODM Pin section for more details.

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

Figure 61. Evaluation Board Full-Power Bandwidth



VREF: VREF is set to 1.0 V by tying the SENSE pin to

ground, R237. This causes the ADC to operate in 2.0 V p-p

full-scale range. A separate external reference option using

the ADR510 is also included on the evaluation board.

Populate R231 and R235 and remove C214. Proper use of the

VREF options is noted in the Voltage Reference section.



CSB: To enable processing of the SPI information on the

SDIO and SCLK pins, tie J202 low in the always enable

mode. To ignore the SDIO and SCLK information, tie J202

to AVDD.

Non-SPI Mode: For users who wish to operate the DUT

without using SPI, remove Jumpers J202, J203, and J204.

This disconnects the CSB, SCLK/DTP, and SDIO/ODM

pins from the control bus, allowing the DUT to operate in its

simplest mode. Each of these pins has internal termination

and will float to its respective level.



RBIAS: RBIAS has a default setting of 10 kΩ (R201) to

ground and is used to set the ADC core bias current.

CLOCK: The default clock input circuitry is derived from a

simple transformer-coupled circuit using a high bandwidth

1:1 impedance ratio transformer (T201) that adds a very

low amount of jitter to the clock path. The clock input is

50 Ω terminated and ac-coupled to handle single-ended

sine wave types of inputs. The transformer converts the

single-ended input to a differential signal that is clipped

before entering the ADC clock inputs.



D + x, D − x: If an alternative data capture method to the setup

shown in Figure 60 is used, optional receiver terminations,

R206 to R211, can be installed next to the high speed back-

plane connector.

Rev. E | Page 36 of 52

Data Sheet

AD9259

ALTERNATIVE ANALOG INPUT DRIVE

CONFIGURATION

•

Populate R101, R114, R127, and R140 with 0 Ω resistors in

the analog input path.

The following is a brief description of the alternative analog input

drive configuration using the AD8332 dual VGA. If this drive

option is in use, some components may need to be populated, in

which case all the necessary components are listed in Table 17. For

more details on the AD8332 dual VGA, including how it works

and its optional pin settings, consult the AD8332 data sheet.

Populate R105, R113, R118, R124, R131, R137, R151, and

R160 with 0 Ω resistors in the analog input path to connect

the AD8332.

•

Populate R152, R153, R154, R155, R156, R157, R158, R159,

C103, C105, C110, C112, C117, C119, C124, and C126

with 10 kΩ resistors to provide an input common-mode

level to the ADC analog inputs.

To configure the analog input to drive the VGA instead of the

default transformer option, the following components need to

be removed and/or changed.

•

Remove R305, R306, R313, R314, R405, R406, R412, and

R424 to configure the AD8332.

•

Remove R102, R115, R128, R141, R161, R162, R163, R164,

T101, T102, T103, and T104 in the default analog input path.

In this configuration, L301 to L308 and L401 to L408 are

populated with 0 Ω resistors to allow signal connection and

use of a filter if additional requirements are necessary.

Rev. E | Page 37 of 52

AD9259

Data Sheet

AVDD_DUT

R105

DNP

R152

DNP

CH_A

C101

FB102 R108

R104

0Ω

P102

DNP

T101

0.1µF

10Ω 33Ω

VGA INPUT CONNECTION

INH1

1

6

VIN_A

AIN

R106

DNP

CHANNEL A

P101

R101

DNP

R161

2

3

5

4

R109

1kΩ

C103

C104

2.2pF

CM1

499Ω

DNP

AIN

R107

DNP

R113

DNP

FB101

10Ω

R103

0Ω

C102

0.1µF

R102

64.9Ω

VIN_A

CH_A

CM1

FB103 R110

C105

DNP

R156

DNP

10Ω

33Ω

E101

AVDD_DUT

C106

DNP

R111

1kΩ

C107

0.1µF

R112

1kΩ

AVDD_DUT

R118

DNP

VGA INPUT CONNECTION

INH2

R153

DNP

CH_B

CHANNEL B

P103

FB105 R121

R114

DNP

T102

10Ω 33Ω

1

6

AIN

VIN_B

FB104

10Ω

R119

DNP

R115

64.9Ω

C108

0.1µF

R162

2

3

5

4

R123

1kΩ

P104

DNP

C110

C111

2.2pF

CM2

499Ω

DNP

R120

DNP

R124

DNP

R116

0Ω

AIN

C109

0.1µF

E102

VIN_B

CH_B

CM2

R117

0Ω

FB106 R122

C112

DNP

R157

DNP

10Ω

33Ω

AVDD_DUT

C113

DNP

R125

1kΩ

C114

0.1µF

R126

1kΩ

AVDD_DUT

R131

DNP

R154

DNP

CH_C

C115

FB108 R134

P106

DNP

R130

0Ω

T103

0.1µF

10Ω 33Ω

VGA INPUT CONNECTION

INH3

1

6

VIN_C

AIN

R132

DNP

CHANNEL C

P105

R127

DNP

R163

2

3

5

4

R135

1kΩ

C117

C118

2.2pF

CM3

499Ω

DNP

AIN

R133

DNP

R137

DNP

FB107

10Ω

R129

0Ω

C116

0.1µF

R128

64.9Ω

VIN_C

CH_C

CM3

FB109 R136

C119

DNP

R158

DNP

10Ω

33Ω

E103

AVDD_DUT

C120

DNP

R138

1kΩ

C121

0.1µF

R139

1kΩ

AVDD_DUT

R151

DNP

VGA INPUT CONNECTION

INH4

R155

DNP

CH_D

CHANNEL D

P107

FB111 R146

R140

DNP

T104

10Ω 33Ω

1

6

AIN

VIN_D

FB110

R144

DNP

R141

64.9Ω

C122

10Ω

0.1µF

R164

499Ω

2

3

5

4

R148

1kΩ

C124

DNP

C125

CM4

P108

CM4

2.2pF

DNP

R145

DNP

R160

DNP

R143

0Ω

AIN

C123

0.1µF

R142

VIN_D

CH_D

CM4

0Ω

FB112 R147

C126

DNP

R159

DNP

10Ω

33Ω

E104

AVDD_DUT

C127

DNP

R149

1kΩ

C128

0.1µF

R150

1kΩ

AVDD_DUT

DNP: DO NOT POPULATE

Figure 62. Evaluation Board Schematic, DUT Analog Inputs

Rev. E | Page 3± of 52

Data Sheet

AD9259

AVDD_DUT

CW

S 0

S 1

S 2

S 3

S 4

S 5

S 6

S 7

S 8

2 5

1 6

1 5

1 4

1 3

1 2

1 1

1 0

2

1

2

Ω k 1 0

3 3

3 1

1

0 5 R 2

3

V –

D

G N

V S

E T R S

Ω 0 k 1 0

0 4 R 2

P N - Ω D 0 1 0 k

7

R 2 6

9

P N - Ω D k 1 0 0

Ω 0 k 1 0

0 3 R 2

S 9

8

6 6 R 2

0

S 1

3 2

7

E F V R

6

B – N V I

N V + I

B _ V I N

B _ N V I

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4

4 5

4 6

4 7

4 8

O

D C

+ O D C

2 4

B

– O D C

+ O F C

– O F C

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

D D A V

S A I R B

E S N S E

V R E F

U T _ D D D A V

O

F C

T U D S E _ S V E N

C H A

C H B

C H C

A

D +

D –

D +

D –

D +

D –

D +

D –

T U D _

V R E F

A

B F R E

T F R E

D D A V

B

1

B

U T _ D D D A V

C

D D A V

C

N V + I

C _ N V I

C H D

D

C _ V I N

C – N V I

D

Figure 63. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface

Rev. E | Page 39 of 52

AD9259

Data Sheet

POPULATE L301 TO L308 WITH

0Ω RESISTORS OR DESIGN

YOUR OWN FILTER.

R301

DNP

R302

DNP

EXTERNAL VARIABLE GAIN DRIVE

VG

C302

DNP

C301

DNP

VARIABLE GAIN CIRCUIT

L301

0Ω

L302 L303

L304

0Ω

(0V TO 1.0V DC)

VG

0Ω

GND

CW

AVDD_5V

C303

C304

L307

0Ω

L306

0Ω

L305 DNP

DNP L308

R320

39kΩ

R319

10kΩ

0Ω

R303

DNP

R304

DNP

C305

0.1µF

C306 C307

0.1µF 0.1µF

C308

0.1µF

R306

374Ω

R305

374Ω

R311

C309

1000pF

10kΩ

DNP

C310

0.1µF

R307

187Ω

R308

187Ω

R309

187Ω

R310

187Ω

R312

10kΩ

U301

25

R313

10kΩ

DNP

R314

ENBV

ENBL

HILO

VCM1

VIN1

VIP1

COM1

LOP1

RCLMP

16

26

27

28

29

30

31

32

10kΩ

VG

GAIN

MODE

VCM2

VIN2

VIP2

COM2

LOP2

15

14

13

12

11

10

9

DNP

AD8332

C311

0.1µF

C313

0.1µF

C312

0.1µF

C314

0.1µF

R316

C320

0.1µF

R317

274Ω

C321

0.1µF

274Ω

R315 C315

10kΩ 10µF

C316

0.1µF

C325

0.1µF

C326

10µF

R318

10kΩ

C317

0.018µF

C322

0.018µF

C318

22pF

C323

22pF

L309

120nH

L310

120nH

C319

0.1µF

C324

0.1µF

DNP: DO NOT POPULATE

INH4

INH3

Figure 64. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit

Rev. E | Page 40 of 52

Data Sheet

AD9259

_ C H D A S O

0 Ω

R 4 2 7

_ C D H S I A

0 Ω

R 4 2 0

K _ C H S L A

0 Ω

R 4 2 8

B 1 _ C C S H A

0 Ω

R 4 2 6

J401

PICVCC

1

2

PICVCC

GP1

GP0

3

5

4

6

GP1

GP0

MCLR/GP3

7

9

8

10

MCLR/GP3

7 5 4 k . Ω

R 4 1 8

OPTIONAL

PIC PROGRAMMING HEADER

7 5 m ± V H = N I = P O L H I

L O = I = N I L H O P

0 V 5 - . 2 5 V 2 . = E P O L N A S I G E V I A T G N E

V m 0 5

±

V . 0

T V O 0 1 = E L O S P I N G E A I T I V O P S

E D P I M O

N I P P A M R C L

D D A _ 5 V V

N

. R E L I T F N W O U R O Y

N I G E S D R O S R O T S I E S R Ω 0

4 0 L 8 O 4 0 L 1 E T T A L U P O P

H T I

W

C H _ A

F

R 4 1 6

0 1 0 8 . µ

C 4 2 0

2 7 4 Ω

2

L O N

M M C O

H 2 O V

O V L 2

8

1 7

1 8

1 9

V P S 2

7

D D A _ 5 V V

N I H 2

6

C H _ A

C H _ B

N C

2 0

D 2 M L

D 1 M L

5

4

V P S V

O V L 1

D D A _ 5 V V

2 1

2 2

N I H 1

H 1 O V

M M C O

3

2 3

2 4

V P S 1

2

D D A _ 5 V V

1

L O N

1

C H _ B

)

E R W E L P B O S I A D V = 1 O V ( T 0

N A B N L W E R E D W O O P

E

D D A _ 5 V V

0 V 1 O .

T

0 V = E

N R A A I G N O G L

N R A A I G N H G I

0 V 5 - . 2 5 V 2 . = E

I N

I L H O P

B L

A L A N D C H A N R N O C E H F T A N N E R C U C E I I V

A G D R V I N A O I L T P O

Figure 65. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit (Continued)

Rev. E | Page 41 of 52

AD9259

Data Sheet

N D G

1

N D G

1

Figure 66. Evaluation Board Schematic, Power Supply Inputs

Rev. E | Page 42 of 52

Data Sheet

AD9259

Figure 67. Evaluation Board Layout, Primary Side

Rev. E | Page 43 of 52

AD9259

Data Sheet

Figure 68. Evaluation Board Layout, Ground Plane

Rev. E | Page 44 of 52

Data Sheet

AD9259

Figure 69. Evaluation Board Layout, Power Plane

Rev. E | Page 45 of 52

AD9259

Data Sheet

Figure 70. Evaluation Board Layout, Secondary Side (Mirrored Image)

Rev. E | Page 46 of 52

Data Sheet

AD9259

Table 17. Evaluation Board Bill of Materials (BOM)¹

Manufacturer’s

Manufacturer Part Number

Item

Qty.

1

75

Reference Designator

Device

PCB

Capacitor

Package

PCB

402

Value

1

2

AD9259LFCSP_REVA

PCB

0.1 μF, ceramic,

C101, C102, C107,

C10±, C109, C114,

C115, C116, C121,

C122, C123, C12±,

C201, C203, C204,

C205, C206, C210,

C211, C212, C213,

C216, C217, C21±,

C219, C220, C221,

C222, C223, C224,

C310, C311, C312,

C313, C314, C316,

C319, C320, C321,

C324, C325, C409,

C410, C412, C414,

C416, C417, C419,

C422, C423, C424,

C425, C427, C42±,

C429, C503, C505,

C507, C509, C516,

C517, C51±, C519,

C520, C521, C522,

C523, C524, C525,

C526, C527, C52±,

C529, C530, C531

Murata

GRM155R71C104KA±±D

X5R, 10 V, 10% tol

3

4

C104, C111, C11±,

C125

Capacitor

402

2.2 pF, ceramic,

COG, 0.25 pF tol,

50 V

Murata

GRM1555C1H2R2GZ01B

4

1

2

4

1

9

C315, C326, C413,

C426

C202

Capacitor

±05

603

402

1206

603

10 μF, 6.3 V ±10%

ceramic, X5R

2.2 μF, ceramic,

X5R, 6.3 V, 10% tol

1000 pF, ceramic,

X7R, 25 V, 10% tol

0.01± μF, ceramic,

X7R, 16 V, 10% tol

22 pF, ceramic,

NPO, 5% tol, 50 V

10 μF, tantalum,

16 V, 20% tol

Murata

AVX

GRM219R60J106KE19D

GRM1±±C70J225KE20D

GRM155R71H102KA01D

0402YC1±3KAT2A

5

6

C309, C411

7

C317, C322, C415,

C420

C31±, C323, C41±,

C421

±

Murata

Rohm

GRM1555C1H220JZ01D

TCA1C106M±R

9

C501

10

C214, C512, C513,

C514, C515, C532,

C533, C534, C535

1 μF, ceramic, X5R, Murata

6.3 V, 10% tol

GRM1±±R61C105KA93D

11

±

C305, C306, C307,

C30±, C405, C406,

C407, C40±

C502, C504, C506,

C50±

Capacitor

±05

0.1 μF, ceramic,

X7R, 50 V, 10% tol

Murata

GRM21BR71H104KA01L

12

13

14

15

16

4

1

2

1

Capacitor

Diode

LED

603

10 μF, ceramic,

X5R, 6.3 V, 20% tol

30 V, 20 mA, dual

Schottky

Green, 4 V, 5 m

candela

GRM1±±R60J106M

HSMS2±12-TRIG

LNJ314G±TRA

SK33-TP

CR201

SOT-23

603

Agilent

Technologies

Panasonic

CR401, CR501

D502

Diode

DO-214AB 3 A, 30 V, SMC

Micro

Commercial Co.

Micro

D501

DO-214AA 2 A, 50 V, SMC

S2A-TP

Commercial Co.

Rev. E | Page 47 of 52

AD9259

Data Sheet

Manufacturer’s

Manufacturer Part Number

Item

Qty.

Reference Designator

Device

Package

Value

17

1

F501

Fuse

1210

6.0 V, 2.2 A trip-

current resettable

fuse

Tyco/Raychem NANOSMDC110F-2

1±

19

1

FER501

Choke coil

2020

603

10 μH, 5 A, 50 V,

190 Ω @ 100 MHz

10 Ω, test freq

100 MHz, 25% tol,

500 mA

Murata

DLW5BSN191SQ2L

BLM1±BA100SN1B

12

FB101, FB102, FB103,

FB104, FB105, FB106,

FB107, FB10±, FB109,

FB110, FB111, FB112

Ferrite bead

20

21

22

1

2

4

JP301

Connector

2-pin

3-pin

12-pin

100 mil header

jumper, 2-pin

100 mil header

jumper, 3-pin

100 mil header

male, 4 × 3 triple

row straight

Samtec

TSW-102-07-G-S

TSW-103-07-G-S

TSW-104-0±-G-T

J205, J402

J201 to J204

23

24

25

26

1

J401

Connector

10-pin

1210

402

100 mil header,

male, 2 × 5 double

row straight

10 μH, bead core

3.2 × 2.5 × 1.6

SMD, 2 A

120 nH, test freq

100 MHz, 5% tol,

150 mA

Samtec

Murata

TSW-105-0±-G-D

BLM31PG500SN1L

LQG15HNR12J02B

NRC10ZOTRF

±

L501, L502, L503, L504, Ferrite bead

L505, L506, L507, L50±

4

L309, L310, L409, L410 Inductor

16

L301, L302, L303, L304, Resistor

L305, L306, L307, L30±,

±05

0 Ω, 1/± W, 5% tol

NIC

Components

L401, L402, L403, L404,

L405, L406, L407, L40±

27

2±

1

5

OSC201

Oscillator

SMT

SMA

Clock oscillator,

50.00 MHz, 3.3 V

Side-mount SMA

for 0.063" board

thickness

Valpey Fisher

VFAC3H-L-50MHz

142-0710-±51

P101, P103, P105,

P107, P201

Connector

Johnson

Components

29

1

P202

Connector

Header

1469169-1, right

angle 2-pair,

25 mm, header

assembly

Tyco

6469169-1

30

31

1

P503

Connector

Resistor

0.1", PCMT SC1153, power

supply connector

Switchcraft

RAPC722X

15

R201, R205, R214,

R215, R221, R239,

R312, R315, R31±,

R411, R414, R417,

R425, R429, R430

402

10 kΩ, 1/16 W,

5% tol

NIC

Components

NRC04J103TRF

32

14

R103, R117, R129,

R142, R216, R217,

R21±, R223, R224,

R237, R420, R426,

R427, R42±

Resistor

402

0 Ω, 1/16 W,

5% tol

NIC

Components

NRC04Z0TRF

33

34

4

R102, R115, R12±,

R141

R104, R116, R130,

R143

Resistor

402

603

64.9 Ω, 1/16 W,

1% tol

0 Ω, 1/10 W,

5% tol

NIC

Components

NIC

Components

NRC04F64R9TRF

NRC06Z0TRF

Rev. E | Page 4± of 52

Data Sheet

AD9259

Manufacturer’s

Manufacturer Part Number

Item

Qty.

Reference Designator

Device

Package

Value

35

15

R109, R111, R112,

R123, R125, R126,

R135, R13±, R139,

R14±, R149, R150,

R431, R432, R433

Resistor

402

1 kΩ, 1/16 W,

1% tol

NIC

Components

NRC04F1001TRF

36

±

R10±, R110, R121,

R122, R134, R136,

R146, R147

Resistor

402

33 Ω, 1/16 W,

5% tol

NIC

Components

NRC04J330TRF

37

3±

39

40

41

42

4

3

1

2

R161, R162, R163,

R164

R202, R203, R204

Resistor

402

499 Ω, 1/16 W,

1% tol

100 kΩ, 1/16 W,

1% tol

4.12 kΩ, 1/16 W,

1% tol

49.9 Ω, 1/16 W,

0.5% tol

4.99 kΩ, 1/16 W,

5% tol

10 kΩ, cermet

trimmer

NIC

Components

NIC

Components

NIC

Components

Susumu

NRC04F4990TRF

NRC04F1003TRF

NRC04F4121TRF

RR0510R-49R9-D

NRC04F4991TRF

CT94EW103

Resistor

402

R222

Resistor

402

R213

Resistor

402

R229

Resistor

402

NIC

Components

BC

R230, R319

Potentiometer

3-lead

Components

potentiometer,

1±-turn top adjust,

10%, 1/2 W

43

44

45

1

±

R22±

R320

Resistor

402

470 kΩ, 1/16 W,

5% tol

39 kΩ, 1/16 W,

5% tol

1±7 Ω, 1/16 W,

1% tol

NIC

Components

NIC

Components

NIC

Components

NRC04J474TRF

NRC04J393TRF

NRC04F1±70TRF

R307, R30±, R309,

R310, R407, R40±,

R409, R410

46

47

4±

4

R305, R306, R405,

R406

R316, R317, R415,

R416

R245, R247, R249,

R251, R253, R255,

R257, R259, R261,

R263, R265

Resistor

402

201

374 Ω, 1/16 W,

1% tol

274 Ω, 1/16 W,

1% tol

NIC

Components

NIC

Components

NRC04F3740TRF

NRC04F2740TRF

ERJ-1GE0R00C

4

11

0 Ω, 1/20 W, 5% tol

Panasonic

49

50

51

52

53

54

55

1

2

1

5

R41±

Resistor

Switch

402

4.75 kΩ, 1/16 W,

1% tol

261 Ω, 1/16 W,

1% tol

261 Ω, 1/16 W,

1% tol

243 Ω, 1/16 W,

1% tol

100 Ω, 1/16 W,

1% tol

Light touch,

100GE, 5 mm

ADT1-1WT, 1:1

impedance ratio

transformer

NIC

Components

NIC

Components

NIC

Components

NIC

Components

NRC04J472TRF

NRC04F2610TRF

NRC06F2610TRF

NRC04F2430TRF

NRC04F1000TRF

EVQ-PLDA15

R419

402

R501

603

R240, R241

R242, R243

S401

402

NIC

Components

Panasonic

SMD

CD542

T101, T102, T103,

T104, T201

Transformer

Mini-Circuits

ADT1-1WT+

56

2

U501, U503

IC

SOT-223

ADP3339AKC-1.±,

1.5 A, 1.± V LDO

regulator

Analog Devices ADP3339AKCZ-1.±

Rev. E | Page 49 of 52

AD9259

Data Sheet

Manufacturer’s

Manufacturer Part Number

Item

Qty.

Reference Designator

Device

Package

Value

57

2

U301, U401

IC

LFCSP,

CP-32

AD±332ACP,

ultralow noise

precision dual VGA

Analog Devices AD±332ACPZ

5±

59

60

1

U504

U502

U201

IC

SOT-223

LFCSP,

ADP3339AKC-5

ADP3339AKC-3.3

AD9259BCPZ-50,

quad, 14-bit, 50

MSPS serial LVDS

1.± V ADC

Analog Devices ADP3339AKCZ-5

Analog Devices ADP3339AKCZ-3.3

Analog Devices AD9259BCPZ-50

CP-4±-1

61

1

U203

IC

SOT-23

ADR510ARTZ, 1.0 V, Analog Devices ADR510ARTZ

precision low

noise shunt

voltage reference

62

63

64

65

1

U202

U403

U404

U402

IC

LFCSP

CP-32-2

SC70,

MAA06A

SC70,

MAA06A

±-SOIC

AD9515BCPZ

Analog Devices AD9515BCPZ

NC7WZ07

Fairchild

Microchip

NC7WZ07P6X_NL

NC7WZ16

NC7WZ16P6X_NL

PIC12F629-I/SN

Flash prog

mem 1k × 14,

RAM size 64 × ±,

20 MHz speed,

PIC12F controller

series

¹This BOM is RoHS compliant.

Rev. E | Page 50 of 52

Data Sheet

AD9259

OUTLINE DIMENSIONS

7.10

7.00 SQ

6.90

0.30

0.23

0.18

0.60 MAX

PIN 1

INDICATOR

37

36

48

1

PIN 1

INDICATOR

0.50

REF

6.85

*

5.55

5.50 SQ

5.45

6.75 SQ

6.65

EXPOSED

PAD

(BOTTOM VIEW)

25

24

12

13

0.50

0.40

0.30

0.22 MIN

TOP VIEW

5.50 REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.08

0.20 REF

*

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

WITH EXCEPTION TO EXPOSED PAD DIMENSION.

Figure 71. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

7 mm × 7 mm Body, Very Thin Quad

(CP-48-8)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Notes Range

Package

Option

Model¹

Package Description

AD9259ABCPZ-50

AD9259ABCPZRL7-50

AD9259-50EBZ

−40°C to +85°C

48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7”Tape and Reel

Evaluation Board

CP-48-8

2

¹Z = RoHS Compliant Part.

²Interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to HSC-ADC-EVALCZ data capture board.

Rev. E | Page 51 of 52

AD9259

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D05965-0-1 /11(E)

Rev. E | Page 52 of 52


型号：	AD9259ABCPZ-50
厂家：	ADI
描述：	Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC 转换器
文件：	总53页 (文件大小：1613K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9259ABCPZ-50 [ADI]

相关型号：

AD9259ABCPZRL7-50

AD9259BCPZ-50

AD9259BCPZRL-50

AD9259BCPZRL7-50

AD9259_17

AD9260

AD9260-EB

AD9260AS

AD9260ASRL

AD9260ASZ

AD9260ASZRL

AD9260EB