AD9267BCPZ_技术文档

10 MHz Bandwidth, 640 MSPS

Dual Continuous Time Sigma-Delta Modulator

AD9267

FUNCTIONAL BLOCK DIAGRAM

FEATURES

AVDD PDWNB

PDWNA

DRVDD

SNR: 83 dB (85 dBFS) to 10 MHz input

SFDR: −88 dBc to 10 MHz input

Noise figure: 15 dB

Input impedance: 1 kΩ

Power: 416 mW

10 MHz real or 20 MHz complex bandwidth

1.8 V analog supply operation

On-chip PLL clock multiplier

On-chip voltage reference

Twos complement data format

640 MSPS, 4-bit LVDS data output

Serial control interface (SPI)

OR±A

D3±A

VIN+A

VIN–A

Σ-Δ

MODULATOR

D0±A

PLL_LOCKED

PLLMULT4

PLLMULT3

PLLMULT2

AD9267

CLK+

CLK–

PHASE-

LOCKED

LOOP

VREF

CFILT

DCO±

D3±B

VIN–B

VIN+B

Σ-Δ

MODULATOR

D0±B

OR±B

APPLICATIONS

SERIAL

INTERFACE

Baseband quadrature receivers: CDMA2000, W-CDMA,

multicarrier GSM/EDGE, 802.16x, and LTE

Quadrature sampling instrumentation

AGND

SDIO/

SCLK/

CSB DGND

PLLMULT1 PLLMULT0

GENERAL DESCRIPTION

Figure 1.

The AD9267 is a dual continuous time (CT) sigma-delta (Σ-Δ)

modulator with −88 dBc of dynamic range over 10 MHz real

or 20 MHz complex bandwidth. The combination of high

dynamic range, wide bandwidth, and characteristics unique

to the continuous time Σ-Δ modulator architecture makes the

AD9267 an ideal solution for wireless communication systems.

The AD9267 operates on a 1.8 V power supply, consuming

416 mW. The AD9267 is available in a 64-lead LFCSP and

is specified over the industrial temperature range (−40°C

to +85°C).

PRODUCT HIGHLIGHTS

1. Continuous time Σ-Δ architecture efficiently achieves high

dynamic range and wide bandwidth.

2. Passive input structure reduces or eliminates the require-

ments for a driver amplifier.

3. An oversampling ratio of 32× and high order loop filter

provide excellent alias rejection, reducing or eliminating

the need for antialiasing filters.

4. Operates from a single 1.8 V power supply.

5. A standard serial port interface (SPI) supports various

product features and functions.

The AD9267 has a resistive input impedance that significantly

relaxes the requirements of the driver amplifier. In addition, a

32× oversampled fifth-order continuous time loop filter attenuates

out-of-band signals and aliases, reducing the need for external

filters at the input. The low noise figure of 15 dB relaxes the

linearity requirements of the front-end signal chain components,

and the high dynamic range reduces the need for an automatic

gain control (AGC) loop.

A differential input clock controls all internal conversion cycles.

An external clock input or the integrated integer-N PLL provides

the 640 MHz internal clock needed for the oversampled conti-

nuous time Σ-Δ modulator. The digital output data is presented

as 4-bit, LVDS at 640 MSPS in twos complement format. A data

clock output (DCO) is provided to ensure proper latch timing

with receiving logic. Additional digital signal processing may be

required on the 4-bit modulator output to remove the out-of-band

noise and to reduce the sample rate.

6. Features a low pin count, high speed LVDS interface with

data output clock.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9267

TABLE OF CONTENTS

Features .............................................................................................. 1

Equivalent Circuits......................................................................... 12

Theory of Operation ...................................................................... 13

Analog Input Considerations ................................................... 13

Clock Input Considerations...................................................... 14

Power Dissipation and Standby Mode .................................... 17

Digital Outputs ........................................................................... 17

Timing ......................................................................................... 18

Serial Port Interface (SPI).............................................................. 19

Configuration Using the SPI..................................................... 19

Hardware Interface..................................................................... 20

Applications Information.............................................................. 21

Filtering Requirement................................................................ 21

Memory Map .................................................................................. 23

Memory Map Definitions ......................................................... 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

REVISION HISTORY

7/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD9267

SPECIFICATIONS

DC SPECIFICATIONS

All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN¹= −2.0 dBFS, unless otherwise noted.

Table 1.

Parameter

Temp

Min

Typ

16

Max

Unit

Bits

RESOLUTION

Full

ANALOG INPUT BANDWIDTH

ACCURACY

10

MHz

No Missing Codes

Offset Error

Gain Error

Integral Nonlinearity (INL)²

MATCHING CHARACTERISTIC

Offset Error

Full

2ꢀ°C

Guaranteed

0.02ꢀ

0.ꢁ

0.2

2.ꢀ

% FSR

LSB

1.ꢀ

Full

0.03ꢀ

0.2

1.2

% FSR

Gain Error

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

1.ꢀ

4ꢁ

ppm/°C

mV

INTERNAL VOLTAGE REFERENCE

ANALOG INPUT

Input Span, VREF = 0.ꢀ V

Input Resistance

Input Common Mode

POWER SUPPLIES

Supply Voltage

AVDD

496

1.ꢁ

ꢀ00

ꢀ0ꢀ

1.9

Full

2

1

V p-p diff

kΩ

V

1.8

Full

1.ꢁ

1.8

1.9

V

CVDD

DVDD

DRVDD

Supply Current

I_AVDD², PLL Enabled

I_AVDD², PLL Disabled

I_CVDD², PLL Enabled

I_CVDD², PLL Disabled

Full

1ꢀ0.ꢁ

1ꢀ1.2

ꢀꢁ

8

ꢁ1.ꢀ

0.26

162

161

63

9.2

ꢁ8

mA

2

I_DVDD

2

I_DRVDD

0.3

POWER CONSUMPTION

Sine Wave Input², PLL Disabled

Sine Wave Input, PLL Enabled

Power-Down Power

Standby Power

Sleep Power

Full

2ꢀ°C

Full

416

ꢀ03

110

9

mW

3

4

¹Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted.

²Measured with a low input frequency, full-scale sine wave with approximately ꢀ pF loading on each output bit.

Rev. 0 | Page 3 of 24

AD9267

AC SPECIFICATIONS

All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN¹= −2.0 dBFS, unless otherwise noted.

Table 2.

Parameter²

Temp

Min

Typ

Max

Unit

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 2.4 MHz

f_IN= 4.2 MHz

f_IN= 8.4 MHz

Full

2ꢀ°C

81

83

dB

SPURIOUS-FREE DYNAMIC RANGE (WORST SECOND OR THIRD HARMONIC)³

f_IN= 2.4 MHz

f_IN= 4.2 MHz

f_IN= 8.4 MHz

Full

2ꢀ°C

−88

<−120

−80

dBc

NOISE SPECTRAL DENSITY

AIN = −2 dBFS

AIN = −40 dBFS

Full

−1ꢀꢀ

−1ꢀ6

−1ꢀ3

−1ꢀꢀ

dBFS/Hz

NOISE FIGURE^{2, 4}

AIN = −2 dBFS

AIN = −40 dBFS

2ꢀ°C

16

1ꢀ

dB

TWO-TONE SFDR

f_IN1= 1.8 MHz @ −8 dBFS, f_IN2= 2.1 MHz @ −8 dBFS

f_IN1= 3.ꢁ MHz @ −8 dBFS, f_IN2= 4.2 MHz @ −8 dBFS

f_IN1= ꢁ.2 MHz @ −8 dBFS, f_IN2= 8.4 MHz @ −8 dBFS

ANALOG INPUT BANDWIDTH

2ꢀ°C

−89.ꢀ

−93

−8ꢁ

dBc

MHz

10

¹Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted.

²See the AN-83ꢀ Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

³Spurious-free dynamic range excluding the second or third harmonic is limited by the FFT size, <−120 dBFS.

⁴Noise figure with respect to ꢀ0 Ω. AD926ꢁ internal impedance is 1000 Ω differential. See the AN-83ꢀ for a definition.

Rev. 0 | Page 4 of 24

AD9267

DIGITAL SPECIFICATIONS

All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS,

unless otherwise noted.

Table 3.

Parameter

Temp

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS¹/LVDS/LVPECL

Differential Input Voltage

Input Common-Mode Range

Full

0.4

0.8

4ꢀ0

2

V p-p

mV

μA

kΩ diff

pF

High Level Input Current

Low Level Input Current

Input Resistance

−60

+60

20

1

Input Capacitance

LOGIC INPUTS (SCLK)

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.2

0

−ꢀ0

−10

DRVDD + 0.3

0.8

−ꢁꢀ

+10

V

μA

kΩ

pF

30

2

Input Capacitance

LOGIC INPUTS (SDIO, CSB, RESET)

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.2

0

−10

+40

DRVDD + 0.3

0.8

+10

V

μA

kΩ

pF

+13ꢀ

26

ꢀ

Input Capacitance

DIGITAL OUTPUTS (D0 x to D3 x)

ANSI-644

Logic Compliance

LVDS

Differential Output Voltage (V_OD

)

Full

24ꢁ

1.12ꢀ

4ꢀ4

1.3ꢁꢀ

mV

V

Output Offset Voltage (V_OS

)

Output Coding (Default)

Low Power, Reduced Signal Option

Logic Compliance

Twos complement

LVDS

Differential Output Voltage (V_OD

)

Full

1ꢀ0

1.10

2ꢀ0

1.30

mV

V

Output Offset Voltage (V_OS

)

Output Coding (Default)

Twos complement

¹For voltage swings beyond the specified range, clamping diodes are recommended.

Rev. 0 | Page ꢀ of 24

AD9267

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted.

Table 4.

Parameter¹

Conditions/Comments

Temp

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Input CLK Rate

Using clock multiplier

Full

30

6.2ꢀ

40

160

33.3

60

MSPS

ns

CLK Period

CLK Duty Cycle

ꢀ0

%

CLOCK INPUT PARAMETERS

Conversion Rate

CLK Period

Direct clocking

Full

608

1.48

40

640

1.ꢀ62ꢀ

ꢀ0

6ꢁ2

1.ꢁ2

60

MSPS

ns

%

CLK Duty Cycle

DATA OUTPUT PARAMETERS

Data Propagation Delay (t_PD

DCO Propagation Delay (t_DCO

2

)

Full

160

-60

180

ꢀ10

268

200

1

840

ꢀꢁ0

280

ps

)

ps

Ps

DCO to Data Skew (t_SKEW

)

Aperture Uncertainty (Jitter, t_J)

WAKE-UP TIME

ps rms

Power-Down Power

Standby Power

Sleep Power

2ꢀ°C

3

9

1ꢀ

100

Μs

ꢂs

ns

OUT-OF-RANGE RECOVERY TIME

SERIAL PORT INTERFACE³

SCLK Period (t_SCLK

SCLK Pulse Width High Time (t_SHIGH

SCLK Pulse Width Low Time (t_SLOW

SDIO to SCLK Set-Up Time (t_SDS

SDIO to SCLK Hold Time (t_SDH

CSB to SCLK Set-Up Time (t_SS)

CSB to SCLK Hold Time (t_SH

)

Full

40

ns

)

16

ꢀ

)

2

ꢀ

2

)

¹See the AN-83ꢀ Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

²Output propagation delay is measured from CLK ꢀ0% transition to data D0 x to D3 x ꢀ0% transition, with ꢀ pF load.

³See Figure 42 and the Serial Port Interface (SPI) section.

Timing Diagram

CLK±

t_DCO

DCO±

t_SKEW

t_PD

D0±x TO D3±x

Figure 2. Timing Diagram

Rev. 0 | Page 6 of 24

AD9267

ABSOLUTE MAXIMUM RATINGS

Table 5.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

Electrical

AVDD to AGND

DVDD to DGND

DRVDD to DGND

AGND to DGND

AVDD to DRVDD

CVDD to CGND

−0.3 V to +2.0 V

−0.3 V to +3.9 V

−0.3 V to +0.3 V

−3.9 V to +2.0 V

−0.3 V to +2.0 V

−0.3 V to +0.3 V

−0.3 V to +2.0 V

−0.3 V to +3.9 V

−0.3 V to +2.ꢀ V

−0.3 V to +2.0 V

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for

the LFCSP package. Soldering the exposed paddle to the PCB

increases the reliability of the solder joints, maximizing the

thermal capability of the package.

CGND to DGND

D0 A to D3 A to DGND

D0 B to D3 B to DGND

DCO to DGND

OR A, OR B to DGND

PDWNA to DGND

PDWNB to DGND

PLLMULTx to DGND

SDIO to DGND

CSB to AGND

SCLK to AGND

VIN A, VIN B to AGND

CLK+, CLK− to CGND

Environmental

Typical θ_JAand θ_JCare specified for a 4-layer board in still air.

Airflow increases heat dissipation, effectively reducing θ_JA. In

addition, metal in direct contact with the package leads from

metal traces, through holes, ground, and power planes reduces

the θ_JA.

Table 6. Thermal Resistance

Package Type

θ_JA

Unit

64-Lead LFCSP (CP-64-4)

22

°C/W

Storage Temperature Range

Operating Temperature Range

−6ꢀ°C to +12ꢀ°C

−40°C to +8ꢀ°C

ESD CAUTION

Lead Temperature (Soldering, 10 sec) 300°C

Junction Temperature 1ꢀ0°C

Rev. 0 | Page ꢁ of 24

AD9267

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

CLK–

CVDD

PDWNA

PDWNB

PLL_LOCKED

DVDD

1

2

3

4

5

6

7

8

9

48 SCLK/PLLMULT0

47 SDIO/PLLMULT1

46 PLLMULT2

45 PLLMULT3

44 PLLMULT4

43 DVDD

42 DGND

41 DRVDD

40 D3+A

39 D3–A

38 D2+A

37 D2–A

36 D1+A

AD9267

DGND

DRVDD

D0–B

D0+B 10

D1–B 11

D1+B 12

D2–B 13

D2+B 14

D3–B 15

D3+B 16

TOP VIEW

(Not to Scale)

35 D1–A

34 D0+A

33 D0–A

NOTES

1. DNC = DO NOT CONNECT.

2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE

LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB

INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING

THE THERMAL CAPACITY OF THE PACKAGE.

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CLK−

Differential Clock Input (−).

2

CVDD

Clock Supply (1.8 V).

3, 4

ꢀ

PDWNA, PDWNB

PLL_LOCKED

DVDD

DGND

DRVDD

D0−B, D0+B to D3−B, D3+B

OR−B, OR+B

DCO−, DCO+

Power-Down Pins. Active high.

PLL Lock Indicator.

Digital Supply (1.8 V).

6, 2ꢀ, 43

ꢁ, 24, 42

8, 23, 41

9 to 16

1ꢁ, 18

19, 20

Digital Ground.

Digital Output Driver Supply

Channel B Differential LVDS Data Output Bits. D0+B is the LSB and D3+B is the MSB.

Channel B Overrange Indicator Pins.

Differential Data Clock Output.

Do Not Connect.

21, 22, 26 to 30 DNC

31, 32

33 to 40

44, 4ꢀ, 46

4ꢁ

48

49

OR−A, OR+A

D0−A, D0+A to D3−A, D3+A

PLLMULT4, PLLMULT3, PLLMULT2

SDIO/PLLMULT1

SCLK/PLLMULT0

CSB

Channel A Overrange Indicator Pins.

Channel A Differential LVDS Data Output Bits. D0+A is the LSB and D3+A is the MSB.

PLL Mode Selection Pins.

Serial Port Interface Data Input/Output/PLL Mode Selection Pins.

Serial Port Interface Clock/PLL Mode Selection Pins.

Serial Port Interface Chip Select Pin Active Low.

Chip Reset.

ꢀ0

RESET

ꢀ1, 62

ꢀ2, ꢀꢀ, ꢀ8, 61

ꢀ3, ꢀ4

ꢀ6

AGND

AVDD

VIN+A, VIN−A

VREF

Analog Ground.

Analog Supply (1.8 V).

Channel A Analog Input.

Voltage Reference Input.

ꢀꢁ

ꢀ9, 60

63

CFILT

VIN+B, VIN−B

CGND

Noise Limiting Filter Capacitor.

Channel B Analog Input.

Clock Ground.

64

CLK+

Differential Clock Input (+).

6ꢀ

Exposed paddle (EPAD)

Analog Ground. (Pin 6ꢀ is the exposed thermal pad on the bottom of the package.) The

exposed paddle must be soldered to analog ground of the PCB to achieve optimal electrical

and thermal performance.

Rev. 0 | Page 8 of 24

AD9267

TYPICAL PERFORMANCE CHARACTERISTICS

All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, T_A= 25°C, unless

otherwise noted. The output spectrums shown in Figure 4 through Figure 9 were obtained after 16× decimation at the output of the AD9267

and are shown for a 10 MHz bandwidth.

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

–100

–110

–120

–130

–140

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

FREQUENCY (MHz)

Figure 4. Single-Tone FFT with f_IN= 2.4 MHz

Figure 7. Two-Tone FFT with f_IN1= 2.1 MHz, f_IN2= 2.4 MHz

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

–100

–110

–120

–130

–140

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

FREQUENCY (MHz)

Figure 5. Single-Tone FFT with f_IN= 4.2 MHz

Figure 8. Two-Tone FFT with f_IN1= 3.6 MHz, f_IN2= 4.2 MHz

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

–100

–110

–120

–130

–140

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

FREQUENCY (MHz)

Figure 9. Two-Tone FFT with f_IN1= 7.2 MHz, f_IN2= 8.4 MHz

Figure 6. Single-Tone FFT with f_IN= 8.4 MHz

Rev. 0 | Page 9 of 24

AD9267

–50

84.0

83.8

83.6

83.4

83.2

83.0

82.8

82.6

82.4

82.2

82.0

–60

–70

–80

–90

–100

–110

–120

–130

0

50

100

150

200

250

300

0

1

2

3

4

5

6

7

8

9

FREQUENCY (MHz)

Figure 10. Noise Transfer Function (NTF)

Figure 13. Single-Tone SNR vs. Input Frequency

84.0

83.8

83.6

83.4

83.2

83.0

82.8

82.6

82.4

82.2

82.0

120

100

80

60

40

20

0

SFDR

(dBFS)

SNR

(dBFS)

SFDR

(dBc)

SNR

(dB)

1.70

1.75

1.80

1.85

1.90

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

INPUT AMPLITUDE (dBFS)

COMMON-MODE VOLTAGE (V)

Figure 14. SNR vs. Input Common-Mode Voltage

Figure 11. Single-Tone SNR and SFDR vs. Input Amplitude with f_IN= 2.4 MHz

83.4

91

90

83.2

83.0

82.8

82.6

82.4

82.2

82.0

81.8

89

1.9V

1.8V

1.7V

1.9V

88

87

1.8V

86

85

1.7V

84

83

–60

–40

–20

0

20

40

60

80

100

–60

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 15. SNR vs. Temperature

Figure 12. SFDR vs. Temperature

Rev. 0 | Page 10 of 24

AD9267

–40

–50

84

83

82

81

80

79

78

2.4MHz

8.4MHz

–60

SFDR (dBc)

–70

–80

–90

SFDR (dBFS)

–100

–110

–120

4.0

5.0

7.0

6.0

8.0

9.0

10.5 12.5 15.0 17.0

–60

–50

–40

–30

–20

–10

4.5

7.5

8.5

10.0 12.0 14.0 16.0 21.0

INPUT AMPLITUDE (dBFS)

PLL DIVIDE RATIO

Figure 16. Two-Tone SFDR vs. Input Amplitude with

f_IN1= 2.1 MHz, f_IN2= 2.4 MHz

Figure 18. Single-Tone SNR vs. PLL Divide Ratio with

f_IN1= 2.4 MHz, f_IN2= 8.4 MHz

–40

–50

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–60

SFDR (dBc)

–70

–80

–90

–100

–110

–120

SFDR (dBFS)

–60

–50

–40

–30

–20

–10

0

8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536

OUTPUT CODE

INPUT AMPLITUDE (dBFS)

Figure 19. INL with f_IN= 2.4 MHz

Figure 17. Two-Tone SFDR vs. Input Amplitude with

f_IN1= 7.2 MHz, f_IN2= 8.4 MHz

Rev. 0 | Page 11 of 24

AD9267

EQUIVALENT CIRCUITS

1kΩ

SCLK

30kΩ

500Ω

2V p-p DIFFERENTIAL

1.8V CM

500Ω

Figure 20. Equivalent Analog Input Circuit

Figure 23. Equivalent SCLK Input Circuit

CVDD

AVDD

26kΩ

1kΩ

CSB

CLK+

CVDD

CLK–

10kΩ

90kΩ

10kΩ

30kΩ

Figure 21. Equivalent Clock Input Circuit

Figure 24. Equivalent CSB Input Circuit

DRVDD

V

D–

D+

DRVDD

V

1kΩ

SDIO

DGND

NOTES

1. D– AND D+ REFERS TO

THE D0±x TO D3±x PINS.

Figure 22. Equivalent SDIO Input Circuit

Figure 25. Equivalent Digital Output Circuit

2.85kΩ

8.5kΩ

10kΩ

0.5V

3.5kΩ

10µF

TO CURRENT

GENERATOR

Figure 26. Equivalent VREF Circuit

Rev. 0 | Page 12 of 24

AD9267

THEORY OF OPERATION

The AD9267 uses a continuous time Σ-Δ modulator to convert

the analog input to a digital word. The modulator consists of a

continuous time loop filter preceding a quantizer (see Figure 27),

which samples at f_MOD= 640 MSPS. This produces an oversam-

pling ratio (OSR) of 32 for a 10 MHz input bandwidth. The output

of the quantizer is fed back to a DAC that ideally cancels the

input signal. The incomplete input cancellation residue is filtered

by the loop filter and is used to form the next quantizer sample.

MODULATOR

In contrast, the continuous time Σ-Δ modulator used within the

AD9267 has inherent antialiasing. The antialiasing property

results from sampling occurring at the output of the loop filter

(see Figure 31), and thus aliasing occurs at the same point in the

loop as quantization noise is injected; aliases are shaped by the

same mechanism as quantization noise. The quantization noise

transfer function, NTF(f), has zeros in the band of interest and

in all alias bands because NTF(f) is a discrete time transfer

function, whereas the loop filter transfer function, LF(f),

introduces poles only in the band of interest because LF(f) is a

continuous time transfer function. The signal transfer function,

being the product of NTF(f) and LF(f), only has zeros in all

alias bands and therefore suppresses all aliases.

LOOP FILTER

QUANTIZER

+

ADC

H(f)

–

LF(f)

LOOP FILTER

INPUT

LF(f)

Figure 27. Σ-Δ Modulator Overview

QUANTIZATION

f_MOD

The quantizer produces a nine-level digital word. The quantiza-

tion noise is spread uniformly over the Nyquist band (see

Figure 28) but the feedback loop causes the quantization noise

present in the nine-level output to have a nonuniform spectral

shape. This noise shaping technique (see Figure 29) pushes the

in-band noise out of band; therefore, the amount of quantiza-

tion noise in the frequency band of interest is minimal.

NOISE

f_MOD

OUTPUT

H(z)

NTF(f)

f

f_MOD

Figure 31. Continuous Time Converter

Input Common Mode

QUANTIZATION NOISE

The analog inputs of the AD9267 are not internally dc biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device such that V_CM= AVDD is

recommended for optimum performance. The analog inputs

are 500 Ω resistors and the internal reference loop aims to

f_MOD/2

BAND OF INTEREST

Figure 28. Quantization Noise

develop 0.5 V across each input resistor (see Figure 32). With

0 V differential input, the driver sources 1 mA into each

analog input.

2.3V

NOISE SHAPING

AVDD – 0.5V

1.8V

1.3V

f_MOD/2

500Ω

BAND OF INTEREST

VIN+x

TO LOOP FILTER

Figure 29. Noise Shaping

STAGE 2

VIN–x

ANALOG INPUT CONSIDERATIONS

500Ω

2.3V

1.8V

The continuous time modulator removes the need for an anti-

alias filter at the input to the AD9267. A discrete time converter

aliases signals around the sample clock frequency and its

multiples to the band of interest (see Figure 30). An external

antialias filter is needed to reject these signals.

1.3V

DAC

FROM QUANTIZER

Figure 32. Input Common Mode

DESIRED

INPUT

UNDESIRED

SIGNAL

f_S

f_S/2

ADC

Figure 30. Discrete Time Converter

Rev. 0 | Page 13 of 24

AD9267

AVDD – 0.5V

Differential Input Configurations

V

= AVDD

p-p = 2V

Optimum performance can be achieved by driving the AD9267

in a differential input configuration. The ADA4937-2 differential

driver provides excellent performance and a flexible interface to

the ADC. The output common-mode voltage of the ADA4937-2 is

easily set by connecting AVDD to the V_OCMxpin of the ADA4937-2

(see Figure 33). The noise and linearity of the ADA4937-2 needs

important consideration because the system performance may

be limited by the ADA4937-2.

CM

IN

500Ω

VIN+x

VIN–x

0.5V

TO LOOP

FILTER

STAGE 2

VREF

10kΩ

AVDD

500Ω

REF

10µF

AVDD – 0.5V

+5V

+1.8V

CFILT

10µF

0.1µF

Figure 35. Voltage Reference Loop

200Ω

Internal Reference Connection

9

2V p-p

R

50Ω

200Ω

6

11

7

13

AVDD

VIN–x

VIN+x

To minimize thermal noise, the internal reference on the AD9267

is an unbuffered 0.5 V. It has an internal 10 kΩ series resistor,

which, when externally decoupled with a 10 ꢀF capacitor, limits

the noise (see Figure 36). Do not use the unbuffered reference

to drive any external circuitry. The internal reference is used by

default and when Serial Register 0x18[6] is reset.

V

OCM2

ADA4937-2

AD9267

V

S

T

60.4

12

15

SIGNAL

SOURCE

200Ω

0.1µF

49.9Ω

0.1µF

60.4Ω

–5V

Figure 33. Differential Input Configuration Using the ADA4937-2

For frequencies offset from dc, where SNR is a key parameter,

differential transformer coupling is the recommended input

configuration. An example is shown in Figure 34. The center

tap of the secondary winding of the transformer is connected to

AVDD to bias the analog input.

2.85kΩ

8.5kΩ

10kΩ

0.5V

3.5kΩ

10µF

TO CURRENT

GENERATOR

The signal characteristics must be considered when selecting a

transformer. Most RF transformers saturate at frequencies

below a couple of megahertz (MHz), and excessive signal power

can cause core saturation, which leads to distortion.

Figure 36. Internal Reference Configuration

External Reference Operation

If an external reference is desired, the internal reference can be

disabled by setting Serial Register 0x18[6] high. Figure 37 shows

an application using the ADR130B as a stable external reference.

0.5V

2V p-p

VIN+x

50Ω

1:1

R

50Ω

T

V

AD9267

S

ADR130B

AVDD

10kΩ

0.1µF

10µF

SIGNAL

SOURCE

VIN–x

AVDD

TO CURRENT

GENERATOR

0.1µF

Figure 37. External Reference Configuration

Figure 34. Differential Transformer Configuration

CLOCK INPUT CONSIDERATIONS

Voltage Reference

The AD9267 offers two modes of sourcing the ADC sample

clock (CLK+ and CLK−). The first mode uses an on-chip clock

multiplier that accepts a reference clock operating at the lower

input frequency. The on-chip phase-locked loop (PLL) then

multiplies the reference clock up to a higher frequency, which is

then used to generate all the internal clocks required by the Σ-Δ

modulator.

A stable and accurate 0.5 V voltage reference is built into the

AD9267. The reference voltage should be decoupled to minim-

ize the noise bandwidth using a 10 μF capacitor. The reference

is used to generate a bias current into a matched resistor such

that when used to bias the current in the feedback DAC, a

voltage of AVDD − 0.5 V is developed at the internal side of the

input resistors (see Figure 35). The current bias circuit should

also be decoupled on the CFILT pin with a 10 ꢀF capacitor. For

this reason, the VREF voltage should always be 0.5 V.

The clock multiplier provides a high quality clock that meets

the performance requirements of most applications. Using the

on-chip clock multiplier removes the burden of generating and

distributing the high speed clock.

Rev. 0 | Page 14 of 24

AD9267

The second mode bypasses the clock multiplier circuitry and

allows the clock to be directly sourced. This mode enables the

user to source a very high quality clock directly to the Σ-Δ

modulator. Sourcing the clock directly may be necessary in

demanding applications that require the lowest possible output

noise. Refer to Figure 18, which shows the degradation in SNR

performance for the various PLL settings.

If a differential clock is not available, the AD9267 can be driven

by a single-ended signal into the CLK+ terminal with the CLK−

terminal ac-coupled to ground. Figure 39 shows the circuit

configuration.

0.1µF

CLK+

CLK–

CLOCK

INPUT

ADC

AD9267

In either case, when using the on-chip clock multiplier or

sourcing the high speed clock directly, it is necessary that the

clock source have low jitter to maximize the Σ-Δ modulator

noise performance. High speed, high resolution ADCs and

modulators are sensitive to the quality of the clock input. As

jitter increases, the SNR performance of the AD9267 degrades

from that specified in Table 2. The jitter inherent to the part due

to the PLL root sum squares with any external clock jitter,

thereby degrading performance. To prevent jitter from dominating

the performance of the AD9267, the input clock source should be

no greater than 1 ps rms of jitter.

50Ω

SCHOTTKY

DIODES:

HSM2812

0.1µF

Figure 39. Single-Ended Clock

Another option is to ac couple a differential LVPECL signal to

the sample clock input pins, as shown in Figure 40. The AD951x

family of clock drivers is recommended because it offers excellent

jitter performance.

The CLK inputs are self-biased to 450 mV (see Figure 21); if

dc-coupled, it is important to maintain the specified 450 mV

input common-mode voltage. Each input pin can safely swing

from 200 mV p-p to 1 V p-p single-ended about the 450 mV

common-mode voltage. The recommended clock inputs are

CMOS or LVPECL.

0.1µF

CLK+

CLK–

CLOCK

INPUT

CLK

ADC

AD9267

AD951x

LVPECL

DRIVER

100Ω

CLOCK

INPUT

CLK

0.1µF

240Ω

1

50Ω

The specified clock rate of the Σ-Δ modulator, f_MOD, is 640 MHz.

The clock rate possesses a direct relationship with the available

input bandwidth of the ADC.

1

50Ω RESISTORS ARE OPTIONAL.

Figure 40. Differential LVPECL Sample Clock

Internal PLL Clock Distribution

Bandwidth = f_MOD÷ 64

The alternative clocking option available on the AD9267 is to

apply a low frequency reference clock and use the on-chip clock

multiplier to generate the high frequency f_MODrate. The internal

clock architecture is shown in Figure 41.

In either case, using the on-chip clock multiplier to generate the

Σ-Δ modulator clock rate or directly sourcing the clock, any

deviation from 640 MHz results in a change in input bandwidth.

The input range of the clock is limited to 640 MHz 5%.

CLK±

Direct Clocking

PHASE

DETECTOR

LOOP

FILTER

VCO

The default configuration of the AD9267 is for direct clocking

where the PLL is bypassed. Figure 38 shows one preferred

method for clocking the AD9267. A low jitter clock source is

converted from a single-ended signal to a differential signal

using an RF transformer. The back-to-back Schottky diodes

across the secondary side of the transformer limits clock

excursions into the AD9267 to approximately 0.8 V p-p differen-

tial. This helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9267 while

preserving the fast rise and fall times of the signal, which are

critical to achieving low jitter.

PLL

÷2

DIVIDER

÷N

PLLMULT

0x0A[5:0]

MODULATOR

CLOCK

640MSPS

PLLENABLE

0x09[2]

Figure 41. Internal Clock Architecture

The clock multiplication circuit operates such that the VCO

outputs a frequency, f_VCO, equal to the reference clock input

multiplied by N

MINI-CIRCUITS

TC1-1-13M+, 1:1

0.1µF

XFMR

CLK+

CLK–

CLOCK

INPUT

f

_VCO= (CLK ) × (N)

ADC

AD9267

50Ω

0.1µF

where N is the PLL multiplication (PLLMULT) factor.

SCHOTTKY

DIODES:

HSM2812

The Σ-Δ modulator clock frequency, f_MOD, is equal to

0.1µF

f

_MOD= f_VCO÷ 2

Figure 38. Transformer-Coupled Differential Clock

Rev. 0 | Page 1ꢀ of 24

AD9267

The reference clock, CLK , is limited to 30 MHz to 160 MHz

when configured to use the on-chip clock multiplier. Given the

input range of the reference clock and the available multiplica-

tion factors, the f_VCOis approximately 1280 MHz. This results in

the desired f_MODrate of 640 MHz with a 50% duty cycle.

Table 8. PLL Multiplication Factors

0x0A[5:0]

PLLMULT (N) 0x0A[5:0]

PLLMULT (N)

1

2

3

4

ꢀ

6

ꢁ

8

33

34

3ꢀ

36

3ꢁ

38

39

40

41

42

43

44

4ꢀ

46

4ꢁ

48

49

ꢀ0

ꢀ1

ꢀ2

ꢀ3

ꢀ4

ꢀꢀ

ꢀ6

ꢀꢁ

ꢀ8

ꢀ9

60

61

62

63

64

32

34

42

The PLL of the AD9267 can be controlled through either the serial

port interface or the PLLMULTx pins. For serial port interface

control, Register 0x09 and Register 0x0A are used. Before the

PLL enable register bit (PLLENABLE) is set, the PLL multiplica-

tion factor should be programmed into Register 0x0A[5:0].

After setting the PLLENABLE bit, the PLL locks and reports a

locked state in Register 0x0A[7]. If the PLL multiplication factor

is changed, the PLL enable bit should be reset and set again.

Some common clock multiplication factors are shown in Table 8.

9

10

11

12

13

14

1ꢀ

16

1ꢁ

18

19

20

21

22

23

24

2ꢀ

26

2ꢁ

28

29

30

31

32

10

12

14

1ꢀ

16

1ꢁ

18

20

21

24

2ꢀ

28

30

32

The recommended sequence for enabling and programming the

on-chip clock multiplier is as follows:

1. Apply a reference clock to the CLK pins.

2. Program the PLL multiplication factor in

Register 0x0A[5:0]. See Table 8.

3. Enable the PLL; Register 0x09 = 04 (decimal).

External PLL Control

At power-up, the serial interface is disabled until the first serial

port access. If the serial interface is disabled, the PLLMULTx

pins control the PLL multiplication factor. The five PLLMULTx

pins (Pin 44 to Pin 48) offer all the available multiplication

factors. If all PLLMULTx pins are tied high, the PLL is disabled

and the AD9267 assumes the high frequency modulator clock

rate that is applied to the CLK pins. Table 10 shows the relation-

ship between PLLMULTx pins and the PLL multiplication factor.

PLL Autoband Select

The PLL VCO has a wide operating range that is covered by

overlapping frequency bands. For any desired VCO output fre-

quency, there are multiple valid PLL band select values. The

AD9267 possesses an automatic PLL band select feature on chip

that determines the optimal PLL band setting. This feature can

be enabled by writing to Register 0x0A[6] and is the recom-

mended configuration with the PLL clocking option.

Table 9. Common Modulator Clock Multiplication Factors

CLK

(MHz)

0x0A[5:0]

(PLLMULT)

f_VCO

(MHz)

f_MOD

BW

(MHz)

30.ꢁ2

39.3216

ꢀ2.00

61.44

ꢁ6.80

ꢁ8.00

ꢁ8.6432

89.60

42

32

2ꢀ

21

1ꢁ

16

1ꢀ

14

10

8

1290.24

12ꢀ8.29

1300.00

1290.24

130ꢀ.60

1326.00

12ꢀ8.29

1344.00

1290.24

1228.80

1344.00

1228.80

12ꢀ8.29

64ꢀ.12

629.1ꢀ

6ꢀ0.00

64ꢀ.12

6ꢀ2.80

663.00

629.1ꢀ

6ꢁ2.00

64ꢀ.12

614.40

6ꢁ2.00

614.40

629.1ꢀ

10.08

9.83

10.16

10.08

10.20

10.36

9.83

10.ꢀ0

10.08

9.60

92.16

122.88

134.40

1ꢀ3.60

1ꢀꢁ.2864

10.ꢀ0

9.60

9.83

8

Rev. 0 | Page 16 of 24

AD9267

Table 10. PLLMULTx Pins and PLL Multiplication Factor

DIGITAL OUTPUTS

Digital Output Format

PLLMULT[4:0] Pins

PLL Multiplication Factors (N)

0

8

The AD9267 digital bus outputs twos complement, single data

rate, LVDS data at 640 MSPS. The output is four bits wide per

channel.

1

9

2

10

3

12

The AD9267 supports both the ANSI-644 and a reduced power

data format similar to the IEEE1596.3 standard. The default

configuration at power-up is ANSI-644. This can be changed to

a low power reduced signal option by addressing Register

0x14[7], DRVSTD.

4

ꢀ

6

ꢁ

14

1ꢀ

16

1ꢁ

8

18

9

10

11

12

13

14

1ꢀ

16

20

21

24

2ꢀ

28

30

32

34

The LVDS driver current is derived on chip and sets the output

current at each output equal to a nominal 3.5 mA for the ANSI-

644 standard. A 100 Ω differential termination resistor placed at

the LVDS receiver inputs result in a nominal 350 mV swing at

the receiver. In the reduced power data format, the output swing

is limited to 200 mV and the resulting output current into the

100 Ω termination is 2 mA. As a result of the reduced LVDS

voltage swing, an additional 25% digital power savings can be

achieved over the ANSI-644 standard.

1ꢁ to 30

31

42

Direct clocking

The desired output format can be selected by addressing

Register 0x14[7], DRVSTD. The LVDSTERM bits, Register

0x15[5:4], provide either 100 Ω or 200 Ω, or no termination

at the output of the data bus. Selecting the appropriate termina-

tion resistor is important to allow maximum signal transfer and

to minimize reflections for signal integrity. This can be achieved

by selecting a termination resistor that impedance matches the

termination of the receiver.

POWER DISSIPATION AND STANDBY MODE

The AD9267 consumes 415 mW. This power consumption can

be further reduced by configuring the chip in channel power-

down, standby, or sleep mode. The low power modes turn off

internal blocks of the chip including the reference. As a result,

the wake-up time is dependent on the amount of circuitry that

is turned off. Fewer internal circuits powered down result in

proportionally shorter wake-up time. The different low power

modes are shown in Table 11. In the standby mode, all clock

related activity is disabled in addition to each channel; the

references and LVDS outputs remain powered up to ensure a

short recovery and link integrity, respectively. During sleep

mode, all internal circuits are powered down, putting the device

into its lowest power mode; the LVDS outputs are disabled.

Overrange (OR) Condition

An overrange condition can be triggered by large in-band signals

that exceed the full-scale range of the Σ-Δ modulator, or it

can be triggered by out-of-band signals gained by the transfer

characteristics of the modulator. Figure 43 shows the signal

transfer function of the Σ-Δ modulator. The modulator output

possesses out-of-band gain above 10 MHz. As a result, the input

signal may exceed full scale for input frequencies beyond 10 MHz

and the ADC may be in an overrange state. The OR x pins

serve as indicators for the overrange condition.

Each ADC channel can be independently powered down or

both channels can be set simultaneously by writing to the

channel index, Register 0x05[1:0]. Additionally, if the serial

port interface is not available, each channel can be indepen-

dently configured by tying the PDWNA (Pin 3) or PDWNB

(Pin 4) high.

The OR x pins are synchronous outputs that are updated at the

output data rate. The pins indicate whether an overrange condi-

tion has occurred within the AD9267. Ideally, OR x should be

latched on the falling edge of DCO to ensure proper setup-and-

hold time. However, because an overrange condition typically

extends well beyond one clock cycle (that is, does not toggle at

the DCO rate); data can usually be successfully detected on

the rising edge of DCO or monitored asynchronously. The

user has the ability to select how the overrange condition is

reported and this is controlled through the SPI bits (AUTORST,

OR_IND1, and OR_IND2) in Register 0x111[7:5]. The two

modes of operation are normal and data valid mode.

Table 11. Low Power Modes

Analog

Mode

0x08[1:0] Circuitry

Clock Ref.

Normal

Channel Power-Down

Standby

0x0

0x1

0x2

0x3

On

Off

On

Off

On

Off

Sleep

Rev. 0 | Page 1ꢁ of 24

AD9267

In normal operation mode, the analog input can toggle the

OR x pin for a number of clock cycles as it approaches full

scale. The OR x pin is a pulse-width modulated (PWM) signal;

therefore, as the analog input increases in amplitude, the

duration of OR x pin toggling increases. Eventually, when the

OR x pin is high for an extended period of time, the ADC

overloads; thus, there is little correspondence between analog

input and digital output. In this mode, the duration of the

OR x pin can be used as a coarse indicator to the signal

amplitude at the input of the ADC. In data valid mode, the

OR x pin remains high when there are no memory access

operations taking place, such as internal calibration or factory

memory transfer, and the inputs of the ADC are within the

operating range.

cycles where OR x remains high or if the loop filter becomes

saturated. The OR x pin remains high until the automatic reset

has completed.

If the AD9267 is used in a system that incorporates automatic

gain control (AGC), the OR x signals can be used to indicate

that the signal amplitude should be reduced. This may be

particularly effective for use in maximizing the signal dynamic

range if the signal includes high occurrence components that

occasionally exceed full scale by a small amount.

TIMING

The AD9267 provides latched data outputs with a latency of

seven clock cycles. The AD9267 also provides a data clock

output (DCO ) pin intended to assist in capturing the data in

an external register. The data outputs are valid on the rising

edge of DCO , unless changed by setting Serial Register 0x16[7]

(see the Serial Port Interface (SPI) section). See Figure 2 for a

graphical timing description.

In either modes of operation, the AUTORST bit can be enabled

and this automatically resets the modulator in an overload

condition. Because the OR x signal is a PWM signal and the

toggling of OR x does not always indicate an overload

condition, the modulator only resets after 16 consecutive clock

Table 12. OR x Conditions

Reset State

AUTORST

OR_IND1

OR_IND2

Function

Normal Reset Off

Data Valid Reset Off

Normal Reset On

Data Valid Reset On

0

1

0

1

0

1

0

1

0

1

If overrange: OR x = 1, else OR x = 0

If memory access: OR x = 0, else OR x = 1

If overrange or reset: OR x = 1, else OR x = 0

If memory access, or reset: OR x = 0, else OR x = 1

Rev. 0 | Page 18 of 24

AD9267

SERIAL PORT INTERFACE (SPI)

additional external timing. When CSB is tied high, SPI

functions are placed in a high impedance mode.

The AD9267 serial port interface (SPI) allows the user to

configure the converter for specific functions or operations

through a structured register space provided inside the ADC.

This provides the user added flexibility and customization

depending on the application. Addresses are accessed via the

serial port and can be written to or read from via the port.

Memory is organized into bytes that are further divided into

fields, as documented in the Memory Map section. For detailed

operational information, see the see the AN-877 Application

Note, Interfacing to High Speed ADCs via SPI.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase and the length is determined

by the W0 bit and the W1 bit. All data is composed of 8-bit words.

The first bit of each individual byte of serial data indicates whether

a read or write command is issued. This allows the serial data

input/output (SDIO) pin to change direction from an input to

an output.

In addition to word length, the instruction phase determines if

the serial frame is a read or write operation, allowing the serial

port to be used to both program the chip as well as to read the

contents of the on-chip memory. If the instruction is a readback

operation, performing a readback causes the serial data input/

output (SDIO) pin to change direction from an input to an

output at the appropriate point in the serial frame.

CONFIGURATION USING THE SPI

As summarized in Table 13, three pins define the SPI of this

ADC. The SCLK pin synchronizes the read and write data

presented to the ADC. The SDIO pin allows data to be sent and

read from the internal ADC memory map registers. The CSB

pin is an active low control that enables or disables the read and

write cycles.

Data can be sent in MSB- or in LSB-first mode. MSB first is

the default setting on power-up and can be changed via the

configuration register. For more information, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

Table 13. Serial Port Interface Pins

Function

SCLK

SCLK (serial clock) is the serial shift clock. SCLK

synchronizes serial interface reads and writes.

Table 14. SPI Timing Diagram Specifications

SDIO

CSB

SDIO (serial data input/output) is an input and output

depending on the instruction being sent and the

relative position in the timing frame.

CSB (chip select) is an active low control that gates the

read and write cycles.

Parameter Definition

t_SDS

t_SDH

t_SCLK

t_SS

Setup time between data and rising edge of SCLK

Hold time between data and rising edge of SCLK

Period of the clock

Setup time between CSB and SCLK

Hold time between CSB and SCLK

The falling edge of CSB in conjunction with the rising edge of

the SCLK determines the start of the framing. Figure 42 and

Table 14 provide an example of the serial timing and its

definitions.

t_SH

t_SHIGH

Minimum period that SCLK should be in a logic

high state

t_SLOW

Minimum period that SCLK should be in a logic

low state

Other modes involving CSB are available. CSB can be held low

indefinitely to permanently enable the device (this is called

streaming). CSB can stall high between bytes to allow for

t_SHIGH

t_SDS

t_SCLK

t_SH

t_SS

t_SDH

t_SLOW

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 42. Serial Port Interface Timing Diagram

Rev. 0 | Page 19 of 24

AD9267

The SPI interface is flexible enough to be controlled by either

PROM or PIC microcontrollers. This provides the user with the

ability to use an alternate method to program the ADC. One

such method is described in detail in the AN-812 Application

Note, MicroController-Based Serial Port Interface (SPI) Boot

Circuit.

HARDWARE INTERFACE

The pins described in Table 13 comprise the physical interface

between the programming device of the user and the serial port

of the AD9267. The SCLK and CSB pins function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

When the SPI interface is not used, SCLK/PLLMULT0 and

SDIO/PLLMULT1 serve a dual function. When strapped to

AVDD or ground during device power-on, the pins are

associated with a specific function.

Rev. 0 | Page 20 of 24

AD9267

APPLICATIONS INFORMATION

Figure 43 shows the gain profile of the AD9267 and this can be

interpreted as the level in which the signal power should be

scaled back to prevent an overload condition. This is the

ultimate trip point and before this point is reached, the in-band

noise (IBN) slowly degrades. As a result, it is recommended that

the low-pass filter be designed to match the profile of Figure 44,

which shows the maximum input signal for a 3 dB degradation

of in-band noise. The input signal is attenuated to allow only

3 dB of noise degradation over frequency.

FILTERING REQUIREMENT

The need for anti-alias protection often requires one or two

octaves for a transition band, which reduces the usable

bandwidth of a Nyquist converter to between 25% and 50% of

the available bandwidth. A CT Σ-Δ converter maximizes the

available signal bandwidth by forgoing the need for an

antialiasing filter because the architecture possesses inherent

antialiasing. Although a high order, sharp cutoff antialiasing

filter may not be necessary because of the unique characteristics

of the architecture, a low order filter may still be required to

precede the ADC for out-of-band signal handling.

The noise performance is normalized to a −2 dBFS in-band

signal. The AD9267 STF and NTF are flat within the band of

interest and should result in almost no change in input level and

IBN. Beyond the bandwidth of the AD9267, out-of-band

peaking adds gain to the system, therefore requiring the input

power to be scaled back to prevent in-band noise degradation.

The input power is scaled back to a point where only 3 dB of

noise degradation is allowed, therefore resulting in Figure 44.

5

Depending on the application and the system architecture, this

low order filter may or may not be necessary. The signal

transfer function (STF) of a continuous time feedforward ADC

usually contains out-of-band peaks. Because these STF peaks

are typically one or two octaves above the pass-band edge, they

are not problematic in applications where the bulk of the signal

energy is in or near the pass band. However, in applications

with large far-out interferers, it is necessary to either add a filter

to attenuate these problematic signals or to allocate some of the

ADC dynamic range to accommodate them.

0

–5

–40°C

Figure 43 shows the normalized STF of the AD9267 CT Σ-Δ

converter. The figure shows out-of-band peaking beyond the

band edge of the ADC. Within the 10 MHz band of interest, the

STF is maximally flat with less than 0.1 dB of gain. Maximum

peaking occurs at 60 MHz with 10 dB of gain. To put this into

perspective, for a fixed input power, a 5 MHz in-band-signal

appears at −5 dBFS, a 25 MHz tone appears at −2 dBFS and

60 MHz tone at +5 dBFS. Because the maximum input to the

ADC is −2 dBFS, large out-of-band signals can quickly saturate

the system. This implies that under these conditions, the digital

outputs of the ADC no longer accurately represents the input.

Refer to the Overrange (OR) Condition section for details on

overrange detection and recovery.

–10

CHEBYSHEV II

FILTER RESPONSE

–15

+85°C

+25°C

–20

–25

0

10

20

30

40

50

60

70

80

90

100

FREQUENCY (MHz)

Figure 44. Maximum Input Level for 3 dB Noise Degradation

An example third-order low-pass Chebyshev II type filter is

shown in Figure 45 and the corresponding magnitude vs.

frequency response of the filter is shown in Figure 44.

15

L1

180nH

13

11

9

VIN+

C2

390pF

C1

39pF

C3

220pF

AD9267

1kΩ

7

CT Σ-Δ

L1

180nH

5

VIN–

3

1

C2

390pF

–1

–3

–5

Figure 45. Third-Order Low-Pass Chebyshev II Filter

0

10

20

30

40

50

60

70

80

90

100

FREQUENCY (MHz)

Figure 43. STF

Rev. 0 | Page 21 of 24

AD9267

0

–2

40

Referring to Figure 46, the 3 dB cutoff frequency of the low-

pass Chebyshev II filter response resides at 15.75 MHz, and at

10 MHz, there is 0.43 dB of attenuation due to the sharp roll-off

of the filter. Table 15 summarizes the components and

manufacturers used to build the circuit.

30

–4

20

–6

10

–8

0

–10

–12

–14

–16

–18

–20

–10

–20

–30

–40

–50

–60

Table 15. Chebyshev II Filter Components

Parameter

Value

Unit

Manufacturer

C1

L1

C2

C3

39

pF

nH

pF

Murata GRM188 series, 0603

Coil Craft 0402AF, 2%

Murata GRM188 series, 0603

180

390

220

pF

0

2

4

6

8

10

12

14

16

18

20

FREQUENCY (MHz)

Figure 46. Low-Pass Chebyshev II Filter Response

In addition to matching the profile of Figure 44, group delay

and channel matching are important filter design criteria. Low

tolerance components are highly recommended for improved

channel matching, which translates to minimal degradation in

image rejection for quadrature systems.

Rev. 0 | Page 22 of 24

AD9267

MEMORY MAP

Table 16. Memory Map

Register

Address (Hex)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPI Port Config

Chip ID

00

01

02

0ꢀ

08

09

0A

14

1ꢀ

16

18

111

0

LSBFIRST

SOFTRESET

1

SOFTRESET LSBFIRST

0

CHIPID[ꢁ:0]

CHILDID[1:0]

Chip Grade

Channel Index

Power Modes

PLLENABLE

PLL

Channel[1:0]

PWRDWN[1:0]

PLLENABLE

PLLMULT[ꢀ:0]

PLLLOCKED PLLAUTO

DRVSTD

Output Modes

Output Adjust

Output Clock

Reference

OUTENB

LVDSTERM[1:0]

DCOINV

EXTREF

Overrange

AUTORST

OR_IND1

OR_IND2

MEMORY MAP DEFINITIONS

Table 17. Memory Map Definitions

Register

Address

Bit Name

Bit(s)

Default

Description

SPI Port Config

0x00

LSBFIRST

[6], [1]

0

0: serial interface uses MSB-first format

1: serial interface uses LSB-first format

SOFTRESET

CHIPID

[ꢀ], [2]

[ꢁ:0]

ꢀ:4]

0

1: default all serial registers except 0x00, 0x09, and 0x0A

0x22: AD926ꢁ

Chip ID

0x01

0x02

0x22

0

Chip Grade

CHILDID

0x00: 10 MHz bandwidth

0x10: ꢀ MHz bandwidth

0x20: 2.ꢀ MHz bandwidth

0x30: modulator only

Channel Index

Power Modes

0x0ꢀ

0x08

Channel

[1:0]

0

0x1: Channel A only addressed

0x2: Channel B only addressed

0x3: both channels addressed simultaneously

PWRDWN

0x0: normal operation

0x1: channel power-down (local)

0x2: standby (everything except reference circuits)

0x3: sleep

PLLENABLE

PLL

0x09

0x0A

PLLENABLE

PLLLOCKED

[2]

[ꢁ]

0

1: enable PLL

0: PLL is not locked

1: PLL is locked

PLLAUTO

[6]

0

0: disable PLL auto band select

1: enable PLL auto band select

PLLMULT

DRVSTD

[ꢀ:0]

[ꢁ]

0

See Table 8

Output Modes

Output Adjust

0x14

0x1ꢀ

0: ANSI-644

1: Low power (IEEE1ꢀ96.3 similar)

OUTENB

[4]

0

1: Channel A and Channel B outputs tristated

LVDSTERM

[ꢀ:4]

0: no termination

1: 200 Ω

2: 100 Ω

3: 100 Ω

Output Clock

Reference

0x16

0x18

0x111

DCOINV

EXTREF

[ꢁ]

[6]

[ꢁ]

[6]

[ꢀ]

0

1: invert DCO

1: use external reference

1: enable autoreset

See Table 12

Overrange

AUTORST

OR_IND1

OR_IND2

See Table 12

Rev. 0 | Page 23 of 24

AD9267

OUTLINE DIMENSIONS

0.60 MAX

9.00

BSC SQ

0.60

MAX

PIN 1

INDICATOR

64

49

1

48

PIN 1

INDICATOR

0.50

BSC

6.35

6.20 SQ

6.05

8.75

BSC SQ

TOP VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.50

0.40

0.30

33

32

16

17

0.25 MIN

7.50

REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

0.30

0.23

0.18

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 47. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD926ꢁBCPZ¹

AD926ꢁEBZ¹

−40°C to +8ꢀ°C

64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

Evaluation Board

CP-64-4

¹Z = RoHs Compliant Part.

registered trademarks are the property of their respective owners.

D07773-0-7/09(0)

Rev. 0 | Page 24 of 24


型号：	AD9267BCPZ
厂家：	ADI
描述：	10 MHz Bandwidth, 640 MSPS Dual Continuous Time Sigma-Delta Modulator 10 MHz带宽， 640 MSPS双通道连续时间Σ -Δ调制器
文件：	总24页 (文件大小：524K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9267BCPZ [ADI]

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