AD9273BSVZ-40_技术文档

Octal LNA/VGA/AAF/ADC

and Crosspoint Switch

AD9273

FUNCTIONAL BLOCK DIAGRAM

FEATURES

8 channels of LNA, VGA, AAF, and ADC

Low noise preamplifier (LNA)

Input-referred noise voltage = 1.26 nV/√Hz

(gain = 21.3 dB) @ 5 MHz typical

LOSW-A

LO-A

AD9273

SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB

Single-ended input; V_INmaximum = 733 mV p-p/

550 mV p-p/367 mV p-p

Dual-mode active input impedance matching

Bandwidth (BW) > 100 MHz

Full-scale (FS) output = 4.4 V p-p differential

Variable gain amplifier (VGA)

Attenuator range = −42 dB to 0 dB

SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB

Linear-in-dB gain control

Antialiasing filter (AAF)

Programmable 2nd-order low-pass filter (LPF) from

8 MHz to 18 MHz

Programmable high-pass filter (HPF)

Analog-to-digital converter (ADC)

12 bits at 10 MSPS to 50 MSPS

LI-A

12-BIT

ADC

DOUTA+

DOUTA–

SERIAL

LVDS

LNA

VGA

LG-A

AAF

LOSW-B

LO-B

LI-B

12-BIT

ADC

DOUTB+

DOUTB–

SERIAL

LVDS

LG-B

LOSW-C

LO-C

LI-C

12-BIT

ADC

DOUTC+

DOUTC–

SERIAL

LVDS

VGA

LG-C

LOSW-D

LO-D

LI-D

12-BIT

ADC

DOUTD+

DOUTD–

SERIAL

LVDS

LG-D

LOSW-E

LO-E

LI-E

DOUTE+

DOUTE–

12-BIT

ADC

SERIAL

LVDS

VGA

LG-E

LOSW-F

LO-F

LI-F

DOUTF+

DOUTF–

SNR = 70 dB

SFDR = 75 dB

12-BIT

ADC

SERIAL

LVDS

VGA

LG-F

LOSW-G

LO-G

Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)

Data and frame clock outputs

Includes an 8 × 8 differential crosspoint switch to support

continuous wave (CW) Doppler

Low power, 109 mW per channel at 12 bits/40 MSPS (TGC)

70 mW per channel in CW Doppler

Flexible power-down modes

LI-G

DOUTG+

DOUTG–

12-BIT

ADC

SERIAL

LVDS

LG-G

LOSW-H

LO-H

LI-H

12-BIT

ADC

DOUTH+

DOUTH–

SERIAL

LVDS

VGA

LG-H

Overload recovery in <10 ns

Fast recovery from low power standby mode, <2 μs

100-lead TQFP and 144-ball BGA

FCO+

FCO–

DCO+

DCO–

REFERENCE

SWITCH

ARRAY

APPLICATIONS

Medical imaging/ultrasound

Automotive radar

GENERAL DESCRIPTION

Figure 1.

The AD9273 is designed for low cost, low power, small size, and

ease of use. It contains eight channels of a low noise preamplifier

(LNA) with a variable gain amplifier (VGA); an antialiasing

filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to-

digital converter (ADC).

The LNA has a single-ended-to-differential gain that is selectable

through the SPI. The LNA input-referred noise voltage is typically

1.26 nV/√Hz at a gain of 21.3 dB, and the combined input-referred

noise voltage of the entire channel is 1.42 nV/√Hz at typical

gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB

LNA gain, the input SNR is about 91 dB. In CW Doppler mode,

the LNA output drives a transconductance amp that is switched

through an 8 × 8 differential crosspoint switch. The switch is

programmable through the SPI.

Each channel features a variable gain range of 42 dB, a fully

differential signal path, an active input preamplifier termination, a

maximum gain of up to 52 dB, and an ADC with a conversion

rate of up to 50 MSPS. The channel is optimized for dynamic

performance and low power in applications where a small

package size is critical.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9273* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

REFERENCE MATERIALS

Press

• Industry’s First Octal Ultrasound Receiver with Digital I/Q

Demodulator and Decimation Filter Reduces Processor

Overhead in Ultrasound Systems

EVALUATION KITS

• AD9273 Evaluation Board

• Low Cost, Octal Ultrasound Receiver with On-Chip RF

Decimator and JESD204B Serial Interface

DOCUMENTATION

Application Notes

Technical Articles

• MS-2210: Designing Power Supplies for High Speed ADC

• AN-1142: Techniques for High Speed ADC PCB Layout

• AN-586: LVDS Outputs for High Speed A/D Converters

• AN-737: How ADIsimADC Models an ADC

• New Components Offer Fexibility in Ultrasound System

Design

• Processors for Ultrasound Improve Image Quality

• AN-812: MicroController-Based Serial Port Interface (SPI)

Boot Circuit

DESIGN RESOURCES

• AD9273 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

• AN-835: Understanding High Speed ADC Testing and

Evaluation

• AN-877: Interfacing to High Speed ADCs via SPI

• AN-878: High Speed ADC SPI Control Software

• AN-905: Visual Analog Converter Evaluation Tool Version

1.0 User Manual

DISCUSSIONS

• AN-935: Designing an ADC Transformer-Coupled Front

End

View all AD9273 EngineerZone Discussions.

Data Sheet

SAMPLE AND BUY

• AD9273: Octal LNA/VGA/AAF/ADC and Crosspoint Switch

Data Sheet

Visit the product page to see pricing options.

SOFTWARE AND SYSTEMS REQUIREMENTS

TECHNICAL SUPPORT

• UG-001: Evaluation Board User Guide

Submit a technical question or find your regional support

number.

TOOLS AND SIMULATIONS

• Visual Analog

DOCUMENT FEEDBACK

Submit feedback for this data sheet.

• AD9273 IBIS Models

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AD9273

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 21

Ultrasound .................................................................................. 21

Channel Overview ..................................................................... 22

Input Overdrive .......................................................................... 25

CW Doppler Operation............................................................. 25

TGC Operation........................................................................... 27

ADC ............................................................................................. 31

Clock Input Considerations...................................................... 31

Serial Port Interface (SPI).............................................................. 38

Hardware Interface..................................................................... 38

Memory Map .................................................................................. 40

Reading the Memory Map Table.............................................. 40

Reserved Locations .................................................................... 40

Default Values............................................................................. 40

Logic Levels................................................................................. 40

Outline Dimensions....................................................................... 44

Ordering Guide .......................................................................... 45

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Product Highlights ........................................................................... 3

Specifications..................................................................................... 4

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 8

Switching Specifications .............................................................. 9

ADC Timing Diagrams ................................................................. 10

Absolute Maximum Ratings.......................................................... 11

Thermal Impedance................................................................... 11

ESD Caution................................................................................ 11

Pin Configuration and Function Descriptions........................... 12

Typical Performance Characteristics ........................................... 15

Equivalent Circuits......................................................................... 19

REVISION HISTORY

7/09—Rev. A to Rev. B

Changes to Ultrasound Section.................................................... 21

Changes to Low Noise Amplifier (LNA) Section....................... 22

Changes to Active Impedance Matching Section and

Figure 40...................................................................................... 23

Changes to LNA Noise Section .................................................... 24

Changes to Input Overload Protection Section and Figure 44 .......25

Changes to Figure 48...................................................................... 28

Changes to Figure 49 and Figure 50............................................. 29

Changes to Clock Input Considerations Section and to

Figure 56 to Figure 59................................................................ 31

Changes to Digital Outputs and Timing Section....................... 33

Changes to CSB Pin Section ......................................................... 36

Changes to Reading the Memory Map Table Section ............... 40

Updated Outline Dimensions....................................................... 44

Changes to Ordering Guide.......................................................... 45

Added BGA Package ..........................................................Universal

Changes to Features and General Description Sections.............. 1

Changes to Product Highlights Section......................................... 3

Changes to Full-Channel (TGC) Characteristics Parameter,

Table 1 ............................................................................................ 4

Changes to Gain Control Interface Parameter and to CW

Doppler Mode Parameter, Table 1.............................................. 6

Change to Wake-Up Time (Standby), GAIN+ = 0.8 V

Parameter....................................................................................... 9

Changes to Figure 2 and Figure 3................................................. 10

Changes to Table 4.......................................................................... 11

Addded Figure 5; Renumbered Sequentially .............................. 12

Changes to Table 6.......................................................................... 13

Changes to Figure 34 and Figure 35............................................. 20

4/09—Revision A: Initial Version

Rev. B | Page 2 of 48

AD9273

The AD9273 requires a LVPECL-/CMOS-/LVDS-compatible

sample rate clock for full performance operation. No external

reference or driver components are required for many

applications.

Fabricated in an advanced CMOS process, the AD9273 is

available in a 16 mm × 16 mm, RoHS compliant, 100-lead

TQFP or a 144-ball BGA. It is specified over the industrial

temperature range of −40°C to +85°C.

The ADC automatically multiplies the sample rate clock for

the appropriate LVDS serial data rate. A data clock (DCO ) for

capturing data on the output and a frame clock (FCO ) trigger

for signaling a new output byte are provided.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight channels are contained in a small,

space-saving package. A full TGC path, ADC, and crosspoint

switch contained within a 100-lead, 16 mm × 16 mm TQFP or

a 144-ball BGA.

2. Low Power of 109 mW per Channel at 40 MSPS.

3. Integrated Crosspoint Switch. This switch allows numerous

multichannel configuration options to enable the CW

Doppler mode.

4. Ease of Use. A data clock output (DCO ) operates up to

300 MHz and supports double data rate (DDR) operation.

5. User Flexibility. Serial port interface (SPI) control offers a wide

range of flexible features to meet specific system requirements.

6. Integrated Second-Order Antialiasing Filter. This filter is

placed between the VGA and the ADC and is programmable

from 8 MHz to 18 MHz.

Powering down individual channels is supported to increase

battery life for portable applications. There is also a standby

mode option that allows quick power-up for power cycling. In

CW Doppler operation, the VGA, AAF, and ADC are powered

down. The power of the time gain control (TGC) path scales

with selectable speed grades.

The ADC contains several features designed to maximize flexibility

and minimize system cost, such as a programmable clock, data

alignment, and programmable digital test pattern generation. The

digital test patterns include built-in fixed patterns, built-in

pseudorandom patterns, and custom user-defined test patterns

entered via the serial port interface.

Rev. B | Page 3 of 48

AD9273

SPECIFICATIONS

AC SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f_IN= 5 MHz, R_S= 50 Ω, LNA gain = 21.3 dB, LNA bias =mid-

high (default), PGA gain = 24 dB, GAIN− = 0.8 V, AAF LPF cutoff = f_SAMPLE/3 (default), HPF = LPF cutoff/20.7 (default), full temperature,

ANSI-644 LVDS mode, unless otherwise noted.

Table 1.

AD9273-25

Typ

AD9273-40

Typ

AD9273-50

Typ

Parameter¹

LNA CHARACTERISTICS

Gain

Conditions

Min

Max Min

Max

Unit

Single-ended

input to

differential

output

15.6/17.9/21.3

9.6/11.9/15.3

733/550/367

15.6/17.9/21.3

9.6/11.9/15.3

733/550/367

15.6/17.9/21.3

9.6/11.9/15.3

733/550/367

dB

Single-ended

input to

single-ended

output

dB

Input Voltage Range LNA gain =

mV p-p

SE²

15.6 dB/

17.9 dB/

21.3 dB,

LNA output

limited to

4.4 V p-p

differential

output

Input Common

Mode

0.9

V

Input Resistance

R_FB= 250 Ω

R_FB= 500 Ω

R_FB= ∞

50

Ω

100

Ω

15

kΩ

Input Capacitance

−3 dB Bandwidth

LI-x

22

pF

70

MHz

nV/√Hz

Input-Referred

Noise Voltage

LNA gain =

15.6 dB/

17.9 dB/

21.3 dB,

1.6/1.42/1.26

R_S= 0 Ω,

R

_FB= ∞

Input Noise Current

R_FB= ∞

1

pA/√Hz

mV p-p

1 dB Input Com-

pression Point

LNA gain =

15.6 dB/

1.0/0.8/0.5

17.9 dB/

21.3 dB,

GAIN+ = 0 V

Noise Figure

LNA gain =

15.6 dB/

17.9 dB/

21.3 dB

Active Termina-

tion Matched

R_S= 50 Ω,

R_FB= 200 Ω/

250 Ω/350 Ω

5.8/5.1/4.3

6.3/5.3/4.4

5.8/5.1/4.3

6.3/5.3/4.4

5.8/5.1/4.3

6.3/5.3/4.4

dB

Unterminated

R_FB= ∞

FULL-CHANNEL (TGC)

CHARACTERISTICS

AAF Low-Pass Filter

Cutoff

In range, −3 dB,

programmable

Out of range,³

−3 dB, pro-

8 to 18

MHz

5 to 8, 18 to 35

grammable,

>>AAF band-

width tolerance

Rev. B | Page 4 of 48

AD9273

AD9273-25

Typ

AD9273-40

Typ

AD9273-50

Typ

Parameter¹

Conditions

Min

Max Min

Max

Unit

AAF Bandwidth

Tolerance

In range

10

%

Group Delay

Variation

f = 1 MHz to

18 MHz,

2

ns

GAIN+ = 0 V to

1.6 V

Input-Referred

Noise Voltage

LNA gain =

15.6 dB/

17.9 dB/

21.3 dB,

1.94/1.64/1.38

nV/√Hz

R

_FB= ∞

Noise Figure

LNA gain =

15.6 dB/

17.9 dB/

21.3 dB

Active Termina-

tion Matched

R_S= 50 Ω,

10.3/8.7/6.8

10.3/8.6/6.7

dB

R_FB= 200 Ω/

250 Ω/350 Ω

Unterminated

R_FB= ∞

7.1/6.0/4.8

−30

7.1/5.9/4.8

−30

7.1/5.9/4.8

−30

dB

Correlated Noise

Ratio

No signal,

correlated/

uncorrelated

Output Offset

−35

+35

−35

+35

−35

+35

LSB

Signal-to-Noise

Ratio (SNR)

f_IN= 5 MHz at

−10 dBFS,

GAIN+ = 0 V

65.5

58.5

64

57

63.5

56.5

dBFS

f_IN= 5 MHz at

−1 dBFS,

dBFS

GAIN+ = 1.6 V

Harmonic Distortion

Second

Harmonic

f_IN= 5 MHz at

−10 dBFS,

GAIN+ = 0 V

−55

−67

−56

−61

−75

−52

−62

−50

−56

−75

−52

−58

−47

−55

−75

dBc

f_IN= 5 MHz at

−1 dBFS,

GAIN+ = 1.6 V

Third Harmonic

f_IN= 5 MHz at

−10 dBFS,

GAIN+ = 0 V

f_IN= 5 MHz at

−1 dBFS,

GAIN+ = 1.6 V

Two-Tone IMD3

(2 × F1 − F2)

Distortion

f_IN1= 5.0 MHz at

−1 dBFS,

f_IN2= 5.01 MHz

at −21 dBFS,

GAIN+ = 1.6 V,

LNA gain =

21.3 dB

Channel-to-Channel f_IN1= 5.0 MHz at

−70

−65

0.3

−70

−65

0.3

−70

−65

0.3

dB

Crosstalk

−1 dBFS

Overrange

condition⁴

dB

Channel-to-Channel

Delay Variation

Full TGC path,

f_IN= 5 MHz,

GAIN+ = 0 V to

1.6 V

Degrees

PGA GAIN

Differential

input to

21/24/27/30

dB

differential

output

Rev. B | Page 5 of 48

AD9273

AD9273-25

Typ

AD9273-40

Typ

AD9273-50

Typ

Parameter¹

Conditions

Min

Max Min

Max

Unit

GAIN ACCURACY

25°C

Gain Law Confor-

mance Error

0 V < GAIN+

< 0.16 V

1.5

dB

0.16 V < GAIN+

< 1.44 V

−1.6

+1.6

−1.6

+1.6

−1.7

+1.7

1.44 V < GAIN+

< 1.6 V

−2.5

Linear Gain Error

GAIN+ = 0.8 V,

normalized for

ideal AAF loss

Channel-to-Channel 0.16 V < GAIN+

0.1

dB

Matching

< 1.44 V

GAIN CONTROL

INTERFACE

Normal Operating

Range

0

1.6

0

1.6

0

1.6

V

Gain Range

GAIN+ =

0 V to 1.6 V

42

dB

Scale Factor

28

dB/V

ns

Response Time

42 dB change

Single ended

750

10

750

10

750

10

Gain+ Impedance

Gain− Impedance

CW DOPPLER MODE

Transconductance

MΩ

kΩ

70

Differential,

LNA gain =

15.6 dB/

5.4/7.3/10.9

mA/V

17.9 dB/

21.3 dB

Output Level Range

Differential,

CW Doppler

output pins

1.5

3.6

1.5

3.6

1.5

3.6

V

Input-Referred

Noise Voltage

LNA gain =

15.6 dB/

17.9 dB/

21.3 dB,

2.6/2.1/1.6

nV/√Hz

R_S= 0 Ω,

R

_FB= ∞,

R_L= 675 Ω

Input-Referred

Dynamic Range

LNA gain =

15.6 dB/

17.9 dB/

21.3 dB,

R_S= 0 Ω,

R_FB= ∞

160/159/158

dBFS/√Hz

Two-Tone IMD3

(2 × F1 − F2)

Distortion

f_IN1= 5.0 MHz at

−1 dBFS (FS at

−70

dBc

LNA input), f_IN2

5.01 MHz at

=

−21 dBFS (FS at

LNA input), LNA

gain = 21.3 dB

Output DC Bias

Single ended,

per channel

2.4

2

2.4

2

2.4

2

mA

Maximum Output

Swing

Single ended,

per channel

mA p-p

POWER SUPPLY

AVDD1

1.7

2.7

1.7

1.8

3.0

1.8

158

1.9

3.6

1.9

1.7

2.7

1.7

1.8

3.0

1.8

186

1.9

3.6

1.9

1.7

2.7

1.7

1.8

3.0

1.8

223

1.9

3.6

1.9

V

AVDD2

V

DRVDD

V

I_AVDD1

Full-channel

mode

mA

CW Doppler

mode with four

channels

32

mA

enabled

Rev. B | Page 6 of 48

AD9273

AD9273-25

Typ

AD9273-40

Typ

AD9273-50

Typ

Parameter¹

Conditions

Min

Max Min

Max

Unit

I_AVDD2

Full-channel

mode

150

mA

CW Doppler

mode with four

channels

70

mA

enabled

I_DRVDD

47

49

50

mA

Total Power

Dissipation

Includes output

drivers, full-

channel mode,

no signal

819

940

873

996

943

1072 mW

mW

CW Doppler

mode with four

channels

275

enabled

Power-Down

Dissipation

5

mW

Standby Power

Dissipation

148

158

170

mW

Power Supply

Rejection Ratio

(PSRR)

1.6

12

1.6

12

1.6

12

mV/V

ADC RESOLUTION

ADC REFERENCE

Bits

Output Voltage Error VREF = 1 V

20

mV

Load Regulation

At 1.0 mA,

VREF = 1 V

2

6

2

6

2

6

Input Resistance

kΩ

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

²SE = single ended.

³AAF settings < 5 MHz are out of range and are not supported.

⁴The overrange condition is specified as being 6 dB more than the full-scale input range.

Rev. B | Page 7 of 48

AD9273

DIGITAL SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f_IN= 5 MHz, full temperature, unless otherwise noted.

Table 2.

Parameter¹

Temperature

Min

Typ

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage²

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

Full

25°C

250

mV p-p

V

kΩ

pF

1.2

20

1.5

LOGIC INPUTS (PDWN, STBY, SCLK)

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

Input Capacitance

Full

25°C

1.2

3.6

0.3

V

kΩ

pF

30

0.5

LOGIC INPUT (CSB)

Logic 1 Voltage

Logic 0 Voltage

Full

3.6

0.3

V

Input Resistance

Input Capacitance

25°C

70

0.5

kΩ

pF

LOGIC INPUT (SDIO)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

0

DRVDD + 0.3

0.3

V

Input Resistance

Input Capacitance

25°C

30

2

kΩ

pF

LOGIC OUTPUT (SDIO)³

Logic 1 Voltage (I_OH= 800 μA)

Logic 0 Voltage (I_OL= 50 μA)

DIGITAL OUTPUTS (DOUTx+, DOUTx−) IN ANSI-644 MODE¹

Logic Compliance

Full

1.79

V

0.05

LVDS

Differential Output Voltage (V_OD)

Output Offset Voltage (V_OS)

Output Coding (Default)

Full

247

1.125

454

1.375

mV

V

Offset binary

LVDS

DIGITAL OUTPUTS (DOUTx+, DOUTx−) WITH

LOW POWER, REDUCED-SIGNAL OPTION¹

Logic Compliance

Differential Output Voltage (V_OD)

Output Offset Voltage (V_OS)

Output Coding (Default)

Full

150

1.10

250

1.30

mV

V

Offset binary

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

²Specified for LVDS and LVPECL only.

³Specified for 13 SDIO pins sharing the same connection.

Rev. B | Page 8 of 48

AD9273

SWITCHING SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f_IN= 5 MHz, full temperature, unless otherwise noted.

Table 3.

Parameter¹

CLOCK²

Temp

Min

Typ

Max

Unit

Clock Rate

Full

10

50

MSPS

ns

Clock Pulse Width High (t_EH)

Clock Pulse Width Low (t_EL)

OUTPUT PARAMETERS^{2, 3}

Propagation Delay (t_PD)

Rise Time (t_R) (20% to 80%)

Fall Time (t_F) (20% to 80%)

FCO Propagation Delay (t_FCO

DCO Propagation Delay (t_CPD

DCO to Data Delay (t_DATA

DCO to FCO Delay (t_FRAME

Data-to-Data Skew

10

Full

(t_SAMPLE/2) + 1.5

(t_SAMPLE/2) + 2.3

300

(t_SAMPLE/2) + 3.1

ns

ps

ns

ps

300

)

(t_SAMPLE/2) + 2.3

t_FCO+ (t_SAMPLE/24)

(t_SAMPLE/24)

100

4

)

(t_SAMPLE/24) − 300

(t_SAMPLE/24) + 300

350

4

)

(t_DATA-MAX− t_DATA-MIN

)

<2

1

Wake-Up Time (Standby), GAIN+ = 0.8 V

Wake-Up Time (Power-Down)

Pipeline Latency

25°C

Full

ꢀs

ms

Clock cycles

8

APERTURE

<1

Aperture Uncertainty (Jitter)

25°C

ps rms

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

²Can be adjusted via the SPI.

³Measurements were made using a part soldered to FR-4 material.

⁴t_SAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.

Rev. B | Page 9 of 48

AD9273

ADC TIMING DIAGRAMS

N – 1

AIN

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

t_PD

t_DATA

DOUTx–

MSB

N – 8

D10

N – 8

D9

N – 8

D8

N – 8

D7

N – 8

D6

N – 8

D5

N – 8

D4

N – 8

D3

N – 8

D2

N – 8

D1

N – 8

D0

N – 8

MSB

N – 7

D10

N – 7

DOUTx+

Figure 2. 12-Bit Data Serial Stream (Default)

N – 1

AIN

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

t_PD

t_DATA

DOUTx–

DOUTx+

D0

(LSB)

D1

N – 8

D2

N – 8

D3

N – 8

D4

N – 8

D5

N – 8

D6

N – 8

D7

N – 8

D8

N – 8

D9

N – 8

D10

N – 8

D11

(MSB)

Figure 3. 12-Bit Data Serial Stream, LSB First

Rev. B | Page 10 of 48

AD9273

ABSOLUTE MAXIMUM RATINGS

Table 4.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

With

Respect To

Parameter

Electrical

AVDD1

AVDD2

DRVDD

GND

AVDD2

AVDD1

Digital Outputs

(DOUTx+, DOUTx−,

DCO+, DCO−,

FCO+, FCO−)

CLK+, CLK−, GAIN+,

GAIN−

LI-x, LO-x, LOSW-x

CWDx−, CWDx+

PDWN, STBY, SCLK, CSB

RBIAS, VREF, SDIO

Environmental

Rating

GND

AVDD1

DRVDD

GND

−0.3 V to +2.0 V

−0.3 V to +3.9 V

−0.3 V to +2.0 V

−0.3 V to +0.3 V

−2.0 V to +3.9 V

−2.0 V to +2.0 V

−0.3 V to +2.0 V

THERMAL IMPEDANCE

Table 5.

Airflow Velocity (m/sec)

1

θ_JA

θ_JB

N/A N/A °C/W

7.6 4.7 °C/W

N/A N/A °C/W

θ_JC

Unit

0.0

1.0

2.5

20.3

14.4

12.9

GND

−0.3 V to +3.9 V

¹θ_JAis for a 4-layer PCB with a solid ground plane (simulated). The exposed

pad is soldered to the PCB.

LG-x

GND

−0.3 V to +2.0 V

−0.3 V to +3.9 V

−0.3 V to +2.0 V

ESD CAUTION

Operating Temperature

Range (Ambient)

Storage Temperature

Range (Ambient)

Maximum Junction

Temperature

−40°C to +85°C

−65°C to +150°C

150°C

Lead Temperature

(Soldering, 10 sec)

300°C

Rev. B | Page 11 of 48

AD9273

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

LI-E

LG-E

1

2

75 LI-D

74 LG-D

AVDD2

AVDD1

LO-F

3

AVDD2

73

72

71

70

AVDD1

LO-C

4

EXPOSED PADDLE, PIN 0

(BOTTOM OF PACKAGE)

5

LOSW-F

LI-F

6

LOSW-C

7

69 LI-C

AD9273

TOP VIEW

(Not to Scale)

LG-F

8

68 LG-C

67 AVDD2

AVDD2

AVDD1

LO-G

9

AVDD1

LO-B

10

11

66

65

LOSW-G 12

LI-G 13

64 LOSW-B

63 LI-B

LG-G 14

62 LG-B

AVDD2

AVDD1

LO-H

AVDD2

AVDD1

LO-A

15

16

17

61

60

59

LOSW-H 18

LI-H 19

58 LOSW-A

57 LI-A

LG-H 20

56 LG-A

21

22

23

AVDD2

AVDD1

CLK–

AVDD2

AVDD1

CSB

55

54

53

CLK+ 24

52 SDIO

51 SCLK

AVDD1 25

NOTES

1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND.

Figure 4. TQFP Pin Configuration

4

6

8

10

12

2

1

3

5

7

9

11

A

B

C

D

E

F

G

H

J

K

L

M

TOP VIEW

(Not to Scale)

Figure 5. BGA Pin Configuration

Rev. B | Page 12 of 48

AD9273

Table 6. Pin Function Descriptions

Pin No.

TQFP

0

N/A

BGA

Name

GND

Description

N/A

Ground (the exposed paddle should be tied to a quiet analog ground)

Ground

B5, B6, B8, C5,

C6, C7, C8, D5,

D6, D7, D8, E1,

E5, E6, E7, E8,

E12, F2, F4, F6,

F7, F9, F11, G1,

G3, G5, G6, G7,

G8, G10, G12,

H2, H3, H4, H5,

H6, H7, H8, H9,

H10, H11, J2,

K1, K2, M1, M12

4, 10, 16, 22,

25, 50, 54, 60,

66, 72

3, 9, 15, 21, 55,

61, 67, 73, 86

F1, F3, F5, F8,

F10, F12, G2,

G4, G9, G11

B7, E2, E3, E4,

E9, E10, E11

AVDD1

AVDD2

1.8 V Analog Supply

3.0 V Analog Supply

26, 47

1

2

L1, L12

A1

B1

DRVDD

LI-E

LG-E

1.8 V Digital Output Driver Supply

LNA Analog Input for Channel E

LNA Ground for Channel E

5

6

7

8

C2

LO-F

LOSW-F

LI-F

LNA Analog Inverted Output for Channel F

LNA Analog Switched Output for Channel F

LNA Analog Input for Channel F

LNA Ground for Channel F

D2

A2

B2

LG-F

11

12

13

14

17

18

19

20

23

24

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

C3

LO-G

LOSW-G

LI-G

LG-G

LO-H

LOSW-H

LI-H

LG-H

CLK−

CLK+

DOUTH−

DOUTH+

DOUTG−

DOUTG+

DOUTF−

DOUTF+

DOUTE−

DOUTE+

DCO−

DCO+

FCO−

FCO+

DOUTD−

DOUTD+

DOUTC−

DOUTC+

DOUTB−

DOUTB+

LNA Analog Inverted Output for Channel G

LNA Analog Switched Output for Channel G

LNA Analog Input for Channel G

LNA Ground for Channel G

LNA Analog Inverted Output for Channel H

LNA Analog Switched Output for Channel H

LNA Analog Input for Channel H

LNA Ground for Channel H

Clock Input Complement

Clock Input True

ADC H Digital Output Complement

ADC H Digital Output True

ADC G Digital Output Complement

ADC G Digital Output True

ADC F Digital Output Complement

ADC F Digital Output True

ADC E Digital Output Complement

ADC E Digital Output True

Digital Clock Output Complement

Digital Clock Output True

Frame Clock Digital Output Complement

Frame Clock Digital Output True

ADC D Digital Output Complement

ADC D Digital Output True

D3

A3

B3

C4

D4

A4

B4

H1

J1

M2

L2

M3

L3

M4

L4

M5

L5

M6

L6

M7

L7

M8

L8

M9

L9

M10

L10

ADC C Digital Output Complement

ADC C Digital Output True

ADC B Digital Output Complement

ADC B Digital Output True

Rev. B | Page 13 of 48

AD9273

Pin No.

BGA

TQFP

45

46

48

49

51

52

53

56

57

58

59

62

63

64

65

68

69

70

71

74

75

76

77

78

79

80

81

82

83

84

85

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Name

DOUTA−

DOUTA+

STBY

PDWN

SCLK

SDIO

CSB

LG-A

LI-A

LOSW-A

LO-A

LG-B

LI-B

LOSW-B

LO-B

LG-C

LI-C

LOSW-C

LO-C

LG-D

Description

M11

L11

K11

J11

K12

J12

H12

B9

ADC A Digital Output Complement

ADC A Digital Output True

Standby Power-Down

Full Power-Down

Serial Clock

Serial Data Input/Output

Chip Select Bar

LNA Ground for Channel A

LNA Analog Input for Channel A

A9

D9

C9

LNA Analog Switched Output for Channel A

LNA Analog Inverted Output for Channel A

LNA Ground for Channel B

B10

A10

D10

C10

B11

A11

D11

C11

B12

A12

D12

C12

K10

J10

K9

J9

K8

J8

K7

J7

A8

A7

A6

LNA Analog Input for Channel B

LNA Analog Switched Output for Channel B

LNA Analog Inverted Output for Channel B

LNA Ground for Channel C

LNA Analog Input for Channel C

LNA Analog Switched Output for Channel C

LNA Analog Inverted Output for Channel C

LNA Ground for Channel D

LI-D

LOSW-D

LO-D

LNA Analog Input for Channel D

LNA Analog Switched Output for Channel D

LNA Analog Inverted Output for Channel D

CW Doppler Output Complement for Channel 0

CW Doppler Output True for Channel 0

CW Doppler Output Complement for Channel 1

CW Doppler Output True for Channel 1

CW Doppler Output Complement for Channel 2

CW Doppler Output True for Channel 2

CW Doppler Output Complement for Channel 3

CW Doppler Output True for Channel 3

Gain Control Voltage Input Complement

Gain Control Voltage Input True

CWD0−

CWD0+

CWD1−

CWD1+

CWD2−

CWD2+

CWD3−

CWD3+

GAIN−

GAIN+

RBIAS

External Resistor to Set the Internal ADC Core Bias Current

Voltage Reference Input/Output

A5

K6

J6

K5

J5

K4

J4

K3

VREF

CWD4−

CWD4+

CWD5−

CWD5+

CWD6−

CWD6+

CWD7−

CWD7+

LO-E

CW Doppler Output Complement for Channel 4

CW Doppler Output True for Channel 4

CW Doppler Output Complement for Channel 5

CW Doppler Output True for Channel 5

CW Doppler Output Complement for Channel 6

CW Doppler Output True for Channel 6

CW Doppler Output Complement for Channel 7

CW Doppler Output True for Channel 7

LNA Analog Inverted Output for Channel E

LNA Analog Switched Output for Channel E

J3

C1

D1

LOSW-E

Rev. B | Page 14 of 48

AD9273

TYPICAL PERFORMANCE CHARACTERISTICS

f_SAMPLE= 40 MSPS, f_IN= 5 MHz, R_S= 50 Ω, LNA gain = 21.3 dB, LNA bias = mid-high, PGA gain = 24 dB, AAF LPF cutoff = f_SAMPLE/3,

HPF = LPF cutoff/20.7 (default), GAIN− = 0.8 V

2.0

14

12

10

8

1.5

1.0

0.5

–40°C

+85°C

+25°C

0

6

–0.5

–1.0

–1.5

–2.0

4

2

0

0.2

0.4

0.6

0.8

GAIN+ (V)

1.0

1.2

1.4

1.6

GAIN ERROR (dB)

Figure 6. Gain Error vs. GAIN+ at Three Temperatures

Figure 9. Gain Error Histogram, GAIN+ = 1.44 V

20

18

16

14

12

10

8

25

20

15

10

6

4

5

0

2

0

–1.25 –1.00 –0.75 –0.50 –0.25

0

0.25 0.50 0.75 1.00 1.25

GAIN ERROR (dB)

CHANNEL-TO-CHANNEL GAIN MATCHING (dB)

Figure 7. Gain Error Histogram, GAIN+ = 0.16 V

Figure 10. Gain Match Histogram, GAIN+ = 0.3 V

25

20

15

10

14

12

10

8

6

4

5

0

2

0

–1.25 –1.00 –0.75 –0.50 –0.25

0

0.25 0.50 0.75 1.00 1.25

CHANNEL-TO-CHANNEL GAIN MATCHING (dB)

GAIN ERROR (dB)

Figure 11. Gain Match Histogram, GAIN+ = 1.3 V

Figure 8. Gain Error Histogram, GAIN+ = 0.8 V

Rev. B | Page 15 of 48

AD9273

–128

–129

–130

–131

–132

–133

–134

–135

–136

–137

–138

–139

500k

450k

400k

350k

300k

250k

200k

150k

100k

50k

LNA GAIN = 12×

LNA GAIN = 8×

LNA GAIN = 6×

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

–7 –6 –5 –4 –3 –2 –1

0

1

2

3

4

5

6

7

GAIN+ (V)

CODES

Figure 12. Output-Referred Noise Histogram, GAIN+ = 0.0 V

Figure 15. Short-Circuit, Output-Referred Noise vs. GAIN+

200k

65

60

55

50

45

40

180k

160k

140k

120k

100k

80k

60k

40k

20k

0

SNR

SINAD

–7 –6 –5 –4 –3 –2 –1

0

1

2

3

4

5

6

7

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6

GAIN+ (V)

CODES

Figure 13. Output-Referred Noise Histogram, GAIN+ = 1.6 V

Figure 16. SNR/SINAD vs. GAIN+, AIN = −1.0 dBFS

3.0

0

–2

50MSPS

2.5

2.0

1.5

1.0

0.5

0

–4

40MSPS

–6

LNA GAIN = 15.6dB

LNA GAIN = 17.9dB

–8

–10

–12

–14

–16

–18

–20

25MSPS

LNA GAIN = 21.3dB

1

2

3

4

5

6

7

8

9

10

0

5

10

15

20

25

FREQUENCY (MHz)

Figure 17. Antialiasing Filter (AAF) Pass-Band Response,

LPF Cutoff = 1 × (1/3) × f_SAMPLE

Figure 14. Short-Circuit, Input-Referred Noise vs. Frequency,

PGA Gain = 30 dB, GAIN+ = 1.6 V

Rev. B | Page 16 of 48

AD9273

150

125

100

75

0

–20

–40

GAIN+ = 1.6V

GAIN+ = 0.8V

GAIN+ = 0V

GAIN+ = 0.8V

–60

GAIN+ = 0V

GAIN+ = 1.6V

50

–80

25

–100

–120

0

–40

–35

–30

–25

–20

–15

–10

–5

0

5

10

15

20

25

30

35

40

ADC OUTPUT LEVEL (dBFS)

FREQUENCY (MHz)

Figure 18. Antialiasing Filter (AAF) Group Delay Response

Figure 21. Second-Order Harmonic Distortion vs. ADC Output Level

0

–20

–40

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

GAIN+ = 0.8V

GAIN+ = 0V

–60

GAIN+ = 0.5V

–80

GAIN+ = 1.6V

GAIN+ = 1.0V

–100

–120

0

2

4

6

8

10

12

14

16

–40

–35

–30

–25

–20

–15

–10

–5

0

INPUT FREQUENCY (MHz)

ADC OUTPUT LEVEL (dBFS)

Figure 19. Second-Order Harmonic Distortion vs. Input Frequency,

AIN = −1.0 dBFS

Figure 22. Third-Order Harmonic Distortion vs. ADC Output Level

0

–10

–20

–30

0

f_IN1

= f_IN2+ 0.01MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

A

1 = –1dBFS, A 2 = –21dBFS

IN

–40

GAIN+ = 0.5V

GAIN+ = 1.6V

–50

5MHz

8MHz

–60

–70

GAIN+ = 1.0V

2.3MHz

–80

0

2

4

6

8

10

12

14

16

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6

GAIN+ (V)

INPUT FREQUENCY (MHz)

Figure 20. Third-Order Harmonic Distortion vs. Input Frequency,

AIN = −1.0 dBFS

Figure 23. IMD3 vs. GAIN+

Rev. B | Page 17 of 48

AD9273

0

f_IN1= 5.00MHz, f_IN2= 5.01MHz

FUND2 LEVEL = FUND1 LEVEL – 20dB

–20

–40

–60

GAIN+ = 0.8V

GAIN+ = 1.6V

GAIN+ = 0V

–80

–100

–120

–40

–35

–30

–25

–20

–15

–10

–5

0

FUND1 LEVEL (dBFS)

Figure 24. IMD3 vs. Fundamental 1 Amplitude (FUND1) Level

Rev. B | Page 18 of 48

AD9273

EQUIVALENT CIRCUITS

AVDDx

V

AVDDx

CM

15kΩ

350Ω

30kΩ

LI-x,

LG-x

SDIO

Figure 25. Equivalent LNA Input Circuit

Figure 28. Equivalent SDIO Input Circuit

DRVDD

AVDDx

V

DOUTx–

DOUTx+

10Ω

V

LO-x,

LOSW-x

DRGND

Figure 26. Equivalent LNA Output Circuit

Figure 29. Equivalent Digital Output Circuit

10Ω

CLK+

10kΩ

1.25V

1kΩ

SCLK, PDWN,

OR STBY

10Ω

CLK–

30kΩ

Figure 27. Equivalent Clock Input Circuit

Figure 30. Equivalent SCLK, PDWN, or STBY Input Circuit

Rev. B | Page 19 of 48

AD9273

AVDDx

100Ω

RBIAS

AVDD2

50Ω

GAIN+

Figure 31. Equivalent RBIAS Circuit

Figure 34. Equivalent GAIN+ Input Circuit

AVDDx

70kΩ

1kΩ

0.8V

CSB

AVDD2

70kΩ

50Ω

GAIN–

Figure 32. Equivalent CSB Input Circuit

Figure 35. Equivalent GAIN− Input Circuit

10Ω

CWDx+,

CWDx–

+0.5V

VREF

6kΩ

Figure 36. Equivalent CWDx Output Circuit

Figure 33. Equivalent VREF Circuit

Rev. B | Page 20 of 48

AD9273

THEORY OF OPERATION

following the TGC amplifier, and then beam forming is

accomplished digitally.

ULTRASOUND

The primary application for the AD9273 is medical ultrasound.

Figure 37 shows a simplified block diagram of an ultrasound

system. A critical function of an ultrasound system is the time

gain control (TGC) compensation for physiological signal

attenuation. Because the attenuation of ultrasound signals is

exponential with respect to distance (time), a linear-in-dB VGA

is the optimal solution.

The ADC resolution of 12 bits with up to 50 MSPS sampling

satisfies the requirements of both general-purpose and high-

end systems.

Power conservation and low cost are two of the most important

factors in low-end and portable ultrasound machines, and the

AD9273 is designed to meet these criteria.

Key requirements in an ultrasound signal chain are very low noise,

active input termination, fast overload recovery, low power, and

differential drive to an ADC. Because ultrasound machines use

beam-forming techniques requiring a large binary-weighted

number of channels (for example, 32 to 512 channels), using the

lowest power at the lowest possible noise is of chief importance.

For additional information regarding ultrasound systems, refer

to “How Ultrasound System Considerations Influence Front-End

Component Choice,” Analog Dialogue, Volume 36, Number 3,

May–July 2002, and “The AD9271—A Revolutionary Solution

for Portable Ultrasound,” Analog Dialogue, Volume 41, Number 3,

July 2007.

Most modern machines use digital beam forming. In this

technique, the signal is converted to digital format immediately

Tx HV AMPs

BEAM-FORMER

CENTRAL CONTROL

Tx BEAM FORMER

MULTICHANNELS

AD9273

HV

Rx BEAM FORMER

(B AND F MODES)

MUX/

ADC

LNA

VGA

T/R

SWITCHES

DEMUX

AAF

CW

TRANSDUCER

ARRAY

128, 256, ETC.,

ELEMENTS

CW (ANALOG)

BEAM FORMER

IMAGE AND

MOTION

PROCESSING

(B MODE)

SPECTRAL

DOPPLER

PROCESSING

MODE

BIDIRECTIONAL

CABLE

COLOR

DOPPLER (PW)

PROCESSING

(F MODE)

AUDIO

OUTPUT

DISPLAY

Figure 37. Simplified Ultrasound System Block Diagram

Rev. B | Page 21 of 48

AD9273

R

LO-x

FB1

CWD[7:0]+

CWD[7:0]–

SWITCH

ARRAY

g_m

C

FB

LOSW-x

FB2

T/R

SWITCH

C

S

LI-x

DOUTx+

DOUTx–

SERIAL

LVDS

ATTENUATOR

–42dB TO 0dB

PIPELINE

ADC

LNA

POSTAMP

FILTER

C

SH

LG-x

C

LG

15.6dB,

17.9dB,

21.3dB

21dB

24dB,

27dB,

30dB

GAIN

INTERPOLATOR

AD9273

Figure 38. Simplified Block Diagram of a Single Channel

The LNA supports differential output voltages as high as

CHANNEL OVERVIEW

4.4 V p-p with positive and negative excursions of 1.1 V from a

common-mode voltage of 1.5 V. The LNA differential gain sets

the maximum input signal before saturation. One of three gains

is set through the SPI. The corresponding full-scale input for

the gain settings of 6, 8, and 12 is 733 mV p-p, 550 mV p-p, and

367 mV p-p, respectively. Overload protection ensures quick

recovery time from large input voltages. Because the inputs are

capacitively coupled to a bias voltage near midsupply, very large

inputs can be handled without interacting with the ESD protection.

Each channel contains both a TGC signal path and a CW Doppler

signal path. Common to both signal paths, the LNA provides user-

adjustable input impedance termination. The CW Doppler path

includes a transconductance amplifier and a crosspoint switch.

The TGC path includes a differential X-AMP® VGA, an antialiasing

filter, and an ADC. Figure 38 shows a simplified block diagram

with external components.

The signal path is fully differential throughout to maximize signal

swing and reduce even-order distortion; however, the LNA is

designed to be driven from a single-ended signal source.

Low value feedback resistors and the current-driving capability

of the output stage allow the LNA to achieve a low input-referred

noise voltage of 1.26 nV/√Hz at a gain of 21.3 dB. This is achieved

with a current consumption of only 10 mA per channel (30 mW).

On-chip resistor matching results in precise single-ended gains,

which are critical for accurate impedance control. The use of a

fully differential topology and negative feedback minimizes

distortion. Low second-order harmonic distortion is particularly

important in second-order harmonic ultrasound imaging

applications. Differential signaling enables smaller swings at

each output, further reducing third-order distortion.

Low Noise Amplifier (LNA)

Good noise performance relies on a proprietary ultralow noise

LNA at the beginning of the signal chain, which minimizes the

noise contribution in the following VGA. Active impedance

control optimizes noise performance for applications that benefit

from input impedance matching.

A simplified schematic of the LNA is shown in Figure 39. LI-x is

capacitively coupled to the source. An on-chip bias generator

establishes dc input bias voltages of around 0.9 V and centers

the output common-mode levels at 1.5 V (AVDD2 divided by

2). A capacitor, C_LG, of the same value as the input coupling

capacitor, C_S, is connected from the LG-x pin to ground.

Recommendation

It is highly recommended that the LG-x pins form a Kelvin type

connection to the input or probe connection ground. Simply

connecting the LG pin to ground near the device may allow

differences in potential to be amplified through the LNA. This

generally shows up as a dc offset voltage that can vary from

channel to channel and part to part, depending on the

application and layout of the PCB (see Figure 38).

C

FB

R

FB1

FB2

V

+

O

R

V

–

O

LOSW-x

LO-x

V

CM

V

CM

T/R

SWITCH

C

S

LI-x

LG-x

C

SH

C

LG

Figure 39. Simplified LNA Schematic

Rev. B | Page 22 of 48

AD9273

1k

100

10

Active Impedance Matching

R

= 500Ω, R = 2kΩ

FB

S

The LNA consists of a single-ended voltage gain amplifier with

differential outputs and the negative output available externally.

For example, with a fixed gain of 8× (17.9 dB), an active input

termination is synthesized by connecting a feedback resistor

between the negative output pin, LO-x, and the positive input pin,

LI-x. This well-known technique is used for interfacing multiple

probe impedances to a single system. The input resistance is

shown in Equation 1.

R

= 200Ω, R = 800Ω

FB

S

= 100Ω, R = 400Ω, C = 20pF

FB SH

R

= 50Ω, R = 200Ω, C = 70pF

FB SH

S

R_FB

R_IN

=

(1)

A

(1 +

)

2

100k

1M

10M

100M

where A/2 is the single-ended gain or the gain from the LI-x

FREQUENCY (Hz)

inputs to the LO-x outputs, and R_FBis the resulting impedance

of the R_FB1and R_FB2combination (see Figure 39).

Figure 40. R_INvs. Frequency for Various Values of R_FB

(Effects of R_Sand C_SHAre Also Shown)

Because the amplifier has a gain of 8× from its input to its

differential output, it is important to note that the gain A/2 is

the gain from Pin LI-x to Pin LO-x, and it is 6 dB less than the

gain of the amplifier, or 12.1 dB (4×). The input resistance is

reduced by an internal bias resistor of 15 kΩ in parallel with the

source resistance connected to Pin LI-x while Pin LG-x is ac

grounded. Equation 2 can be used to calculate the needed R_FB

for a desired R_IN, even for higher values of R_IN.

Note that at the lowest value (50 Ω), R_INpeaks at frequencies

greater than 10 MHz. This is due to the BW roll-off of the LNA,

as mentioned previously.

However, as can be seen for larger R_INvalues, parasitic capacitance

starts rolling off the signal BW before the LNA can produce

peaking. C_SHfurther degrades the match; therefore, C_SHshould

not be used for values of R_INthat are greater than 100 Ω. Table 7

lists the recommended values for R_FBand C_SHin terms of R_IN.

R_FB

(2)

R_IN

=

||15 kΩ

C_FBis needed in series with R_FBbecause the dc levels at Pin LO-x

and Pin LI-x are unequal.

(1+ 3)

For example, to set R_INto 200 Ω, the value of R_FBmust be

1000 Ω. If the simplified equation (Equation 2) is used to

calculate R_IN, the value is 188 Ω, resulting in a gain error less

than 0.6 dB. Some factors, such as the presence of a dynamic

source resistance, might influence the absolute gain accuracy

more significantly. At higher frequencies, the input capacitance

of the LNA needs to be considered. The user must determine

the level of matching accuracy and adjust R_FBaccordingly.

Table 7. Active Termination External Component Values

LNA Gain

(dB)

Minimum

C_SH(pF)

R_IN(Ω)

50

R_FB(Ω)

200

BW (MHz)

15.6

17.9

21.3

15.6

17.9

21.3

15.6

17.9

21.3

90

57

69

88

57

69

88

72

50

250

70

50

350

50

100

200

400

500

700

800

1000

1400

30

20

10

N/A

The bandwidth (BW) of the LNA is greater than 100 MHz.

Ultimately, the BW of the LNA limits the accuracy of the

synthesized R_IN. For R_IN= R_Sup to about 200 Ω, the best match

is between 100 kHz and 10 MHz, where the lower frequency

limit is determined by the size of the ac-coupling capacitors,

and the upper limit is determined by the LNA BW. Furthermore,

the input capacitance and R_Slimit the BW at higher frequencies.

Figure 40 shows R_INvs. frequency for various values of R_FB.

Rev. B | Page 23 of 48

AD9273

Figure 42 shows the relative noise figure performance. In this

graph, the input impedance was swept with R_Sto preserve the

match at each point. The noise figures for a source impedance of

50 ꢀ are 7.3 dB, 4.2 dB, and 2.8 dB for the resistive termination,

active termination, and unterminated configurations, respectively.

The noise figures for 200 ꢀ are 4.5 dB, 1.7 dB, and 1.0 dB,

respectively.

LNA Noise

The short-circuit noise voltage (input-referred noise) is an impor-

tant limit on system performance. The short-circuit input-referred

noise voltage for the LNA is 1.4 nV/√Hz at a gain of 21.3 dB,

including the VGA noise at a VGA postamp gain of 27 dB. These

measurements, which were taken without a feedback resistor,

provide the basis for calculating the input noise and noise figure

(NF) performance of the configurations shown in Figure 41.

UNTERMINATED

Figure 43 shows the noise figure as it relates to R_Sfor various values

of R_IN, which is helpful for design purposes.

R

IN

R

S

12.0

10.5

9.0

+

–

V

OUT

LI-x

RESISTIVE TERMINATION

R

IN

R

SHUNT TERMINATION

7.5

S

+

–

R

V

S

OUT

LI-x

6.0

4.5

3.0

1.5

0

UNTERMINATED

ACTIVE

TERMINATION

ACTIVE IMPEDANCE MATCH

R

FB

R

IN

R

S

+

–

V

OUT

LI-x

10

100

(Ω)

1k

R

S

R

FB

R

=

Figure 42. Noise Figure vs. R_Sfor Shunt Termination,

Active Termination Matched, and Unterminated Inputs, V_GAIN= 0.8 V

IN

1 + A/2

Figure 41. Input Configurations

12.0

Figure 42 and Figure 43 are simulations of noise figure vs. source

resistance (R_S) results using these configurations and an input-

referred noise voltage of 6 nV/√Hz for the VGA. Unterminated

(R_FB= ∞) operation exhibits the lowest equivalent input noise

and noise figure. Figure 43 shows the noise figure vs. R_Srising at

low R_S—where the LNA voltage noise is large compared with the

source noise—and at high R_Sdue to the noise contribution from

R_FB. The lowest NF is achieved when R_Smatches R_IN.

UNTERMINATED

10.5

9.0

7.5

6.0

4.5

3.0

1.5

0

R

= 200Ω

= 100Ω

= 75Ω

IN

= 50Ω

The main purpose of input impedance matching is to improve the

transient response of the system. With resistive termination, the

input noise increases due to the thermal noise of the matching

resistor and the increased contribution of the LNA’s input

voltage noise generator. With active impedance matching,

however, the contributions of both are smaller (by a factor of

1/(1 + LNA Gain)) than they would be for resistive termination.

10

100

1k

R

(Ω)

S

Figure 43. Noise Figure vs. R_Sfor Various Fixed Values of R_IN

,

Active Termination Matched Inputs, V_GAIN= 0.8 V

Rev. B | Page 24 of 48

AD9273

INPUT OVERDRIVE

CW DOPPLER OPERATION

Excellent overload behavior is of primary importance in

ultrasound. Both the LNA and VGA have built-in overdrive

protection and quickly recover after an overload event.

Modern ultrasound machines used for medical applications

employ a 2^Nbinary array of receivers for beam forming, with

typical array sizes of 16 or 32 receiver channels phase-shifted

and summed together to extract coherent information. When

used in multiples, the desired signals from each channel can be

summed to yield a larger signal (increased by a factor N, where

N is the number of channels), and the noise is increased by the

square root of the number of channels. This technique enhances

the signal-to-noise performance of the machine. The critical

elements in a beam-former design are the means to align the

incoming signals in the time domain and the means to sum the

individual signals into a composite whole.

Input Overload Protection

As with any amplifier, voltage clamping prior to the inputs is

highly recommended if the application is subject to high

transient voltages.

In Figure 44, a simplified ultrasound transducer interface is

shown. A common transducer element serves the dual functions

of transmitting and receiving ultrasound energy. During the

transmitting phase, high voltage pulses are applied to the ceramic

elements. A typical transmit/receive (T/R) switch can consist of

four high voltage diodes in a bridge configuration. Although the

diodes ideally block transmit pulses from the sensitive receiver

input, diode characteristics are not ideal, and the resulting leakage

transients imposed on the LI-x inputs can be problematic.

Beam forming, as applied to medical ultrasound, is defined as the

phase alignment and summation of signals that are generated

from a common source but received at different times by a

multielement ultrasound transducer. Beam forming has two

functions: it imparts directivity to the transducer, enhancing its

gain, and it defines a focal point within the body from which the

location of the returning echo is derived.

Because ultrasound is a pulse system and time-of-flight is used to

determine depth, quick recovery from input overloads is essential.

Overload can occur in the preamp and the VGA. Immediately

following a transmit pulse, the typical VGA gains are low, and

the LNA is subject to overload from T/R switch leakage. With

increasing gain, the VGA can become overloaded due to strong

echoes that occur near field echoes and acoustically dense materials,

such as bone.

The AD9273 includes the front-end components needed to

implement analog beam forming for CW Doppler operation.

These components allow CW channels with similar phases to be

coherently combined before phase alignment and down mixing,

thus reducing the number of delay lines or adjustable phase shifters/

down mixers (AD8333 or AD8339) required. Next, if delay lines

are used, the phase alignment is performed, and then the channels

are coherently summed and down converted by a dynamic range

I/Q demodulator. Alternatively, if phase shifters/down mixers,

such as the AD8333 and AD8339, are used, phase alignment

and downconversion are done before coherently summing all

channels into I/Q signals. In either case, the resultant I and Q

signals are filtered and sampled by two high resolution ADCs,

and the sampled signals are processed to extract the relevant

Doppler information.

Figure 44 illustrates an external overload protection scheme. A

pair of back-to-back signal diodes is installed prior to installing the

ac-coupling capacitors. Keep in mind that all diodes shown in

this example are prone to exhibiting some amount of shot noise.

Many types of diodes are available for achieving the desired noise

performance. The configuration shown in Figure 44 tends to add

2 nV/√Hz of input-referred noise. Decreasing the 5 kΩ resistor

and increasing the 2 kΩ resistor may improve noise contribution,

depending on the application. With the diodes shown in Figure 44,

clamping levels of 0.5 V or less significantly enhance the overload

performance of the system.

Alternately, the LNA of the AD9273 can directly drive the AD8333

or AD8339 without the crosspoint switch. The LO-x pins present

the inverting LNA output, and the LOSW-x pins can be configured

via Register 0x2C (see Table 17) to connect to the noninverting

output to provide a differential output of the LNA. The LNA output

full-scale voltage of the AD9273 is 4.4 V p-p, and the input full-

scale voltage is 2.7 V p-p. If no attenuation is provided between

the LNA output and the demodulator, the LNA input full-scale

voltage must be limited.

+5V

Tx

DRIVER

5kΩ

HV

AD9273

10nF

LNA

2kΩ

10nF

5kΩ

TRANSDUCER

–5V

Figure 44. Input Overload Protection

Rev. B | Page 25 of 48

AD9273

g_m

LNA

g_m

SWITCH

ARRAY

8 × CHANNEL

LNA

g_m

AD8333

600µH

LNA

2.5V

700Ω

600µH

AD8333

AD9273

g_m

600µH

700Ω

2.5V

LNA

600µH

g_m

SWITCH

ARRAY

I

8 × CHANNEL

LNA

16-BIT

ADC

g_m

Q

16-BIT

ADC

LNA

Figure 45. Typical Connection Interface with the AD8333 or AD8339 using the CWDx Outputs

2.5V

AD9273

5kΩ

1nF

AD8339

LO-A

500Ω

LNA

LOSW-A

1nF

2.5V

LOS-B

LNA

LOSW-B

1nF

2.5V

5kΩ

1nF

AD8339

LO-H

500Ω

LNA

I

LOSW-H

16-BIT

ADC

Q

16-BIT

ADC

Figure 46. Typical Connection Interface with the AD8333 or AD8339 using the LO-x and LOSW-x Outputs

Rev. B | Page 26 of 48

AD9273

The maximum gain required is determined by

Crosspoint Switch

Each LNA is followed by a transconductance amp for voltage-

to-current conversion. Currents can be routed to one of eight

pairs of differential outputs or to 16 single-ended outputs for

summing. Each CWD output pin sinks 2.4 mA dc current, and

the signal has a full-scale current of 2 mA for each channel

selected by the crosspoint switch. For example, if four channels

are summed on one CWD output, the output sinks 9.6 mA dc

and has a full-scale current output of 8 mA.

(ADC Noise Floor/VGA Input Noise Floor) + Margin =

20 log(224/5.4) + 11 dB = 43 dB

The minimum gain required is determined by

(ADC Input FS/VGA Input FS) + Margin =

20 log(2/0.55) – 10 dB = 3 dB

Therefore, 42 dB of gain range for a 12-bit, 40 MSPS ADC with

15 MHz of bandwidth should suffice in achieving the dynamic

range required for most of today’s ultrasound systems.

The maximum number of channels combined must be considered

when setting the load impedance for current-to-voltage conversion

to ensure that the full-scale swing and common-mode voltage

are within the operating limits of the AD9273. When interfacing

to the AD8339, a common-mode voltage of 2.5 V and a full-scale

swing of 2.8 V p-p are desired. This can be accomplished by

connecting an inductor between each CWD output and a 2.5 V

supply, and then connecting either a single-ended or differential

load resistance to the CWDx outputs. The value of resistance

should be calculated based on the maximum number of channels

that can be combined.

The system gain is distributed as listed in Table 8.

Table 8. Channel Gain Distribution

Section

Nominal Gain (dB)

LNA

15.6/17.9/21.3

Attenuator

VGA Amp

Filter

−42 to 0

21/24/27/30

0

ADC

The linear-in-dB gain (law conformance) range of the TGC path

is 42 dB. The slope of the gain control interface is 28 dB/V, and

the gain control range is −0.8 V to +0.8 V. Equation 3 is the

expression for the differential voltage V_GAIN, and Equation 4 is

the expression for the channel gain.

CWDx outputs are required under full-scale swing to be

greater than 1.5 V and less than AVDD2 (3.0 V supply).

TGC OPERATION

The TGC signal path is fully differential throughout to maximize

signal swing and reduce even-order distortion; however, the LNAs

are designed to be driven from a single-ended signal source. Gain

values are referenced from the single-ended LNA input to the

differential ADC input. A simple exercise in understanding the

maximum and minimum gain requirements is shown in Figure 47.

V

_GAIN(V) = GAIN(+)− GAIN(−)

(3)

dB

V

Gain (dB) = 28

V_GAIN+ ICPT

(4)

where ICPT is the intercept point of the TGC gain.

In its default condition, the LNA has a gain of 21.3 dB (12×) and

the VGA postamp gain is 24 dB if the voltage on the GAIN+ pin is

0 V and the voltage on the GAIN− pin is 0.8 V (42 dB attenuation).

This gives rise to a total gain (or ICPT) of 3.6 dB through the

TGC path if the LNA input is unmatched, or of −2.4 dB if the

LNA is matched to 50 Ω (R_FB= 350 Ω). If the voltage on the

GAIN+ pin is 1.6 V and the voltage on the GAIN− pin is 0.8 V

(0 dB attenuation), however, the VGA gain is 24 dB. This results

in a total gain of 45 dB through the TGC path if the LNA input is

unmatched, or in a total gain of 39 dB if the LNA input is matched.

ADC FS (2V p-p)

MINIMUM GAIN

~10dB MARGIN

LNA FS

(0.55V p-p SE)

70dB

ADC

91dB

>11dB MARGIN

ADC NOISE FLOOR

(224µV rms)

LNA

MAXIMUM GAIN

LNA INPUT-REFERRED

NOISE FLOOR

(5.4µV rms) @ AAF BW = 15MHz

LNA + VGA NOISE = 1.4nV/ Hz

VGA GAIN RANGE > 42dB

MAX CHANNEL GAIN > 48dB

Figure 47. Gain Requirements of TGC Operation for a 12-Bit, 40 MSPS ADC

Each LNA output is dc-coupled to a VGA input. The VGA consists

of an attenuator with a range of −42 dB to 0 dB followed by an

amplifier with 21 dB, 24 dB, 27 dB, or 30 dB of gain. The X-AMP

gain-interpolation technique results in low gain error and uniform

bandwidth, and differential signal paths minimize distortion.

Rev. B | Page 27 of 48

AD9273

Table 9. Sensitivity and Dynamic Range of Trade-Offs^{1, 2, 3}

LNA

Channel

Typical Output Dynamic Range

Gain

Input-Referred

Full-Scale Input Noise Voltage

VGA

Input-Referred Noise⁶

@

GAIN+ = 1.6 V (nV/√Hz)

(V/V) (dB) (V p-p)

(nV/√Hz)

Postamp Gain (dB) GAIN+ = 0 V⁴

GAIN+ = 1.6 V⁵

62.3

59.7

57.0

6

15.6 0.733

17.9 0.550

21.3 0.367

1.6

21

24

27

30

21

24

27

30

21

24

27

30

65.9

64.1

61.8

59.2

65.9

64.1

61.8

59.2

65.9

64.1

61.8

59.2

1.98

1.91

1.87

1.85

1.66

1.61

1.58

1.57

1.35

1.32

1.31

1.30

54.1

8

1.42

1.26

61.6

58.9

56.2

53.3

12

60.1

57.3

54.4

51.5

¹LNA: output full scale = 4.4 V p-p differential.

²Filter: loss ~ 1 dB, NBW = 13.3 MHz, GAIN− = 0.8 V.

³ADC: 40 MSPS, 70 dB SNR, 2 V p-p full-scale input.

⁴Output dynamic range at minimum VGA gain (VGA dominated).

⁵Output dynamic range at maximum VGA gain (LNA dominated).

⁶Channel noise at maximum VGA gain.

Table 9 demonstrates the sensitivity and dynamic range of

trade-offs that can be achieved relative to various LNA and

VGA gain settings.

GAIN+ and GAIN− pins. The LNA has three limitations, or full-

scale settings, that can be applied through the SPI. Similarly, the

VGA has four postamp gain settings that can be applied through

the SPI. The voltage applied to the GAIN pins determines

which amplifier (the LNA or VGA) saturates first. The maximum

signal input level that can be applied as a function of voltage on

the GAIN pins for the selectable gain options of the SPI is shown

in Figure 48 to Figure 50.

For example, when the VGA is set for the minimum gain voltage,

the TGC path is dominated by VGA noise and achieves the

maximum output SNR. However, as the postamp gain options

are increased, the input-referred noise is reduced and the SNR

is degraded.

0.40

If the VGA is set for the maximum gain voltage, the TGC path

is dominated by LNA noise and achieves the lowest input-

referred noise, but with degraded output SNR. The higher the

TGC (LNA + VGC) gain, the lower the output SNR. As the

postamp gain is increased, the input-referred noise is reduced.

0.35

PGA GAIN = 21dB

0.30

PGA GAIN = 24dB

0.25

PGA GAIN = 27dB

0.20

At low gains, the VGA should limit the system noise perfor-

mance (SNR); at high gains, the noise is defined by the source and

the LNA. The maximum voltage swing is bound by the full-

scale peak-to-peak ADC input voltage (2 V p-p).

0.15

PGA GAIN = 30dB

0.10

0.05

0

Both the LNA and VGA have full-scale limitations within each

section of the TGC path. These limitations are dependent on the

gain setting of each function block and on the voltage applied to the

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

GAIN+ (V)

Figure 48. LNA with 15.6 dB Gain Setting/VGA Full-Scale Limitations

Rev. B | Page 28 of 48

AD9273

0.6

0.5

0.4

0.3

0.2

0.1

per side is 180 Ω nominally for a total differential resistance of

360 Ω. The ladder is driven by a fully differential input signal from

the LNA. LNA outputs are dc-coupled to avoid external decoupling

capacitors. The common-mode voltage of the attenuator and the

VGA is controlled by an amplifier that uses the same midsupply

voltage derived in the LNA, permitting dc coupling of the LNA

to the VGA without introducing large offsets due to common-

mode differences. However, any offset from the LNA becomes

amplified as the gain increases, producing an exponentially

increasing VGA output offset.

PGA GAIN = 21dB

PGA GAIN = 24dB

PGA GAIN = 27dB

The input stages of the X-AMP are distributed along the ladder,

and a biasing interpolator, controlled by the gain interface, deter-

mines the input tap point. With overlapping bias currents, signals

from successive taps merge to provide a smooth attenuation range

from −42 dB to 0 dB. This circuit technique results in linear-in-dB

gain law conformance and low distortion levels—only deviating

0.5 dB or less from the ideal. The gain slope is monotonic with

respect to the control voltage and is stable with variations in

process, temperature, and supply.

PGA GAIN = 30dB

0.4 0.6

0

0.2

0.8

1.0

1.2

1.4

1.6

GAIN+ (V)

Figure 49. LNA with 17.9 dB Gain Setting/VGA Full-Scale Limitations

0.9

0.8

PGA GAIN = 21dB

0.7

0.6

The X-AMP inputs are part of a programmable gain feedback

amplifier that completes the VGA. Its bandwidth is approximately

100 MHz. The input stage is designed to reduce feedthrough to

the output and to ensure excellent frequency response uniformity

across the gain setting.

PGA GAIN = 24dB

0.5

0.4

0.3

0.2

Gain Control

PGA GAIN = 27dB

0.1

The gain control interface, GAIN , is a differential input. V_GAIN

varies the gain of all VGAs through the interpolator by selecting

the appropriate input stages connected to the input attenuator.

For GAIN− at 0.8 V, the nominal GAIN+ range for 28 dB/V is

0 V to 1.6 V, with the best gain linearity from about 0.16 V to

1.44 V, where the error is typically less than 0.5 dB. For

GAIN+ voltages greater than 1.44 V and less than 0.16 V, the

error increases. The value of GAIN+ can exceed the supply

voltage by 1 V without gain foldover.

PGA GAIN = 30dB

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

GAIN+ (V)

Figure 50. LNA with 21.3 dB Gain Setting/VGA Full-Scale Limitations

Variable Gain Amplifier

The differential X-AMP VGA provides precise input attenuation

and interpolation. It has a low input-referred noise of 6 nV/√Hz

and excellent gain linearity. A simplified block diagram is shown in

Figure 51.

Gain control response time is less than 750 ns to settle within 10%

of the final value for a change from minimum to maximum gain.

GAIN±

GAIN INTERPOLATOR

POSTAMP

+

There are two ways in which the GAIN+ and GAIN− pins can

be interfaced. With the single-ended method, a Kelvin type of

connection to ground can be used as shown in Figure 52. For

driving multiple devices, it is preferable to use the differential

method shown in Figure 53. In either method, the GAIN+ and

GAIN− pins should be dc-coupled and driven to accommodate

a 1.6 V full-scale input.

g

m

3dB

VIP

VIN

AD9273

100Ω

0V TO 1.6V DC

GAIN+

GAIN–

–

POSTAMP

50Ω

0.01µF

Figure 51. Simplified VGA Schematic

KELVIN

CONNECTION

0.01µF

The input of the VGA is a 14-stage differential resistor ladder with

3.5 dB per tap. The resulting total gain range is 42 dB, which

allows for range loss at the endpoints. The effective input resistance

Figure 52. Single-Ended GAIN Pins Configuration

Rev. B | Page 29 of 48

AD9273

499Ω

AVDD2

31.3kΩ

50Ω

The antialaising filter is a combination of a single-pole high-

pass filter and a second-order low-pass filter. The high-pass

filter can be configured at a ratio of the low-pass filter cutoff.

This is selectable through the SPI.

±0.4VDC AT

0.8V CM

AD9273

499Ω

100Ω

0.01µF

100Ω

GAIN+

±0.8V DC

0.8V CM

AD8138

523Ω

GAIN–

10kΩ

The filter uses on-chip tuning to trim the capacitors and in turn

set the desired cutoff frequency and reduce variations. The

default −3 dB low-pass filter cutoff is 1/3 or 1/4.5 the ADC

sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1,

1.2, or 1.3 times this frequency through the SPI. The cutoff

tolerance is maintained from 8 MHz to 18 MHz.

4kΩ

±0.4VDC AT

0.8V CM

0.01µF

499Ω

Figure 53. Differential GAIN Pins Configuration

VGA Noise

In a typical application, a VGA compresses a wide dynamic

range input signal to within the input span of an ADC. The

input-referred noise of the LNA limits the minimum resolvable

input signal, whereas the output-referred noise, which depends

primarily on the VGA, limits the maximum instantaneous

dynamic range that can be processed at any one particular gain

control voltage. This latter limit is set in accordance with the

total noise floor of the ADC.

C

30C

4kΩ

10kΩ/n

4kΩ

2kΩ

4C

2kΩ

30C

C

Output-referred noise as a function of GAIN+ is shown in Figure 15

for the short-circuit input conditions. The input noise voltage is

simply equal to the output noise divided by the measured gain

at each point in the control range.

C = 0.8pF TO 5.1pF

n = 0 TO 7

4kΩ

Figure 54. Simplified Filter Schematic

Tuning is normally off to avoid changing the capacitor settings

during critical times. The tuning circuit is enabled and disabled

through the SPI. Initializing the tuning of the filter must be

performed after initial power-up and after reprogramming the

filter cutoff scaling or ADC sample rate. Occasional retuning

during an idle time is recommended to compensate for

temperature drift.

The output-referred noise is a flat 90 nV/√Hz (postamp gain =

24 dB) over most of the gain range because it is dominated by

the fixed output-referred noise of the VGA. At the high end of

the gain control range, the noise of the LNA and of the source

prevail. The input-referred noise reaches its minimum value

near the maximum gain control voltage, where the input-

referred contribution of the VGA is miniscule.

There is a total of eight SPI-programmable settings that allow the

user to vary the high-pass filter cutoff frequency as a function

of the low-pass cutoff frequency. Two examples are shown in

Table 10: one is for an 8 MHz low-pass cutoff frequency, and the

other is for an 18 MHz low-pass cutoff frequency. In both cases,

as the ratio decreases, the amount of rejection on the low-end

frequencies increases. Therefore, making the entire AAF

frequency pass band narrow can reduce low frequency noise or

maximize dynamic range for harmonic processing.

At lower gains, the input-referred noise, and therefore the noise

figure, increases as the gain decreases. The instantaneous

dynamic range of the system is not lost, however, because the

input capacity increases as the input-referred noise increases.

The contribution of the ADC noise floor has the same

dependence. The important relationship is the magnitude of the

VGA output noise floor relative to that of the ADC.

Gain control noise is a concern in very low noise applications.

Thermal noise in the gain control interface can modulate the

channel gain. The resultant noise is proportional to the output

signal level and is usually evident only when a large signal is

present. The gain interface includes an on-chip noise filter, which

significantly reduces this effect at frequencies greater than 5 MHz.

Care should be taken to minimize noise impinging at the GAIN

inputs. An external RC filter can be used to remove V_GAINsource

noise. The filter bandwidth should be sufficient to accommodate

the desired control bandwidth.

Table 10. SPI-Selectable High-Pass Filter Cutoff Options

High-Pass Cutoff

Low-Pass Cutoff

SPI Setting Ratio¹= 8 MHz

Low-Pass Cutoff

= 18 MHz

0

1

2

3

4

5

6

7

20.65

11.45

7.92

6.04

4.88

4.10

3.52

3.09

387 kHz

698 kHz

872 kHz

1.571 MHz

2.273 MHz

2.978 MHz

3.685 MHz

4.394 MHz

5.107 MHz

5.822 MHz

1.010 MHz

1.323 MHz

1.638 MHz

1.953 MHz

2.270 MHz

2.587 MHz

Antialiasing Filter

The filter that the signal reaches prior to the ADC is used to

reject dc signals and to band limit the signal for antialiasing.

Figure 54 shows the architecture of the filter.

¹Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency.

Rev. B | Page 30 of 48

AD9273

3.3V

ADC

AD951x/AD952x

FAMILY

*

50Ω

VFAC3

OUT

0.1µF

The AD9273 uses a pipelined ADC architecture. The quantized

output from each stage is combined into a 12-bit result in the

digital correction logic. The pipelined architecture permits the

first stage to operate on a new input sample and the remaining

stages to operate on preceding samples. Sampling occurs on the

rising edge of the clock.

CLK

CLK+

ADC

AD9273

100Ω

LVDS DRIVER

CLK

0.1µF

CLK–

*

50Ω RESISTOR IS OPTIONAL.

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. The data is then serialized

and aligned to the frame and output clocks.

Figure 57. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

CLK+ should be driven directly from a CMOS gate, and the

CLK− pin should be bypassed to ground with a 0.1 μF capacitor

in parallel with a 39 kΩ resistor (see Figure 58). Although the

CLK+ input circuit supply is AVDDx (1.8 V), this input is

designed to withstand input voltages of up to 3.3 V, making the

selection of the drive logic voltage very flexible.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9273 sample clock inputs

(CLK+ and CLK−) should be clocked with a differential signal.

This signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or using capacitors. These pins are biased

internally and require no additional bias.

3.3V

Figure 55 shows the preferred method for clocking the AD9273.

A low jitter clock source, such as the Valpey Fisher oscillator

VFAC3-BHL-50MHz, is converted from single ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD9273 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD9273, and it preserves the

fast rise and fall times of the signal, which are critical to low

jitter performance.

AD951x/AD952x

FAMILY

0.1µF

VFAC3

CLK

CMOS DRIVER

CLK

OUT

OPTIONAL

0.1µF

*

50Ω

100Ω

CLK+

ADC

AD9273

0.1µF

CLK–

0.1µF

39kΩ

*

50Ω RESISTOR IS OPTIONAL.

Figure 58. Single-Ended 1.8 V CMOS Sample Clock

3.3V

AD951x/AD952x

FAMILY

MINI-CIRCUITS

ADT1-1WT, 1:1Z

0.1µF

VFAC3

OUT

CLK

0.1µF

OPTIONAL

XFMR

0.1µF

*

50Ω

OUT

CLK+

100Ω

CLK+

CMOS DRIVER

CLK

100Ω

ADC

50Ω

0.1µF

AD9273

VFAC3

ADC

AD9273

CLK–

0.1µF

SCHOTTKY

DIODES:

0.1µF

CLK–

HSM2812

Figure 55. Transformer-Coupled Differential Clock

*

50Ω RESISTOR IS OPTIONAL.

If a low jitter clock is available, another option is to ac-couple a

differential PECL signal to the sample clock input pins as shown

in Figure 56. The AD951x/AD952x family of clock drivers offers

excellent jitter performance.

Figure 59. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD9273 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9273. When the DCS is on, noise and distortion perfor-

mance are nearly flat for a wide range of duty cycles. However,

some applications may require the DCS function to be off. If so,

keep in mind that the dynamic range performance can be affected

when operated in this mode. See Table 17 for more details on

using this feature.

3.3V

AD951x/AD952x

*

50Ω

FAMILY

VFAC3

0.1µF

OUT

CLK

PECL DRIVER

CLK

CLK+

ADC

AD9273

100Ω

0.1µF

CLK–

240Ω

*

50Ω RESISTOR IS OPTIONAL.

Figure 56. Differential PECL Sample Clock

Rev. B | Page 31 of 48

AD9273

250

200

150

100

50

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately eight clock cycles

to allow the DLL to acquire and lock to the new rate.

I

, 50MSPS SPEED GRADE

AVDD1

I

, 40MSPS SPEED GRADE

AVDD1

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency (f_A)

due only to aperture jitter (t_J) can be calculated by

I

, 25MSPS SPEED GRADE

AVDD1

SNR Degradation = 20 × log 10[1/2 × π × f_A× t_J]

I

DRVDD

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter. IF undersampling applications

are particularly sensitive to jitter (see Figure 60).

0

10

20

30

40

50

SAMPLING FREQUENCY (MSPS)

Figure 61. Supply Current vs. f_SAMPLEfor f_IN= 5 MHz

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9273.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources, such as the Valpey Fisher VFAC3 series.

If the clock is generated from another type of source (by gating,

dividing, or other methods), it should be retimed by the

original clock during the last step.

120

115

110

105

100

95

50MSPS SPEED GRADE

40MSPS SPEED GRADE

25MSPS SPEED GRADE

90

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about how

jitter performance relates to ADCs (visit www.analog.com).

85

80

130

0

10

20

30

40

50

RMS CLOCK JITTER REQUIREMENT

120

110

SAMPLING FREQUENCY (MSPS)

Figure 62. Power per Channel vs. f_SAMPLEfor f_IN= 5 MHz

16 BITS

100

90

80

70

60

50

40

30

The AD9273 features scalable LNA bias currents (see Register 0x12

in Table 17). The default LNA bias current settings are high.

Figure 63 shows the typical reduction of AVDD2 current with

each bias setting. It is also recommended to adjust the LNA

offset using Register 0x10 (see Table 17) when the LNA bias

setting is low.

14 BITS

12 BITS

10 BITS

8 BITS

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

HIGH

1

10

100

1000

ANALOG INPUT FREQUENCY (MHz)

MID-HIGH

Figure 60. Ideal SNR vs. Analog Input Frequency and Jitter

Power Dissipation and Power-Down Mode

As shown in Figure 62, the power dissipated by the AD9273 is

proportional to its sample rate. The digital power dissipation

does not vary much because it is determined primarily by the

DRVDD supply and bias current of the LVDS output drivers.

MID-LOW

LOW

0

20

40

60

80

100

120

140

160

180

TOTAL AVDD2 CURRENT (mA)

Figure 63. AVDD2 Current at Different LNA Bias Settings, AD9273-40

Rev. B | Page 32 of 48

AD9273

By asserting the PDWN pin high, the AD9273 is placed into

power-down mode. In this state, the device typically dissipates

2 mW. During power-down, the LVDS output drivers are placed

into a high impedance state. The AD9273 returns to normal

operating mode when the PDWN pin is pulled low. This pin is

both 1.8 V and 3.3 V tolerant.

The AD9273 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs that have LVDS capability

for superior switching performance in noisy environments.

Single point-to-point net topologies are recommended with a

100 Ω termination resistor placed as close to the receiver as

possible. No far-end receiver termination and poor differential

trace routing may result in timing errors. It is recommended

that the trace length be no longer than 24 inches and that the

differential output traces be kept close together and at equal

lengths. An example of the FCO, DCO, and data stream with

proper trace length and position can be found in Figure 64.

By asserting the STBY pin high, the AD9273 is placed into a

standby mode. In this state, the device typically dissipates

140 mW. During standby, the entire part is powered down

except the internal references. The LVDS output drivers are

placed into a high impedance state. This mode is well suited for

applications that require power savings because it allows the

device to be powered down when not in use and then quickly

powered up. The time to power this device back up is also greatly

reduced. The AD9273 returns to normal operating mode when

the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V

tolerant.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on VREF are discharged

when entering power-down mode and must be recharged when

returning to normal operation. As a result, the wake-up time is

related to the time spent in the power-down mode: shorter

cycles result in proportionally shorter wake-up times. To restore

the device to full operation, approximately 0.5 ms is required when

using the recommended 1 ꢁF and 0.1 ꢁF decoupling capacitors

on the VREF pin and a 0.01 ꢁF capacitor on the GAIN pins.

Most of this time is dependent on the gain decoupling: higher

value decoupling capacitors on the GAIN pins result in longer

wake-up times.

5.0ns/DIV

CH1 500mV/DIV Ω

CH2 500mV/DIV Ω

CH3 500mV/DIV Ω

Figure 64. LVDS Output Timing Example in ANSI-644 Mode (Default)

An example of the LVDS output using the ANSI-644 standard

(default) data eye and a time interval error (TIE) jitter histogram

with trace lengths of less than 24 inches on regular FR-4 material

is shown in Figure 65. Figure 66 shows an example of the trace

lengths exceeding 24 inches on regular FR-4 material. Notice

that the TIE jitter histogram reflects the decrease of the data eye

opening as the edge deviates from the ideal position; therefore,

the user must determine if the waveforms meet the timing budget

of the design when the trace lengths exceed 24 inches.

There are a number of other power-down options available

when using the SPI port interface. The user can individually

power down each channel or put the entire device into standby

mode. This allows the user to keep the internal PLL powered up

when fast wake-up times are required. The wake-up time is

slightly dependent on gain. To achieve a 1 ꢁs wake-up time

when the device is in standby mode, 0.8 V must be applied to

the GAIN pins. See Table 17 for more details on using these

features.

Additional SPI options allow the user to further increase the

internal termination and therefore increase the current of all

eight outputs in order to drive longer trace lengths (see Figure 67).

Even though this produces sharper rise and fall times on the

data edges, is less prone to bit errors, and improves frequency

distribution (see Figure 67), the power dissipation of the DRVDD

supply increases when this option is used.

Digital Outputs and Timing

The AD9273 differential outputs conform to the ANSI-644 LVDS

standard by default at power-up. This can be changed to a low

power, reduced-signal option similar to the IEEE 1596.3 standard

by using the SDIO pin or via the SPI. This LVDS standard can

further reduce the overall power dissipation of the device by

approximately 36 mW. See the SDIO Pin section or Table 17 for

more information.

In cases that require increased driver strength to the DCO and

FCO outputs because of load mismatch, Register 0x15 allows

the user to double the drive strength. To do this, set Bit 0 in

Register 0x15. Note that this feature cannot be used with Bit 4

and Bit 5 in Register 0x15 because these bits take precedence

over this feature. See Table 17 for more details.

The LVDS driver current is derived on chip and sets the output

current at each output equal to a nominal 3.5 mA. A 100 Ω differ-

ential termination resistor placed at the LVDS receiver inputs

results in a nominal 350 mV swing at the receiver.

Rev. B | Page 33 of 48

AD9273

600

400

300

EYE: ALL BITS

ULS: 2398/2398

ULS: 2399/2399

400

200

100

0

–100

–200

–400

–600

–100

–200

–300

–400

–1.5ns

–1.0ns –0.5ns

0ns

0.5ns

1.0ns

1.5ns

–1.5ns

–1.0ns –0.5ns

0ns

0.5ns

1.0ns

1.5ns

25

20

25

20

15

10

5

15

10

5

0

–200ps

–100ps

0ps

100ps

200ps

–200ps

–100ps

0ps

100ps

200ps

Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

of Less than 24 Inches on Standard FR-4

Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

of Greater than 24 Inches on Standard FR-4

Rev. B | Page 34 of 48

AD9273

600

400

200

The format of the output data is offset binary by default. An

EYE: ALL BITS

ULS: 2396/2396

example of the output coding format can be found in Table 11.

To change the output data format to twos complement, see the

Memory Map section.

Table 11. Digital Output Coding

(VIN+) − (VIN−),

Code Input Span = 2 V p-p (V)

Digital Output Offset Binary

(D11 ... D0)

0

4095

2048

2047

0

+1.00

1111 1111 1111

1000 0000 0000

0111 1111 1111

0000 0000 0000

–200

0.00

−0.000488

−1.00

–400

–600

–1.5ns

–1.0ns –0.5ns

0ns

0.5ns

1.0ns

1.5ns

Data from each ADC is serialized and provided on a separate

channel. The data rate for each serial stream is equal to 12 bits

times the sample clock rate, with a maximum of 600 Mbps

(12 bits × 50 MSPS = 600 Mbps). The lowest typical conversion

rate is 10 MSPS, but the PLL can be set up for encode rates as

low as 5 MSPS via the SPI if lower sample rates are required for

a specific application. See Table 17 for details on enabling this

feature.

25

20

15

10

5

Two output clocks are provided to assist in capturing data from

the AD9273. DCO is used to clock the output data and is equal

to six times the sampling clock rate. Data is clocked out of the

AD9273 and must be captured on the rising and falling edges of

the DCO that supports double data rate (DDR) capturing. The

frame clock output (FCO ) is used to signal the start of a new

output byte and is equal to the sampling clock rate. See the

timing diagram shown in Figure 2 for more information.

0

–200ps

–100ps

0ps

100ps

200ps

Figure 67. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination

Resistor and Trace Lengths of Greater than 24 Inches on Standard FR-4

Table 12. Flexible Output Test Modes

Output Test Mode

Bit Sequence

Subject to Data

Format Select

Pattern Name

Off (default)

Digital Output Word 1

N/A

Digital Output Word 2

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

N/A

Yes

No

Yes

No

Midscale short

+Full-scale short

−Full-scale short

Checkerboard output

PN sequence long

PN sequence short

One-/zero-word toggle

User input

1000 0000 0000

1111 1111 1111

0000 0000 0000

1010 1010 1010

N/A

1000 0000 0000

1111 1111 1111

0000 0000 0000

0101 0101 0101

N/A

0000 0000 0000

Register 0x1B and Register 0x1C

N/A

1111 1111 1111

Register 0x19 and Register 0x1A

1010 1010 1010

0000 0011 1111

1000 0000 0000

1010 0011 0011

1-/0-bit toggle

1× sync

One bit high

1100

Mixed bit frequency

Rev. B | Page 35 of 48

AD9273

When using the serial port interface (SPI), the DCO phase can

be adjusted in 60° increments relative to the data edge. This

enables the user to refine system timing margins if required.

The default DCO timing, as shown in Figure 2, is 90° relative

to the output data edge.

Consult the Memory Map section for information on how to change

these additional digital output timing features through the SPI.

SDIO Pin

This pin is required to operate the SPI. It has an internal 30 kΩ

pull-down resistor that pulls this pin low and is only 1.8 V

tolerant. If applications require that this pin be driven from a

3.3 V logic level, insert a 1 kΩ resistor in series with this pin to

limit the current.

An 8-, 10-, and 14-bit serial stream can also be initiated from the

SPI. This allows the user to implement different serial streams and

to test the device’s compatibility with lower and higher resolution

systems. When changing the resolution to an 8- or 10-bit serial

stream, the data stream is shortened. When using the 14-bit

option, the data stream stuffs two 0s at the end of the normal

14-bit serial data.

SCLK Pin

This pin is required to operate the SPI port interface. It has an

internal 30 kΩ pull-down resistor that pulls this pin low and is

both 1.8 V and 3.3 V tolerant.

When the SPI is used, all of the data outputs can also be inverted

from their nominal state. This is not to be confused with inverting

the serial stream to an LSB-first mode. In default mode, as shown

in Figure 2, the MSB is represented first in the data output serial

stream. However, this can be inverted so that the LSB is repre-

sented first in the data output serial stream (see Figure 3).

CSB Pin

This pin is required to operate the SPI port interface. It has an

internal 70 kΩ pull-up resistor that pulls this pin high and is both

1.8 V and 3.3 V tolerant.

RBIAS Pin

There are 12 digital output test pattern options available that

can be initiated through the SPI. This is a useful feature when

validating receiver capture and timing. Refer to Table 12 for the

output bit sequencing options available. Some test patterns have

two serial sequential words and can be alternated in various

ways, depending on the test pattern chosen. Note that some

patterns may not adhere to the data format select option. In

addition, customer user patterns can be assigned in the 0x19,

0x1A, 0x1B, and 0x1C register addresses. All test mode options

except PN sequence short and PN sequence long can support

8- to 14-bit word lengths in order to verify data capture to the

receiver.

To set the internal core bias current of the ADC, place a resistor

nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using

other than the recommended 10.0 kΩ resistor for RBIAS degrades

the performance of the device. Therefore, it is imperative that at

least a 1% tolerance on this resistor be used to achieve consistent

performance.

Voltage Reference

A stable and accurate 0.5 V voltage reference is built into the

AD9273. This is gained up internally by a factor of 2, setting

VREF to 1.0 V, which results in a full-scale differential input

span of 2.0 V p-p for the ADC. VREF is set internally by

default, but the VREF pin can be driven externally with a 1.0 V

reference to achieve more accuracy. However, this device does

not support ADC full-scale ranges below 2.0 V p-p.

The PN sequence short pattern produces a pseudorandom

bit sequence that repeats itself every 2⁹− 1 bits, or 511 bits. A

description of the PN sequence and how it is generated can be

found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The

only difference is that the starting value is a specific value instead

of all 1s (see Table 13 for the initial values).

When applying the decoupling capacitors to the VREF pin, use

ceramic low-ESR capacitors. These capacitors should be close to

the reference pin and on the same layer of the PCB as the

AD9273. The VREF pin should have both a 0.1 ꢁF capacitor

and a 1 ꢁF capacitor connected in parallel to the analog ground.

These capacitor values are recommended for the ADC to

properly settle and acquire the next valid sample.

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 2²³− 1 bits, or 8,388,607 bits.

A description of the PN sequence and how it is generated can

be found in Section 5.6 of the ITU-T 0.150 (05/96) standard.

The only differences are that the starting value is a specific value

instead of all 1s and the AD9273 inverts the bit stream with

relation to the ITU standard (see Table 13 for the initial values).

The reference settings can be selected using the SPI. The settings

allow two options: using the internal reference or using an external

reference. The internal reference option is the default setting and

has a resulting differential span of 2 V p-p.

Table 13. PN Sequence

Table 14. SPI-Selectable Reference Settings

Initial

Value

First Three Output Samples

(MSB First)

Sequence

Resulting Resulting Differential

SPI-Selected Mode

VREF (V)

Span (V p-p)

2 × external reference

2.0

PN Sequence Short 0x0DF

PN Sequence Long 0x29B80A 0x591, 0xFD7, 0x0A3

0xDF9, 0x353, 0x301

External Reference

Internal Reference (Default) 1.0

N/A

Rev. B | Page 36 of 48

AD9273

Power and Ground Recommendations

the AD9273 exposed paddle, Pin 0. The copper plane should

have several vias to achieve the lowest possible resistive thermal

path for heat dissipation to flow through the bottom of the PCB.

These vias should be filled or plugged with nonconductive epoxy.

When connecting power to the AD9273, it is recommended

that two separate 1.8 V supplies be used: one for analog (AVDD)

and one for digital (DRVDD). If only one 1.8 V supply is

available, it should be routed to the AVDD1 first and then

tapped off and isolated with a ferrite bead or a filter choke

preceded by decoupling capacitors for the DRVDD. The user

should employ several decoupling capacitors on all supplies to

cover both high and low frequencies. These should be located

close to the point of entry at the PC board level and close to the

parts with minimal trace lengths.

To maximize the coverage and adhesion between the device and

PCB, partition the continuous copper pad by overlaying a silk-

screen or solder mask to divide this into several uniform sections.

This ensures several tie points between the two during the reflow

process. Using one continuous plane with no partitions only

guarantees one tie point between the AD9273 and PCB. See

Figure 68 for a PCB layout example. For more detailed infor-

mation on packaging and for more PCB layout examples, see

the AN-772 Application Note.

A single PC board ground plane should be sufficient when

using the AD9273. With proper decoupling and smart parti-

tioning of the PC board’s analog, digital, and clock sections,

optimum performance can be achieved easily.

SILKSCREEN PARTITION

PIN 1 INDICATOR

Exposed Paddle Thermal Heat Slug Recommendations

It is required that the exposed paddle on the underside of the

device be connected to a quiet analog ground to achieve the

best electrical and thermal performance of the AD9273. An

exposed continuous copper plane on the PCB should mate to

Figure 68. Typical PCB Layout

Rev. B | Page 37 of 48

AD9273

SERIAL PORT INTERFACE (SPI)

The AD9273 serial port interface allows the user to configure

the signal chain for specific functions or operations through a

structured register space provided inside the chip. This offers

the user added flexibility and customization depending on the

application. Addresses are accessed via the serial port and can

be written to or read from via the port. Memory is organized

into bytes that can be further divided down into fields, as doc-

umented in the Memory Map section. Detailed operational

information can be found in the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

In addition to the operation modes, the SPI port can be

configured to operate in different manners. For applications

that do not require a control port, the CSB line can be tied and

held high. This places the remainder of the SPI pins in their

secondary mode, as defined in the SDIO Pin and SCLK Pin

sections. CSB can also be tied low to enable 2-wire mode. When

CSB is tied low, SCLK and SDIO are the only pins required for

communication. Although the device is synchronized during

power-up, caution must be exercised when using this mode to

ensure that the serial port remains synchronized with the CSB

line. When operating in 2-wire mode, it is recommended to use

a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB

line, streaming mode can be entered but not exited.

There are three pins that define the serial port interface (SPI):

the SCLK, SDIO, and CSB pins. The SCLK (serial clock) is used

to synchronize the read and write data presented to the device.

The SDIO (serial data input/output) is a dual-purpose pin that

allows data to be sent to and read from the device’s internal

memory map registers. The CSB (chip select bar) is an active

low control that enables or disables the read and write cycles

(see Table 15).

In addition to word length, the instruction phase determines if

the serial frame is a read or write operation, allowing the serial

port to be used to both program the chip and read the contents

of the on-chip memory. If the instruction is a readback operation,

performing a readback causes the serial data input/output (SDIO)

pin to change direction from an input to an output at the

appropriate point in the serial frame.

Table 15. Serial Port Pins

Function

Data can be sent in MSB- or LSB-first mode. MSB-first mode

is the default at power-up and can be changed by adjusting the

configuration register. For more information about this and

other features, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

SCLK

Serial clock. The serial shift clock input. SCLK is used to

synchronize serial interface reads and writes.

Serial data input/output. A dual-purpose pin. The typical

role for this pin is as an input or output, depending on

the instruction sent and the relative position in the

timing frame.

SDIO

CSB

HARDWARE INTERFACE

Chip select bar (active low). This control gates the read

and write cycles.

The pins described in Table 15 constitute the physical interface

between the user’s programming device and the serial port of

the AD9273. The SCLK and CSB pins function as inputs when

using the SPI interface. The SDIO pin is bidirectional, functioning

as an input during write phases and as an output during readback.

The falling edge of the CSB in conjunction with the rising edge of

the SCLK determines the start of the framing sequence. During an

instruction phase, a 16-bit instruction is transmitted, followed by

one or more data bytes, which is determined by Bit Field W0 and

Bit Field W1. An example of the serial timing and its definitions

can be found in Figure 70 and Table 16.

In cases where multiple SDIO pins share a common connection,

care should be taken to ensure that proper V_OHlevels are met.

Figure 69 shows the number of SDIO pins that can be connected

together, assuming the same load as the AD9273, as well as the

resulting V_OHlevel.

During normal operation, CSB is used to signal to the device

that SPI commands are to be received and processed. When

CSB is brought low, the device processes SCLK and SDIO to

process instructions. Normally, CSB remains low until the

communication cycle is complete. However, if connected to a

slow device, CSB can be brought high between bytes, allowing

older microcontrollers enough time to transfer data into shift

registers. CSB can be stalled when transferring one, two, or three

bytes of data. When W0 and W1 are set to 11, the device enters

streaming mode and continues to process data, either reading

or writing, until CSB is taken high to end the communication

cycle. This allows complete memory transfers without having

to provide additional instructtions. Regardless of the mode,

if CSB is taken high in the middle of any byte transfer, the SPI

state machine is reset and the device waits for a new instruction.

1.800

1.795

1.790

1.785

1.780

1.775

1.770

1.765

1.760

1.755

1.750

1.745

1.740

1.735

1.730

1.725

1.720

1.715

0

10

20

30

40

50

60

70

80

90

100

NUMBER OF SDIO PINS CONNECTED TOGETHER

Figure 69. SDIO Pin Loading

Rev. B | Page 38 of 48

AD9273

This interface is flexible enough to be controlled by either serial

PROMS or PIC mirocontrollers. This provides the user with

an alternative method, other than a full SPI controller, for

programming the device (see the AN-812 Application Note).

If the user chooses not to use the SPI interface, these pins serve

a dual function and are associated with secondary functions

when the CSB is strapped to AVDD during device power-up.

See the SDIO Pin and SCLK Pin sections for details on which

pin-strappable functions are supported on the SPI pins.

t_DS

t_HI

t_CLK

t_H

t_S

t_DH

t_LO

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 70. Serial Timing Details

Table 16. Serial Timing Definitions

Parameter

Minimum Timing (ns)

Description

t_DS

5

2

40

5

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the clock

t_DH

t_CLK

t_S

Setup time between CSB and SCLK

t_H

2

Hold time between CSB and SCLK

t_HI

t_LO

t_{EN_SDIO}

16

10

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge (not shown in Figure 70)

t_{DIS_SDIO}

10

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge (not shown in Figure 70)

Rev. B | Page 39 of 48

AD9273

MEMORY MAP

READING THE MEMORY MAP TABLE

RESERVED LOCATIONS

Undefined memory locations should not be written to except

when writing the default values suggested in this data sheet.

Addresses that have values marked as 0 should be considered

reserved and have a 0 written into their registers during power-up.

Each row in the memory map table has eight address locations.

The memory map is roughly divided into three sections: the

chip configuration register map (Address 0x00 to Address 0x02),

the device index and transfer register map (Address 0x04 to

Address 0xFF), and the ADC functions register map

(Address 0x08 to Address 0x2D).

DEFAULT VALUES

After a reset, critical registers are automatically loaded with

default values. These values are indicated in Table 17, where an

X refers to an undefined feature.

The leftmost column of the memory map indicates the register

address number, and the default value is shown in the second

rightmost column. The Bit 7 (MSB) column is the start of the

default hexadecimal value given. For example, Address 0x09,

the clock register, has a default value of 0x01, meaning that Bit 7

= 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0,

and Bit 0 = 1, or 0000 0001 in binary. This setting is the default

for the duty cycle stabilizer in the on condition. By writing a 0

to Bit 0 of this address followed by an 0x01 to the SW transfer

bit in Register 0xFF, the duty cycle stabilizer turns off. It is

important to follow each writing sequence with a write to the

SW transfer bit to update the SPI registers.

LOGIC LEVELS

An explanation of various registers follows: “bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly, “clear a bit” is synonymous with “bit is set to

Logic 0” or “writing Logic 0 for the bit.”

Caution

All registers except Register 0x00, Register 0x02, Register 0x04,

Register 0x05, and Register 0xFF are buffered with a master

slave latch and require writing to the transfer bit. For more

information on this and other functions, consult the AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

Rev. B | Page 40 of 48

AD9273

Table 17. AD9273 Memory Map Register

Addr.

Bit 7

Bit 0

Default Default Notes/

(Hex) Register Name

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Value

Comments

Chip Configuration Registers

00

CHIP_PORT_CONFIG

0

LSB first

1 = on

Soft

reset

1

Soft

reset

LSB first

1 = on

0

0x18

The nibbles

should be

0 = off

(default)

1 = on

0 = off

(default)

1 = on

0 = off

(default)

0 = off

(default)

mirrored so that

LSB- or MSB-first

mode is set cor-

rectly regardless

of shift mode.

01

02

CHIP_ID

Chip ID Bits[7:0]

(AD9273 = 0x2F, default)

Read

only

Default is unique

chip ID, different

for each device.

This is a read-only

register.

CHIP_GRADE

X

Child ID[5:4]

X

0x00

Child ID used to

differentiate

graded devices.

(identify device

variants of Chip ID)

00 = 40 MSPS

(default)

01 = 25 MSPS

10 = 50 MSPS

Device Index and Transfer Registers

04

05

FF

DEVICE_INDEX_2

DEVICE_INDEX_1

DEVICE_UPDATE

X

Data

0x0F

0x00

Bits are set to

Channel Channel Channel Channel

H

1 = on

(default)

0 = off

determine which

on-chip device

receives the next

write command.

G

F

E

1 = on

(default)

0 = off

1 = on

(default)

0 = off

1 = on

(default)

0 = off

Clock

Data

Bits are set to

Channel Channel Channel Channel Channel Channel

DCO

1 = on

0 = off

(default)

determine which

on-chip device

receives the next

write command.

FCO

1 = on

0 = off

D

C

B

A

1 = on

(default)

1 = on

(default)

0 = off

1 = on

(default)

0 = off

1 = on

(default)

0 = off

(default) 0 = off

X

SW

Synchronously

transfers data

from the master

shift register to

the slave.

transfer

1 = on

0 = off

(default)

ADC Functions Registers

08

09

0D

Modes

X

0

Internal power-down mode

000 = chip run (default)

001 = full power-down

010 = standby

011 = reset

100 = CW mode (TGC PDWN)

0x00

0x01

0x00

Determines

various generic

modes of chip

operation

(global).

Clock

X

Duty

cycle

Turns the internal

duty cycle stabilizer

on and off

stabilizer

1 = on

(default)

0 = off

(global).

TEST_IO

User test mode

00 = off (default)

01 = on, single

alternate

Reset PN Reset PN Output test mode—see Table 12

long

gen

1 = on

0 = off

When this register

is set, the test data

is placed on the

output pins in

place of normal

data. (Local, expect

for PN sequence.)

short

gen

1 = on

0 = off

0000 = off (default)

0001 = midscale short

0010 = +FS short

10 = on, single once

11 = on, alternate once (default) (default) 0100 = checkerboard output

0101 = PN sequence long

0011 = −FS short

0110 = PN sequence short

0111 = one-/zero-word toggle

1000 = user input

1001 = 1-/0-bit toggle

1010 = 1× sync

1011 = one bit high

1100 = mixed bit frequency (format

determined by the OUTPUT_MODE register)

Rev. B | Page 41 of 48

AD9273

Addr.

Bit 7

Bit 0

Default Default Notes/

(Hex) Register Name

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Value

Comments

0F

FLEX_CHANNEL_

INPUT

Filter cutoff frequency control

0000 = 1.3 × 1/3 × f_SAMPLE

0001 = 1.2 × 1/3 × f_SAMPLE

0010 = 1.1 × 1/3 × f_SAMPLE

0011 = 1.0 × 1/3 × f_SAMPLE(default)

0100 = 0.9 × 1/3 × f_SAMPLE

0101 = 0.8 × 1/3 × f_SAMPLE

0110 = 0.7 × 1/3 × f_SAMPLE

1000 = 1.3 × 1/4.5 × f_SAMPLE

1001 = 1.2 × 1/4.5 × f_SAMPLE

1010 = 1.1 × 1/4.5 × f_SAMPLE

1011 = 1.0 × 1/4.5 × f_SAMPLE

1100 = 0.9 × 1/4.5 × f_SAMPLE

1101 = 0.8 × 1/4.5 × f_SAMPLE

1110 = 0.7 × 1/4.5 × f_SAMPLE

X

0x30

Antialiasing filter

cutoff (global).

10

11

FLEX_OFFSET

FLEX_GAIN

X

6-bit LNA offset adjustment

10 0000 = LNA bias high, mid-high, mid-low (default)

10 0001 = LNA bias low

0x20

0x06

LNA force offset

correction

(local).

X

PGA gain

LNA gain

LNA and PGA

gain adjustment

(global).

00 = 21 dB

01 = 24 dB (default)

10 = 27 dB

00 = 15.6 dB

01 = 17.9 dB

10 = 21.3 dB

(default)

11 = 30 dB

12

14

BIAS_CURRENT

OUTPUT_MODE

X

1

X

LNA bias

00 = high

01 = mid-high

(default)

10 = mid-low

11 = low

0x08

0x00

LNA bias current

adjustment

(global).

0 = LVDS

ANSI-644

(default)

1 = LVDS

low power,

(IEEE

X

Output

invert

1 = on

0 = off

(default)

00 = offset binary

(default)

01 = twos

Configures the

outputs and the

format of the data

(Bits[7:3] and

Bits[1:0] are global;

Bit 2 is local).

complement

1596.3

similar)

15

OUTPUT_ADJUST

X

Output driver

termination

00 = none (default)

01 = 200 Ω

10 = 100 Ω

11 = 100 Ω

X

DCO

and

FCO

2× drive

strength

1 = on

0 = off

(default)

0x00

Determines LVDS

or other output

properties. Pri-

marily functions to

set the LVDS span

and common-

mode levels in

place of an

external resistor

(Bits[7:1] are global;

Bit 0 is local).

16

OUTPUT_PHASE

X

0011 = output clock phase adjust

(0000 through 1010)

0x03

On devices that

utilize global

0000 = 0° relative to data edge

0001 = 60° relative to data edge

0010 = 120° relative to data edge

clock divide,

determines which

phase of the

divider output is

used to supply

the output clock.

Internal latching

is unaffected.

0011 = 180° relative to data edge (default)

0100 = 240° relative to data edge

0101 = 300° relative to data edge

0110 = 360° relative to data edge

0111 = 420° relative to data edge

1000 = 480° relative to data edge

1001 = 540° relative to data edge

1010 = 600° relative to data edge

1011 to 1111 = 660° relative to data edge

18

FLEX_VREF

X

0 =

X

0x00

Select internal

reference

(recommended

default) or external

reference (global).

internal

reference

1 =

external

reference

Rev. B | Page 42 of 48

AD9273

Addr.

Bit 7

Bit 0

Default Default Notes/

(Hex) Register Name

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Value

Comments

19

1A

1B

1C

21

USER_PATT1_LSB

USER_PATT1_MSB

USER_PATT2_LSB

USER_PATT2_MSB

SERIAL_CONTROL

B7

B6

B5

B4

B3

B2

B1

B0

B8

B0

B8

0x00

User-defined

pattern, 1 LSB

(global).

B15

B7

B14

B6

B13

B5

B12

B4

B11

B3

B10

B2

B9

B1

B9

0x00

User-defined

pattern, 1 MSB

(global).

User-defined

pattern, 2 LSB

(global).

B15

B14

X

B13

X

B12

X

B11

B10

User-defined

pattern, 2 MSB

(global).

LSB first

1 = on

0 = off

<10

MSPS,

low

encode

rate

000 = 12 bits (default, normal

bit stream)

001 = 8 bits

010 = 10 bits

011 = 12 bits

Serial stream

control. Default

causes MSB first

and the native bit

stream (global).

(default)

mode

1 = on

0 = off

(default)

100 = 14 bits

22

2B

SERIAL_CH_STAT

FLEX_FILTER

X

Channel Channel 0x00

Used to power

down individual

sections of a

output

reset

power-

down

1 = on

0 = off

1 = on

0 = off

converter (local).

(default) (default)

Enable

High-pass filter cutoff

0000 = f_LP/20.7

0001 = f_LP/11.5

0010 = f_LP/7.9

0011 = f_LP/6.0

0100 = f_LP/4.9

0101 = f_LP/4.1

0110 = f_LP/3.5

0111 = f_LP/3.1

0x00

Filter cutoff

(global). (f_LP=

low-pass filter

cutoff frequency.)

automatic

low-pass

tuning

1 = on

(self-

clearing)

2C

2D

ANALOG_INPUT

X

LOSW-x connect

00 = high-Z

01 = (−)LNA output

10 = (+)LNA output

11 = high-Z

0x00

LNA active

termination/input

impedance

(global).

CROSS_POINT_

SWITCH

Crosspoint switch enable

Crosspoint switch

enable (local).

10 0000 = CWD0 (differential)

10 0001 = CWD1 (differential)

10 0010 = CWD2 (differential)

10 0011 = CWD3 (differential)

10 0100 = CWD4 (differential)

10 0101 = CWD5 (differential)

10 0110 = CWD6 (differential)

10 0111 = CWD7 (differential)

11 0000 = CWD0+ (single ended)

11 0001 = CWD1+ (single ended)

11 0010 = CWD2+ (single ended)

11 0011 = CWD3+ (single ended)

11 0100 = CWD4+ (single ended)

11 0101 = CWD5+ (single ended)

11 0110 = CWD6+ (single ended)

11 0111 = CWD7+ (single ended)

11 1000 = CWD0− (single ended)

11 1001 = CWD1− (single ended)

11 1010 = CWD2− (single ended)

11 1011 = CWD3− (single ended)

11 1100 = CWD4− (single ended)

11 1101 = CWD5− (single ended)

11 1110 = CWD6− (single ended)

11 1111 = CWD7− (single ended)

0x xxxx = power down CW channel (default)

Rev. B | Page 43 of 48

AD9273

OUTLINE DIMENSIONS

16.00 BSC SQ

1.20

MAX

0.75

0.60

0.45

14.00 BSC SQ

76

75

100

76

75

100

1

PIN 1

EXPOSED

PAD

9.50 SQ

TOP VIEW

(PINS DOWN)

0° MIN

1.05

1.00

0.95

0.20

0.09

7°

BOTTOM VIEW

(PINS UP)

51

25

26

50

26

3.5°

0°

0.50 BSC

LEAD PITCH

0.27

0.22

0.17

VIEW A

0.15

0.05

SEATING

PLANE

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.08 MAX

COPLANARITY

SECTION OF THIS DATA SHEET.

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD

Figure 71. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-100-3)

Dimensions shown in millimeters

A1 CORNER

INDEX AREA

10.10

10.00

9.90

9

7

3

1

11

5

12

10

8

6

4

2

A

B

C

D

E

F

G

H

J

BALL A1

INDICATOR

8.80

BSC SQ

TOP VIEW

K

L

M

BOTTOM VIEW

DETAIL A

0.80 BSC

DETAIL A

1.40 MAX

1.00

0.85

0.43 MAX

0.25 MIN

COPLANARITY

0.12 MAX

0.55

0.50

0.45

SEATING

PLANE

BALL DIAMETER

COMPLIANT WITH JEDEC STANDARDS MO-205-AC.

Figure 72. 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]

(BC-144-1)

Dimensions shown in millimeters

Rev. B | Page 44 of 48

AD9273

ORDERING GUIDE

Temperature

Range

Package

Option

Model

Package Description

AD9273BSVZ-50¹

AD9273BSVZRL-50¹

AD9273BSVZ-40¹

AD9273BSVZRL-40¹

AD9273BSVZ-25¹

AD9273BSVZRL-25¹

AD9273BBCZ-25¹

AD9273BBCZ-40¹

AD9273BBCZ-50¹

AD9273-50EBZ¹

−40°C to +85°C

100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel

100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel

100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel

144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]

Evaluation Board, 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

SV-100-3

BC-144-1

¹Z = RoHS Compliant Part.

Rev. B | Page 45 of 48

AD9273

NOTES

Rev. B | Page 46 of 48

AD9273

NOTES

Rev. B | Page 47 of 48

AD9273

NOTES

registered trademarks are the property of their respective owners.

D07030-0-7/09(B)

Rev. B | Page 48 of 48


型号：	AD9273BSVZ-40
厂家：	ADI
描述：	Octal LNA/VGA/AAF/ADC and Crosspoint Switch
文件：	总49页 (文件大小：706K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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