AD9280ARSRL [ADI]
Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D Converter; 完整的8位， 32 MSPS ， 95毫瓦的CMOS A / D转换器
| 型号： | AD9280ARSRL |
| 厂家： | 
ADI |
| 描述： | Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D Converter |
| 文件： | 总24页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete 8-Bit, 32 MSPS, 95 mW
CMOS A/D Converter
a
AD9280
FEATURES
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal (OTR) indicates an over-
flow condition which can be used with the most significant bit
to determine low or high overflow.
CMOS 8-Bit 32 MSPS Sampling A/D Converter
Pin-Compatible with AD876-8
Power Dissipation: 95 mW (3 V Supply)
Operation Between +2.7 V and +5.5 V Supply
Differential Nonlinearity: 0.2 LSB
Power-Down (Sleep) Mode
Three-State Outputs
Out-of-Range Indicator
Built-In Clamp Function (DC Restore)
Adjustable On-Chip Voltage Reference
IF Undersampling to 135 MHz
The AD9280 can operate with a supply range from +2.7 V to
+5.5 V, ideally suiting it for low power operation in high speed
applications.
The AD9280 is specified over the industrial (–40°C to +85°C)
temperature range.
PRODUCT HIGHLIGHTS
Low Power
PRODUCT DESCRIPTION
The AD9280 is a monolithic, single supply, 8-bit, 32 MSPS
analog-to-digital converter with an on-chip sample-and-hold
amplifier and voltage reference. The AD9280 uses a multistage
differential pipeline architecture at 32 MSPS data rates and
guarantees no missing codes over the full operating temperature
range.
The AD9280 consumes 95 mW on a 3 V supply (excluding the
reference power). In sleep mode, power is reduced to below
5 mW.
Very Small Package
The AD9280 is available in a 28-lead SSOP package.
Pin Compatible with AD876-8
The AD9280 is pin compatible with the AD876-8, allowing
older designs to migrate to lower supply voltages.
The input of the AD9280 has been designed to ease the devel-
opment of both imaging and communications systems. The user
can select a variety of input ranges and offsets and can drive the
input either single-ended or differentially.
300 MHz Onboard Sample-and-Hold
The versatile SHA input can be configured for either single-
ended or differential inputs.
The sample-and-hold amplifier (SHA) is equally suited for both
multiplexed systems that switch full-scale voltage levels in suc-
cessive channels and sampling single-channel inputs at frequen-
cies up to and beyond the Nyquist rate. AC-coupled input
signals can be shifted to a predetermined level, with an onboard
clamp circuit. The dynamic performance is excellent.
Out-of-Range Indicator
The OTR output bit indicates when the input signal is beyond
the AD9280’s input range.
Built-In Clamp Function
Allows dc restoration of video signals.
The AD9280 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy and
temperature drift requirements of the application.
FUNCTIONAL BLOCK DIAGRAM
CLAMP
IN
DRVDD
CLAMP
CLK
AVDD
STBY
SHA
GAIN
SHA
GAIN
SHA
GAIN
SHA
GAIN
SHA
MODE
VINA
A/D
REFTF
REFTS
THREE-
STATE
D/A
A/D
D/A
D/A
A/D
D/A
A/D
A/D
CORRECTION LOGIC
OUTPUT BUFFERS
REFBS
REFBF
OTR
VREF
D7 (MSB)
D0 (LSB)
AD9280
1V
REFSENSE
AVSS
DRVSS
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input
AD9280–SPECIFICATIONS Span from 0.5 V to 2.5 V, External Reference, TMIN to TMAX unless otherwise noted)
Parameter
Symbol
Min
Typ
Max
Units
Bits
Condition
RESOLUTION
CONVERSION RATE
8
FS
32
MHz
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
Offset Error
DNL
INL
EZS
±0.2
±0.3
±0.2
±1.2
±1.0
±1.5
±1.8
±3.9
LSB
LSB
% FSR
% FSR
REFTS = 2.5 V, REFBS = 0.5 V
Gain Error
EFS
REFERENCE VOLTAGES
Top Reference Voltage
Bottom Reference Voltage
Differential Reference Voltage
Reference Input Resistance1
REFTS
REFBS
1
AVDD
AVDD – 1 V
V p-p
V
GND
2
10
4.2
kΩ
kΩ
REFTS, REFBS: MODE = AVDD
Between REFTF & REFBF: MODE = AVSS
ANALOG INPUT
Input Voltage Range
Input Capacitance
AIN
CIN
tAP
tAJ
BW
REFBS
REFTS
V
REFBS Min = GND: REFTS Max = AVDD
Switched
1
4
2
pF
ns
ps
Aperture Delay
Aperture Uncertainty (Jitter)
Input Bandwidth (–3 dB)
Full Power (0 dB)
300
43
MHz
µA
DC Leakage Current
Input = ±FS
INTERNAL REFERENCE
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2 V Mode)
Load Regulation (1 V Mode)
VREF
VREF
1
±10
2
V
mV
V
REFSENSE = VREF
±25
REFSENSE = GND
1 mA Load Current
0.5
2
mV
POWER SUPPLY
Operating Voltage
AVDD
DRVDD
IAVDD
PD
2.7
2.7
3
3
31.7
95
4
5.5
5.5
36.7
110
V
V
mA
mW
mW
Supply Current
Power Consumption
Power-Down
AVDD = 3 V, MODE = AVSS
AVDD = DRVDD = 3 V, MODE = AVSS
STBY = AVDD, MODE and CLOCK
= AVSS
Gain Error Power Supply Rejection
PSRR
1
% FS
DYNAMIC PERFORMANCE (AIN = 0.5 dBFS)
Signal-to-Noise and Distortion
f = 3.58 MHz
f = 16 MHz
Effective Bits
f = 3.58 MHz
f = 16 MHz
Signal-to-Noise
f = 3.58 MHz
SINAD
46.4
47.8
49
48
dB
dB
7.8
7.7
Bits
Bits
SNR
49
48
dB
dB
f = 16 MHz
Total Harmonic Distortion
f = 3.58 MHz
f = 16 MHz
Spurious Free Dynamic Range
f = 3.58 MHz
f = 16 MHz
THD
SFDR
–62
–58
–49.5
51.4
dB
dB
66
61
dB
dB
Differential Phase
Differential Gain
DP
DG
0.2
0.08
Degree NTSC 40 IRE Mod Ramp
%
REV. D
–2–
AD9280
Parameter
Symbol
Min
Typ
Max
Units
Condition
DIGITAL INPUTS
High Input Voltage
Low Input Voltage
VIH
VIL
2.4
V
V
0.3
DIGITAL OUTPUTS
High-Z Leakage
Data Valid Delay
Data Enable Delay
Data High-Z Delay
IOZ
tOD
tDEN
tDHZ
–10
+10
µA
ns
ns
ns
Output = GND to VDD
CL = 20 pF
25
25
13
LOGIC OUTPUT (with DRVDD = 3 V)
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 µA)
VOH
VOH
VOL
VOL
+2.95
+2.80
V
V
V
V
+0.4
+0.05
LOGIC OUTPUT (with DRVDD = 5 V)
High Level Output Voltage (IOH = 50 µA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 µA)
VOH
VOH
VOL
VOL
+4.5
+2.4
V
V
V
V
+0.4
+0.1
CLOCKING
Clock Pulsewidth High
Clock Pulsewidth Low
Pipeline Latency
tCH
tCL
14.7
14.7
ns
ns
Cycles
3
CLAMP
Clamp Error Voltage
EOC
±60
±80
mV
CLAMPIN = +0.5 V to +2.0 V,
RIN = 10 Ω
Clamp Pulsewidth
tCPW
2
µs
CIN = 1 µF (Period = 63.5 µs)
NOTES
1See Figures 1a and 1b.
Specifications subject to change without notice.
REFTS
10k⍀
10k⍀
AD9280
AD9280
REFTS
REFTF
REFBF
4.2k⍀
REFBS
MODE
0.4
؋
V DD
REFBS
MODE
AV
DD
a.
Figure 1. Equivalent Input Load
b.
REV. D
–3–
AD9280
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
With
Respect
to
Parameter
Min
Max
Units
ORDERING GUIDE
AVDD
DRVDD
AVSS
AVDD
MODE
CLK
Digital Outputs
AIN
AVSS
DRVSS
DRVSS
–0.3
–0.3
–0.3
+6.5
+6.5
+0.3
+6.5
AVDD + 0.3
AVDD + 0.3
DRVDD + 0.3 V
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
+150
V
V
V
V
V
V
Temperature
Range
Package
Description
Package
Option*
Model
DRVDD –6.5
AVSS
AVSS
DRVSS
AVSS
AVSS
AVSS
AVSS
AVSS
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
AD9280ARS
–40°C to +85°C 28-Lead SSOP
AD9280ARSRL –40°C to +85°C 28-Lead SSOP (Reel) RS-28
RS-28
AD9280-EB
Evaluation Board
V
V
V
V
V
°C
°C
*RS = Shrink Small Outline.
VREF
REFSENSE
REFTF, REFTB
REFTS, REFBS
Junction Temperature
Storage Temperature
Lead Temperature
10 sec
–65
+150
+300
°C
AVDD
DRVDD
AVDD
AVDD
AVDD
AVDD
AVSS
DRVSS
DRVSS
AVSS
AVSS
AVSS
AVSS
a. D0–D7, OTR
b. Three-State, Standby, Clamp
c. CLK
AVDD
AVDD
22
REFTF
REFTS
25
REFBS
AVDD
AVSS
AVSS
AVDD
AVDD
21
24
REFBF
AVSS
AVSS
AVSS
d. AIN
e. Reference
AVDD
AVDD
AVDD
AVDD
AVSS
AVSS
AVSS
AVSS
f. CLAMPIN
g. MODE
h. REFSENSE
i. VREF
Figure 2. Equivalent Circuits
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9280 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–4–
AD9280
PIN CONFIGURATION
28-Lead Wide Body (SSOP)
1
2
28
27
26
25
24
23
AVDD
AIN
AVSS
DRVDD
NC
3
VREF
REFBS
REFBF
MODE
4
NC
5
D0
AD9280
TOP VIEW
6
D1
(Not to Scale)
7
D2
22 REFTF
8
21
D3
REFTS
9
20 CLAMPIN
D4
10
11
19
18
17
16
15
D5
CLAMP
D6
REFSENSE
STBY
12
13
14
D7
OTR
DRVSS
THREE-STATE
CLK
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
SSOP
Pin No.
Name
Description
1
2
3
AVSS
DRVDD
NC
Analog Ground
Digital Driver Supply
No Connect
4
NC
No Connect
5
D0
Bit 0
6
D1
Bit 1
7
D2
Bit 2
8
D3
Bit 3
9
D4
Bit 4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
D5
D6
D7
OTR
DRVSS
CLK
THREE-STATE
STBY
REFSENSE
CLAMP
CLAMPIN
REFTS
REFTF
MODE
REFBF
REFBS
VREF
AIN
Bit 5
Bit 6
Bit 7, Most Significant Bit
Out-of-Range Indicator
Digital Ground
Clock Input
HI: High Impedance State. LO: Normal Operation
HI: Power-Down Mode. LO: Normal Operation
Reference Select
HI: Enable Clamp Mode. LO: No Clamp
Clamp Reference Input
Top Reference
Top Reference Decoupling
Mode Select
Bottom Reference Decoupling
Bottom Reference
Internal Reference Output
Analog Input
Analog Supply
AVDD
REV. D
–5–
AD9280
DEFINITIONS OF SPECIFICATIONS
Offset Error
Integral Nonlinearity (INL)
The first transition should occur at a level 1 LSB above “zero.”
Offset is defined as the deviation of the actual first code transi-
tion from that point.
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB before the first code transi-
tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last
code transition. The deviation is measured from the center of
each particular code to the true straight line.
Gain Error
The first code transition should occur for an analog value 1 LSB
above nominal negative full scale. The last transition should
occur for an analog value 1 LSB below the nominal positive full
scale. Gain error is the deviation of the actual difference be-
tween first and last code transitions and the ideal difference
between the first and last code transitions.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
Pipeline Delay (Latency)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every rising edge.
(AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input
Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted)
Typical Characterization Curves
60
55
1.0
0.5
0
50
–0.5 AMPLITUDE
45
–6.0 AMPLITUDE
40
35
–0.5
–1.0
30
–20.0 AMPLITUDE
25
20
0
32
64
96
128
160
192
224
240
1.00E+05
1.00E+06
1.00E+07
1.00E+08
INPUT FREQUENCY – Hz
CODE OFFSET
Figure 3. Typical DNL
Figure 5. SNR vs. Input Frequency
60
55
50
45
40
35
30
1.0
0.5
–0.5 AMPLITUDE
–6.0 AMPLITUDE
0
–0.5
–1.0
–20.0 AMPLITUDE
25
20
0
32
64
96
128
160
192
224
240
1.00E+05
1.00E+06
1.00E+07
1.00E+08
INPUT FREQUENCY – Hz
CODE OFFSET
Figure 6. SINAD vs. Input Frequency
Figure 4. Typical INL
REV. D
–6–
AD9280
–30
–35
–40
105
100
95
–45
–50
–55
–60
–65
–20.0 AMPLITUDE
–6.0 AMPLITUDE
90
85
80
–0.5 AMPLITUDE
1.00E+07
–70
1.00E+05
75
0
5
10
15
20
25
30
35
40
1.00E+06
1.00E+08
CLOCK FREQUENCY – MHz
INPUT FREQUENCY – Hz
Figure 10. Power Consumption vs. Clock Frequency
(MODE = AVSS)
Figure 7. THD vs. Input Frequency
–80
–70
–60
–50
–40
–30
–20
–10
1M
1M
900k
800k
700k
600k
500k
400k
300k
200k
AIN = –0.5dBFS
100k
0
0
0
0
N–1
N
N+1
1.00E+06
1.00E+07
CLOCK FREQUENCY – Hz
1.00E+08
CODE
Figure 8. THD vs. Clock Frequency
Figure 11. Grounded Input Histogram
30
20
1.01
F
F
= 1MHz
= 32MHz
CLOCK = 32MHz
IN
S
10
FUND
1.009
0
–10
–20
1.008
1.007
1.006
–30
–40
–50
2nd
3rd
–60
–70
9th
5th
7th
8th
6th
–80
4th
–90
–100
–110
–120
1.005
–50
–30
–10
10
30
50
70
90
0E+0
4E+6
8E+6
12E+6
16E+6
SINGLE-TONE FREQUENCY DOMAIN
TEMPERATURE – °C
Figure 12. Single-Tone Frequency Domain
Figure 9. Voltage Reference Error vs. Temperature
REV. D
–7–
AD9280
0
APPLYING THE AD9280
THEORY OF OPERATION
–3
The AD9280 implements a pipelined multistage architecture to
achieve high sample rate with low power. The AD9280 distrib-
utes the conversion over several smaller A/D subblocks, refining
the conversion with progressively higher accuracy as it passes
the results from stage to stage. As a consequence of the distrib-
uted conversion, the AD9280 requires a small fraction of the
256 comparators used in a traditional flash type A/D. A sample-
and-hold function within each of the stages permits the first
stage to operate on a new input sample while the second, third
and fourth stages operate on the three preceding samples.
–6
–9
–12
–15
–18
–21
–24
1.0E+6
1.0E+7
1.0E+8
1.0E+9
OPERATIONAL MODES
FREQUENCY – Hz
The AD9280 is designed to allow optimal performance in a
wide variety of imaging, communications and instrumentation
applications, including pin compatibility with the AD876-8 A/D.
To realize this flexibility, internal switches on the AD9280 are
used to reconfigure the circuit into different modes. These modes
are selected by appropriate pin strapping. There are three parts
of the circuit affected by this modality: the voltage reference, the
reference buffer, and the analog input. The nature of the appli-
cation will determine which mode is appropriate: the descrip-
tions in the following sections, as well as Table I should assist in
selecting the desired mode.
Figure 13. Full Power Bandwidth
50
40
30
20
REFBS = 0.5V
REFTS = 2.5V
CLOCK = 32MHz
10
0
–10
–20
–30
–40
–50
0
0.5
1.0
1.5
2.0
2.5
3.0
INPUT VOLTAGE – V
Figure 14. Input Bias Current vs. Input Voltage
Table I. Mode Selection
Input
Connect
Input
Span
MODE
Pin
REFSENSE
Pin
Modes
REF
REFTS
REFBS Figure
TOP/BOTTOM AIN
AIN
1 V
2 V
AVDD
AVDD
Short REFSENSE, REFTS and VREF Together
AGND Short REFTS and VREF Together
AGND
AGND
18
19
CENTER SPAN AIN
AIN
1 V
2 V
AVDD/2 Short VREF and REFSENSE Together
AVDD/2 AGND No Connect
AVDD/2 Short VREF and REFSENSE Together
AVDD/2
AVDD/2
AVDD/2 20
AVDD/2
Differential
AIN Is Input 1
1 V
AVDD/2
AVDD/2 29
REFTS and
REFBS Are
Shorted Together
for Input 2
2 V
AVDD/2 AGND
No Connect
No Connect
AVDD/2
AVDD/2
External Ref
AD876-8
AIN
2 V max AVDD
AVDD
Span = REFTS
21, 22
– REFBS (2 V max)
AGND
Short to
VREFTF
Short to 23
VREFBF
AIN
2 V
Float or AVDD
AVSS
No Connect
Short to
VREFTF
Short to 30
VREFBF
REV. D
–8–
AD9280
SUMMARY OF MODES
VOLTAGE REFERENCE
1 V Mode the internal reference may be set to 1 V by connect-
ing REFSENSE and VREF together.
AIN
A/D
CORE
SHA
REFTS
2 V Mode the internal reference my be set to 2 V by connecting
REFSENSE to analog ground
AD9280
External Divider Mode the internal reference may be set to a
point between 1 V and 2 V by adding external resistors. See
Figure 16f.
REFBS
Figure 15. AD9280 Equivalent Functional Input Circuit
In single-ended operation, the input spans the range,
REFBS ≤ AIN ≤ REFTS
External Reference Mode enables the user to apply an exter-
nal reference to REFTS, REFBS and VREF pins. This mode
is attained by tying REFSENSE to VDD.
where REFBS can be connected to GND and REFTS con-
nected to VREF. If the user requires a different reference range,
REFBS and REFTS can be driven to any voltage within the
power supply rails, so long as the difference between the two is
between 1 V and 2 V.
REFERENCE BUFFER
Center Span Mode midscale is set by shorting REFTS and
REFBS together and applying the midscale voltage to that point
The MODE pin is set to AVDD/2. The analog input will swing
about that midscale point.
In differential operation, REFTS and REFBS are shorted to-
gether, and the input span is set by VREF,
Top/Bottom Mode sets the input range between two points.
The two points are between 1 V and 2 V apart. The Top/Bottom
Mode is enabled by tying the MODE pin to AVDD.
(REFTS – VREF/2) ≤ AIN ≤ (REFTS + VREF/2)
where VREF is determined by the internal reference or brought
in externally by the user.
ANALOG INPUT
Differential Mode is attained by driving the AIN pin as one
differential input, shorting REFTS and REFBS together and
driving them as the second differential input. The MODE pin
is tied to AVDD/2. Preferred mode for optimal distortion
performance.
The best noise performance may be obtained by operating the
AD9280 with a 2 V input range. The best distortion perfor-
mance may be obtained by operating the AD9280 with a 1 V
input range.
Single-Ended is attained by driving the AIN pin while the
REFTS and REFBS pins are held at dc points. The MODE pin is
tied to AVDD.
REFERENCE OPERATION
The AD9280 can be configured in a variety of reference topolo-
gies. The simplest configuration is to use the AD9280’s onboard
bandgap reference, which provides a pin-strappable option to
generate either a 1 V or 2 V output. If the user desires a refer-
ence voltage other than those two, an external resistor divider
can be connected between VREF, REFSENSE and analog
ground to generate a potential anywhere between 1 V and 2 V.
Another alternative is to use an external reference for designs
requiring enhanced accuracy and/or drift performance. A
third alternative is to bring in top and bottom references,
bypassing VREF altogether.
Single-Ended/Clamped (AC Coupled) the input may be
clamped to some dc level by ac coupling the input. This is done
by tying the CLAMPIN to some dc point and applying a pulse
to the CLAMP pin. MODE pin is tied to AVDD.
SPECIAL
AD876-8 Mode enables users of the AD876-8 to drop the
AD9280 into their socket. This mode is attained by floating or
grounding the MODE pin.
Figures 16d, 16e and 16f illustrate the reference and input ar-
chitecture of the AD9280. In tailoring a desired arrangement,
the user can select an input configuration to match drive circuit.
Then, moving to the reference modes at the bottom of the
figure, select a reference circuit to accommodate the offset and
amplitude of a full-scale signal.
INPUT AND REFERENCE OVERVIEW
Figure 16, a simplified model of the AD9280, highlights the
relationship between the analog input, AIN, and the reference
voltages, REFTS, REFBS and VREF. Like the voltages applied
to the resistor ladder in a flash A/D converter, REFTS and
REFBS define the maximum and minimum input voltages to
the A/D.
Table I outlines pin configurations to match user requirements.
The input stage is normally configured for single-ended opera-
tion, but allows for differential operation by shorting REFTS
and REFBS together to be used as the second input.
REV. D
–9–
AD9280
V*
MIDSCALE
MODE
REFTF
AD9280
AIN
+FS
–FS
AVDD/2
SHA
AD9280
AIN
MODE
(AVDD)
SHA
0.1F
+F/S RANGE
OBTAINED FROM
VREF PIN OR
10k⍀
0.1F
10k⍀
REFTF
10k⍀
10k⍀
EXTERNAL REF
REFTS
REFBS
A2
10F
0.1F
10k⍀
10k⍀
REFTS
REFBS
A/D
CORE
4.2k⍀
TOTAL
A2
0.1F
4.2k⍀
TOTAL
A/D
CORE
10F
INTERNAL
REF
0.1F
10k⍀
–F/S RANGE
OBTAINED FROM
VREF PIN OR
0.1F
REFBF
10k⍀
MIDSCALE OFFSET
VOLTAGE IS DERIVED
FROM INTERNAL OR
EXTERNAL REF
EXTERNAL REF
REFBF
* MAXIMUM MAGNITUDE OF V IS DETERMINED
BY INTERNAL REFERENCE
a. Top/Bottom Mode
b. Center Span Mode
MAXIMUM MAGNITUDE OF V
IS DETERMINED BY INTERNAL
REFERENCE AND TURNS RATIO
V
MODE
REFTF
AD9280
AIN
AVDD/2
SHA
AVDD/2
0.1F
10k⍀
10k⍀
10k⍀
REFTS
REFBS
A2
10F
0.1F
4.2k⍀
TOTAL
A/D
CORE
INTERNAL
REF
0.1F
10k⍀
REFBF
c. Differential Mode
VREF
(2V)
VREF
(1V)
A1
1.0F
0.1F
1V
A1
1V
10k⍀
REFSENSE
AVSS
1.0F
0.1F
REFSENSE
AVSS
10k⍀
AD9280
AD9280
d. 1 V Reference
e. 2 V Reference
VREF
(= 1 + R /R
)
A
B
A1
1V
VREF
A1
1.0F
0.1F
R
A
1V
REFSENSE
REFSENSE
AVDD
R
B
AD9280
AVSS
AD9280
INTERNAL 10K REF RESISTORS ARE
SWITCHED OPEN BY THE PRESENSE
OF R AND R
.
A
B
g. Internal Reference Disable
(Power Reduction)
f. Variable Reference
(Between 1 V and 2 V)
Figure 16.
–10–
REV. D
AD9280
The actual reference voltages used by the internal circuitry of
the AD9280 appear on REFTF and REFBF. For proper opera-
tion, it is necessary to add a capacitor network to decouple these
pins. The REFTF and REFBF should be decoupled for all
internal and external configurations as shown in Figure 17.
Figure 19 shows the single-ended configuration for 2 V p-p
operation. REFSENSE is connected to GND, resulting in a 2 V
reference output.
2V
0V
AIN
AD9280
MODE
REFTF
SHA
AVDD
0.1F
REFTF
10k⍀
10F
0.1F
AD9280
10k⍀
10k⍀
REFTS
REFBS
A2
REFBF
10F
0.1F
4.2k⍀
TOTAL
A/D
CORE
0.1F
0.1F
0.1F
10k⍀
Figure 17. Reference Decoupling Network
REFBF
VREF
A1
1V
Note: REFTF = reference top, force
REFBF = reference bottom, force
REFTS = reference top, sense
1.0F
0.1F
REF
SENSE
REFBS = reference bottom, sense
INTERNAL REFERENCE OPERATION
Figure 19. Internal Reference, 2 V p-p Input Span
(Top/Bottom Mode)
Figures 18, 19 and 20 show sample connections of the AD9280
internal reference in its most common configurations. (Figures
18 and 19 illustrate top/bottom mode while Figure 20 illustrates
center span mode). Figure 29 shows how to connect the AD9280
for 1 V p-p differential operation. Shorting the VREF pin
directly to the REFSENSE pin places the internal reference
amplifier, A1, in unity-gain mode and the resultant reference
output is 1 V. In Figure 18 REFBS is grounded to give an input
range from 0 V to 1 V. These modes can be chosen when the
supply is either +3 V or +5 V. The VREF pin must be bypassed to
AVSS (analog ground) with a 1.0 µF tantalum capacitor in
parallel with a low inductance, low ESR, 0.1 µF ceramic capacitor.
Figure 20 shows the single-ended configuration that gives the
good high frequency dynamic performance (SINAD, SFDR).
To optimize dynamic performance, center the common-mode
voltage of the analog input at approximately 1.5 V. Connect the
shorted REFTS and REFBS inputs to a low impedance 1.5 V
source. In this configuration, the MODE pin is driven to a volt-
age at midsupply (AVDD/2).
Maximum reference drive is 1 mA. An external buffer is re-
quired for heavier loads.
2V
1V
AIN
AD9280
MODE
SHA
AVDD/2
1V
0V
AIN
AD9280
MODE
REFTF
SHA
AVDD
0.1F
10k⍀
REFTF
0.1F
10k⍀
10k⍀
10k⍀
REFTS
REFBS
A2
+1.5V
10F
0.1F
10k⍀
10k⍀
REFTS
REFBS
4.2k⍀
TOTAL
A/D
CORE
A2
10F
0.1F
4.2k⍀
TOTAL
A/D
CORE
0.1F
10k⍀
REFBF
0.1F
10k⍀
VREF
A1
REFBF
1V
REF
SENSE
1.0F
0.1F
VREF
A1
1V
1.0F
0.1F
REF
SENSE
Figure 20. Internal Reference 1 V p-p Input Span
(Center Span Mode)
Figure 18. Internal Reference—1 V p-p Input Span
(Top/Bottom Mode)
REV. D
–11–
AD9280
EXTERNAL REFERENCE OPERATION
Figure 23a shows an example of the external references driving
the REFTF and REFBF pins that is compatible with the
AD876. REFTS is shorted to REFTF and driven by an external
4 V low impedance source. REFBS is shorted to REFBF and
driven by a 2 V source. The MODE pin is connected to GND
in this configuration.
Using an external reference may provide more flexibility and
improve drift and accuracy. Figures 21 through 23 show ex-
amples of how to use an external reference with the AD9280.
To use an external reference, the user must disable the internal
reference amplifier by connecting the REFSENSE pin to VDD.
The user then has the option of driving the VREF pin, or driv-
ing the REFTS and REFBS pins.
4V
VIN
The AD9280 contains an internal reference buffer (A2), that
simplifies the drive requirements of an external reference. The
external reference must simply be able to drive a 10 kΩ load.
2V
REFTS
4V
2V
REFTF
10F
0.1F
0.1F
AD9280
REFBF
Figure 21 shows an example of the user driving the top and bottom
references. REFTS is connected to a low impedance 2 V source
and REFBS is connected to a low impedance 1 V source. REFTS
and REFBS may be driven to any voltage within the supply as long
as the difference between them is between 1 V and 2 V.
0.1F
REFBS
VREF
REFSENSE
MODE
AVDD
2V
1V
AIN
AD9280
SHA
Figure 23a. External Reference—2 V p-p Input Span
0.1F
10k⍀
REFTF
10k⍀
10k⍀
REFTS
REFBS
REFTS
2V
1V
+5V
C4
A2
10F
0.1F
4.2k⍀
TOTAL
A/D
CORE
0.1F
6
5
8
7
REFTF
REF
SENSE
REFT
C3
0.1F
C6
0.1F
0.1F
10k⍀
AD9280
REFBS
AVDD
C2
10F
MODE
REFBF
C5
0.1F
2
3
6
Figure 21. External Reference Mode—1 V p-p Input Span
REFBF
REFB
C1
0.1F
4
Figure 22 shows an example of an external reference generating
2.5 V at the shorted REFTS and REFBS inputs. In this in-
stance, a REF43 2.5 V reference drives REFTS and REFBS. A
resistive divider generates a 1 V VREF signal that is buffered by
A3. A3 must be able to drive a 10 kΩ, capacitive load. Choose
this op amp based on noise and accuracy requirements.
Figure 23b. Kelvin Connected Reference Using the AD9280
STANDBY OPERATION
The ADC may be placed into a powered down (sleep) mode by
driving the STBY (standby) pin to logic high potential and
holding the clock at logic low. In this mode the typical power
drain is approximately 4 mW.
AD9280
3.0V
2.5V
2.0V
AIN
AVDD
AVDD
The ADC will “wake up” in 400 ns (typ) after the standby pulse
goes low.
REFTS
REFBS
0.1F
REFTF
10F
0.1F
0.1F
1.5k⍀
A3
CLAMP OPERATION
0.1F
10F
VREF
The AD9280ARS features an optional clamp circuit for dc
restoration of video or ac coupled signals. Figure 24 shows the
internal clamp circuitry and the external control signals needed
for clamp operation. To enable the clamp, apply a logic high to
the CLAMP pin. This will close the switch SW1. The clamp
amplifier will then servo the voltage at the AIN pin to be equal
to the clamp voltage applied at the CLAMPIN pin. After the
desired clamp level is attained, SW1 is opened by taking
CLAMP back to a logic low. Ignoring the droop caused by the
input bias current, the input capacitor CIN will hold the dc
voltage at AIN constant until the next clamp interval. The input
resistor RIN has a minimum recommended value of 10 Ω, to
maintain the closed-loop stability of the clamp amplifier.
1.0F
0.1F
REFBF
0.1F
1k⍀
AVDD/2
AVDD
MODE
+5V
REFSENSE
REF43
0.1F
Figure 22. External Reference Mode—1 V p-p Input
Span 2.5 VCM
REV. D
–12–
AD9280
The allowable voltage range that can be applied to CLAMPIN
depends on the operational limits of the internal clamp ampli-
fier. The recommended clamp range is between 0.5 volts and
2.0 volts.
back porch to truncate the SYNC below the AD9280’s mini-
mum input voltage. With a CIN = 1 µF, and RIN = 20 Ω, the
acquisition time needed to set the input dc level to one volt
with 1 mV accuracy is about 140 µs, assuming a full 1 volt VC.
The input capacitor should be sized to allow sufficient acquisi-
tion time of the clamp voltage at AIN within the CLAMP inter-
val, but also be sized to minimize droop between clamping
intervals. Specifically, the acquisition time when the switch is
closed will equal:
With a 1 µF input coupling capacitor, the droop across one
horizontal can be calculated:
IBIAS = 22 µA, and t = 63.5 µs, so dV = 1.397 mV, which is less
than one LSB.
After the input capacitor is initially charged, the clamp pulse
width only needs to be wide enough to correct small voltage
errors such as the droop. The fine scale settling characteristics
of the clamp circuitry are shown in Table II.
VC
TACQ = RINCIN ln
VE
where VC is the voltage change required across CIN, and VE is
the error voltage. VC is calculated by taking the difference be-
tween the initial input dc level at the start of the clamp interval
and the clamp voltage supplied at CLAMPIN. VE is a system
dependent parameter, and equals the maximum tolerable devia-
tion from VC. For example, if a 2-volt input level needs to be
clamped to 1 volt at the AD9280’s input within 10 millivolts,
then VC equals 2 – 1 or 1 volt, and VE equals 10 mV. Note that
once the proper clamp level is attained at the input, only a very
small voltage change will be required to correct for droop.
Depending on the required accuracy, a CLAMP pulse width of
1 µs–3 µs should work in most applications. The OFFSET val-
ues ignore the contribution of offset from the clamp amplifier;
they simply compare the output code with a “final value” mea-
sured with a much longer CLAMP pulse duration.
Table II.
CLAMP
OFFSET
8 µs
4 µs
3 µs
2 µs
1 µs
<1 LSB
<2 LSBs
2 LSBs
5 LSBs
9 LSBs
The voltage droop is calculated with the following equation:
IBIAS
dV =
t
( )
CIN
where t = time between clamping intervals.
The bias current of the AD9280 will depend on the sampling
rate, FS, and the difference between the reference midpoint,
(REFTS–REFBS)/2 and the input voltage. For a fixed sampling
rate of 32 MHz, Figure 14 shows the input bias current for a
given input. For a 1 V input range, the maximum input bias
current from Figure 14 is 22 µA. For lower sampling rates the
input bias current will scale proportionally.
AD9280
CLAMP IN
CLAMP
SW1
CIN
RIN
AIN
TO
If droop is a critical parameter, then the minimum value of CIN
should be calculated first based on the droop requirement.
Acquisition time—the width of the CLAMP pulse—can be
adjusted accordingly once the minimum capacitor value is cho-
sen. A tradeoff will often need to be made between droop and
acquisition time, or error voltage VE.
SHA
Figure 24a. Clamp Operation
AIN
Clamp Circuit Example
A single supply video amplifier outputs a level-shifted video
signal between 2 and 3 volts with the following parameters:
0.1F
REFTF
REFTS
0.1F
10F
AD9280
REFBF
horizontal period = 63.56 µs,
horizontal sync interval = 10.9 µs,
horizontal sync pulse = 4.7 µs,
sync amplitude = 0.3 volts,
video amplitude of 0.7 volts,
reference black level = 2.3 volts
0.1F
REFBS
AVDD
2
MODE
CLAMP
SHORT TO REFBS
OR EXTERNAL DC
CLAMPIN
The video signal must be dc restored from a 2- to 3-volt range
down to a 1- to 2-volt range. Configuring the AD9280 for a
one volt input span with an input range from 1 to 2 volts (see
Figure 24), the CLAMPIN voltage can be set to 1 volt with an
external voltage or by direct connection to REFBS. The CLAMP
pulse may be applied during the SYNC pulse, or during the
Figure 24b. Video Clamp Circuit
REV. D
–13–
AD9280
DRIVING THE ANALOG INPUT
In many cases, particularly in single-supply operation, ac cou-
pling offers a convenient way of biasing the analog input signal
at the proper signal range. Figure 27 shows a typical configura-
tion for ac-coupling the analog input signal to the AD9280.
Maintaining the specifications outlined in the data sheet
requires careful selection of the component values. The most
important is the f–3 dB high-pass corner frequency. It is a function of
R2 and the parallel combination of C1 and C2. The f–3 dB point
can be approximated by the equation:
Figure 25 shows the equivalent analog input of the AD9280, a
sample-and-hold amplifier (switched capacitor input SHA).
Bringing CLK to a logic low level closes Switches 1 and 2 and
opens Switch 3. The input source connected to AIN must
charge capacitor CH during this time. When CLK transitions
from logic “low” to logic “high,” Switches 1 and 2 open, placing
the SHA in hold mode. Switch 3 then closes, forcing the output
of the op amp to equal the voltage stored on CH. When CLK
transitions from logic “high” to logic “low,” Switch 3 opens
first. Switches 1 and 2 close, placing the SHA in track mode.
f
–3 dB = 1/(2 × pi × [R2] CEQ)
where CEQ is the parallel combination of C1 and C2. Note that
C1 is typically a large electrolytic or tantalum capacitor that
becomes inductive at high frequencies. Adding a small ceramic
or polystyrene capacitor (on the order of 0.01 µF) that does not
become inductive until negligibly higher frequencies, maintains
a low impedance over a wide frequency range.
The structure of the input SHA places certain requirements on
the input drive source. The combination of the pin capacitance,
CP, and the hold capacitance, CH, is typically less than 5 pF.
The input source must be able to charge or discharge this ca-
pacitance to 8-bit accuracy in one half of a clock cycle. When
the SHA goes into track mode, the input source must charge or
discharge capacitor CH from the voltage already stored on CH
to the new voltage. In the worst case, a full-scale voltage step on
the input, the input source must provide the charging current
through the RON (50 Ω) of Switch 1 and quickly (within 1/2 CLK
period) settle. This situation corresponds to driving a low input
impedance. On the other hand, when the source voltage equals
the value previously stored on CH, the hold capacitor requires
no input current and the equivalent input impedance is ex-
tremely high.
NOTE: AC coupled input signals may also be shifted to a desired
level with the AD9280’s internal clamp. See Clamp Operation.
C1
R1
V
AIN
IN
R2
V
I
B
AD9280
C2
BIAS
Adding series resistance between the output of the source and
the AIN pin reduces the drive requirements placed on the
source. Figure 26 shows this configuration. The bandwidth of
the particular application limits the size of this resistor. To
maintain the performance outlined in the data sheet specifica-
tions, the resistor should be limited to 20 Ω or less. For applica-
tions with signal bandwidths less than 16 MHz, the user may
proportionally increase the size of the series resistor. Alterna-
tively, adding a shunt capacitance between the AIN pin and
analog ground can lower the ac load impedance. The value of
this capacitance will depend on the source resistance and the
required signal bandwidth.
Figure 27. AC Coupled Input
There are additional considerations when choosing the resistor
values. The ac-coupling capacitors integrate the switching tran-
sients present at the input of the AD9280 and cause a net dc
bias current, IB, to flow into the input. The magnitude of the
bias current increases as the signal magnitude deviates from
V midscale and the clock frequency increases; i.e., minimum
bias current flow when AIN = V midscale. This bias current
will result in an offset error of (R1 + R2) × IB. If it is necessary
to compensate this error, consider making R2 negligibly small or
modifying VBIAS to account for the resultant offset.
In systems that must use dc coupling, use an op amp to level-
shift a ground-referenced signal to comply with the input re-
quirements of the AD9280. Figure 28 shows an AD8041 config-
ured in noninverting mode.
The input span of the AD9280 is a function of the reference
voltages. For more information regarding the input range, see
the Internal and External Reference sections of the data sheet.
CH
+V
CC
AIN
0.1F
S1
CP
SHA
S3
NC
1
AD9280
7
0V
1V p-p
DC
S2
2
3
(REFTS
REFBS)
CH
20⍀
AD8041
6
AIN
CP
5
AD9280
4
MIDSCALE
NC
OFFSET
VOLTAGE
Figure 25. AD9280 Equivalent Input Structure
Figure 28. Bipolar Level Shift
< 20⍀
AIN
V
S
AD9280
Figure 26. Simple AD9280 Drive Configuration
REV. D
–14–
AD9280
DIFFERENTIAL INPUT OPERATION
The pipelined architecture of the AD9280 operates on both
rising and falling edges of the input clock. To minimize duty
cycle variations the recommended logic family to drive the clock
input is high speed or advanced CMOS (HC/HCT, AC/ACT)
logic. CMOS logic provides both symmetrical voltage threshold
levels and sufficient rise and fall times to support 32 MSPS
operation. The AD9280 is designed to support a conversion rate
of 32 MSPS; running the part at slightly faster clock rates may
be possible, although at reduced performance levels. Conversely,
some slight performance improvements might be realized by
clocking the AD9280 at slower clock rates.
The AD9280 will accept differential input signals. This function
may be used by shorting REFTS and REFBS and driving them
as one leg of the differential signal (the top leg is driven into
AIN). In the configuration below, the AD9280 is accepting a
1 V p-p signal. See Figure 29.
AD9280
AIN
2V
0.1F
1V
AVDD/2
REFTF
REFTS
REFBS
0.1F
10F
0.1F
S1
S2
VREF
REFBF
ANALOG
INPUT
S4
tC
1.0F
0.1F
S3
REFSENSE
MODE
tCH
tCL
INPUT
AVDD/2
CLOCK
25ns
Figure 29. Differential Input
AD876-8 MODE OF OPERATION
The AD9280 may be dropped into the AD876-8 socket. This
will allow AD876-8 users to take advantage of the reduced
power consumption realized when running the AD9280 on a
3.0 V analog supply.
DATA
OUTPUT
DATA 1
Figure 31. Timing Diagram
The power dissipated by the output buffers is largely propor-
tional to the clock frequency; running at reduced clock rates
provides a reduction in power consumption.
Figure 30 shows the pin functions of the AD876-8 and AD9280.
The grounded REFSENSE pin and floating MODE pin effec-
tively put the AD9280 in the external reference mode. The
external reference input for the AD876-8 will now be placed
on the reference pins of the AD9280.
DIGITAL INPUTS AND OUTPUTS
Each of the AD9280 digital control inputs, THREE-STATE
and STBY are reference to analog ground. The clock is also
referenced to analog ground.
The format of the digital output is straight binary (see Figure
32). A low power mode feature is provided such that for STBY
= HIGH and the clock disabled, the static power of the AD9280
will drop below 5 mW.
The clamp controls will be grounded by the AD876-8 socket.
The AD9280 has a 3 clock cycle delay compared to a 3.5 cycle
delay of the AD876-8.
4V
OTR
AIN
AD9280
2V
REFTS
REFTF
4V
2V
10F
0.1F
0.1F
REFBF
REFBS
0.1F
NC MODE
AVDD
REFSENSE
+FS
–FS+1LSB
–FS
CLAMP
CLAMPIN
OTR
+FS–1LSB
Figure 32. Output Data Format
VREF
0.1F
THREE-
STATE
Figure 30. AD876 Mode
tDHZ
tDEN
DATA
(D0–D9)
CLOCK INPUT
HIGH
IMPEDANCE
The AD9280 clock input is buffered internally with an inverter
powered from the AVDD pin. This feature allows the AD9280
to accommodate either +5 V or +3.3 V CMOS logic input sig-
nal swings with the input threshold for the CLK pin nominally
at AVDD/2.
Figure 33. Three-State Timing Diagram
REV. D
–15–
AD9280
that the bandlimited IF signal aliases back into the center of the
ADC’s baseband region (i.e., FS/4). For example, if an IF sig-
nal centered at 45 MHz is sampled at 20 MSPS, an image of
this IF signal will be aliased back to 5.0 MHz which corre-
sponds to one quarter of the sample rate (i.e., FS/4). This
demodulation technique typically reduces the complexity of the
post digital demodulator ASIC which follows the ADC.
APPLICATIONS
DIRECT IF DOWN CONVERSION USING THE AD9280
Sampling IF signals above an ADC’s baseband region (i.e., dc
to FS/2) is becoming increasingly popular in communication
applications. This process is often referred to as Direct IF Down
Conversion or Undersampling. There are several potential ben-
efits in using the ADC to alias (i.e., or mix) down a narrowband
or wideband IF signal. First and foremost is the elimination of a
complete mixer stage with its associated amplifiers and filters,
reducing cost and power dissipation. Second is the ability to
apply various DSP techniques to perform such functions as
filtering, channel selection, quadrature demodulation, data
reduction, detection, etc. A detailed discussion on using this
technique in digital receivers can be found in Analog Devices
Application Notes AN-301 and AN-302.
To maximize its distortion performance, the AD9280 is config-
ured in the differential mode with a 1 V span using a transformer.
The center tap of the transformer is biased at midsupply via a
resistor divider. Preceding the AD9280 is a bandpass filter as
well as a 32 dB gain stage. A large gain stage may be required
to compensate for the high insertion losses of a SAW filter used
for image rejection. The gain stage will also provide adequate
isolation for the SAW filter from the charge “kick back” currents
associated with AD9280’s input stage.
In Direct IF Down Conversion applications, one exploits the
inherent sampling process of an ADC in which an IF signal
lying outside the baseband region can be aliased back into the
baseband region in a similar manner that a mixer will down-
convert an IF signal. Similar to the mixer topology, an image
rejection filter is required to limit other potential interfering
signals from also aliasing back into the ADC’s baseband region.
A tradeoff exists between the complexity of this image rejection
filter and the sample rate as well as dynamic range of the ADC.
The gain stage can be realized using one or two cascaded
AD8009 op amps amplifiers. The AD8009 is a low cost, 1 GHz,
current-feedback op amp having a 3rd order intercept character-
ized up to 250 MHz. A passive bandpass filter following the
AD8009 attenuates its dominant 2nd order distortion products
which would otherwise be aliased back into the AD9280’s
baseband region. Also, it reduces any out-of-band noise which
would also be aliased back due to the AD9280’s noise band-
width of 220+ MHz. Note, the bandpass filters specifications
are application dependent and will affect both the total distor-
tion and noise performance of this circuit.
The AD9280 is well suited for various narrowband IF sampling
applications. The AD9280’s low distortion input SHA has a
full-power bandwidth extending to 300 MHz thus encompassing
many popular IF frequencies. The AD9280 will typically yield
an improvement in SNR when configured for the 2 V span, the
1 V span provides the optimum full-scale distortion perfor-
mance. Furthermore, the 1 V span reduces the performance
requirements of the input driver circuitry and thus may be
more practical for system implementation purposes.
The distortion and noise performance of an ADC at the given
IF frequency is of particular concern when evaluating an ADC
for a narrowband IF sampling application. Both single-tone and
dual-tone SFDR vs. amplitude are very useful in assessing an
ADC’s noise performance and noise contribution due to aper-
ture jitter. In any application, one is advised to test several units
of the same device under the same conditions to evaluate the
given applications sensitivity to that particular device.
Figure 34 shows a simplified schematic of the AD9280 config-
ured in an IF sampling application. To reduce the complexity of
the digital demodulator in many quadrature demodulation ap-
plications, the IF frequency and/or sample rate are selected such
G
= 20dB
G
= 12dB
L-C
1
2
SAW
FILTER
OUTPUT
MINI CIRCUITS
BANDPASS
FILTER
AD9280
AIN
50⍀
T4 - 6T
1:4
50⍀
50⍀
200⍀
200⍀
REFTS
REFBS
280⍀
22.1⍀
93.1⍀
VREF
1.0F
0.1F
REFSENSE
1k⍀
1k⍀
AVDD
0.1F
Figure 34. Simplified AD9280 IF Sampling Circuit
REV. D
–16–
AD9280
Figures 35–38 combine the dual-tone SFDR as well as single
tone SFDR and SNR performance at IF frequencies of 45 MHz,
70 MHz, 85 MHz and 135 MHz. Note, the SFDR vs. ampli-
tude data is referenced to dBFS while the single tone SNR data
is referenced to dBc. The AD9280 was operated in the differen-
tial mode (via transformer) with a 1 V span. The analog sup-
ply (AVDD) and the digital supply (DRVDD) were set to +5 V
and 3.3 V, respectively.
70
80
DUAL TONE SFDR
70
60
50
40
30
20
SINGLE TONE SFDR
60
SINGLE TONE SFDR
50
40
DUAL TONE SFDR
30
SNR
SNR
20
CLK = 25.7MHz
CLK = 30.9MHz
SINGLE TONE = 45.5MHz
DUAL TONE F1 = 44.5MHz
F2 = 45.5MHz
SINGLE TONE = 85.5MHz
DUAL TONE F1 = 84.5MHz
F2 = 85.5MHz
10
0
10
0
–0.5
–5
–10
–15
–20
–25
–30
–35
–40
–0.5
–5
–10
–15
–20
–25
–30
–35
–40
INPUT POWER LEVEL – dBFS
INPUT POWER LEVEL – dBFS
Figure 35. SNR/SFDR for IF @ 45 MHz
Figure 37. SNR/SFDR for IF @ 85 MHz
70
60
50
40
30
20
70
60
50
40
30
20
SINGLE TONE SFDR
DUAL TONE SFDR
DUAL TONE SFDR
SINGLE TONE SFDR
SNR
SNR
FS = 32MHz
SINGLE TONE = 135.5MHz
F1 = 134.5MHz
CLK = 31.1MHz
SINGLE TONE = 70.5MHz
DUAL TONE F1 = 69.5MHz
F2 = 70.5MHz
F2 = 135.5MHz
10
0
10
0
–0.5
–5
–10
–15
–20
–25
–30
–35
–40
–0.5
–5
–10
–15
–20
–25
–30
–35
–40
INPUT POWER LEVEL – dBFS
INPUT POWER LEVEL – dBFS
Figure 36. SNR/SFDR for IF @ 70 MHz
Figure 38. SNR/SFDR for IF @ 135 MHz
REV. D
–17–
AD9280
R11
15k⍀
R10
5k⍀
+3–5A
R15
R17
316⍀
+3–5A
TP14
AD822
U2
5
6
0.626V TO 4.8V
AD822
R7
1k⍀
7
Q1
2N3906
TP16
2
3
5.49k⍀
4
XXXX
1
U2
ADJ.
R8
10k⍀
C7
0.1F
EXTT
8
D1
AD1580
CW
R9
C11
0.1F
C8
10/10V
C13
C12
0.1F
R19
178⍀
10/10V
+3–5A
1.5k⍀
CM
R13
11k⍀
R20
178⍀
TP17
R12
10k⍀
C29
0.1F
AD822
2
3
XXXX
ADJ.
4
AD822
U3
EXTB
1
6
5
U3
C14
0.1F
C15
10/10V
7
Q2
2N3904
8
CW
C10
0.1F
R16
1k⍀
C9
10/10V
R18
316k⍀
TP11
+3–5A
J7
JP5
JP17
JP18
CLAMP
R37
1k⍀
DRVDD
R53
49.9⍀
B
B
1
S3
2
2
THREE-STATE
STBY
3
1
R38
1k⍀
A
S4
GND
3
A
R39
1k⍀
7
10
13
11
9
J8
J8
J8
J8
J8
RN1
22⍀
DRVDD
AVDD
27
25
3
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
J8
6
4
11
C16
0.1F
C19
0.1F
RN1
22⍀
C18
10/10V
C17
10/10V
2
12
5
4
RN1
22⍀
6
28
2
OTR
TP19
WHITE
16
8
9
3
4
5
6
7
10
1
2
13
B
B
B
B
B
B
B
B
VCCB
NC1
OE
GD1
A
A
A
A
A
A
A
A
U4
U4
U4
U4
U4
U4
U4
U4
8
AVDD
DRVDD
7
15
21
20
19
18
17
14
24
23
22
13
RN1
22⍀
D5
10
12
14
16
18
20
22
24
26
39
28
29
30
31
32
34
35
36
37
38
40
AD9280
D6
D7
D8
D9
13
U1
OTR
2
15
5
RN1
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
15
NC
NC
DUTCLK
THREE-STATE
STBY
REFSENSE
CLAMP
CLAMPIN
REFTS
CLK
16
B 1
22⍀
S2
THREE-STATE
STBY
REFSENSE
CLAMP
CLAMPIN
REFTS
2
17
18
19
20
21
22
23
24
25
26
27
+3–5D
DRVDD
VCCA
T/R
GD2
GD3
1
16
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
3
1
J8
C20
C40
11
12
0.1F
RN1
22⍀
A
0.1F
GND
U4
GND
GND GND
JP21
1
10 D7
11 D8
12 D9
CLK
74LVXC4245WM
REFTF
REFTF
MODE
3
WHITE
MODE
+3–5D
2
6
11
REFBF
REFBF
REFBS
VREF
19
20
21
5
4
3
NC
U5
U5
U5
U5
U5
U5
U5
U5
CLK
B
B
B
B
B
B
B
B
VCCB
NC1
OE
GD1
33
J8
A
A
A
A
A
A
A
A
REFBS
C42
0.1F
RN2
22⍀
VREF
CLK_OUT
AIN
AIN
5
3
12
RN2
18
17
16
15
14
24
23
22
6
D0
D1
D2
D3
D4
23
21
19
J8
J8
J8
7
+
AVSS DRVSS
14
C33
8
22⍀
10/10V
1
9
10
1
13
4
+3–5D
VCCA
T/R
GD2
GD3
RN2
22⍀
2
11
12
C21
DRVDD
NOTE:
THE AD9280 IS EXERCISED IN
AN AD9200 EVALUATION BOARD
0.1F
NC
NC
13
14
C41
0.1F
U5
GND
1
RN2
22⍀
74LVXC4245WM
3
GND
GND
2
15
2
17 J8
RN2
22⍀
JP20
C43
0.1F
GND
16
RN2
1
15
J8
GND
22⍀
Figure 39a. Evaluation Board Schematic
REV. D
–18–
AD9280
REFSENSE
EXTB
JP1
JP2
JP10
JP14
AVDD
AVDD
TP3
TP4
C3
0.1F
TP1
R5
10k⍀
MODE
REFBF
REFTF
C5
10/10V
C4
0.1F
JP15
JP16
+
JP9
JP3
JP4
R6
10k⍀
C6
0.1F
VREF
B
1
TP5
GND
EXTT
S5
2
CLAMPIN
EXTT
3
JP11
GND
TP6
A
JP6
REFTS
JP22
GND
JP12
AVDDCLK
AVDD
C36
C37
C38
C35
0.1F 0.1F 0.1F
10/10V
TP7
R35
REFBS
EXTB
4.99k⍀
GND
JP13
JP7
R34
2k⍀
CW
U6
B
T1–1T
U6
AIN
1
2
5
6
J1
3
2
R36
4.99k⍀
A
2
3
4
S8
TP12
2
B
1
R1
49.9⍀
1
TP8
S6
6
B
A
C30
0.1F
P
1
3
3
1
S7
S
JP8
2
REFBS
CM
T1
A
R51
49.9⍀
TP9
R2
J5
JP26
S1
100⍀
C1
0.1F
ADC_CLK
CLK
TP10
R3
R4
49.9⍀
A
3
TP13
DCIN
2
R52
49.9⍀
100⍀
U6
3
4
C2
1
DUTCLK
47/10V
B
TP29
L4
+3–5D
J9
J2
J3
J4
C32
C31
10/10V
0.1F
TP20
TP21
TP22
U6 DECOUPLING
AVDDCLK
U6
8
L1
L2
9
DRVDD
C22
0.1F
C23
10/10V
U6
10
14
11
13
74AHC14
PWR
U6
C28
0.1F
U6
12
AVDD
+3–5A
GND
7
C24
0.1F
C25
33/16V
L3
C26
0.1F
C27
10/10V
TP23 TP24 TP25 TP26 TP27 TP28
GND J6
GND J10
Figure 39b. Evaluation Board Schematic
REV. D
–19–
AD9280
Figure 40a. Evaluation Board, Component Signal (Not to Scale)
Figure 40b. Evaluation Board, Solder Signal (Not to Scale)
–20–
REV. D
AD9280
Figure 40c. Evaluation Board Power Plane (Not to Scale)
Figure 40d. Evaluation Board Ground Plane (Not to Scale)
–21–
REV. D
AD9280
Figure 40e. Evaluation Board Component Silk (Not to Scale)
C33 C6
C18 C19
C4
C3
C5
C16
C17
Figure 40f. Evaluation Board Solder Silk (Not to Scale)
REV. D
–22–
AD9280
DIGITAL OUTPUTS
GROUNDING AND LAYOUT RULES
Each of the on-chip buffers for the AD9280 output bits
(D0–D7) is powered from the DRVDD supply pins, separate
from AVDD. The output drivers are sized to handle a variety
of logic families while minimizing the amount of glitch energy
generated. In all cases, a fan-out of one is recommended to
keep the capacitive load on the output data bits below the speci-
fied 20 pF level.
As is the case for any high performance device, proper ground-
ing and layout techniques are essential in achieving optimal
performance. The analog and digital grounds on the AD9280
have been separated to optimize the management of return
currents in a system. Grounds should be connected near the
ADC. It is recommended that a printed circuit board (PCB) of
at least four layers, employing a ground plane and power planes,
be used with the AD9280. The use of ground and power planes
offers distinct advantages:
For DRVDD = 5 V, the AD9280 output signal swing is com-
patible with both high speed CMOS and TTL logic families.
For TTL, the AD9280 on-chip, output drivers were designed to
support several of the high speed TTL families (F, AS, S). For
applications where the clock rate is below 32 MSPS, other TTL
families may be appropriate. For interfacing with lower voltage
CMOS logic, the AD9280 sustains 32 MSPS operation with
DRVDD = 3 V. In all cases, check your logic family data sheets
for compatibility with the AD9280 Digital Specification table.
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power plane,
PCB insulation and ground plane.
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
THREE-STATE OUTPUTS
The digital outputs of the AD9280 can be placed in a high
impedance state by setting the THREE-STATE pin to HIGH.
This feature is provided to facilitate in-circuit testing or evaluation.
It is important to design a layout that prevents noise from cou-
pling onto the input signal. Digital signals should not be run in
parallel with the input signal traces and should be routed away
from the input circuitry. Separate analog and digital grounds
should be joined together directly under the AD9280 in a solid
ground plane. The power and ground return currents must be
carefully managed. A general rule of thumb for mixed signal
layouts dictates that the return currents from digital circuitry
should not pass through critical analog circuitry.
REV. D
–23–
AD9280
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline Package (SSOP)
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
14
1
0.07 (1.79)
0.078 (1.98)
PIN 1
0.066 (1.67)
0.068 (1.73)
0.03 (0.762)
8°
0°
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.022 (0.558)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
REV. D
–24–
相关型号：
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