AD9288/PCB [ADI]
8-Bit, 40/80/100 MSPS Dual A/D Converter; 8位， 40/80/100 MSPS双通道A / D转换器
| 型号： | AD9288/PCB |
| 厂家： | 
ADI |
| 描述： | 8-Bit, 40/80/100 MSPS Dual A/D Converter |
| 文件： | 总16页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit, 40/80/100 MSPS
Dual A/D Converter
a
AD9288
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Dual 8-Bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC
Low Power: 90 mW at 100 MSPS per Channel
On-Chip Reference and Track/Holds
475 MHz Analog Bandwidth Each Channel
SNR = 47 dB @ 41 MHz
1 V p-p Analog Input Range Each Channel
Single +3.0 V Supply Operation (2.7 V–3.6 V)
Standby Mode for Single Channel Operation
Twos Complement or Offset Binary Output Mode
Output Data Alignment Mode
V
DD
AD9288
TIMING
ENC
A
A
A
A
A
8
8
IN
T/H
ADC
REF
ADC
D7 –D0
A A
IN
SELECT #1
SELECT #2
REF
REF
A
IN
OUT
REF
B
IN
DATA FORMAT
SELECT
APPLICATIONS
A
A
B
B
8
8
IN
T/H
D7 –D0
Battery Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
I and Q Communications
B
B
IN
ENC
TIMING
B
V
GND
V
DD
D
GENERAL DESCRIPTION
The encode input is TTL/CMOS compatible and the 8-bit
digital outputs can be operated from +3.0 V (2.5 V to 3.6 V)
supplies. User-selectable options are available to offer a combi-
nation of standby modes, digital data formats and digital data
timing schemes. In standby mode, the digital outputs are driven
to a high impedance state.
The AD9288 is a dual 8-bit monolithic sampling analog-to-
digital converter with on-chip track-and-hold circuits and is
optimized for low cost, low power, small size and ease of use.
The product operates at a 100 MSPS conversion rate with out-
standing dynamic performance over its full operating range.
Each channel can be operated independently.
Fabricated on an advanced CMOS process, the AD9288 is avail-
able in a 48-lead surface mount plastic package (7 × 7 mm,
1.4 mm LQFP) specified over the industrial temperature range
(–40°C to +85°C).
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and an encode clock for full-performance operation. No
external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS compatible
and a separate output power supply pin supports interfacing
with 3.3 V or 2.5 V logic.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(V = 3.0 V; V = 3.0 V, Differential Input; External reference unless otherwise noted.)
AD9288–SPECIFICATIONS
DD
D
Test
AD9288BST-100
AD9288BST-80
AD9288BST-40
Parameter
Temp
Level Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
RESOLUTION
8
8
8
Bits
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
Full
+25°C
Full
Full
+25°C
+25°C
I
VI
I
VI
VI
I
VI
VI
V
±0.5
+1.25
+1.50
±0.5
+1.25
+1.50
±0.5
+1.25
+1.50
LSB
LSB
LSB
LSB
Integral Nonlinearity
±0.50 +1.25
±0.50 +1.25
±0.50 +1.25
+1.50
+1.50
+1.50
No Missing Codes
Gain Error1
Guaranteed
±2.5
Guaranteed
±2.5
Guaranteed
±2.5
–6
–8
+6
+8
–6
–8
+6
+8
–6
–8
+6
+8
% FS
% FS
ppm/°C
% FS
mV
Gain Tempco1
Gain Matching
Voltage Matching
80
±1.5
±15
80
±1.5
±15
80
±1.5
±15
V
ANALOG INPUT
Input Voltage Range
(With Respect to AIN)
Common-Mode Voltage
Input Offset Voltage
Full
Full
+25°C
Full
Full
Full
+25°C
Full
+25°C
+25°C
V
V
I
VI
VI
VI
I
VI
V
±512
±200
±10
±40
1.25
±130
10
±512
±200
±10
±40
1.25
±130
10
±512
±200
±10
±40
1.25
±130
10
mV p-p
mV
mV
mV
V
ppm/°C
kΩ
kΩ
pF
MHz
–35
1.2
+35
1.3
–35
1.2
+35
1.3
–35
1.2
+35
1.3
Reference Voltage
Reference Tempco
Input Resistance
7
5
13
16
7
5
13
16
7
5
13
16
Input Capacitance
Analog Bandwidth, Full Power
2
475
2
475
2
475
V
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Full
VI
IV
IV
IV
V
V
VI
VI
100
80
40
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
+25°C
+25°C
+25°C
+25°C
+25°C
Full
1
1
1
Encode Pulsewidth High (tEH
)
4.3
4.3
1000
1000
5.0
5.0
1000
1000
8.0
8.0
1000
1000
Encode Pulsewidth Low (tEL
)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Valid Time (tV)2
0
5
3.0
4.5
0
5
3.0
4.5
0
5
3.0
4.5
2
Output Propagation Delay (tPD
)
Full
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Full
Full
Full
Full
VI
VI
VI
VI
V
2.0
2.0
2.0
V
V
µA
µA
pF
0.8
±1
±1
0.8
±1
±1
0.8
±1
±1
+25°C
2.0
2.0
2.0
DIGITAL OUTPUTS3
Logic “1” Voltage
Logic “0” Voltage
Full
Full
VI
VI
2.45
2.45
2.45
V
V
0.05
0.05
0.05
POWER SUPPLY
Power Dissipation4
Standby Dissipation4, 5
Power Supply Rejection Ratio
(PSRR)
Full
Full
VI
VI
180
6
218
11
171
6
207
11
156
6
189
11
mW
mW
+25°C
I
8
20
8
20
8
20
mV/V
DYNAMIC PERFORMANCE6
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
+25°C
+25°C
V
V
2
2
2
2
2
2
ns
ns
f
IN = 10.3 MHz
+25°C
+25°C
+25°C
I
I
I
47.5
47.5
47.0
47.5
47
44
47.5
dB
dB
dB
fIN = 26 MHz
fIN = 41 MHz
44
44
–2–
REV. 0
AD9288
Test
AD9288BST-100
AD9288BST-80
AD9288BST-40
Parameter
Temp
Level Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
DYNAMIC PERFORMANCE6 (Continued)
Signal-to-Noise Ratio (SINAD) (With Harmonics)
f
f
f
IN = 10.3 MHz
IN = 26 MHz
IN = 41 MHz
+25°C
+25°C
+25°C
I
I
I
47
47
47
47
47
47
44
7.0
55
55
47
dB
dB
dB
44
7.0
55
55
44
7.0
55
52
Effective Number of Bits
f
f
fIN = 41 MHz
2nd Harmonic Distortion
fIN = 10.3 MHz
IN = 10.3 MHz
IN = 26 MHz
+25°C
+25°C
+25°C
I
I
I
7.5
7.5
7.5
7.5
7.5
7.5
7.5
70
60
60
Bits
Bits
Bits
+25°C
+25°C
+25°C
I
I
I
70
70
70
70
70
70
dBc
dBc
dBc
f
IN = 26 MHz
fIN = 41 MHz
3rd Harmonic Distortion
fIN = 10.3 MHz
+25°C
+25°C
+25°C
I
I
I
60
60
60
60
60
60
dBc
dBc
dBc
f
IN = 26 MHz
fIN = 41 MHz
Two-Tone Intermod Distortion (IMD)
fIN = 10.3 MHz +25°C
V
60
60
dBc
NOTES
1Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference).
2tV and tPD are measured from the 1.5 V level of the ENCODE input to the 10%/90% levels of the digital outputs swing. The digital output load during test is not to
exceed an ac load of 10 pF or a dc current of ±40 µA.
3Digital supply current based on VDD = +3.0 V output drive with <10 pF loading under dynamic test conditions.
4Power dissipation measured under the following conditions: fS = 100 MSPS, analog input is –0.7 dBFS, both channels in operation.
5Standby dissipation calculated with encode clock in operation.
6SNR/harmonics based on an analog input voltage of –0.7 dBFS referenced to a 1.024 V full-scale input range.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
ABSOLUTE MAXIMUM RATINGS*
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150°C
I
100% production tested.
II 100% production tested at +25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V
Parameter is a typical value only.
VI 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes for
military devices.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
Table I. User Select Options
ORDERING GUIDE
S1
S2
User Select Options
Temperature
Ranges
Package
Options
0
0
1
1
0
1
0
1
Standby Both Channels A and B.
Standby Channel B Only.
Normal Operation (Data Align Disabled).
Data align enabled (data from both channels avail-
able on rising edge of Clock A. Channel B data is
delayed a 1/2 clock cycle).
Model
AD9288BST
-40, -80, -100
AD9288/PCB
–40°C to +85°C
+25°C
ST-48*
Evaluation Board
*ST = Thin Plastic Quad Flatpack (1.4 mm thick, 7 × 7 mm: LQFP).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9288 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD9288
PIN CONFIGURATION
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
48 47 46 45 44 43 42 41 40 39 38 37
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
1
2
GND
36
35
34
33
32
31
30
29
28
NC
PIN 1
A
A
A
A
IDENTIFIER
NC
IN
3
GND
IN
Encode Pulsewidth/Duty Cycle
4
DFS
V
DD
Pulsewidth high is the minimum amount of time that the EN-
CODE pulse should be left in Logic “1” state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these
specs define an acceptable Encode duty cycle.
5
REF
A
GND
IN
AD9288
TOP VIEW
(Not to Scale)
6
REF
V
D
OUT
7
REF
B
V
D
IN
8
S1
S2
B
GND
9
V
DD
A
A
10
11
27
GND
IN
B
26 NC
25
IN
Integral Nonlinearity
GND 12
NC
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line” deter-
mined by a least square curve fit.
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
PIN FUNCTION DESCRIPTIONS
Maximum Conversion Rate
Pin No.
Name
Description
The encode rate at which parametric testing is performed.
1, 12, 16, 27, 29,
32, 34, 45
2
3
Output Propagation Delay
GND
AINA
AINA
Ground.
Analog Input for Channel A.
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Analog Input for Channel A
(Complementary).
Data Format Select: (Offset
binary output available if set
low. Twos complement output
available if set high).
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
4
DFS
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
5
REFINA
Reference Voltage Input for
Channel A.
Internal Reference Voltage.
Reference Voltage Input for
Channel B.
User Select #1 (Refer to Table
I), Tied with Respect to VD.
6
7
REFOUT
REFINB
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
8
S1
Spurious-Free Dynamic Range (SFDR)
9
S2
User Select #2 (Refer to Table
I), Tied with Respect to VD.
Analog Input for Channel B
(Complementary).
Analog Input for Channel B.
Analog Supply (3 V).
Clock Input for Channel B.
Digital Supply (3 V).
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
10
AINB
11
AINB
VD
ENCB
VDD
D7B–D0B
NC
13, 30, 31, 48
14
15, 28, 33, 46
17–24
25, 26, 35, 36
37–44
47
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product; re-
ported in dBc.
Digital Output for Channel B.
Do Not Connect.
Two-Tone SFDR
D0A–D7A Digital Output for Channel A.
ENCA Clock Input for Channel A.
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
DEFINITION OF SPECIFICATIONS
Analog Bandwidth (Small Signal)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Worst Harmonic
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.
–4–
REV. 0
AD9288
SAMPLE N
SAMPLE N+1
SAMPLE N+5
A
A, A B
IN
IN
tA
SAMPLE N+2
SAMPLE N+3
SAMPLE N+4
tEH
tEL
1/
fS
ENCODE A, B
D7 –D0
tPD
tV
DATA N–4
DATA N–4
DATA N–3
DATA N–2
DATA N–1
DATA N–1
DATA N
DATA N+1
DATA N+1
A
A
D7 –D0
B
DATA N–3
DATA N–2
DATA N
B
Figure 1. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
SAMPLE N
SAMPLE N+1
SAMPLE N+5
A
A, A B
IN IN
tA
SAMPLE N+2
SAMPLE N+3
SAMPLE N+4
tEH
tEL
1/
fS
ENCODE A
ENCODE B
tPD
tV
D7 –D0
DATA N–4
DATA N–3
DATA N–2
DATA N–1
DATA N
DATA N+1
A
A
D7 –D0
B
DATA N–4
DATA N–3
DATA N–2
DATA N–1
DATA N
DATA N+1
B
Figure 2. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
REV. 0
–5–
AD9288
SAMPLE N
SAMPLE N+1
SAMPLE N+5
A
A, A B
IN
IN
tA
SAMPLE N+2
SAMPLE N+3
SAMPLE N+4
tEH
tEL
1/
fS
ENCODE A
ENCODE B
tPD
tV
D7 –D0
DATA N–4
DATA N–4
DATA N–3
DATA N–2
DATA N–1
DATA N–1
DATA N
DATA N
DATA N+1
DATA N+1
A
A
D7 –D0
B
DATA N–3
DATA N–2
B
Figure 3. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing
–6–
REV. 0
Typical Performance Characteristics–AD9288
72.00
0
–10
–20
–30
ENCODE = 100MSPS
= 10.3MHz
SNR = 48.52dB
SINAD = 48.08dB
2ND HARMONIC = –62.54dBc
3RD HARMONIC = –63.56dBc
ENCODE RATE = 100MSPS
A
IN
68.00
64.00
2ND
60.00
56.00
–40
–50
–60
–70
–80
3RD
52.00
48.00
44.00
40.00
–90
0
10
20
30
40
50
60
70
80
90
SAMPLE
MHz
Figure 7. Harmonic Distortion vs. AIN Frequency
Figure 4. Spectrum: fS = 100 MSPS, fIN = 10 MHz,
Single-Ended Input
0
0
ENCODE = 100MSPS
ENCODE = 100MSPS
A
= 41MHz
IN
–10
–20
–30
–40
–50
–60
–70
–80
A
1 = 9.3MHz
–10
–20
–30
–40
–50
–60
–70
–80
IN
SNR = 47.87dB
SINAD = 46.27dB
2ND HARMONIC = –54.10dBc
3RD HARMONIC = –55.46dBc
A
2 = 10.3MHz
IN
IMD = –60.0dBc
–90
–90
SAMPLE
SAMPLE
Figure 5. Spectrum: fS = 100 MSPS, fIN = 41 MHz,
Single-Ended Input
Figure 8. Two-Tone Intermodulation Distortion
0
50.00
ENCODE = 100MSPS
ENCODE RATE = 100MSPS
A
= 76MHz
IN
–10
–20
–30
–40
–50
–60
–70
–80
48.00
SNR = 47.1dB
SINAD = 43.2dB
2ND HARMONIC = –52.2dBc
3RD HARMONIC = –51.5dBc
SNR
46.00
SINAD
44.00
42.00
40.00
38.00
36.00
–90
0
10
20
30
40
50
60
70
80
90
SAMPLE
MHz
Figure 6. Spectrum: fS = 100 MSPS, fIN = 76 MHz,
Single-Ended Input
Figure 9. SINAD/SNR vs. AIN Frequency
REV. 0
–7–
AD9288
49.00
190
185
180
175
A
= 10.3MHz
IN
SNR
A
= 10.3MHz
IN
SINAD
48.00
47.00
170
165
160
155
150
145
46.00
45.00
140
30
40
50
60
70
80
90
100
110
0
10
20
30
40
50
60
70
80
90
100
MSPS
MSPS
Figure 10. SINAD/SNR vs. Encode Rate
Figure 13. Analog Power Dissipation vs. Encode Rate
50.00
46.00
42.00
38.00
34.00
30.00
48.0
A
= 10.3MHz
ENCODE RATE = 100MSPS
SNR
IN
A
= 10.3MHz
IN
47.5
SINAD
47.0
46.5
46.0
SNR
SINAD
45.5
45.0
44.5
44.0
43.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
–40
25
TEMPERATURE – ؇C
85
ENCODE HIGH PULSEWIDTH – ns
Figure 11. SINAD/SNR vs. Encode Pulsewidth High
Figure 14. SINAD/SNR vs. Temperature
0.6
0.5
ENCODE RATE = 100MSPS
ENCODE RATE = 100MSPS
= 10.3MHz
0.0
–0.5
–1.0
–1.5
A
IN
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–3dB
–1.0
0
100
200
300
400
500
600
–40
25
TEMPERATURE – ؇C
85
BANDWIDTH – MHz
Figure 12. ADC Frequency Response: fS = 100 MSPS
Figure 15. ADC Gain vs. Temperature (with External
+1.25 V Reference)
–8–
REV. 0
AD9288
V
2.0
1.5
D
28k⍀
28k⍀
A
A
IN
IN
12k⍀
1.0
12k⍀
0.5
Figure 19. Equivalent Analog Input Circuit
0.0
–0.5
–1.0
–1.5
–2.0
V
D
V
BIAS
REF
CODE
IN
Figure 16. Integral Nonlinearity
Figure 20. Equivalent Reference Input Circuit
1.00
0.75
V
D
0.50
ENCODE
0.25
0.00
Figure 21. Equivalent Encode Input Circuit
–0.25
–0.50
–0.75
–1.00
V
DD
OUT
CODE
Figure 17. Differential Nonlinearity
Figure 22. Equivalent Digital Output Circuit
1.3
1.2
1.1
1.0
0.9
ENCODE = 100MSPS
V
= 3.0V
D
A
V
D
T
= +25؇C
OUT
Figure 23. Equivalent Reference Output Circuit
0.8
0.7
0
0.25
0.5
0.75
1
1.25
1.5
1.75
LOAD – mA
Figure 18. Voltage Reference Out vs. Current Load
REV. 0
–9–
AD9288
Timing
APPLICATION NOTES
The AD9288 provides latched data outputs, with four pipeline
delays. Data outputs are available one propagation delay (tPD
after the rising edge of the encode command (see Figures 1, 2
and 3). The length of the output data lines and loads placed on
them should be minimized to reduce transients within the
AD9288. These transients can detract from the converter’s
dynamic performance.
THEORY OF OPERATION
)
The AD9288 ADC architecture is a bit-per-stage pipeline-type
converter utilizing switch capacitor techniques. These stages
determine the 5 MSBs and drive a 3-bit flash. Each stage pro-
vides sufficient overlap and error correction allowing optimiza-
tion of comparator accuracy. The input buffers are differential
and both sets of inputs are internally biased. This allows the
most flexible use of ac or dc and differential or single-ended
input modes. The output staging block aligns the data, carries
out the error correction and feeds the data to output buffers.
The set of output buffers are powered from a separate supply,
allowing adjustment of the output voltage swing. There is no
discernible difference in performance between the two channels.
The minimum guaranteed conversion rate of the AD9288 is
1 MSPS. At clock rates below 1 MSPS, dynamic performance
will degrade. Typical power-up recovery time after standby
mode is 15 clock cycles.
User Select Options
Two pins are available for a combination of operational modes.
These options allow the user to place both channels in standby,
excluding the reference, or just the B channel. Both modes place
the output buffers and clock inputs in high impedance states.
USING THE AD9288
Good high speed design practices must be followed when using
the AD9288. To obtain maximum benefit, decoupling capacitors
should be physically as close to the chip as possible, minimizing
trace and via inductance between chip pins and capacitor (0603
surface mount caps are used on the AD9288/PCB evaluation
board). It is recommended to place a 0.1 µF capacitor at each
power-ground pin pair for high frequency decoupling, and in-
clude one 10 µF capacitor for local low frequency decoupling.
The VREF IN pin should also be decoupled by a 0.1 µF capaci-
tor. It is also recommended to use a split power plane and
contiguous ground plane (see evaluation board section). Data
output traces should be short (<1 inch), minimizing on-chip
noise at switching.
The other option allows the user to skew the B channel output
data by 1/2 a clock cycle. In other words, if two clocks are fed to
the AD9288 and are 180° out of phase, enabling the data align
will allow Channel B output data to be available at the rising
edge of Clock A. If the same encode clock is provided to both
channels and the data align pin is enabled, then output data
from Channel B will be 180° out of phase with respect to Chan-
nel A. If the same encode clock is provided to both channels
and the data align pin is disabled, then both outputs are deliv-
ered on the same rising edge of the clock.
EVALUATION BOARD
ENCODE Input
The AD9288 evaluation board offers an easy way to test the
AD9288. It provides a means to drive the analog inputs single-
endedly or differentially. The two encode clocks are easily
accessible at on-board SMB connectors J2, J7. These clocks are
buffered on the board to provide the clocks for an on-board
DAC and latches. The digital outputs and output clocks are
available at a standard 37-pin connector, P2. The board has
several different modes of operation, and is shipped in the fol-
lowing configuration:
Any high speed A/D converter is extremely sensitive to the qual-
ity of the sampling clock provided by the user. A track/hold
circuit is essentially a mixer. Any noise, distortion or timing
jitter on the clock will be combined with the desired signal at
the A/D output. For that reason, considerable care has been
taken in the design of the ENCODE input of the AD9288, and
the user is advised to give commensurate thought to the clock
source. The ENCODE input is fully TTL/CMOS compatible.
Digital Outputs
• Single-Ended Analog Input
• Normal Operation Timing Mode
• Internal Voltage Reference
The digital outputs are TTL/CMOS compatible for lower
power consumption. During standby, the output buffers transi-
tion to a high impedance state. A data format selection option
supports either twos complement (set high) or offset binary
output (set low) formats.
Power Connector
Power is supplied to the board via a detachable 6-pin power
strip, P1.
Analog Input
The analog input to the AD9288 is a differential buffer. For
best dynamic performance, impedance at AIN and AIN should
match. Special care was taken in the design of the analog input
stage of the AD9288 to prevent damage and corruption of
data when the input is overdriven. The nominal input range is
1.024 V p-p centered at VD × 0.3.
VREFA – Optional External Reference Input (1.25 V/1 µA)
VREFB – Optional External Reference Input (1.25 V/1 µA)
VDL
VDD
VD
–
–
–
Supply for Support Logic and DAC (3 V/215 mA)
Supply for ADC Outputs
(3 V/15 mA)
(3 V/30 mA)
Supply for ADC Analog
Analog Inputs
Voltage Reference
The evaluation board accepts a 1 V analog input signal centered
at ground at each analog input. These can be single-ended sig-
nals using SMB connectors J5 (channel A) and J1 (Channel B).
In this mode use jumpers E4–E5 and E6–E7. (E1–E2 and E9–
E10 jumpers should be lifted.)
A stable and accurate 1.25 V voltage reference is built into the
AD9288 (REFOUT). In normal operation, the internal reference
is used by strapping Pins 5 (REFINA) and 7 (REFINB) to Pin 6
(REFOUT). The input range can be adjusted by varying the
reference voltage applied to the AD9288. No appreciable degra-
dation in performance occurs when the reference is adjusted
±5%. The full-scale range of the ADC tracks reference voltage,
which changes linearly.
Differential analog inputs use SMB connectors J4 and J6. Input
is 1 V centered at ground. The single-ended input is converted
–10–
REV. 0
AD9288
to differential by transformers T1, T2—allowing the ADC perfor-
mance for differential inputs to be measured using a single-
ended source. In this mode use jumpers E1–E2, E3–E4, E7–E8
and E9–E10. (E4–E5 and E6–E7 jumpers should be lifted.)
PIN 22 (DATA)
Each analog input is terminated on the board with 50 Ω to
ground. Each input is ac-coupled on the board through a 0.1 µF
capacitor to an on-chip resistor divider that provides dc bias.
Note that the inverting analog inputs are terminated on the
board with 25 Ω (optimized for single-ended operation). When
driving the board differentially these resistors can be changed to
50 Ω to provide balanced inputs.
1
PIN 2 (CLOCK)
Ch1 2.00V CH2 2.00V M 10.0ns CH4
40mV
Figure 24. Data Output and Clock at 37-Pin Connector
Encode
DAC Outputs
The encode clock for channel A uses SMB connector J7. Chan-
nel B encode is at SMB connector J2. Each clock input is termi-
nated on the board with 50 Ω to ground. The input clocks are
fed directly to the ADC and to buffers U5, U6 which drive the
DAC and latches. The clock inputs are TTL compatible, but
should be limited to a maximum of VD.
Each channel is reconstructed by an on-board dual channel
DAC, an AD9763. This DAC is intended to assist in debug—it
should not be used to measure the performance of the ADC. It
is a current output DAC with on-board 50 Ω termination resis-
tors. Figure 25 is representative of the DAC output with a full-
scale analog input. The scope setting was low bandwidth, 50 Ω
termination.
Voltage Reference
The AD9288 has an internal 1.25 V voltage reference. An ex-
ternal reference for each channel may be employed instead. The
evaluation board is configured for the internal reference (use
jumpers E18–E41 and E17–E19. To use external references,
connect to VREFA and VREFB pins on the power connector
P1 and use jumpers E20–E18 and E21–E19.
1
Normal Operation Mode
In this mode both converters are clocked by the same encode
clock; latency is four clock cycles (see timing diagram). Signal
S1 (Pin 8) is held high and signal S2 (Pin 9) is held low. This is
set at jumpers E22–E29 and E26–E23.
Ch1 500mV⍀B
W
M 50.0ns CH1
380mV
Data Align Mode
Figure 25. AD9763 Reconstruction DAC Output
Troubleshooting
If the board does not seem to be working correctly, try the
following:
In this mode channel B output is delayed an additional 1/2 cycle.
Signal S1 (Pin 8) and signal S2 (Pin 9) are both held high. This
is set at jumpers E22–E29 and E26–E28.
Data Format Select
•
•
Verify power at IC pins.
Check that all jumpers are in the correct position for the
desired mode of operation.
Data Format Select sets the output data format that the ADC
outputs. Setting DFS (Pin 4) low at E30–E27 sets the output
format to be offset binary; setting DFS high at E30–E25 sets
the output to be twos complement.
•
•
Verify VREF is at 1.25 V
Try running encode clock and analog inputs at low speeds
(10 MSPS/1 MHz) and monitor 574 outputs, DAC outputs,
and ADC outputs for toggling.
Data Outputs
The ADC digital outputs are latched on the board by two 574s,
the latch outputs are available at the 37-pin connector at Pins
22–29 (Channel A) and Pins 30–37 (Channel B). A latch out-
put clock (data ready) is available at Pin 2 or 21 on the output
connector. The data ready signal can be aligned with clock A
input by connecting E31–E32 or aligned with clock B input by
connecting E31–E33.
The AD9288 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warran-
ties, express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.
REV. 0
–11–
AD9288
BILL OF MATERIALS
DEVICE
#
QTY
REFDES
PACKAGE
VALUE
1
2
3
4
22
5
43
8
C1–C15, C20–C25, C27
C16–C19, C26
E1–E43
J1–J8
Ceramic Cap
Tantalum Cap
W-HOLE
SMBPN
0603
TAJD
W-HOLE
SMBP
0.1 µF
10 µF
5
1
P1
TB6
TB6
6
7
8
9
10
11
12
13
14
15
1
10
2
2
2
2
1
1
2
P2
37DRFP
Resistor
Resistor
Resistor
Resistor
Transformer
AD9288
AD9763
74ACQ574
SN74LCX86
C37DRFP
R1206
R1206
R1206
R1206
T1–1T
LQFP48
LQFP48
DIP20\SOL
SO14
R1, R3, R5–R7, R10–R14
50 Ω
25 Ω
2 kΩ
0 Ω
R2, R4
R8, R9
R15, R16
T1, T2
U1
U2
U3, U4
U5, U6
2
–12–
REV. 0
AD9288
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
D 2
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
G N D
D 2
D 3
D 4
D 5
D 6
D 7
D 8
D 9
D 3
D 4
D 5
D 6
D 7
D 8
D 9
D B 8 – P 2
D B 9 – P 2
D V D D 2
G N D
G N D
S L E E P
A C O M
G N D
F 0 . 1
C 8
G N D
F 0 . 1
G N D
G N D 3
G N D
D D
C 6
A 2
D L
V
D D
V
3
V
D D
V
A
E
G N D
G N D
B 2
D C O M 2
B
B
A
E N C
V
⍀
R 0 5 0
E N C
E N C
D D
V
C L K D A C B
C L K D A C B D
C L K D A C A
C L K D A C A
G N D
F S A D J 2
R E F I O
W R T 2 / I Q S E L
⍀
R 8 2 k
C 2 1 0 . 1
D
D
D
V
3
V
V
C L K 2 / I Q R E S E T
C L K 1 / I Q C L K
W R T 1 / I Q W R T
D V D D 1
F 0 . 1
F 0 . 1
G N D
F
C 5
C 7
R E F I O
G N D
G N D
G N D
F S A D J 1
⍀
R 9 2 k
B 1
R 1 3 5 0
A 1
G N D
⍀
D L
V
G N D
D C O M 1
N C 3
G N D
G N D
A V D D
M O D E
N C 2
Figure 26 . Dual Evaluation Board Schematic
–13–
REV. 0
AD9288
Figure 27. Printed Circuit Board Top Side Copper
Figure 29. Printed Circuit Board Ground Layer
Figure 28. Printed Circuit Board Bottom Side Silkscreen
Figure 30. Printed Circuit Board “Split” Power Layer
–14–
REV. 0
AD9288
Figure 31. Printed Circuit Board Bottom Side Copper
Figure 32. Printed Circuit Board Top Side Silkscreen
REV. 0
–15–
AD9288
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead LQFP
(ST-48)
0.063 (1.60) MAX
30 0 7
0.354 (9.00) BSC
0.276 (7.0) BSC
0.057 (1.45)
0.030 (0.75)
0.053 (1.35)
0.018 (0.45)
37
36
48
1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.006 (0.15)
12
13
25
24
0.002 (0.05)
0° MIN
0° – 7°
0.007 (0.18)
0.004 (0.09)
0.011 (0.27)
0.006 (0.17)
0.019 (0.5)
BSC
–16–
REV. 0
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