AD9288BSTZ-100 [ADI]
8-Bit, 40/80/100 MSPS Dual A/D Converter; 8位， 40/80/100 MSPS双通道A / D转换器
| 型号： | AD9288BSTZ-100 |
| 厂家： | 
ADI |
| 描述： | 8-Bit, 40/80/100 MSPS Dual A/D Converter |
| 文件： | 总24页 (文件大小：833K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit, 40/80/100 MSPS
Dual A/D Converter
AD9288
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
Dual 8-bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC
Low power: 90 mW at 100 MSPS per channel
On-chip reference and track-and-hold
475 MHz analog bandwidth each channel
SNR = 47 dB @ 41 MHz
DD
AD9288
ENC
TIMING
A
A
A
A
A
8
8
IN
T/H
D7 –D0
A A
ADC
IN
1 V p-p analog input range each channel
Single 3.0 V supply operation (2.7 V to 3.6 V)
Standby mode for single-channel operation
Twos complement or offset binary output mode
Output data alignment mode
SELECT 1
SELECT 2
REF
REF
A
IN
REF
ADC
OUT
REF
B
IN
DATA FORMAT
SELECT
A
A
B
B
8
8
Pin-compatible 10-bit upgrade available
IN
T/H
D7 –D0
B
B
IN
APPLICATIONS
ENC
TIMING
B
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
I and Q communications
V
GND
V
DD
D
Figure 1.
GENERAL DESCRIPTION
The AD9288 is a dual 8-bit monolithic sampling analog-to-
digital converter with on-chip track-and-hold circuits. It is
optimized for low cost, low power, small size, and ease of use.
The product operates at a 100 MSPS conversion rate with
outstanding dynamic performance over its full operating range.
Each channel can be operated independently.
The Encode input is TTL/CMOS-compatible, and the 8-bit
digital outputs can be operated from 3.0 V (2.5 V to 3.6 V)
supplies. User-selectable options offer a combination of standby
modes, digital data formats, and digital data timing schemes. In
standby mode, the digital outputs are driven to a high
impedance state.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and an Encode clock for full-performance operation. No
external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS-compatible,
and a separate output power supply pin supports interfacing
with 3.3 V or 2.5 V logic.
Fabricated on an advanced CMOS process, the AD9288 is
available in a 48-lead surface-mount plastic package (7 mm ×
7 mm, 1.4 mm LQFP) specified over the industrial temperature
range (–40°C to +85°C). The AD9288 is pin-compatible with
the 10-bit AD9218, facilitating future system migrations.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD9288
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing ......................................................................................... 14
User-Selectable Options ............................................................ 14
AD9218/AD9288 Customer PCB BOM...................................... 15
Evaluation Board ............................................................................ 16
Power Connector........................................................................ 16
Analog Inputs ............................................................................. 16
Voltage Reference ....................................................................... 16
Clocking....................................................................................... 16
Data Outputs............................................................................... 16
Data Format/Gain ...................................................................... 16
Timing ......................................................................................... 16
Troubleshooting.......................................................................... 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
Explanation of Test Levels........................................................... 4
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 12
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 14
Using the AD9288 ...................................................................... 14
Encode Input............................................................................... 14
Digital Outputs ........................................................................... 14
Analog Input ............................................................................... 14
Voltage Reference ....................................................................... 14
REVISION HISTORY
12/04—Rev. B to Rev. C
Change to Absolute Maximum Ratings......................................... 7
Replaced Evaluation Board Section ............................................. 16
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 21
2/02—Rev. A to Rev. B
Edits to ABSOLUTE MAXIMUM RATINGS .............................. 3
1/01—Rev. 0 to Rev. A
2/99—Revision 0: Initial Version
Rev. C | Page 2 of 24
AD9288
SPECIFICATIONS
VDD = 3.0 V; VD = 3.0 V, differential input; external reference, unless otherwise noted.
Table 1.
Test
Level
AD9288BST-100
Typ
AD9288BST-80
Typ
AD9288BST-40
Typ
Parameter
Temp
Min
Max
Min
Max
Min
Max
Unit
RESOLUTION
8
8
8
Bits
DC ACCURACY
Differential Nonlinearity
25°C
Full
I
ꢀ.5
ꢀ.5ꢀ
+1.25
1.5ꢀ
ꢀ.5
ꢀ.5ꢀ
+1.25
1.5ꢀ
ꢀ.5
ꢀ.5ꢀ
+1.25
1.5ꢀ
LSB
LSB
LSB
LSB
VI
I
Integral Nonlinearity
25°C
Full
+1.25
1.5ꢀ
+1.25
1.5ꢀ
+1.25
1.5ꢀ
VI
VI
I
No Missing Codes
Gain Error1
Full
Guaranteed
2.5
Guaranteed
2.5
Guaranteed
2.5
25°C
Full
–6
–8
+6
+8
–6
–8
+6
+8
–6
–8
+6
+8
% FS
% FS
ppm/°C
% FS
mV
VI
VI
V
V
Gain Tempco1
Gain Matching
Full
8ꢀ
1.5
15
8ꢀ
1.5
15
8ꢀ
1.5
15
25°C
25°C
Voltage Matching
ANALOG INPUT
Input Voltage Range (with
Full
Full
V
V
512
512
512
mV p-p
V
AIN
)
Respect to
Common-Mode Voltage
ꢀ.3 × ꢀ.3 × VD
VD
ꢀ.3 ×
VD
ꢀ.3 ×
VD
ꢀ.3 × VD
ꢀ.3 ×
VD
ꢀ.3 ×
VD
ꢀ.3 × VD
ꢀ.3 ×
VD
–ꢀ.2
+ꢀ.2
+35
+4ꢀ
1.3
–ꢀ.2
–35
–4ꢀ
1.2
+ꢀ.2
+35
+4ꢀ
1.3
–ꢀ.2
–35
–4ꢀ
1.2
+ꢀ.2
+35
+4ꢀ
1.3
Input Offset Voltage
25°C
Full
I
–35
–4ꢀ
1.2
1ꢀ
1ꢀ
1ꢀ
mV
VI
VI
VI
I
mV
Reference Voltage
Reference Tempco
Input Resistance
Full
1.25
1.25
13ꢀ
1ꢀ
1.25
13ꢀ
1ꢀ
V
Full
13ꢀ
ppm/°C
kΩ
25°C
Full
7
5
1ꢀ
13
16
7
5
13
16
7
5
13
16
VI
V
V
Input Capacitance
25°C
25°C
2
2
2
pF
Analog Bandwidth, Full
Power
475
475
475
MHz
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulse Width High (tEH)
Encode Pulse Width Low (tEL)
Aperture Delay (tA)
Full
VI
IV
IV
IV
V
1ꢀꢀ
8ꢀ
4ꢀ
MSPS
MSPS
ns
25°C
25°C
25°C
25°C
25°C
Full
1
1
1
4.3
4.3
1ꢀꢀꢀ
1ꢀꢀꢀ
5.ꢀ
5.ꢀ
1ꢀꢀꢀ
1ꢀꢀꢀ
8.ꢀ
8.ꢀ
1ꢀꢀꢀ
1ꢀꢀꢀ
ns
3ꢀꢀ
5
3ꢀꢀ
5
3ꢀꢀ
5
ps
Aperture Uncertainty (Jitter)
Output Valid Time (tV)2
V
ps rms
ns
VI
VI
2
3.ꢀ
4.5
2
3.ꢀ
4.5
2
3.ꢀ
4.5
Output Propagation Delay
Full
6.ꢀ
6.ꢀ
6.ꢀ
ns
2
(tPD
)
DIGITAL INPUTS
Logic 1 Voltage
Logic ꢀ Voltage
Logic 1 Current
Logic ꢀ Current
Input Capacitance
DIGITAL OUTPUTS3
Logic 1 Voltage
Logic ꢀ Voltage
POWER SUPPLY
Power Dissipation4
Standby Dissipation4, 5
Full
Full
Full
Full
25°C
VI
VI
VI
VI
V
2.ꢀ
2.ꢀ
2.ꢀ
V
ꢀ.8
1
ꢀ.8
1
ꢀ.8
1
V
µA
µA
pF
1
1
1
2.ꢀ
2.ꢀ
2.ꢀ
Full
Full
VI
VI
2.45
2.45
2.45
V
V
ꢀ.ꢀ5
ꢀ.ꢀ5
ꢀ.ꢀ5
Full
Full
25°C
VI
VI
I
18ꢀ
6
218
11
171
6
2ꢀ7
11
156
6
189
11
mW
mW
Power Supply Rejection
Ratio (PSRR)
8
2ꢀ
8
2ꢀ
8
2ꢀ
mV/V
Rev. C | Page 3 of 24
AD9288
Test
Level
AD9288BST-100
Typ
AD9288BST-80
Typ
AD9288BST-40
Typ
Parameter
Temp
Min
Max
Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE6
Transient Response
Overvoltage Recovery Time
25°C
25°C
V
V
2
2
2
2
2
2
ns
ns
Signal-to-Noise Ratio (SNR)
(without Harmonics)
fIN = 1ꢀ.3 MHz
fIN = 26 MHz
fIN = 41 MHz
25°C
25°C
25°C
I
I
I
47.5
47.5
47.ꢀ
47.5
47
44
47.5
dB
dB
dB
44
44
Signal-to-Noise Ratio
(SINAD) (with Harmonics)
fIN = 1ꢀ.3 MHz
fIN = 26 MHz
25°C
25°C
25°C
I
I
I
47
47
47
47
47
47
44
7.ꢀ
55
55
47
7.5
7ꢀ
6ꢀ
dB
dB
dB
44
7.ꢀ
55
55
fIN = 41 MHz
44
7.ꢀ
55
52
Effective Number of Bits
fIN = 1ꢀ.3 MHz
25°C
25°C
25°C
I
I
I
7.5
7.5
7.5
7.5
7.5
7.5
Bits
Bits
Bits
fIN = 26 MHz
fIN = 41 MHz
Second Harmonic Distortion
fIN = 1ꢀ.3 MHz
25°C
25°C
25°C
I
I
I
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
dBc
dBc
dBc
fIN = 26 MHz
fIN = 41 MHz
Third Harmonic Distortion
fIN = 1ꢀ.3 MHz
25°C
25°C
25°C
I
I
I
6ꢀ
6ꢀ
6ꢀ
6ꢀ
6ꢀ
6ꢀ
dBc
dBc
dBc
fIN = 26 MHz
fIN = 41 MHz
Two-Tone Intermod
Distortion (IMD)
fIN = 1ꢀ.3 MHz
25°C
V
6ꢀ
6ꢀ
6ꢀ
dBc
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference).
2 tV and tPD are measured from the 1.5 V level of the Encode input to the 1ꢀ%/9ꢀ% levels of the digital outputs swing. The digital output load during test is not to exceed
an ac load of 1ꢀ pF or a dc current of 4ꢀ µA.
3 Digital supply current based on VDD = 3.ꢀ V output drive with < 1ꢀ pF loading under dynamic test conditions.
4 Power dissipation measured under the following conditions: fS = 1ꢀꢀ MSPS, analog input is –ꢀ.7 dBFS, both channels in operation.
5 Standby dissipation calculated with Encode clock in operation.
6 SNR/harmonics based on an analog input voltage of –ꢀ.7 dBFS referenced to a 1.ꢀ24 V full-scale input range.
EXPLANATION OF TEST LEVELS
Level
Description
I
1ꢀꢀ% production tested.
II
1ꢀꢀ% production tested at 25°C and sample tested at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
III
IV
V
VI
1ꢀꢀ% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range;
1ꢀꢀ% production tested at temperature extremes for military devices.
Rev. C | Page 4 of 24
AD9288
TIMING DIAGRAMS
SAMPLE N
SAMPLE N + 1
SAMPLE N + 5
A
A, A B
IN IN
tA
SAMPLE N + 2
SAMPLE N + 3
SAMPLE N + 4
tEH
tEL
1/f
s
ENCODE A, B
tPD
tV
D7 –D0
A
A
B
DATA N – 4
DATA N – 4
DATA N – 3
DATA N – 3
DATA N – 2
DATA N – 1
DATA N
DATA N + 1
DATA N + 1
D7 –D0
B
DATA N – 2
DATA N – 1
DATA N
Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing
SAMPLE SAMPLE SAMPLE
SAMPLE
N + 3
SAMPLE
N + 4
N
N + 1
N + 2
A
A, A B
IN IN
tA
tEH
tEL
1/f
s
ENCODE A
ENCODE B
tPD
tV
D7 –D0
A
A
B
DATA N – 8
DATA N – 6
DATA N – 4
DATA N – 2
DATA N
DATA N + 2
D7 –D0
B
DATA N – 7
DATA N – 5
DATA N – 3
DATA N – 1
DATA N + 1
DATA N + 3
Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing
Rev. C | Page 5 of 24
AD9288
SAMPLE SAMPLE SAMPLE
SAMPLE
N + 3
SAMPLE
N + 4
N
N + 1
N + 2
A
A, A B
IN IN
tA
tEH
tEL
1/f
s
ENCODE A
ENCODE B
tPD
tV
D7 –D0
A
A
DATA N – 8
DATA N – 9
DATA N – 6
DATA N – 7
DATA N – 4
DATA N – 5
DATA N – 2
DATA N – 3
DATA N
DATA N + 2
DATA N + 1
D7 –D0
B
B
DATA N – 1
Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing
Rev. C | Page 6 of 24
AD9288
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
VD, VDD
Analog Inputs
Digital Inputs
VREF IN
Digital Output Current
Operating Temperature
Storage Temperature
Maximum Junction Temperature
Maximum Case Temperature
Thermal Impedance θja
4 V
Stresses above those listed under Absolute Maximum Ratings
–ꢀ.5 V to VD + ꢀ.5 V
–ꢀ.5 V to VDD + ꢀ.5 V
–ꢀ.5 V to VD + ꢀ.5 V
2ꢀ mA
–55°C to +125°C
–65°C to +15ꢀ°C
15ꢀ°C
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
15ꢀ°C
57°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4ꢀꢀꢀ V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 7 of 24
AD9288
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
GND
1
2
36
35
34
33
32
31
30
29
28
NC
PIN 1
A
A
A
A
IN
IDENTIFIER
NC
3
IN
GND
4
DFS
V
DD
5
REF
A
IN
GND
AD9288
6
REF
V
D
OUT
TOP VIEW
7
REF
B
V
D
IN
(Not to Scale)
8
S1
S2
B
GND
9
V
DD
10
11
12
A
A
27 GND
IN
B
26
25
NC
NC
IN
GND
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Figure 5. Pin Configuration
Table 3.
Pin No.
Name
Description
1, 12, 16, 27, 29, GND
32, 34, 45
Ground
2
3
AINA
AINA
DFS
REFINA
REFOUT
REFINB
S1
Analog Input for Channel A.
Analog Input for Channel A (Complementary).
4
5
6
7
8
9
1ꢀ
Data Format Select. Offset binary output available if set low. Twos complement output available if set high.
Reference Voltage Input for Channel A.
Internal Reference Voltage.
Reference Voltage Input for Channel B.
User Select 1. Refer to Table 4. Tied with respect to VD.
User Select 2. Refer to Table 4. Tied with respect to VD.
Analog Input for Channel B (Complementary).
Analog Input for Channel B.
S2
AINB
AINB
VD
ENCB
VDD
11
13, 3ꢀ, 31, 48
14
15, 28, 33, 46
17–24
25, 26, 35, 36
37–44
47
Analog Supply (3 V).
Clock Input for Channel B.
Digital Supply (3 V).
D7B–DꢀB Digital Output for Channel B.
NC Do Not Connect.
DꢀA–D7 A Digital Output for Channel A.
ENC A Clock Input for Channel A.
Rev. C | Page 8 of 24
AD9288
TYPICAL PERFORMANCE CHARACTERISTICS
0
72
68
64
60
56
52
48
44
40
ENCODE = 100MSPS
ENCODE RATE = 100MSPS
A
= 10.3MHz
IN
–10
–20
–30
–40
–50
–60
–70
–80
–90
SNR = 48.52dB
SINAD = 48.08dB
SECOND HARMONIC = –62.54dBc
THIRD HARMONIC = –63.56dBc
2ND
3RD
0
10
20
30
40
50
60
70
80
90
SAMPLE
MHz
Figure 9. Harmonic Distortion vs. AIN Frequency
Figure 6. Spectrum: fS = 100 MSPS, fIN = 10 MHz, Single-Ended Input
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
ENCODE = 100MSPS
ENCODE = 100MSPS
A
A
1 = 9.3MHz
A
= 41MHz
IN
IN
–10
–20
–30
–40
–50
–60
–70
–80
–90
2 = 10.3MHz
SNR = 47.87dB
SINAD = 46.27dB
SECOND HARMONIC = –54.10dBc
THIRD HARMONIC = –55.46dBc
IN
IMD = –60.0dBc
SAMPLE
SAMPLE
Figure 10. Two-Tone Intermodulation Distortion
Figure 7. Spectrum: fS = 100 MSPS, fIN = 41 MHz, Single-Ended Input
50
48
46
44
42
40
38
36
0
ENCODE = 100MSPS
ENCODE RATE = 100MSPS
A
= 76MHz
IN
–10
–20
–30
–40
–50
–60
–70
–80
–90
SNR = 47.1dB
SINAD = 43.2dB
SECOND
HARMONIC = –52.2dBc
THIRD HARMONIC = –51.5dBc
SNR
SINAD
0
10
20
30
40
50
60
70
80
90
SAMPLE
MHz
Figure 8. Spectrum: fS = 100 MSPS, fIN = 76 MHz, Single-Ended Input
Figure 11. SINAD/SNR vs. AIN Frequency
Rev. C | Page 9 of 24
AD9288
49
190
185
180
175
170
165
160
155
150
145
140
A
= 10.3MHz
A
= 10.3MHz
IN
SNR
IN
SINAD
48
47
46
45
30
40
50
60
70
80
90
100
110
0
10
20
30
40
50
60
70
80
90
100
MSPS
MSPS
Figure 12. SINAD/SNR vs. Encode Rate
Figure 15. Analog Power Dissipation vs. Encode Rate
50
46
42
38
34
30
48.0
47.5
47.0
46.5
46.0
45.5
45.0
44.5
44.0
43.5
A
= 10.3MHz
ENCODE RATE = 100MSPS
IN
SNR
IN
A
= 10.3MHz
SINAD
SNR
SINAD
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
–40
25
TEMPERATURE (°C)
85
ENCODE HIGH PULSE WIDTH (ns)
Figure 13. SINAD/SNR vs. Encode Pulse Width High
Figure 16. SINAD/SNR vs. Temperature
0.5
0
0.6
0.4
ENCODE RATE = 100MSPS
ENCODE RATE = 100MSPS
= 10.3MHz
A
IN
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
0.2
0
–3dB
–0.2
–0.4
–0.6
–0.8
–1.0
0
100
200
300
400
500
600
–40
25
TEMPERATURE (°C)
85
BANDWIDTH (MHz)
Figure 14. ADC Frequency Response: fS = 100 MSPS
Figure 17. ADC Gain vs. Temperature (with External 1.25 V Reference)
Rev. C | Page 1ꢀ of 24
AD9288
2.0
1.5
1.3
1.2
1.1
1.0
0.9
0.8
0.7
ENCODE = 100MSPS
V
= 3.0V
D
A
T
= 25°C
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
0.25
0.50
0.75
LOAD (mA)
1.00
1.25
1.50
1.75
CODE
Figure 20. Voltage Reference Out vs. Current Load
Figure 18. Integral Nonlinearity
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
CODE
Figure 19. Differential Nonlinearity
Rev. C | Page 11 of 24
AD9288
TEST CIRCUITS
V
D
V
DD
28kΩ
28kΩ
OUT
A
IN
A
IN
12kΩ
12kΩ
Figure 21. Equivalent Analog Input Circuit
Figure 24. Equivalent Digital Output Circuit
V
D
V
D
V
BIAS
REF
IN
OUT
Figure 22. Equivalent Reference Input Circuit
Figure 25. Equivalent Reference Output Circuit
V
D
ENCODE
Figure 23. Equivalent Encode Input Circuit
Rev. C | Page 12 of 24
AD9288
TERMINOLOGY
Output Propagation Delay
The delay between a 50% crossing of Encode and the time
when all output data bits are within valid logic levels.
Analog Bandwidth (Small Signal)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Aperture Delay
The delay between a 50% crossing of Encode and the instant at
which the analog input is sampled.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
Signal-to-Noise Ratio (SNR)
The deviation of any code from an ideal 1 LSB step.
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
Encode pulse should be left in Logic 1 state to achieve rated
performance; pulse width low is the minimum time Encode
pulse should be left in low state. At a given clock rate, these
specs define an acceptable Encode duty cycle.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Two-Tone Intermodulation Distortion Rejection
Two-Tone SFDR
Minimum Conversion Rate
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
The Encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The Encode rate at which parametric testing is performed.
Worst Harmonic
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in
dBc.
Rev. C | Page 13 of 24
AD9288
THEORY OF OPERATION
the input is overdriven. The nominal input range is 1.024 V p-p
centered at VD × 0.3.
The AD9288 ADC architecture is a bit-per-stage pipeline-type
converter utilizing switch capacitor techniques. These stages
determine the 5 MSBs and drive a 3-bit flash. Each stage
provides sufficient overlap and error correction, allowing
optimization of comparator accuracy. The input buffers are
differential, and both sets of inputs are internally biased. This
allows the most flexible use of ac or dc and differential or
single-ended input modes. The output staging block aligns the
data, carries out the error correction, and feeds the data to
output buffers. The set of output buffers are powered from a
separate supply, allowing adjustment of the output voltage
swing. There is no discernible difference in performance
between the two channels.
VOLTAGE REFERENCE
A stable and accurate 1.25 V voltage reference is built into the
AD9288 (REFOUT). In normal operation, the internal reference
is used by strapping Pins 5 (REFINA) and 7 (REFINB) to Pin 6
(REFOUT). The input range can be adjusted by varying the
reference voltage applied to the AD9288. No appreciable
degradation in performance occurs when the reference is
adjusted 5%. The full-scale range of the ADC tracks reference
voltage, which changes linearly.
TIMING
The AD9288 provides latched data outputs, with four pipeline
delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the Encode command (see Figure 2,
Figure 3, and Figure 4). The length of the output data lines and
loads placed on them must be minimized to reduce transients
within the AD9288. These transients can detract from the
converter’s dynamic performance.
USING THE AD9288
Good high speed design practices must be followed when
using the AD9288. To obtain maximum benefit, decoupling
capacitors should be physically as close as possible to the chip,
minimizing trace and via inductance between chip pins and
capacitor (0603 surface-mount capacitors are used on the
AD9288/PCB evaluation board). It is recommended to place a
0.1 µF capacitor at each power-ground pin pair for high
frequency decoupling, and to include one 10 µF capacitor for
local low frequency decoupling. The VREF IN pin should also
be decoupled by a 0.1 µF capacitor. It is also recommended to
use a split power plane and a contiguous ground plane (see the
Evaluation Board section). Data output traces should be short
(< 1 inch), minimizing on-chip noise at switching.
The minimum guaranteed conversion rate of the AD9288 is
1 MSPS. At clock rates below 1 MSPS, dynamic performance
degrades. Typical power-up recovery time after standby mode is
15 clock cycles.
USER-SELECTABLE OPTIONS
Two pins are available for a combination of operational modes.
These options allow the user to place both channels, excluding
the reference, into standby mode, or just the B channel. Both
modes place the output buffers and clock inputs into high
impedance states.
ENCODE INPUT
Any high speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A track-and-
hold circuit is essentially a mixer. Any noise, distortion, or
timing jitter on the clock is combined with the desired signal at
the A/D output. For that reason, considerable care has been
taken in the design of the Encode (Clock) input of the AD9288,
and the user is advised to give commensurate thought to the
clock source. The Encode input is fully TTL/CMOS-compatible.
The other option allows the user to skew the B channel output
data by 1/2 of a clock cycle. In other words, if two clocks are fed
to the AD9288 and are 180° out of phase, enabling the data
align allows Channel B output data to be available at the rising
edge of Clock A. If the same Encode clock is provided to both
channels and the data align pin is enabled, then output data
from Channel B is 180° out of phase with respect to Channel A.
If the same Encode clock is provided to both channels and the
data align pin is disabled, both outputs are delivered on the
same rising edge of the clock.
DIGITAL OUTPUTS
The digital outputs are TTL/CMOS-compatible for lower power
consumption. During standby, the output buffers transition to a
high impedance state. A data format selection option supports
either twos complement (set high) or offset binary output (set
low) formats.
Table 4. User-Selectable Options
S1 S2
Option
ꢀ
ꢀ
Standby Both Channels A and B.
ANALOG INPUT
ꢀ
1
1
1
ꢀ
1
Standby Channel B Only.
Normal Operation (Data Align Disabled).
Data Align Enabled (data from both channels avail-
able on rising edge of Clock A. Channel B data is
delayed a 1/2 clock cycle).
The analog input to the AD9288 is a differential buffer. For best
dynamic performance, impedance at AIN and
Special care was taken in the design of the analog input stage of
the AD9288 to prevent damage and corruption of data when
AIN
should match.
Rev. C | Page 14 of 24
AD9288
AD9218/AD9288 CUSTOMER PCB BOM
Table 5. Bill of Materials
No.
Qty.
Reference Designator
Device
Package
Value
Comments
1
29
C1, C3-C15, C2ꢀ, C21, C24,
C25, C27, C3ꢀ–C35, C39–C42
Capacitor
ꢀ6ꢀ3
ꢀ.1 µF
2
3
4
2
C2, C36
Capacitor
Capacitor
W-HOLE
ꢀ6ꢀ3
15 pF
1ꢀ µF
8138 out
7
C16–C19, C26, C37, C38
TAJD
28
E1, E2, E3, E4, E12–E3ꢀ,
E34–E38
W-HOLE
5
6
7
8
4
5
3
3
H1, H2, H3, H4
J1, J2, J3, J4, J5
P1, P4, P11
MTHOLE
MTHOLE
SMA
SMA
J2, J3, not placed
Wieland
4-pin power connector
4-pin power connector
Post
Z5.531.3425.ꢀ
25.6ꢀ2.5453.ꢀ
P1, P4, P11
Detachable
Connector
Wieland
9
1
4
9
P2, P31
8ꢀ-pin rt. angle male
Resistor
TSW-14ꢀ-ꢀ8-
L-D-RA
Samtec
1ꢀ
11
R1, R2, R32, R34
ꢀ6ꢀ3
ꢀ6ꢀ3
36 Ω
R1, R2, R32, R34,
not placed
R3, R7, R11, R14, R22, R23,
R24, R3ꢀ, R51
Resistor
5ꢀ Ω
R11, R22, R23,
R24, R3ꢀ, R51
not placed
12
17
R4, R5, R8, R9, R1ꢀ, R12, R13,
R2ꢀ, R33, R35, R36, R37, R4ꢀ,
R42, R43, R5ꢀ, R53
Resistor
ꢀ6ꢀ3
Zero Ω
R43, R5ꢀ
not placed
13
14
2
6
R6, R38
Resistor
Resistor
ꢀ6ꢀ3
ꢀ6ꢀ3
25 Ω
R6, R38
not placed
R15, R16, R18, R26, R29, R31
5ꢀꢀ Ω
R16, R29
not placed
15
16
17
2
R17, R25
R19, R27
Resistor
Resistor
Resistor
ꢀ6ꢀ3
ꢀ6ꢀ3
ꢀ6ꢀ3
525 Ω
4 kΩ
1 kΩ
2
12
R21, R28, R39, R41, R44,
R46–R49, R52, R54, R55
18
19
2ꢀ
21
22
23
2
1
2
2
4
2
T1, T2
Transformer
AD92882
ADT1-1WT
LQFP48
Minicircuits
7682ꢀ347ꢀG
U1
U2, U3
74LCX821
U5, U6
SN74VCX86
Resistor array
AD8138 op amp3
U7, U8, U9, U1ꢀ
U11, U12
CTS
47 Ω
1 P2, P3 are implemented as one physical 8ꢀ-pin connector SAMTEC TSW-14ꢀ-ꢀ8-L-D-RA.
2 AD9288/PCB populated with AD9288-1ꢀꢀ.
3 To use optional amp: place R22, R23, R3ꢀ, R24, R16, R29, remove R4, R36.
Rev. C | Page 15 of 24
AD9288
EVALUATION BOARD
CLOCKING
The AD9218/AD9288 customer evaluation board offers an easy
way to test the AD9218 or the AD9288. The compatible pinout
of the two parts facilitates the use of one PCB for testing either
part. The PCB requires power supplies, a clock source, and a
filtered analog source for most ADC testing required.
Each channel can be clocked by a common clock input at SMA
input ENCODE A/B. The channels can also be clocked
independently by a simple board modification. The clock input
should be a low jitter sine source for maximum performance.
POWER CONNECTOR
DATA OUTPUTS
Power is supplied to the board via a detachable 12-lead power
strip. The minimum 3 V supplies required to run the board are
VDD, VDL, and VDD. To allow the use of the optional amplifier
path, 5 V supplies are required.
The data outputs are latched on-board by two 10-bit latches and
drive an 8-pin connector which is compatible with the dual-
channel FIFO board available from Analog Devices. This board,
together with ADC analyzer software, can greatly simplify ADC
testing.
ANALOG INPUTS
DATA FORMAT/GAIN
The DFS/Gain pin can be biased for desired operation at the DFS
jumper located at the S1, S2 jumpers.
Each channel has an independent analog path that uses a
wideband transformer to drive the ADC differentially from a
single-ended sine source at the input SMAs. The transformer
paths can be bypassed to allow the use of a dc-coupled path by
using two AD8138 op amps with a simple board modification.
The analog input should be band-pass filtered to remove any
harmonics in the input signal and to minimize aliasing.
TIMING
Timing on each channel can be controlled if needed on the
PCB. Clock signals at the latches or the data ready signals that
go to the output 80-pin connector can be inverted if required.
Jumpers also allow for biasing of Pins S1 and S2 for power-
down and timing alignment control.
VOLTAGE REFERENCE
The AD9288 has an internal 1.25 V voltage reference; an
external reference for each channel can be used instead by
connecting two external voltage references at the power
connector and setting jumpers at E18 and E19. The evaluation
board is shipped configured for internal reference mode.
Rev. C | Page 16 of 24
AD9288
0 0 5 8 5 - 0 2 6
B
B
B
B
B
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
3 7
3 8
3 9
4 0
4 1
D 2
D 3
D 4
D 5
D 6
D 7
D 8
D 2 2 4
D 3 2 3
D 2
D 3
D 4
D 5
D 6
D 7
D 8
D 2
D 3
D 4
D 5
D 6
D 7
D 8
D 4
2 2
D 5 2 1
D 6
D 7
D 8
2 0
A
A
B
B
4 2
4 3
1 9
1 8
B
A
( M S B D ) 9
D 9
( M S B ) D 9
4 4
4 5
4 6
4 7
4 8
D 9
1 7
G N D
1 6
G N D
G N D
G N D
D D
D D
D D
D D
V
V
V
V
1 5
A
A
D
B
B
E N C
E N C
E N C
E N C
1 4
1 3
D
D
D
V
V
V
V
Figure 26. PCB Schematic
Rev. C | Page 17 of 24
AD9288
0 0 5 8 5 - 0 2 7
Figure 27. PCB Schematic (Continued)
Rev. C | Page 18 of 24
AD9288
Figure 28. Top Silkscreen
Figure 31. Split Power Plane
Figure 29. Top Routing
Figure 32. Bottom Routing
Figure 33. Bottom Silkscreen
Figure 30. Ground Plane
Rev. C | Page 19 of 24
AD9288
TROUBLESHOOTING
If the board does not seem to be working correctly, try the
following:
The AD9218/AD9288 evaluation board is provided as a design
example for customers of Analog Devices, Inc. ADI makes no
warranties, express, statutory, or implied, regarding
•
•
Verify power at the IC pins.
merchantability or fitness for a particular purpose.
Check that all jumpers are in the correct position for the
desired mode of operation.
•
•
Verify that VREF is at 1.23 V.
Try running Encode clock and analog inputs at low speeds
(20 MSPS/1 MHz) and monitor LCX821 outputs, DAC
outputs, and ADC outputs for toggling.
Rev. C | Page 2ꢀ of 24
AD9288
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
37
48
36
1
PIN 1
SEATING
PLANE
10°
6°
2°
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
VIEW A
7°
3.5
0°
25
12
°
13
24
0.15
0.05
SEATING
PLANE
0.27
0.22
0.17
0.08 MAX
COPLANARITY
0.50
BSC
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
Figure 34. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Options
48-Lead Low Profile Quad Flat Package
48-Lead Low Profile Quad Flat Package
48-Lead Low Profile Quad Flat Package
48-Lead Low Profile Quad Flat Package
48-Lead Low Profile Quad Flat Package
48-Lead Low Profile Quad Flat Package
48-Lead Low Profile Quad Flat Package
Evaluation Board
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
AD9288BST-4ꢀ
AD9288BSTZ-4ꢀ1
AD9288BSTZRL-4ꢀ1
AD9288BST-8ꢀ
AD9288BSTZ-8ꢀ1
AD9288BST-1ꢀꢀ
AD9288BSTZ-1ꢀꢀ1
AD9288/PCB
1 Z = Pb-free part.
Rev. C | Page 21 of 24
AD9288
NOTES
Rev. C | Page 22 of 24
AD9288
NOTES
Rev. C | Page 23 of 24
AD9288
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00585–0–12/04(C)
Rev. C | Page 24 of 24
相关型号：
©2020 ICPDF网 联系我们和版权申明