AD9381_技术文档

HDMI™ Display Interface

AD9381

FUNCTIONAL BLOCK DIAGRAM

R/G/B 8 × 3

FEATURES

Internal HDCP keys

HDMI interface

Supports high bandwidth digital content protection

RGB to YCbCr 2-way color conversion

1.8 V/3.3 V power supply

100-lead Pb-free LQFP

SCL

SDA

SERIAL REGISTER

YCbCr (4:2:2

OR 4:4:4)

AND

POWER MANAGEMENT

2

DATACK

HSOUT

VSOUT

R/G/B 8 × 3

RGB and YCbCr output formats

Digital video interface

OR YCbCr

Rx0+

Rx0–

2

DATACK

Rx1+

HDMI 1.1, DVI 1.0

150 MHz HDMI receiver

Supports high bandwidth digital content protection

(HDCP 1.1)

HSYNC

VSYNC

Rx1–

HDMI RECEIVER

Rx2+

DE

Rx2–

DE

RxC+

RxC–

RTERM

S/PDIF

Digital audio interface

8-CHANNEL

HDMI 1.1-compatible audio interface

S/PDIF (IEC90658-compatible) digital audio output

Multichannel I²S audio output (up to 8 channels)

2

I S

MCLK

LRCLK

DDCSDA

DDCSCL

HDCP

HDCP KEYS

APPLICATIONS

AD9381

Advanced TVs

HDTVs

Figure 1.

Projectors

LCD monitors

GENERAL DESCRIPTION

The AD9381 offers a high definition multimedia interface

(HDMI) receiver integrated on a single chip. Also included is

support for high bandwidth digital content protection (HDCP)

via an internal key storage.

Fabricated in an advanced CMOS process, the AD9381 is

provided in a space-saving, 100-lead, surface-mount, Pb-free

plastic LQFP and is specified over the 0°C to 70°C temperature

range.

The AD9381 contains an HDMI 1.0-compatible receiver and

supports all HDTV formats (up to 1080p) and display

resolutions up to SXGA (1280×1024 @ 75 Hz). The receiver

features an intrapair skew tolerance of up to one full clock cycle.

With the inclusion of HDCP, displays may now receive

encrypted video content. The AD9381 allows for authentication

of a video receiver, decryption of encoded data at the receiver,

and renewability of that authentication during transmission as

specified by the HDCP 1.1 protocol.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights ofthird parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9381

TABLE OF CONTENTS

Features .............................................................................................. 1

4:4:4 to 4:2:2 Filter...................................................................... 11

Audio PLL Setup......................................................................... 12

Audio Board Level Muting........................................................ 13

Output Data Formats................................................................. 13

2-Wire Serial Register Map ........................................................... 14

2-Wire Serial Control Register DetailS........................................ 26

Chip Identification..................................................................... 26

BT656 Generation...................................................................... 28

Macrovision................................................................................. 29

Color Space Conversion............................................................ 30

2-Wire Serial Control Port............................................................ 37

Data Transfer via Serial Interface............................................. 37

Serial Interface Read/Write Examples..................................... 38

PCB Layout Recommendations.................................................... 39

Power Supply Bypassing............................................................ 39

Outputs (Both Data and Clocks).............................................. 39

Digital Inputs .............................................................................. 39

Color Space Converter (CSC) Common Settings...................... 40

Outline Dimensions....................................................................... 42

Ordering Guide .......................................................................... 42

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Digital Interface Electrical Characteristics ............................... 3

Absolute Maximum Ratings............................................................ 5

Explanation of Test Levels........................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Design Guide..................................................................................... 9

General Description..................................................................... 9

Digital Inputs ................................................................................ 9

Serial Control Port ....................................................................... 9

Output Signal Handling............................................................... 9

Timing.............................................................................................. 10

VSYNC Filter and Odd/Even Fields ........................................ 10

HDMI Receiver........................................................................... 10

DE Generator.............................................................................. 10

REVISION HISTORY

10/05—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

AD9381

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V_DD, V_D= 3.3 V, DV_DD= PV_DD= 1.8 V, ADC clock = maximum.

Table 1.

AD9381KSTZ-100

Typ

AD9381KSTZ-150

Typ

Parameter

Temp

Test Level

Min

Max

Min

Max

Unit

DIGITAL INPUTS (5 V Tolerant)

Input Voltage, High (V_IH)

Input Voltage, Low (V_IL)

Input Current, High (I_IH)

Input Current, Low (I_IL)

Input Capacitance

Full

25°C

VI

V

2.6

V

μA

pF

0.8

−82

82

3

−82

82

3

DIGITAL OUTPUTS

Output Voltage, High (V_OH)

Output Voltage, Low (V_OL)

Duty Cycle, DATACK

Full

VI

V

V_DD− 0.1

45

V_DD− 0.1

45

V

%

0.4

55

0.4

55

50

Output Coding

Binary

THERMAL CHARACTERISTICS

θ_JA-Junction-to-Ambient

V

35

°C/W

DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS

V_DD= V_D= 3.3 V, DV_DD= PV_DD= 1.8 V, ADC clock = maximum.

Table 2.

AD9381KSTZ-150

AD9381KSTZ-100

Parameter

Test Level

Conditions

Min

Typ

Max

Min

Typ Max

Unit

RESOLUTION

8

Bit

DC DIGITAL I/O Specifications

High-Level Input Voltage, (V_IH)

Low-Level Input Voltage, (V_IL)

High-Level Output Voltage, (V_OH)

Low-Level Output Voltage, (V_OL)

DC SPECIFICATIONS

Output High Level

I_OHD, (V_OUT= V_OH)

Output Low Level

I_OLD, (V_OUT= V_OL)

DATACK High Level

V_OHC, (V_OUT= V_OH)

VI

2.5

V

0.8

0.1

0.8

0.1

V_DD− 0.1

IV

Output drive = high

Output drive = low

Output drive = high

Output drive = low

Output drive = high

Output drive = low

Output drive = high

Output drive = low

36

24

12

8

40

20

30

15

36

24

12

8

mA

mV

40

20

30

15

700

DATACK Low Level

V_OLC, (V_OUT= V_OL)

Differential Input Voltage, Single-

Ended Amplitude

75

700

75

POWER SUPPLY

V_DSupply Voltage

V_DDSupply Voltage

IV

V

3.15

1.7

3.3

1.8

80

3.47

347

1.9

100

100³

3.15

1.7

3.3

1.8

80

3.47

347

1.9

110

175³

V

mA

DV_DDSupply Voltage

PV_DDSupply Voltage

I_VDSupply Current (Typical Pattern)¹

I_VDDSupply Current (Typical

Pattern)²

1.7

V

40

55

Rev. 0 | Page 3 of 44

AD9381

AD9381KSTZ-150

Min Typ Max

AD9381KSTZ-100

Parameter

Test Level

Conditions

Min

Typ

Max

Unit

I_DVDDSupply Current (Typical

Pattern)^{1, 4}

V

88

110

145

mA

I_PVDDSupply Current (Typical

Pattern)¹

Power-Down Supply Current (I_PD)

AC SPECIFICATIONS

V

26

35

30

40

mA

VI

130

Intrapair (+ to −) Differential Input

IV

360

6

ps

Skew (T_DPS

Channel to Channel Differential

Input Skew (T_CCS

Low-to-High Transition Time for

Data and Controls (D_LHT

)

Clock

Period

ps

)

Output drive = high;

C_L= 10 pF

Output drive = low;

C_L= 5 pF

Output drive = high;

C_L= 10 pF

Output drive = low;

C_L= 5 pF

Output drive = high;

C_L= 10 pF

Output drive = low;

C_L= 5 pF

Output drive = high;

C_L= 10 pF

Output drive = low;

C_L= 5 pF

900

)

1300 ps

650 ps

1200 ps

850 ps

1250 ps

800 ps

1200 ps

Low-to-High Transition Time for

DATACK (D_LHT

)

High-to-Low Transition Time for

Data and Controls (D_HLT

)

High-to-Low Transition Time for

DATACK (D_HLT

)

Clock to Data Skew⁵(T_SKEW

Duty Cycle, DATACK⁵

DATACK Frequency (F_CIP)

)

IV

VI

–0.5

45

20

+2.0

–0.5

+2.0

55

150

ns

%

MHz

50

¹The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels.

²The typical pattern contains a gray scale area, output drive = high.

³Specified current and power values with a worst-case pattern (on/off).

⁴DATACK load = 10 pF, data load = 5 pF.

⁵Drive strength = high.

Rev. 0 | Page 4 of 44

AD9381

ABSOLUTE MAXIMUM RATINGS

Table 3.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_D

3.6 V

V_DD

3.6 V

DV_DD

1.98 V

PV_DD

1.98 V

Analog Inputs

Digital Inputs

V_Dto 0.0 V

5 V to 0.0 V

20 mA

−25°C to +85°C

−65°C to +150°C

150°C

EXPLANATION OF TEST LEVELS

Table 4.

Digital Output Current

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

Maximum Case Temperature

Level

Test

I

100% production tested.

II

100% production tested at 25°C and sample tested at

specified temperatures.

150°C

III

Sample tested only.

IV

Parameter is guaranteed by design and

characterization testing.

V

Parameter is a typical value only.

VI

100% production tested at 25°C; guaranteed by design

and characterization testing.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. 0 | Page 5 of 44

AD9381

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

GND

NC

GND

PIN 1

2

3

GREEN 7

GREEN 6

GREEN 5

GREEN 4

GREEN 3

GREEN 2

GREEN 1

GREEN 0

NC

4

V

D

5

NC

6

NC

7

GND

NC

8

9

V

D

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

V

NC

AD9381

DD

TOP VIEW

GND

BLUE 7

BLUE 6

BLUE 5

BLUE 4

BLUE 3

BLUE 2

BLUE 1

BLUE 0

MCLKIN

MCLKOUT

SCLK

GND

(Not to Scale)

PV

DD

GND

FILT

PV

DD

GND

PV

DD

LRCLK

GND

PU1

PU2

2

I S3

2

I S2

NC = NO CONNECT

Figure 2. Pin Configuration

Table 5. Complete Pinout List

Pin Type

Pin No.

81

Mnemonic

Function

Value

3.3 V CMOS

TMDS

V_DD

INPUTS

PWRDN

Rx0+

Rx0−

Rx1+

Rx1−

Power-Down Control

DIGITAL VIDEO DATA INPUTS

35

34

38

37

41

40

Digital Input Channel 0 True

Digital Input Channel 0 Complement

Digital Input Channel 1 True

Digital Input Channel 1 Complement

Digital Input Channel 2 True

Digital Input Channel 2 Complement

Digital Data Clock True

Rx2+

Rx2−

DIGITAL VIDEO CLOCK INPUTS 43

44

RxC+

RxC−

Digital Data Clock Complement

Outputs of Red Converter, Bit 7 is MSB

OUTPUTS

92 to 99

RED [7:0]

2 to 9

12 to 19

89

87

85

GREEN [7:0] Outputs of Green Converter, Bit 7 is MSB

V_DD

BLUE [7:0]

DATACK

HSOUT

VSOUT

SOGOUT

O/E FIELD

Outputs of Blue Converter, Bit 7 is MSB

Data Output Clock

HSYNC Output Clock (Phase-Aligned with DATACK)

VSYNC Output Clock (Phase-Aligned with DATACK)

SOG Slicer Output

86

84

Odd/Even Field Output

Rev. 0 | Page 6 of 44

AD9381

Pin Type

Pin No.

Mnemonic

Function

Value

REFERENCES

POWER SUPPLY

57

FILT

Connection for External Filter Components for Audio PLL

Analog Power Supply and DVI Terminators

PV_DD

3.3 V

80, 76, 72, 67, V_D

45, 33

100, 90, 10

59, 56, 54

48, 32, 30

V_DD

PV_DD

DV_DD

GND

Output Power Supply

PLL Power Supply

Digital Logic Power Supply

Ground

1.8 V to 3.3 V

1.8 V

0 V

CONTROL

HDCP

83

82

49

50

51

52

28

27

26

25

24

20

21

22

23

88

46

SDA

SCL

Serial Port Data I/O

3.3 V CMOS

Serial Port Data Clock

HDCP Slave Serial Port Data Clock

HDCP Slave Serial Port Data I/O

This should be pulled up to 3.3 V through a 10 kΩ resistor 3.3 V CMOS

DDCSCL

DDCSDA

PU2

PU1

AUDIO DATA OUTPUTS

S/PDIF

I²S0

S/PDIF Digital Audio Output

V_DD

I²S Audio (Channel 1, Channel 2)

I²S Audio (Channels 3, Channel 4)

I²S Audio (Channels 5, Channel 6)

I²S Audio (Channels 7, Channel 8)

External Reference Audio Clock In

Audio Master Clock Output

I²S1

I²S2

I²S3

MCLKIN

MCLKOUT

SCLK

LRCLK

DE

Audio Serial Clock Output

Data Output Clock for Left and Right Audio Channels

Data Enable

V_DD

DATA ENABLE

RTERM

3.3 V CMOS

500 Ω

RTERM

Sets Internal Termination Resistance

Table 6. Pin Function Descriptions

Mnemonic

INPUTS

Rx0+

Description

Digital Input Channel 0 True.

Rx0−

Rx1+

Digital Input Channel 0 Complement.

Digital Input Channel 1 True.

Rx1−

Rx2+

Digital Input Channel 1 Complement.

Digital Input Channel 2 True.

Rx2−

Digital Input Channel 2 Complement.

These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel

rate) from a digital graphics transmitter.

RxC+

RxC−

Digital Data Clock True.

Digital Data Clock Complement.

This clock pair receives a TMDS clock at 1× pixel data rate.

External Filter Connection.

FILT

For proper operation, the audio clock generator PLL requires an external filter. Connect the filter shown in

Figure 8 to this pin. For optimal performance, minimize noise and parasitics on this node. For more information

see the PCB Layout Recommendations section .

PWRDN

Power-Down Control/Three-State Control.

The function of this pin is programmable via Register 0x26 [2:1].

Rev. 0 | Page 7 of 44

AD9381

Mnemonic

OUTPUTS

HSOUT

Description

Horizontal Sync Output.

A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this output can

be programmed via serial bus registers. By maintaining alignment with DATACK and Data, data timing with

respect to horizontal sync can always be determined.

VSOUT

Vertical Sync Output.

The separated VSYNC from a composite signal or a direct pass through of the VSYNC signal. The polarity of this

output can be controlled via the serial bus bit (Register 0x24[6]).

O/E FIELD

Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced signal) is

odd or even. The polarity of this signal is programmable via Register 0x24[4].

SERIAL PORT

SDA

SCL

Serial Port Data I/O for Programming AD9381 Registers—I²C Address is 0x98.

Serial Port Data Clock for Programming AD9381 Registers.

DDCSDA

DDCSCL

PU2

Serial Port Data I/O for HDCP Communications to Transmitter—I²C Address is 0x74 or 0x76.

Serial Port Data Clock for HDCP Communications to Transmitter.

This should be pulled up to 3.3 V through a 10 kΩ resistor.

PU1

This should be pulled up to 3.3 V through a 10 kΩ resistor.

DATA OUTPUTS

Red [7:0]

Green [7:0]

Blue [7:0]

Data Output, Red Channel.

Data Output, Green Channel.

Data Output, Blue Channel.

The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed, but will be

different if the color space converter is used. When the sampling time is changed by adjusting the phase register,

the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship

among the signals is maintained.

DATA CLOCK OUTPUT

DATACK

Data Clock Output.

This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible

output clocks can be selected with Register 0x25[7:6]. These are related to the pixel clock (1/2× pixel clock, 1×

pixel clock, 2× frequency pixel clock, and a 90° phase shifted pixel clock). They are produced either by the

internal PLL clock generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of

DATACK can also be inverted via Register 0x24[0]. The sampling time of the internal pixel clock can be changed

by adjusting the phase register. When this is changed, the pixel-related DATACK timing is shifted as well. The

DATA, DATACK, and HSOUT outputs are all moved, so the timing relationship among the signals is maintained.

POWER SUPPLY¹

V_D(3.3 V)

Analog Power Supply.

These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible.

Digital Output Power Supply.

V_DD(1.8 V to 3.3 V)

A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply

transients (noise). These supply pins are identified separately from the V_Dpins so special care can be taken to

minimize output noise transferred into the sensitive analog circuitry. If the AD9381 is interfacing with lower

voltage logic, V_DDmay be connected to a lower supply voltage (as low as 1.8 V) for compatibility.

PV_DD(1.8 V)

Clock Generator Power Supply.

The most sensitive portion of the AD9381 is the clock generation circuitry. These pins provide power to the clock

PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to

these pins.

DV_DD(1.8 V)

GND

Digital Input Power Supply.

This supplies power to the digital logic.

Ground.

The ground return for all circuitry on chip. It is recommended that the AD9381 be assembled on a single solid

ground plane, with careful attention to ground current paths.

¹The supplies should be sequenced such that V_Dand V_DDare never less than 300 mV below DV_DD. At no time should DV_DDbe more than 300 mV greater than V_Dor V_DD.

Rev. 0 | Page 8 of 44

AD9381

DESIGN GUIDE

GENERAL DESCRIPTION

SERIAL CONTROL PORT

The AD9381 is a fully integrated solution for receiving DVI/

HDMI signals and is capable of decoding HDCP-encrypted

signals through connections to an internal EEPROM. The

circuit is ideal for providing an interface for HDTV monitors

or as the front end to high performance video scan converters.

The serial control port is designed for 3.3 V logic. However, it is

tolerant of 5 V logic signals.

OUTPUT SIGNAL HANDLING

The digital outputs operate from 1.8 V to 3.3 V (V_DD).

Power Management

Implemented in a high performance CMOS process, the

interface can capture signals with pixel rates of up to 150 MHz.

The AD9381 uses the activity detect circuits, the active interface

bits in the serial bus, the active interface override bits, the

power-down bit, and the power-down pin to determine the

correct power state. There are four power states: full-power,

seek mode, auto power-down, and power-down.

The AD9381 includes all necessary circuitry for decoding

TMDS signaling including those encrypted with HDCP. The

output data formatting includes a color space converter (CSC),

which accommodates any input color space and can output any

color space. All controls are programmable via a 2-wire serial

interface. Full integration of these sensitive mixed signal

functions makes system design straight-forward and less

sensitive to the physical and electrical environment.

Table 7 summarizes how the AD9381 determines which power

mode to use and which circuitry is powered on/off in each of

these modes. The power-down command has priority and then

the automatic circuitry. The power-down pin (Pin 81—polarity

set by Register 0x26[3]) can drive the chip into four power-

down options. Bit 2 and Bit1 of Register 0x26 control these four

options. Bit 0 controls whether the chip is powered down or the

outputs are placed in high impedance mode (with the exception

of SOG). Bit 7 to Bit 4 of Register 0x26 control whether the

outputs, SOG, Sony Philips digital interface (S/PDIF ) or Inter-

IC sound bus (I²S or IIS) outputs are in high impedance mode

or not. See the 2-Wire Serial Control Register Detail section for

more details.

DIGITAL INPUTS

The digital control inputs (I²C) on the AD9381 operate to 3.3 V

CMOS levels. In addition, all digital inputs, except the TMDS

(HDMI/DVI) inputs, are 5 V tolerant (applying 5 V to them

does not cause damage). The TMDS input pairs (Rx0+/Rx0−,

Rx1+/Rx1−, Rx2+/Rx2−, and RxC+/RxC−) must maintain a

100 Ω differential impedance (through proper PCB layout)

from the connector to the input where they are internally

terminated (50 Ω to 3.3 V). If additional ESD protection is

desired, use of a California Micro Devices (CMD) CM1213

(among others) series low capacitance ESD protection offers

8 kV of protection to the HDMI TMDS lines.

Table 7. Power-Down Mode Descriptions

Inputs

Sync Detect²

Mode

Power-Down¹

Auto PD Enable³

Power-On or Comments

Full Power

Seek Mode

Power-Down

1

0

1

0

X

0

1

Everything

Serial bus, sync activity detect, SOG, band gap reference

¹Power-down is controlled via Bit 0 in Serial Bus Register 0x26.

²Sync detect is determined by OR’ing Bits 7 to Bit 2 in Serial Bus Register 0x15.

³Auto power-down is controlled via Bit 7 in Serial Bus Register 0x27.

Rev. 0 | Page 9 of 44

AD9381

TIMING

SYNC SEPARATOR THRESHOLD

FIELD 1

FIELD 0

FIELD 1

FIELD 0

The output data clock signal is created so that its rising edge

always occurs between data transitions and can be used to latch

the output data externally.

QUADRANT

HSIN

2

3

4

1

2

3

4

1

VSIN

VSYOUT

Figure 3 shows the timing operation of the AD9381.

t_PER

O/E FIELD

t_DCYCLE

ODD FIELD

Figure 5. VSYNC Filter—Odd/Even

DATACK

HDMI RECEIVER

t_SKEW

The HDMI receiver section of the AD9381 allows the reception

of a digital video stream, which is backward compatible with

DVI and able to accommodate not only video of various for-

mats (RGB, YCrCb 4:4:4, 4:2:2), but also up to eight channels of

audio. Infoframes are transmitted carrying information about

the video format, audio clocks, and many other items necessary

for a monitor to use fully the information stream available.

DATA

HSOUT

Figure 3. Output Timing

VSYNC FILTER AND ODD/EVEN FIELDS

The VSYNC filter eliminates spurious VSYNCs, maintains a

consistent timing relationship between the VSYNC and HSYNC

output signals, and generates the odd/even field output.

The earlier digital visual interface (DVI) format was restricted

to an RGB 24-bit color space only. Embedded in this data

stream were HSYNCs, VSYNCs, and display enable (DE)

signals, but no audio information. The HDMI specification

allows transmission of all the DVI capabilities, but adds several

YCrCb formats that make the inclusion of a programmable

color space converter (CSC) a very desirable feature. With this,

the scaler following the AD9381 can specify that it always

wishes to receive a particular format—for instance, 4:2:2

YCrCb—regardless of the transmitted mode. If RGB is sent, the

CSC can easily convert that to 4:2:2 YCrCb while relieving the

scaler of this task.

The filter works by examining the placement of VSYNC

with respect to HSYNC and, if necessary, slightly shifting

it in time at the VSOUT output. The goal is to keep the

VSYNC and HSYNC leading edges from switching at the

same time, eliminating confusion as to when the first line

of a frame occurs. Enabling the VSYNC filter is done with

Register 0x21[5]. Use of the VSYNC filter is recommended for

all cases, including interlaced video, and is required when using

the HSYNC per VSYNC counter. Figure 4 and Figure 5

illustrate even/odd field determination in two situations.

SYNC SEPARATOR THRESHOLD

In addition, the HDMI specification supports the transmission

of up to eight channels of S/PDIF or I²S audio. The audio

information is packetized and transmitted during the video

blanking periods along with specific information about the

clock frequency. Part of this audio information (audio

Infoframe) tells the user how many channels of audio are being

transmitted, where they should be placed, information

regarding the source (make, model), and other data.

FIELD 1

FIELD 0

FIELD 1

FIELD 0

QUADRANT

HSIN

2

3

4

1

2

3

4

1

VSIN

VSOUT

O/E FIELD

DE GENERATOR

EVEN FIELD

The AD9381 has an onboard generator for DE, for start of

active video (SAV) and for end of active video (EAV), all of

which is necessary for describing the complete data stream for a

BT656-compatible output. In addition to this particular output,

it is possible to generate the DE for cases in which a scaler is not

used. This signal alerts the following circuitry as to which are

displayable video pixels.

Figure 4.

Rev. 0 | Page 10 of 44

AD9381

One of the three channels is represented in Figure 6. In each

4:4:4 TO 4:2:2 FILTER

processing channel, the three inputs are multiplied by three

separate coefficients marked a1, a2, and a3. These coefficients

are divided by 4096 to obtain nominal values ranging from

–0.9998 to +0.9998. The variable labeled a4 is used as an offset

control. The CSC_Mode setting is the same for all three

processing channels. This multiplies all coefficients and offsets

The AD9381 contains a filter that allows it to convert a signal

from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the

maximum accuracy and fidelity of the original signal.

Input Color Space to Output Color Space

The AD9381 can accept a wide variety of input formats and

either retain that format or convert to another. Input formats

supported are:

by a factor of 2^CSC_Mode

.

The functional diagram for a single channel of the CSC, as

shown in Figure 6, is repeated for the remaining G and B

channels. The coefficients for these channels are b1, b2, b3, b4,

c1, c2, c3, and c4.

•

4:4:4 YCrCb 8-bit

4:2:2 YCrCb 8-bit, 10-bit, and 12-bit

RGB 8-bit

CSC_Mode[1:0]

a4[12:0]

+

a1[12:0]

Output modes supported are:

×4

×2

2

1

0

•

4:4:4 YCrCb 8-bit

1

4096

R

G

B

[11:0]

×

+

IN

R

[11:0]

OUT

4:2:2 YCrCb 8-bit, 10-bit, and 12-bit

Dual 4:2:2 YCrCb 8-bit

a2[12:0]

1

4096

×

Color Space Conversion (CSC) Matrix

a3[12:0]

The CSC matrix in the AD9381 consists of three identical

processing channels. In each channel, three input values are

multiplied by three separate coefficients. Also included are an

offset value for each row of the matrix and a scaling multiple for

all values. Each value has a 13-bit, twos complement resolution

to ensure the signal integrity is maintained. The CSC is

designed to run at speeds up to 150 MHz supporting resolu-

tions up to 1080p at 60 Hz. With any-to-any color space

support, formats such as RGB, YUV, YCbCr, and others are

supported by the CSC.

1

4096

×

Figure 6. Single CSC Channel

A programming example and register settings for several

common conversions are listed in the Color Space Converter

(CSC) Common Settings section.

For a detailed functional description and more programming

examples, please refer to the application note AN-795, AD9800

Color Space Converter User's Guide.

The main inputs, R_IN, G_IN, and B_INcome from the 8- to 12-bit

inputs from each channel. These inputs are based on the input

format detailed in Table 7. The mapping of these inputs to the

CSC inputs is shown in Table 8.

Table 8. CSC Port Mapping

Input Channel

CSC Input Channel

R/CR

Gr/Y

B/CB

R_IN

G_IN

B_IN

Rev. 0 | Page 11 of 44

AD9381

AUDIO PLL SETUP

Data contained in the audio infoframes, among other registers,

define for the AD9381 HDMI receiver not only the type of

audio, but the sampling frequency (f_S). The audio infoframe also

contains information about the N and CTS values used to

recreate the clock. With this information it is possible to

regenerate the audio sampling frequency. The audio clock is

regenerated by dividing the 20-bit CTS value into the TMDS

clock, then multiplying by the 20-bit N value. This yields a

multiple of the f_s(sampling frequency) of either 128 × f_sor

256 × f_s. It is possible for this to be specified up to 1024 × f_s.

In order to provide the most flexibility in configuring the audio

sampling clock, an additional PLL is employed. The PLL

characteristics are determined by the loop filter design, the PLL

charge pump current, and the VCO range setting. The loop

filter design is shown in Figure 8.

PV

D

C

Z

P

8nF

80nF

R

Z

1.5kΩ

FILT

SOURCE DEVICE

SINK DEVICE

Figure 8. PLL Loop Filter Detail

1

CTS

DIVIDE

BY

N

CYCLE

TIME

COUNTER

128 × f_S

To fully support all audio modes for all video resolutions up to

1080p, it is necessary to adjust certain audio-related registers

from their power-on default values. Table 9 describes these

registers and gives their recommended settings.

128 × f_S

MULTIPLY

DIVIDE

BY

CTS

TMDS

VIDEO

CLOCK

BY

N

CLOCK

1

N

REGISTER

N

1

N AND CTS VALUES ARE TRANSMITTED USING THE

AUDIO CLOCK REGENERATION PACKET. VIDEO

CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.

Figure 7. N and CTS for Audio Clock

Table 9. AD9398 Audio Register Settings

Register

Bits Recommended

Setting

Function

Comments

0x01

0x02

0x03

7:0

7:4

7:6

5:3

2

0x00

0x40

01

010

1

PLL Divisor (MSBs)

PLL Divisor (Lab’s)

VCO Range

Charge Pump Current

PLL Enable

The analog video PLL is also used for the audio clock

circuit when in HDMI mode. This is done automatically.

In HDMI mode, this bit enables a lower frequency to be

used for audio MCLK generation.

0x34

0x58

4

0

Audio Frequency Mode Override

PLL Enable

Allows the chip to determine the low frequency mode

of the audio PLL.

7

1

This enables the analog PLL to be used for audio MCLK

generation.

6:4

011

MCLK PLL Divisor

When the analog PLL is enabled for MCLK generation,

another frequency divider is provided. These bits set

the divisor to 4.

3

0

N/CTS Disable

The N and CTS values should always be enabled.

2:0

0**

MCLK Sampling Frequency

000 = 128 × f_S

001 = 256 × f_S

010 = 384 × f_S

011 = 512 × f_S

Rev. 0 | Page 12 of 44

AD9381

This information is the fundamental difference between DVI

AUDIO BOARD LEVEL MUTING

and HDMI transmissions and is located in read-only registers

R0x5A to R0xEE. In addition to this information, registers are

provided to indicate that new information has been received.

Registers with addresses ending in 0xX7 or 0xXF beginning at

R0x87 contain the new data flags (NDF) information. All of

these registers contain the same information and all are reset

once any of them are read. Although there is no external

interrupt signal, it is easy for the user to read any of these

registers and see if there is new information to be processed.

The audio can be muted through the infoframes or locally

via the serial bus registers. This can be controlled with

Register R0x57, Bits [7:4].

AVI Infoframes

The HDMI TMDS transmission contains Infoframes with

specific information for the monitor such as:

•

Audio information

•

2 to 8 channels of audio identified

OUTPUT DATA FORMATS

Audio coding

The AD9398 supports 4:4:4, 4:2:2, double data-rate (DDR),

and BT656 output formats. Register 0x25[3:0] controls the

output mode. These modes and the pin mapping are shown

in Table 10.

Audio sampling frequency

•

Speaker placement

N and CTS values (for reconstruction of the audio)

Muting

Source information

•

CD

SACD

•

DVD

•

Video information

•

Video ID code (per CEA861B)

Color space

Aspect ratio

Horizontal and vertical bar information

MPEG frame information (I, B, or P frame)

Vendor (transmitter source) name and product model

.

Table 10.

Port

Red

7

Green

Blue

Bit

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

4:4:4

Red/Cr [7:0]

Green/Y [7:0]

Y [7:0]

Blue/Cb [7:0]

DDR 4:2:2 ↑ CbCr ↓ Y, Y

4:2:2

CbCr [7:0]

1

4:4:4 DDR

DDR ↑ G [3:0]

DDR ↑ B [7:4]

DDR ↑ B [3:0]

DDR ↓ G [7:4]

DDR 4:2:2 ↑ CbCr [11:0]

DDR 4:2:2 ↓ Y,Y [11:0]

Y [11:0]

DDR ↓ R [7:0]

4:2:2 to 12

CbCr [11:0]

¹Arrows in the table indicate clock edge. Rising edge of clock = ↑, falling edge = ↓.

Rev. 0 | Page 13 of 44

AD9381

2-WIRE SERIAL REGISTER MAP

The AD9381 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to

write and read the control registers through the 2-wire serial interface port.

Table 11. Control Register Map

Hex

Address

Read/Write

or Read Only

Bits

[7:0]

[7:4]

[7:6]

[5:3]

[2]

Default Value

00000000

01101001

1101****

01******

Register Name

Chip Revision

PLL Divider MSB

PLL Divider

Description

0x00

0x01

0x02

0x03

Read

Chip revision ID. Revision is read [7:4]. [3:0].

PLL feedback divider value MSB.

PLL feedback divider value.

VCO range.

Charge pump current control for PLL.

This bit enables a lower frequency to be used for

audio MCLK generation

Read/Write

VCO Range

Charge Pump

PLL Enable

**001***

*****0**

0x11

Read/Write

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

[7]

[6]

[5]

[4]

0*******

*0******

**0*****

***0****

****0***

*****0**

******0*

*******0

1*******

*0******

**1*****

***0****

HSYNC Source

0 = HSYNC.

1 = SOG.

HSYNC Source Override

VSYNC Source

0 = auto HSYNC source.

1 = manual HSYNC source.

0 = VSYNC.

1 = VSYNC from SOG.

0 = auto HSYNC source.

1 = manual HSYNC source.

0 = Channel 0.

VSYNC Source Override

Channel Select

1 = Channel 1.

Channel Select Override

Interface Select

0 = autochannel select.

1 = manual channel select.

0 = analog interface.

1 = digital interface.

0 = auto-interface select.

1 = manual interface select.

0 = active low.

Interface Override

Input HSYNC Polarity

HSYNC Polarity Override

Input VSYNC Polarity

VSYNC Polarity Override

0x12

Read/Write

1 = active high.

0 = auto HSYNC polarity.

1 = manual HSYNC polarity.

0 = active low.

1 = active high.

0 = auto VSYNC polarity.

1 = manual VSYNC polarity.

MSB of HSYNCs per VSYNC.

HSYNCs per VSYNC count.

VSYNC duration.

0x17

0x18

0x22

0x23

Read

[3:0]

[7:0]

****0000

HSYNCs Per VSYNC MSB

HSYNCs Per VSYNC

VSYNC Duration

Read

00000000

Read/Write

4

32

HSYNC Duration

HSYNC duration. Sets the duration of the output

HSYNC in pixel clocks.

0x24

Read/Write

[7]

[6]

[5]

1*******

*1******

**1*****

HSYNC Output Polarity

VSYNC Output Polarity

DE Output Polarity

Output HSYNC polarity.

0 = active low out.

1 = active high out.

Output VSYNC polarity.

0 = active low out.

1 = active high out.

Output DE polarity.

0 = active low out.

1 = active high out.

Rev. 0 | Page 14 of 44

AD9381

Hex

Address

Read/Write

or Read Only

Bits

Default Value

Register Name

Description

[4]

***1****

Field Output Polarity

Output field polarity.

0 = active low out.

1 = active high out.

0 = don’t invert clock out.

1 = invert clock out.

[0]

*******0

01******

Output CLK Invert

Output CLK Select

0x25

Read/Write

[7:6]

Selects which clock to use on output pin. 1× CLK is

divided down from TMDS clock input when pixel

repetition is in use.

00 = ½× CLK.

01 = 1× CLK.

10 = 2× CLK.

11 = 90° phase 1× CLK.

[5:4]

[3:2]

**11****

****00**

Output Drive Strength

Output Mode

Sets the drive strength of the outputs.

00 = lowest, 11 = highest.

Selects the data output mapping.

00 = 4:4:4 mode (normal).

01 = 4:2:2 + DDR 4:2:2 on blue.

10 = DDR 4:4:4 + DDR 4:2:2 on blue.

11 = 12-bit 4:2:2 (HDMI option only).

Enables primary output.

[1]

[0]

******1*

*******0

Primary Output Enable

Secondary Output

Enable

Enables secondary output (DDR 4:2:2 in Output

Mode 1 and Mode 2).

0x26

Read/Write

[7]

[5]

[4]

[3]

0*******

**0*****

***0****

****1***

Output Three-State

SPDIF Three-State

I²S Three-State

Three-state the outputs.

Three-state the S/PDIF output.

Three-state the I²S output and the MCLK out.

Power-Down Pin Polarity Sets polarity of power-down pin.

0 = active low.

1 = active high.

[2:1]

*****00*

Power-Down Pin

Function

Selects the function of the power-down pin.

00 = power-down.

01 = power-down and three-state SOG.

10 = three-state outputs only.

11 = three-state outputs and SOG.

0 = normal.

[0]

[7]

*******0

1*******

Power-Down

1 = power-down.

0x27

Read/Write

Auto Power-Down

Enable

0 = disable auto low power state.

1 = enable auto low power state.

[6]

[5]

*0******

**0*****

HDCP A0

Sets the LSB of the address of the HDCP I²C.

Set to 1 only for a second receiver in a dual-link

configuration.

0 = use internally generated MCLK.

1 = use external MCLK input.

If an external MCLK is used, it must be locked to the

video clock according to the CTS and N available in

the I2C. Any mismatch between the internal MCLK

and the input MCLK results in dropped or repeated

audio samples.

MCLK External Enable

[4]

[3]

***0****

****0***

BT656 EN

Enables EAV/SAV codes to be inserted into the

video output data.

Allows use of the internal DE generator in DVI

mode.

Force DE Generation

Rev. 0 | Page 15 of 44

AD9381

Hex

Address

Read/Write

or Read Only

Bits

Default Value

Register Name

Description

[2:0]

*****000

Interlace Offset

Sets the difference (in HSYNCs) in field length

between Field 0 and Field 1.

0x28

0x29

Read/Write

[7:2]

011000**

VS Delay

Sets the delay (in lines) from the VSYNC leading

edge to the start of active video.

MSB, Register 0x29.

[1:0]

[7:0]

******01

HS Delay MSB

HS Delay

00000100

Sets the delay (in pixels) from the HSYNC leading

edge to the start of active video.

0x2A

0x2B

0x2C

0x2D

0x2E

Read/Write

[3:0]

[7:0]

[3:0]

[7:0]

[7]

****0101

00000000

****0010

11010000

0*******

Line Width MSB

Line Width

MSB, Register 0x2B.

Sets the width of the active video line in pixels.

MSB, Register 0x2D.

Screen Height MSB

Screen Height

Ctrl EN

Sets the height of the active screen in lines.

Allows Ctrl [3:0] to be output on the I²S data pins.

00 = I²S mode.

[6:5]

*00*****

I2S Out Mode

01 = right-justified.

10 = left-justified.

11 = raw IEC60958 mode.

[4:0]

[6]

[5]

***11000

*0******

**0*****

***0****

I2S Bit Width

TMDS Sync Detect

TMDS Active

AV Mute

Sets the desired bit width for right-justified mode.

Detects a TMDS DE.

Detects a TMDS clock.

Gives the status of AV mute based on general

control packets.

Returns 1 when read of EEPROM keys is successful.

Returns quality number based on DE edges.

0x2F

0x30

Read

[4]

[3]

[2:0]

[6]

****0***

*****000

*0******

HDCP Keys Read

HDMI Quality

HDMI Content Encrypted This bit is high when HDCP decryption is in use

(content is protected). The signal goes low when

HDCP is not being used. Customers can use this bit

to allow copying of the content. The bit should be

sampled at regular intervals because it can change

on a frame-by-frame basis.

[5]

[4]

[3:0]

**0*****

***0****

****0000

DVI HSYNC Polarity

DVI VSYNC Polarity

HDMI Pixel Repetition

Returns DVI HSYNC polarity.

Returns DVI VSYNC polarity.

Returns current HDMI pixel repetition amount.

0 = 1×, 1 = 2×, ... .The clock and data outputs

automatically de-repeat by this value.

0x31

0x32

Read/Write

[7:4]

[3:0]

[7]

1001****

****0110

0*******

*0******

MV Pulse Max

MV Pulse Min

MV Oversample En

MV Pal En

Sets the maximum pseudo sync pulse width for

Macrovision® detection.

Sets the minimum pseudo sync pulse width for

Macrovision detection.

Tells the Macrovision detection engine whether we

are oversampling or not.

Tells the Macrovision detection engine to enter PAL

mode.

[6]

[5:0]

[7]

**001101

1*******

MV Line Count Start

MV Detect Mode

Sets the start line for Macrovision detection.

0 = standard definition.

1 = progressive scan mode.

0 = use hard-coded settings for line counts and

pulse widths.

1 = use I²C values for these settings.

0x33

0x34

Read/Write

[6]

*0******

MV Settings Override

[5:0]

[7:6]

**010101

10******

MV Line Count End

MV Pulse Limit Set

Sets the end line for Macrovision detection.

Sets the number of pulses required in the last 3

lines (SD mode only).

[5]

**0*****

Low Freq Mode

Sets audio PLL to low frequency mode. Low

frequency mode should only be set for pixel clocks

<80 MHz.

Rev. 0 | Page 16 of 44

AD9381

Hex

Address

Read/Write

or Read Only

Bits

Default Value

Register Name

Description

[4]

***0****

Low Freq Override

Allows the previous bit to be used to set low

frequency mode rather than the internal auto-

detect.

[3]

****0***

Up Conversion Mode

0 = repeat Cr and Cb values.

1 = interpolate Cr and Cb values.

Enables the FIR filter for 4:2:2 CrCb output.

Enables the color space converter (CSC). The

default settings for the CSC provide HDT-to-RGB

conversion.

[2]

[1]

*****0**

******0*

CrCb Filter Enable

CSC_Enable

Sets the fixed-point position of the CSC

coefficients, including the A4, B4, and C4 offsets.

0x35

0x36

Read/Write

[6:5]

*01* ****

CSC_Mode

00 = 1.0, −4096 to 4095.

01 = 2.0, −8192 to 8190.

1× = 4.0, −16384 to 16380.

MSB, Register 0x36.

[4:0]

[7:0]

***01100

01010010

CSC_Coeff_A1 MSB

CSC_Coeff_A1 LSB

Color space converter (CSC) coefficient for

equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB, Register 0x38.

0x37

0x38

Read/Write

[4:0]

[7:0]

***01000

00000000

CSC_Coeff_A2 MSB

CSC_Coeff_A2 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB, Register 0x3A.

0x39

0x3A

Read/Write

[4:0]

[7:0]

***00000

00000000

CSC_Coeff_A3 MSB

CSC_Coeff_A3 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB, Register 0x3C.

0x3B

0x3C

Read/Write

[4:0]

[7:0]

***11001

11010111

CSC_Coeff_A4 MSB

CSC_Coeff_A4 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB, Register 0x3E.

0x3D

0x3E

Read/Write

[4:0]

[7:0]

***11100

01010100

CSC_Coeff_B1 MSB

CSC_Coeff_B1 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G

_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB, Register 0x40.

0x3F

0x40

Read/Write

[4:0]

[7:0]

***01000

00000000

CSC_Coeff_B2 MSB

CSC_Coeff_B2

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB, Register 0x42.

0x41

0x42

Read/Write

[4:0]

[7:0]

***11110

10001001

CSC_Coeff_B3 MSB

CSC_Coeff_B3 LSB

Color space converter (CSC) coefficient for

equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

Rev. 0 | Page 17 of 44

AD9381

Hex

Address

Read/Write

or Read Only

Bits

[4:0]

[7:0]

Default Value

***00010

Register Name

Description

0x43

0x44

Read/Write

CSC_Coeff_B4 MSB

CSC_Coeff_B4 LSB

MSB, Register 0x44.

10010010

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G

_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB, Register 0x46.

0x45

0x46

Read/Write

[4:0]

[7:0]

***00000

00000000

CSC_Coeff_C1 MSB

CSC_Coeff_C1 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB, Register 0x48.

0x47

0x48

Read/Write

[4:0]

[7:0]

***01000

00000000

CSC_Coeff_C2 MSB

CSC_Coeff_C2 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB, Register 0x4A.

0x49

0x4A

Read/Write

[4:0]

[7:0]

***01110

10000111

CSC_Coeff_C3 MSB

CSC_Coeff_C3 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB, Register 0x4C.

0x4B

0x4C

Read/Write

[4:0]

[7:0]

***11000

10111101

CSC_Coeff_C4 MSB

CSC_Coeff_C4 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

Must be written to 0x20 for proper operation.

0x50

0x56

Read/Write

[7:0]

00100000

00001111

Test

Must be written to default of 0x0F for proper

operation.

0x57

Read/Write

[7]

[6]

[3]

[2]

0*******

*0******

****0***

*****0**

A/V Mute Override

AV Mute Value

Disable Video Mute

Disable Audio Mute

MCLK PLL Enable

MCLK PLL_N

A1 overrides the AV mute value with Bit 6.

Sets AV mute value if override is enabled.

Disables mute of video during AV mute.

Disables mute of audio during AV mute.

MCLK PLL enable—uses analog PLL.

MCLK PLL N [2:0]—this controls the division of the

MCLK out of the PLL: 0 = /1, 1 = /2, 2 = /3, 3 = /4,

etc.

0x58

Read/Write

[7]

[6:4]

[3]

N_CTS_Disable

MCLK FS_N

Prevents the N/CTS packet on the link from writing

to the N and CTS registers.

Controls the multiple of 128 Fs, used for MCLK out .

0 = 128 f_S, 1 = 256 f_S, 2 = 384, 7 = 1024 f_S.

[2:0]

0x59

Read/Write

[6]

[5]

MDA/MCL PU

CLK Term O/R

This disables the MDA/MCL pull-ups.

Clock termination power-down override: 0 = auto,

1 = manual.

[4]

[2]

Manual CLK Term

FIFO Reset UF

Clock termination: 0 = normal, 1 = disconnected.

This bit resets the audio FIFO if underflow is

detected.

[1]

[0]

FIFO Reset OF

This bit resets the audio FIFO if overflow is

detected.

This bit three-states the MDA/MCL lines.

MDA/MCL Three-State

Rev. 0 | Page 18 of 44

AD9381

Hex

Address

Read/Write

or Read Only

Bits

Default Value

Register Name

Description

0x5A

Read

[6:0]

Packet Detected

These 7 bits are updated if any specific packet has

been received since last reset or loss of clock

detect. Normal is 0x00.

Bit Data Packet Detected

0

1

2

3

4

5

6

AVI infoframe.

Audio infoframe.

SPD infoframe.

MPEG source infoframe.

ACP packets.

ISRC1 packets.

ISRC2 packets.

0x5B

0x5E

Read

[3]

HDMI Mode

0 = DVI, 1 = HDMI.

[7:6]

[5:3]

Channel Status

Mode = 00. All others are reserved.

When Bit 1 = 0 (Linear PCM).

000 = 2 audio channels without pre-emphasis.

001 = 2 audio channels with 50/15 μs pre-

emphasis.

010 = reserved.

011 = reserved.

2

1

0 = software for which copyright is asserted.

1 = software for which no copyright is asserted.

0 = audio sample word represents linear PCM

samples.

1 = audio sample word used for other purposes.

0 = consumer use of channel status block.

0

Audio Channel Status

0x5F

0x60

Read

[7:0]

Channel Status Category

Code

[7:4]

[3:0]

[5:4]

Channel Number

Source Number

Clock Accuracy

0x61

Read

Clock accuracy.

00 = Level II.

01 = Level III.

10 = Level I.

11 = reserved.

0011 =32 kHz

0000 = 44.1 kHz

1000 = 88.2 kHz.

1100 = 176.4 kHz.

0010 = 48 kHz.

1010 = 96 kHz.

1110 = 192 kHz.

[3:0]

Sampling Frequency

Rev. 0 | Page 19 of 44

AD9381

Hex

Address

Read/Write

or Read Only

Bits

Default Value

Register Name

Description

0x62

Read

[3:0]

Word Length

Word length.

0000 not specified.

0100 = 16 bits.

0011 = 17 bits.

0010 = 18 bits.

0001 = 19 bits.

0101 = 20 bits.

1000 not specified.

1100 = 20 bits.

1011 = 21 bits.

1010 = 22 bits.

1001 = 23 bits.

1101 = 24 bits.

0x7B

Read

[7:0]

CTS [19:12]

Cycle time stamp—this 20-bit value is used with

the N value to regenerate an audio clock. For

remaining bits, see Register 0x7C and Register

0x7D.

0x7C

0x7D

Read

[7:0]

[7:4]

[3:0]

CTS [11:4]

CTS [3:0]

N [19:16]

20-bit N used with CTS to regenerate the audio

clock. For remaining bits, see Register 0x7E and

Register 0x7F.

0x7E

0x7F

Read

[7:0]

N [15:8]

N [7:0]

AVI Infoframe

AVI Infoframe Version

0x80

0x81

Read

[7:0]

[6:5]

Y [1:0] Indicates RGB, 4:2:2 or 4:4:4.

00 = RGB.

01 = YCbCr 4:2:2.

10 = YCbCr 4:4:4.

4

Active Format

Information Status

Active format information present.

0 = no data.

1 = active format information valid.

B [1:0].

[3:2]

Bar Information

00 = no bar information.

01 =horizontal bar information valid.

10 = vertical bar information valid.

11 = horizontal and vertical bar information valid.

S [1:0].

00 = no information.

01 = overscanned (television).

10 = underscanned (computer).

C [1:0].

[1:0]

[7:6]

[5:4]

Scan Information

Colorimetry

0x82

Read

00 = no data.

01 = SMPTE 170M, ITU601.

10 = ITU709.

Picture Aspect Ratio

M [1:0].

00 = no data.

01 = 4:3.

10 = 16:9.

Rev. 0 | Page 20 of 44

AD9381

Hex

Address

Read/Write

or Read Only

Bits

Default Value

Register Name

Description

[3:0]

Active Format Aspect

Ratio

R [3:0].

1000 = same as picture aspect ratio.

1001 = 4:3 (center).

1010 = 16:9 (center).

1011 = 14:9 (center).

SC [1:0].

0x83

Read

[1:0]

Nonuniform Picture

Scaling

00 = no known nonuniform scaling.

01 = picture has been scaled horizontally.

10 = picture has been scaled vertically.

11 = picture has been scaled horizontally and

vertically.

0x84

0x85

Read

[6:0]

[3:0]

Video Identification Code VIC [6:0] video identification code—refer to CEA

EDID short video descriptors.

Pixel Repeat

PR [3:0]—This specifies how many times a pixel has

been repeated.

0000 = no repetition (pixel sent once).

0001 = pixel sent twice (repeated once).

0010 = pixel sent 3 times.

1001 = pixel sent 10 times.

0xA—0xF reserved.

0x86

0x87

Read

[7:0]

[6:0]

Active Line Start LSB

New Data Flags

This represents the line number of the end of the

top horizontal bar. If 0, there is no horizontal bar.

Combines with Register 0x88 for a 16-bit value.

New data flags. These 8 bits are updated if any

specific data changes. Normal (no NDFs) is 0x00.

When any NDF register is read, all bits reset to 0x00.

All NDF registers contain the same data.

Bit Data Packet Changed

0

1

2

3

4

5

6

AVI infoframe.

Audio infoframe.

SPD infoframe.

MPEG source infoframe.

ACP packets.

ISRC1 packets.

ISRC2 packets.

0x88

0x89

Read

[7:0]

Active Line Start MSB

Active Line End LSB

Active line start MSB (see Register 0x86).

This represents the line number of the beginning of

a lower horizontal bar. If greater than the number

of active video lines, there is no lower horizontal

bar. Combines with Register 0x8A for a 16-bit value.

0x8A

0x8B

Read

[7:0]

Active Line End MSB

Active Pixel Start LSB

Active line end MSB. See Register 0x89.

This represents the last pixel in a vertical pillar bar

at the left side of the picture. If 0, there is no left

bar. Combines with Register 0x8C for a 16-bit value.

0x8C

0x8D

Read

[7:0]

Active Pixel Start MSB

Active Pixel End LSB

Active pixel start MSB. See Register 0x8B.

This represents the first horizontal pixel in a vertical

pillar-bar at the right side of the picture. If greater

than the maximum number of horizontal pixels,

there is no vertical bar. Combines with Register

0x8E for a16-bit value.

0x8E

0x8F

Read

[7:0]

[6:0]

Active Pixel End MSB

New Data Flags

Active pixel end MSB. See Register 0x8D.

New data flags (see 0x87).

Rev. 0 | Page 21 of 44

AD9381

Hex

Address

Read/Write

or Read Only

Bits

[7:0]

[7:4]

Default Value

Register Name

Description

0x90

0x91

Read

Audio Infoframe Version

Audio Coding Type

CT [3:0]. Audio coding type.

0x00 = refer to stream header.

0x01 = IEC60958 PCM.

0x02 = AC3.

0x03 = MPEG1 (Layer 1 and Layer 2).

0x04 = MP3 (MPEG1 Layer 3).

0x05 = MPEG2 (multichannel).

0x06 = AAC.

0x07 = DTS.

0x08 = ATRAC.

[2:0]

[4:2]

Audio Coding Count

Sampling Frequency

CC [2:0]. Audio channel count.

000 = refer to stream header.

001 = 2 channels.

010 = 3 channels.

111 = 8 channels.

0x92

Read

SF [2:0]. Sampling frequency.

000 = refer to stream header.

001 = 32 kHz.

010 = 44.1 kHz (CD).

011 = 48 kHz.

100 = 88.2 kHz.

101 = 96 kHz.

110 = 176.4 kHz.

111 = 192 kHz.

[1:0]

[7:0]

Sample Size

Max Bit Rate

SS [1:0]. Sample size.

00 = refer to stream header.

01 = 16-bit.

10 = 20-bit.

11 = 24-bit.

0x93

Read

Max bit rate (compressed audio only).The value of

this field multiplied by 8 kHz represents the

maximum bit rate.

0x94

0x95

Read

[7:0]

7

Speaker Mapping

Down-Mix

CA [7:0]. Speaker mapping or placement for up to 8

channels. See Table 33.

DM_INH—down-mix inhibit.

0 = permitted or no information.

1 = prohibited.

[6:3]

Level Shift

LSV [3:0]—level shift values with attenuation

information.

0000 = 0 dB attenuation.

0001 = 1 dB attenuation.

…..

1111 = 15 dB attenuation.

Reserved.

0x96

0x97

Read

[7:0]

[6:0]

New Data Flags

New data flags (see 0x87).

Rev. 0 | Page 22 of 44

AD9381

Hex

Address

Read/Write

or Read Only

Bits

Default Value

Register Name

Description

Source Product Description (SPD) Infoframe

0x98

0x99

Read

[7:0]

Source Product

Description (SPD)

Infoframe Version

[7:0]

Vendor Name

Character 1

Vendor name character 1 (VN1) 7-bit ASCII code.

The first character in 8 that is the name of the

company that appears on the product.

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

Read

[7:0]

[6:0]

[7:0]

VN2

VN2.

VN3

VN3.

VN4

VN4.

VN5

VN5.

VN6

VN6.

New Data Flags

New data flags (see 0x87).

VN7

VN8

VN7.

VN8.

Product Description

Character 1

Product Description Character 1 (PD1) 7-bit ASCII

code. The first character of 16 that contains the

model number and a short description.

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

Read

[7:0]

[6:0]

[7:0]

[6:0]

[7:0]

PD2

PD2.

PD3

PD3.

PD4

PD4.

PD5

PD5.

New Data Flags

PD6

New data flags (see 0x87).

PD6.

PD7

PD7.

PD8

PD8.

PD9

PD9.

PD10

PD10.

PD11

PD11.

PD12

PD12.

New Data Flags

PD13

New data flags (see 0x87).

PD13.

PD14

PD14.

PD15

PD15.

PD16

Source Device

Information Code

PD16.

This is a code that classifies the source device.

0x00 = unknown.

0x01 = digital STB.

0x02 = DVD.

0x03 = D-VHS.

0x04 = HDD video.

0x05 = DVC.

0x06 = DSC.

0x07 = video CD.

0x08 = game.

0x09 = PC general.

New data flags (see 0x87).

0xB7

Read

[6:0]

New Data Flags

Rev. 0 | Page 23 of 44

AD9381

Hex

Address

Read/Write

or Read Only

Bits

Default Value

Register Name

Description

MPEG Source Infoframe

0xB8

0xB9

Read

[7:0]

MPEG Source Infoframe

Version

MB(0)

MB [0] (Lower byte of MPEG bit rate: Hz). The lower

8 bits of 32 bits (4 bytes) that specify the MPEG bit

rate in Hz.

0xBA

0xBB

0xBC

Read

[7:0]

4

MB[1]

MB[2]

MB [1].

MB [2].

MB [3] (upper byte).

FR—New field or repeated field.

0 = New field or picture.

1 = Repeated field.

Field Repeat

MPEG Frame

0xBD

Read

[1:0]

MF [1:0] This identifies whether frame is an I, B, or P

picture.

00 = unknown.

01 = I picture.

10 = B picture.

11 = P picture.

0xBE

0xBF

0xC0

Read

[7:0]

[6:0]

[7:0]

Reserved.

New Data Flags

New data flags (see 0x87).

Audio content protection packet (ACP) type.

Audio Content

Protection Packet (ACP)

Type

0x00 = generic audio.

0x01 = IEC 60958-identified audio.

0x02 = DVD-audio.

0x03 = reserved for super audio CD (SACD).

0x04 = 0xFF reserved.

ACP Packet Byte 0 (ACP_PB0).

ACP_PB1.

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

Read

Rea

[7:0]

[6:0]

7

ACP Packet Byte 0

ACP_PB1

ACP_PB2

ACP_PB2.

ACP_PB3

ACP_PB3.

ACP_PB4

ACP_PB4.

Read

ACP_PB5

ACP_PB5.

NDF

New data flags (see 0x87).

ISRC1 Continued

International standard recording code (ISRC1)

continued. This indicates an ISRC2 packet is being

transmitted.

Read

6

ISRC1 Valid

0 = ISRC1 status bits and PBs not valid.

1 = ISRC1 status bits and PBs valid.

001 = starting position.

010 = intermediate position.

100 = final position.

ISRC1 Packet Byte 0 (ISRC1_PB0).

ISRC1_PB1.

[2:0]

ISRC1 Status

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

Read

[7:0]

[6:0]

[7:0]

ISRC1 Packet Byte 0

ISRC1_PB1

ISRC1_PB2

ISRC1_PB3

ISRC1_PB4

ISRC1_PB5

NDF

ISRC1_PB2.

ISRC1_PB3.

ISRC1_PB4.

ISRC1_PB5.

New data flags (see 0x87).

ISRC1_PB6.

ISRC1_PB6

ISRC1_PB7

ISRC1_PB7.

Rev. 0 | Page 24 of 44

AD9381

Hex

Address

Read/Write

or Read Only

Bits

[7:0]

[6:0]

[7:0]

Default Value

Register Name

ISRC1_PB8

Description

ISRC1_PB8.

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

Read

ISRC1_PB9

ISRC1_PB9.

ISRC1_PB10

ISRC1_PB11

ISRC1_PB12

NDF

ISRC1_PB10.

ISRC1_PB11.

ISRC1_PB12.

New data flags (see 0x87).

ISRC1_PB13.

ISRC1_PB14.

ISRC1_PB15.

ISRC1_PB16.

ISRC1_PB13

ISRC1_PB14

ISRC1_PB15

ISRC1_PB16

ISRC2 Packet Byte 0

ISRC2 Packet Byte 0 (ISRC2_PB0). This is transmitted

only when the ISRC_ continue bit (Register 0xC8,

Bit 7) is set to 1.

0xDD

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

0xEA

0xEB

0xEC

0xED

0xEE

Read

[7:0]

[6:0]

[7:0]

[6:0]

[7:0]

ISRC2_PB1

ISRC2_PB2

New Data Flags

ISRC2_PB3

ISRC2_PB4

ISRC2_PB5

ISRC2_PB6

ISRC2_PB7

ISRC2_PB8

ISRC2_PB9

New Data Flags

ISRC2_PB10

ISRC2_PB11

ISRC2_PB12

ISRC2_PB13

ISRC2_PB14

ISRC2_PB15

ISRC2_PB16

ISRC2_PB1.

ISRC2_PB2.

New data flags (see 0x87).

ISRC2_PB3.

ISRC2_PB4.

ISRC2_PB5.

ISRC2_PB6.

ISRC2_PB7.

ISRC2_PB8.

ISRC2_PB9.

New data flags (see 0x87).

ISRC2_PB10.

ISRC2_PB11.

ISRC2_PB12.

ISRC2_PB13.

ISRC2_PB14.

ISRC2_PB15.

ISRC2_PB16.

Rev. 0 | Page 25 of 44

AD9381

2-WIRE SERIAL CONTROL REGISTER DETAILS

CHIP IDENTIFICATION

0x12—Bit[4] VSYNC Polarity Override

0 = auto VSYNC polarity, 1 = manual VSYNC polarity. Manual

VSYNC polarity is defined in Register 0x11, Bit 5. The power-

up default is 0.

0x00—Bits[7:0] Chip Revision

An 8-bit value that reflects the current chip revision.

0x11—Bit[7] HSYNC Source

0x17—Bits[3:0] HSYNCs per VSYNC MSBs

0 = HSYNC, 1 = SOG. The power-up default is 0. These

selections are ignored if Register 0x11, Bit 6 = 0.

The 4 MSBs of the 12-bit counter that reports the number of

HSYNCs/VSYNC on the active input. This is useful in

determining the mode and an aid in setting the PLL divide

ratio.

0x11—Bit[6] HSYNC Source Override

0 = auto HSYNC source, 1 = manual HSYNC source. Manual

HSYNC source is defined in Register 0x11, Bit 7. The power-up

default is 0.

0x18—Bits[7:0] HSYNCs per VSYNC LSBs

The 8 LSBs of the 12-bit counter that reports the number of

HSYNCs/VSYNC on the active input.

0x11—Bit[5] VSYNC Source

0 = VSYNC, 1 = VSYNC from SOG. The power-up default is 0.

These selections are ignored if Register 0x11, Bit 4 = 0.

0x21—Bit[5] VSYNC Filter Enable

The purpose of the VSYNC filter is to guarantee the position of

the VSYNC edge with respect to the HSYNC edge and to

generate a field signal. The filter works by examining the

placement of VSYNC and regenerating a correctly placed

VSYNC one line later. The VSYNC is first checked to see

whether it occurs in the Field 0 position or the Field 1 position.

This is done by checking the leading edge position against the

sync separator threshold and the HSYNC position. The HSYNC

width is divided into four quadrants with Quadrant 1 starting at

the HSYNC leading edge plus a sync separator threshold. If the

VSYNC leading edge occurs in Quadrant 1 or Quadrant 4, the

field is set to 0 and the output VSYNC is placed coincident with

the HSYNC leading edge. If the VSYNC leading edge occurs in

Quadrant 2 or Quadrant 3, the field is set to 1 and the output

VSYNC leading edge is placed in the center of the line. In this

way, the VSYNC filter creates a predictable relative position

between HSYNC and VSYNC edges at the output.

0x11—Bit[4] VSYNC Source Override

0 = auto VSYNC source, 1 = manual VSYNC source. Manual

VSYNC source is defined in Register 0x11, Bit 5. The power-up

default is 0.

0x11—Bit[3] Channel Select

0 = Channel 0, 1 = Channel 1. The power-up default is 0. These

selections are ignored if Register 0x11, Bit 2 = 0.

0x11—Bit[2] Channel Select Override

0 = auto channel select, 1 = manual channel select. Manual

channel select is defined in Register 0x11, Bit 3. The power-up

default is 0.

0x11—Bit[1] Interface Select

0 = analog interface, 1 = digital interface. The power-up default

is 0. These selections are ignored if Register 0x11, Bit 0 = 0.

If the VSYNC occurs near the HSYNC edge, this guarantees

that the VSYNC edge follows the HSYNC edge. This performs

filtering also in that it requires a minimum of 64 lines between

VSYNCs. The VSYNC filter cleans up extraneous pulses that

might occur on the VSYNC. This should be enabled whenever

the HSYNC/VSYNC count is used. Setting this bit to 0 disables

the VSYNC filter. Setting this bit to 1 enables the VSYNC filter.

Power-up default is 0.

0x11—Bit[0] Interface Select Override

0 = auto interface select, 1 = manual interface select. Manual

interface select is defined in Register 0x11, Bit 1. The power-up

default is 0.

0x12—Bit[7] Input HSYNC Polarity

0 = active low, 1 = active high. The power-up default is 1. These

selections are ignored if Register 10x2, Bit 6 = 0.

0x21—Bit[4] VSYNC Duration Enable

0x12—Bit[6] HSYNC Polarity Override

This enables the VSYNC duration block that is designed to be

used with the VSYNC filter. Setting the bit to 0 leaves the

VSYNC output duration unchanged; setting the bit to 1 sets the

VSYNC output duration based on Register 0x22. The power-up

default is 0.

0 = auto HSYNC polarity, 1 = manual HSYNC polarity. Manual

HSYNC polarity is defined in Register 0x11, Bit 7. The power-

up default is 0.

0x12—Bit[5] Input VSYNC Polarity

0 = active low, 1 = active high. The power-up default is 1. These

selections are ignored if Register 0x11, Bit 4 = 0.

Rev. 0 | Page 26 of 44

AD9381

0x22—Bits[7:0] VSYNC Duration

0x25—Bits[5:4] Output Drive Strength

This is used to set the output duration of the VSYNC, and is

designed to be used with the VSYNC filter. This is valid only if

Register 0x21, Bit 4 is set to 1. Power-up default is 4.

These two bits select the drive strength for all the high speed

digital outputs (except VSOUT, A0 and O/E field). Higher drive

strength results in faster rise/fall times and in general makes it

easier to capture data. Lower drive strength results in slower

rise/fall times and helps to reduce EMI and digitally generated

power supply noise. The power-up default setting is 11.

0x23—Bits[7:0]HSYNC Duration

An 8-bit register that sets the duration of the HSYNC output

pulse. The leading edge of the HSYNC output is triggered by

the internally generated, phase-adjusted PLL feedback clock.

The AD9381 then counts a number of pixel clocks equal to the

value in this register. This triggers the trailing edge of the

HSYNC output, which is also phase-adjusted. The power-up

default is 32.

Table 13. Output Drive Strength

Output Drive

Result

00

01

10

11

Low output drive strength

Medium low output drive strength

Medium high output drive strength

High output drive strength

0x24—Bit[7] HSYNC Output Polarity

This bit sets the polarity of the HSYNC output. Setting this bit

to 0 sets the HSYNC output to active low. Setting this bit to 1

sets the HSYNC output to active high. Power-up default setting

is 1.

0x25—Bits[3:2] Output Mode

These bits choose between four options for the output mode,

one of which is exclusive to an HDMI input. 4:4:4 mode is

standard RGB; 4:2:2 mode is YCrCb, which reduces the number

of active output pins from 24 to 16; 4:4:4 is double data rate

(DDR) output mode; and the data is RGB mode that changes on

every clock edge. The power-up default setting is 00.

0x24—Bit[6] VSYNC Output Polarity

This bit sets the polarity of the VSYNC output (both DVI and

analog). Setting this bit to 0 sets the VSYNC output to active

low. Setting this bit to 1 sets the VSYNC output to active high.

Power-up default is 1.

Table 14. Output Mode

Output Mode

Result

00

01

4:4:4 RGB mode

4:2:2 YCrCb mode + DDR 4:2:2 on blue

(secondary)

0x24—Bit[5] Display Enable Output Polarity

This bit sets the polarity of the display enable (DE) for both

DVI and analog. 0 = DE output polarity is negative. 1 = DE

output polarity is positive.

10

11

DDR 4:4:4: DDR mode + DDR 4:2:2 on blue

(secondary)

12-bit 4:2:2 (HDMI option only)

The power-up default is 1.

0x25—Bit[1] Primary Output Enable

0x24—Bit[4] Field Output Polarity

This bit places the primary output in active or high impedance

mode. The primary output is designated when using either 4:2:2

or DDR 4:4:4. In these modes, the data on the red and green

output channels is the primary output, while the output data

on the blue channel (DDR YCrCb) is the secondary output.

0 = primary output is in high impedance mode. 1 = primary

output is enabled. The power-up default setting is 1.

This bit sets the polarity (both DVI and analog) of the field

output signal on Pin 21. 0 = active low out. 1 = active high out.

The power-up default is 1.

0x24—Bit[0] Output Clock Invert

This bit allows inversion of the output clock as specified by

Register 0x25, Bits 7 to 6. 0 = noninverted clock. 1 =inverted

clock .The power-up default setting is 0.

0x25—Bit[0] Secondary Output Enable

0x25—Bits[7:6] Output Clock Select

This bit places the secondary output in active or high

impedance mode. The secondary output is designated when

using either 4:2:2 or DDR 4:4:4. In these modes, the data on

the blue output channel is the secondary output while the

output data on the red and green channels is the primary

output. Secondary output is always a DDR YCrCb data mode.

The power-up default setting is 0. 0 = secondary output is in

high impedance mode. 1 = secondary output is enabled.

These bits select the clock output on the DATACLK pin. They

include 1/2× clock, a 2× clock, a 90° phase shifted clock or the

normal pixel clock. The power-up default setting is 01.

Table 12. Output Clock Select

Select

Result

00

01

10

11

½× pixel clock

1× pixel clock

2× pixel clock

90° phase 1× pixel clock

Rev. 0 | Page 27 of 44

AD9381

0x27—Bit[5] MCLK External Enable

0x26—Bit[7] Output Three-State

This bit enables the MCLK to be supplied externally. If an

external MCLK is used, then it must be locked to the video

clock according to the CTS and N available in the I²C. Any

mismatch between the internal MCLK and the input MCLK

results in dropped or repeated audio samples. 0 = use internally

generated MCLK. 1 = use external MCLK input. The power-up

default setting is 0.

When enabled, this bit puts all outputs (except SOGOUT)

in a high impedance state. 0 = normal outputs. 1 = all outputs

(except SOGOUT) in high impedance mode. The power-up

default setting is 0.

0x26—Bit[5] S/PDIF Three-State

When enabled, this bit places the S/PDIF audio output pins in a

high impedance state. 0 = normal S/PDIF output. 1 = S/PDIF

pins in high impedance mode. The power-up default setting

is 0.

BT656 GENERATION

0x27—Bit[4] BT656 Enable

This bit enables the output to be BT656 compatible with the

defined start of active video (SAV) and the end of active video

(EAV) controls to be inserted. These require specification of the

number of active lines, active pixels per line, and delays to place

these markers. 0 = disable BT656 video mode. 1 = enable BT656

video mode. The power-up default setting is 0.

0x26—Bit[4] I²S Three-State

When enabled, this bit places the I²S output pins in a high

impedance state. 0 = normal I²S output. 1 = I²S pins in high

impedance mode. The power-up default setting is 0.

0x26—Bit[3] Power-Down Polarity

0x27—Bit[3] Force DE Generation

This bit defines the polarity of the input power-down pin.

0 = power-down pin is active low. 1 = power-down pin is active

high. The power-up default setting is 1.

This bit allows the use of the internal DE generator in DVI

mode. 0 = internal DE generation disabled. 1 = force DE

generation via programmed registers. The power-up default

setting is 0.

0x26—Bits[2-1] Power-Down Pin Function

These bits define the different operational modes of the power-

down pin. These bits are functional only when the power-down

pin is active; when it is not active, the part is powered up and

functioning. 0 = chip is powered down and all outputs are in

high impedance mode. 1 = chip remains powered up, but all

outputs are in high impedance mode. The power-up default

setting is 00.

0x27—Bits[2:0] Interlace Offset

These bits define the offset in HSYNCs from Field 0 to Field 1.

The power-up default setting is 000.

0x28—Bits[7:2] VSYNC Delay

These bits set the delay (in lines) from the leading edge of

VSYNC to active video. The power-up default setting is 24.

0x26—Bit[0] Power-Down

0x28—Bits[1:0] HSYNC Delay MSBs

This bit is used to put the chip in power-down mode. In this

mode, the power dissipation is reduced to a fraction of the

typical power (see Table 1 for exact power dissipation). When in

power-down, the HSOUT, VSOUT, DATACK, and all 30 of the

data outputs are put into a high impedance state. Note that the

SOGOUT output is not put into high impedance. Circuit blocks

that continue to be active during power-down include the

voltage references, sync processing, sync detection, and the

serial register. These blocks facilitate a fast start-up from power-

down. 0 = normal operation. 1 = power-down. The power-up

default setting is 0.

Along with register 0x29, these ten bits set the delay (in pixels)

from the HSYNC leading edge to the start of active video. The

power-up default setting is 0x104.

0x29—Bits[7:0] HSYNC Delay LSBs

See the HSYNC Delay MSBs section.

0x2A—Bits[3:0] Line Width MSBs

Along with register 0x2B, these 12 bits set the width of the

active video line (in pixels). The power-up default setting is

0x500.

0x27—Bit[7] Auto Power-Down Enable

0x2B—Bits[7:0] Line Width LSBs

This bit enables the chip to go into low power mode, or seek

mode if no sync inputs are detected. 0 = auto power-down

disabled. 1 = chip powers down if no sync inputs present. The

power-up default setting is 1.

See the line width MSBs section.

0x2C—Bits[3:0] Screen Height MSBs

Along with register 0x2D, these 12 bits, set the height of the

active screen (in lines). The power-up default setting is 0x2D0.

0x27—Bit[6] HDCP A0 Address

This bit sets the LSB of the address of the HDCP I²C. This

should be set to 1 only for a second receiver in a dual-link

configuration. The power-up default is 0.

0x2D—Bits[7:0] Screen Height LSBs

See the Screen Height MSBs section.

Rev. 0 | Page 28 of 44

AD9381

0x2E—Bit[7] Ctrl Enable

0x30—Bit[5] DVI HSYNC Polarity

When set, this bit allows Ctrl [3:0] signals decoded from the

DVI to be output on the I²S data pins. 0 = I²S signals on I²S

lines. 1 = Ctrl [3:0] output on I²S lines. The power-up default

setting is 0.

This read-only bit indicates the polarity of the DVI HSYNC.

0 = DVI HSYNC polarity is low active. 1 = DVI HSYNC

polarity is high active.

0x30—Bit[4] DVI VSYNC Polarity

0x2E—Bits[6:5] I²S Output Mode

This read-only bit indicates the polarity of the DVI VSYNC.

0 = DVI VSYNC polarity is low active. 1 = DVI VSYNC polarity

is high active.

These bits select between four options for the I²S output: I²S,

right-justified, left-justified, or raw IEC60958 mode. The

power-up default setting is 00.

0x30—Bits[3:0] HDMI Pixel Repetition

Table 15. I²S Output Select

These read-only bits indicate the pixel repetition on DVI. 0 =

1×, 1 = 2×, 2 = 3×, up to a maximum repetition of 10× (0x9).

I²S Output Mode

Result

00

01

10

11

I²S mode

Table 16.

Right-justified

Left-justified

Raw IEC60958 mode

Select

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

Repetition Multiplier

1×

2×

3×

4×

5×

6×

7×

8×

9×

10×

0x2E—Bits[4:0] I²S Bit Width

These bits set the I²S bit width for right-justified mode. The

power-up default setting is 24 bits.

0x2F—Bit[6] TMDS Sync Detect

This read-only bit indicates the presence of a TMDS DE.

0 = no TMDS DE present. 1 = TMDS DE detected.

0x2F—Bit[5] TMDS Active

This read-only bit indicates the presence of a TMDS clock.

0 = no TMDS clock present. 1 = TMDS clock detected.

MACROVISION®

0x31—Bits[7:4] Macrovision Pulse Max

0x2F—Bit[4] AV Mute

These bits set the pseudo sync pulse width maximum for

Macrovision detection in pixel clocks. This is functional for

13.5 MHz SDTV or 27 MHz progressive scan. Power-up

default is 9.

This read-only bit indicates the presence of AV mute based on

general control packets. 0 = AV not muted. 1 = AV muted.

0x2F—Bit[3] HDCP Keys Read

0x31—Bits[3:0] Macrovision Pulse Min

This read-only bit reports if the HDCP keys were read

successfully. 0 = failure to read HDCP keys. 1 = HDCP keys

read.

These bits set the pseudo sync pulse width maximum for

Macrovision detection in pixel clocks. This is functional for

13.5 MHz SDTV or 27 MHz progressive scan. Power-up

default is 6.

0x2F—Bits[2:0] HDMI Quality

These read-only bits indicate a level of HDMI quality based on

the DE (display enable) edges. A larger number indicates a

higher quality.

0x32—Bit[7] Macrovision Oversample Enable

Tells the Macrovision detection engine whether oversampling is

used. This accommodates 27 MHz sampling for SDTV and 54

MHz sampling for progressive scan and is used as a correction

factor for clock counts. Power-up default is 0.

0x30—Bit[6] HDMI Content Encrypted

This read-only bit is high when HDCP decryption is in use

(content is protected). The signal goes low when HDCP is not

being used. Customers can use this bit to determine whether or

not to allow copying of the content. The bit should be sampled

at regular intervals since it can change on a frame by frame

basis. 0 = HDCP not in use. 1 = HDCP decryption in use.

0x32—Bit[6] Macrovision PAL Enable

Tells the Macrovision detection engine to enter PAL mode when

set to 1. Default is 0 for NTSC mode.

0x32—Bits[5:0] Macrovision Line Count Start

Set the start line for Macrovision detection. Along with

Register 0x33, Bits [5:0], they define the region where MV

pulses are expected to occur. The power-up default is Line 13.

Rev. 0 | Page 29 of 44

AD9381

0x33—Bit[7] Macrovision Detect Mode

0x35—Bits[6:5] Color Space Converter Mode

0 = standard definition. 1 = progressive scan mode.

These two bits set the fixed point position of the CSC

coefficients, including the A4, B4, and C4 offsets.

0x33—Bit[6] Macrovision Settings Override

Table 17. CSC Fixed Point Converter Mode

This defines whether preset values are used for the MV line

counts and pulse widths or the values stored in I²C registers.

0 = use hard-coded settings for line counts and pulse widths.

1 = use I²C values for these settings.

Select

Result

00

01

1×

1.0, −4096 to +4095

2.0, −8192 to +8190

4.0, −16384 to +16380

0x33—Bits[5:0] Macrovision Line Count End

Set the end line for Macrovision detection. Along with

Register 0x32, Bits [5:0], they define the region where MV

pulses are expected to occur. The power-up default is Line 21.

0x35—Bits[4:0] Color Space Conversion Coefficient A1

MSBs

These 5 bits form the 5 MSBs of the Color Space Conversion

Coefficient A1. This, combined with the 8 LSBs of the following

register, form a 13-bit, twos complement coefficient which is

user programmable. The equation takes the form of:

0x34—Bits[7:6] Macrovision Pulse Limit Select

Set the number of pulses required in the last three lines (SD

mode only). If there is not at least this number of MV pulses,

the engine stops. These 2 bits define these pulse counts:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

00 = 6

01 = 4

B

_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

10 = 5 (default)

11 = 7

The default value for the 13-bit, A1 coefficient is 0x0C52.

0x36—Bits[7:0] Color Space Conversion Coefficient A1

LSBs

0x34—Bit[5] Low Frequency Mode

Sets the audio PLL to low frequency mode. Low frequency

mode should only be set for pixel clocks < 80 MHz.

See the Register 0x35 section.

0x37—Bits[4:0] CSC A2 MSBs

0x34—Bit[4] Low Frequency Override

These five bits form the 5 MSBs of the Color Space Conversion

Coefficient A2. Combined with the 8 LSBs of the following

register, they form a 13-bit, twos complement coefficient that is

user programmable. The equation takes the form of:

Allows the previous bit to be used to set low frequency mode

rather than the internal auto-detect.

0x34—Bit[3] Up Conversion Mode

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

0 = repeat Cb/Cr values. 1 = interpolate Cb/Cr values.

0x34—Bit[2] CbCr Filter Enable

B

_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

Enables the FIR filter for 4:2:2 CbCr output.

The default value for the 13-bit, A2 coefficient is 0x0800.

COLOR SPACE CONVERSION

0x38—Bits[7:0] CSC A2 LSBs

The default power-up values for the color space converter

coefficients (R0x35 through R0x4C) are set for ATSC RGB-to-

YCbCr conversion. They are completely programmable for

other conversions.

See the Register 0x37 section.

0x39—Bits[4:0] CSC A3 MSBs

The default value for the 13-bit A3 is 0x0000.

0x34—Bit[1] Color Space Converter Enable

0x3A—Bits[7:0] CSC A3 LSBs

This bit enables the color space converter. 0 = disable color

space converter. 1 = enable color space converter. The power-up

default setting is 0.

0x3B—Bits[4:0] CSC A4 MSBs

The default value for the 13-bit A4 is 0x19D7.

0x3C—Bits[7:0] CSC A4 LSBs

0x3D—Bits[4:0] CSC B1 MSBs

The default value for the 13-bit B1 is 0x1C54.

0x3E—Bits[7:0] CSC B1 LSBs

0x3F—Bits[4:0] CSC B2 MSB

The default value for the 13-bit B2 is 0x0800.

Rev. 0 | Page 30 of 44

AD9381

0x40—Bits[7:0] CSC B2 LSBs

0x58—Bits[2:0] MCLK f_S_N

0x41—Bits[4-0] CSC B3 MSBs

These bits control the multiple of 128 f_Sused for MCLK out.

The default value for the 13-bit B3 is 0x1E89.

Table 19.

MCLK f_S_N [2:0]

f_SMultiple

128

256

384

512

640

768

896

1024

0x42—Bits[7:0] CSC B3 LSBs

0

1

2

3

4

5

6

7

0x43—Bits[4-0] CSC B4 MSBs

The default value for the 13-bit B4 is 0x0291.

0x44—Bits[7:0] CSC B4 LSBs

0x45—Bits[4-0] CSC C1 MSBs

The default value for the 13-bit C1 is 0x0000.

0x46—Bits[7:0] CSC C1 LSBs

0x47—Bits[4-0] CSC C2 MSBs

0x59—Bit[6] MDA/MCL PU Disable

The default value for the 13-bit C2 is 0x0800.

This bit disables the inter-MDA/MCL pull-ups.

0x48—Bits[7:0] CSC C2 LSBs

0x59—Bit[5] CLK Term O/R

0x49—Bits[4:0] CSC C3 MSBs

This bit allows for overriding during power down.

0 = auto, 1 = manual.

The default value for the 13-bit C3 is 0x0E87.

0x4A—Bits[7:0] CSC C3 LSBs

0x59—Bit[4] Manual CLK Term

0x4B—Bits[4:0] CSC C4 MSBs

This bit allows normal clock termination or disconnects this.

0 = normal, 1 = disconnected.

The default value for the 13-bit C4 is 0x18BD.

0x4C—Bits[7:0] CSC C4 LSBs

0x59—Bit[2] FIFO Reset UF

0x57—Bit[7] AV Mute Override

0x57—Bit[6] AV Mute Value

This bit resets the audio FIFO if underflow is detected.

0x59—Bit[1] FIFO Reset OF

0x57—Bit[3] Disable AV Mute

0x57—Bit[2] Disable Audio Mute

0x58—Bit[7] MCLK PLL Enable

This bit enables the use of the analog PLL.

This bit resets the audio FIFO if overflow is detected.

0x59—Bit[0] MDA/MCL Three-State

This bit three-states the MDA/MCL lines to allow in-circuit

programming of the EEPROM.

0x58—Bits[6:4] MCLK PLL_N

These bits control the division of the MCLK out of the PLL.

Table 18.

0x5A—Bits[6:0] Packet Detect

This register indicates if a data packet in specific sections has

been detected. These seven bits are updated if any specific

packet has been received since last reset or loss of clock detect.

Normal is 0x00.

PLL_N [2:0]

MCLK Divide Value

0

1

2

3

4

5

6

7

/1

/2

/3

/4

/5

/6

/7

/8

Table 20.

Packet Detect Bit

Packet Detected

AVI infoframe

Audio infoframe

SPD infoframe

MPEG source infoframe

ACP packets

0

1

2

3

4

5

6

0x58—Bit[3] N_CTS_Disable

ISRC1 packets

ISRC2 packets

This bit makes it possible to prevent the N/CTS packet on the

link from writing to the N and CTS registers.

0x5B—Bit[3] HDMI Mode

0 = DVI, 1 = HDMI.

Rev. 0 | Page 31 of 44

AD9381

0x5E—Bits[7:6] Channel Status Mode

0x5E—Bits[5:3] PCM Audio Data

0x81—Bits[1:0] Scan Information

Table 24.

S [1:0]

Scan Type

0x5E—Bit[2] Copyright Information

0x5E—Bit[1] Linear PCM Identification

0x5E—Bit[0] Use of Channel Status Block

0x5F—Bits[7:0] Channel Status Category Code

0x60—Bits[7:4] Channel Number

00

No information

01

10

Overscanned (television)

Underscanned (computer)

0x82—Bits[7:6] Colorimetry

Table 25.

0x60—Bits[3:0] Source Number

C [1:0]

Colorimetry

No data

SMPTE 170M, ITU601

ITU 709

0x61—Bits[5:4] Clock Accuracy

00

01

10

0x61—Bits[3:0] Sampling Frequency

Table 21.

Code

0x0

0x2

0x3

0x8

0xA

0xC

0xE

Frequency (kHz)

44.1

48

32

88.2

96

176.4

192

0x82—Bits[5:4] Picture Aspect Ratio

Table 26.

M[1:0]

Aspect Ratio

No data

4:3

00

01

10

16:9

0x62—Bits[3-0] Word Length

0x82—Bits[3:0] Active Format Aspect Ratio

Table 27.

R [3:0]

0x7B—Bits[7:0] CTS (Cycle Time Stamp) (19:12)

Active Format A/R

Same as picture aspect ratio (M [1:0])

4:3 (center)

These are the most significant 8 bits of a 20-bit word used in the

20-bit N term in the regeneration of the audio clock.

0x8

0x9

0x7C—Bits[7:0]CTS (11:4)

0x7D—Bits[7:4] CTS (3:0)

0x7D—Bits[3:0] N (19:16)

0xA

0xB

16:9 (center)

14:9 (center)

0x83—Bits[1:0] Nonuniform Picture Scaling

Table 28.

SC [1:0]

These are the most significant 4 bits of a 20-bit word used along

with the 20-bit CTS term to regenerate the audio clock.

Picture Scaling

0x80 AVI Infoframe Version

00

01

10

11

No known nonuniform scaling

Has been scaled horizontally

Has been scaled vertically

0x81—Bits[6:5] Y [1:0]

This register indicates whether data is RGB, 4:4:4, or 4:2:2.

Has been scaled both horizontally and vertically

Table 22.

Y

Video Data

RGB

YCbCr 4:2:2

YCbCr 4:4:4

0x84—Bits[6:0] Video ID Code

00

01

10

See CEA EDID short video descriptors.

0x85—Bits[3:0] Pixel Repeat

This value indicates how many times the pixel was repeated.

0x0 = no repeats, sent once; 0x8 = 8 repeats, sent 9 times; and

so on.

0x81—Bit[4] Active Format Information Present

0 = no data. 1 = active format information valid.

0x81—Bits[3:2] Bar Information

Table 23.

0x86—Bits[7:0] Active Line Start LSB

Combined with the MSB in Register 0x88, these bits indicate

the beginning line of active video. All lines before this comprise

a top horizontal bar. This is used in letter box modes. If the 2-

byte value is 0x00, there is no horizontal bar.

B

Bar Type

00

01

10

11

No bar information

Horizontal bar information valid

Vertical bar information valid

Horizontal and vertical bar information valid

Rev. 0 | Page 32 of 44

AD9381

0x87—Bits[6:0] New Data Flags (NDF)

0x91—Bits[7:4] Audio Coding Type

This register indicates whether data in specific sections has

changed. In the address space from 0x80 to 0xFF, each register

address ending in 0b111 (for example, 0x87, 0x8F, 0x97, 0xAF)

is an NDF register. They all have the same data and all are reset

upon reading any one of them.

These bits identify the audio coding so that the receiver may

process audio properly.

Table 30.

CT [3:0]

Audio Coding

Refer to stream header

IEC60958 PCM

AC-3

0x0

0x1

0x2

Table 29.

NDF Bit number

Changes Occurred

AVI infoframe

Audio infoframe

SPD infoframe

MPEG source infoframe

ACP packets

ISRC1 packets

0

1

2

3

4

5

6

0x3

0x4

0x5

0x6

MPEG1 (Layer 1 and Layer 2)

MP3 (MPEG1 Layer 3)

MPEG2 (multichannel)

AAC

0x7

DTS

0x8

ATRAC

ISRC2 packets

0x91—Bits[2:0] Audio Channel Count

0x88—Bits[7:0] Active Line Start MSB

These bits specify how many audio channels are being sent—

2 channels to 8 channels.

See Register 0x86.

0x89—Bits[7:0] Active Line End LSB

Table 31.

CC [2:0]

Channel Count

Combined with the MSB in Register 0x8A, these bits indicate

the last line of active video. All lines past this comprise a lower

horizontal bar. This is used in letter-box modes. If the 2-byte

value is greater than the number of lines in the display, there is

no lower horizontal bar.

000

001

010

011

100

101

110

111

Refer to stream header

2

3

4

5

6

7

8

0x8A—Bits[7:0] Active Line End MSB

See Register 0x89.

0x8B—Bits[7:0] Active Pixel Start LSB

Combined with the MSB in Register 0x8C, these bits indicate

the first pixel in the display that is active video. All pixels before

this comprise a left vertical bar. If the 2-byte value is 0x00, there

is no left bar.

0x92—Bits[4:2] Sampling Frequency

0x92—Bits[1:0] Ample Size

0x93—Bits[7:0] Max Bit Rate

For compressed audio only, when this value is multiplied by

8 kHz represents the maximum bit rate. A value of 0x08 in this

field yields a maximum bit rate of (8 kHz × 8 kHz = 64 kHz).

0x8C—Bits[7:0] Active Pixel Start MSB

See Register 0x8B.

0x8D—Bits[7:0] Active Pixel End LSB

0x94—Bits[7:0] Speaker Mapping

These bits define the suggested placement of speakers.

Table 32.

Combined with the MSB in Register 0x8E, these bits indicate

the last active video pixel in the display. All pixels past this

comprise a right vertical bar. If the 2-byte value is greater than

the number of pixels in the display, there is no vertical bar.

Abbreviation

Speaker Placement

FL

Front left

0x8E—Bits[7:0] Active Pixel End MSB

FC

Front center

FR

Front right

See Register 0x8D.

FCL

FCR

RL

Front center left

Front center right

Rear left

0x8F—Bits[6:0] NDF

See Register 0x87.

RC

RR

Rear center

Rear right

0x90—Bits[7:0] Audio Infoframe Version

RCL

RCR

LFE

Rear center left

Rear center right

Low frequency effect

Rev. 0 | Page 33 of 44

AD9381

Table 33.

CA

Bit 2

0

1

0

1

0

1

0

1

Channel Number

Bit 4

0

1

Bit 3

0

1

0

1

Bit 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Bit 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

–

Bit 3

–

LFE

–

LFE

–

LFE

–

LFE

–

LFE

–

LFE

–

LFE

–

LFE

–

LFE

–

LFE

v

LFE

–

LFE

–

LFE

–

LFE

v

LFE

–

Bit 2

FR

Bit 1

FL

–

FC

–

RC

RL

–

FC

–

RR

–

FC

–

RC

–

FC

–

RC

RRC

FRC

RLC

FLC

–

FC

–

v

–

FC

–

RC

RL

–

FC

–

FC

RR

1

LFE

0x95—Bit[7] Down-Mix Inhibit

0x95—Bits[6:3] Level Shift Values

0x9A—Bits[7:0] VN2

0x9B—Bits[7:0] VN3

0x9C—Bits[7:0] VN4

0x9D—Bits[7:0] VN5

0x9E—Bits[7:0] VN6

These bits define the amount of attenuation. The value directly

corresponds to the amount of attenuation: for example, 0000 =

0 dB, 0001 = 1 dB to 1111 = 15 dB attenuation.

0x9F—Bits[6:0] New Data Flags

0x96—Bits[7:0] Reserved

See Register 0x87 for a description.

0x97—Bits[6:0] New Data Flags

See Register 0x87 for a description.

0xA0—Bits[7:0] VN7

0xA1—Bits[7:0] VN8

0x98—Bits[7:0] Source Product Description (SPD)

Infoframe Version

0xA2—Bits[7:0] Product Description Character 1 (PD1)

0x99—Bits[7:0] Vender Name Character 1 (VN1)

This is the first character of 16 that contains the model number

and a short description of the product. The data characters are

7-bit ASCII code.

This is the first character in eight that is the name of the

company that appears on the product. The data characters are

7-bit ASCII code.

Rev. 0 | Page 34 of 44

AD9381

0xA3—Bits[7:0] PD2

0xBD—Bit[4] Field Repeat

0xA4—Bits[7:0] PD3

This defines whether the field is new or repeated. 0 = new field

or picture. 1 = repeated field.

0xA5—Bits[7:0] PD4

0xA6—Bits[7:0] PD5

0xBD—Bits[1:0] MPEG Frame

This identifies the frame as I, B, or P.

Table 35.

0xA7—Bits[6:0] New Data Flags

See Register 0x87 for a description.

0xA8—Bits[7:0] PD6

MF [1-0]

Frame Type

Unknown

I—picture

B—picture

P—picture

0xA9—Bits[7:0] PD7

00

01

10

11

0xAA—Bits[7:0] PD8

0xAB—Bits[7:0] PD9

0xAC—Bits[7:0] PD10

0xAD—Bits[7:0] PD11

0xAE—Bits[7:0] PD12

0xAF—Bits[6:0] New Data Flags

See Register 0x87 for a description.

0xBE—Bits[7:0] Reserved

0xBF—Bits[6:0] New Data Flags

See Register 0x87 for a description.

0xC0—Bits[7:0] AudioContentProtectionPacket(ACPType)

These bits define which audio content protection is used.

Table 36.

0xB0—Bits[7:0] PD13

0xB1—Bits[7:0] PD14

0xB2—Bits[7:0] PD15

Code

ACP Type

0xB3—Bits[7:0] PD16

0x00

Generic audio

0xB4—Bits[7:0] Source Device Information Code

These bytes classify the source device.

0x01

0x02

IEC 60958-identified audio

DVD-audio

0x03

0x04—0xFF

Reserved for super audio CD (SACD)

Reserved

Table 34.

SDI Code

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

Source

Unknown

Digital STB

DVD

D-VHS

HDD video

DVC

DSC

Video CD

Game

0xC1—ACP Packet Byte 0 (ACP_PB0)

0xC2—Bits[7:0] ACP_PB1

0xC3—Bits[7:0] ACP_PB2

0xC4—Bits[7:0] ACP_PB3

0xC5—Bits[7:0] ACP_PB4

0xC7—Bits[6:0] New Data Flags

See Register 0x87 for a description.

PC general

0xC8—Bit[7] International Standard Recording Code

(ISRC1) Continued

0xB7—Bits[6:0] New Data Flags

This bit indicates that a continuation of the 16 ISRC1 packet

bytes (an ISRC2 packet) is being transmitted.

See Register 0x87 for a description.

0xB8—Bits[7:0] MPEG Source Infoframe Version

0xB9—Bits[7:0] MPEG Bit Rate Byte 0 (MB0)

0xC8—Bit[6] ISRC1 Valid

This bit is an indication of the whether ISRC1 packet bytes are

valid. 0 = ISRC1 status bits and PBs not valid. 1 = ISRC1 status

bits and PBs valid.

The lower 8 of 32 bits that specify the MPEG bit rate in Hz.

0xBA—Bits[7:0] MB1

0xC8—Bits[2:0] ISRC Status

0xBB—Bits[7:0] MB2

0xBC—Bits[7:0] MB3—Upper Byte

These bits define where in the ISRC track the samples are: at

least two transmissions of 001 occur at the beginning of the

track, while continuous transmission of 010 occurs in the

middle of the track, followed by at least two transmissions of

100 near the end of the track.

Rev. 0 | Page 35 of 44

AD9381

0xC9—Bits[7:0] ISRC1 Packet Byte 0 (ISRC1_PB0)

0xCA—Bits[7:0] ISRC1_PB1

0xDD—Bits[7:0] ISRC2_PB1

0xDE—Bits[7:0] ISRC2_PB2

0xDF—Bits[6-0] New Data Flags

See Register 0x87 for a description.

0xCB—Bits[7:0] ISRC1_PB2

0xCC—Bits[7:0] ISRC1_PB3

0xCD—Bits[7:0] ISRC1_PB4

0xE0—Bits[7:0] ISRC2_PB3

0xE1—Bits[7:0] ISRC2_PB4

0xE2—Bits[7:0] ISRC2_PB5

0xE3—Bits[7:0] ISRC2_PB6

0xE4—Bits[7:0] ISRC2_PB7

0xE5—Bits[7:0] ISRC2_PB8

0xE6—Bits[7:0] ISRC2_PB9

0xE7—Bits[6:0] New Data Flags

See Register 0x87 for a description.

0xCE—Bits[7:0] ISRC1_PB5

0xCF—Bits[6:0] New Data Flags

See Register 0x87 for a description.

0xD0—Bits[7:0] ISRC1_PB6

0xD1—Bits[7:0] ISRC1_PB7

0xD2—Bits[7:0] ISRC1_PB8

0xD3—Bits[7:0] ISRC1_PB9

0xD4—Bits[7:0] ISRC1_PB10

0xD5—Bits[7:0] ISRC1_PB11

0xD6—Bits[7:0] ISRC1_PB12

0xD7—Bits[6:0] New Data Flags

See Register 0x87 for a description.

0xE8—Bits[7:0] ISRC2_PB10

0xE9—Bits[7:0] ISRC2_PB11

0xEA—Bits[7:0] ISRC2_PB12

0xEB—Bits[7:0] ISRC2_PB13

0xEC—Bits[7:0] ISRC2_PB14

0xED—Bits[7:0] ISRC2_PB15

0xEE—Bits[7:0] ISRC2_PB16

0xD8—Bits[7:0] ISRC1_PB13

0xD9—Bits[7:0] ISRC1_PB14

0xDA—Bits[7:0] ISRC1_PB15

0xDB—Bits[7:0] ISRC1_PB16

0xDC—Bits[7:0] ISRC2 Packet Byte 0 (ISRC2_PB0)

This is transmitted only when the ISRC continue bit (Register

0xC8 Bit 7) is set to 1.

Rev. 0 | Page 36 of 44

AD9381

2-WIRE SERIAL CONTROL PORT

A 2-wire serial interface control is provided in the AD9381. Up

to two AD9381 devices can be connected to the 2-wire serial

interface, with a unique address for each device.

DATA TRANSFER VIA SERIAL INTERFACE

For each byte of data read or written, the MSB is the first bit of

the sequence. If the AD9381 does not acknowledge the master

device during a write sequence, the SDA remains high so the

master can generate a stop signal. If the master device does not

acknowledge the AD9381 during a read sequence, the AD9381

interprets this as the end of data. The SDA remains high so the

master can generate a stop signal.

The 2-wire serial interface comprises a clock (SCL) and a

bidirectional data (SDA) pin. The analog flat panel interface

acts as a slave for receiving and transmitting data over the serial

interface. When the serial interface is not active, the logic levels

on SCL and SDA are pulled high by external pull-up resistors.

To write data to specific control registers of the AD9381, the 8-

bit address of the control register of interest must be written

after the slave address has been established. This control register

address is the base address for subsequent write operations. The

base address auto-increments by 1 for each byte of data written

after the data byte intended for the base address. If more bytes

are transferred than there are available addresses, the address

does not increment and remains at its maximum value. Any

base address higher than the maximum value does not produce

an acknowledge signal.

Data received or transmitted on the SDA line must be stable for

the duration of the positive-going SCL pulse. Data on SDA must

change only when SCL is low. If SDA changes state while SCL is

high, the serial interface interprets that action as a start or stop

sequence.

There are six components to serial bus operation:

•

Start signal

Slave address byte

Base register address byte

Data byte to read or write

Stop signal

Data are read from the control registers of the AD9381 in a

similar manner. Reading requires two data transfer operations:

•

The base address must be written with the R/ bit of the

W

Acknowledge (Ack)

slave address byte low to set up a sequential read

operation.

When the serial interface is inactive (SCL and SDA are high),

communications are initiated by sending a start signal. The start

signal is a high-to-low transition on SDA while SCL is high.

This signal alerts all slave devices that a data transfer sequence

is coming.

•

Reading (the R/ bit of the slave address byte high) begins

W

at the previously established base address. The address of

the read register auto-increments after each byte is

transferred.

The first 8 bits of data transferred after a start signal comprise a

To terminate a read/write sequence to the AD9381, a stop signal

must be sent. A stop signal comprises a low-to-high transition

of SDA while SCL is high.

7-bit slave address (the first 7 bits) and a single R/ bit (the 8th

bit). The R/ bit indicates the direction of data transfer, read

W

from (1) or write to (0) the slave device. If the transmitted slave

address matches the address of the device (set by the state of the

SA0 input pin as shown in Table 37), the AD9381 acknowledges

by bringing SDA low on the 9th SCL pulse. If the addresses do

not match, the AD9381 does not acknowledge.

W

A repeated start signal occurs when the master device driving

the serial interface generates a start signal without first genera-

ting a stop signal to terminate the current communication. This

is used to change the mode of communication (read, write)

between the slave and master without releasing the serial

interface lines.

Table 37. Serial Port Addresses

Bit 7

A₆(MSB)

1

Bit 6

Bit 5

Bit 4

Bit 3

A₂

1

Bit 2

A₁

0

Bit 1

A₀

0

A₅

0

A₄

0

A₃

1

SDA

t_BUFF

t_STAH

t_DSU

t_DHO

t_STOSU

t_STASU

t_DAL

SCL

t_DAH

Figure 9. Serial Port Read/Write Timing

Rev. 0 | Page 37 of 44

AD9381

SERIAL INTERFACE READ/WRITE EXAMPLES

Write to one control register:

Read from one control register:

•

Start signal

•

Start signal

Slave address byte (R/ bit = low)

W

Slave address byte (R/ bit = low)

W

•

Base address byte

Data byte to base address

Stop signal

•

Base address byte

Start signal

Slave address byte (R/ bit = high)

W

Data byte from base address

Stop signal

Write to four consecutive control registers:

•

Start signal

Slave address byte (R/ bit = low)

W

Read from four consecutive control registers:

Base address byte

•

Start signal

Data byte to base address

Data byte to (base address + 1)

Data byte to (base address + 2)

Data byte to (base address + 3)

Stop signal

Slave address byte (R/ bit = low)

W

•

Base address byte

Start signal

Slave address byte (R/ bit = high)

W

Data byte from base address

Data byte from (base address + 1)

Data byte from (base address + 2)

Data byte from (base address + 3)

Stop signal

SDA

SCL

BIT 7 BIT 6

BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ACK

Figure 10. Serial Interface—Typical Byte Transfer

Rev. 0 | Page 38 of 44

AD9381

PCB LAYOUT RECOMMENDATIONS

The AD9381 is a high precision, high speed digital device. To

achieve the maximum performance from the part, it is impor-

tant to have a well laid-out board. The following is a guide for

designing a board using the AD9381.

In some cases, using separate ground planes is unavoidable, so

it is recommend to place a single ground plane under the

AD9381. The location of the split should be at the receiver of

the digital outputs. In this case, it is even more important to

place components wisely because the current loops are much

longer, (current takes the path of least resistance). An example

of a current loop is power plane to AD9381 to digital output

trace to digital data receiver to digital ground plane to analog

ground plane.

POWER SUPPLY BYPASSING

It is recommended to bypass each power supply pin with a

0.1 μF capacitor. The exception is in the case where two or more

supply pins are adjacent to each other. For these groupings of

powers/grounds, it is only necessary to have one bypass

capacitor. The fundamental idea is to have a bypass capacitor

within about 0.5 cm of each power pin. Also, avoid placing the

capacitor on the opposite side of the PC board from the

AD9381, because that interposes resistive vias in the path.

OUTPUTS (BOTH DATA AND CLOCKS)

Try to minimize the trace length that the digital outputs have to

drive. Longer traces have higher capacitance, which require

more current that causes more internal digital noise.

The bypass capacitors should be physically located between the

power plane and the power pin. Current should flow from the

power plane to the capacitor to the power pin. Do not make the

power connection between the capacitor and the power pin.

Placing a via underneath the capacitor pads down to the power

plane is generally the best approach.

Shorter traces reduce the possibility of reflections.

Adding a series resistor of value 50 Ω to 200 Ω can suppress

reflections, reduce EMI, and reduce the current spikes inside

the AD9381. If series resistors are used, place them as close as

possible to the AD9381 pins (although try not to add vias or

extra length to the output trace to move the resistors closer).

It is particularly important to maintain low noise and good

stability of PV_DD(the clock generator supply). Abrupt changes

in PV_DDcan result in similarly abrupt changes in sampling clock

phase and frequency. This can be avoided by careful attention to

regulation, filtering, and bypassing. It is highly desirable to

provide separate regulated supplies for each of the analog

circuitry groups (V_Dand PV_DD).

If possible, limit the capacitance that each of the digital outputs

drives to less than 10 pF. This can be accomplished easily by

keeping traces short and by connecting the outputs to only one

device. Loading the outputs with excessive capacitance increases

the current transients inside of the AD9381 and creates more

digital noise on its power supplies.

DIGITAL INPUTS

Some graphic controllers use substantially different levels of

power when active (during active picture time) and when idle

(during HSYNC and VSYNC periods). This can result in a

measurable change in the voltage supplied to the analog supply

regulator, which can in turn produce changes in the regulated

analog supply voltage. This can be mitigated by regulating the

analog supply, or at least PV_DD, from a different, cleaner power

source (for example, from a 12 V supply).

The digital inputs on the AD9381 were designed to work with

3.3 V signals, but are tolerant of 5.0 V signals. Therefore, no

extra components need to be added if using 5.0 V logic.

Any noise that enters the HSYNC input trace can add jitter to

the system. Therefore, minimize the trace length and do not run

any digital or other high frequency traces near it.

It is recommended to use a single ground plane for the entire

board. Experience has shown repeatedly that the noise perfor-

mance is the same or better with a single ground plane. Using

multiple ground planes can be detrimental because each

separate ground plane is smaller and long ground loops can

result.

Rev. 0 | Page 39 of 44

AD9381

COLOR SPACE CONVERTER (CSC) COMMON SETTINGS

Table 38. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9381)

Register

Address

Value

Red/Cr Coeff 1

Red/Cr Coeff 2

Red/Cr Coeff 3

Red/Cr Offset

0x3C

0x35

0x0C

0x36

0x52

0x37

0x08

0x38

0x00

0x39

0x00

0x3A

0x00

0x3B

0x19

0xD7

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x1C

0x3F

0x08

0x41

0x3E

0x43

0x02

0x54

0x00

0x89

0x91

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x00

0x47

0x08

0x49

0x0E

0x4B

0x18

0x00

0x87

0xBD

Table 39. HDTV YCrCb (16 to 235) to RGB (0 to 255)

Register

Address

Value

Red/Cr Coeff 1

Red/Cr Coeff 2

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x3C

0x35

0x47

0x36

0x2C

0x37

0x04

0x38

0xA8

0x39

0x00

0x3B

0x1C

0x00

0x1F

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x1D

0x3F

0x04

0x41

0x1F

0x43

0x01

0xDD

0xA8

0x26

0x34

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x00

0x47

0x04

0x49

0x08

0x4B

0x1B

0x00

0xA8

0x75

0x7B

Table 40. SDTV YCrCb (0 to 255) to RGB (0 to 255)

Register

Address

Value

Red/Cr Coeff 1

Red/Cr Coeff 2

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x3C

0x35

0x2A

0x36

0xF8

0x37

0x08

0x38

0x00

0x39

0x00

0x3B

0x1A

0x00

0x84

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x1A

0x3F

0x08

0x41

0x1D

0x43

0x04

0x6A

0x00

0x50

0x23

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x00

0x47

0x08

0x49

0x0D

0x4B

0x19

0x00

0xDB

0x12

Table 41. SDTV YCrCb (16 to 235) to RGB (0 to 255)

Register

Address

Value

Red/Cr Coeff 1

Red/Cr Coeff 2

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x3C

0x35

0x46

0x36

0x63

0x37

0x04

0x38

0xA8

0x39

0x00

0x3B

0x1C

0x00

0x84

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x1C

0x3F

0x04

0x41

0x1E

0x43

0x02

0xC0

0xA8

0x6F

0x1E

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x00

0x47

0x04

0x49

0x08

0x4B

0x1B

0x00

0xA8

0x11

0xAD

Rev. 0 | Page 40 of 44

AD9381

Table 42. RGB (0 to 255) to HDTV YCrCb (0 to 255)

Register

Address

Value

Red/Cr Coeff 1

Red/Cr Coeff 2

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x35

0x08

0x36

0x2D

0x37

0x18

0x38

0x93

0x39

0x1F

0x3B

0x08

0x3C

0x00

0x3F

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x03

0x3F

0x0B

0x41

0x01

0x43

0x00

0x68

0x71

0x27

0x00

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x1E

0x47

0x19

0x49

0x08

0x4B

0x08

0x21

0xB2

0x2D

0x00

Table 43. RGB (0 to 255) to HDTV YCrCb (16 to 235)

Register

Address

Value

Red/Cr Coeff 1

Red/Cr Coeff 2

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x3C

0x35

0x07

0x36

0x06

0x37

0x19

0x38

0xA0

0x39

0x1F

0x3B

0x08

0x5B

0x00

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x02

0x3F

0x09

0x41

0x00

0x43

0x01

0xED

0xD3

0xFD

0x00

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x1E

0x47

0x1A

0x49

0x07

0x4B

0x08

0x64

0x96

0x06

0x00

Table 44. RGB (0 to 255) to SDTV YCrCb (0 to 255)

Register

Address

Value

Red/Cr Coeff 1

Red/Cr Coeff 2

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x3C

0x35

0x08

0x36

0x2D

0x37

0x19

0x38

0x27

0x39

0x1E

0x3B

0x08

0xAC

0x00

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x04

0x3F

0x09

0x41

0x01

0x43

0x00

0xC9

0x64

0xD3

0x00

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x1D

0x47

0x1A

0x49

0x08

0x4B

0x08

0x3F

0x93

0x2D

0x00

Table 45. RGB (0 to 255) to SDTV YCrCb (16 to 235)

Register

Address

Value

Red/Cr Coeff 1

Red/Cr Coeff 2

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x3C

0x35

0x07

0x36

0x06

0x37

0x1A

0x38

0x1E

0x39

0x1E

0x3B

0x08

0xDC

0x00

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x04

0x3F

0x08

0x41

0x01

0x43

0x01

0x1C

0x11

0x91

0x00

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x1D

0x47

0x1B

0x49

0x07

0x4B

0x08

0xA3

0x57

0x06

0x00

Rev. 0 | Page 41 of 44

AD9381

OUTLINE DIMENSIONS

16.00

BSC SQ

1.60 MAX

0.75

0.60

0.45

100

1

76

75

PIN 1

14.00

BSC SQ

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

0.08 MAX

COPLANARITY

25

51

50

0.15

0.05

26

SEATING

PLANE

0.27

0.22

0.17

VIEW A

0.50

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BED

Figure 11. 100-Lead Low Profile Quad Flat Package [LQFP]

(ST-100)

Dimensions shown in millimeters

ORDERING GUIDE

Max Speed (MHz)

Temperature

Model

Analog

Digital

100

150

Range

Package Description

Package Option

ST-100

AD9381KSTZ-100¹100

0°C to 70°C

100-Lead Low Profile Quad Flat Package (LQFP)

Evaluation Board

AD9381KSTZ-150¹

AD9381/PCB

150

¹Z = Pb-free part.

Rev. 0 | Page 42 of 44

AD9381

NOTES

Rev. 0 | Page 43 of 44

AD9381

NOTES

©

registered trademarks are the property of their respective owners.

D05689-0-10/05(0)

Rev. 0 | Page 44 of 44


型号：	AD9381
厂家：	ADI
描述：	HDMI Display Interface HDMI显示接口
文件：	总44页 (文件大小：738K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9381 [ADI]

相关型号：

AD9381/PCB

AD9381KSTZ-100

AD9381KSTZ-150

AD9387NK

AD9387NK/PCB

AD9387NKBBCZ-80

AD9387NKBBCZRL-80

AD9387NKBCPZ-80

AD9388A

AD9388ABSTZ-110

AD9388ABSTZ-110

AD9388ABSTZ-1101