AD9432BST-100 [ADI]
IC 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, PLASTIC, LQFP-52, Analog to Digital Converter;
| 型号： | AD9432BST-100 |
| 厂家： | 
ADI |
| 描述： | IC 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, PLASTIC, LQFP-52, Analog to Digital Converter 信息通信管理 转换器 |
| 文件： | 总16页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 80 MSPS/105 MSPS ADC
AD9432
FEATURES
GENERAL INTRODUCTION
On-chip reference and track-and-hold
On-chip input buffer
Power dissipation: 850 mW typical at 105 MSPS
500 MHz analog bandwidth
SNR: 67 dB @ 49 MHz AIN at 105 MSPS
SFDR: 80 dB @ 49 MHz AIN at 105 MSPS
2.0 V p-p analog input range
5.0 V supply operation
3.3 V CMOS/TTL outputs
Twos complement output format
The AD9432 is a 12-bit, monolithic sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit and is
optimized for high speed conversion and ease of use. The prod-
uct operates up to a 105 MSPS conversion rate with outstanding
dynamic performance over its full operating range.
The ADC requires only a single 5.0 V power supply and a 105 MHz
encode clock for full performance operation. No external refer-
ence or driver components are required for many applications.
The digital outputs are TTL-/CMOS-compatible, and a separate
output power supply pin supports interfacing with 3.3 V logic.
The encode input supports either differential or single-ended
mode and is TTL-/CMOS-compatible.
APPLICATIONS
Communications
Base stations and zero-IF subsystems
Wireless local loop (WLL)
Local multipoint distribution service (LMDS)
HDTV broadcast cameras and film scanners
Fabricated on an advanced BiCMOS process, the AD9432 is
available in a 52-lead low profile quad flat package (LQFP) and
in a 52-lead thin quad flat package (TQFP_EP). The AD9432 is
specified over the industrial temperature range of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
V
V
DD
CC
12
AIN
12
D11 TO D0
OR
PIPELINE
ADC
BUF
T/H
OUTPUT
STAGING
AIN
ENCODE
ENCODE
TIMING
REF
AD9432
GND
VREFOUT VREFIN
Figure 1.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
AD9432
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology.................................................................................... 11
Equivalent Circuits......................................................................... 12
Theory of Operation ...................................................................... 13
Analog Input ............................................................................... 13
Encode Input............................................................................... 13
Encode Voltage Level Definition.............................................. 13
Digital Outputs ........................................................................... 14
Voltage Reference ....................................................................... 14
Timing ......................................................................................... 14
Applications Information.............................................................. 15
Using the AD8138 to Drive the AD9432 ................................ 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
General Introduction ....................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
Explanation of Test Levels........................................................... 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
6/09—Rev. E to Rev. F
1/02—Rev. D to Rev. E
Updated Format..................................................................Universal
Reorganized Layout............................................................Universal
Added TQFP_EP Package.................................................Universal
Deleted LQFP_ED Package...............................................Universal
Changes to Thermal Characteristics Section................................ 6
Changes to Pin Configurations and Function Descriptions
Section................................................................................................ 7
Changes to Terminology Section.................................................. 11
Deleted Evaluation Board Section................................................ 15
Updated Outline Dimensions....................................................... 16
Changes to Ordering Guide .......................................................... 16
Edits to Specifications.......................................................................3
Edits to Absolute Maximum Ratings..............................................4
Edits to Ordering Guide ...................................................................4
Addition of Text to Using the AD9432 Section.......................... 10
Edits to Figure 17a.......................................................................... 15
Edits to Figure 17b ......................................................................... 16
Addition of SQ-52 Package Outline............................................. 18
Rev. F | Page 2 of 16
AD9432
SPECIFICATIONS
VDD = 3.3 V, VCC = 5.0 V; external reference; differential encode input, unless otherwise noted.
Table 1.
Test
Level
80 MSPS
Typ
105 MSPS
Typ
Parameter
Temp
Min
Max
Min
Max
Unit
RESOLUTION
12
12
Bits
DC ACCURACY
Differential Nonlinearity (DNL)
25°C
Full
25°C
Full
Full
25°C
Full
I
VI
I
VI
VI
I
−0.75
−1.0
−1.0
−1.5
0.25
0.5
0.5
1.0
Guaranteed
+2
+0.75
+1.0
+1.0
+1.5
−0.75
−1.0
−1.0
−1.5
0.25
0.5
0.5
1.0
Guaranteed
+2
+0.75
+1.0
+1.0
+1.5
LSB
LSB
LSB
LSB
Integral Nonlinearity (INL)
No Missing Codes
Gain Error1
Gain Tempco1
−5
+7
−5
+7
% FS
ppm/°C
V
150
150
ANALOG INPUTS (AIN, AIN)
Input Voltage Range
Common-Mode Voltage
Input Offset Voltage
Input Resistance
Full
Full
Full
Full
25°C
25°C
V
V
VI
VI
V
2
3.0
0
3
4
2
3.0
0
3
4
V p-p
V
mV
kΩ
pF
MHz
−5
2
+5
4
−5
2
+5
4
Input Capacitance
Analog Bandwidth, Full Power
ANALOG REFERENCE
Output Voltage
Tempco
Input Bias Current
V
500
500
Full
Full
Full
VI
V
VI
2.4
2.5
50
15
2.6
50
2.4
2.5
50
15
2.6
50
V
ppm/°C
μΑ
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulse Width High (tEH
Encode Pulse Width Low (tEL)
Aperture Delay (tA)
Full
Full
VI
IV
IV
IV
V
80
105
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
1
1
)
25°C
25°C
25°C
25°C
Full
Full
Full
Full
4.0
4.0
6.2
6.2
2.0
0.25
5.3
5.5
2.1
1.9
2
4.0
4.0
4.8
4.8
2.0
0.25
5.3
5.5
2.1
1.9
2
Aperture Uncertainty (Jitter)
Output Valid Time (tV)2
V
VI
VI
V
V
V
3.0
3.0
2
Output Propagation Delay (tPD
Output Rise Time (tR)2
Output Fall Time (tF)2
Out-of-Range Recovery Time
Transient Response Time
Latency
)
8.0
8.0
25°C
25°C
Full
ns
ns
Cycles
V
IV
2
10
2
10
DIGITAL INPUTS
Encode Input Common Mode
Differential Input
Full
Full
V
V
1.6
750
1.6
750
V
mV
(ENCODE, ENCODE)
Single-Ended Input
Logic 1 Voltage
Logic 0 Voltage
Full
Full
Full
25°C
IV
IV
VI
V
2.0
3
2.0
3
V
V
kΩ
pF
0.8
8
0.8
8
Input Resistance
5
4.5
5
4.5
Input Capacitance
DIGITAL OUTPUTS
Logic 1 Voltage (VDD = 3.3 V)
Logic 0 Voltage (VDD = 3.3 V)
Output Coding
Full
Full
VI
VI
VDD − 0.05
VDD − 0.05
V
V
0.05
0.05
Twos complement
Twos complement
Rev. F | Page 3 of 16
AD9432
Test
Level
80 MSPS
Typ
105 MSPS
Typ
Parameter
POWER SUPPLY
Power Dissipation3
IVCC
Temp
Min
Max
Min
Max
Unit
Full
Full
Full
25°C
VI
VI
VI
I
790
158
9.5
1000
200
12.2
+5
850
170
12.5
+0.5
1100
220
16
mW
mA
mA
IVDD
Power Supply Rejection Ratio
(PSRR)
−5
+0.5
−5
+5
mV/V
DYNAMIC PERFORMANCE4
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
fIN = 10 MHz
fIN = 40 MHz
fIN = 49 MHz
fIN = 70 MHz
25°C
25°C
25°C
25°C
I
I
I
V
65.5
65
67.5
67.2
67.0
66.1
65.5
64
67.5
67.2
67.0
66.1
dB
dB
dB
dB
Signal-to-Noise and Distortion
(SINAD) Ratio (with Harmonics)
fIN = 10 MHz
fIN = 40 MHz
fIN = 49 MHz
25°C
25°C
25°C
25°C
I
I
I
V
65
64.5
67.2
66.9
66.7
65.8
65
63
67.2
66.9
66.7
65.8
dB
dB
dB
dB
fIN = 70 MHz
Effective Number of Bits (ENOB)
fIN = 10 MHz
fIN = 40 MHz
fIN = 49 MHz
fIN = 70 MHz
25°C
25°C
25°C
25°C
V
V
V
V
11.0
10.9
10.9
10.7
11.0
10.9
10.9
10.7
Bits
Bits
Bits
Bits
Second-Order and Third-Order
Harmonic Distortion
fIN = 10 MHz
fIN = 40 MHz
fIN = 49 MHz
fIN = 70 MHz
25°C
25°C
25°C
25°C
I
I
I
V
−75
−73
−85
−85
−83
−80
−75
−72
−85
−83
−80
−78
dBc
dBc
dBc
dBc
Worst Other Harmonic or Spur
(Excluding Second-Order and
Third-Order Harmonics)
fIN = 10 MHz
fIN = 40 MHz
fIN = 49 MHz
fIN = 70 MHz
25°C
25°C
25°C
25°C
I
I
I
V
−80
−80
−90
−90
−90
−90
−80
−80
−90
−90
−90
−90
dBc
dBc
dBc
dBc
Two-Tone Intermodulation
Distortion (IMD)
fIN1 = 29.3 MHz; fIN2 = 30.3 MHz 25°C
fIN1 = 70.3 MHz; fIN2 = 71.3 MHz 25°C
V
V
−75
−66
−75
−66
dBc
dBc
1 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input).
2 tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital output swing. The digital output load during testing is not
to exceed an ac load of 10 pF or a dc current of 40 μA. Rise and fall times are measured from 10% to 90%.
3 Power dissipation measured with encode at rated speed and a dc analog input (outputs static, IVDD = 0).
4 SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 2 V full-scale input range.
Rev. F | Page 4 of 16
AD9432
TIMING DIAGRAM
SAMPLE N
SAMPLE N + 11
SAMPLE N – 1
SAMPLE N + 10
AIN
tA
SAMPLE N + 1
SAMPLE N + 9
tEH
tEL
1/fS
ENCODE
ENCODE
tPD
tV
DATA N + 1
DATA
N – 9
DATA
N – 2
D11 TO D0
DATA N – 11
DATA N – 10
DATA N – 1
DATA N
Figure 2. Timing Diagram
Rev. F | Page 5 of 16
AD9432
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 2.
Table 3 lists AD9432 thermal characteristics for simulated typical
performance in a 4-layer JEDEC board, horizontal orientation.
Parameter
Rating
VDD
6 V
VCC
6 V
Table 3. Thermal Resistance
Package Type
Analog Inputs
Digital Inputs
VREFIN
Digital Output Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Maximum Case Temperature
−0.5 V to VCC + 0.5 V
−0.5 V to VDD + 0.5 V
−0.5 V to VCC + 0.5 V
20 mA
−55°C to +125°C
−65°C to +150°C
150°C
θJA
50
θJMA
θJC
Unit
52-Lead LQFP (ST-52)
No Airflow
52-Lead TQFP_EP (SV-52-2)1
No Airflow
1.0 m/s Airflow
°C/W
°C/W
°C/W
°C/W
2
19.3
16
150°C
1 Bottom of package (soldered exposed pad).
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
EXPLANATION OF TEST LEVELS
I
100% production tested.
II 100% production tested at 25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V
Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
Rev. F | Page 6 of 16
AD9432
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
52 51 50 49 48 47 46 45 44 43 42 41 40
52 51 50 49 48
46 45 44 43 42 41 40
47
1
2
39
38
37
36
35
34
33
32
31
30
29
28
27
GND
GND
GND
PIN 1
V
1
2
CC
39
38
37
36
35
34
33
32
31
30
29
28
27
GND
GND
GND
PIN 1
3
GND
GND
V
V
CC
CC
V
CC
4
3
GND
GND
V
V
CC
CC
5
V
GND
GND
GND
4
CC
AD9432
TOP VIEW
(Not to Scale)
6
V
CC
5
V
V
GND
GND
GND
CC
AD9432
TOP VIEW
7
ENCODE
ENCODE
GND
6
CC
8
V
(Not to Scale)
DD
7
ENCODE
ENCODE
GND
9
DGND
D0 (LSB)
D1
8
V
DD
10
11
12
13
V
CC
9
DGND
D0 (LSB)
D1
GND
10
11
12
13
V
CC
DGND
D2
GND
V
D3
DD
DGND
D2
V
D3
DD
14 15 16 17 18 19 20 21 22 23 24 25 26
14 15 16 17 18 19 20 21 22 23 24 25 26
NOTES
1. ALTHOUGH NOT REQUIRED IN ALL APPLICATIONS, THE EXPOSED PADDLE
ON THE UNDERSIDE OF THE PACKAGE SHOULD BE SOLDERED TO THE
GROUND PLANE. SOLDERING THE EXPOSED PADDLE TO THE PCB
INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING
THE THERMAL CAPABILITY OF THE PACKAGE.
NOTES
1. DNC = DO NOT CONNECT.
Figure 3. Pin Configuration, LQFP
Figure 4. Pin Configuration, TQFP_EP
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 3, 4, 9, 11, 33,
34, 35, 38, 39, 40,
43, 48, 51
GND
Analog Ground.
2, 5, 6, 10, 36, 37,
42, 44, 47, 52
VCC
Analog Supply (5 V).
7
ENCODE
ENCODE
DGND
VDD
Encode Clock for ADC, Complementary.
Encode Clock for ADC, True. ADC samples on rising edge of ENCODE.
Digital Output Ground.
Digital Output Power Supply (2.7 V to 3.6 V).
Out-of-Range Output.
8
12, 21, 24, 31
13, 22, 23, 32
14
OR
15 to 20, 25 to 30
D11 to D6, D5 to D0 Digital Output.
41
45
46
49
50
DNC
Do Not Connect.
VREFIN
VREFOUT
AIN
Reference Input for ADC (2.5 V Typical). Bypass with 0.1 μF capacitor to ground.
Internal Reference Output (2.5 V Typical).
Analog Input, True.
AIN
Analog Input, Complementary.
Exposed Pad
(TQFP_EP)
Although not required in all applications, the exposed paddle on the underside of the TQFP_EP
package should be soldered to the ground plane. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints, maximizing the thermal capability of the package.
Rev. F | Page 7 of 16
AD9432
TYPICAL PERFORMANCE CHARACTERISTICS
90
70
65
60
AIN = –0.5dBFS
AIN = 10.3MHz
85
SFDR
80
75
70
SNR
55
50
65
SINAD
60
0
20
40
60
80
100
120
140
160
0
50
100
150
200
250
ENCODE (MSPS)
ANALOG INPUT FREQUENCY (MHz)
Figure 5. SNR/SINAD/SFDR vs. fS, fIN = 10.3 MHz
Figure 8. SNR vs. fIN, Encode = 105 MSPS
100
90
80
70
60
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
AIN = 10.3MHz
ENCODE = 105MSPS
2ND or 3RD (–6.0dBFS)
3RD
2ND
2ND or 3RD (–0.5dBFS)
50
40
2ND or 3RD (–3.0dBFS)
0
20
40
60
80
100 120 140 160 180 200
0
20
40
60
80
100
120
140
160
ANALOG INPUT FREQUENCY (MHz)
ENCODE (MSPS)
Figure 6. Second-Order and Third-Order Harmonics vs. fS, fIN = 10.3 MHz
Figure 9. Second-Order and Third-Order Harmonics vs. fIN, fS = 105 MSPS
70
100
ENCODE = 105MSPS
ENCODE = 105MSPS
WORST OTHER (–0.5dBFS)
65
90
60
80
SINAD (–3.0dBFS)
WORST OTHER (–6.0dBFS)
55
70
SINAD (–6.0dBFS)
WORST OTHER (–3.0dBFS)
50
60
SINAD (–0.5dBFS)
45
40
50
40
0
20
40
60
80
100 120 140 160 180 200
0
20
40
60
80
100 120 140 160 180 200
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 7. SINAD vs. fIN, fS = 105 MSPS
Figure 10. Worst Other (Excluding Second-Order and Third-Order
Harmonics) vs. fIN, fS = 105 MSPS
Rev. F | Page 8 of 16
AD9432
0
–10
–20
–30
–40
–50
0
–10
–20
–30
–40
–50
ENCODE = 105MSPS
AIN = 50.3MHz (–0.46dBFS)
SNR = 67.0dB
SINAD = 66.7dB
SFDR = –80dBc
ENCODE = 105MSPS
AIN = 10.3MHz (–0.53dBFS)
SNR = 67.32dB
SINAD = 67.07dB
SFDR = –85dBc
–60
–70
–60
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
FREQUENCY
FREQUENCY
Figure 11. FFT: fS = 105 MSPS, fIN = 10.3 MHz
Figure 14. FFT: fS = 105 MSPS, fIN = 50.3 MHz
0
–10
–20
–30
–40
–50
0
–10
–20
–30
–40
–50
AIN1 = 29.3MHz (–7dBFS)
AIN2 = 30.3MHz (–7dBFS)
ENCODE = 105MSPS
ENCODE = 105MSPS
AIN = 27.0MHz (–0.52dBFS)
SNR = 67.3dB
SINAD = 67.0dB
SFDR = –83.1dBc
–60
–70
–60
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
FREQUENCY
FREQUENCY
Figure 12. FFT: fS = 105 MSPS, fIN = 27 MHz
Figure 15. Two-Tone FFT, Wideband: fS = 105 MSPS, AIN1 = 29.3 MHz,
AIN2 = 30.3 MHz
0
–10
–20
–30
–40
–50
0
ENCODE = 105MSPS
AIN = 40.9MHz (–0.56dBFS)
SNR = 67.2dB
SINAD = 66.9dB
SFDR = –80dBc
AIN1 = 70.3MHz (–7dBFS)
AIN2 = 71.3MHz (–7dBFS)
ENCODE = 105MSPS
–10
–20
–30
–40
–50
–60
–70
–60
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
FREQUENCY
FREQUENCY
Figure 13. FFT: fS = 105 MSPS, fIN = 40.9 MHz
Figure 16. Two-Tone FFT, Wideband: fS = 105 MSPS, AIN1 = 70.3 MHz,
AIN2 = 71.3 MHz
Rev. F | Page 9 of 16
AD9432
1.00
0.75
0.50
0.25
0
110
100
90
dBFS
80
ENCODE = 105MSPS
AIN = 50.3MHz
70
60
50
40
30
20
10
dBc
–0.25
–0.50
–0.75
–1.00
0
–80
–70
–60
–50
–40
–30
–20
–10
0
ANALOG INPUT POWER LEVEL (dBFS)
Figure 17. Single-Tone SFDR, fS = 105 MSPS, fIN = 50.3 MHz
Figure 19. Integral Nonlinearity, fS = 105 MSPS
1.00
3.0
0.75
0.50
0.25
0
2.5
2.0
1.5
–0.25
–0.50
–0.75
–1.00
0
2
4
6
8
10
CURRENT (mA)
Figure 20. Voltage Reference Output vs. Current Load
Figure 18. Differential Nonlinearity, fS = 105 MSPS
Rev. F | Page 10 of 16
AD9432
TERMINOLOGY
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio (PSRR)
The ratio of a change in input offset voltage to a change in
power supply voltage.
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE
and the instant at which the analog input is sampled.
Signal-to-Noise and Distortion (SINAD) Ratio
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Differential Nonlinearity (DNL)
The deviation of any code from an ideal 1 LSB step.
Signal-to-Noise Ratio (SNR)
Effective Number of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
measured SNR based on the following equation:
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral com-
ponents, excluding the first five harmonics and dc.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
Full −Scale Amplitude
Spurious-Free Dynamic Range (SFDR)
SNRMEASURED −1.76 dB + 20 log
Input Amplitude
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(degrades as signal level is lowered) or in dBFS (always related
back to converter full scale).
ENOB =
6.02
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the encode
pulse should be left in the Logic 1 state to achieve the rated per-
formance. Pulse width low is the minimum amount of time that
the encode pulse should be left in the Logic 0 state. At a given clock
rate, these specifications define an acceptable encode duty cycle.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone (f1, f2) to the rms
value of the worst third-order intermodulation product;
reported in dBc. Products are located at 2f1 − f2 and 2f2 − f1.
Two-Tone SFDR
Harmonic Distortion
The ratio of the rms value of either input tone (f1, f2) to the rms
value of the peak spurious component. The peak spurious com-
ponent may or may not be an IMD product. May be reported in
dBc (degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
The ratio of the rms signal amplitude fundamental frequency
to the rms signal amplitude of a single harmonic component
(second, third, and so on); reported in dBc.
Integral Nonlinearity (INL)
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second-order and
third-order harmonic); reported in dBc.
Maximum Conversion Rate
The maximum encode rate at which parametric testing is
performed.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Rev. F | Page 11 of 16
AD9432
EQUIVALENT CIRCUITS
V
DD
V
CC
VREFIN
Dx
Figure 21. Voltage Reference Input Circuit
Figure 24. Digital Output Circuit
V
CC
V
CC
5kΩ
5kΩ
7kΩ
AIN
AIN
VREFOUT
7kΩ
Figure 22. Voltage Reference Output Circuit
Figure 25. Analog Input Circuit
V
CC
17kΩ
100Ω
17kΩ
100Ω
ENCODE
ENCODE
8kΩ
8kΩ
Figure 23. Encode Input Circuit
Rev. F | Page 12 of 16
AD9432
THEORY OF OPERATION
The AD9432 is a 12-bit pipeline converter that uses a switched-
capacitor architecture. Optimized for high speed, this converter
provides flat dynamic performance up to frequencies near
Nyquist. DNL transitional errors are calibrated at final test to
a typical accuracy of 0.25 LSB or less.
Note that the encode inputs cannot be driven directly from PECL
level signals (VIHD is 3.5 V maximum). PECL level signals can
easily be accommodated by ac coupling, as shown in Figure 27.
Good performance is obtained using an MC10EL16 translator
in the circuit to drive the encode inputs.
ANALOG INPUT
AD9432
0.1µF
ENCODE
The analog input to the AD9432 is a differential buffer. The
input buffer is self-biased by an on-chip resistor divider that
sets the dc common-mode voltage to a nominal 3 V (see the
Equivalent Circuits section). Rated performance is achieved
by driving the input differentially. The minimum input offset
voltage is obtained when driving from a source with a low
differential source impedance, such as a transformer in ac
applications. Capacitive coupling at the inputs increases the
input offset voltage by as much as 25 mV. Driving the ADC
single-ended degrades performance. For best dynamic perfor-
PECL
GATE
ENCODE
0.1µF
510Ω
510Ω
Figure 27. AC Coupling to Encode Inputs
ENCODE VOLTAGE LEVEL DEFINITION
ENCODE
The voltage level definitions for driving ENCODE and
in single-ended and differential mode are shown in Figure 28.
V
IHD
AIN
mance, impedances at AIN and
should match.
ENCODE
ENCODE
V
V
ID
ICM
Special care was taken in the design of the analog input section
of the AD9432 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is 2 V p-p.
Each analog input is 1 V p-p when driven differentially.
4.0
V
ILD
V
IHS
ENCODE
0.1µF
V
ILS
AIN
3.5
Figure 28. Differential and Single-Ended Input Levels
Table 5. Encode Inputs
3.0
Input
Min
Nominal Max
Differential Signal Amplitude (VID)
500 mV 750 mV
High Differential Input Voltage (VIHD
Low Differential Input Voltage (VILD
Common-Mode Input (VICM
High Single-Ended Voltage (VIHS
Low Single-Ended Voltage (VILS
)
)
3.5 V
2.5
0 V
1.25 V
2 V
AIN
)
1.6 V
)
3.5 V
0.8 V
2.0
)
0 V
Figure 26. Full-Scale Analog Input Range
Often, the cleanest clock source is a crystal oscillator producing a
pure sine wave. In this configuration, or with any roughly symmet-
rical clock input, the input can be ac-coupled and biased to a
reference voltage that also provides the encode. This ensures
that the reference voltage is centered on the encode signal.
ENCODE INPUT
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the ADC output.
For this reason, considerable care has been taken in the design
of the encode input of the AD9432, and the user is advised to
give commensurate thought to the clock source. The encode
input supports differential or single-ended mode and is fully
TTL-/CMOS-compatible.
Rev. F | Page 13 of 16
AD9432
DIGITAL OUTPUTS
VOLTAGE REFERENCE
The digital outputs are 3.3 V (2.7 V to 3.6 V) TTL-/CMOS-
compatible for lower power consumption. The output data
format is twos complement (see Table 6).
A stable and accurate 2.5 V voltage reference is built into the
AD9432 (VREFOUT). In normal operation, the internal refer-
ence is used by strapping Pin 45 to Pin 46 and placing a 0.1 μF
decoupling capacitor at VREFIN.
Table 6. Twos Complement Output Coding (VREF = 2.5 V)
The input range can be adjusted by varying the reference voltage
applied to the AD9432. No appreciable degradation in performance
occurs when the reference is adjusted 5%. The full-scale range
of the ADC tracks reference voltage changes linearly.
AIN − AIN (V)
Code
+2047
…
Digital Output
0111 1111 1111
…
1.000
…
0
−1
…
0
0000 0000 0000
1111 1111 1111
…
TIMING
−0.00049
…
The AD9432 provides latched data outputs, with 10 pipeline
delays. Data outputs are included or available one propagation
delay (tPD) after the rising edge of the encode command (see
Figure 2). The length of the output data lines and the loads
placed on them should be minimized to reduce transients
within the AD9432; these transients can detract from the
dynamic performance of the converter.
−2048
−1.000
1000 0000 0000
The out-of-range (OR) output is logic low for normal operation.
During any clock cycle when the ADC output data (Dx) reaches
positive or negative full scale (+2047 or −2048), the OR output
goes high. The OR output is internally generated each clock cycle.
It has the same pipeline latency and propagation delay as the ADC
output data and remains high until the output data reflects an
in-range condition. The ADC output bits (Dx) do not roll over
and, therefore, remain at positive or negative full scale (+2047
or −2048) while the OR output is high.
The minimum guaranteed conversion rate of the AD9432 is
1 MSPS. At internal clock rates below 1 MSPS, dynamic perfor-
mance may degrade. Therefore, input clock rates below 1 MHz
should be avoided.
During initial power-up, or whenever the clock to the AD9432
is interrupted, the output data will not be accurate for 200 ns or
10 clock cycles, whichever is longer.
Rev. F | Page 14 of 16
AD9432
APPLICATIONS INFORMATION
66
65
64
63
62
61
60
USING THE AD8138 TO DRIVE THE AD9432
The AD8138 differential output op amp can be used to drive the
AD9432 in dc-coupled applications. The AD8138 was specifically
designed for ADC driver applications. Superior SNR performance
is maintained up to analog frequencies of 30 MHz. The AD8138
op amp provides single-ended-to-differential conversion, which
allows for a low cost alternative to transformer coupling for ac
applications, as well.
SNR
SINAD
The circuit in Figure 29 was breadboarded, and the measured
performance is shown in Figure 30 and Figure 31. These figures
are for 5 V supplies at the AD8138; with a single 5 V supply at
the AD8138, performance dropped by about 1 dB to 2 dB.
0
20
40
60
AIN (MHz)
Figure 30 shows SNR and SINAD for a −1 dBFS analog input
frequency varied from 2 MHz to 40 MHz with an encode rate
of 105 MSPS. The measurements are for nominal conditions
at room temperature. Figure 31 shows the second-order and
third-order harmonic distortion performance under the same
conditions.
Figure 30. Measured SNR and SINAD (Encode = 105 MSPS)
–70
H2
The dc common-mode voltage for the AD8138 outputs can be
adjusted via the VOCM input to provide the 3 V common-mode
voltage that the AD9432 inputs require.
–80
–90
H3
500Ω
AD9432
10pF
50Ω
AIN
AIN
VIN
500Ω
–100
0
20
40
60
22pF
50Ω
AD8138
OCM
50Ω
AIN (MHz)
Figure 31. Measured Second-Order and Third-Order Harmonic Distortion
(Encode = 105 MSPS)
V
5V
2kΩ
500Ω
3kΩ
0.1µF
10pF
25Ω
500Ω
Figure 29. AD8138/AD9432 Schematic
Rev. F | Page 15 of 16
AD9432
OUTLINE DIMENSIONS
12.20
12.00 SQ
11.80
0.75
0.60
0.45
1.60
MAX
52
40
39
1
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
13
27
3.5°
0.15
0.05
0°
14
26
SEATING
PLANE
0.10
COPLANARITY
0.38
0.32
0.22
VIEW A
0.65
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCC
Figure 32. 52-Lead Low Profile Quad Flat Package [LQFP]
(ST-52)
Dimensions shown in millimeters
1.20
MAX
0.75
0.60
0.45
12.00 BSC
SQ
52
1
40
52
40
39
39
1
SEATING
PLANE
PIN 1
10.00
BSC SQ
TOP VIEW
(PINS DOWN)
7.30 BSC
SQ
EXPOSED
PAD
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
BOTTOM VIEW
(PINS UP)
13
13
14
27
27
14
VIEW A
26
26
3.5°
0°
0.15
0.05
0.65
BSC
LEAD PITCH
0.38
0.32
0.22
0.08 MAX
COPLANARITY
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
VIEW A
ROTATED 90
°
CCW
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MS-026-ACC
Figure 33. 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-52-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9432BSTZ-801
AD9432BSTZ-1051
AD9432BSVZ-801
AD9432BSVZ-1051
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
ST-52
ST-52
SV-52-2
SV-52-2
52-Lead Low Profile Quad Flat Package [LQFP]
52-Lead Low Profile Quad Flat Package [LQFP]
52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
1 Z = RoHS Compliant Part.
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00587-0-6/09(F)
Rev. F | Page 16 of 16
相关型号：
AD9432BSTZ-105
1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, ROHS COMPLIANT, MS-026BCC, LQFP-52
ROCHESTER
AD9432BSTZ-80
1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP52, ROHS COMPLIANT, MS-026BCC, LQFP-52
ROCHESTER
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