AD9444-CMOS/PCB [ADI]
14-Bit, 80 MSPS, A/D Converter; 14位， 80 MSPS ，A / D转换器
| 型号： | AD9444-CMOS/PCB |
| 厂家： | 
ADI |
| 描述： | 14-Bit, 80 MSPS, A/D Converter |
| 文件： | 总40页 (文件大小：1622K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Bit, 80 MSPS, A/D Converter
AD9444
FEATURES
FUNCTIONAL BLOCK DIAGRAM
80 MSPS guaranteed sampling rate
100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz
73.1 dB SNR with 70 MHz input
97 dBc SFDR with 70 MHz input
Excellent linearity
DNL = 0.4 LSB typical
INL = 0.6 LSB typical
1.2 W power dissipation
AGND AVDD1 AVDD2 DRGND DRVDD
DFS
AD9444
DCS MODE
BUFFER
OUTPUT MODE
14
VIN+
VIN–
2
PIPELINE
ADC
CMOS
OR
LVDS
OUTPUT
STAGING
T/H
OR
28
D13–D0
2
CLOCK
CLK+
CLK–
DCO
AND TIMING
MANAGEMENT
REF
3.3 V and 5 V supply operation
2.0 V p-p differential full-scale input
LVDS outputs (ANSI-644 compatible)
Data format select
VREF SENSE REFT REFB
Figure 1.
Output clock available
Optional features allow users to implement various selectable
operating conditions, including data format select and output
data mode.
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
The AD9444 is available in a 100-lead surface-mount plastic
package (100-lead TQFP/EP) specified over the industrial
temperature range (−40°C to +85°C).
Radar, infared imaging
Communications instrumentation
PRODUCT HIGHLIGHTS
1. High performance: Outstanding SFDR performance for mul-
ticarrier, multimode 3G and 4G cellular base station
receivers.
GENERAL DESCRIPTION
The AD9444 is a 14-bit monolithic, sampling analog-to-digital
converter (ADC) with an on-chip, track-and-hold circuit and is
optimized for power, small size, and ease of use. The product
operates at up to an 80 MSPS conversion rate and is optimized
for multicarrier, multimode receivers, such as those found in
cellular infrastructure equipment.
2. Ease of use: On-chip reference and track-and-hold. An
output clock simplifies data capture.
3. Packaged in a Pb-free, 100-lead TQFP/EP.
4. Clock DCS maintains overall ADC performance over a wide
range of clock pulse widths.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are LVDS-compatible (ANSI-
644) or CMOS-compatible and include the means to reduce
the overall current needed for short trace distances.
5. OR (out-of-range) outputs indicate when the signal is beyond
the selected input range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD9444
TABLE OF CONTENTS
DC Specifications ............................................................................. 3
Clock Input Considerations...................................................... 22
Power Considerations................................................................ 23
Digital Outputs ........................................................................... 23
Timing ......................................................................................... 23
Operational Mode Selection..................................................... 23
Evaluation Board........................................................................ 24
LVDS Evaluation Board Schematics........................................ 25
LVDS Mode Evaluation Board Bill of Materials (BOM) ...... 30
CMOS Evaluation Board Schematics ...................................... 32
CMOS Mode Evaluation Board Bill of Materials (BOM)..... 37
Outline Dimensions....................................................................... 39
Ordering Guide .......................................................................... 39
AC Specifications.............................................................................. 4
Digital Specifications........................................................................ 5
Switching Specifications .................................................................. 6
Explanation of Test Levels........................................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Definitions of Specifications ........................................................... 9
Pin Configurations and Function Descriptions ......................... 10
Equivalent Circuits......................................................................... 14
Typical Performance Characteristics ........................................... 15
Theory of Operation ...................................................................... 20
Analog Input and Reference Overview ................................... 20
REVISION HISTORY
10/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
AD9444
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed
reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted.
Table 1.
AD9444BSVZ-80
Parameter
Temp
Test Level
Unit
Min
Typ
Max
RESOLUTION
Full
VI
14
Bits
ACCURACY
No Missing Codes
Offset Error
Full
Full
Full
Full
25°C
Full
VI
VI
VI
VI
I
Guaranteed
6
0.3
0.4
0.4
0.6
6
mV
% FSR
LSB
LSB
LSB
Gain Error1
−3.0
−0.8
−1.3
−1.7
+3.0
+0.8
+1.3
+1.7
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
VI
TEMPERATURE DRIFT
Offset Error
Gain Error
Full
Full
V
V
12
0.002
µV/°C
%FS/°C
VOLTAGE REFERENCE
Output Voltage1
Load Regulation @ 1.0 mA
Reference Input Current (External 1.0 V Reference)
INPUT REFERRED NOISE
ANALOG INPUT
Full
Full
Full
25°C
VI
V
VI
V
0.87
1.0
2
80
1.0
1.13
125
V
mV
µA
LSB rms
Input Span
Input Common-Mode Voltage
Input Resistance3
Input Capacitance3
POWER SUPPLIES
Supply Voltage
Full
Full
Full
Full
V
V
V
V
2
3.5
1
V p-p
V
kΩ
pF
2.5
AVDD1
AVDD2
DRVDD—LVDS Outputs
DRVDD—CMOS Outputs
Supply Current
Full
Full
Full
Full
IV
IV
IV
IV
3.14
4.75
3.0
3.3
5.0
3.46
5.25
3.6
V
V
V
V
3.0
3.3
3.6
AVDD1
Full
Full
Full
Full
VI
VI
VI
V
217
71
55
240
80
62
mA
mA
mA
mA
AVDD22
IDRVDD2—LVDS Outputs
IDRVDD2—CMOS Outputs
PSRR
12
Offset
Gain
Full
Full
V
V
1
0.2
mV/V
%/V
POWER CONSUMPTION
DC Input—LVDS Outputs
DC Input—CMOS Outputs
Sine Wave Input2—LVDS Outputs
Sine Wave Input2—CMOS Outputs
Full
Full
Full
Full
VI
V
VI
V
1.21
1.07
1.25
1.11
1.4
W
W
W
W
1 The internal voltage reference is trimmed at final test to minimize the gain error of the AD9444.
2 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
3 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input
structure.
Rev. 0 | Page 3 of 40
AD9444
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, sample rate = 80 MSPS, 2 V p-p differential input, internal trimmed
reference (1.0 V mode), AIN = −0.5 dBFS, DCS on, unless otherwise noted.
Table 2.
AD9444BSVZ-80
Parameter
Temp
Test Level
Unit
Min
Typ
74.0
73.7
73.1
72.3
74.0
73.7
73.1
72.3
Max
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 10 MHz
25°C
Full
IV
IV
I
73.0
72.7
72.4
72.3
72.3
72.0
dB
dB
dB
dB
dB
dB
dB
fIN = 35 MHz
fIN = 70 MHz
25°C
Full
IV
IV
IV
V
25°C
Full
fIN = 100 MHz
25°C
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
fIN = 10 MHz
25°C
Full
IV
IV
I
73.0
72.7
72.4
72.2
72.2
72.0
dB
dB
dB
dB
dB
dB
dB
fIN = 35 MHz
fIN = 70 MHz
25°C
Full
IV
IV
IV
V
25°C
Full
fIN = 100 MHz
25°C
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
25°C
25°C
25°C
25°C
V
V
V
V
12.1
12.0
11.9
11.8
Bits
Bits
Bits
Bits
fIN = 35 MHz
fIN = 70 MHz
fIN = 100 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 10 MHz
25°C
Full
IV
IV
I
91
87
91
87
90
87
97
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fIN = 35 MHz
fIN = 70 MHz
25°C
Full
97
IV
IV
IV
V
25°C
Full
97
fIN = 100 MHz
25°C
96
WORST HARMONIC, SECOND OR THIRD
fIN = 10 MHz
25°C
Full
IV
IV
I
−97
−97
−97
−96
−102
−103
−102
−99
−91
−87
−91
−87
−90
−87
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fIN = 35 MHz
fIN = 70 MHz
25°C
Full
IV
IV
IV
V
25°C
Full
fIN = 100 MHz
25°C
WORST SPUR EXCLUDING SECOND OR HARMONICS
fIN = 10 MHz
25°C
Full
IV
IV
I
−93
−93
−93
−93
−93
−93
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fIN = 35 MHz
fIN = 70 MHz
25°C
Full
IV
IV
IV
V
25°C
Full
fIN = 100 MHz
25°C
TWO-TONE SFDR
fIN = 10.8 MHz @ −7 dBFS, 9.8 MHz @ −7 dBFS
fIN = 70.3 MHz @ −7 dBFS, 69.3 MHz @ −7 dBFS
ANALOG BANDWIDTH
25°C
25°C
Full
V
V
V
−102
dBFS
dBFS
MHz
−100
650
Rev. 0 | Page 4 of 40
AD9444
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDSBIAS = 3.74 kΩ, unless otherwise noted.
Table 3.
AD9444BSVZ-80
Parameter
Temp
Test Level
Unit
Min
Typ
Max
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS Mode (D0 to D13, OTR)1
DRVDD = 3.3 V
High Level Output Voltage
Low Level Output Voltage
Full
Full
Full
Full
Full
IV
IV
VI
VI
V
2.0
V
V
µA
µA
pF
0.8
+200
+10
−10
3.25
2
Full
Full
IV
IV
V
V
0.2
DIGITAL OUTPUT BITS LVDS Mode (D0 to D13, OTR)
VOD Differential Output Voltage2
VOS Output Offset Voltage
Full
Full
VI
VI
247
1.125
545
1.375
mV
V
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
Full
Full
Full
Full
IV
VI
V
0.2
1.3
8
V
V
kΩ
pF
1.5
10
4
1.6
12
V
1 Output voltage levels measured with 5 pF load on each output.
2 LVDS RTERM = 100 Ω.
Rev. 0 | Page 5 of 40
AD9444
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
AD9444BSVZ-80
Parameter
Temp
Test Level
Unit
Min
Typ
Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
Full
Full
Full
Full
Full
VI
V
V
V
V
80
MSPS
MSPS
ns
ns
ns
10
12.5
4
4
CLK Pulse Width High1 (tCLKH
)
CLK Pulse Width Low1 (tCLKL
)
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD)2 (DX, DCO+)
Output Propagation Delay—LVDS (tPD)3 (DX+, DCO+)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Full
Full
Full
Full
Full
IV
VI
V
V
V
3
3
5.25
5
12
8
7.5
ns
ns
Cycles
ns
ps rms
0.2
1 With duty cycle stabilizer (DCS) enabled.
2 Output propagation delay is measured from clock 50% transition to data 50% transition, with 5 pF load.
3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
N–1
N
N+1
A
IN
tCLKL
tCLKH
1/fS
CLK+
CLK–
tPD
N–12
N
N+1
N–11
12 CLOCK CYCLES
DATA OUT
DCO+
DCO–
tCPD
Figure 2. LVDS Mode Timing Diagram
Rev. 0 | Page 6 of 40
AD9444
N
N–1
N+1
VIN
N+2
tCLKL
tCLKH
CLK–
CLK+
tPD
12 CYCLES
N-11
N-12
N-1
N
DX
tDCOPD
DCO+
DCO–
Figure 3. CMOS Timing Diagram
EXPLANATION OF TEST LEVELS
Test Level Definitions
I
100% production tested.
II
100% production tested at 25°C and sample tested at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
III
IV
V
VI
100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
Rev. 0 | Page 7 of 40
AD9444
ABSOLUTE MAXIMUM RATINGS
Table 5.
Thermal Resistance
With
Respect to
The heat sink of the AD9444 package must be soldered to
ground.
Parameter
ELECTRICAL
AVDD1
AVDD2
DRVDD
AGND
AVDD1
AVDD2
AVDD2
D0 to D13
CLK, MODE
VIN+, VIN−
VREF
SENSE
REFT, REFB
ENVIRONMENTAL
Min Max
Unit
Table 6.
AGND
AGND
DGND
DGND
DRVDD
DRVDD
AVDD1
DGND
AGND
AGND
AGND
AGND
AGND
−0.3 +4
−0.3 +6
−0.3 +4
−0.3 +0.3
V
V
V
V
V
V
V
V
V
V
V
V
V
Package Type
θJA
θJB
θJC
Unit
100-Lead TQFP/EP
19.8
8.3
2
°C/W
−4
−4
−4
+4
+6
+6
Typical θJA = 19.8°C/W (heat-sink soldered) for multilayer
board in still air.
–0.3 DRVDD + 0.3
–0.3 AVDD1 + 0.3
–0.3 AVDD2 + 0.3
–0.3 AVDD1 + 0.3
–0.3 AVDD1 + 0.3
–0.3 AVDD1 + 0.3
Typical θJB = 8.3°C/W (heat-sink soldered) for multilayer board
in still air.
Typical θJC = 2°C/W (junction to exposed heat sink) represents
the thermal resistance through heat-sink path.
Airflow increases heat dissipation effectively reducing θJA. Also,
more metal directly in contact with the package leads, from
metal traces, through holes, ground, and power planes, reduces
the θJA. It is required that the exposed heat sink be soldered to
the ground plane.
Storage Temperature
Operating Temperature Range –40
Lead Temperature Range
(Soldering 10 sec)
–65
+125
+85
300
°C
°C
°C
Junction Temperature
150
°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Rev. 0 | Page 8 of 40
AD9444
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Aperture Delay (tA)
Offset Error
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
Aperture Uncertainty (Jitter, tJ)
The sample-to-sample variation in aperture delay.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Output Propagation Delay (tPD)
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed no
missing codes to 14-bit resolution indicates that all 16384 codes
must be present over all operating ranges.
Power-Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum limit.
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula
Signal-to-Noise Ratio (SNR)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
(
SINAD −1.76
)
ENOB =
Gain Error
6.02
Spurious-Free Dynamic Range (SFDR)
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1 ½ LSB below the positive full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered) or dBFS (always related
back to converter full scale).
Temperature Drift
Integral Nonlinearity (INL)
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1 ½ LSBs beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
at TMIN or TMAX
.
Total Harmonic Distortion (THD)
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Rev. 0 | Page 9 of 40
AD9444
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
75
74
73
72
71
DRVDD
DRGND
AVDD1
DNC
1
2
DNC
3
D10+
D10–
DNC
4
OUTPUT MODE
DFS
5
D9+
70 D9–
6
69
LVDSBIAS
AVDD1
7
D8+
68
8
D8–
67
66
65
64
63
AVDD1
SENSE
VREF
9
DRGND
10
11
12
13
14
15
16
17
18
19
20
21
D7+
D7–
AD9444
AGND
REFT
DCO+
DCO–
TOP VIEW
(Not to Scale)
REFB
AGND
62 DRVDD
61
DRGND
60 D6+
AVDD1
AVDD1
AVDD1
AVDD2
59
D6–
58
D5+
57
56
D5–
D4+
AGND
VIN+
55 D4–
54
53
52
51
VIN– 22
DRVDD
AGND
23
24
25
DRGND
D3+
AVDD1
AVDD1
D3–
DNC = DO NOT CONNECT
Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode
Rev. 0 | Page 10 of 40
AD9444
Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode
Pin No.
Mnemonic Description
Pin No.
Mnemonic Description
1, 8 to 9,
16 to 18,
24 to 27,
34 to 35, 38,
41 to 42, 87,
89 to 95, 98
AVDD1
3.3 V ( 5%) Analog Supply.
44
45
46
D0+
D1−
D1+
DRVDD
D0 True Output Bit.
D1 Complement Output Bit.
D1 True Output Bit.
3.3 V Digital Output Supply
(3.0 V to 3.6 V).
Digital Ground.
47, 54, 62,
75, 83
48, 53, 61,
67, 74, 82
DRGND
2 to 4
DNC
Do Not Connect. These pins
should float.
CMOS Compatible Output Logic
Mode Control Pin. OUTPUT MODE
= 0 for CMOS mode, and OUTPUT
MODE = 1 (AVDD1) for LVDS
outputs.
Data Format Select Pin. CMOS
control pin that determines the
format of the output data. DFS =
high (AVDD1) for twos comple-
ment, DFS = low (ground) for
offset binary format.
Set Pin for LVDS Output Current.
Place 3.7 kΩ resistor terminated to
DRGND.
Reference Mode Selection.
Connect to AGND for internal 1 V
reference, and connect to AVDD2
for external reference.
1.0 V Reference I/O—Function
Dependent on SENSE. Decouple
to ground with 0.1 µF and 10 µF
capacitors.
Analog Ground. The exposed
heat sink on the bottom of the
package must be connected to
AGND.
49
50
51
52
55
56
57
58
59
60
63
64
65
66
68
69
70
71
72
73
76
77
78
79
80
81
84
D2−
D2+
D3−
D3+
D4−
D4+
D5−
D5+
D6−
D6+
DCO−
DCO+
D7−
D7+
D8−
D8+
D9−
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
Data Clock Output—Complement.
Data Clock Output—True.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
5
OUTPUT
MODE
6
DFS
7
LVDSBIAS
SENSE
10
11
VREF
D9+
D10−
D10+
D11−
D11+
D12−
D12+
D13−
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
D12 Complement Output Bit.
D12 True Output Bit.
D13 Complement Output.
12, 15, 20,
23, 32, 86,
88, 96 to 97,
99, Exposed
Heat Sink
AGND
13
REFT
REFB
Differential Reference Output.
Decoupled to ground with 0.1 µF
capacitor and to REFB (Pin 14) with
0.1 µF and 10 µF capacitors.
Differential Reference Output.
Decoupled to ground with a 0.1 µF
capacitor and to REFT (Pin 13) with
0.1 µF and 10 µF capacitors.
D13+ (MSB) D13 True Output Bit.
OR−
Out-of-Range Complement
Output Bit.
Out-of-Range True Output Bit.
14
85
100
OR+
DCS MODE Clock Duty Cycle Stabilizer (DCS)
Control Pin, CMOS-Compatible.
DCS = low (AGND) to enable DCS
(recommended). DCS = high
19, 28 to 31, AVDD2
39 to 40
5.0 V Analog Supply ( 5%).
(AVDD1) to disable DCS.
21
22
33
VIN+
VIN−
C1
Analog Input—True.
Analog Input—Complement.
Internal Bypass Node. Connect a
0.1 µF capacitor from this pin
to AGND.
36
37
43
CLK+
CLK−
D0− (LSB)
Clock Input—True.
Clock Input—Complement.
D0 Complement Output Bit
(LVDS Levels).
Rev. 0 | Page 11 of 40
AD9444
75
74
73
72
71
70
69
68
67
66
DRVDD
DRGND
AVDD1
DNC
1
2
DNC
3
D6
D5
DNC
4
OUTPUT MODE
DFS
5
D4
D3
6
DNC
7
D2
AVDD1
8
D1
AVDD1
SENSE
VREF
9
DRGND
10
11
12
13
14
15
16
17
18
19
20
21
D0 (LSB)
65 DNC
AD9444
64
AGND
REFT
DCO+
TOP VIEW
(Not to Scale)
63
DCO–
REFB
AGND
62 DRVDD
61
DRGND
60 DNC
AVDD1
AVDD1
AVDD1
AVDD2
59
DNC
58
DNC
57
56
DNC
DNC
AGND
VIN+
55 DNC
54
53
52
51
VIN– 22
DRVDD
AGND
23
24
25
DRGND
DNC
AVDD1
AVDD1
DNC
DNC = DO NOT CONNECT
Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode
Rev. 0 | Page 12 of 40
AD9444
Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode
Pin No.
Mnemonic Description
Pin No.
Mnemonic Description
1, 8 to 9, 16 to 18, AVDD1
24 to 27, 34 to 35,
38, 41 to 42, 87,
3.3 V ( 5%) Analog Supply.
33
C1
Internal Bypass Node.
Connect a 0.1 µF capacitor
from this pin to AGND.
89 to 95, 98
2 to 4, 7,
43 to 46, 49 to 52,
55 to 60, 65
5
36
37
CLK+
CLK−
DRVDD
Clock Input—True.
Clock Input—Complement.
3.3 V Digital Output
Supply (2.5V to 3.6 V).
Digital Ground.
DNC
Do Not Connect. These
pins should float.
47, 54, 62,
75, 83
48, 53, 61,
67, 74, 82
63
64
66
OUTPUT
MODE
CMOS Compatible Output
Logic Mode Control Pin.
OUTPUT MODE = 0 for CMOS
mode, and OUTPUT MODE =
1 (AVDD1) for LVDS outputs.
Data Format Select Pin.
CMOS control pin that de-
termines the format of the
output data. DFS = high
(AVDD1) for twos comple-
ment, DFS = low (ground) for
offset binary format.
Reference Mode Selection.
Connect to AGND for internal
1 V reference, and connect to
AVDD2 for external reference.
1.0 V Reference I/O—
Function Dependent on
SENSE. Decouple to ground
with 0.1 µF and 10 µF
capacitors.
Analog Ground. The exposed
heat sink on the bottom of
the package must be
DRGND
DCO−
Data Clock Output—
Complement (CMOS Levels).
Data Clock Output—
True.
D0 Output Bit (LSB)
(CMOS Levels).
DCO+
6
DFS
D0 (LSB)
68
69
70
71
72
73
76
77
78
79
80
81
84
85
100
D1
D2
D3
D4
D5
D6
D7
D8
D1 Output Bit.
D2 Output Bit.
D3 Output Bit.
D4 Output Bit.
D5 Output Bit.
D6 Output Bit.
D7 Output Bit.
D8 Output Bit.
D9 Output Bit.
D10 Output Bit.
D11 Output Bit.
D12 Output Bit.
D13 Output Bit.
Out-of-Range Output.
10
11
SENSE
VREF
D9
D10
D11
D12
D13 (MSB)
OR
DCS MODE Clock Duty Cycle Stabilizer
(DCS) Control Pin, CMOS-
Compatible. DCS = low
12, 15, 20, 23,
32, 86, 88, 96 to
97, 99, Exposed
Heat Sink
AGND
REFT
connected to AGND.
13
Differential Reference Out-
put. Decoupled to ground
with 0.1 µF capacitor and to
REFB (Pin 14) with 0.1 µF and
10 µF capacitors.
(AGND) to enable DCS
(recommended). DCS =
high (AVDD1) to disable DCS.
14
REFB
Differential Reference Out-
put. Decoupled to ground
with a 0.1 µF capacitor and to
REFT (Pin 13) with 0.1 µF and
10 µF capacitors.
19, 28 to 31,
39 to 40
AVDD2
5.0 V Analog Supply ( 5%).
21
22
VIN+
VIN−
Analog Input—True.
Analog Input—Complement.
Rev. 0 | Page 13 of 40
AD9444
EQUIVALENT CIRCUITS
AVDD2
DRVDD
VIN+
AVDD2
2.5pF
1k
Ω
Ω
DX
3.5V
X1
SHA
1k
AVDD2
Figure 9. Equivalent CMOS Digital Output Circuit
VIN–
VDD
2.5pF
Figure 6. Equivalent Analog Input Circuit
DRVDD DRVDD
DCS MODE,
OUTPUT MODE,
DFS
30k
Ω
K
1.2V
LVDSBIAS
3.74kΩ
I
LVDSOUT
Figure 10. Equivalent Digital Input Circuit,
DFS, DCS MODE, OUTPUT MODE
Figure 7. Equivalent LVDS BIAS Circuit
AVDD2
DRVDD
12k
Ω
12k
Ω
Ω
CLK+
CLK–
V
V
DX–
V
150Ω
150
DX+
V
10k
Ω
10k
Ω
Figure 8. Equivalent LVDS Digital Output Circuit
Figure 11. Equivalent Sample Clock Input Circuit
Rev. 0 | Page 14 of 40
AD9444
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, sample rate = 80 MSPS, LVDS mode, DCS enabled, TA = 25°C, 2 V p-p differential
input, AIN = −0.5 dBFS, internal trimmed reference (nominal VREF = 1.0 V), unless otherwise noted.
0
0
80MSPS
80MSPS
100.3MHz @ –0.5dBFS
SNR: 72.3dB
ENOB: 11.8BITS
SFDR: 96dBc
10.1MHz @ –0.5dBFS
SNR: 73.9dB
ENOB: 12.0BITS
SFDR: 97dBc
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. 64K Point Single-Tone FFT/80 MSPS/10.1 MHz
Figure 15. 64K Point Single-Tone FFT/80 MSPS/100 MHz
0
–20
0
–20
80MSPS
125MHz @ –0.5dBFS
SNR: 71.2dB
ENOB: 11.6BITS
SFDR: 91dBc
80MSPS
30.3MHz @ –0.5dBFS
SNR: 74.0dB
ENOB: 12.1BITS
SFDR: 95dBc
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. 64K Point Single-Tone FFT/80 MSPS/30.3 MHz
Figure 16. 64K Point Single-Tone FFT/80 MSPS/125 MHz
0
–20
0
–20
80MSPS
151MHz @ –0.5dBFS
SNR: 71.1dB
ENOB: 11.5BITS
SFDR: 87dBc
80MSPS
70.3MHz @ –0.5dBFS
SNR: 73.3dB
ENOB: 11.9BITS
SFDR: 100dBc
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 17. 64K Point Single-Tone FFT/80 MSPS/151 MHz
Figure 14. 64K Point Single-Tone FFT/80 MSPS/70 MHz
Rev. 0 | Page 15 of 40
AD9444
75
74
73
75
74
73
72
71
70
69
68
67
66
65
SNR dB @ –40°C
SNR dB @ –40°C
SNR dB @ +25°C
SNR dB @ +85°C
72
71
70
69
68
67
SNR dB @ +25°C
SNR dB @ +85°C
66
65
0
20
40
60
80
100 120 140 160 180 200
0
20
40
60
80
100 120 140 160 180 200
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 18. SNR vs. Analog Input Frequency, 80 MSPS/LVDS Mode
Figure 21. SNR vs. Analog Input Frequency, 80 MSPS/CMOS Mode
105
105
SFDR dBc @ +85°C
SFDR dBc @ +85°C
100
SFDR dBc @ +25°C
100
95
90
85
80
75
70
SFDR dBc @ +25°C
95
SFDR dBc @ –40°C
90
SFDR dBc @ –40°C
85
80
75
70
0
20
40
60
80
100 120 140 160 180 200
0
20
40
60
80
100 120 140 160 180 200
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 22. SFDR vs. Analog Input Frequency, 80 MSPS/CMOS Mode
Figure 19. SFDR vs. Analog Input Frequency, 80 MSPS/LVDS Mode
120
120
SECOND –dBFS
THIRD –dBFS
SECOND –dBFS
THIRD –dBFS
110
100
90
80
70
60
50
40
30
20
10
110
100
90
80
70
60
50
40
30
20
10
SFDR –dBFS
SECOND –dBc
THIRD –dBc
SFDR –dBFS
SFDR –dBFS
SECOND –dBc
THIRD –dBc
SFDR –dBFS
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
ANALOG INPUT AMPLITUDE (dBc)
ANALOG INPUT AMPLITUDE (dBc)
Figure 20. Single-Tone SFDR/Second/Third vs.
Analog Input Level, 80 MSPS, AIN = 30.3 MHz
Figure 23. Single-Tone SFDR/Second/Third vs.
Analog Input Level 80 MSPS, AIN = 70.30 MHz
Rev. 0 | Page 16 of 40
AD9444
0
–20
0
–10
SFDR: 102dBFS
90dBFS REFERENCE LINE
–20
–30
SFDR (dBc)
–40
–40
–50
–60
–60
WORST THIRD-ORDER IMD (dBc)
SFDR (dBFS)
–70
–80
–80
–90
–100
–120
–100
–110
–120
WORST THIRD-ORDER IMD (dBFS)
0
5
10
15
20
25
30
35
40
–110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10
ANALOG INPUT LEVEL (dBFS)
0
FREQUENCY (MHz)
Figure 27. Two-Tone SFDR vs. Analog Input Level, AIN = 9.8 MHz/10.8 MHz
Figure 24. 32K Point Two-Tone FFT 80 MSPS/9.8 MHz/10.8 MHz
0
0
SFDR: –100dBFS
–10
–10
90dBFS REFERENCE LINE
–20
–30
–20
–30
SFDR (dBc)
–40
–40
–50
–50
–60
–60
WORST THIRD-ORDER IMD (dBc)
–70
–70
–80
–80
SFDR (dBFS)
–90
–90
–100
–110
–120
–100
–110
WORST THIRD-ORDER IMD (dBFS)
–120
0
5
10
15
20
25
30
35
40
–110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
FREQUENCY (MHz)
ANALOG INPUT LEVEL (dBFS)
Figure 25. 32K Point Two-Tone FFT 80 MSPS/69.3 MHz/70.3 MHz
Figure 28. Two-Tone SFDR vs. Analog Input Level, AIN = 69.3 MHz/70.3 MHz
100
100
95
90
85
80
75
70
95
90
85
80
75
70
20
30
40
50
60
70
80
90
100
110
10
20
30
40
50
60
70
80
90
100 110
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
Figure 26. SFDR vs. Sample Rate, VIN = 10.3 MHz @ −0.5 dBFS
Figure 29. SFDR vs. Sample Rate, VIN = 70.3 MHz @ −0.5 dBFS
Rev. 0 | Page 17 of 40
AD9444
0
–10
12000
10000
8000
6000
4000
2000
0
61.44MSPS
TOTAL INPUT SIGNAL
POWER: –30dBFS
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
8179 8180 8181 8182 8183 8184 8185 8186 8187
7.68
15.36
23.04
30.72
B
IN
FREQUENCY (MHz)
Figure 33. Ground Input Histogram
80 MSPS, VIN+ = VIN−, 32K Samples
Figure 30. 64K FFT, 61.44 MSPS, 4 @ WCDMA, IF = 46.08 MHz
0
250
230
210
190
170
150
130
110
90
NPR: 63.1dB
–10
–20
–30
–40
AVDD1 (3.3V)
–50
–60
–70
–80
–90
–100
–110
–120
–130
AVDD2 (5.0V)
DRVDD (3.3V)
70
50
20
30
40
50
60
70
80
90 100 110 120 130
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
SAMPLE RATE (MSPS)
Figure 31. NPR, 80 MSPS/18 MHz Notch
Figure 34. ISUPPLY vs. Sample Rate, AIN = 10.3 MHz @ −0.5 dBFS
100
105
100
95
SFDR (dBc)
SFDR - DCS ON (dBFS)
95
90
85
80
75
70
65
60
SFDR - DCS OFF (dBFS)
90
85
SNR (dB)
80
75
SNR - DCS ON (dB)
SNR - DCS OFF (dB)
70
2.5
2.7
2.9
3.1
3.3
3.5
3.7
3.9
20
30
40
50
60
70
80
CLOCK DUTY CYCLE (%)
V
COMMON-MODE (V)
IN
Figure 32. Single-Tone SNR/SFDR vs. Clock Duty Cycle,
FSAMPLE = 80 MSPS, 10.3 MHz @ −0.5 dBFS
Figure 35. Single-Tone SNR/SFDR vs.
VIN Common-Mode Voltage 80 MSPS/10.3 MHz
Rev. 0 | Page 18 of 40
AD9444
0.961
0.960
0.959
0.958
0.957
0.956
0.955
0.954
0.953
0.952
0.951
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 36. VREF vs. Temperature
Figure 38. Gain vs. Temperature
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
0
2048
4096
6144
8192 10240 12288 14336 16384
0
2048
4096
6144
8192 10240 12288 14336 16384
OUTPUT CODE
OUTPUT CODE
Figure 37. DNL Error vs. Output Code, 80 MSPS, AIN = 15 MHz
Figure 39. INL Error vs. Output Code, 80 MSPS, AIN = 15 MHz
Rev. 0 | Page 19 of 40
AD9444
THEORY OF OPERATION
Internal Reference Trim
The AD9444 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated, high bandwidth,
track-and-hold circuit that samples the signal prior to quantiza-
tion by the 14-bit pipeline ADC core. The device includes an
on-board reference and input logic that accepts TTL, CMOS, or
LVPECL levels. The digital output logic levels are user selectable
as standard 3 V CMOS or LVDS (ANSI-644 compatible) via the
OUTPUT MODE pin.
The internal reference voltage is trimmed during the produc-
tion test to adjust the gain (analog input voltage range) of the
AD9444. Therefore, there is little advantage to the user supply-
ing an external voltage reference to the AD9444. The gain trim
is performed with the AD9444’s input range set to 2 V p-p
nominal (SENSE connected to AGND). Because of this trim,
and because the 2 V p-p analog input range provides maximum
ac performance, there is little benefit to using analog input
ranges < 2 V p-p. Users are cautioned that the differential
nonlinearity of the ADC varies with the reference voltage.
Configurations that use < 2 V p-p may exhibit missing codes
and, therefore, degraded noise and distortion performance.
ANALOG INPUT AND REFERENCE OVERVIEW
A stable and accurate 0.5 V voltage reference is built into the
AD9444. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9444, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly. The
various reference modes are described in the next few sections.
VIN+
VIN–
REFT
Internal Reference Connection
0.1µF
+
ADC
CORE
A comparator within the AD9444 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 9. If SENSE is grounded,
the reference amplifier switch is connected to the internal resis-
tor divider (see Figure 40), setting VREF to ~1 V. Connecting
the SENSE pin to VREF switches the reference amplifier output
to the SENSE pin, completing the loop and providing a ~0.5 V
reference output. If a resistor divider is connected, as shown in
Figure 41, the switch again sets to the SENSE pin. This puts the
reference amplifier in a noninverting mode with the VREF
output defined as
0.1µF
10µF
REFB
0.1µF
VREF
0.1µF
+
10µF
SELECT
LOGIC
SENSE
0.5V
AD9444
R2
R1
⎛
⎝
⎞
⎟
⎠
Figure 40. Internal Reference Configuration
VREF = 0.5× 1+
⎜
VIN+
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
VIN–
REFT
0.1µF
0.1µF
REFB
+
ADC
CORE
10µF
0.1µF
VREF
+
10µF
0.1µF
SELECT
LOGIC
R2
SENSE
R1
0.5V
AD9444
Figure 41. Programmable Reference Configuration
Rev. 0 | Page 20 of 40
AD9444
Table 9. Reference Configuration Summary
Selected Mode
SENSE Voltage
Resulting VREF (V)
Resulting Differential Span (V p-p)
External Reference
Internal Fixed Reference
Programmable Reference
AVDD
VREF
0.2 V to VREF
N/A
0.5
2 × External Reference
1.0
2 × VREF
R2
R1
⎛
⎝
⎞
⎟
⎠
(See Figure 41)
0.5 × 1 +
⎜
Internal Fixed Reference
AGND to 0.2 V
1.0
2.0
External Reference Operation
The AD9444’s internal reference is trimmed to enhance the gain
accuracy of the ADC. An external reference may be more stable
over temperature, but the gain of the ADC is not likely to be
improved. Figure 36 shows the typical drift characteristics of the
internal reference in both 1 V and 0.5 V modes.
VIN+
1Vp-p
3.5V
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V.
VIN–
DIGITAL OUT = ALL 1s
DIGITAL OUT = ALL 0s
Figure 42. Differential Analog Input Range for VREF = 1 V
The AD9444 analog input voltage range is offset from ground
by 3.5 V. Each analog input connects through a 1 kΩ resistor to
the 3.5 V bias voltage and to the input of a differential buffer.
The internal bias network on the input properly biases the
buffer for maximum linearity and range (see the Equivalent
Circuits section). Therefore, the analog source driving the
AD9444 should be ac-coupled to the input pins. The recom-
mended method for driving the analog input of the AD9444 is
to use an RF transformer to convert single-ended signals to
differential (see Figure 44). Series resistors between the output
of the transformer and the AD9444 analog inputs help isolate
the analog input source from switching transients caused by the
internal sample-and-hold circuit. The series resistors, along with
the 1 kΩ resisters connected to the internal 3.5 V bias, must be
considered in impedance matching the transformers input. For
example, if RT were set to 51 Ω and RS were set to 33 Ω, along
with a 1:1 impedance ratio transformer, the input would match
a 50 Ω source with a full-scale drive of 10.0 dBm. The 50 Ω
impedance matching can also be incorporated on the secondary
side of the transformer, as shown in the evaluation board sche-
matic (see Figure 47 and Figure 59).
Analog Inputs
As with most new high speed, high dynamic range ADCs, the
analog input to the AD9444 is differential. Differential inputs
improve on-chip performance as signals are processed through
attenuation and gain stages. Most of the improvement is a result
of differential analog stages having high rejection of even-order
harmonics. There are also benefits at the PCB level. First,
differential inputs have high common-mode rejection of stray
signals, such as ground and power noise. Second, they provide
good rejection of common-mode signals, such as local oscillator
feedthrough. The specified noise and distortion of the AD9444
cannot be realized with a single-ended analog input, so such
configurations are discouraged. Contact ADI for recommenda-
tions of other 14-bit ADCs that support single-ended analog
input configurations.
With the 1 V reference (nominal value, see the Internal Refer-
ence Trim section), the differential input range of the AD9444’s
analog input is nominally 2 V p-p or 1 V p-p on each input
(VIN+ or VIN−).
R
ADT1–1WT
S
ANALOG
INPUT
SIGNAL
AIN
R
T
AD9444
R
S
AIN
0.1µF
Figure 43. Transformer-Coupled Analog Input Circuit
Rev. 0 | Page 21 of 40
AD9444
CLOCK INPUT CONSIDERATIONS
the CLK+ and CLK− pins via a transformer or capacitors.
Figure 44 shows one preferred method for clocking the AD9444.
The clock source (low jitter) is converted from single-ended-to-
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD9444 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9444 and limits the noise
presented to the sample clock inputs.
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the A/D output.
For that reason, considerable care was taken in the design of the
clock inputs of the AD9444, and the user is advised to give
careful thought to the clock source.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be
sensitive to the clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic perform-
ance characteristics. The AD9444 contains a clock duty cycle
stabilizer (DCS) that retimes the nonsampling edge, providing
an internal clock signal with a nominal 50% duty cycle. As
shown in Figure 32, noise and distortion performance are nearly
flat for a 30% to 70% duty cycle with the DCS enabled. The DCS
circuit locks to the rising edge of CLK+ and optimizes timing
internally. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern and is not re-
duced by the internal stabilization circuit. The duty cycle con-
trol loop does not function for clock rates less than 30 MHz
nominally. The loop has a time constant associated with it that
needs to be considered in applications where the clock rate can
change dynamically, which requires a wait time of 1.5 µs to 5 µs
after a dynamic clock frequency increase (or decrease) before
the DCS loop is relocked to the input signal. During the time
period the loop is not locked, the DCS loop is bypassed, and the
internal device timing is dependant on the duty cycle of the
input clock signal. In such an application, it may appropriate to
disable the duty cycle stabilizer. In all other applications,
enabling the DCS circuit is recommended to maximize ac
performance.
If a low jitter clock is available, another option is to ac couple a
differential ECL/PECL signal to the encode input pins, as shown
in Figure 46.
ADT1–1WT
CLOCK
SOURCE
CLK+
0.1µF
AD9444
CLK–
HSMS2812
DIODES
Figure 44. Crystal Clock Oscillator, Differential Encode
VT
0.1µF
ENCODE
ECL/
PECL
AD9444
0.1µF
ENCODE
VT
Figure 45. Differential ECL for Encode
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fINPUT) and rms amplitude due only to aperture jitter
(tJ) can be calculated using the following equation.
SNR = 20 log[2πfINPUT × tJ]
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle stabi-
lizer, and logic high (AVDD1 = 3.3 V) disables the controller.
In the equation, the rms aperture jitter represents the root-mean
square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter,
see Figure 46.
The AD9444 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of
performance. Maintaining 14-bit accuracy places a premium on
the encode clock phase noise. SNR performance can easily
degrade by 3 dB to 4 dB with 70 MHz analog input signals
when using a high jitter clock source. (See AN-501, Aperture
Uncertainty and ADC System Performance, for complete
details.) For optimum performance, the AD9444 must be
clocked differentially. The sample clock inputs are internally
biased to ~2.2 V, and the input signal is usually ac-coupled into
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9444. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other meth-
ods), it should be retimed by the original clock at the last step.
Rev. 0 | Page 22 of 40
AD9444
75
70
65
60
55
50
45
40
tion resistor placed at the LVDS receiver inputs results in a
0.2ps
0.5ps
nominal 350 mV swing at the receiver. LVDS mode facilitates
interfacing with LVDS receivers in custom ASICs and FPGAs
that have LVDS capability for superior switching performance
in noisy environments. Single point-to-point net topologies are
recommended with a 100 Ω termination resistor as close to the
receiver as possible. It is recommended to keep the trace length
less than 1 inch to 2 inches and to keep differential output trace
lengths as equal as possible.
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
CMOS Mode
In applications that can tolerate a slight degradation in dynamic
performance, the AD9444 output drivers can be configured to
interface with 2.5 V or 3.3 V logic families by matching DRVDD
to the digital supply of the interfaced logic. CMOS outputs are
available when OUTPUT MODE is CMOS logic low (or AGND
for convenience). In this mode, the output data bits are single-
ended CMOS, DX, as is the overrange output, OR. The output
clock is provided as a differential CMOS signal, DCO+/DCO−.
Lower supply voltages are recommended to avoid coupling
switching transients back to the sensitive analog sections of the
ADC. The capacitive load to the CMOS outputs should be
minimized, and each output should be connected to a single
gate through a series resistor (220 Ω) to minimize switching
transients caused by the capacitive loading.
1
10
100
1000
INPUT FREQUENCY (MHz)
Figure 46. SNR vs. Input Frequency and Jitter
POWER CONSIDERATIONS
Care should be taken when selecting a power source. The use of
linear dc supplies is highly recommended. Switching supplies
tend to have radiated components that may be received by the
AD9444. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 µF chip capacitors.
The AD9444 has separate digital and analog power supply
pins. The analog supplies are denoted AVDD1 (3.3 V) and
AVDD2 (5 V) and the digital supply pins are denoted DRVDD.
Although the AVDD1 and DRVDD supplies may be tied
together, best performance is achieved when the supplies are
separate. This is because the fast digital output swings can
couple switching current back into the analog supplies. Note
that both AVDD1 and AVDD2 must be held within 5% of the
specified voltage.
TIMING
The AD9444 provides latched data outputs with a pipeline delay
of 12 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and
Figure 3 for detailed timing diagrams.
OPERATIONAL MODE SELECTION
Data Format Select
The DRVDD supply of the AD9444 is a dedicated supply for the
digital outputs, in either LVDS or CMOS output modes. When
in LVDS mode, the DRVDD should be set to 3.3 V. In CMOS
mode, the DRVDD supply may be connected from 2.5 V to
3.6 V to be compatible with the receiving logic.
The data format select (DFS) pin of the AD9444 determines
the coding format of the output data. This pin is 3.3 V CMOS
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement, and DFS logic low (AGND) selecting offset binary
format. Table 10 summarizes the output coding.
DIGITAL OUTPUTS
LVDS Mode
Output Mode Select
The OUPUT MODE pin controls the logic compatibility,
as well as the pinout of the digital outputs. This pin is a CMOS
compatible input. With OUTPUT MODE = 0 (AGND), the
AD9444 outputs are CMOS-compatible and the pin assignment
for the device is defined in Table 8. With OUTPUT MODE = 1
(AVDD1, 3.3 V), the AD9444 outputs are LVDS-compatible and
the pin assignment for the device is defined in Table 7.
The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin 5 (OUTPUT MODE).
LVDS outputs are available when OUTPUT MODE is CMOS
logic high (or AVDD1 for convenience) and a 3.74 kΩ RSET
resistor is placed at Pin 7 (LVDSBIAS) to ground. Dynamic
performance, including both SFDR and SNR, is maximized
when the AD9444 is used in LVDS mode, and designers are
encouraged to take advantage of this mode. The AD9444 out-
puts include complimentary LVDS outputs for each data bit
(DX+/DX−), the overrange output (OR+/OR−), and the output
data clock output (DCO+/DCO−). The RSET resistor current is
ratioed on-chip, setting the output current at each output equal
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.
to a nominal 3.5 mA (11 × IR ). A 100 Ω differential termina-
SET
Rev. 0 | Page 23 of 40
AD9444
Table 10. Digital Output Coding
VIN+ − VIN−
Input Span = 2 V p-p (V)
VIN+ − VIN−
Input Span = 1 V p-p (V)
Digital Output
Offset Binary (D9••••••D0)
Digital Output
Twos Complement (D9••••••D0)
Code
16383
8192
8191
0
1.000
0
−0.000122
−1.00
0.500
0
−0.000061
−0.5000
11 1111 1111 1111
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0000
11 1111 1111 1111
10 0000 0000 0000
Both the LVDS and CMOS versions of the evaluation board are
compatible with the high speed ADC FIFO evaluation kit (part
number HSC-ADC-EVALA-SC). The kit includes a high speed
data capture board that provides a hardware solution for captur-
ing up to 32Ksamples of high speed ADC output data in a FIFO
memory chip (user upgradeable to 256K samples). Software is
provided to enable the user to download the captured data to a
PC via the USB port. This software also includes a behavioral
model of the AD9444 and many other high speed ADCs.
EVALUATION BOARD
Evaluation boards are offered to configure the AD9444 in
either CMOS or LVDS mode. Each represents a recommended
configuration for using the device over a wide range of sample
rates and analog input frequencies. These evaluation boards
provide all the support circuitry required to operate the ADC in
its various modes and configurations. Complete schematics and
layout plots follow and demonstrate the proper routing and
grounding techniques that should be applied at the system level.
Behavioral modeling of the AD9444 is also available at
www.analog.com/ADIsimADC. The ADIsimADC™ software
supports virtual ADC evaluation using ADI proprietary
behavioral modeling technology. This allows rapid comparison
between the AD9444 and other high speed ADCs, with or
without hardware evaluation boards.
It is critical that signal sources with very low phase noise
(< 1 ps rms jitter) be used to realize the ultimate performance
of the converter. Proper filtering of the input signal, to remove
harmonics and lower the integrated noise at the input, is also
necessary to achieve the specified noise performance.
The evaluation boards are shipped with an ac to 6 V dc power
supply. The evaluation boards include low dropout regulators to
generate the various dc supplies required by the AD9444 and its
support circuitry. Separate power supplies are provided to iso-
late the DUT from the support circuitry. Each input configura-
tion can be selected by proper connection of various jumpers
(see Figure 47 to Figure 50 and Figure 59 to Figure 61).
The AD9444 LVDS evaluation board includes an on-board,
LVDS-to-CMOS translator, but the user may choose to remove
the translator and terminations to access the LVDS outputs
directly.
The CMOS evaluation board includes a buffer for the output
data and the DCO output clock of the AD9444.
Rev. 0 | Page 24 of 40
AD9444
LVDS EVALUATION BOARD SCHEMATICS
GND
GND
GND
H4
MTHOLE6
8
7
6
5
4
3
2
1
VDL
H3
MTHOLE6
DRVDD
H2
MTHOLE6
VCC
5V
GND
H1
MTHOLE6
GND
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
D2+
D2–
D11_C/D7_YN
D11_T/D8_YN
D12_C/D9_YN
D11–
D2_TN
D2_CN
GND
D11+
DRGND
D12–
D12+
DRVDD
D1+
D12_T/D10_YN
D13_C/D11_YN
DRVDD
D1_TN
D1_CN
D0_TN
D0_CN
VCC
D13–
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
D1–
D13_T/D12_YN
D13+ (MSB)
DRGND
DRVDD
OR–
GND
D0+
(LSB) D0–
AVDD1
AVDD1
DRVDD
DOR_C/D13_YN
DOR_T/DOR_YN
GND
OR+
VCC
AGND
AVDD1
AVDD2
AVDD2
AVDD1
CLK–
1
2
VCC
5V
3
GND
AGND
VCC
ENCB
ENC
VCC
VCC
VCC
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
VCC
CLK+
CR2
VCC
AVDD1
VCC
AVDD1
C1
AGND
AVDD2
AVDD2
VCC
GND
VCC
AVDD1
AVDD1
AGND
AGND
GND
C40
0.1µF
VCC
GND
GND
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AGND
DCS MOD
5V
VCC
VCC
R39
XX
C36
0.1µF
EPAD
101
C26
0.1µF
50Ω
R7
50Ω
R8
XTALINPUTB
C2
0.1µF
OPTIONAL
R28
33Ω
R35
33Ω
C51
10µF
C91
0.1µF
C3
0.1µF
C9
0.1µF
GND
C24
0.1µF
R37
XX
R27
XX
+
R36
XX
R20
XX
R1
R2
3.8kΩ
3.8kΩ
R3
3.8kΩ
Figure 47. LVDS Mode Evaluation Board Schematic
Rev. 0 | Page 25 of 40
AD9444
POWER OPTIONS
ADP3338
U4
ADP3338
U15
P4
3.3V
3.3V
PJ-102A
1
2
3
1
2
3
2
3
1
GND
GND
2
3
1
4
4
OUT1
IN
OUT1
IN
OUT
OUT
+
+
+
C1
C6
C33
10µF
10µF
10µF
+
+
C57
C87
10µF
10µF
ADP3338
ADP3338
U14
U3
3.3V
5V
1
2
3
1
2
3
GND
OUT1
IN
GND
OUT1
IN
4
4
OUT
OUT
+
+
C34
C4
10µF
10µF
+
+
C88
C89
10µF
10µF
Figure 48. LVDS Mode Evaluation Board Schematic (Continued)
VCC
+
P19
C43
0.1µF
C35
0.1µF
C32
0.1µF
C30
0.1µF
C28
0.1µF
C27
0.1µF
C48
0.1µF
C50
0.1µF
C60
0.1µF
C61
0.1µF
C46
0.1µF
C75
0.1µF
C64
10µF
GND
GND
VCC
C10
XX
C11
XX
C14
XX
C17
XX
C16
XX
C15
XX
C31
XX
C37
XX
C38
XX
C29
XX
C19
XX
C18
XX
C90
XX
GND
DRVDD
GND
DRVDD
+
C69
XX
C70
XX
C45
XX
C49
XX
C59
XX
C65
10µF
C47
0.1µF
C23
0.1µF
C22
0.1µF
C21
0.1µF
C20
0.1µF
GND
5V
EXTREF
GND
5V
+
+
C55
10µF
C71
XX
C72
XX
C73
XX
C62
XX
C56
10µF
C85
0.1µF
C53
0.1µF
C52
0.1µF
C58
0.1µF
GND
GND
Figure 49. LVDS Mode Evaluation Board Schematic (Continued)
Rev. 0 | Page 26 of 40
AD9444
U7
SN75LVDS386
1
2
3
4
5
6
7
8
9
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DOR_T/DOR_YN
DOR_C/D13_YN
D13_T/D12_YN
D13_C/D11_YN
D12_T/D10_YN
D12_C/D9_YN
A1A
A1B
A2A
A2B
A3A
A3B
A4A
A4B
B1A
B1B
B2A
B2B
B3A
B3B
B4A
B4B
C1A
C1B
C2A
C2B
C3A
C3B
C4A
C4B
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
GND
VCC1
VCC2
GND1
ENA
A1Y
A2Y
A3Y
A4Y
ENB
B1Y
B2Y
B3Y
B4Y
GND2
VCC3
VCC4
GND3
C1Y
C2Y
C3Y
C4Y
ENC
D1Y
D2Y
D3Y
D4Y
END
GND4
VCC5
VCC6
GND5
GND
VDL
VDL
GND
VDL
RZ5
220
P6
C40MS
RSO16ISO
R1
R2
R3
R4
R5
R6
R7
R8
1
2
3
4
5
6
7
8
16
ORO
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
P39
GND
GND
P40
P38
P36
P34
P32
P30
P28
P26
P24
P22
P20
P18
P16
P14
P12
P10
P8
15
D13O
P37
P35
P33
P31
P29
P27
P25
P23
P21
P19
P17
P15
P13
P11
P9
D11_T/D8_YN
D11_C/D7_YN
D10_T/D6_YN
D10_C/D5_YN
D9_T/D4_YN
D9_C/D3_YN
D8_T/D2_YN
14
D12O
GND
GND
DOR_C/D13_YN
D13_C/D11_YN
D12_C/D9_YN
D11_C/D7_YN
D10_C/D5_YN
13
D11O
DOR_T/DOR_YN
D13_T/D12_YN
D12_T/D10_YN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDL
12
D10O
11
D9O
10
D11_T/D8_YN
D10_T/D6_YN
D9_T/D4_YN
D8O
D8_C/D1_YN
D7_T/D0_YN
D7_CN
DRN
9
GND
VDL
VDL
GND
DRP
D7O
D9_C/D3_YN
D8_C/D1_YN
D7_CN
220
D8_T/D2_YN
D7_T/D0_YN
DRBN
RSO16ISO
D6_TN
D6_CN
D5_TN
D5_CN
D4_TN
D4_CN
D3_TN
D3_CN
D2_TN
D2_CN
D1_TN
D1_CN
D0_TN
D0_CN
R1
1
2
3
4
5
6
7
8
16
D6O
DRN
DRBN
R2
R3
R4
R5
R6
R7
R8
15
D5O
D6_TN
D5_TN
D4_TN
D3_TN
D2_TN
D1_TN
D0_TN
GND
D6_CN
14
VDL
D4O
D5_CN
13
D3O
D4_CN
12
D3_CN
D2O
7
P7
11
D2_CN
D1O
VDL
GND
VDL
VDL
GND
6
5
P5
P6
D1_CN
10
D0O
4
3
P3
P4
D0_CN
GND
9
2
1
P1
P2
RZ4
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
39
P39
P37
P35
P33
P31
P29
P27
P25
P23
P21
P19
P17
P15
P13
P11
P9
GND
P40
P38
P36
P34
P32
P30
P28
P26
P24
P22
P20
P18
P16
P14
P12
P10
P8
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
DRO
GND
D13O
D12O
D11O
D10O
D9O
D8O
D7O
D6O
D5O
D4O
D3O
D2O
D1O
D0O
ORO
74VCX86
3
6
1
2
4
5
9
1A
1B
2A
2B
3A
1Y
2Y
3Y
4Y
GND
00
8
DRO
R52
00
XORN
11
14
VDL
E43
E34
R53
10 3B
12 4A
13 4B
PWR
GND
E32
VDL
GND
GND
7
GND
U10
VDL
+
C76
10µF
C97
0.1µF
C82
0.1µF
C80
0.1µF
81
0.1µF
GND
7
P7
6
5
P5
P6
4
3
P3
P4
2
1
P1
GND
P2
GND
P3
C40MS
Figure 50. LVDS Mode Evaluation Board Schematic (Continued)
Rev. 0 | Page 27 of 40
AD9444
Figure 54. LVDS Mode Evaluation Board Layout, Ground Plane 2
Figure 55. LVDS Mode Evaluation Board Layout, Power Plane 1
Figure 56. LVDS Mode Evaluation Board Layout, Power Plane 2
Figure 51. LVDS Mode Evaluation Board Layout, Primary Side
Figure 52. LVDS Mode Evaluation Board Layout, Secondary Side
Figure 53. LVDS Mode Evaluation Board Layout, Ground Plane 1
Rev. 0 | Page 28 of 40
AD9444
Figure 58. LVDS Mode Evaluation Board Layout, Secondary Silkscreen
Figure 57. LVDS Mode Evaluation Board Layout, Primary Silkscreen
Rev. 0 | Page 29 of 40
AD9444
LVDS MODE EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 11.
Item Qty. REFDES
Description
Manufacturer
PCSM
MFG_PART_NO
1
2
1
AD9444PCB
PCB, AD9444 LVDS Engineering Evaluation Board
Capacitors, Tantalum, SMT BCAPTAJC, 10 µF, 16 V, 10%
AD9444LVDSCUSTREVC
T491C106K016AS
16
C1, C4, C6,
C33, C34,
C39, C44,
C55 to C57,
C64, C65,
C76, C87 to
C89
KEMET
3
38
C2, C3, C5,
C9, C12, C20
to C24, C26
to C28, C30,
C32, C35,
C40, C42,
C43, C46 to
C48, C50,
C52, C53,
C58, C60,
C61, C75,
C80 to C82,
C85, C86,
C91 to C93,
C97
Capacitors, 0.1 µF 10 V Ceramic X5R 0402
Panasonic
ECJ-0EB1A104K
4
5
6
1
C51
CR2
Capacitor, Ceramic 10 µF 6.3 V X5R 0805
KEMET
Panasonic
3M
C0805C106K9PACTU
MA716-(TX)
1
Diode, Dual Schottky HSMS2812, SOT-23, 30 V, 20 mA
17
E1 to E3, E24, 40-Pin Breakable Header
2340-611TN
to E27, E32,
E34, E38,
E39, E40,
E41, E43,
E46, E47, E52
7
2
1
1
1
1
2
1
4
J1, J4
L1
Connector, Gold, Male, Coaxial, SMA, Vertical
Johnston Comp.
Coilcraft
142-0701-201
0603CJ-10NXGBU
TSW-120-08-T-D-RA
RAPC722
8
10 nH Inductor
9
P3
Header, 40-Pin, Male, 40-Pin Right Angle
Power Jack
Samtec
10
11
12
13
14
P4
Swithcraft
Panasonic
Panasonic
Panasonic
Panasonic
R3
Resistor, 3.6 kΩ 1/16 W 1% 0402 SMD
Resistor, 36 Ω 1/16 W 5% 0402 SMD
Resistor, 49.9 Ω 1/16 W 1% 0402 SMD
ERJ-2GEJ362X
ERJ-2GEJ360X
ERJ-2RKF49R9X
ERJ-2RKF1001X
R4, R6
R8
R9, R12, R14, Resistor, 1.00 kΩ 1/16 W 1% 0402 SMD
R15
15
16
2
3
R28, R35
Resistor, 33 Ω 1/16 W 5% 0402 SMD
Resistor, 0 Ω 1/16 W 5% 0402 SMD
Panasonic
Panasonic
ERJ-2GEJ330X
ERJ-2GE0R00X
R39, R52,
R53
17
18
19
20
21
22
23
24
25
2
2
1
3
1
1
1
1
4
RZ4, RZ5
T3, T5
U1
22 Ω Resistor Array, 16 Term
Transformer, ADT1-1WT, CD542, ADT1-1WT
14-Bit, 80 MSPS ADC
CTS Corp.
Mini-Circuits
ADI
742163220JTR
ADT1-1WT
AD9444BSVZ-80
ADP3338-3.3 V
ADP3338-5.0 V
MX045-80
U3, U4, U15
U14
3.3 V Voltage Regulator
ADI
5 V Voltage Regulator
ADI
U6
Clock Oscillator, 80 MHz
CTS Reeves
U7
LVDS-to-CMOS Translator with 100 Term
2 Input XOR Gate
Texas Instruments SN75LVDT386DGG
U10
Fairchild
AMP
74VCX86M
5-330808-3
U6
Pin Sockets, Closed End
Rev. 0 | Page 30 of 40
AD9444
Item Qty. REFDES
Description
Manufacturer
MFG_PART_NO
26
24
C10, C11,
C13, to C19,
C29, C31,
C36 to C38,
C45, C49,
C59, C62,
C69, C70 to
C73, C901
Capacitors, Select 10 V Ceramic X5R 0402
Panasonic
27
28
29
1
2
1
J51
Connector, Gold, Male, Coaxial, SMA, Vertical
Power Connectors
Johnston Comp.
Weiland
142-0701-201
P5, P61
R1, R2, R5,
R7, R131
Resistors, Select 1/16 W 1% 0402 SMD
Panasonic
30
31
1
5
R17 to R20,
R27, R36 to
R38, R401
U21
Resistors, Select 1/16 W 1% 0402 SMD
XO Select
Panasonic
Vectron
1 Parts not placed.
Rev. 0 | Page 31 of 40
AD9444
CMOS EVALUATION BOARD SCHEMATICS
GND
8
VDL
7
6
5
4
3
2
1
GND
GND
DRVDD
VCC
5V
GND
H4
MTHOLE6
H3
MTHOLE6
H2
MTHOLE6
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
D11C/D7YN
D11T/D8YN
D12C/D9YN
DNC
DNC
D7
H1
MTHOLE6
D8
GND
GND
DRGND
DRVDD
DNC
D9
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
D12T/D10YN
D13C/D11YN
DRVDD
D10
D11
D13T/D12YN
GND
DNC
D12
DNC
DRGND
DRVDD
(MSB) D13
OR
DRVDD
DORC/D13Y
DORT/DORY
GND
DNC
VCC
VCC
AVDD1
AVDD1
AVDD2
AVDD2
AVDD1
CLK–
AGND
DRVDD
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
AVDD1
AGND
DCS MODE
1
2
VCC
5V
3
GND
VCC
ENCB
ENC
VCC
VCC
VCC
VCC
CLK+
CR2
VCC
AVDD1
VCC
AVDD1
C1
AGND
AVDD2
AVDD2
VCC
GND
VCC
GND
C40
0.1µF
VCC
GND
GND
AVDD2
AVDD2
AVDD1
AVDD1
5V
VCC
VCC
R39
XX
C36
0.1µF
EPAD
101
C26
0.1µF
50Ω
R7
50Ω
R8
C78
0.1µF
OPTIONAL
R28
33Ω
R35
33Ω
C51
10µF
C91
0.1µF
C3
0.1µF
C9
0.1µF
GND
R37
XX
C2
R27
0.1µF
XX
R36
XX
R20
XX
+
R1
R2
3.8kΩ
3.8kΩ
R3
3.8kΩ
Figure 59. CMOS Mode Evaluation Board Schematic
Rev. 0 | Page 32 of 40
AD9444
ADP3338
U8
ADP3338
U15
P4
3.3V
3.3V
PJ-102A
1
2
3
1
2
3
2
3
1
GND
GND
2
3
1
4
4
OUT1
IN
OUT1
IN
OUT
OUT
+
C1
C6
C33
+
+
10µF
10µF
10µF
C57
C87
+
+
10µF
10µF
ADP3338
ADP3338
U14
U3
3.3V
5V
1
2
3
1
2
3
GND
OUT1
IN
GND
OUT1
IN
4
4
OUT
OUT
C34
C4
+
+
10µF
10µF
C88
C89
+
+
10µF
10µF
Figure 60. CMOS Mode Evaluation Board Schematic (Continued)
Rev. 0 | Page 33 of 40
AD9444
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
P39
P37
P35
P33
P31
P29
P27
P25
P23
P21
P19
P17
P15
P13
P11
P9
GND
DRM
GND
D13M
D12M
D11M
D10M
D9M
D8M
D7M
D6M
D5M
D4M
D3M
D2M
D1M
D0M
ORM
P40
P38
P36
P34
P32
P30
P28
P26
P24
P22
P20
P18
P16
P14
P12
P10
P8
RZ1
220
RZ5
220
RSO16ISO
RSO16ISO
U5
SN74LVCH16373A
R1
R2
R3
R4
R5
R6
R7
R8
R1
R2
R3
R4
R5
R6
R7
R8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
ORM
D13M
D12M
D11M
D10M
D9M
DORT/DORY
DORC/D13Y
D13T/D12Y
D13C/D11Y
D12T/D10Y
D12C/D9Y
D11T/D8Y
Q = OUTPUT
D = INPUT
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
LE2
OE2
2Q8
2Q7
GND
2Q6
2Q5
VCC
2Q4
2Q3
GND
2Q2
2Q1
1Q8
1Q7
XOR2IN
GND
GND
VDL
GND
2D8
2D7
GND
2D6
2D5
VCC
2D4
2D3
GND
2D2
2D1
1D8
1D7
GND
1D6
1D5
VCC
1D4
1D3
GND
1D2
1D1
LE1
GND
VDL
D8M
9
GND
D7M
D11C/D7Y
RZ2
RSO16ISO
220
RZ5
RSO16ISO
220
R1
R1
1
2
3
4
5
6
7
8
16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
VDL
GND
GND
GND
VDL
GND
1Q6
1Q5
VCC
1Q4
1Q3
GND
1Q2
1Q1
OE1
D6M
D5M
D4M
D3M
D2M
D1M
D0M
D10T/D6Y
D10C/D5Y
D9T/D4Y
D9C/D3Y
D8T/D2Y
D8C/D1Y
D7T/D0Y
R2
R3
R4
R5
R6
R7
R8
R2
R3
R4
R5
R6
R7
R8
15
14
13
12
11
10
9
7
P7
GND
6
5
P5
P6
4
3
P3
XOR2IN
P4
2
1
P1
GND
GND
P2
RZ4
RZ4
P3
C40MS
NOT PLACED
00
R50
00
COUTB
U4
74VCX86
XORZIN
COUT
VDL
R16
00
3
6
1
1A
1B
2A
2B
3A
DRM
1Y
E49
R14
00
2
4
5
9
E42
R41
E45
GND
GND
2Y
3Y
4Y
8
GATE
00
11
DRM
10 3B
12 4A
13 4B
R42
PWR
GND
14
7
VDL
GATE2
VDL
E32
E30
GND
E31
GND
U10
VDL
+
C66
10µF
C25
0.1µF
C41
0.1µF
C24
0.1µF
C68
0.1µF
C67
0.1µF
63
0.01µF
GND
Figure 61. CMOS Mode Evaluation Board Schematic (Continued)
Rev. 0 | Page 34 of 40
AD9444
Figure 65. CMOS Mode Evaluation Board Layout, Ground Plane 2
Figure 62. CMOS Mode Evaluation Board Layout, Primary Side
Figure 63. CMOS Mode Evaluation Board Layout, Secondary Side
Figure 64. CMOS Mode Evaluation Board Layout, Ground Plane 1
Figure 66. CMOS Mode Evaluation Board Layout, Power Plane 1
Figure 67. CMOS Mode Evaluation Board Layout, Power Plane 2
Rev. 0 | Page 35 of 40
AD9444
Figure 69. CMOS Mode Evaluation Board Layout, Secondary Silkscreen
Figure 68. CMOS Mode Evaluation Board Layout, Primary Silkscreen
Rev. 0 | Page 36 of 40
AD9444
CMOS MODE EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 12.
Item Qty. REFDES
Description
Manufacturer
MFG_PART_NO
1
2
1
AD9444PCB
PCB, AD9444 LVDS Evaluation Board
PCSM
AD9444LVDSCUSTREVC
T491C106K016AS
16
C1, C4, C6, C33, C34,
C39, C44, C55 to
C57, C64 to C66,
C87 to C89
Capacitors, Tantalum, SMT BCAPTAJC, 10 µF, 16 V, 10% KEMET
3
32
C2, C3, C5, C9, C12,
C20 to C23, C26 to
C28, C30, C32, C35,
C40, C42, C43, C46 to
C48, C50, C52, C53,
C58, C60, C61, C75,
C78, C85, C91, C92
Capacitors, 0.1 µF 10 V Ceramic X5R 0402
Panasonic
ECJ-0EB1A104K
4
5
C24, C25, C41, C67,
C68
Capacitors, 0.1 µF 16 V Ceramic X7R 0603
Panasonic
ECJ-1VB1C104K
5
6
7
1
C51
CR2
Capacitor, Ceramic 10 µF 6.3 V X5R 0805
Diode, Dual Schottky HSMS2812, SOT-23, 30 V, 20 mA
40-Pin Breakable Header
KEMET
Panasonic
3M
C0805C106K9PACTU
MA716-(TX)
1
20
E1 to E3, E24 to E27,
E30 to E32, E38 to
E42, E45 to E47,
E49, E52
2340-611TN
8
2
1
1
1
1
2
1
4
2
2
1
4
2
1
4
1
1
4
J1, J4
Connector, Gold, Male, Coaxial, SMA, Vertical
10 nH O402 Inductor
Johnston Comp. 142-0701-201
9
L1
Coilcraft
Samtec
0402CS-10NX_B_
TSW-120-08-T-D-RA
RAPC722
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P3
Header, 40-Pin, Male, 40-Pin Right Angle
Power Jack
P4
Swithcraft
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
CTS Corp.
Mini-Circuits
ADI
R3
Resistor, 3.6 kΩ 1/16 W 1% 0402 SMD
Resistors, 36 Ω 1/16 W 5% 0402 SMD
Resistor, 49.9 Ω 1/16 W 1% 0402 SMD
Resistors, 1.00 kΩ 1/16 W 1% 0402 SMD
Resistors, 0 Ω 1/10 W 5% 0603 SMD
Resistors, 33 Ω 1/16 W 5% 0402 SMD
Resistor, 0 Ω 1/16 W 5% 0402 SMD
220 Ω Resistor Array, 16 Term
Transformer, ADT1-1WT, CD542, ADT1-1WT
14-Bit, 80 MSPS ADC
ERJ-2GEJ362X
ERJ-2GEJ360X
ERJ-2RKF49R9X
ERJ-2RKF1001X
ERJ-3GEY0R00V
ERJ-2GEJ330X
ERJ-2GE0R00X
742163221JTR
ADT1-1WT
R4, R6
R8
R9, R12, R15, R21
R14, R50
R28, R35
R39
RZ1 to RZ3, RZ6
T3, T5
U1
AD9444BSVZ-80
ADP3338-3.3 V
ADP3338-5.0 V
74LVTH162374
5-330808-3
U3, U8, U15
U14
3.3 V Voltage Regulator
ADI
5 V Voltage Regulator
ADI
U5
16-Bit Flip Flop
Fairchild
AMP
U6
Pin Sockets, Closed End
Rev. 0 | Page 37 of 40
AD9444
Item Qty. REFDES
Description
Manufacturer
MFG_PART_NO
26
26
C10, C11, C13, C14 to Capacitors, Select 10 V Ceramic X5R 0402
C19, C29, C31, C36 to
Panasonic
C37, C38, C45, C49,
C59, C62,C69, C70 to
C73, C90, C93, C961
27
28
1
J51
Connector, Gold, Male, Coaxial, SMA, Vertical
Resistors, Select 1/16 W 1% 0402 SMD
Johnston Comp. 142-0701-201
Panasonic
15
R1,R2,R5,R7, R13,
R17 to R20, R27,
R36 to R401
29
30
31
32
3
1
1
2
R16, R41, R421
C631
U41
Resistors, Select 1/16 W 5% 0603 SMD
Capacitor, Select 10 V Ceramic X5R 0603
XOR 74VCX86D
Panasonic
Panasonic
Fairchild
Weiland
74VCX86D
P5, P61
Power Connectors
1 Parts not placed.
Rev. 0 | Page 38 of 40
AD9444
OUTLINE DIMENSIONS
1.20
MAX
16.00 SQ
14.00 SQ
0.75
0.60
0.45
100
1
76
75
76
100
75
1
SEATING
PLANE
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
CONDUCTIVE
HEAT SINK
51
51
25
25
26
50
50
26
0.20
0.09
1.05
1.00
0.95
6.50
NOM
7°
3.5°
0°
0.15
0.05
COPLANARITY
0.08
0.27
0.22
0.17
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MS-026AED-HD
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
NOTES
2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
3. THE EXPOSED HEAT SINK SOLDERED TO THE GROUND PLANE IS REQUIRED FOR THE 100-LEAD TQFP/EP.
Figure 70. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9444BSVZ-801
AD9444-CMOS/PCB
AD9444-LVDS/PCB
Temperature Range
Package Description
Package Outline
SV-100-1
–40°C to +85°C
100-Lead TQFP_EP
CMOS Mode Evaluation Board
LVDS Mode Evaluation Board
1 Z = Pb-free part.
Rev. 0 | Page 39 of 40
AD9444
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05089–0–10/04(0)
Rev. 0 | Page 40 of 40
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