AD9516-5BCPZ_技术文档

14-Output Clock Generator

AD9516-5

FEATURES

FUNCTIONAL BLOCK DIAGRAM

CP

Low phase noise, phase-locked loop (PLL)

External VCO/VCXO to 2.4 GHz optional

1 differential or 2 single-ended reference inputs

Reference monitoring capability

Automatic revertive and manual reference

switchover/holdover modes

REF1

REF2

STATUS

MONITOR

REFIN

Accepts LVPECL, LVDS, or CMOS references to 250 MHz

Programmable delays in path to PFD

Digital or analog lock detect, selectable

Six 1.6 GHz LVPECL outputs, arranged in 3 groups

Each group shares a 1-to-32 divider with coarse phase delay

Additive output jitter: 225 fs rms

Channel-to-channel skew paired outputs of <10 ps

Four 800 MHz LVDS outputs, arranged in 2 groups

Each group has 2 cascaded 1-to-32 dividers with coarse

phase delay

CLK

DIVIDER

AND MUXes

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

DIV/Φ

LVPECL

∆t

DIV/Φ

LVDS/CMOS

Additive output jitter: 275 fs rms

SERIAL CONTROL PORT

AND

Fine delay adjust (Δt) on each LVDS output

Each LVDS output can be reconfigured as two 250 MHz

CMOS outputs

Automatic synchronization of all outputs on power-up

Manual output synchronization available

Available in 64-lead LFCSP

AD9516-5

DIGITAL LOGIC

Figure 1.

The AD9516-5 features six LVPECL outputs (in three pairs)

and four LVDS outputs (in two pairs). Each LVDS output can

be reconfigured as two CMOS outputs. The LVPECL outputs

operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and

the CMOS outputs operate to 250 MHz.

APPLICATIONS

Low jitter, low phase noise clock distribution

10/40/100 Gb/sec networking line cards, including SONET,

Synchronous Ethernet, OTU2/3/4

Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

Each pair of outputs has dividers that allow both the divide ratio

and coarse delay (or phase) to be set. The range of division for

the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow

a range of divisions up to a maximum of 1024.

ATE and high performance instrumentation

The AD9516-5 is available in a 64-lead LFCSP and can be

operated from a single 3.3 V supply. An external VCO, which

requires an extended voltage range, can be accommodated by

connecting the charge pump supply (V_CP) to 5.5 V. A separate

LVPECL power supply can be from 2.375 V to 3.6 V (nominal).

GENERAL DESCRIPTION

The AD9516-5¹provides a multi-output clock distribution function

with subpicosecond jitter performance, along with an on-chip PLL

that can be used with an external VCO/VCXO of up to 2.4 GHz.

The AD9516-5 is specified for operation over the industrial

range of −40°C to +85°C.

The AD9516-5 emphasizes low jitter and phase noise to

maximize data converter performance, and it can benefit other

applications with demanding phase noise and jitter requirements.

For applications requiring an integrated EEPROM, or needing

additional outputs, the AD9520-5 and AD9522-5 are available.

¹AD9516 is used throughout the data sheet to refer to all members of the AD9516

family. However, when AD9516-5 is used, it refers to that specific member of the

AD9516 family.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD9516-5

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Performance Characteristics ........................................... 18

Terminology.................................................................................... 23

Detailed Block Diagram ................................................................ 24

Theory of Operation ...................................................................... 25

Operational Configurations...................................................... 25

Lock Detect ................................................................................. 31

Clock Distribution ..................................................................... 35

Reset Modes ................................................................................ 43

Power-Down Modes .................................................................. 43

Serial Control Port ......................................................................... 44

Serial Control Port Pin Descriptions....................................... 44

General Operation of Serial Control Port............................... 44

Instruction Word (16 Bits)........................................................ 45

MSB/LSB First Transfers ........................................................... 45

Thermal Performance.................................................................... 48

Register Maps.................................................................................. 49

Register Map Overview ............................................................. 49

Register Map Descriptions........................................................ 52

Applications Information.............................................................. 71

Frequency Planning Using the AD9516 .................................. 71

Using the AD9516 Outputs for ADC Clock Applications .... 71

LVPECL Clock Distribution..................................................... 72

LVDS Clock Distribution.......................................................... 72

CMOS Clock Distribution ........................................................ 73

Outline Dimensions....................................................................... 74

Ordering Guide .......................................................................... 74

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Power Supply Requirements ....................................................... 4

PLL Characteristics ...................................................................... 4

Clock Inputs .................................................................................. 6

Clock Outputs............................................................................... 6

Clock Output Additive Phase Noise (Distribution Only;

VCO Divider Not Used).............................................................. 7

Clock Output Absolute Time Jitter (Clock Generation

Using External VCXO) ................................................................ 8

Clock Output Additive Time Jitter (VCO Divider

Not Used)....................................................................................... 8

Clock Output Additive Time Jitter (VCO Divider Used) ....... 9

Delay Block Additive Time Jitter................................................ 9

Serial Control Port ..................................................................... 10

PD RESET

SYNC

Pins ..................................................... 10

,

, and

LD, STATUS, and REFMON Pins............................................ 11

Power Dissipation....................................................................... 11

Timing Characteristics .............................................................. 13

Absolute Maximum Ratings.......................................................... 15

Thermal Resistance .................................................................... 15

ESD Caution................................................................................ 15

Pin Configuration and Function Descriptions........................... 16

Rev. A | Page 2 of 76

AD9516-5

REVISION HISTORY

8/11—Rev. 0 to Rev. A

Changes to A and B Counters, Digital Lock Detect (DLD),

Changes to Features, Applications, and General Description..... 1

Changes to CPRSET Pin Resistor Parameter, Table 1 .................. 4

Change to P = 2 DM (2/3) Parameter, Table 2 .............................. 5

Changes Test Conditions/Comments, Table 4 .............................. 6

Moved Table 5 to End of Specifications and Renumbered

Sequentially......................................................................................13

Change to Shortest Delay Range Parameter,

Test Conditions/Comments, Table 14 ..........................................13

Moved Timing Diagrams ...............................................................14

Change to Endnote, Table 16.........................................................15

Change to Caption, Figure 8..........................................................18

Change to Captions, Figure 20 and Figure 21 .............................20

Moved Figure 23 and Figure 24.....................................................21

Added Figure 31; Renumbered Sequentially...............................22

Change to Mode 1—Clock Distribution or External VCO <

1600 MHz Section ..........................................................................25

Changes to Mode 2 (High Frequency Clock Distribution)—

CLK or External VCO > 1600 MHz; Change to Table 22..........26

Change to Charge Pump (CP) Section.........................................28

Changes to PLL Reference Inputs and Reference Switchover

Sections.............................................................................................29

Changes to Prescaler Section and Table 24..................................30

and Current Source Digital Lock Detect (CSDLD) Sections .... 31

Change to Holdover Section.......................................................... 32

Changes to Automatic/Internal Holdover Mode........................ 34

Changes to Clock Distribution Section........................................ 35

Changes to Channel Dividers—LVDS/CMOS Outputs

Section .............................................................................................. 37

Change to the Instruction Word (16 Bits) Section ..................... 45

Change to Figure 53........................................................................ 46

Changes to θ_JAand Ψ_JTParameters, Table 46............................... 48

Changes to Register Address 0x003 and

Register Address 0x01C, Table 47................................................. 49

Changes to Register Address 0x003, Table 48 ............................. 52

Changes to Register Address 0x016, Bits[2:0], Table 49 ............ 54

Changes to Register Address 0x01C, Bits[4:3], Table 49 ........... 57

Changes to Register Address 0x191, Register Address 0x194,

and Register Address 0x197, Bit 5, Table 53................................ 66

Added Frequency Planning Using the AD9516 Section............ 71

Changes to LVPECL Clock Distribution and LVDS Clock

Distribution Sections; Changes to Figure 59, Figure 60, and

Figure 61...........................................................................................72

1/09—Revision 0: Initial Version

Rev. A | Page 3 of 76

AD9516-5

SPECIFICATIONS

Typical is given for V_S= V_{S_LVPECL}= 3.3 V 5ꢀ; V_S≤ V_CP≤ 5.25 V; T_A= 25°C; R_SET= 4.12 kΩ; CP_RSET= 5.1 kΩ, unless otherwise noted.

Minimum and maximum values are given over full V_Sand T_A(−40°C to +85°C) variation.

POWER SUPPLY REQUIREMENTS

Table 1.

Parameter

Min

3.135

2.375

V_S

Typ

Max

3.465

VS

Unit

V

kΩ

Test Conditions/Comments

3.3 V 5ꢀ

Nominally 2.5 V to 3.3 V 5ꢀ

Nominally 3.3 V to 5.0 V 5ꢀ

Sets internal biasing currents; connect to ground

Sets internal CP current range, nominally 4.8 mA

(CP_lsb = 600 μA); actual current can be calculated by:

CP_lsb = 3.06/CPRSET; connect to ground

V_S

V_{S_LVPECL}

V_CP

RSET Pin Resistor

CPRSET Pin Resistor

3.3

5.25

4.12

5.1

2.7

10

PLL CHARACTERISTICS

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE INPUTS

Differential Mode (REFIN, REFIN)

Differential mode (can accommodate single-ended

input by ac grounding undriven input)

Input Frequency

Input Sensitivity

0

250

MHz

Frequencies below about 1 MHz should be dc-coupled;

be careful to match V_CM(self-bias voltage)

250

mV p-p PLL figure of merit (FOM) increases with increasing slew

rate; see Figure 13

Self-Bias Voltage, REFIN

Input Resistance, REFIN

Dual Single-Ended Mode (REF1, REF2)

Input Frequency (AC-Coupled)

Input Frequency (DC-Coupled)

Input Sensitivity (AC-Coupled)

Input Logic High

1.35

1.30

4.0

1.60

1.50

4.8

1.75

1.60

5.9

V

Self-bias voltage of REFIN¹

Self-biased¹

kΩ

4.4

5.3

6.4

Self-biased¹

Two single-ended CMOS-compatible inputs

Slew rate > 50V/μs

Slew rate > 50V/μs; CMOS levels

Should not exceed V_Sp-p

20

0

250

MHz

V p-p

V

0.8

2

2.0

Input Logic Low

Input Current

Input Capacitance

0.8

+100 μA

pF

V

−100

Each pin, REFIN/REFIN (REF1/REF2)

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency

100

45

MHz

ns

Antibacklash pulse width = 1.3 ns, 2.9 ns

Antibacklash pulse width = 6.0 ns

Register 0x017[1:0] = 01b

Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b

Register 0x017[1:0] = 10b

Antibacklash Pulse Width

1.3

2.9

6.0

CHARGE PUMP (CP)

I_CPSink/Source

Programmable

High Value

Low Value

4.8

0.60

2.5

2.7/10

1

2

1.5

2

mA

ꢀ

kΩ

nA

ꢀ

With CP_RSET= 5.1 kΩ

Absolute Accuracy

CPRSET Range

I_CPHigh Impedance Mode Leakage

Sink-and-Source Current Matching

I_CPvs. CP_V

CP_V= V_CP/2

0.5 < CP_V< V_CP− 0.5 V

V_CP= VCP/2 V

ꢀ

I_CPvs. Temperature

Rev. A | Page 4 of 76

AD9516-5

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PRESCALER (PART OF N DIVIDER)

Prescaler Input Frequency

P = 1 FD

See the VCXO/VCO Feedback Divider N—P, A, B section

300

600

900

200

MHz

P = 2 FD

P = 3 FD

P = 2 DM (2/3)

P = 4 DM (4/5)

P = 8 DM (8/9)

P = 16 DM (16/17)

P = 32 DM (32/33)

Prescaler Output Frequency

1000 MHz

2400 MHz

3000 MHz

300

MHz

A, B counter input frequency (prescaler input frequency

divided by P)

PLL DIVIDER DELAYS

Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 49

000

001

010

011

100

101

110

111

Off

ps

330

440

550

660

770

880

990

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge

Pump/Phase Frequency Detector

(In-Band Is Within the LBW of the PLL)

The PLL in-band phase noise floor is estimated by

measuring the in-band phase noise at the output of

the VCO and subtracting 20 log(N) (where N is the

value of the N divider)

At 500 kHz PFD Frequency

At 1 MHz PFD Frequency

At 10 MHz PFD Frequency

At 50 MHz PFD Frequency

PLL Figure of Merit (FOM)

−165

−162

−151

−143

−220

dBc/Hz

Reference slew rate > 0.25 V/ns; FOM + 10 log(f_PFD) is

an approximation of the PFD/CP in-band phase noise

(in the flat region) inside the PLL loop bandwidth; when

running closed-loop, the phase noise, as observed at

the VCO output, is increased by 20 log(N)

PLL DIGITAL LOCK DETECT WINDOW²

Signal available at the LD, STATUS, and REFMON pins

when selected by appropriate register settings

Required to Lock (Coincidence of Edges)

Low Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 6.0 ns)

Selected by Register 0x017[1:0] and Register 0x018[4]

Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b

Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b

Register 0x017[1:0] = 10b; Register 0x018[4] = 0b

3.5

7.5

3.5

ns

To Unlock After Lock (Hysteresis)²

Low Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 6.0 ns)

7

15

11

ns

Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b

Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b

Register 0x017[1:0] = 10b; Register 0x018[4] = 0b

1

REFIN

The REFIN and

self-bias points are offset slightly to avoid chatter on an open input condition.

²For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

Rev. A | Page 5 of 76

AD9516-5

CLOCK INPUTS

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Differential input

CLK

CLOCK INPUTS (CLK,

Input Frequency

)

0¹

2.4

1.6

GHz

High frequency distribution (VCO divider enabled)

Distribution only (VCO divider bypassed; this is the

frequency range supported by the channel divider)

Input Sensitivity, Differential

Input Level, Differential

150

mV p-p Measured at 2.4 GHz; jitter performance is

improved with slew rates > 1 V/ns

2

V p-p

Larger voltage swings may turn on the

protection diodes and may degrade jitter

performance

Input Common-Mode Voltage, V_CM

Input Common-Mode Range, V_CMR

Input Sensitivity, Single-Ended

Input Resistance

1.3

1.57

1.8

V

Self-biased; enables ac coupling

With 200 mV p-p signal applied; dc-coupled

150

4.7

2

mV p-p

kΩ

pF

CLK

ac-bypassed to RF ground

CLK ac-coupled;

Self-biased

3.9

5.7

Input Capacitance

¹Below about 1 MHz, the input should be dc-coupled. Care should be taken to match V_CM

.

CLOCK OUTPUTS

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL CLOCK OUTPUTS

Termination = 50 Ω to V_{S_LVPECL}− 2 V

OUT0, OUT1, OUT2, OUT3, OUT4,

OUT5

OUT

)

Differential (OUT,

Output Frequency, Maximum

Output High Voltage (V_OH)

Output Low Voltage (V_OL)

2400

MHz

V

Using direct to output; see Figure 20 for peak-to-

peak differential amplitude

Measured at dc using the default amplitude setting;

see Figure 20 for amplitude vs. frequency

Measured at dc using the default amplitude setting;

see Figure 20 for amplitude vs. frequency

V_{S_LVPECL}− 1.12 V_{S_LVPECL}− 0.98 V_{S_LVPECL}− 0.84

V_{S_LVPECL}− 2.03 V_{S_LVPECL}− 1.77 V_{S_LVPECL}− 1.49

V

Output Differential Voltage (V_OD)

550

790

980

mV

V_OH− V_OLfor each leg of a differential pair for

default amplitude setting with driver not toggling;

see Figure 20 for variation over frequency

LVDS CLOCK OUTPUTS

Differential termination 100 Ω at 3.5 mA

OUT6, OUT7, OUT8, OUT9

Output Frequency, Maximum

OUT

)

Differential (OUT,

800

247

MHz

mV

The AD9516 outputs can toggle at higher

frequencies, but the output amplitude may not

meet the V_ODspecification; see Figure 21

V_OH− V_OLmeasurement across a differential pair

at the default amplitude setting with output

driver not toggling; see Figure 21 for variation

over frequency

Differential Output Voltage (V_OD)

360

454

Delta V_OD

25

mV

V

This is the absolute value of the difference between

V_ODwhen the normal output is high vs. when the

complementary output is high

(V_OH+ V_OL)/2 across a differential pair at the

default amplitude setting with output driver not

toggling

This is the absolute value of the difference between

V_OSwhen the normal output is high vs. when the

complementary output is high

Output Offset Voltage (V_OS)

Delta V_OS

1.125

1.24

14

1.375

25

mV

mA

Short-Circuit Current (I_SA, I_SB)

CMOS CLOCK OUTPUTS

24

Output shorted to GND

OUT6A, OUT6B, OUT7A, OUT7B,

OUT8A, OUT8B, OUT9A, OUT9B

Single-ended; termination = 10 pF

Output Frequency

Output Voltage High (V_OH)

Output Voltage Low (V_OL)

250

MHz

V

See Figure 22

At 1 mA load

V_{S_LVPECL}− 0.1

0.1

Rev. A | Page 6 of 76

AD9516-5

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 1 GHz, Output = 1 GHz

Divider = 1

Distribution section only; does not include PLL input

slew rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

−109

−118

−130

−139

−144

−146

−147

−149

dBc/Hz

At 10 MHz Offset

At 100 MHz Offset

CLK = 1 GHz, Output = 200 MHz

Divider = 5

Input slew rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

−120

−126

−139

−150

−155

−157

dBc/Hz

CLK-TO-LVDS ADDITIVE PHASE NOISE

CLK = 1.6 GHz, Output = 800 MHz

Divider = 2

Distribution section only; does not include input slew

rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

−103

−110

−120

−127

−133

−138

−147

−149

dBc/Hz

At 10 MHz Offset

At 100 MHz Offset

CLK = 1.6 GHz, Output = 400 MHz

Divider = 4

Input slew rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

−114

−122

−132

−140

−146

−150

−155

dBc/Hz

CLK-TO-CMOS ADDITIVE PHASE NOISE

CLK = 1 GHz, Output = 250 MHz

Divider = 4

Distribution section only; does not include PLL input

slew rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

−110

−120

−127

−136

−144

−147

−154

dBc/Hz

Rev. A | Page 7 of 76

AD9516-5

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK = 1 GHz, Output = 50 MHz

Divider = 20

Input slew rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

−124

−134

−142

−151

−157

−160

−163

dBc/Hz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical setup using

an external 245.76 MHz VCXO (Toyocom TCO-2112);

reference = 15.36 MHz; R = 1

LVPECL = 245.76 MHz; PLL LBW = 125 Hz

LVPECL = 122.88 MHz; PLL LBW = 125 Hz

LVPECL = 61.44 MHz; PLL LBW = 125 Hz

54

77

109

79

114

163

124

176

259

fs rms

Integration bandwidth = 200 kHz to 5 MHz

Integration bandwidth = 200 kHz to 10 MHz

Integration bandwidth = 12 kHz to 20 MHz

Integration bandwidth = 200 kHz to 5 MHz

Integration bandwidth = 200 kHz to 10 MHz

Integration bandwidth = 12 kHz to 20 MHz

Integration bandwidth = 200 kHz to 5 MHz

Integration bandwidth = 200 kHz to 10 MHz

Integration bandwidth = 12 kHz to 20 MHz

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL;

uses rising edge of clock signal

CLK = 622.08 MHz; LVPECL = 622.08 MHz;

Divider = 1

CLK = 622.08 MHz; LVPECL = 155.52 MHz;

Divider = 4

CLK = 1.6 GHz; LVPECL = 100 MHz;

Divider = 16

CLK = 500 MHz; LVPECL = 100 MHz;

Divider = 5

40

fs rms

Bandwidth = 12 kHz to 20 MHz

80

Bandwidth = 12 kHz to 20 MHz

215

245

Calculated from SNR of ADC method; DCC not used

for even divides

Calculated from SNR of ADC method; DCC on

LVDS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL;

uses rising edge of clock signal

CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2

(VCO Divider Not Used)

85

fs rms

Bandwidth = 12 kHz to 20 MHz

CLK = 1 GHz; LVDS = 200 MHz; Divider = 5

CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16

113

280

fs rms

Bandwidth = 12 kHz to 20 MHz

Calculated from SNR of ADC method; DCC not used

for even divides

CMOS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL; uses

rising edge of clock signal

CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16

365

fs rms

Calculated from SNR of ADC method; DCC not used

for even divides

Rev. A | Page 8 of 76

AD9516-5

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

Table 8.

Parameter

Min

Typ

Max Unit

Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL;

uses rising edge of clock signal

CLK = 2.4 GHz; VCO Div = 2; LVPECL = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

210

fs rms

Calculated from SNR of ADC method

LVDS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL;

uses rising edge of clock signal

CLK = 2.4 GHz; VCO Div = 2; LVDS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

285

350

fs rms

Calculated from SNR of ADC method

CMOS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL;

uses rising edge of clock signal

Calculated from SNR of ADC method

CLK = 2.4 GHz; VCO Div = 2; CMOS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

DELAY BLOCK ADDITIVE TIME JITTER

Table 9.

Parameter

DELAY BLOCK ADDITIVE TIME JITTER¹

Min

Typ

Max Unit

Test Conditions/Comments

Incremental additive jitter

100 MHz Output

Delay (1600 μA, 0x1C) Fine Adjust 000000b

Delay (1600 μA, 0x1C) Fine Adjust 101111b

Delay (800 μA, 0x1C) Fine Adjust 000000b

Delay (800 μA, 0x1C) Fine Adjust 101111b

Delay (800 μA, 0x4C) Fine Adjust 000000b

Delay (800 μA, 0x4C) Fine Adjust 101111b

Delay (400 μA, 0x4C) Fine Adjust 000000b

Delay (400 μA, 0x4C) Fine Adjust 101111b

Delay (200 μA, 0x1C) Fine Adjust 000000b

Delay (200 μA, 0x1C) Fine Adjust 101111b

Delay (200 μA, 0x4C) Fine Adjust 000000b

Delay (200 μA, 0x4C) Fine Adjust 101111b

0.54

0.60

0.65

0.85

0.79

1.2

2.0

1.3

2.5

ps rms

1.9

3.8

¹This value is incremental; that is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

Rev. A | Page 9 of 76

AD9516-5

SERIAL CONTROL PORT

Table 10.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CS (INPUT)

CS has an internal 30 kΩ pull-up resistor

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SCLK (INPUT)

2.0

V

μA

pF

0.8

3

110

2

SCLK has an internal 30 kΩ pull-down resistor

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO (WHEN INPUT)

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

Output Logic 0 Voltage

TIMING

2.0

2.7

V

μA

pF

0.8

1

110

2

V

nA

pF

0.8

10

20

2

V

0.4

25

Clock Rate (SCLK, 1/t_SCLK

Pulse Width High, t_HIGH

Pulse Width Low, t_LOW

SDIO to SCLK Setup, t_DS

SCLK to SDIO Hold, t_DH

)

MHz

ns

16

2

1.1

SCLK to Valid SDIO and SDO, t_DV

CS to SCLK Setup and Hold, t_S, t_H

CS Minimum Pulse Width High, t_PWH

8

ns

2

3

ns

PD, RESET, AND SYNC PINS

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT CHARACTERISTICS

Logic 1 Voltage

Logic 0 Voltage

Logic 1 Current

Logic 0 Current

Capacitance

Each of these pins has an internal 30 kΩ pull-up resistor

2.0

V

μA

pF

0.8

1

110

2

RESET TIMING

Pulse Width Low

SYNC TIMING

50

ns

Pulse Width Low

1.5

High speed

clock cycles

High speed clock is CLK input signal

Rev. A | Page 10 of 76

AD9516-5

LD, STATUS, AND REFMON PINS

Table 12.

Parameter

Min Typ Max Unit Test Conditions/Comments

OUTPUT CHARACTERISTICS

When selected as a digital output (CMOS); there are other

modes in which these pins are not CMOS digital outputs; see

Table 49: Register 0x017, Register 0x01A, and Register 0x01B

Output Voltage High, V_OH

Output Voltage Low, V_OL

MAXIMUM TOGGLE RATE

2.7

V

0.4

100

3

MHz Applies when mux is set to any divider or counter output or

PFD up/down pulse; also applies in analog lock detect mode;

usually debug mode only; beware that spurs may couple to

output when any of these pins are toggling

ANALOG LOCK DETECT

Capacitance

pF

On-chip capacitance; used to calculate RC time constant for

analog lock detect readback; use a pull-up resistor

REF1, REF2, AND CLK FREQUENCY STATUS

MONITOR

Normal Range

1.02

8

MHz Frequency above which the monitor always indicates the

presence of the reference

Extended Range

kHz

Frequency above which the monitor always indicates the

presence of the reference

LD PIN COMPARATOR

Trip Point

1.6

V

Hysteresis

260

mV

POWER DISSIPATION

Table 13.

Parameter

Min Typ Max Unit Test Conditions/Comments

The values in this table include all power supplies, unless

POWER DISSIPATION, CHIP

otherwise noted; the power deltas for individual drivers are

at dc; see Figure 7, Figure 8, and Figure 9 for power dissipation

vs. output frequency

Power-On Default

1.0

1.5

1.2

2.1

185

W

No clock; no programming; default register values; does not

include power dissipated in external resistors; this configuration

has the following blocks already powered up: VCO divider,

six channel dividers, three LVPECL drivers, and two LVDS drivers

f_CLK= 2.25 GHz; VCO divider = 2; all channel dividers on; six

LVPECL outputs at 562.5 MHz; eight CMOS outputs (10 pF load)

at 225 MHz; all four fine delay blocks on, maximum current;

does not include power dissipated in external resistors

f_CLK= 2.25 GHz; VCO divider = 2; all channel dividers on; six

LVPECL outputs at 562.5 MHz; four LVDS outputs at 225 MHz;

all four fine delay blocks on: maximum current; does not include

power dissipated in external resistors

PD pin pulled low; does not include power dissipated in

terminations

Full Operation; CMOS Outputs at 225 MHz

Full Operation; LVDS Outputs at 225 MHz

PD Power-Down

75

31

mW

PD Power-Down, Maximum Sleep

PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b;

SYNC power-down, Register 0x230[2] = 1b; REF for distribution

power-down, Register 0x230[1] = 1b

V_CPSupply

4

4.8

mW

PLL operating; typical closed-loop configuration (this

number is included in all other power measurements)

AD9516 core only, all drivers off, PLL off, VCO divider off, and

delay blocks off; the power consumption of the configuration

of the user can be derived from this number and the power

deltas that follow

AD9516 Core

220

Rev. A | Page 11 of 76

AD9516-5

Parameter

Min Typ Max Unit Test Conditions/Comments

Power delta when a function is enabled/disabled

VCO divider bypassed

POWER DELTAS, INDIVIDUAL FUNCTIONS

VCO Divider

REFIN (Differential)

30

20

4

mW

All references off to differential reference enabled

All references off to REF1 or REF2 enabled; differential

reference not enabled

REF1, REF2 (Single-Ended)

PLL

75

30

120

mW

PLL off to PLL on, normal operation; no reference enabled

Divider bypassed to divide-by-2 to divide-by-32

No LVPECL output on to one LVPECL output on (that is, enabling

OUT0 with OUT1 off; Divider 0 enabled), independent of

frequency

Channel Divider

LVPECL Channel (Divider Plus Output Driver)

LVPECL Driver

90

mW

Second LVPECL output turned on, same channel (that is,

enabling OUT0 with OUT1 already on)

No LVDS output on to one LVDS output on (that is, enabling

OUT8 with OUT9 off with Divider 4.1 enabled and Divider 4.2

bypassed); see Figure 8 for dependence on output frequency

LVDS Channel (Divider Plus Output Driver)

140

LVDS Driver

50

mW

Second LVDS output turned on, same channel (that is, enabling

OUT8 with OUT9 already on)

CMOS Channel (Divider Plus Output Driver)

100

Static; no CMOS output on to one CMOS output on (that is,

enabling OUT8A starting with OUT8 and OUT9 off); see Figure 9

for variation over output frequency

CMOS Driver (Second in Pair)

CMOS Driver (First in Second Pair)

Fine Delay Block

0

mW

Static; second CMOS output, same pair, turned on (that is,

enabling OUT8A with OUT8B already on)

Static; first output, second pair, turned on (that is, enabling

OUT9A with OUT9B off and OUT8A and OUT8B already on)

Delay block off to delay block enabled; maximum current

setting

30

50

Rev. A | Page 12 of 76

AD9516-5

TIMING CHARACTERISTICS

Table 14.

Parameter

LVPECL

Min

Typ

Max

Unit

Test Conditions/Comments

Termination = 50 Ω to V_{S_LVPECL}− 2 V; default amplitude setting

(810 mV)

Output Rise Time, t_RP

Output Fall Time, t_FP

70

180

ps

20ꢀ to 80ꢀ, measured differentially

80ꢀ to 20ꢀ, measured differentially

PROPAGATION DELAY, t_PECL, CLK-TO-LVPECL OUTPUT

High Frequency Clock Distribution Configuration

Clock Distribution Configuration

Variation with Temperature

OUTPUT SKEW, LVPECL OUTPUTS¹

LVPECL Outputs That Share the Same Divider

LVPECL Outputs on Different Dividers

All LVPECL Outputs Across Multiple Parts

LVDS

835

773

995

933

0.8

1180 ps

1090 ps

See Figure 34

See Figure 33

ps/°C

5

13

15

ps

40

220

ps

Termination = 100 Ω differential; 3.5 mA setting

20ꢀ to 80ꢀ, measured differentially²

Delay off on all outputs

Output Rise Time, t_RL

Output Fall Time, t_FL

170

160

350

ps

PROPAGATION DELAY, t_LVDS, CLK-TO-LVDS OUTPUT

OUT6, OUT7, OUT8, OUT9

For All Divide Values

1.4

1.8

2.1

ns

Variation with Temperature

OUTPUT SKEW, LVDS OUTPUTS¹

LVDS Outputs That Share the Same Divider

LVDS Outputs on Different Dividers

All LVDS Outputs Across Multiple Parts

CMOS

1.25

ps/°C

Delay off on all outputs

6

25

62

150

430

ps

Termination = open

20ꢀ to 80ꢀ; C_LOAD= 10 pF

80ꢀ to 20ꢀ; C_LOAD= 10 pF

Fine delay off

Output Rise Time, t_RC

Output Fall Time, t_FC

495

475

1000 ps

985

ps

PROPAGATION DELAY, t_CMOS, CLK-TO-CMOS OUTPUT

For All Divide Values

1.6

2.1

2.6

ns

ps/°C

Variation with Temperature

OUTPUT SKEW, CMOS OUTPUTS¹

CMOS Outputs That Share the Same Divider

All CMOS Outputs on Different Dividers

All CMOS Outputs Across Multiple Parts

DELAY ADJUST³

Shortest Delay Range⁴

Zero Scale

Full Scale

Longest Delay Range⁴

Fine delay off

4

28

66

180

675

ps

LVDS and CMOS

Register 0x0A1 (0x0A4, 0x0A7, 0x0AA), Bits[5:0] = 101111b

Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b

Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b

Register 0x0A1 (0x0A4, 0x0A7, 0x0AA) Bits[5:0] = 000000b

Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b

Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 001100b

Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b

50

540

315

880

680

ps

1180 ps

Zero Scale

Quarter Scale

Full Scale

200

1.72

5.7

570

2.31

8.0

950

2.89

10.1

ps

ns

Delay Variation with Temperature

Short Delay Range⁵

Zero Scale

Full Scale

Long Delay Range⁵

0.23

−0.02

ps/°C

Zero Scale

Full Scale

0.3

0.24

ps/°C

¹This is the difference between any two similar delay paths while operating at the same voltage and temperature.

²Corresponding CMOS drivers set to OUTxA for noninverting and OUTxB for inverting; x = 6, 7, 8, or 9.

³The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.

⁴Incremental delay; does not include propagation delay.

⁵All delays between zero scale and full scale can be estimated by linear interpolation.

Rev. A | Page 13 of 76

AD9516-5

Timing Diagrams

t_CLK

CLK

DIFFERENTIAL

80%

t_PECL

LVDS

t_LVDS

20%

t_CMOS

t_RL

t_FL

CLK

Figure 2. CLK/

to Clock Output Timing, Divider = 1

Figure 4. LVDS Timing, Differential

DIFFERENTIAL

80%

SINGLE-ENDED

80%

LVPECL

CMOS

10pF LOAD

20%

t_RP

t_FP

t_RC

t_FC

Figure 3. LVPECL Timing, Differential

Figure 5. CMOS Timing, Single-Ended, 10 pF Load

Rev. A | Page 14 of 76

AD9516-5

ABSOLUTE MAXIMUM RATINGS

Table 15.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

VS, VS_LVPECL to GND

VCP to GND

−0.3 V to +3.6 V

−0.3 V to +5.8 V

REFIN, REFIN to GND

REFIN to REFIN

−0.3 V to VS + 0.3 V

−3.3 V to +3.3 V

RSET to GND

−0.3 V to VS + 0.3 V

−1.2 V to +1.2 V

CPRSET to GND

CLK, CLK to GND

CLK to CLK

THERMAL RESISTANCE

Table 16.

Package Type¹

θ_JA

Unit

SCLK, SDIO, SDO, CS to GND

−0.3 V to VS + 0.3 V

64-Lead LFCSP (CP-64-4)

22

°C/W

OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,

OUT3, OUT3, OUT4, OUT4, OUT5, OUT5,

OUT6, OUT6, OUT7, OUT7, OUT8, OUT8,

OUT9, OUT9 to GND

¹Thermal impedance measurements were taken on a 4-layer board in still air

in accordance with EIA/JESD51-2.

ESD CAUTION

SYNC

−0.3 V to VS + 0.3 V

to GND

REFMON, STATUS, LD to GND

Temperature

Junction Temperature¹

Storage Temperature Range

Lead Temperature (10 sec)

150°C

−65°C to +150°C

300°C

¹See Table 16 for θ_JA

.

Rev. A | Page 15 of 76

AD9516-5

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LVPECL LVPECL

VS

REFMON

LD

VCP

CP

STATUS

REF_SEL

1

2

3

4

5

6

7

48 OUT6 (OUT6A)

47 OUT6 (OUT6B)

46 OUT7 (OUT7A)

45 OUT7 (OUT7B)

44 GND

43 OUT2

42 OUT2

41 VS_LVPECL

40 OUT3

39 OUT3

PIN 1

INDICATOR

AD9516-5

TOP VIEW

(Not to Scale)

SYNC

NC

NC 10

VS 11

8

9

38 VS

VS 12

37 GND

CLK 13

CLK 14

NC 15

36 OUT9 (OUT9B)

35 OUT9 (OUT9A)

34 OUT8 (OUT8B)

33 OUT8 (OUT8A)

SCLK 16

LVPECL LVPECL

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. EXPOSED DIE PAD MUST BE CONNECTED TO GND.

Figure 6. Pin Configuration

Table 17. Pin Function Descriptions

Input/

Output Pin Type

Pin No.

Mnemonic

Description

1, 11, 12, 30,

31, 32, 38,

49, 50, 51,

57, 60, 61

I

Power

VS

3.3 V Power Pins.

2

O

3.3 V CMOS

REFMON

LD

Reference Monitor (Output). This pin has multiple selectable outputs;

see Table 49, Register 0x01B.

Lock Detect (Output). This pin has multiple selectable outputs; see Table 49,

Register 0x01A.

3

4

5

I

O

Power

Loop filter

VCP

CP

Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.25 V.

Charge Pump (Output). This pin connects to an external loop filter. This pin can

be left unconnected if the PLL is not used.

6

7

8

O

I

3.3 V CMOS

STATUS

REF_SEL

SYNC

Status (Output). This pin has multiple selectable outputs; see Table 49,

Register 0x017.

Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ

pull-down resistor.

Manual Synchronizations and Manual Holdover. This pin initiates a manual

synchronization and is also used for manual holdover. Active low. This pin has

an internal 30 kΩ pull-up resistor.

I

9, 10, 15, 18,

19, 20

N/A

NC

No Connection. These pins can be left floating.

13

I

Differential

clock input

Differential

clock input

CLK

Along with CLK, this is the differential input for the clock distribution section.

14

Along with CLK, this is the differential input for the clock distribution section.

If a single-ended input is connected to the CLK pin, connect a 0.1 μF bypass

capacitor from CLK to ground.

Rev. A | Page 16 of 76

AD9516-5

Input/

Output Pin Type

Pin No.

16

17

Mnemonic

SCLK

CS

Description

I

3.3 V CMOS

Serial Control Port Data Clock Signal.

Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up

resistor.

21

22

23

O

I/O

I

3.3 V CMOS

LVPECL

SDO

SDIO

RESET

PD

Serial Control Port Unidirectional Serial Data Output.

Serial Control Port Bidirectional Serial Data Input/Output.

Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor.

Chip Power-Down; Active Low. This pin has an internal 30 kΩ pull-up resistor.

LVPECL Output; One Side of a Differential LVPECL Output.

Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.

24

I

25

26

O

I

O

OUT4

VS_LVPECL

OUT5

LVPECL

27, 41, 54

Power

LVPECL

28

29

33

LVPECL Output; One Side of a Differential LVPECL Output.

LVDS or CMOS OUT8 (OUT8A) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

34

35

36

O

I

LVDS or CMOS OUT8 (OUT8B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

LVDS or CMOS OUT9 (OUT9A) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

LVDS or CMOS OUT9 (OUT9B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

37, 44, 59,

EPAD

GND

Ground Pins, Including External Paddle (EPAD). The external die paddle on the

bottom of the package must be connected to ground for proper operation.

39

40

42

43

45

O

LVPECL

OUT3

OUT2

LVPECL Output; One Side of a Differential LVPECL Output.

LVDS or CMOS OUT7 (OUT7B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

46

47

48

O

LVDS or CMOS OUT7 (OUT7A) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

LVDS or CMOS OUT6 (OUT6B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

LVDS or CMOS OUT6 (OUT6A) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended

CMOS Output.

52

53

55

56

58

O

LVPECL

Current set

resistor

OUT1

OUT0

RSET

LVPECL Output; One Side of a Differential LVPECL Output.

A resistor connected to this pin sets internal bias currents. Nominal value = 4.12 kΩ.

62

63

O

I

Current set

resistor

Reference

input

CPRSET

A resistor connected to this pin sets the CP current range. Nominal value = 5.1 kΩ.

This resistor can be omitted if the PLL is not used.

Along with REFIN, this pin is the differential input for the PLL reference.

Alternatively, this pin is a single-ended input for REF2. This pin can be left

unconnected when the PLL is not used.

REFIN (REF2)

64

I

Reference

input

REFIN (REF1)

Along with REFIN, this pin is the differential input for the PLL reference.

Alternatively, this pin is a single-ended input for REF1. This pin can be left

unconnected when the PLL is not used.

Rev. A | Page 17 of 76

AD9516-5

TYPICAL PERFORMANCE CHARACTERISTICS

300

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3 CHANNELS—6 LVPECL

280

260

240

220

PUMP DOWN

PUMP UP

200

180

160

140

120

100

3 CHANNELS—3 LVPECL

2 CHANNELS—2 LVPECL

1 CHANNEL—1 LVPECL

0

500

1000

1500

2000

2500

3000

0

0.5

1.0

1.5

2.0

2.5

3.0

FREQUENCY (MHz)

VOLTAGE ON CP PIN (V)

Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs

Figure 10. Charge Pump Characteristics at VCP = 3.3 V

180

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2 CHANNELS—4 LVDS

160

PUMP DOWN

PUMP UP

140

2 CHANNELS—2 LVDS

120

100

1 CHANNEL—1 LVDS

80

0

200

400

600

800

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

FREQUENCY (MHz)

VOLTAGE ON CP PIN (V)

Figure 8. Current vs. Frequency—LVDS Outputs

(Includes Clock Distribution Current Draw)

Figure 11. Charge Pump Characteristics at V_CP= 5.0 V

240

220

200

180

160

140

120

100

80

–140

–145

–150

–155

–160

–165

–170

2 CHANNELS—8 CMOS

2 CHANNELS—2 CMOS

1 CHANNEL—2 CMOS

1 CHANNEL—1 CMOS

0

50

100

150

200

250

0.1

1

10

100

FREQUENCY (MHz)

PFD FREQUENCY (MHz)

Figure 9. Current vs. Frequency—CMOS Outputs with 10 pF Load

Figure 12. PFD Phase Noise Referred to PFD Input vs. PFD Frequency

Rev. A | Page 18 of 76

AD9516-5

–210

–212

–214

–216

–218

–220

–222

–224

0.4

0.2

0

–0.2

–0.4

0

0.5

1.0

1.5

2.0

2.5

25

2

0

5

10

15

20

25

SLEW RATE (V/ns)

TIME (ns)

REFIN

Figure 16. LVDS Output (Differential) at 100 MHz

Figure 13. PLL Figure of Merit vs. Slew Rate at REFIN/

1.0

0.4

0.2

0.6

0.2

0

–0.2

–0.6

–1.0

–0.2

–0.4

0

5

10

15

20

0

1

2

TIME (ns)

Figure 14. LVPECL Output (Differential) at 100 MHz

Figure 17. LVDS Output (Differential) at 800 MHz

1.0

0.6

2.8

1.8

0.2

–0.2

–0.6

–1.0

0.8

–0.2

0

20

40

60

80

100

0

1

TIME (ns)

Figure 15. LVPECL Output (Differential) at 1600 MHz

Figure 18. CMOS Output at 25 MHz

Rev. A | Page 19 of 76

AD9516-5

700

600

500

2.8

1.8

0.8

–0.2

0

2

4

6

8

10

12

0

100

200

300

400

500

600

700

800

TIME (ns)

FREQUENCY (MHz)

Figure 19. CMOS Output at 250 MHz

Figure 21. LVDS Differential Swing vs. Frequency

(Using a Differential Probe Across the Output Pair)

1600

1400

1200

1000

C

= 2pF

L

3

2

1

0

C

= 10pF

L

C

= 20pF

L

800

0

100

200

300

400

500

600

1

2

3

OUTPUT FREQUENCY (MHz)

FREQUENCY (GHz)

Figure 22. CMOS Output Swing vs. Frequency and Capacitive Load

Figure 20. LVPECL Differential Swing vs. Frequency

(Using a Differential Probe Across the Output Pair)

Rev. A | Page 20 of 76

AD9516-5

–110

–120

–130

–140

–150

–160

–120

–125

–130

–135

–140

–145

–150

–155

–160

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 23. Phase Noise (Additive) LVPECL at 245.76 MHz, Divide-by-1

Figure 26. Phase Noise (Additive) LVDS at 200 MHz, Divide-by-1

–100

–110

–120

–130

–140

–150

–120

–130

–140

–150

–160

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 27. Phase Noise (Additive) LVDS at 800 MHz, Divide-by-2

Figure 24. Phase Noise (Additive) LVPECL at 200 MHz, Divide-by-5

–120

–100

–130

–140

–150

–160

–170

–110

–120

–130

–140

–150

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 28. Phase Noise (Additive) CMOS at 50 MHz, Divide-by-20

Figure 25. Phase Noise (Additive) LVPECL at 1600 MHz, Divide-by-1

Rev. A | Page 21 of 76

AD9516-5

–100

–110

–120

–130

–140

–150

–160

1000

100

10

OC-48 OBJECTIVE MASK

AD9516

f_OBJ

1

NOTE: 375UI MAX AT 10Hz OFFSET IS THE

MAXIMUM JITTER THAT CAN BE

GENERATED BY THE TEST EQUIPMENT.

FAILURE POINT IS GREATER THAN 375UI.

0.1

0.01

0.1

1

10

100

1000

10

100

1k

10k

100k

1M

10M

100M

JITTER FREQUENCY (kHz)

FREQUENCY (Hz)

Figure 31. GR-253 Jitter Tolerance Plot

Figure 29. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4

–120

–130

–140

–150

–160

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 30. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)

at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz

Rev. A | Page 22 of 76

AD9516-5

TERMINOLOGY

Time Jitter

Phase Jitter and Phase Noise

Phase noise is a frequency domain phenomenon. In the time

domain, the same effect is exhibited as time jitter. When

observing a sine wave, the time of successive zero crossings

varies. In a square wave, the time jitter is a displacement of the

edges from their ideal (regular) times of occurrence. In both

cases, the variations in timing from the ideal are the time jitter.

Because these variations are random in nature, the time jitter is

specified in units of seconds root mean square (rms) or 1 sigma

of the Gaussian distribution.

An ideal sine wave can be thought of as having a continuous

and even progression of phase with time from 0° to 360° for

each cycle. Actual signals, however, display a certain amount

of variation from ideal phase progression over time. This

phenomenon is called phase jitter. Although many causes can

contribute to phase jitter, one major cause is random noise,

which is characterized statistically as being Gaussian (normal)

in distribution.

This phase jitter leads to a spreading out of the energy of the

sine wave in the frequency domain, producing a continuous

power spectrum. This power spectrum is usually reported as

a series of values whose units are dBc/Hz at a given offset in

frequency from the sine wave (carrier). The value is a ratio

(expressed in decibels, dB) of the power contained within

a 1 Hz bandwidth with respect to the power at the carrier

frequency. For each measurement, the offset from the carrier

frequency is also given.

Time jitter that occurs on a sampling clock for a DAC or an

ADC decreases the signal-to-noise ratio (SNR) and dynamic

range of the converter. A sampling clock with the lowest possible

jitter provides the highest performance from a given converter.

Additive Phase Noise

Additive phase noise is the amount of phase noise that is

attributable to the device or subsystem being measured. The phase

noise of any external oscillators or clock sources is subtracted.

This makes it possible to predict the degree to which the device

impacts the total system phase noise when used in conjunction

with the various oscillators and clock sources, each of which

contributes its own phase noise to the total. In many cases, the

phase noise of one element dominates the system phase noise.

When there are multiple contributors to phase noise, the total is

the square root of the sum of squares of the individual contributors.

It is meaningful to integrate the total power contained within

some interval of offset frequencies (for example, 10 kHz to

10 MHz). This is called the integrated phase noise over that

frequency offset interval and can be readily related to the time

jitter due to the phase noise within that offset frequency interval.

Phase noise has a detrimental effect on the performance of

ADCs, DACs, and RF mixers. It lowers the achievable dynamic

range of the converters and mixers, although they are affected

in somewhat different ways.

Additive Time Jitter

Additive time jitter is the amount of time jitter that is attributable to

the device or subsystem being measured. The time jitter of any

external oscillators or clock sources is subtracted. This makes it

possible to predict the degree to which the device impacts the total

system time jitter when used in conjunction with the various

oscillators and clock sources, each of which contributes its own

time jitter to the total. In many cases, the time jitter of the external

oscillators and clock sources dominates the system time jitter.

Rev. A | Page 23 of 76

AD9516-5

DETAILED BLOCK DIAGRAM

REF_ SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

REFIN (REF2)

HOLD

VCO STATUS

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

PROGRAMMABLE

N DELAY

CP

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

OUT0

DIVIDE BY

1 TO 32

LVPECL

PD

SYNC

OUT1

DIGITAL

LOGIC

RESET

OUT2

DIVIDE BY

1 TO 32

LVPECL

OUT3

SCLK

SDIO

SDO

CS

SERIAL

CONTROL

PORT

OUT4

DIVIDE BY

1 TO 32

OUT5

OUT6 (OUT6A)

OUT6 (OUT6B)

∆t

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT7 (OUT7A)

OUT7 (OUT7B)

∆t

OUT8 (OUT8A)

OUT8 (OUT8B)

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT9 (OUT9A)

OUT9 (OUT9B)

AD9516-5

∆t

Figure 32. Detailed Block Diagram

Rev. A | Page 24 of 76

AD9516-5

THEORY OF OPERATION

REF_SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

LOCK

DETECT

STATUS

REF2

R

PROGRAMMABLE

R DELAY

DIVIDER

STATUS

REFIN (REF1)

HOLD

VCO STATUS

REFIN (REF2)

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

PROGRAMMABLE

N DELAY

CP

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

OUT0

DIVIDE BY

1 TO 32

LVPECL

PD

OUT1

DIGITAL

LOGIC

SYNC

RESET

OUT2

DIVIDE BY

1 TO 32

LVPECL

OUT3

SCLK

SERIAL

SDIO

CONTROL

SDO

CS

PORT

OUT4

DIVIDE BY

1 TO 32

OUT5

OUT6 (OUT6A)

OUT6 (OUT6B)

∆t

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT7 (OUT7A)

OUT7 (OUT7B)

∆t

OUT8 (OUT8A)

OUT8 (OUT8B)

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

AD9516-5

OUT9 (OUT9A)

OUT9 (OUT9B)

∆t

Figure 33. Clock Distribution or External VCO < 1600 MHz (Mode 1)

For clock distribution applications where the external clock is less

than 1600 MHz, use the register settings shown in Table 18.

OPERATIONAL CONFIGURATIONS

The AD9516 can be configured in several ways. These

configurations must be set up by loading the control registers

(see Table 47 and Table 48 through Table 57). Each section or

function must be individually programmed by setting the

appropriate bits in the corresponding control register or registers.

Table 18. Settings for Clock Distribution < 1600 MHz

Register

Description

0x010[1:0] = 01b

0x1E1[0] = 1b

PLL asynchronous power-down (PLL off)

Bypass the VCO divider as source for

distribution section

Mode 1—Clock Distribution or External VCO < 1600 MHz

Mode 1 bypasses the VCO divider. Mode 1 can be used only

with an external clock source of <1600 MHz, due to the maximum

input frequency allowed at the channel dividers.

When using the internal PLL with an external VCO of <1600 MHz,

the PLL must be turned on.

Rev. A | Page 25 of 76

AD9516-5

Table 19. Settings for Using an Internal PLL with an External

VCO < 1600 MHz

The register settings shown in Table 21 are the default values

of these registers at power-up or after a reset operation. If the

contents of the registers are altered by prior programming after

power-up or reset, these registers can also be set intentionally to

these values.

Register

Description

0x1E1[0] = 1b

Bypass the VCO divider as source for

distribution section

0x010[1:0] = 00b PLL normal operation (PLL on) along with other

appropriate PLL settings in Register 0x010 to

Register 0x01E

Table 21. Default Settings of Some PLL Registers

Register

Description

0x010[1:0] = 01b

0x1E0[2:0] = 010b Set VCO divider = 4.

0x1E1[0] = 0b Use the VCO divider.

PLL asynchronous power-down (PLL off).

An external VCO/VCXO requires an external loop filter that

must be connected between CP and the tuning pin of the VCO/

VCXO. This loop filter determines the loop bandwidth and

stability of the PLL. Ensure that the correct PFD polarity is

selected for the VCO/VCXO that is being used.

When using the internal PLL with an external VCO, the PLL

must be turned on.

Table 22. Settings When Using an External VCO

Table 20. Setting the PFD Polarity

Register

Description

Register

Description

0x010[1:0] = 00b

0x010 to 0x01D

PLL normal operation (PLL on).

0x010[7] = 0b

PFD polarity positive (higher control voltage

produces higher frequency)

PFD polarity negative (higher control voltage

produces lower frequency)

PLL settings. Select and enable a reference

input. Set R, N (P, A, B), PFD polarity, and I_CP

according to the intended loop configuration.

0x010[7] = 1b

0x1E1[1] = 0b

CLK selected as the source.

After the appropriate register values are programmed,

Register 0x232 must be set to 0x01 for the values to take effect.

An external VCO requires an external loop filter that must be

connected between CP and the tuning pin of the VCO. This loop

filter determines the loop bandwidth and stability of the PLL.

Ensure that the correct PFD polarity is selected for the VCO

that is being used.

Mode 2 (High Frequency Clock Distribution)—CLK or

External VCO > 1600 MHz

The AD9516 power-up default configuration has the PLL

powered off and the routing of the input set so that the CLK/

CLK

input is connected to the distribution section through the

Table 23. Setting the PFD Polarity

VCO divider (divide-by-2/divide-by-3/divide-by-4/divide-by-5/

divide-by-6). This is a distribution-only mode that allows for an

external input of up to 2400 MHz (see Table 4). For divide ratios

other than 1, the maximum frequency that can be applied to the

channel dividers is 1600 MHz. Therefore, the VCO divider must

be used to divide down input frequencies that are greater than

1600 MHz before the channel dividers can be used for further

division. This input routing can also be used for lower input

frequencies, but the minimum divide is 2 before the channel

dividers.

Register

Description

0x010[7] = 0b

PFD polarity positive (higher control

voltage produces higher frequency).

PFD polarity negative (higher control

voltage produces lower frequency).

0x010[7] = 1b

After the appropriate register values are programmed,

Register 0x232 must be set to 0x01 for the values to take effect.

When the PLL is enabled, this routing also allows the use of

the PLL with an external VCO or VCXO with a frequency of

<2400 MHz. In this configuration, the external VCO/VCXO

feeds directly into the prescaler.

Rev. A | Page 26 of 76

AD9516-5

REF_SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

REFIN (REF2)

HOLD

VCO STATUS

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

PROGRAMMABLE

N DELAY

CP

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

OUT0

DIVIDE BY

1 TO 32

LVPECL

PD

SYNC

OUT1

DIGITAL

LOGIC

RESET

OUT2

DIVIDE BY

1 TO 32

LVPECL

OUT3

SCLK

SDIO

SDO

CS

SERIAL

CONTROL

PORT

OUT4

DIVIDE BY

1 TO 32

OUT5

OUT6 (OUT6A)

OUT6 (OUT6B)

∆t

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT7 (OUT7A)

OUT7 (OUT7B)

∆t

OUT8 (OUT8A)

OUT8 (OUT8B)

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

AD9516-5

OUT9 (OUT9A)

OUT9 (OUT9B)

∆t

Figure 34. High Frequency Clock Distribution—CLK or External VCO > 1600 MHz (Mode 2)

Rev. A | Page 27 of 76

AD9516-5

Phase-Locked Loop (PLL)

REF_SEL

VS

GND

RSET

REFMON

CPRSET VCP

DIST

REF

REFERENCE

SWITCHOVER

LD

LOCK

DETECT

REF1

REF2

STATUS

PROGRAMMABLE

R DELAY

HOLD

R DIVIDER

PLL

REF

REFIN (REF1)

REFIN (REF2)

PHASE

CHARGE PUMP

FREQUENCY

DETECTOR

CP

N DIVIDER

P, P + 1

A/B

PROGRAMMABLE

N DELAY

PRESCALER

COUNTERS

VCO STATUS

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

0

1

CLK

1

0

Figure 35. PLL Functional Blocks

The AD9516 includes on-chip PLL blocks that can be used with

an external VCO or VCXO to create a complete phase-locked

loop. The PLL requires an external loop filter, which usually

consists of a small number of capacitors and resistors. The

configuration and components of the loop filter help to establish

the loop bandwidth and stability of the PLL.

Phase Frequency Detector (PFD)

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. The PFD includes a programmable

delay element that controls the width of the antibacklash pulse.

This pulse ensures that there is no dead zone in the PFD transfer

function and minimizes phase noise and reference spurs. The

antibacklash pulse width is set by Register 0x017[1:0].

The AD9516 PLL is useful for generating clock frequencies from a

supplied reference frequency. This includes conversion of reference

frequencies to much higher frequencies for subsequent division

and distribution. In addition, the PLL can be exploited to clean up

jitter and phase noise on a noisy reference. The exact choices of

PLL parameters and loop dynamics are very application specific.

The flexibility and depth of the PLL allow the part to be tailored

to function in many different applications and signal environments.

An important limit to keep in mind is the maximum frequency

allowed into the PFD, which, in turn, determines the correct anti-

backlash pulse setting. The antibacklash pulse setting is specified

in the phase/frequency detector (PFD) parameter of Table 2.

Charge Pump (CP)

The charge pump is controlled by the PFD. The PFD monitors the

phase and frequency relationship between its two inputs, and tells

the CP to pump up or pump down to charge or discharge the

integrating node (part of the loop filter). The integrated and

filtered CP current is transformed into a voltage that drives the

tuning node of the external VCO to move the VCO frequency

up or down. The CP can be set (via Register 0x010[6:4]) for high

impedance (allows holdover operation), for normal operation

(attempts to lock the PLL loop), for pump-up, or for pump-down

(test modes). The CP current is programmable in eight steps from

(nominally) 600 μA to 4.8 mA.

Configuration of the PLL

Configuration of the PLL is accomplished by programming

the various settings for the R divider, N divider, PFD polarity,

and charge pump current. The combination of these settings

determines the PLL loop bandwidth. These are managed through

programmable register settings (see Table 47 and Table 49) and

by the design of the external loop filter. Successful PLL operation

and satisfactory PLL loop performance are highly dependent upon

proper configuration of the PLL settings.

The design of the external loop filter is crucial to the proper

operation of the PLL. A thorough knowledge of PLL theory and

design is helpful.

The exact value of the CP current LSB is set by the CPRSET

resistor, which is nominally 5.1 kΩ. If the value of the resistor

connected to the CP_RSET pin is doubled, the resulting charge

pump current range becomes 300 μA to 2.4 mA.

ADIsimCLK™ (V1.2 or later) is a free program that can help

with the design and exploration of the capabilities and features

of the AD9516, including the design of the PLL loop filter. It is

available at www.analog.com/clocks.

Rev. A | Page 28 of 76

AD9516-5

PLL External Loop Filter

In differential mode, the reference input pins are internally self-

biased so that they can be ac-coupled via capacitors. It is possible to

dc couple to these inputs. If the differential REFIN is driven by a

An example of an external loop filter for a PLL is shown in

Figure 36. A loop filter must be calculated for each desired PLL

configuration. The values of the components depend on the VCO

frequency, the K_VCO, the PFD frequency, the charge pump current,

the desired loop bandwidth, and the desired phase margin. The

loop filter affects the phase noise, loop settling time, and loop

stability. A basic knowledge of PLL theory is helpful for under-

standing loop filter design. ADIsimCLK can help with calculation

of a loop filter according to the application requirements.

REFIN

single-ended signal, the unused side (

) should be decoupled

via a suitable capacitor to a quiet ground. Figure 37 shows the

equivalent circuit of REFIN.

V

S

85kΩ

REF1

AD9516-5

EXTERNAL

VCO/VCXO

CLK/CLK

CP

V

S

R2

R1

10kΩ 12kΩ

150Ω

REFIN

CHARGE

PUMP

C1

C2

C3

150Ω

10kΩ 10kΩ

Figure 36. Example of External Loop Filter for PLL

V

S

PLL Reference Inputs

REF2

The AD9516 features a flexible PLL reference input circuit that

allows a fully differential input or two separate single-ended

inputs. The input frequency range for the reference inputs is

specified in Table 2. Both the differential and the single-ended

inputs are self-biased, allowing for easy ac coupling of input signals.

85kΩ

Figure 37. REFIN Equivalent Circuit

The differential input and the single-ended inputs share two

REFIN

pins, REFIN (REF1) and

(REF2). The desired reference

Reference Switchover

input type is selected and controlled by Register 0x01C (see

Table 47 and Table 49).

The AD9516 supports dual single-ended CMOS inputs, as well as

a single differential reference input. In dual single-ended reference

mode, automatic and manual PLL reference clock switching

When the differential reference input is selected, the self-bias

level of the two sides is offset slightly (see Table 2) to prevent

chattering of the input buffer when the reference is slow or missing.

The specification for this voltage level is found in Table 2. The input

hysteresis increases the voltage swing required of the driver to

overcome the offset. The differential reference input can be driven

by either ac-coupled LVDS or ac-coupled LVPECL signals.

REFIN

between REF1 (Pin REFIN) and REF2 (Pin

) is supported.

This feature supports networking and other applications that

require smooth switching of redundant references. When used in

conjunction with the automatic holdover function, the AD9516

can achieve a worst-case reference input switchover with an

output frequency disturbance as low as 10 ppm.

When using reference switchover, the single-ended reference inputs

should be dc-coupled CMOS levels that are never allowed to go to

high impedance. If the inputs are allowed to go to high impedance,

noise may cause the buffer to chatter, causing false detection of

the presence of a reference. Reference switchover can be performed

manually or automatically. Manual switchover is performed

either through Register 0x01C or by using the REF_SEL pin.

The single-ended inputs can be driven by either a dc-coupled

CMOS level signal or an ac-coupled sine wave or square wave.

Each single-ended input can be independently powered down

when not needed to increase isolation and reduce power. Either

a differential or a single-ended reference must be specifically

enabled. All PLL reference inputs are off by default.

The differential reference input is powered down whenever the

PLL is powered down, or when the differential reference input

is not selected. The single-ended buffers power down when the

PLL is powered down and when their individual power-down

registers are set. When the differential mode is selected, the

single-ended inputs are powered down.

Manual switchover requires the presence of a clock on the reference

input that is being switched to, or that the deglitching feature be

disabled (Register 0x01C[7]). The reference switching logic fails

if this condition is not met, and the PLL does not reacquire.

Rev. A | Page 29 of 76

AD9516-5

Automatic revertive switchover relies on the REFMON pin to

indicate when REF1 disappears. By programming Register 0x01B =

0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed

to be high when REF1 is invalid, which commands the switch to

REF2. When REF1 is valid again, the REFMON pin goes low, and

the part again locks to REF1. The STATUS pin can also be used

for this function, and REF2 can be used as the preferred reference.

VCXO/VCO Feedback Divider N—P, A, B

The N divider is a combination of a prescaler (P) and two

counters, A and B. The total divider value is

N = (P × B) + A

where P can be 2, 4, 8, 16, or 32.

Prescaler

A switchover deglitch feature ensures that the PLL does not receive

rising edges that are far out of alignment with the newly selected

reference. Automatic nonrevertive switching is not supported.

The prescaler of the AD9516 allows for two modes of operation:

a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM)

mode where the prescaler divides by P and (P + 1) {2 and 3, 4

and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes

of operation are given in Table 49, Register 0x016[2:0]. Not all

modes are available at all frequencies (see Table 2).

Reference Divider R

The reference inputs are routed to the reference divider, R.

R (a 14-bit counter) can be set to any value from 0 to 16,383 by

writing to Register 0x011 and Register 0x012. (Both R = 0 and

R = 1 give divide-by-1.) The output of the R divider goes to one

of the PFD inputs to be compared with the VCO frequency divided

by the N divider. The frequency applied to the PFD must not

exceed the maximum allowable frequency, which depends on

the antibacklash pulse setting (see Table 2).

When operating the AD9516 in dual modulus mode, P/(P + 1),

the equation used to relate the input reference frequency to the

VCO output frequency is

f

_VCO= (f_REF/R) × (P × B + A) = f_REF× N/R

However, when operating the prescaler in FD Mode 1,

FD Mode 2, or FD Mode 3, the A counter is not used (A = 0)

and the equation simplifies to

The R counter has its own reset. The R counter can be reset via

the shared reset bit of the R, A, and B counters. It can also be

f

_VCO= (f_REF/R) × (P × B) = f_REF× N/R

SYNC

reset by a

operation.

When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,

in which case, the previous equation also applies.

By using combinations of DM and FD modes, the AD9516

can achieve values of N all the way down to N = 1 and up to N =

26,2175. Table 24 shows how a 10 MHz reference input can be

locked to any integer multiple of N.

Table 24. Using a 10 MHz Reference to Generate Different VCO Frequencies

f_REF(MHz)

R

1

P

1

2

1

2

A

B

1

3

4

5

3

N

1

2

3

4

5

6

7

f_VCO(MHz) Mode Conditions/Comments

10

X¹

0

10

20

30

40

50

60

70

FD

DM

P = 1, B = 1 (A and B counters are bypassed).

P = 2, B = 1 (A and B counters are bypassed).

A counter is bypassed.

1

Maximum frequency into prescaler in P = 2/3 mode is 200 MHz.

If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz

to 300 MHz, use P = 1, and N = 7 or 11, respectively.

10

1

10

1

2

8

16

32

8

2

1

6

7

6

0

14

3

4

8

9

150

151

1510 1510

200

270

80

90

1500

1510

DM

18

9

47

25

16

2000

2700

1

16

P = 8 is not allowed (2700 ÷ 8 > 300 MHz).

P = 32 is not allowed (A > B not allowed).

P = 32, A = 22, B = 84.

10

32

22

84

2710 2710

DM

P = 16 is also permitted.

¹X = don’t care.

Rev. A | Page 30 of 76

AD9516-5

Note that the same value of N can be derived in different ways,

as illustrated by the case of N = 12. The user can choose a fixed

divide mode of P = 2 with B = 6; use the dual modulus mode of

2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with

A = 0, B = 3.

lock detect counter (Register 0x018[6:5]). A lock is not indicated

until there is a programmable number of consecutive PFD cycles

with a time difference that is less than the lock detect threshold.

The lock detect circuit continues to indicate a lock until a time

difference greater than the unlock threshold occurs on a single

subsequent cycle. For the lock detect to work properly, the period

of the PFD frequency must be greater than the unlock threshold.

The number of consecutive PFD cycles required for lock is

programmable (Register 0x018[6:5]).

A and B Counters

The B counter must be ≥3 or bypassed, and, unlike the R counter,

A = 0 is actually zero. When the prescaler is in dual modulus mode,

the A counter must be less than the B counter.

Analog Lock Detect (ALD)

The maximum input frequency to the A or B counter is reflected

in the maximum prescaler output frequency (~300 MHz) that

is specified in Table 2. This is the prescaler input frequency

(external VCO or CLK) divided by P. For example, a dual

modulus mode of P = 8/9 mode is not allowed if the external

VCO frequency is greater than 2400 MHz because the frequency

going to the A or B counter is too high.

The AD9516 provides an ALD function that can be selected for

use at the LD pin. There are two versions of ALD, as follows:

•

N-channel open-drain lock detect. This signal requires

a pull-up resistor to the positive supply, VS. The output is

normally high with short, low going pulses. Lock is indicated

by the minimum duty cycle of the low going pulses.

P-channel open-drain lock detect. This signal requires

a pull-down resistor to GND. The output is normally low

with short, high going pulses. Lock is indicated by the

minimum duty cycle of the high going pulses.

•

When the B counter is bypassed (B = 1), the A counter should

be set to 0, and the overall resulting divide is equal to the prescaler

setting, P. The possible divide ratios in this mode are 1, 2, 3, 4, 8,

16, and 32. This mode is useful only when an external VCO/VCXO

is used because the frequency range of the internal VCO requires

an overall feedback divider that is greater than 32.

The analog lock detect function requires an R-C filter to

provide a logic level indicating lock/unlock.

VS = 3.3V

Although manual reset is not normally required, the A and B

counters have their own reset bit. Alternatively, the A and B

counters can be reset using the shared reset bit of the R, A, and

B counters. Note that these reset bits are not self-clearing.

AD9516-5

R2

V

OUT

R1

LD

ALD

C

SYNC

R, A, and B Counters—

Pin Reset

The R, A, and B counters can also be reset simultaneously via

SYNC

Figure 38. Example of Analog Lock Detect Filter, Using

N-Channel Open-Drain Driver

the

(see Table 49). The

R and N Divider Delays

pin. This function is controlled by Register 0x019[7:6]

SYNC

pin reset is disabled by default.

Current Source Digital Lock Detect (CSDLD)

During the PLL locking sequence, it is normal for the DLD

signal to toggle a number of times before remaining steady

when the PLL is completely locked and stable. There may be

applications where it is desirable to have DLD asserted only

after the PLL is solidly locked. This is made possible by using

the current source lock detect function. This function is set

when it is selected as the output from the LD pin control

(Register 0x01A[5:0]).

Both the R and N dividers feature a programmable delay cell.

These delays can be enabled to allow adjustment of the phase

relationship between the PLL reference clock and the VCO or

CLK. Each delay is controlled by three bits. The total delay

range is about 1 ns. See Register 0x019 in Table 49.

LOCK DETECT

Digital Lock Detect (DLD)

The current source lock detect provides a current of 110 μA

when DLD is true, and it shorts to ground when DLD is false.

If a capacitor is connected to the LD pin, it charges at a rate that

is determined by the current source during the DLD true time

but is discharged nearly instantly when DLD is false. By

monitoring the voltage at the LD pin (top of the capacitor), it is

possible to get a logic high level only after the DLD has been

true for a sufficiently long time. Any momentary DLD false

resets the charging. By selecting a properly sized capacitor, it is

possible to delay a lock detect indication until the PLL is locked

in a stable condition and the lock detect does not chatter.

By selecting the proper output through the mux on each pin, the

DLD function can be made available at the LD, STATUS, and

REFMON pins. The DLD circuit indicates a lock when the time

difference of the rising edges at the PFD inputs is less than a

specified value (the lock threshold). The loss of a lock is indicated

when the time difference exceeds a specified value (the unlock

threshold). Note that the unlock threshold is wider than the

lock threshold, which allows some phase error in excess of the

lock window to occur without chattering on the lock indicator.

The lock detect window timing depends on three settings: the

digital lock detect window bit (Register 0x018[4]), the antibacklash

pulse width setting (Register 0x017[1:0]), see Table 2), and the

Rev. A | Page 31 of 76

AD9516-5

The voltage on the capacitor can be sensed by an external

comparator connected to the LD pin. However, there is an

internal LD pin comparator that can be read at the REFMON

pin control (Register 0x01B[4:0]) or the STATUS pin control

(Register 0x017[7:2]) as an active high signal. It is also available

as an active low signal (REFMON, Register 0x01B[4:0] and

STATUS, Register 0x017[7:2]). The internal LD pin comparator

trip point and hysteresis are listed in Table 12.

Holdover

The AD9516 PLL has a holdover function. Holdover is

implemented by putting the charge pump into a high impedance

state. This is useful when the PLL reference clock is lost. Holdover

mode allows the VCO to maintain a relatively constant frequency

even though there is no reference clock. Without this function,

the charge pump is placed into a constant pump-up or pump-

down state, resulting in a large VCO frequency shift. Because

the charge pump is placed in a high impedance state, any leakage

that occurs at the charge pump output or the VCO tuning node

causes a drift of the VCO frequency. This can be mitigated by

using a loop filter that contains a large capacitive component

because this drift is limited by the current leakage induced slew

rate (I_LEAK/C) of the VCO control voltage. For most applications,

the frequency is sufficient for 3 sec to 5 sec.

AD9516-5

110µA

DLD

V

OUT

LD

C

LD PIN

COMPARATOR

REFMON

OR

STATUS

SYNC

Both a manual holdover mode, using the

pin, and an

automatic holdover mode are provided. To use either function,

the holdover function must be enabled (Register 0x01D[0] and

Register 0x01D[2]).

Figure 39. Current Source Lock Detect

CLK

External VCXO/VCO Clock Input (CLK/

)

Manual Holdover Mode

CLK is a differential input that can be used to drive the AD9516

clock distribution section. This input can receive up to 2.4 GHz.

The pins are internally self-biased, and the input signal should

be ac-coupled via capacitors.

A manual holdover mode can be enabled that allows the user

to place the charge pump into a high impedance state when the

SYNC

pin is asserted low. This operation is edge sensitive, not

level sensitive. The charge pump enters a high impedance state

immediately. To take the charge pump out of a high impedance

CLOCK INPUT

STAGE

VS

SYNC

state, take the

pin high. The charge pump then leaves the

CLK

high impedance state synchronously with the next PFD rising

edge from the reference clock. This prevents extraneous charge

CLK

2.5kΩ

5kΩ

2.5kΩ

SYNC

pump events from occurring during the time between

going high and the next PFD event. This also means that the

charge pump stays in a high impedance state as long as there is

no reference clock present.

5kΩ

Figure 40. CLK Equivalent Input Circuit

The B counter (in the N divider) is reset synchronously with the

charge pump leaving the high impedance state on the reference

path PFD event. This helps align the edges out of the R and N

dividers for faster settling of the PLL. Because the prescaler is

not reset, this feature works best when the B and R numbers are

close because this results in a smaller phase difference for the

loop to settle out.

CLK

The CLK/

input can be used either as a distribution only

input (with the PLL off), or as a feedback input for an external

VCO/VCXO using the PLL. The CLK/

for frequencies up to 2.4 GHz.

CLK

input can be used

When using this mode, set the channel dividers to ignore the

SYNC

pin (at least after an initial

event). If the dividers are

SYNC

not set to ignore the

pin, the distribution outputs turn off

SYNC

each time

is taken low to put the part into holdover.

Rev. A | Page 32 of 76

AD9516-5

Automatic/Internal Holdover Mode

PLL ENABLED

When enabled, this function automatically puts the charge pump

into a high impedance state when the loop loses lock. The

assumption is that the only reason that the loop loses lock is due

to the PLL losing the reference clock; therefore, the holdover

function puts the charge pump into a high impedance state to

maintain the VCO frequency as close as possible to the original

frequency before the reference clock disappears.

LOOP OUT OF LOCK. DIGITAL LOCK

NO

DETECT SIGNAL GOES LOW WHEN THE

LOOP LEAVES LOCK AS DETERMINED

BY THE PHASE DIFFERENCE AT THE

INPUT OF THE PFD.

DLD == LOW

YES

See Figure 41 for a flowchart of the internal/automatic holdover

function operation.

NO

ANALOG LOCK DETECT PIN INDICATES

LOCK WAS PREVIOUSLY ACHIEVED.

REGISTER 0x1D[3] = 1: USE LD PIN

VOLTAGE WITH HOLDOVER.

The holdover function senses the logic level of the LD pin as a

condition to enter holdover. The signal at LD can be from the

DLD, ALD, or current source LD (CSDLD) mode. It is possible

to disable the LD comparator (Register 0x01D[3]), which causes

the holdover function to always sense LD as high. If DLD is

used, it is possible for the DLD signal to chatter somewhat while

the PLL is reacquiring lock. The holdover function may retrigger,

thereby preventing the holdover mode from ever terminating.

Use of the current source lock detect mode is recommended to

avoid this situation (see the Current Source Digital Lock Detect

section).

WAS

LD PIN == HIGH

WHEN DLD WENT

LOW?

REGISTER 0x1D[3] = 0: IGNORE LD PIN

VOLTAGE,TREAT LD PIN AS ALWAYS HIGH.

YES

CHARGE PUMP IS MADE

HIGH IMPEDANCE.

PLL COUNTERS CONTINUE

OPERATING NORMALLY.

HIGH IMPEDANCE

CHARGE PUMP

YES

NO

CHARGE PUMP REMAINS HIGH

IMPEDANCE UNTIL THE REFERENCE

HAS RETURNED.

REFERENCE

EDGE AT PFD?

When in holdover mode, the charge pump stays in a high

impedance state as long as there is no reference clock present.

As in the external holdover mode, the B counter (in the N divider)

is reset synchronously with the charge pump leaving the high

impedance state on the reference path PFD event. This helps to

align the edges out of the R and N dividers for faster settling of

the PLL and reduce frequency errors during settling. Because the

prescaler is not reset, this feature works best when the B and R

numbers are close because this results in a smaller phase difference

for the loop to settle out.

YES

TAKE CHARGE PUMP OUT OF

HIGH IMPEDANCE. PLL CAN

NOW RESETTLE.

RELEASE

CHARGE PUMP

HIGH IMPEDANCE

YES

NO

WAIT FOR DLD TO GO HIGH. THIS TAKES

5 TO 255 CYCLES (PROGRAMMING OF

THE DLD DELAY COUNTER) WITH THE

REFERENCE AND FEEDBACK CLOCKS

INSIDE THE LOCK WINDOW AT THE PFD.

THIS ENSURES THAT THE HOLDOVER

FUNCTION WAITS FOR THE PLL TO SETTLE

AND LOCK BEFORE THE HOLDOVER

FUNCTION CAN BE RETRIGGERED.

After leaving holdover, the loop then reacquires lock, and the

LD pin must charge (if Register 0x01D[3] = 1) before it can

re-enter holdover (CP high impedance).

DLD == HIGH

The holdover function always responds to the state of the currently

selected reference (Register 0x01C). If the loop loses lock during a

reference switchover (see the Reference Switchover section),

holdover is triggered briefly until the next reference clock edge

at the PFD.

Figure 41. Flowchart of Automatic/Internal Holdover Mode

Rev. A | Page 33 of 76

AD9516-5

The following registers affect the internal/automatic holdover

function:

•

Register 0x018[3] = 0b; DLD normal operation.

Register 0x01A[5:0] = 000100b; current source lock detect

mode.

Register 0x01B[7:0] = 0xF7; set REFMON pin to status of

REF1 (active low).

Register 0x01C[2:1] = 11b; enable REF1 and REF2 input

buffers.

Register 0x01D[3] = 1b; enable LD pin comparator.

Register 0x01D[2] = 1b; enable holdover function.

Register 0x01D[1] = 0b; use internal/automatic holdover

mode.

•

Register 0x018[6:5], lock detect counter. These bits change

how many PFD cycles with edges inside the lock detect

window are required for the DLD indicator to indicate lock.

This impacts the time required before the LD pin can begin

to charge, as well as the delay from the end of a holdover

event until the holdover function can be reengaged.

Register 0x018[3], disable digital lock detect. This bit must

be set to 0b to enable the DLD circuit. Internal/automatic

holdover does not operate correctly without the DLD function

enabled.

Register 0x01A[5:0], lock detect pin output select. Set this

to 000100b to put it in the current source lock detect mode

if using the LD pin comparator. Load the LD pin with a

capacitor of an appropriate value.

Register 0x01D[3], LD pin comparator enable. 1b = enable;

0b = disable. When disabled, the holdover function always

senses the LD pin as high.

•

Register 0x01D[0] = 1b; enable holdover function

(complete VCO calibration before enabling this bit).

Register 0x232 = 0x01; update all registers.

And, finally,

•

Connect REFMON pin to REFSEL pin.

Frequency Status Monitors

The AD9516 contains three frequency status monitors that are

used to indicate if the PLL reference (or references, in the case

of single-ended mode) and the VCO have fallen below a threshold

frequency. Figure 42 is a diagram that shows their location in

the PLL.

•

Register 0x01D[1], external holdover control.

Register 0x01D[0] and Register 0x01D[2], holdover enable.

If holdover is disabled, both external and automatic/internal

holdover are disabled.

For example, to use automatic holdover with the following:

The PLL reference frequency monitors have two threshold

frequencies: normal and extended (see Table 12). The reference

frequency monitor thresholds are selected in Register 0x01B[7:5].

The reference frequency monitor status can be found in

Register 0x01F[3:1].

•

Digital lock detect: five PFD cycles, high range window

Automatic holdover using the LD pin comparator

Set the following registers (in addition to the normal PLL registers):

•

Register 0x018[6:5] = 00b; lock detect counter = five cycles.

Register 0x018[4] = 0b; lock detect window = high range.

REF_SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

REFIN (REF2)

HOLD

N DIVIDER

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

PROGRAMMABLE

N DELAY

CP

P, P + 1

A/B

PRESCALER

COUNTERS

CLK FREQUENCY

STATUS

0

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

Figure 42. Reference and CLK Status Monitors

Rev. A | Page 34 of 76

AD9516-5

CLK Direct to LVPECL Outputs

CLOCK DISTRIBUTION

It is possible to connect the CLK directly to the LVPECL outputs,

OUT0 to OUT5. However, the LVPECL outputs may not be able

to provide full a voltage swing at the highest frequencies.

A clock channel consists of a pair (or double pair, in the case of

CMOS) of outputs that share a common divider. A clock output

consists of the drivers that connect to the output pins. The clock

outputs have either LVPECL or LVDS/CMOS signal levels at

the pins.

To connect the LVPECL outputs directly to the CLK input, the

VCO divider must be selected as the source to the distribution

section even if no channel uses it.

The AD9516 has five clock channels: three channels are LVPECL

(six outputs); two channels are LVDS/CMOS (up to four LVDS

outputs, or up to eight CMOS outputs).

Table 26. Settings for Routing VCO Divider Input Directly

to LVPECL Outputs

Each channel has its own programmable divider that divides the

clock frequency that is applied to its input. The LVPECL channel

dividers can divide by any integer from 2 to 32, or the divider

can be bypassed to achieve a divide-by-1. Each LVDS/CMOS

channel divider contains two of these divider blocks in a cascaded

configuration. The total division of the channel is the product

of the divide value of the cascaded dividers. This allows divide

values of (1 to 32) × (1 to 32), or up to 1024 (note that this is

not all values from 1 to 1024 but only the set of numbers that

are the product of the two dividers).

Register Setting

0x1E1[0] = 0b

0x192[1] = 1b

0x195[1] = 1b

0x198[1] = 1b

Selection

VCO divider selected

Direct to OUT0, OUT1 outputs

Direct to OUT2, OUT3 outputs

Direct to OUT4, OUT5 outputs

Clock Frequency Division

The total frequency division is a combination of the VCO

divider (when used) and the channel divider. When the VCO

divider is used, the total division from the VCO or CLK to the

output is the product of the VCO divider (2, 3, 4, 5, and 6) and

the division of the channel divider. Table 27 and Table 28 indicate

how the frequency division for a channel is set. For the LVPECL

outputs, there is only one divider per channel. For the LVDS/

CMOS outputs, there are two dividers (X.1, X.2) cascaded

per channel.

The VCO divider can be set to divide by 2, 3, 4, 5, or 6 and must

be used if the external clock signal connected to the CLK input

is greater than 1600 MHz.

The channel dividers allow for a selection of various duty cycles,

depending on the currently set division. That is, for any specific

division, D, the output of the divider can be set to high for N + 1

input clock cycles and low for M + 1 input clock cycles (where

D = N + M + 2). For example, a divide-by-5 can be high for one

divider input cycle and low for four cycles, or a divide-by-5 can

be high for three divider input cycles and low for two cycles.

Other combinations are also possible.

Table 27. Frequency Division for Divider 0 to Divider 2

VCO

Divider

Setting

Channel

Divider

Setting

CLK Direct

to Output

Setting

Frequency

Division

2 to 6

Don’t care Enable

Bypass

2 to 32

1

Disable

No

(2 to 6) × (1)

(2 to 6) × (2 to 32)

1

The channel dividers include a duty-cycle correction function

that can be disabled. In contrast to the selectable duty cycle

just described, this function can correct a non-50ꢀ duty cycle

caused by an odd division. However, this requires that the

division be set by M = N + 1.

VCO Divider Bypass

Bypassed

VCO Divider 2 to 32

Bypassed

No

2 to 32

In addition, the channel dividers allow a coarse phase offset or

delay to be set. Depending on the division selected, the output

can be delayed by up to 31 input clock cycles. The divider

outputs can also be set to start high or start low.

Table 28. Frequency Division for Divider 3 and Divider 4

Channel Divider Setting

VCO Divider

Setting

Resulting Frequency

Division

X.1

X.2

Operating Modes

2 to 6

Bypass

2 to 32

Bypass

2 to 32

(2 to 6) × (1) × (1)

(2 to 6) × (2 to 32) × (1)

(2 to 6) × (2 to 32) ×

(2 to 32)

There are two clock distribution operating modes. These operating

modes are shown in Table 25.

It is not necessary to use the VCO divider if the CLK frequency

is less than the maximum channel divider input frequency

(1600 MHz); otherwise, the VCO divider must be used to

reduce the frequency going to the channel dividers.

Bypass

1

2 to 32

(2 to 32) × (1)

2 to 32 × (2 to 32)

2 to 32

The channel dividers feeding the LVPECL output drivers contain

one 2-to-32 frequency divider. This divider provides for division

by 2 to 32. Division by 1 is accomplished by bypassing the divider.

The dividers also provide for a programmable duty cycle, with

optional duty-cycle correction when the divide ratio is odd.

Table 25. Clock Distribution Operating Modes

Mode

0x1E1[0]

VCO Divider

2

1

0

1

Used

Not used

Rev. A | Page 35 of 76

AD9516-5

A phase offset or delay in increments of the input clock cycle is

selectable. The channel dividers operate with a signal at their

inputs up to 1600 MHz. The features and settings of the dividers

are selected by programming the appropriate setup and control

registers (see Table 47 through Table 57).

The DCC function is enabled, by default, for each channel divider.

However, the DCC function can be disabled individually for each

channel divider by setting the DCCOFF bit for that channel.

Certain M and N values for a channel divider result in a non-50ꢀ

duty cycle. A non-50ꢀ duty cycle can also result with an even

division, if M ≠ N. The duty-cycle correction function

automatically corrects non-50ꢀ duty cycles at the channel

divider output to 50ꢀ duty cycle. Duty-cycle correction

requires the following channel divider conditions:

VCO Divider

The VCO divider provides frequency division between the

external CLK input and the clock distribution channel dividers.

The VCO divider can be set to divide by 2, 3, 4, 5, or 6 (see

Table 55, Register 0x1E0[2:0]).

•

An even division must be set as M = N

An odd division must be set as M = N + 1

Channel Dividers—LVPECL Outputs

Each pair of LVPECL outputs is driven by a channel divider.

There are three channel dividers (0, 1, and 2) driving six

LVPECL outputs (OUT0 to OUT5). Table 29 lists the register

locations used for setting the division and other functions of

these dividers. The division is set by the values of M and N. The

divider can be bypassed (equivalent to divide-by-1, divider circuit

is powered down) by setting the bypass bit. The duty-cycle

correction can be enabled or disabled according to the setting

of the DCCOFF bits.

When not bypassed or corrected by the DCC function, the duty

cycle of each channel divider output is the numerical value of

(N + 1)/(N + M + 2), expressed as a percentage (ꢀ).

Table 30 to Table 32 list the duty cycles at the output of the channel

dividers for various configurations.

Table 30. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%

D_X

Output Duty Cycle

VCO

Divider

N + M + 2 DCCOFF = 1 DCCOFF = 0

Even

1 (divider

bypassed)

50ꢀ

1

Table 29. Setting D_Xfor Divider 0, Divider 1, and Divider 2

Low Cycles High Cycles

Odd = 3 1 (divider

bypassed)

Odd = 5 1 (divider

bypassed)

Even,

Odd

Even,

Odd

33.3ꢀ

40ꢀ

50ꢀ

Divider

M

N

Bypass

DCCOFF

0x192[0]

0x195[0]

0x198[0]

0

1

2

0x190[7:4]

0x193[7:4]

0x196[7:4]

0x190[3:0]

0x193[3:0]

0x196[3:0]

0x191[7]

0x194[7]

0x197[7]

50ꢀ

Even

(N + 1)/

(N + M + 2)

(N + 1)/

(N + M + 2)

50ꢀ, requires M = N

50ꢀ, requires M = N + 1

¹Note that the value stored in the register = # of cycles minus 1. For example,

0x190[7:4] = 0001b equals two low cycles (M = 2) for Divider 0.

Odd

Channel Frequency Division (0, 1, and 2)

Table 31. Duty Cycle with VCO Divider, Input Duty Cycle Is X%

For each channel (where the channel number is x: 0, 1, or 2),

the frequency division, D_X, is set by the values of M and N

(four bits each, representing Decimal 0 to Decimal 15), where

D_X

Output Duty Cycle

VCO

Divider

N + M + 2 DCCOFF = 1 DCCOFF = 0

Even

1 (divider

bypassed)

50ꢀ

Number of Low Cycles = M + 1

Number of High Cycles = N + 1

Odd = 3 1 (divider

bypassed)

Odd = 5 1 (divider

bypassed)

33.3ꢀ

40ꢀ

(1 + Xꢀ)/3

(2 + Xꢀ)/5

The cycles are cycles of the clock signal currently routed to the

input of the channel dividers (VCO divider out or CLK).

When a divider is bypassed, D_X= 1.

Even

(N + 1)/

50ꢀ,

(N + M + 2)

(N + 1)/

(N + M + 2)

(N + 1)/

(N + M + 2)

(N + 1)/

(N + M + 2)

(N + 1)/

requires M = N

50ꢀ,

requires M = N + 1

50ꢀ,

requires M = N

(3N + 4 + Xꢀ)/(6N + 9),

requires M = N + 1

50ꢀ,

requires M = N

Otherwise, D_X= (N + 1) + (M + 1) = N + M + 2. This allows

each channel divider to divide by any integer from 2 to 32.

Odd

Duty Cycle and Duty-Cycle Correction (0, 1, and 2)

The duty cycle of the clock signal at the output of a channel is a

result of some or all of the following conditions:

Odd = 3 Even

Odd = 3 Odd

Odd = 5 Even

Odd = 5 Odd

•

What are the M and N values for the channel?

Is the DCC enabled?

Is the VCO divider used?

(N + M + 2)

(N + 1)/

(N + M + 2)

(5N + 7 + Xꢀ)/(10N + 15),

requires M = N + 1

What is the CLK input duty cycle?

Rev. A | Page 36 of 76

AD9516-5

Case 1

Table 32. Channel Divider Output Duty Cycle When the

VCO Divider Is Not Used

For Φ ≤ 15:

Δ_t= Φ × T_X

Δ_c= Δ_t/T_X= Φ

D_X

Output Duty Cycle

Input Clock

Duty Cycle

N + M + 2 DCCOFF = 1 DCCOFF = 0

Case 2

Any

Channel

divider

bypassed

Even

Odd

1 (divider

bypassed)

Same as input

duty cycle

For Φ ≥ 16:

Δ_t= (Φ − 16 + M + 1) × T_X

Δ_c= Δ_t/T_X

Any

50ꢀ

Xꢀ

(N + 1)/

(M + N + 2)

(N + 1)/

(M + N + 2)

(N + 1)/

(M + N + 2)

50ꢀ, requires M = N

By giving each divider a different phase offset, output-to-output

delays can be set in increments of the channel divider input

clock cycle. Figure 43 shows the results of setting such a coarse

offset between outputs.

50ꢀ, requires

M = N + 1

(N + 1 + Xꢀ)/(2 × N + 3),

requires M = N + 1

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

If the CLK input is routed directly to the output, the duty cycle of

the output is the same as the CLK input.

CHANNEL

DIVIDER INPUT

Tx

TPUTS

CHANNEL DIVIDER OU

Phase Offset or Coarse Time Delay (0, 1, and 2)

DIV = 4, DUTY = 50%

SH = 0

DIVIDER 0

DIVIDER 1

DIVIDER 2

Each channel divider allows for a phase offset, or a coarse time

delay, to be programmed by setting register bits (see Table 33).

These settings determine the number of cycles (successive

rising edges) of the channel divider input frequency by which to

offset, or delay, the rising edge of the output of the divider. This

delay is with respect to a nondelayed output (that is, with a

phase offset of zero). The amount of the delay is set by five bits

loaded into the phase offset (PO) register, plus the start high

(SH) bit for each channel divider. When the start high bit is set,

the delay is also affected by the number of low cycles (M) that

are programmed for the divider.

PO = 0

SH = 0

PO = 1

SH = 0

PO = 2

1 × Tx

2 × Tx

Figure 43. Effect of Coarse Phase Offset (or Delay)

Channel Dividers—LVDS/CMOS Outputs

Channel Divider 3 and Channel Divider 4 each drive a pair of

LVDS outputs, giving four LVDS outputs (OUT6 to OUT9).

Alternatively, each of these LVDS differential outputs can be

configured individually as a pair (A and B) of CMOS single-

ended outputs, providing for up to eight CMOS outputs. By default,

the B output of each pair is off but can be turned on as desired.

The sync function must be used to make phase offsets effective

(see the Synchronizing the Outputs—SYNC Function section).

Table 33. Setting Phase Offset and Division for Divider 0,

1

Divider 1, and Divider 2

Channel Divider 3 and Channel Divider 4 each consist of two

cascaded, 2 to 32, frequency dividers. The channel frequency

division is D_X.1× D_X.2, or up to 1024. Divide-by-1 is achieved by

bypassing one or both of these dividers. Both of the dividers also

have DCC enabled by default, but this function can be disabled,

if desired, by setting the DCCOFF bit of the channel. A coarse

phase offset or delay is also programmable (see the Phase Offset

or Coarse Time Delay (Divider 3 and Divider 4) section). The

channel dividers operate up to 1600 MHz. The features and

settings of the dividers are selected by programming the

appropriate setup and control registers (see Table 47 and Table 48

through Table 57).

Start

Phase

Low

High

Cycles (N)

Divider High (SH) Offset (PO) Cycles (M)

0

1

2

0x191[4]

0x194[4]

0x197[4]

0x191[3:0]

0x194[3:0]

0x197[3:0]

0x190[7:4]

0x193[7:4]

0x196[7:4]

0x190[3:0]

0x193[3:0]

0x196[3:0]

¹Note that the value stored in the register = # of cycles minus 1. For example,

Register 0x190[7:4] = 0001b equals two low cycles (M = 2) for Divider 0.

Let

Δ_t= delay (in seconds).

Δ_c= delay (in cycles of clock signal at input to D_X).

T_X= period of the clock signal at the input of the divider, D_X(in

seconds).

Φ =

1

Table 34. Setting Division (D_X) for Divider 3 and Divider 4

Divider

M

N

Bypass

DCCOFF

0x19D[0]

0x1A2[0]

16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]

3

4

3.1 0x199[7:4]

3.2 0x19B[7:4]

4.1 0x19E[7:4]

4.2 0x1A0[7:4]

0x199[3:0]

0x19B[3:0]

0x19E[3:0]

0x1A0[3:0]

0x19C[4]

0x19C[5]

0x1A1[4]

0x1A1[5]

The channel divide-by is set as N = high cycles and M = low

cycles.

¹Note that the value stored in the register = # of cycles minus 1. For example,

Register 0x199[7:4] = 0001b equals two low cycles (M = 2) for Divider 3.1.

Rev. A | Page 37 of 76

AD9516-5

Table 36. Divider 3 and Divider 4 Duty Cycle; VCO Divider

Not Used; Duty Cycle Correction Off (DCCOFF = 1)

Channel Frequency Division (Divider 3 and Divider 4)

The division for each channel divider is set by the bits in the

registers for the individual dividers (X.Y = 3.1, 3.2, 4.1, and 4.2).

Input

Clock

Duty

Cycle

D_X.1

D_X.2

Number of Low Cycles = M_X.Y+ 1

Output

Duty Cycle

N_X.1+ M_X.1+ 2

Bypassed

N_X.2+ M_X.2+ 2

Bypassed

Number of High Cycles = N_X.Y+ 1

50ꢀ

Xꢀ

50ꢀ

Xꢀ

When both X.1 and X.2 are bypassed, D_X= 1 × 1 = 1.

When only X.2 is bypassed, D_X= (N_X.1+ M_X.1+ 2) × 1.

50ꢀ

Even, odd

Bypassed

(N_X.1+ 1)/

(N_X.1+ M_X.1+ 2)

When both X.1 and X.2 are not bypassed, D_X= (N_X.1+ M_X.1+ 2) ×

(N_X.2+ M_X.2+ 2).

Xꢀ

Even, odd

Bypassed

Even, odd

(N_X.1+ 1)/

(N_X.1+ M_X.1+ 2)

(N_X.2+ 1)/

(N_X.2+ M_X.2+ 2)

By cascading the dividers, channel division up to 1024 can be

obtained. However, not all integer value divisions from 1 to

1024 are obtainable; only the values that are the product of the

separate divisions of the two dividers (D_X.1× D_X.2) can be realized.

50ꢀ

Xꢀ

(N_X.2+ 1)/

(N_X.2+ M_X.2+ 2)

If only one divider is needed when using Divider 3 and Divider 4,

use the first one (X.1) and bypass the second one (X.2). Do not

bypass X.1 and use X.2.

Table 37. Divider 3 and Divider 4 Duty Cycle; VCO Divider

Used; Duty Cycle Correction On (DCCOFF = 0); VCO Divider

Input Duty Cycle = 50%

Duty Cycle and Duty-Cycle Correction (Divider 3 and

Divider 4)

D_X.1

D_X.2

VCO

Divider

Output

Duty Cycle

N_X.1+ M_X.1+ 2

Bypassed

Even (N_X.1= M_X.1

Odd (M_X.1= N_X.1+ 1) Bypassed

Even (N_X.1= M_X.1

N_X.2+ M_X.2+ 2

Bypassed

The same duty cycle and DCC considerations apply to Divider 3

and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see the

Duty Cycle and Duty-Cycle Correction (0, 1, and 2) section);

however, with these channel dividers, the number of possible

configurations is more complex.

Even

Odd

Even

Odd

Even

Odd

Even

50ꢀ

)

Duty-cycle correction on Divider 3 and Divider 4 requires the

following channel divider conditions:

)

Even

(N_X.2= M_X.2

)

•

An even D_X.Ymust be set as M_X.Y= N_X.Y(low cycles = high

cycles).

An odd D_X.Ymust be set as M_X.Y= N_X.Y+ 1 (number of low

cycles must be one greater than the number of high cycles).

If only one divider is bypassed, it must be the second

divider, X.2.

Odd

Even

Odd

Even

Odd

Even (N_X.1= M_X.1

)

Even

50ꢀ

(N_X.2= M_X.2

Odd (M_X.1= N_X.1+ 1) Even

(N_X.2= M_X.2

Odd (M_X.1= N_X.1+ 1) Even

(N_X.2= M_X.2

Odd (M_X.1= N_X.1+ 1) Odd

(M_X.2= N_X.2+ 1)

Odd (M_X.1= N_X.1+ 1) Odd

(M_X.2= N_X.2+ 1)

If only one divider has an even divide-by, it must be the

second divider, X.2.

The possibilities for the duty cycle of the output clock from

Divider 3 and Divider 4 are shown in Table 35 through Table 39.

Table 35. Divider 3 and Divider 4 Duty Cycle; VCO Divider

Used; Duty Cycle Correction Off (DCCOFF = 1)

D_X.1

D_X.2

VCO

Divider

Output Duty Cycle

N

_X.1+ M_X.1+ 2

N_X.2+ M_X.2+ 2

Bypassed

Even

Bypassed

50ꢀ

33.3ꢀ

40ꢀ

(N_X.1+ 1)/

(N_X.1+ M_X.1+ 2)

(N_X.1+ 1)/

(N_X.1+ M_X.1+ 2)

(N_X.2+ 1)/

(N_X.2+ M_X.2+ 2)

Odd = 3 Bypassed

Odd = 5 Bypassed

Even

Odd

Even

Odd

Even, odd

Bypassed

Even, odd

(N_X.2+ 1)/

(N_X.2+ M_X.2+ 2)

Rev. A | Page 38 of 76

AD9516-5

Table 38. Divider 3 and Divider 4 Duty Cycle; VCO Divider

Used; Duty Cycle Correction On (DCCOFF = 0); VCO

Divider Input Duty Cycle = X%

Table 39. Divider 3 and Divider 4 Duty Cycle; VCO Divider

Not Used; Duty Cycle Correction On (DCCOFF = 0)

Input

D_X.1

D_X.2

Clock

Duty

Cycle

D_X.1

D_X.2

Output

Duty Cycle

VCO

Divider

Output

Duty Cycle

N_X.2+ M_X.2+

2

N_X.1+ M_X.1+ 2 N_X.2+ M_X.2+ 2

N_X.1+ M_X.1+ 2

50ꢀ

Bypassed

Even

Bypassed

50ꢀ

Even

Bypassed

50ꢀ

Odd = 3 Bypassed

Odd = 5 Bypassed

Even

Odd

Even

(1 + Xꢀ)/3

(2 + Xꢀ)/5

50ꢀ

(N_X.1= M_X.1

)

Xꢀ

Bypassed

Even

Bypassed

Xꢀ (high)

50ꢀ

Even

(N_X.1= M_X.1

Even

(N_X.1= M_X.1

)

(N_X.1= M_X.1

)

Bypassed

50ꢀ

Xꢀ

Odd

(M_X.1= N_X.1+ 1)

Odd

(M_X.1= N_X.1+ 1)

Odd

(M_X.1= N_X.1+ 1)

Bypassed

50ꢀ

)

Odd

(N_X.1+ 1 + Xꢀ)/

(2N_X.1+ 3)

(N_X.1+ 1 + Xꢀ)/

(2N_X.1+ 3)

(M_X.1= N_X.1+ 1)

Odd = 3 Odd

(M_X.1= N_X.1+ 1)

Odd = 5 Odd

(M_X.1= N_X.1+ 1)

Even

(N_X.1= M_X.1

(3N_X.1+ 4 + Xꢀ)/

(6N_X.1+ 9)

(5N_X.1+ 7 + Xꢀ)/

(10N_X.1+ 15)

50ꢀ

Xꢀ

Even

(N_X.1= M_X.1

Even

(N_X.1= M_X.1

Even

(N_X.2= M_X.2

Even

(N_X.2= M_X.2

50ꢀ

)

Even

Odd

Even

Odd

Even

(N_X.2= M_X.2)

Even

(N_X.2= M_X.2

Even

(N_X.2= M_X.2

Even

(N_X.2= M_X.2

50ꢀ

)

Even

(N_X.1= M_X.1

Odd

(M_X.1= N_X.1+ 1)

Odd

(M_X.1= N_X.1+ 1)

Odd

50ꢀ

Xꢀ

Odd

Even

50ꢀ

)

(M_X.1= N_X.1+ 1) (N_X.2= M_X.2

Odd Even

(M_X.1= N_X.1+ 1) (N_X.2= M_X.2

Odd Odd

(M_X.1= N_X.1+ 1) (M_X.2= N_X.2+ 1)

Odd Odd

50ꢀ

Xꢀ

50ꢀ

Odd

(2N_X.1N_X.2+ 3N_X.1

+

(M_X.1= N_X.1+ 1)

(M_X.2= N_X.2+ 1)

(M_X.1= N_X.1+ 1) (M_X.2= N_X.2+ 1) 3N_X.2+ 4 + Xꢀ)/

((2N_X.1+ 3)(2N_X.2+ 3))

Odd = 3 Odd

(M_X.1= N_X.1+ 1)

Odd

(6N_X.1N_X.2+ 9N_X.1+

(M_X.2= N_X.2+ 1) 9N_X.2+ 13 + Xꢀ)/

(3(2N_X.1+ 3)

Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)

(2N_X.2+ 3))

Divider 3 and Divider 4 can be set to have a phase offset or

delay. The phase offset is set by a combination of the bits in the

phase offset and start high registers (see Table 40).

Odd = 5 Odd

(M_X.1= N_X.1+ 1)

Odd

(10N_X.1N_X.2+ 15N_X.1+

(M_X.2= N_X.2+ 1) 15N_X.2+ 22 + Xꢀ)/

(5(2 N_X.1+ 3)

(2 N_X.2+ 3))

Table 40. Setting Phase Offset and Division for Divider 3 and

Divider 4

1

Start

Phase

Low

High

Cycles N

Divider High (SH) Offset (PO) Cycles M

3

4

3.1 0x19C[0]

3.2 0x19C[1]

4.1 0x1A1[0]

4.2 0x1A1[1]

0x19A[3:0]

0x19A[7:4]

0x19F[3:0]

0x19F[7:4]

0x199[7:4] 0x199[3:0]

0x19B[7:4] 0x19B[3:0]

0x19E[7:4] 0x19E[3:0]

0x1A0[7:4] 0x1A0[3:0]

¹Note that the value stored in the register is equal to the number of cycles

minus 1. For example, Register 0x199[7:4] = 0001b equals two low cycles

(M = 2) for Divider 3.1.

Rev. A | Page 39 of 76

AD9516-5

Calculating the Fine Delay

Let

Δ_t= delay (in seconds).

The following values and equations are used to calculate the

delay of the delay block.

Φ_x.y= 16 × SH[0] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] +

1 × PO[0].

I

_RAMP(μA) = 200 × (Ramp Current + 1)

T

_X.1= period of the clock signal at the input to D_X.1(in seconds).

_X.2= period of the clock signal at the input to D_X.2(in seconds).

Number of Capacitors = Number of Bits =

0 in Ramp Capacitors + 1

Case 1

Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3;

001 = 2 + 1 = 3; 111 = 0 + 1 = 1.

When Φ_x.1≤ 15 and Φ_x.2≤ 15:

Δ_t= Φ_x.1× T_X.1+ Φ_X.2× T_x.2

Delay Range (ns) = 200 × ((No. of Caps + 3)/(I_RAMP)) × 1.3286

Case 2

No.of Caps 1













Offset



ns



 0.34 



1600  I_RAMP



10^4



6

When Φ_x.1≤ 15 and Φ_x.2≥ 16:

Δ_t= Φ_X.1× T_X.1+ (Φ_X.2– 16 + M_X.2+ 1) × T_X.2

I_RAMP

Delay Full Scale (ns) = Delay Range + Offset

Case 3

Fine Delay (ns) =

Delay Range × Delay Fraction × (1/63) + Offset

When Φ_X.1≥ 16 and Φ_X.2≤ 15:

Δ_t= (Φ_X.1− 16 + M_X.1+ 1) × T_X.1+ Φ_X.2× T_X.2

Note that only delay fraction values up to 47 decimal (101111b;

0x02F) are supported.

Case 4

When Φ_X.1≥ 16 and Φ_X.2≥ 16:

Δ_t=

(Φ_X.1− 16 + M_X.1+ 1) × T_X.1+ (Φ_X.2− 16 + M_X.2+ 1) × T_X.2

In no case can the fine delay exceed one-half of the output clock

period. If a delay longer than half of the clock period is attempted,

the output stops clocking.

Fine Delay Adjust (Divider 3 and Divider 4)

The delay function adds some jitter that is greater than that

specified for the nondelayed output. This means that the delay

function should be used primarily for clocking digital chips, such

as FPGA, ASIC, DUC, and DDC. An output with this delay

enabled may not be suitable for clocking data converters. The

jitter is higher for long full scales because the delay block uses a

ramp and trip points to create the variable delay. A slower ramp

time produces more time jitter.

Each AD9516 LVDS/CMOS output (OUT6 to OUT9) includes

an analog delay element that can be programmed to give variable

time delays (Δ_t) in the clock signal at that output.

VCO

CLK DIVIDER

BYPASS

CMOS

LVDS

CMOS

OUTM

∆t

FINE DELAY

ADJUST

OUTPUT

DRIVERS

DIVIDER

X.1

DIVIDER

X.2

Synchronizing the Outputs—SYNC Function

BYPASS

CMOS

LVDS

CMOS

The AD9516 clock outputs can be synchronized to each other.

Outputs can be individually excluded from synchronization.

Synchronization consists of setting the nonexcluded outputs to

a preset set of static conditions and, subsequently, releasing

these outputs to continue clocking at the same instant with the

preset conditions applied. This allows for the alignment of the

edges of two or more outputs or for the spacing of edges

according to the coarse phase offset settings for two or more

outputs.

OUTN

∆t

FINE DELAY

ADJUST

Figure 44. Fine Delay (OUT6 to OUT9)

The amount of delay applied to the clock signal is determined

by programming four registers per output (see Table 41).

Table 41. Setting Analog Fine Delays

OUTPUT

Ramp

Delay

Fraction

Delay

Bypass

Synchronization of the outputs is executed in several ways:

(LVDS/CMOS) Capacitors Current

OUT6

OUT7

OUT8

OUT9

0x0A1[5:3] 0x0A1[2:0] 0x0A2[5:0] 0x0A0[0]

0x0A4[5:3] 0x0A4[2:0] 0x0A5[5:0] 0x0A3[0]

0x0A7[5:3] 0x0A7[2:0] 0x0A8[5:0] 0x0A6[0]

0x0AA[5:3] 0x0AA[2:0] 0x0AB[5:0] 0x0A9[0]

SYNC

pin and then releasing it (manual sync)



By forcing the

By setting and then resetting any one of the following three

bits: the soft SYNC bit (Register 0x230[0]), the soft reset bit

(Register 0x000[2] [mirrored]), or the power-down

distribution reference bit (Register 0x230[1])

By executing synchronization of the outputs as part of the

chip power-up sequence



RESET



By forcing the

PD

pin low, then releasing it (chip reset)

pin low, then releasing it (chip power-down)

By forcing the

Rev. A | Page 40 of 76

AD9516-5

The most common way to execute the SYNC function is to use

SYNC

between 14 and 15 cycles of clock at the channel divider input,

plus either one cycle of the VCO divider input (see Figure 45),

or one cycle of the CLK input (see Figure 46), depending on

whether the VCO divider is used. Cycles are counted from the

rising edge of the signal.

the

pin to do a manual synchronization of the outputs.

SYNC

This requires a low going signal on the

pin, which is held

low and then released when synchronization is desired. The timing

of the SYNC operation is shown in Figure 45 (using VCO divider)

and Figure 46 (VCO divider not used). There is an uncertainty

of up to one cycle of the clock at the input to the channel divider

due to the asynchronous nature of the SYNC signal with respect

Another common way to execute the SYNC function is by setting

and resetting the soft SYNC bit at Register 0x230[0] (see Table 47

through Table 57 for details). Both the setting and resetting of

the soft SYNC bit require an update all registers operation

(Register 0x232[0] = 1) to take effect.

SYNC

to the clock edges inside the AD9516. The delay from the

rising edge to the beginning of synchronized output clocking is

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER OUTPUT STATIC

INPUT TO VCO DIVIDER

1

11

13

14

1

2

3

4

5

6

7

9

10

12

INPUT TO CHANNEL DIVIDER

8

SYNC PIN

OUTPUT OF

CHANNEL DIVIDER

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

Figure 45. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER OUTPUT STATIC

INPUT TO CLK

1

11

13

14

INPUT TO CHANNEL DIVIDER

1

2

3

4

5

6

7

9

10

12

8

SYNC PIN

OUTPUT OF

CHANNEL DIVIDER

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT

Figure 46. SYNC Timing When VCO Divider Is Not Used—CLK Input Only

Rev. A | Page 41 of 76

AD9516-5

A sync operation brings all outputs that have not been excluded (by

the nosync bit) to a preset condition before allowing the outputs to

begin clocking in synchronicity. The preset condition takes into

account the settings in each of the channel’s start high bit and its

phase offset. These settings govern both the static state of each

output when the sync operation is happening and the state and

relative phase of the outputs when they begin clocking again upon

completion of the sync operation. Between outputs and after

synchronization, this allows for the setting of phase offsets.

For this reason, the LVPECL outputs have several power-down

modes. This includes a safe power-down mode that continues

to protect the output devices while powered down, although it

consumes somewhat more power than a total power-down. If

the LVPECL output pins are terminated, it is best to select the

safe power-down mode. If the pins are not connected (unused),

it is acceptable to use the total power-down mode.

LVDS/CMOS Outputs—OUT6 to OUT9

OUT6 to OUT9 can be configured as either an LVDS differential

output or as a pair of CMOS single-ended outputs. The LVDS

outputs allow for selectable output current from ~1.75 mA to ~7 mA.

The AD9516 outputs are in pairs, sharing a channel divider per

pair (two pairs of pairs, four outputs, in the case of CMOS). The

synchronization conditions apply to both outputs of a pair.

3.5mA

Each channel (a divider and its outputs) can be excluded from

any sync operation by setting the nosync bit of the channel.

Channels that are set to ignore SYNC (excluded channels) do

not set their outputs static during a sync operation, and their

outputs are not synchronized with those of the nonexcluded

channels.

OUT

3.5mA

Clock Outputs

The AD9516 offers three output level choices: LVPECL, LVDS,

and CMOS. OUT0 to OUT5 are LVPECL differential outputs;

and OUT6 to OUT9 are LVDS/CMOS outputs. These outputs

can be configured as either LVDS differential or as pairs of

single-ended CMOS outputs.

Figure 48. LVDS Output, Simplified Equivalent Circuit with

3.5 mA Typical Current Source

The LVDS output polarity can be set as noninverting or inverting,

which allows for the adjustment of the relative polarity of outputs

within an application without requiring a board layout change. Each

LVDS output can be powered down, if not needed, to save power.

LVPECL Outputs—OUT0 to OUT5

The LVPECL differential voltage (VOD) is selectable from 400 mV

to 960 mV (see Register 0x0F0[3:2] to Register 0x0F5[3:2]). The

LVPECL outputs have dedicated pins for power supply

(VS_LVPECL), allowing a separate power supply to be used.

V_{S_LVPECL}can range from 2.5 V to 3.3 V.

OUT6 to OUT9 can also be CMOS outputs. Each LVDS output can

be configured to be two CMOS outputs. This provides for up to

eight CMOS outputs: OUT6A, OUT6B, OUT7A, OUT7B,

OUT8A, OUT8B, OUT9A, and OUT9B. When an output is

configured as CMOS, the CMOS Output A is automatically turned

on. The CMOS Output B can be turned on or off independently.

The relative polarity of the CMOS outputs can also be selected for

any combination of inverting and noninverting. See Table 52:

Register 0x140[7:5], Register 0x141[7:5], Register 0x142[7:5], and

Register 0x143[7:5].

3.3V

OUT

Each LVDS/CMOS output can be powered down, as needed, to

save power. The CMOS output power-down is controlled by the

same bit that controls the LVDS power-down for that output.

This power-down control affects both CMOS Output A and

CMOS Output B. However, when CMOS Output A is powered up,

CMOS Output B output can be powered on or off separately.

GND

Figure 47. LVPECL Output, Simplified Equivalent Circuit

V

S

The LVPECL output polarity can be set as noninverting or

inverting, which allows for the adjustment of the relative

polarity of outputs within an application without requiring a

board layout change. Each LVPECL output can be powered

down or powered up as needed. Because of the architecture of

the LVPECL output stages, there is the possibility of electrical

overstress and breakdown under certain power-down conditions.

OUT1/

OUT1

Figure 49. CMOS Equivalent Output Circuit

Rev. A | Page 42 of 76

AD9516-5

PD

When the AD9516 is in a

following state:

power-down, the chip is in the

RESET MODES

The AD9516 has several ways to force the chip into a reset

condition that restores all registers to their default values and

makes these settings active.

•

The PLL is off (asynchronous power-down).

The CLK input buffer is off.

All dividers are off.

Power-On Reset—Start-Up Conditions When VS Is Applied

All LVDS/CMOS outputs are off.

All LVPECL outputs are in safe off mode.

The serial port is active and responds to commands.

A power-on reset (POR) is issued when the VS power supply is

turned on. The POR pulse duration is <100 ms and initializes

the chip to the power-on conditions that are determined by the

default register settings. These are indicated in the Default Value

(Hex) column of Table 47. At power-on, the AD9516 also executes

a SYNC operation, which brings the outputs into phase alignment

according to the default settings. It is recommended that the

user not toggle SCLK during the reset pulse.

If the AD9516 clock outputs must be synchronized to each

other, a SYNC is required upon exiting power-down (see the

Synchronizing the Outputs—SYNC Function section).

PLL Power-Down

The PLL section of the AD9516 can be selectively powered

down. There are three PLL operating modes that are set by

Register 0x010[1:0], as shown in Table 49.

RESET

Asynchronous Reset via the

An asynchronous hard reset is executed by momentarily pulling

RESET

low. A reset restores the chip registers to the default settings.

It is recommended that the user not toggle SCLK for 20 ns after

RESET

In asynchronous power-down mode, the device powers down as

soon as the registers are updated.

goes high.

In synchronous power-down mode, the PLL power-down is

gated by the charge pump to prevent unwanted frequency jumps.

The device goes into power-down on the occurrence of the next

charge pump event after the registers are updated.

Soft Reset via Register 0x000[2]

A soft reset is executed by writing Register 0x000[2] and

Register 0x000[5] = 1b. This bit is not self-clearing; therefore,

it must be cleared by writing Register 0x000[2] and Register

0x000[2] = 0b to reset it and complete the soft reset operation.

A soft reset restores the default values to the internal registers.

The soft reset bit does not require an update registers command

(Register 0x232 = 0x01) to be issued.

Distribution Power-Down

The distribution section can be powered down by writing to

Register 0x230[1] = 1b. This turns off the bias to the distribution

section. If the LVPECL power-down mode is normal operation

(00b), it is possible for a low impedance load on that LVPECL

output to draw significant current during this power-down. If the

LVPECL power-down mode is set to 11b, the LVPECL output is

not protected from reverse bias and can be damaged under

certain termination conditions.

POWER-DOWN MODES

PD

Chip Power-Down via

The AD9516 can be put into a power-down condition by pulling

PD

the

currents inside the AD9516. The chip remains in this power-down

PD

pin low. Power-down turns off most of the functions and

Individual Clock Output Power-Down

state until

is brought back to logic high. When the AD9516

Any of the clock distribution outputs can be powered down

individually by writing to the appropriate registers. The register

map details the individual power-down settings for each output.

The LVDS/CMOS outputs can be powered down, regardless of

their output load configuration.

wakes up, it returns to the settings programmed into its registers

prior to the power-down, unless the registers are changed by

PD

new programming while the

pin is held low.

PD

The

power-down shuts down the currents on the chip, except

the bias current that is necessary to maintain the LVPECL outputs

in a safe shutdown mode. This is needed to protect the LVPECL

output circuitry from damage that can be caused by certain

termination and load configurations when tristated. Because this

is not a complete power-down, it can be called sleep mode.

The LVPECL outputs have multiple power-down modes

(see Table 53) that give some flexibility in dealing with the

various output termination conditions. When the mode is set to

10b, the LVPECL output is protected from reverse bias to

2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is

not protected from reverse bias and can be damaged under

certain termination conditions. This setting also affects the

operation when the distribution block is powered down with

0x230[1] = 1b (see the Distribution Power-Down section).

Individual Circuit Block Power-Down

Other AD9516 circuit blocks (such as CLK, REF1, and REF2)

can be powered down individually. This gives flexibility in

configuring the part for power savings whenever certain chip

functions are not needed.

Rev. A | Page 43 of 76

AD9516-5

SERIAL CONTROL PORT

The AD9516 serial control port is a flexible, synchronous, serial

communications port that allows an easy interface with many

industry-standard microcontrollers and microprocessors. The

AD9516 serial control port is compatible with most synchronous

transfer formats, including both the Motorola SPI® and Intel®

SSR® protocols. The serial control port allows read/write access

to all registers that configure the AD9516. Single or multiple byte

transfers are supported, as well as MSB first or LSB first transfer

formats. The AD9516 serial control port can be configured for a

single bidirectional I/O pin (SDIO only) or for two unidirectional

I/O pins (SDIO/SDO). By default, the AD9516 is in bidirectional

mode, long instruction (long instruction is the only instruction

mode supported).

During this period, the serial control port state machine enters

a wait state until all data is sent. If the system controller decides

to abort the transfer before all of the data is sent, the state machine

must be reset, either by completing the remaining transfers or

by returning the

low for at least one complete SCLK cycle

CS

(but less than eight SCLK cycles). Raising the

on a nonbyte

CS

boundary terminates the serial transfer and flushes the buffer.

In streaming mode (see Table 42), any number of data bytes can

be transferred in a continuous stream. The register address is

automatically incremented or decremented (see the MSB/LSB

First Transfers section).

must be raised at the end of the last

CS

byte to be transferred, thereby ending the stream mode.

Communication Cycle—Instruction Plus Data

SERIAL CONTROL PORT PIN DESCRIPTIONS

There are two parts to a communication cycle with the AD9516.

The first part writes a 16-bit instruction word into the AD9516,

coincident with the first 16 SCLK rising edges. The instruction

word provides the AD9516 serial control port with information

regarding the data transfer, which is the second part of the

communication cycle. The instruction word defines whether

the upcoming data transfer is a read or a write, the number of

bytes in the data transfer, and the starting register address for

the first byte of the data transfer.

SCLK (serial clock) is the serial shift clock. This pin is an input.

SCLK is used to synchronize serial control port reads and writes.

Write data bits are registered on the rising edge of this clock,

and read data bits are registered on the falling edge. This pin

is internally pulled down by a 30 kΩ resistor to ground.

SDIO (serial data input/output) is a dual-purpose pin that acts

as either an input only (unidirectional mode) or as both an input/

output (bidirectional mode). The AD9516 defaults to the

bidirectional I/O mode (Register 0x000[0] = 0b).

Write

SDO (serial data output) is used only in the unidirectional I/O

mode (Register 0x000[0] = 1b) as a separate output pin for

reading back data.

If the instruction word is for a write operation, the second part

is the transfer of data into the serial control port buffer of the

AD9516. Data bits are registered on the rising edge of SCLK.

CS

(chip select bar) is an active low control that gates the read

The length of the transfer (1, 2, or 3 bytes or streaming mode)

is indicated by two bits ([W1:W0]) in the instruction byte.

CS

and write cycles. When

is high, SDO and SDIO are in a high

impedance state. This pin is internally pulled up by a 30 kΩ

resistor to VS.

When the transfer is 1, 2, or 3 bytes, but not streaming,

can

CS

be raised after each sequence of eight bits to stall the bus (except

after the last byte, where it ends the cycle). When the bus is stalled,

16

SCLK

AD9516-5

SERIAL

CONTROL

PORT

the serial transfer resumes when

is lowered. Raising

on

CS

17

CS

21

SDO

a nonbyte boundary resets the serial control port. During a write,

streaming mode does not skip over reserved or unused registers;

therefore, the user must know the correct bit pattern to write to

the reserved registers to preserve proper operation of the part.

Refer to the register map (see Table 47) to determine if the default

value for reserved registers is nonzero. It does not matter what

data is written to blank or unused registers.

22

SDIO

Figure 50. Serial Control Port

GENERAL OPERATION OF SERIAL CONTROL PORT

A write or a read operation to the AD9516 is initiated by pulling

low.

CS

Because data is written into a serial control port buffer area, and

not directly into the actual control registers of the AD9516, an

additional operation is needed to transfer the serial control port

buffer contents to the actual control registers of the AD9516,

thereby causing them to become active. The update registers

operation consists of setting Register 0x232[0] = 1b (this bit is self-

clearing). Any number of bytes of data can be changed before

executing an update registers. The update registers operation

simultaneously actuates all register changes that have been

written to the buffer since any previous update.

stall high is supported in modes where three or fewer bytes

CS

of data (plus instruction data) are transferred (see Table 42).

In these modes, can temporarily return high on any byte

CS

boundary, allowing time for the system controller to process the

next byte. can go high on byte boundaries only and during

CS

either part (instruction or data) of the transfer.

Rev. A | Page 44 of 76

AD9516-5

Read

The 13 bits found in Bits[A12:A0] select the address within the

register map that is written to or read from during the data

transfer portion of the communications cycle. Only Bits[A9:A0]

are needed to cover the range of the 0x232 registers used by the

AD9516. Bits[A12:A10] must always be set to 0b. For multibyte

transfers, this address is the starting byte address. In MSB first

mode, subsequent bytes decrement the address.

If the instruction word is for a read operation, the next N × 8

SCLK cycles clock out the data from the address specified in the

instruction word, where N is 1 to 3, as determined by [W1:W0].

If N = 4, the read operation is in streaming mode, continuing

until

is raised. Streaming mode does not skip over reserved

CS

or blank registers. The readback data is valid on the falling

edge of SCLK.

MSB/LSB FIRST TRANSFERS

The AD9516 instruction word and byte data can be MSB first

or LSB first. Any data written to Register 0x000 must be mirrored;

the upper four bits (Bits[7:4]) must mirror the lower four bits

(Bits[3:0]). This makes it irrelevant whether LSB first or MSB first

is in effect. As an example of this mirroring, see the default

setting for this register: 0x000, which mirrors Bit 4 and Bit 3.

This sets the long instruction mode (which is the default and

the only mode that is supported).

The default mode of the AD9516 serial control port is the

bidirectional mode. In bidirectional mode, both the sent data

and the readback data appear on the SDIO pin. It is also possible to

set the AD9516 to unidirectional mode via the SDO active bit

(Register 0x000[0] = 1b). In unidirectional mode, the readback

data appears on the SDO pin.

A readback request reads the data that is in the serial control

port buffer area, or the data that is in the active registers (see

Figure 51). Readback of the buffer or active registers is controlled

by Register 0x004[0].

The default for the AD9516 is MSB first.

When LSB first is set by Register 0x000[1] and Register 0x000[6],

it takes effect immediately, because it affects only the operation

of the serial control port and does not require that an update be

executed.

The AD9516 supports only the long instruction mode; therefore,

Register 0x000[4:3] must be set to 11b. (This register uses

mirrored bits). Long instruction mode is the default at power-

up or reset.

When MSB first mode is active, the instruction and data bytes

must be written from MSB to LSB. Multibyte data transfers in

MSB first format start with an instruction byte that includes the

register address of the most significant data byte. Subsequent data

bytes must follow, in order, from high address to low address. In

MSB first mode, the serial control port internal address generator

decrements for each data byte of the multibyte transfer cycle.

The AD9516 uses Register Address 0x000 to Register

Address 0x232.

SCLK

SDIO

SDO

UPDATE

REGISTERS

CS

When LSB first is active, the instruction and data bytes must be

written from LSB to MSB. Multibyte data transfers in LSB first

format start with an instruction byte that includes the register

address of the least significant data byte followed by multiple

data bytes. The internal byte address generator of the serial control

port increments for each byte of the multibyte transfer cycle.

SERIAL

CONTROL

PORT

WRITE REGISTER 0x232 = 0x01

TO UDATE REGISTERS

Figure 51. Relationship Between Serial Control Port Buffer Registers and

Active Registers of the AD9516

INSTRUCTION WORD (16 BITS)

The AD9516 serial control port register address decrements from

the register address just written toward 0x000 for multibyte I/O

operations if the MSB first mode is active (default). If the LSB

first mode is active, the register address of the serial control port

increments from the address just written toward Register 0x232

for multibyte I/O operations.

W

The MSB of the instruction word is R/ , which indicates

whether the instruction is a read or a write. The next two bits,

[W1:W0], indicate the length of the transfer in bytes. The final

13 bits are the address ([A12:A0]) at which to begin the read or

write operation.

Streaming mode always terminates when it hits Address 0x232.

Note that unused addresses are not skipped during multibyte

I/O operations.

For a write, the instruction word is followed by the number of

bytes of data indicated by Bits[W1:W0], see Table 42.

Table 42. Byte Transfer Count

Table 43. Streaming Mode (No Addresses Are Skipped)

W1

W0

Bytes to Transfer

Write Mode Address Direction Stop Sequence

0

1

LSB first

MSB first

Increment

Decrement

0x230, 0x231, 0x232, stop

0x001, 0x000, 0x232, stop

0

1

0

2

3

1

Streaming mode

Rev. A | Page 45 of 76

AD9516-5

Table 44. Serial Control Port, 16-Bit Instruction Word, MSB First

MSB

LSB

I0

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I1

R/W

W1

W0

A12 = 0

A11 = 0

A10 = 0

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

CS

SCLK DON'T CARE

DON'T CARE

SDIO

R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA

Figure 52. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data

CS

SCLK

DON'T CARE

R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DON'T CARE

SDIO

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDO DON'T CARE

16-BIT INSTRUCTION HEADER

REGISTER (N) DATA

REGISTER (N – 1) DATA

REGISTER (N – 2) DATA

REGISTER (N – 3) DATA

DON'T

CARE

Figure 53. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data

t_HIGH

t_DS

t_S

t_C

t_SCLK

t_DH

t_LOW

CS

DON'T CARE

SCLK

SDIO

R/W

W1

W0

A12

A11

A10

A9

A8

A7

A6

A5

D4

D3

D2

D1

D0

DON'T CARE

Figure 54. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements

CS

SCLK

t_DV

SDIO

SDO

DATA BIT N

DATA BIT N – 1

Figure 55. Timing Diagram for Serial Control Port Register Read

CS

SCLK DON'T CARE

DON'T CARE

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA

SDIO

Figure 56. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data

Rev. A | Page 46 of 76

AD9516-5

t_S

t_C

CS

t_SCLK

t_HIGH

t_LOW

t_DS

SCLK

SDIO

t_DH

BIT N

BIT N + 1

Figure 57. Serial Control Port Timing—Write

Table 45. Serial Control Port Timing

Parameter

Description

t_DS

t_DH

t_CLK

t_S

Setup time between data and the rising edge of SCLK

Hold time between data and the rising edge of SCLK

Period of the clock

Setup time between the CS falling edge and the SCLK rising edge (start of communication cycle)

Setup time between the SCLK rising edge and the CS rising edge (end of communication cycle)

Minimum period that SCLK should be in a logic high state

t_C

t_HIGH

t_LOW

t_DV

Minimum period that SCLK should be in a logic low state

SCLK to valid SDIO and SDO (see Figure 55)

Rev. A | Page 47 of 76

AD9516-5

THERMAL PERFORMANCE

Table 46. Thermal Parameters for 64-Lead LFCSP

Symbol

Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board

Junction-to-ambient thermal resistance, natural convection per JEDEC JESD51-2 (still air)

Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)

Junction-to-ambient thermal resistance, 2.0 m/sec airflow per JEDEC JESD51-6 (moving air)

Value (°C/W)

22.0

19.2

θ_JA

θ_JMA

17.2

Ψ_JB

Junction-to-board characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)

and JEDEC JESD51-8

11.6

θ_JC

Ψ_JT

Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1

Junction-to-top-of-package characterization parameter, natural convection per JEDEC JESD51-2 (still air)

1.3

0.1

The AD9516 is specified for a case temperature (T_CASE). To ensure

that T_CASEis not exceeded, an airflow source can be used.

Values of θ_JAare provided for package comparison and PCB

design considerations. θ_JAcan be used for a first-order

approximation of T_Jby the following equation:

Use the following equation to determine the junction

temperature on the application PCB:

T_J= T_A+ (θ_JA× PD)

T_J= T_CASE+ (Ψ_JT× PD)

where T_Ais the ambient temperature (°C).

where:

Values of θ_JCare provided for package comparison and PCB

design considerations when an external heat sink is required.

T_Jis the junction temperature (°C).

T

_CASEis the case temperature (°C) measured by the user at the

Values of Ψ_JBare provided for package comparison and PCB

design considerations.

top center of the package.

Ψ_JTis the value from Table 46.

PD is the power dissipation of the device (see Table 13.)

Rev. A | Page 48 of 76

AD9516-5

REGISTER MAPS

REGISTER MAP OVERVIEW

Register addresses that are not listed in Table 47 (as well as ones marked unused) are not used and writing to those registers has no effect.

The user should write the default value only to the register addresses marked reserved.

Table 47. Register Map Overview

Ref.

Addr.

(Hex)

Default

Value

(Hex)

Parameter

Bit 7 (MSB) Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Serial Port Configuration

0x000

Serial port

configuration

SDO active LSB first

Soft reset

Long

instruction

Long

instruction

Soft reset

LSB first

SDO active

0x18

0x001

0x002

0x003

0x004

Blank

Reserved

Part ID

Part ID (read only)

0x01

0x00

Readback

control

Blank

Read back

active

registers

PLL

0x010

PFD and

PFD

Charge pump current

Charge pump mode

PLL power-down

0x7D

charge pump

polarity

0x011

0x012

0x013

0x014

0x015

0x016

R Counter

14-bit R divider, Bits[7:0] (LSB)

14-bit R divider, Bits[13:8] (MSB)

6-bit A counter

13-bit B counter, Bits[7:0] (LSB)

13-bit B counter, Bits[12:8] (MSB)

B counter Prescaler P

0x01

0x00

0x03

0x00

0x06

Blank

A counter

B counter

Blank

PLL Control 1

Set CP pin

to V_CP/2

Reset R

counter

Reset A and

B counters

Reset all

counters

bypass

0x017

0x018

PLL Control 2

PLL Control 3

STATUS pin control

Antibacklash pulse width

Reserved

0x00

0x06

Reserved

Lock detect counter

Digital

lock detect

window

Disable

digital

lock detect

0x019

PLL Control 4

R, A, B counters

SYNC

R path delay

N path delay

0x00

pin reset

0x01A PLL Control 5

Reserved

Reference

frequency

monitor

LD pin control

threshold

0x01B

0x01C

PLL Control 6

PLL Control 7

CLK

frequency

monitor

REF2

REF1 (REFIN)

frequency

monitor

REFMON pin control

0x00

REFIN

(

)

frequency

monitor

Disable

switchover REF2

deglitch

Select

Use

REF_SEL pin

Reserved

REF2

REF1

Differential

reference

0x00

power-on

0x01D PLL Control 8

Reserved

PLL status

register

disable

LD pin

comparator

enable

Holdover

enable

External

holdover

control

Holdover

enable

0x01E

0x01F

PLL Control 9

Reserved

0x00

N/A

PLL readback

(read-only)

Reserved

Holdover

active

REF2

selected

CLK

frequency >

threshold

REF2

REF1

Digital

lock detect

frequency > frequency >

threshold threshold

0x020

to

Blank

0x04F

Rev. A | Page 49 of 76

AD9516-5

Ref.

Addr.

(Hex)

Default

Value

(Hex)

Parameter

Bit 7 (MSB) Bit 6

Bit 5

Bit 4

Blank

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Fine Delay Adjust—OUT6 to OUT9

0x0A0 OUT6 delay

bypass

OUT6 delay

bypass

0x01

0x00

0x01

0x00

0x01

0x00

0x01

0x00

0x0A1 OUT6 delay

full-scale

Blank

OUT6 ramp capacitors

OUT6 ramp current

0x0A2 OUT6 delay

fraction

OUT6 delay fraction

OUT7 delay fraction

OUT8 delay fraction

0x0A3 OUT7 delay

bypass

Blank

OUT7 delay

bypass

OUT7 ramp current

0x0A4 OUT7 delay

full-scale

Blank

OUT7 ramp capacitors

0x0A5 OUT7 delay

fraction

0x0A6 OUT8 delay

bypass

Blank

OUT8 delay

bypass

0x0A7 OUT8 delay

full-scale

Blank

OUT8 ramp capacitors

OUT8 ramp current

0x0A8 OUT8 delay

fraction

0x0A9 OUT9 delay

bypass

Blank

OUT9 delay

bypass

0x0AA OUT9 delay

full-scale

Blank

OUT9 ramp capacitors

OUT9 ramp current

0x0AB OUT9 delay

fraction

OUT9 delay fraction

0x00

0x0AC

to

Blank

0x0EF

LVPECL Outputs

0x0F0

OUT0

Blank

OUT0

invert

OUT0 LVPECL

differential voltage

OUT0 power-down

0x08

0x0A

0x0F1

OUT1

invert

OUT1 LVPECL

differential voltage

OUT1 power-down

0x0F2

0x0F3

0x0F4

0x0F5

OUT2

OUT3

OUT4

OUT5

Blank

OUT2

invert

OUT2 LVPECL

differential voltage

OUT2 power-down

OUT3 power-down

OUT4 power-down

OUT5 power-down

0x08

0x0A

0x08

0x0A

OUT3

invert

OUT3 LVPECL

differential voltage

OUT4

invert

OUT4 LVPECL

differential voltage

OUT5

invert

OUT5 LVPECL

differential voltage

0x0F6

to

Blank

0x13F

LVDS/CMOS Outputs

0x140

0x141

0x142

0x143

OUT6

OUT7

OUT8

OUT9

OUT6 CMOS

output polarity

OUT6

CMOS B

OUT6 select

LVDS/CMOS

OUT6 LVDS

output current

OUT6

power-down

0x42

0x43

0x42

0x43

OUT7 CMOS

output polarity

OUT7

CMOS B

OUT7 select

LVDS/CMOS

OUT7 LVDS

output current

OUT7

power-down

OUT8 CMOS

output polarity

OUT8

CMOS B

OUT8 select

LVDS/CMOS

OUT8 LVDS

output current

OUT8

power-down

OUT9 CMOS

output polarity

OUT9

CMOS B

OUT9 select

LVDS/CMOS

OUT9 LVDS

output current

OUT9

power-down

0x144

to

Blank

0x18F

Rev. A | Page 50 of 76

AD9516-5

Ref.

Addr.

(Hex)

Default

Value

(Hex)

Parameter

Bit 7 (MSB) Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

LVPECL Channel Dividers

0x190

0x191

Divider 0

(PECL)

Divider 0 low cycles

Divider 0 high cycles

Divider 0 phase offset

0x00

0x80

Divider 0

bypass

Divider 0

nosync

Divider 0

force high

Divider 0

start high

0x192

Blank

Divider 0

direct to

output

Divider 0

DCCOFF

0x00

0x193

0x194

Divider 1

(PECL)

Divider 1 low cycles

Divider 1 high cycles

Divider 1 phase offset

0xBB

0x00

Divider 1

bypass

Divider 1

nosync

Divider 1

force high

Divider 1

start high

0x195

Blank

Divider 1

direct to

output

Divider 1

DCCOFF

0x00

0x196

0x197

Divider 2

(PECL)

Divider 2 low cycles

Divider 2 high cycles

Divider 2 phase offset

0x00

Divider 2

bypass

Divider 2

nosync

Divider 2

force high

Divider 2

start high

0x198

Blank

Divider 2

direct to

output

Divider 2

DCCOFF

0x00

LVDS/CMOS Channel Dividers

0x199

Divider 3

Low Cycles Divider 3.1

High Cycles Divider 3.1

0x22

(LVDS/CMOS)

0x19A

0x19B

0x19C

Phase Offset Divider 3.2

Low Cycles Divider 3.2

Phase Offset Divider 3.1

High Cycles Divider 3.2

0x00

0x11

0x00

Reserved

Bypass

Divider 3.2

Bypass

Divider 3.1

Divider 3

nosync

Divider 3

Start High

Divider 3.2

Start High

Divider 3.1

force high

0x19D

Blank

Divider 3

DCCOFF

0x00

0x19E

0x19F

0x1A0

0x1A1

Divider 4

(LVDS/CMOS)

Low Cycles Divider 4.1

Phase Offset Divider 4.2

Low Cycles Divider 4.2

High Cycles Divider 4.1

Phase Offset Divider 4.1

High Cycles Divider 4.2

0x22

0x00

0x11

0x00

Reserved

Bypass

Divider 4.2

Bypass

Divider 4.1

Divider 4

nosync

Divider 4

Start High

Divider 4.2

Start High

Divider 4.1

force high

0x1A2

Blank

Divider 4

DCCOFF

0x00

0x1A3

Reserved (read-only)

Blank

0x1A4

to

0x1DF

VCO Divider and CLK Input

0x1E0

0x1E1

VCO divider

Input CLKs

Blank

VCO divider

0x02

0x00

Reserved

Power-

down

Reserved

Bypass

VCO divider

clock input

section

0x1E2

to

Blank

0x22A

System

0x230

Power-down

and SYNC

Reserved

Power-

down

SYNC

Power-

down

distribution

reference

Soft SYNC

0x00

0x231

Blank

0x00

Update All Registers

0x232

Update all

registers

Blank

Update all

registers

(self-clearing)

Rev. A | Page 51 of 76

AD9516-5

REGISTER MAP DESCRIPTIONS

Table 48 through Table 57 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal

address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, as follows: [5:2].

Table 48. Serial Port Configuration

Reg.

Addr.

(Hex) Bits

Name

Description

0x000 [7:4]

Mirrored, Bits[3:0]

Bits[7:4] should always mirror Bits[3:0], so that it does not matter whether the part is in

MSB or LSB first mode (see Bit 1, Register 0x000). The user should set the bits as follows:

Bit 7 = Bit 0.

Bit 6 = Bit 1.

Bit 5 = Bit 2.

Bit 4 = Bit 3.

3

Long instruction

Short/long instruction mode. This part uses long instruction mode only, so this bit should

always be set to 1b.

0: 8-bit instruction (short).

1: 16-bit instruction (long) (default).

Soft reset.

1: soft reset; restores default values to internal registers. Not self-clearing. Must be cleared

to 0b to complete reset operation.

2

1

Soft reset

LSB first

MSB or LSB data orientation.

0: data-oriented MSB first; addressing decrements (default).

1: data-oriented LSB first; addressing increments.

Selects unidirectional or bidirectional data transfer mode.

0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default).

1: SDO used for read, SDIO used for write; unidirectional mode.

Uniquely identifies the dash version (-0 through -5) of the AD9516.

AD9516-0: 0x01.

0

SDO active

0x003 [7:0]

Part ID (read only)

AD9516-1: 0x41.

AD9516-2: 0x81.

AD9516-3: 0x43.

AD9516-4: 0xC3.

AD9516-5: 0xC1.

0x004

0

Read back active registers

Selects register bank used for a readback.

0: reads back buffer registers (default).

1: reads back active registers.

Rev. A | Page 52 of 76

AD9516-5

Table 49. PLL

Reg.

Addr.

(Hex)

Bits

Name

Description

0x010

7

PFD polarity

Sets the PFD polarity.

0: positive; higher control voltage produces higher frequency (default).

1: negative; higher control voltage produces lower frequency.

Charge pump current (with CPRSET = 5.1 kΩ).

[6:4] CP current

6

0

1

5

0

1

0

1

4

0

1

0

1

0

1

0

1

ICP (mA)

0.6

1.2

1.8

2.4

3.0

3.6

4.2

4.8 (default)

[3:2] CP mode

Charge pump operating mode.

3

0

1

2

0

1

0

1

Charge Pump Mode

High impedance state

Force source current (pump up)

Force sink current (pump down)

Normal operation (default)

[1:0] PLL power-down

PLL operating mode.

1

0

1

0

1

0

1

Mode

Normal operation

Asynchronous power-down (default)

Normal operation

Synchronous power-down

0x011

0x012

[7:0] 14-bit R divider,

Bits[7:0] (LSB)

R divider LSBs—lower eight bits (default = 0x01).

R divider MSBs—upper six bits (default = 0x00).

A counter (part of N divider) (default = 0x00).

[5:0] 14-bit R divider,

Bits[13:8] (MSB)

0x013

0x014

[5:0] 6-bit A counter

[7:0] 13-bit B counter, B counter (part of N divider)—lower eight bits (default = 0x03).

Bits[7:0] (LSB)

0x015

0x016

[4:0] 13-bit B counter, B counter (part of N divider)—upper five bits (default = 0x00).

Bits[12:8] (MSB)

7

6

5

4

3

Set CP pin

to V_CP/2

Sets the CP pin to one-half of the V_CPsupply voltage.

0: CP normal operation (default).

1: CP pin set to V_CP/2.

Reset R counter

Resets R counter (R divider). This bit is not self-clearing.

0: normal (default).

1: holds the R counter in reset.

Reset A and B

counters

Resets A and B counters (part of N divider).

0: normal (default). This bit is not self-clearing.

1: holds the A and B counters in reset.

Reset all counters Resets R, A, and B counters. This bit is not self-clearing.

0: normal (default).

1: holds the R, A, and B counters in reset.

B counter bypass

B counter bypass. This is valid only when operating the prescaler in FD mode.

0: normal (default).

1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.

Rev. A | Page 53 of 76

AD9516-5

Reg.

Addr.

(Hex)

Bits

Name

Description

[2:0] Prescaler P

Prescaler. DM = dual modulus, and FD = fixed divide.

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Mode

FD

Prescaler

Divide-by-1

FD

Divide-by-2

DM

FD

Divide-by-2 (2/3 mode)

Divide-by-4 (4/5 mode)

Divide-by-8 (8/9 mode)

Divide-by-16 (16/17 mode)

Divide-by-32 (22/23 mode) (default)

Divide-by-3

0x017

[7:2] STATUS pin

control

Selects the STATUS pin signal.

Level or

Dynamic

Signal

7

0

6

0

X

5

0

X

4

0

1

X

3

0

1

0

1

X

2

0

1

0

1

0

1

0

X

Signal at STATUS Pin

LVL

Ground (dc) (default)

DYN

LVL

N divider output (after the delay)

R divider output (after the delay)

A divider output

Prescaler output

PFD up pulse

PFD down pulse

Ground (dc); for all other cases of 0x0XXXX not specified

The selections that follow are the same as for REFMON:

Ground (dc)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LVL

DYN

LVL

DYN

LVL

REF1 clock (differential reference when in differential mode)

REF2 clock (not available in differential mode)

Selected reference to PLL (differential reference when in differential mode)

Unselected reference to PLL (not available in differential mode)

Status of selected reference (status of differential reference); active high

Status of unselected reference (not available in differential mode); active high

Status of REF1 frequency (active high)

Status of REF2 frequency (active high)

(Status of REF1 frequency) AND (status of REF2 frequency)

(DLD) AND (status of selected reference) AND (status of CLK)

Status of CLK frequency (active high)

Selected reference (low = REF1, high = REF2)

Digital lock detect (DLD); active high

Holdover active (active high)

LD pin comparator output (active high)

VS (PLL supply)

REF1 clock

REF2 clock

(differential reference when in differential mode)

(not available in differential mode)

Selected reference to PLL

(differential reference when in differential mode)

Unselected reference to PLL

(not available when in differential mode)

Status of selected reference (status of differential reference); active low

Status of unselected reference (not available in differential mode); active low

Status of REF1 frequency (active low)

Status of REF2 frequency (active low)

(Status of REF1 frequency) AND (status of REF2 frequency)

(DLD) AND (status of selected reference) AND (status of CLK)

Status of CLK Frequency (active low)

Selected reference (low = REF2, high = REF1)

Digital lock detect (DLD) (active low)

Holdover active (active low)

LD pin comparator output (active low)

Rev. A | Page 54 of 76

AD9516-5

Reg.

Addr.

(Hex)

Bits

Name

Description

[1:0] Antibacklash

pulse width

1

0

1

0

1

0

1

Antibacklash Pulse Width (ns)

2.9 (default)

1.3

6.0

2.9

0x018

[6:5] Lock detect

counter

Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked

condition.

6

0

1

5

0

1

0

1

PFD Cycles to Determine Lock

5 (default)

16

64

255

4

3

Digital lock

detect window

If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital

lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.

0: high range (default).

1: low range.

Disable digital

lock detect

Digital lock detect operation.

0: normal lock detect operation (default).

1: disables lock detect.

0x019

[7:6] R, A, B counters

SYNC

7

0

1

6

0

1

0

1

Action

pin reset

SYNC

Does nothing on

(default)

Asynchronous reset

Synchronous reset

SYNC

Does nothing on

[5:3] R path delay

[2:0] N path delay

R path delay (default = 0x0); see Table 2.

N path delay (default = 0x0); see Table 2.

Rev. A | Page 55 of 76

AD9516-5

Reg.

Addr.

(Hex)

Bits

Name

Description

0x01A

6

Reference

frequency

monitor

Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the CLK

frequency monitor’s detection threshold (see Table 12: REF1, REF2, and CLK frequency status monitor parameter).

0: frequency valid if frequency is above the higher frequency threshold (default).

1: frequency valid if frequency is above the lower frequency threshold.

Selects the LD pin signal.

threshold

[5:0] LD pin control

Level or

Dynamic

5

0

4

0

X

3

0

X

2

0

1

X

1

0

1

0

X

0

1

0

1

0

X

Signal

Signal at LD Pin

LVL

Digital lock detect (high = lock, low = unlock) (default)

P-channel, open-drain lock detect (analog lock detect)

N-channel, open-drain lock detect (analog lock detect)

High-Z LD pin

DYN

HIZ

CUR

LVL

Current source lock detect (110 μA when DLD is true)

Ground (dc); for all other cases of 0x0XXXX not specified

The selections that follow are the same as for REFMON:

Ground (dc)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LVL

DYN

LVL

DYN

LVL

REF1 clock (differential reference when in differential mode)

REF2 clock (not available in differential mode)

Selected reference to PLL (differential reference when in differential mode)

Unselected reference to PLL (not available in differential mode)

Status of selected reference (status of differential reference); active high

Status of unselected reference (not available in differential mode); active high

Status of REF1 frequency (active high)

Status of REF2 frequency (active high)

(Status of REF1 frequency) AND (status of REF2 frequency)

(DLD) AND (status of selected reference) AND (status of CLK)

Status of CLK frequency (active high)

Selected reference (low = REF1, high = REF2)

Digital lock detect (DLD); active high

Holdover active (active high)

Not available; do not use

VS (PLL supply)

REF1 clock

REF2 clock

(differential reference when in differential mode)

(not available in differential mode)

Selected reference to PLL

(differential reference when in differential mode)

Unselected reference to PLL

(not available when in differential mode)

Status of selected reference (status of differential reference); active low

Status of unselected reference (not available in differential mode); active low

Status of REF1 frequency (active low)

Status of REF2 frequency (active low)

(Status of REF1 frequency) AND (status of REF2 frequency)

(DLD) AND (status of selected reference) AND (status of CLK)

Status of CLK frequency (active low)

Selected reference (low = REF2, high = REF1)

Digital lock detect (DLD); active low

Holdover active (active low)

Not available; do not use

0x01B

7

6

5

CLK frequency

monitor

Enables or disables CLK frequency monitor.

0: disables CLK frequency monitor (default).

1: enables CLK frequency monitor.

REFIN

Enables or disables REF2 frequency monitor.

REF2 (

)

frequency

monitor

0: disables REF2 frequency monitor (default).

1: enables REF2 frequency monitor.

REF1 (REFIN)

frequency

monitor

REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs (as selected

by differential reference mode).

0: disables REF1 (REFIN) frequency monitor (default).

1: enables REF1 (REFIN) frequency monitor.

Rev. A | Page 56 of 76

AD9516-5

Reg.

Addr.

(Hex)

Bits

Name

Description

[4:0] REFMON pin

control

Selects the signal that is connected to the REFMON pin.

Level or

Dynamic

4

0

1

3

0

1

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Signal

LVL

DYN

LVL

DYN

LVL

Signal at REFMON Pin

Ground (dc) (default)

REF1 clock (differential reference when in differential mode)

REF2 clock (not available in differential mode)

Selected reference to PLL (differential reference when in differential mode)

Unselected reference to PLL (not available in differential mode)

Status of selected reference (status of differential reference); active high

Status of unselected reference (not available in differential mode); active high

Status of REF1 frequency (active high)

Status of REF2 frequency (active high)

(Status of REF1 frequency) AND (status of REF2 frequency)

(DLD) AND (status of selected reference) AND (status of CLK)

Status of CLK frequency (active high)

Selected reference (low = REF1, high = REF2)

Digital lock detect (DLD); active low

Holdover active (active high)

LD pin comparator output (active high)

VS (PLL supply)

REF1 clock

REF2 clock

(differential reference when in differential mode)

(not available in differential mode)

Selected reference to PLL

(differential reference when in differential mode)

Unselected reference to PLL

(not available when in differential mode)

Status of selected reference (status of differential reference); active low

Status of unselected reference (not available in differential mode); active low

Status of REF1 frequency (active low)

Status of REF2 frequency (active low)

(Status of REF1 frequency) AND (status of REF2 frequency)

(DLD) AND (status of selected reference) AND (status of CLK)

Status of CLK frequency (active low)

Selected reference (low = REF2, high = REF1)

Digital lock detect (DLD); active low

Holdover active (active low)

LD pin comparator output (active low)

0x01C

7

6

5

Disable

switchover

deglitch

Disables or enables the switchover deglitch circuit.

0: enables switchover deglitch circuit (default).

1: disables switchover deglitch circuit.

If Register 0x01C[5] = 0, selects reference for PLL.

0: select REF1 (default).

Select REF2

1: select REF2.

Use REF_SEL pin

If Register 0x01C[4] = 0 (manual), sets method of PLL reference selection.

0: uses Register 0x01C[6] (default).

1: uses REF_SEL pin.

4

3

2

Reserved

0: default.

REF2

power-on

This bit turns the REF2 power on.

0: REF2 power off (default).

1: REF2 power on.

1

0

REF1

power-on

This bit turns the REF1 power on.

0: REF1 power off (default).

1: REF1 power on.

Differential

reference

Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic

reference switchover or REF1 and REF2 to work.

0: single-ended reference mode (default).

1: differential reference mode.

Rev. A | Page 57 of 76

AD9516-5

Reg.

Addr.

(Hex)

Bits

Name

Description

0x01D

4

PLL status

register disable

Disables the PLL status register readback.

0: PLL status register enable (default).

1: PLL status register disable.

3

LD pin

comparator

enable

Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When in

the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if the

PLL was previously in a locked state (see Figure 41). Otherwise, this function can be used with the REFMON and STATUS

pins to monitor the voltage on the LD pin.

0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true/high (default).

1: enables LD pin comparator.

2

1

Holdover enable Along with Register 0x01D[0], enables the holdover function.

0: holdover disabled (default).

1: holdover enabled.

External

holdover control

SYNC

pin. (This disables the internal holdover mode.)

Enables the external hold control through the

0: automatic holdover mode—holdover controlled by automatic holdover circuit (default).

SYNC

1: external holdover mode—holdover controlled by

pin.

0

5

4

3

Holdover enable Along with Register 0x01D[2], enables the holdover function.

0: holdover disabled (default).

1: holdover enabled.

0x01F

Holdover active

REF2 selected

Read-only register. Indicates if the part is in the holdover state (see Figure 41). This is not the same as holdover enabled.

0: not in holdover.

1: holdover state active.

Read-only register. Indicates which PLL reference is selected as the input to the PLL.

0: REF1 selected (or differential reference if in differential mode).

1: REF2 selected.

CLK frequency >

threshold

Read-only register. Indicates if the CLK frequency is greater than the threshold (see Table 12: REF1, REF2, and CLK

frequency status monitor).

0: CLK frequency is less than the threshold.

1: CLK frequency is greater than the threshold.

2

1

0

REF2

frequency >

threshold

Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by

Register 0x01A[6].

0: REF2 frequency is less than threshold frequency.

1: REF2 frequency is greater than threshold frequency.

REF1

frequency >

threshold

Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by

Register 0x01A[6].

0: REF1 frequency is less than threshold frequency.

1: REF1 frequency is greater than threshold frequency.

Read-only register. Digital lock detect.

0: PLL is not locked.

Digital

lock detect

1: PLL is locked.

Rev. A | Page 58 of 76

AD9516-5

Table 50. Fine Delay Adjust—OUT6 to OUT9

Reg.

Addr.

(Hex)

Bits Name

OUT6 delay

bypass

Description

0x0A0

0

Bypasses or uses the delay function.

0: uses the delay function.

1: bypasses the delay function (default).

0x0A1 [5:3] OUT6 ramp

capacitors

Selects the number of ramp capacitors used by the delay function. The combination of the number of

capacitors and the ramp current sets the full-scale delay.

5

0

1

4

0

1

0

1

3

0

1

0

1

0

1

0

1

Number of Capacitors

4 (default)

3

2

3

2

1

[2:0] OUT6 ramp

current

Ramp current for the delay function. The combination of the number of capacitors and the ramp current

sets the full-scale delay.

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Current (μA)

200 (default)

400

600

800

1000

1200

1400

1600

0x0A2 [5:0] OUT6 delay

fraction

Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay.

Only delay values of up to 47 decimals (101111b; 0x02F) are supported (default: 0x00).

0x0A3

0

OUT7 delay

bypass

Bypasses or uses the delay function.

0: uses the delay function.

1: bypasses the delay function (default).

0x0A4 [5:3] OUT7 ramp

capacitors

Selects the number of ramp capacitors used by the delay function. The combination of the number of the

capacitors and the ramp current sets the full-scale delay.

5

0

1

4

0

1

0

1

3

0

1

0

1

0

1

0

1

Number of Capacitors

4 (default)

3

2

3

2

1

Rev. A | Page 59 of 76

AD9516-5

Reg.

Addr.

(Hex)

Bits Name

Description

0x0A4 [2:0] OUT7 ramp

current

Ramp current for the delay function. The combination of the number of capacitors and the ramp

current sets the full-scale delay.

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Current (μA)

200 (default)

400

600

800

1000

1200

1400

1600

0x0A5 [5:0] OUT7 delay

fraction

Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay.

Only delay values of up to 47 decimals (101111b; 0x02F) are supported (default: 0x00).

0x0A6

0

OUT8 delay

bypass

Bypasses or uses the delay function.

0: uses the delay function.

1: bypasses the delay function (default).

0x0A7 [5:3] OUT8 ramp

capacitors

Selects the number of ramp capacitors used by the delay function. The combination of the number of

capacitors and the ramp current sets the full-scale delay.

5

0

1

4

0

1

0

1

3

0

1

0

1

0

1

0

1

Number of Capacitors

4 (default)

3

2

3

2

1

[2:0] OUT8 ramp

current

Ramp current for the delay function. The combination of the number of capacitors and the ramp

current sets the full-scale delay.

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Current (μA)

200 (default)

400

600

800

1000

1200

1400

1600

0x0A8 [5:0] OUT8 delay

fraction

Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay.

Only delay values of up to 47 decimals (101111b; 0x02F) are supported (default: 0x00).

0x0A9 [0]

OUT9 delay

bypass

Bypasses or uses the delay function.

0: uses the delay function.

1: bypasses the delay function (default).

Rev. A | Page 60 of 76

AD9516-5

Reg.

Addr.

(Hex)

Bits Name

Description

0x0AA [5:3] OUT9 ramp

capacitors

Selects the number of ramp capacitors used by the delay function. The combination of the number of

capacitors and the ramp current sets the full-scale delay.

5

0

1

4

0

1

0

1

3

0

1

0

1

0

1

0

1

Number of Capacitors

4 (default)

3

2

3

2

1

[2:0] OUT9 ramp

current

Ramp current for the delay function. The combination of the number of capacitors and the ramp

current sets the full-scale delay.

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Current Value (μA)

200 (default)

400

600

800

1000

1200

1400

1600

0x0AB [5:0] OUT9 delay

fraction

Selects the fraction of the full-scale delay desired (6-bit binary). A setting of 000000b gives zero delay.

Only delay values of up to 47 decimals (101111b; 0x02F) are supported (default: 0x00).

Table 51. LVPECL Outputs

Reg.

Addr.

(Hex) Bits Name

Description

0x0F0

4

OUT0 invert

Sets the output polarity.

0: noninverting (default).

1: inverting.

[3:2] OUT0 LVPECL Sets the LVPECL output differential voltage (V_OD).

differential

3

0

1

2

0

1

0

1

V_OD(mV)

400

600

780 (default)

960

voltage

[1:0] OUT0

LVPECL power-down modes.

power-down

1

0

1

0

1

0

1

Mode

Output

On

Off

Normal operation (default)

Partial power-down, reference on; use only if there are no external load resistors

Partial power-down, reference on; safe LVPECL power-down

Total power-down, reference off; use only if there are no external load resistors

Rev. A | Page 61 of 76

AD9516-5

Reg.

Addr.

(Hex) Bits Name

Description

0x0F1

0x0F2

0x0F3

4

OUT1 invert

Sets the output polarity.

0: noninverting (default).

1: inverting.

[3:2] OUT1 LVPECL Sets the LVPECL output differential voltage (V_OD).

differential

3

0

1

2

0

1

0

1

V_OD(mV)

400

600

780 (default)

960

voltage

[1:0] OUT1

LVPECL power-down modes.

power-down

1

0

1

0

1

0

1

Mode

Output

On

Off

Normal operation

Partial power-down, reference on; use only if there are no external load resistors

Partial power-down, reference on; safe LVPECL power-down (default)

Total power-down, reference off; use only if there are no external load resistors

4

OUT2 invert

Sets the output polarity.

0: noninverting (default).

1: inverting.

[3:2] OUT2 LVPECL Sets the LVPECL output differential voltage (V_OD).

differential

3

0

1

2

0

1

0

1

V_OD(mV)

400

600

780 (default)

960

voltage

[1:0] OUT2

LVPECL power-down modes.

power-down

1

0

1

0

1

0

1

Mode

Output

On

Off

Normal operation (default)

Partial power-down, reference on; use only if there are no external load resistors

Partial power-down, reference on, safe LVPECL power-down

Total power-down, reference off; use only if there are no external load resistors

4

OUT3 invert

Sets the output polarity.

0: noninverting (default).

1: inverting.

[3:2] OUT3 LVPECL Sets the LVPECL output differential voltage (V_OD).

differential

3

0

1

2

0

1

0

1

V_OD(mV)

400

600

780 (default)

960

voltage

[1:0] OUT3

LVPECL power-down modes.

power-down

1

0

1

0

1

0

1

Mode

Output

On

Off

Normal operation

Partial power-down, reference on; use only if there are no external load resistors

Partial power-down, reference on, safe LVPECL power-down (default)

Total power-down, reference off; use only if there are no external load resistors

Rev. A | Page 62 of 76

AD9516-5

Reg.

Addr.

(Hex) Bits Name

Description

0x0F4

4

OUT4 invert

Sets the output polarity.

0: noninverting (default).

1: inverting.

[3:2] OUT4 LVPECL Sets the LVPECL output differential voltage (V_OD).

differential

3

0

1

2

0

1

0

1

V_OD(mV)

400

600

780 (default)

960

voltage

[1:0] OUT4

LVPECL power-down modes.

power-down

1

0

1

0

1

0

1

Mode

Output

On

Off

Normal operation

Partial power-down, reference on; use only if there are no external load resistors

Partial power-down, reference on, safe LVPECL power-down

Total power-down, reference off; use only if there are no external load resistors

OUT5 invert

0x0F5

4

Sets the output polarity.

0: noninverting (default).

1: inverting.

[3:2] OUT5 LVPECL Sets the LVPECL output differential voltage (V_OD).

differential

voltage

3

0

1

2

0

1

0

1

V_OD(mV)

400

600

780 (default)

960

OUT5

power-down

[1:0]

LVPECL power-down modes.

1

0

1

0

1

0

1

Mode

Output

On

Off

Normal operation

Partial power-down, reference on; use only if there are no external load resistors

Partial power-down, reference on, safe LVPECL power-down (default)

Total power-down, reference off; use only if there are no external load resistors

Rev. A | Page 63 of 76

AD9516-5

Table 52. LVDS/CMOS Outputs

Reg.

Addr.

(Hex) Bits Name

Description

0x140 [7:5] OUT6 output polarity

In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.

In LVDS mode, only Bit 5 determines LVDS polarity.

7

0

1

0

1

6

0

1

0

1

0

1

0

1

5

0

1

OUT6A (CMOS)

Noninverting

Inverting

Noninverting

OUT6B (CMOS)

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

OUT6 (LVDS)

Noninverting

Noninverting (default)

Noninverting

Inverting

4

3

OUT6 CMOS B

In CMOS mode, turns on/off the CMOS B output. This has no effect in LVDS mode.

0: turns off the CMOS B output (default).

1: turns on the CMOS B output.

OUT6 select LVDS/CMOS

Selects LVDS or CMOS logic levels.

0: LVDS (default).

1: CMOS.

[2:1] OUT6 LVDS output current

Sets output current level in LVDS mode. This has no effect in CMOS mode.

2

0

1

0

1

0

1

Current (mA)

Recommended Termination (Ω)

1.75

3.5

5.25

7

100

100 (default)

50

0

OUT6 power-down

Power-down output (LVDS/CMOS).

0: powers on (default).

1: powers off.

0x141 [7:5] OUT7 output polarity

In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.

In LVDS mode, only Bit 5 determines LVDS polarity.

7

0

1

0

1

6

0

1

0

1

0

1

0

1

5

0

1

OUT7A (CMOS)

Noninverting

Inverting

Noninverting

OUT7B (CMOS)

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

OUT7 (LVDS)

Noninverting

Noninverting (default)

Noninverting

Inverting

4

3

OUT7 CMOS B

In CMOS mode, turns on/off the CMOS B output. This has no effect in LVDS mode.

0: turns off the CMOS B output (default).

1: turns on the CMOS B output.

OUT7 select LVDS/CMOS

Selects LVDS or CMOS logic levels.

0: LVDS (default).

1: CMOS.

[2:1] OUT7 LVDS output current

Sets output current level in LVDS mode. This has no effect in CMOS mode.

2

0

1

0

1

0

1

Current (mA)

Recommended Termination (Ω)

1.75

3.5

5.25

7

100

100 (default)

50

Rev. A | Page 64 of 76

AD9516-5

Reg.

Addr.

(Hex) Bits Name

Description

0

OUT7 power-down

Power-down output (LVDS/CMOS).

0: powers on.

1: powers off (default).

0x142 [7:5] OUT8 output polarity

In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.

In LVDS mode, only Bit 5 determines LVDS polarity.

7

0

1

0

1

6

0

1

0

1

0

1

0

1

5

0

1

OUT8A (CMOS)

Noninverting

Inverting

Noninverting

OUT8B (CMOS)

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

OUT8 (LVDS)

Noninverting

Noninverting (default)

Noninverting

Inverting

4

3

OUT8 CMOS B

In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode.

0: turns off the CMOS B output (default).

1: turns on the CMOS B output.

OUT8 select LVDS/CMOS

Selects LVDS or CMOS logic levels.

0: LVDS (default).

1: CMOS.

[2:1] OUT8 LVDS output current

Sets output current level in LVDS mode. This has no effect in CMOS mode.

2

0

1

0

1

0

1

Current (mA)

Recommended Termination (Ω)

1.75

3.5

5.25

7

100

100 (default)

50

0

OUT8 power-down

Power-down output (LVDS/CMOS).

0: powers on (default).

1: powers off.

0x143 [7:5] OUT9 output polarity

In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.

In LVDS mode, only Bit 5 determines LVDS polarity.

7

0

1

0

1

6

0

1

0

1

0

1

0

1

5

0

1

OUT9A (CMOS)

Noninverting

Inverting

Noninverting

OUT9B (CMOS)

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

OUT9 (LVDS)

Noninverting

Noninverting (default)

Noninverting

Inverting

4

3

OUT9 CMOS B

In CMOS mode, turns on/off the CMOS B output. This has no effect in LVDS mode.

0: turns off the CMOS B output (default).

1: turns on the CMOS B output.

Selects LVDS or CMOS logic levels.

0: LVDS (default).

OUT9 select LVDS/CMOS

1: CMOS.

Rev. A | Page 65 of 76

AD9516-5

Reg.

Addr.

(Hex) Bits Name

Description

[2:1] OUT9 LVDS output current

Sets output current level in LVDS mode. This has no effect in CMOS mode.

2

0

1

0

1

0

1

Current (mA)

Recommended Termination (Ω)

1.75

3.5

5.25

7

100

100 (default)

50

[0]

OUT9 power-down

Power-down output (LVDS/CMOS).

0: powers on.

1: powers off (default).

Table 53. LVPECL Channel Dividers

Reg.

Addr.

(Hex)

Bits Name

Description

0x190

[7:4] Divider 0 low cycles

Number of clock cycles (minus 1) of the Divider 0 input during which the Divider 0 output

stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).

[3:0] Divider 0 high cycles

Number of clock cycles (minus 1) of the Divider 0 input during which the Divider 0 output

stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).

0x191

7

6

5

Divider 0 bypass

Divider 0 nosync

Divider 0 force high

Bypasses and powers down the divider; routes input to the divider output.

0: uses the divider.

1: bypasses the divider (default).

No sync.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Forces divider output to high. This operation requires that the Divider 0 nosync bit (Bit 6) also

be set. This bit has no effect if the Divider 0 bypass bit (Bit 7) is set.

0: normal operation (default).

1: divider output forced to the setting of the Divider 0 start high bit.

Selects clock output to start high or start low.

0: starts low (default).

4

Divider 0 start high

1: starts high.

[3:0] Divider 0 phase offset

Phase offset (default: 0x0).

0x192

1

Divider 0 direct to output Connects OUT0 and OUT1 to Divider 0 or directly to CLK input.

0: OUT0 and OUT1 are connected to Divider 0 (default).

1: If Register 0x1E1[0] = 0b, the CLK is routed directly to OUT0 and OUT1.

If Register 0x1E1[0] = 1b, there is no effect.

0

Divider 0 DCCOFF

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

0x193

0x194

[7:4] Divider 1 low cycles

[3:0] Divider 1 high cycles

Number of clock cycles (minus 1) of the Divider 1 input during which the Divider 1 output stays

low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0xB).

Number of clock cycles (minus 1) of the Divider 1 input during which the Divider 1 output stays

high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0xB).

7

Divider 1 bypass

Bypasses and powers down the divider; routes input to divider output.

0: uses divider (default).

1: bypasses divider.

6

Divider 1 nosync

No sync.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Rev. A | Page 66 of 76

AD9516-5

Reg.

Addr.

(Hex)

Bits Name

Description

5

Divider 1 force high

Forces divider output to high. This operation requires that the Divider 1 nosync bit (Bit 6) also

be set. This bit has no effect if the Divider 1 bypass bit (Bit 7) is set.

0: normal operation (default).

1: divider output forced to the setting of the Divider 1 start high bit.

Selects clock output to start high or start low.

0: starts low (default).

4

Divider 1 start high

1: starts high.

[3:0] Divider 1 phase offset

Phase offset (default: 0x0).

0x195

1

Divider 1 direct to output Connects OUT2 and OUT3 to Divider 1 or directly to CLK input.

0: OUT2 and OUT3 are connected to Divider 1 (default).

1: If Register 0x1E1[0] = 0b, the CLK is routed directly to OUT2 and OUT3.

If Register 0x1E1[0] = 1b, this has no effect.

0

Divider 1 DCCOFF

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

0x196

0x197

[7:4] Divider 2 low cycles

[3:0] Divider 2 high cycles

Number of clock cycles (minus 1) of the Divider 2 input during which the Divider 2 output stays

low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).

Number of clock cycles (minus 1) of the Divider 2 input during which the Divider 2 output stays

high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).

7

6

5

Divider 2 bypass

Divider 2 nosync

Divider 2 force high

Bypasses and powers down the divider; route input to divider output.

0: uses divider (default).

1: bypasses divider.

No sync.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Forces divider output to high. This operation requires that the Divider 2 nosync bit (Bit 6) also

be set. This bit has no effect if the Divider 2 bypass bit (Bit 7) is set.

0: normal operation (default).

1: divider output forced to the setting of the Divider 2 start high bit.

Selects clock output to start high or start low.

0: starts low (default).

4

Divider 2 start high

1: starts high.

[3:0] Divider 2 phase offset

Phase offset (default: 0x0).

0x198

1

Divider 2 direct to output Connects OUT4 and OUT5 to Divider 2 or directly to CLK input.

0: OUT4 and OUT5 are connected to Divider 2 (default).

1: if 0x1E1[0] = 0b, the CLK is routed directly to OUT4 and OUT5.

If 0x1E1[0] = 1b, there is no effect.

0

Divider 2 DCCOFF

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

Rev. A | Page 67 of 76

AD9516-5

Table 54. LVDS/CMOS Channel Dividers

Reg.

Addr.

(Hex)

Bits

Name

Description

0x199 [7:4] Low Cycles Divider 3.1

Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output

stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).

[3:0] High Cycles Divider 3.1

Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output

stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).

0x19A [7:4] Phase Offset Divider 3.2

[3:0] Phase Offset Divider 3.1

Refers to LVDS/CMOS channel divider function description (default: 0x0).

0x19B [7:4] Low Cycles Divider 3.2

Number of clock cycles (minus 1) of the Divider 3.2 input during which the Divider 3.2 output

stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).

[3:0] High Cycles Divider 3.2

Number of clock cycles (minus 1) of the Divider 3.2 input during which the Divider 3.2 output

stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).

0x19C

5

4

3

2

1

0

Bypass Divider 3.2

Bypass Divider 3.1

Divider 3 nosync

Bypasses (and powers down) 3.2 divider logic, routes clock to 3.2 output.

0: does not bypass (default).

1: bypasses.

Bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output.

0: does not bypass (default).

1: bypasses.

No sync.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Forces Divider 3 output high. Requires that the Divider 3 nosync bit (Bit 3) also be set.

0: forces low (default).

Divider 3 force high

Start High Divider 3.2

Start High Divider 3.1

Divider 3 DCCOFF

1: forces high.

Divider 3.2 starts high/low.

0: starts low (default).

1: starts high.

Divider 3.1 starts high/low.

0: starts low (default).

1: starts high.

0x19D

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

0x19E [7:4] Low Cycles Divider 4.1

[3:0] High Cycles Divider 4.1

Number of clock cycles (minus 1) of the Divider 4.1 input during which the Divider 4.1 output

stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).

Number of clock cycles (minus 1) of the Divider 4.1 input during which the Divider 4.1 output

stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).

0x19F [7:4] Phase Offset Divider 4.2

[3:0] Phase Offset Divider 4.1

Refers to LVDSCMOS channel divider function description (default: 0x0).

0x1A0 [7:4] Low Cycles Divider 4.2

Number of clock cycles (minus 1) of the Divider 4.2 input during which the Divider 4.2 output

stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).

[3:0] High Cycles Divider 4.2

Number of clock cycles (minus 1) of the Divider 4.2 input during which the Divider 4.2 output

stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).

0x1A1

5

4

Bypass Divider 4.2

Bypass Divider 4.1

Bypasses (and powers down) 4.2 divider logic, routes clock to 4.2 output.

0: does not bypass (default).

1: bypasses.

Bypasses (and powers down) 4.1 divider logic, routes clock to 4.1 output.

0: does not bypass (default).

1: bypasses.

3

Divider 4 nosync

No sync.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Rev. A | Page 68 of 76

AD9516-5

Reg.

Addr.

(Hex)

Bits

Name

Description

2

Divider 4 force high

Forces Divider 4 output high. Requires that the Divider 4 nosync bit (Bit 3) also be set.

0: forces low (default).

1: forces high.

1

0

Start High Divider 4.2

Start High Divider 4.1

Divider 4 DCCOFF

Divider 4.2 starts high/low.

0: starts low (default).

1: starts high.

Divider 4.1 starts high/low.

0: starts low (default).

1: starts high.

0x1A2

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

Table 55. VCO Divider and CLK Input

Reg.

Addr.

(Hex) Bits

Name

Description

0x1E0 [2:0]

VCO divider

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Divide

2

3

4 (default)

5

6

Output static

0x1E1

4

0

Power-down clock input

section

Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).

0: normal operation (default).

1: powers down.

Bypass VCO divider

Bypasses or uses the VCO divider.

0: uses VCO divider (default).

1: bypasses VCO divider.

Table 56. System

Reg.

Addr.

(Hex) Bits

Name

Description

230

2

1

0

Power-down SYNC

Powers down the sync function.

0: normal operation of the sync function (default).

1: powers down the SYNC circuitry.

Power-down distribution Powers down the reference for distribution section.

reference

0: normal operation of the reference for the distribution section (default).

1: powers down the reference for the distribution section.

Soft SYNC

The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit is

reversed; that is, a high level forces selected channels into a predetermined static state, and a 1-

to-0 transition triggers a SYNC.

0: same as SYNC high (default).

1: same as SYNC low.

Rev. A | Page 69 of 76

AD9516-5

Table 57. Update All Registers

Reg.

Addr.

(Hex)

Bits

Name

Description

0x232

0

Update all registers

This bit must be set to 1 to transfer the contents of the buffer registers into the active registers,

which happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to

be set back to 0.

1: updates all active registers to the contents of the buffer registers (self-clearing).

Rev. A | Page 70 of 76

AD9516-5

APPLICATIONS INFORMATION

Considering an ideal ADC of infinite resolution, where the step

size and quantization error can be ignored, the available SNR

can be expressed approximately by

FREQUENCY PLANNING USING THE AD9516

The AD9516 is a highly flexible PLL. When choosing the PLL

settings and version of the AD9516, keep in mind the following

guidelines.

⎛

⎞

1

⎜

⎟

SNR(dB) = 20× log

2π × f _A× t_J

⎝

⎠

The AD9516 has the following four frequency dividers: the

reference (or R) divider, the feedback (or N) divider, the VCO

divider, and the channel divider. When trying to achieve a

particularly difficult frequency divide ratio requiring a large

amount of frequency division, some of the frequency division

can be done by either the VCO divider or the channel divider,

thus allowing a higher phase detector frequency and more

flexibility in choosing the loop bandwidth.

where:

f_Ais the highest analog frequency being digitized.

t_Jis the rms jitter on the sampling clock.

Figure 58 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

110

18

1

SNR = 20log

2πf_At_J

100

90

80

70

60

50

40

30

Within the AD9516 family, lower VCO frequencies generally

result in slightly lower jitter. The difference in integrated jitter

(from 12 kHz to 20 MHz offset) for the same output frequency is

usually less than 150 fs over the entire VCO frequency range

(1.45 GHz to 2.95 GHz) of the AD9516 family. If the desired

frequency plan can be achieved with a version of the AD9516

that has a lower VCO frequency, choosing the lower frequency

part results in the lowest phase noise and the lowest jitter. However,

choosing a higher VCO frequency may result in more flexibility

in frequency planning.

16

14

12

10

8

6

Choosing a nominal charge pump current in the middle of the

allowable range as a starting point allows the designer to increase or

decrease the charge pump current and, thus, allows the designer

to fine-tune the PLL loop bandwidth in either direction.

10

100

1k

f_A(MHz)

Figure 58. SNR and ENOB vs. Analog Input Frequency

See the AN-756 Application Note, Sampled Systems and the Effects

of Clock Phase Noise and Jitter; and the AN-501 Application Note,

Aperture Uncertainty and ADC System Performance, at

www.analog.com.

ADIsimCLK is a powerful PLL modeling tool that can be

downloaded from www.analog.com. It is a very accurate tool for

determining the optimal loop filter for a given application.

USING THE AD9516 OUTPUTS FOR ADC CLOCK

APPLICATIONS

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. (Distributing a single-ended clock on a noisy PCB

may result in coupled noise on the sample clock. Differential

distribution has inherent common-mode rejection that can

provide superior clock performance in a noisy environment.)

The AD9516 features both LVPECL and LVDS outputs that

provide differential clock outputs, which enable clock solutions that

maximize converter SNR performance. The input requirements of

the ADC (differential or single-ended, logic level, and termination)

should be considered when selecting the best clocking/converter

solution.

Any high speed ADC is extremely sensitive to the quality of its

sampling clock. An ADC can be thought of as a sampling mixer,

and any noise, distortion, or timing jitter on the clock is combined

with the desired signal at the analog-to-digital output. Clock

integrity requirements scale with the analog input frequency

and resolution, with higher analog input frequency applications

at ≥14-bit resolution being the most stringent. The theoretical

SNR of an ADC is limited by the ADC resolution and the jitter

on the sampling clock.

Rev. A | Page 71 of 76

AD9516-5

LVPECL Y-termination is an elegant termination scheme that

uses the fewest components and offers both odd- and even-mode

impedance matching. Even-mode impedance matching is an

important consideration for closely coupled transmission lines

at high frequencies. Its main drawback is that it offers limited

flexibility for varying the drive strength of the emitter-follower

LVPECL driver. This can be an important consideration when

driving long trace lengths but is usually not an issue. In the case

shown in Figure 60, where V_{S_LVPECL}= 2.5 V, the 50 Ω termination

resistor connected to ground should be changed to 19 Ω.

LVPECL CLOCK DISTRIBUTION

The LVPECL outputs of the AD9516 provide the lowest jitter clock

signals that are available from the AD9516. The LVPECL outputs

(because they are open emitter) require a dc termination to bias

the output transistors. The simplified equivalent circuit in

Figure 47 shows the LVPECL output stage.

In most applications, an LVPECL far-end Thevenin termination

(see Figure 59) or Y-termination (see Figure 60) is recommended.

In each case, the V_Sof the receiving buffer should match the

V_{S_LVPECL}. If it does not match, ac coupling is recommended (see

Figure 61).

Thevenin-equivalent termination uses a resistor network to provide

50 Ω termination to a dc voltage that is below V_OLof the LVPECL

driver. In this case, V_{S_LVPECL}on the AD9516 should equal V_Sof

the receiving buffer. Although the resistor combination shown

in Figure 60 results in a dc bias point of V_{S_LVPECL}− 2 V, the actual

common-mode voltage is V_{S_LVPECL}− 1.3 V because additional

current flows from the AD9516 LVPECL driver through the pull-

down resistor.

The resistor network is designed to match the transmission line

impedance (50 Ω) and the switching threshold (V_S− 1.3 V).

V

S_DRV

V

S

S_LVPECL

LVPECL

127Ω

50Ω

SINGLE-ENDED

(NOT COUPLED)

LVPECL

The circuit is identical when V_{S_LVPECL}= 2.5 V, except that the

pull-down resistor is 62.5 Ω and the pull-up resistor is 250 Ω.

50Ω

83Ω

LVDS CLOCK DISTRIBUTION

The AD9516 provides four clock outputs (OUT6 to OUT9) that

are selectable as either CMOS or LVDS level outputs. LVDS is a

differential output option that uses a current mode output stage.

The nominal current is 3.5 mA, which yields a 350 mV output

swing across a 100 Ω resistor. An output current of 7 mA is also

available in cases where a larger output swing is required. The

LVDS output meets or exceeds all ANSI/TIA/EIA-644

specifications.

Figure 59. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination

V

= 3.3V

S_LVPECL

LVPECL

S

Z

= 50Ω

0

50Ω

LVPECL

0

A recommended termination circuit for the LVDS outputs is

shown in Figure 62.

Figure 60. DC-Coupled 3.3 V LVPECL Y-Termination

V

S

V

S

S_LVPECL

0.1nF

100Ω

LVDS

DIFFERENTIAL (COUPLED)

100Ω DIFFERENTIAL

(COUPLED)

TRANSMISSION LINE

100Ω

LVPECL

0.1nF

Figure 62. LVDS Output Termination

200Ω

See the AN-586 Application Note, LVDS Data Outputs for High-

Speed Analog-to-Digital Converters for more information on LVDS.

Figure 61. AC-Coupled LVPECL with Parallel Transmission Line

Rev. A | Page 72 of 76

AD9516-5

60.4Ω

(1.0 INCH)

CMOS CLOCK DISTRIBUTION

10Ω

CMOS

The AD9516 provides four clock outputs (OUT6 to OUT9)

that are selectable as either CMOS or LVDS level outputs. When

selected as CMOS, each output becomes a pair of CMOS outputs,

each of which can be individually turned on or off and set as

noninverting or inverting. These outputs are 3.3 V CMOS

compatible.

MICROSTRIP

Figure 63. Series Termination of CMOS Output

Termination at the far end of the PCB trace is a second option.

The CMOS outputs of the AD9516 do not supply enough current

to provide a full voltage swing with a low impedance resistive, far-

end termination, as shown in Figure 64. The far-end termination

network should match the PCB trace impedance and provide the

desired switching point. The reduced signal swing may still meet

receiver input requirements in some applications. This can be

useful when driving long trace lengths on less critical nets.

Whenever single-ended CMOS clocking is used, some general

guidelines should be followed.

Point-to-point nets should be designed such that a driver has

only one receiver on the net, if possible. This allows for simple

termination schemes and minimizes ringing due to possible

mismatched impedances on the net. Series termination at the

source is generally required to provide transmission line matching

and/or to reduce current transients at the driver. The value of

the resistor is dependent on the board design and timing

requirements (typically 10 Ω to 100 Ω is used). CMOS outputs

are also limited in terms of the capacitive load or trace length

that they can drive. Typically, trace lengths less than 3 inches

are recommended to preserve signal rise/fall times and preserve

signal integrity.

V

S

100Ω

50Ω

10Ω

CMOS

Figure 64. CMOS Output with Far-End Termination

Because of the limitations of single-ended CMOS clocking,

consider using differential outputs when driving high speed

signals over long traces. The AD9516 offers both LVPECL and

LVDS outputs that are better suited for driving long traces where

the inherent noise immunity of differential signaling provides

superior performance for clocking converters.

Rev. A | Page 73 of 76

AD9516-5

OUTLINE DIMENSIONS

0.60 MAX

9.00

BSC SQ

0.60

MAX

PIN 1

INDICATOR

64

49

1

48

PIN 1

INDICATOR

0.50

BSC

6.35

6.20 SQ

6.05

8.75

BSC SQ

TOP VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.50

0.40

0.30

33

32

16

17

0.25 MIN

7.50

REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

0.30

0.23

0.18

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 65. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +85°C

Package Description

Package Option

CP-64-4

AD9516-5BCPZ

AD9516-5BCPZ-REEL7

AD9516-5/PCBZ

64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. A | Page 74 of 76

AD9516-5

NOTES

Rev. A | Page 75 of 76

AD9516-5

NOTES

registered trademarks are the property of their respective owners.

D07972-0-8/11(A)

Rev. A | Page 76 of 76


型号：	AD9516-5BCPZ
厂家：	ADI
描述：	14-Output Clock Generator 14路输出时钟发生器时钟发生器
文件：	总76页 (文件大小：1131K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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