AD9525BCPZ-REEL7_技术文档

Low Jitter Clock Generator

with Eight LVPECL Outputs

Data Sheet

AD9525

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Integrated ultralow noise synthesizer

8 differential 3.6 GHz LVPECL outputs and 1 LVPECL SYNC

output or 2 CMOS SYNC outputs

2 differential reference inputs and 1 single-ended reference

input

REFA

AD9525

REFB

SYNC_OUT

÷S

PLL

SYNC_OUT

OUT7

REFC

APPLICATIONS

OUT6

LTE and multicarrier GSM base stations

Clocking high speed ADCs, DACs

ATE and high performance instrumentation

40/100 Gb/sec OTN line side clocking

Cable/DOCSIS CMTS clocking

OUT5

OUT4

CLKIN

DIVIDERS

Test and measurement

OUT3

OUT2

OUT1

SPI CONTROL

OUT0

Figure 1.

GENERAL DESCRIPTION

The AD9525 is designed to support converter clock requirements

for long-term evolution (LTE) and multicarrier GSM base station

designs.

The AD9525 offers a dedicated output that can be used to provide

a programmable signal for resetting or synchronizing a data

converter. The output signal is activated by a SPI write.

The AD9525 provides a low power, multioutput, clock distribution

function with low jitter performance, along with an on-chip PLL

that can be used with an external VCO or VCXO. The VCO input

and eight LVPECL outputs can operate up to a frequency of

3.6 GHz. All outputs share a common divider that can provide

a division of 1 to 6.

The AD9525 is available in a 48-lead LFCSP and can be operated

from a single 3.3 V supply. The external VCXO or VCO can

have an operating voltage of up to 5.5 V.

The AD9525 operates over the extended industrial temperature

range of −40°C to +85°C.

Rev. 0

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Tel: 781.329.4700

Technical Support

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AD9525

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Absolute Maximum Ratings ......................................................... 12

Thermal Resistance.................................................................... 12

ESD Caution................................................................................ 12

Pin Configuration and Function Descriptions........................... 13

Typical Performance Characteristics ........................................... 15

Terminology.................................................................................... 18

Detailed Block Diagram ................................................................ 19

Theory of Operation ...................................................................... 20

Configuration of the PLL .......................................................... 20

Clock Distribution ..................................................................... 23

SYNC_OUT ................................................................................ 23

Reset Modes ................................................................................ 25

Power-Down Modes .................................................................. 26

Serial Control Port ......................................................................... 27

Pin Descriptions ......................................................................... 27

General Operation of Serial Control Port............................... 27

The Instruction Word (16 Bits)................................................ 28

MSB/LSB First Transfers ........................................................... 28

Control Registers ............................................................................ 31

Control Register Map Overview .............................................. 31

Register Map Descriptions............................................................ 33

Applications Information.............................................................. 45

Frequency Planning Using the AD9525.................................. 45

Using the AD9525 Outputs for ADC Clock Applications.... 45

LVPECL Clock Distribution..................................................... 46

SYNC_OUT Distribution ......................................................... 46

Outline Dimensions....................................................................... 47

Ordering Guide............................................................................... 47

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Conditions..................................................................................... 3

Supply Current.............................................................................. 3

Power Dissipation......................................................................... 3

REFA and REFB Input Characteristics...................................... 4

REFC Input Characteristics ........................................................ 4

Clock Inputs .................................................................................. 5

PLL Characteristics ...................................................................... 5

PLL Digital Lock Detect .............................................................. 6

Clock Outputs............................................................................... 6

Timing Characteristics ................................................................ 7

Clock Output Absolute Time Jitter (Clock Generation

Using External 122.88 MHz VCXO).......................................... 8

Clock Output Absolute Time Jitter (Clock Generation

Using External 1475 MHz VCO) ............................................... 8

Clock Output Absolute Time Jitter (Clock Generation

Using External 2.05 GHz VCO) ................................................. 9

Clock Output Absolute Time Jitter (Clock Generation

Using External 3 GHz VCO) ...................................................... 9

Clock Output Additive Phase Noise (Distribution Only;

Clock Input to Distribution Output, Including VCO

Divider).......................................................................................... 9

PD RESET

,

, and REF_SEL Pins................................................ 10

STATUS and REF_MON Pins .................................................. 10

Serial Control Port ..................................................................... 11

REVISION HISTORY

10/12—Revision 0: Initial Version

Rev. 0 | Page 2 of 48

Data Sheet

AD9525

SPECIFICATIONS

Typical is given for VDD3 = 3.3 V 5%; VDD3 ≤ VDD_CP ≤ 5.25 V; T_A= 25°C; OUT_RSET resistor = 4.12 kΩ; CP_RSET resistor (CPRSET) =

5.1 kΩ, unless otherwise noted. Minimum and maximum values are given over full VDD3 and T_A(−40°C to +85°C) variation as listed in Table 1.

REFA at 122.88 MHz, CLKIN frequency = 2949.12 MHz.

CONDITIONS

Table 1.

Parameter

Min

Typ Max

Unit

Test Conditions/Comments

SUPPLY VOLTAGE

VDD3

3.3

V

3.3 V 5%

VDD_CP

VDD3

5.25

4.12

5.1

V

Nominally 3.3 V to 5.0 V 5%

Sets internal biasing currents; connect to ground

OUT_RSET PIN RESISTOR

CP_RSET PIN RESISTOR (CPRSET RESISTOR)

kΩ

Sets internal CP current range, nominally 4.8 mA

(CP_LSB = 600 µA); actual current calculated by

CP_LSB = 3.06/CPRSET, connect to ground; CPRSET

range = 2.7 kΩ to10 kΩ

TEMPERATURE RANGE, T_A

−40

+25 +85

°C

SUPPLY CURRENT

Table 2.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

SUPPLY CURRENT FOR VDD3 and VDD_CP PINS

f_CLK= 2949.12 MHz; REFA and REFB enabled

at 122.88 MHz; R dividers = 2; M divider = 2;

PFD = 61.44 MHz; eight LVPECL outputs at

1474.56 MHz; LVPECL 780 mV mode

VDD3 (Pin 3, Pin 36, Pin 41, Pin 46), Total Supply

Voltage for Outputs

VDD3 (Pin 9), Supply Voltage for M Divider,

CLK Inputs and Distribution

310

98

369

107

mA

Outputs terminated with 50 Ω to VDD3 − 2 V

VDD_CP (Pin 13), Supply Voltage for Charge Pump

VDD3 (Pin 20), Supply Voltage for PLL

VDD3 (Pin 32), Supply Voltage for SYNC_OUT

6.6

53

45

7.6

63.4

54

mA

POWER DISSIPATION

Table 3.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

POWER DISSIPATION, CHIP

Does not include power dissipated in external

resistors; all LVPECL outputs terminated with

50 Ω to VDD3 − 2 V; LVPECL 780 mV mode

Power-On Default

Typical Operation 1

782

1.15

871

1.23

mW

W

No programming; default register values

f_CLK= 2949.12 MHz; REFA and REFB enabled

at 122.88 MHz; R dividers = 2; M divider = 2;

PFD = 61.44 MHz; eight LVPECL outputs at

1474.56 MHz

Typical Operation 2

1.17

1.25

W

f_CLK= 2949.12 MHz; PLL on; REFA enabled at

122.88 MHz; M divider = 1; PFD = 122.88MHz;

eight LVPECL outputs at 2949.12 MHz

PD Power-Down

51

56.4

19.1

mW

PD pin pulled low

PD Power-Down, Maximum Sleep

13.2

PD pin pulled low; power-down distribution

reference, Reg. 0x230[1] = 1b; note that powering

down distribution reference disables safe power-

down mode (see Power-Down Modes section)

VDD_CP Supply

22

25

mW

PLL operating; typical closed-loop configuration

Rev. 0 | Page 3 of 48

AD9525

Data Sheet

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

POWER DELTAS, INDIVIDUAL FUNCTIONS

M Divider On/Off

P Divider On/Off

B Divider On/Off

REFB On

Power delta when a function is enabled/disabled

M divider bypassed

P divider bypassed

B divider bypassed

Delta from powering down REFB differential input

5

3

16

15

254

8.7

5.7

23.1

25

mW

PLL On/Off

300.5 mW

PLL off to PLL on, normal operation; no reference

enabled

One Channel, One Driver

One Channel, Two Drivers

159

288

184

337

mW

No LVPECL output on to one LVPECL output on

at 2949.12 MHz; same output pair

No LVPECL output on to two LVPECL outputs on

at 2949.12 MHz; same output pair

REFA AND REFB INPUT CHARACTERISTICS

Table 4.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL MODE (REFA, REFA; REFB, REFB)

Differential mode (can accommodate single-

ended input by ac grounding unused input)

Input Frequency

0

500

MHz

Frequencies below ~1 MHz should be dc-coupled;

be careful to match self-bias voltage

Input Sensitivity

200

1.52 1.65

1.38 1.50

mV p-p Frequency at 122.88 MHz

Self-Bias Voltage, REFA and REFB

Input Resistance, REFA and REFB

1.78

1.61

4.9

V

Self-bias voltage of REFA and REFB inputs¹

4.5

4.9

4.7

5.2

kΩ

Self-biased¹

5.4

DUTY CYCLE

Duty cycle bounds are set by pulse width high and

pulse width low

Pulse Width Low

Pulse Width High

500

ps

1

REFA

, REFB and

REFB

self-bias points are offset slightly to avoid chatter on an open input condition.

The differential pairs of REFA and

REFC INPUT CHARACTERISTICS

Table 5.

Parameter

Min Typ

Max

300

0.8

Unit

Test Conditions/Comments

REFC INPUT

Input Frequency Range

Input High Voltage

Input Low Voltage

Input Current

Duty Cycle

MHz

V

DC-coupled input (not self-biased)

2.0

1

µA

Duty cycle bounds are set by pulse width high and

pulse width low

Pulse Width Low

Pulse Width High

1

ns

Rev. 0 | Page 4 of 48

Data Sheet

AD9525

CLOCK INPUTS

Table 6.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

Input Frequency

0

3.6

GHz

Frequencies below ~1 MHz should be dc-coupled; be careful to

match self-bias voltage

Input Sensitivity

Input Level

150

mV p-p Measured at 3.1 GHz

2

V p-p

Larger voltage swings can turn on the protection diodes and

can degrade jitter performance

Self-biased; enables ac coupling

With 200 mV p-p signal applied; dc-coupled

Self-biased

Input Common-Mode Voltage, V_CM

Input Common-Mode Range, V_CMR

Input Resistance

1.55 1.64

1.3

1.74

1.8

7.4

V

kΩ

pF

6.7

7

2

Input Capacitance

PLL CHARACTERISTICS

Table 7.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency

125

45

MHz

Antibacklash pulse width = 1.3 ns, 2.9 ns

Antibacklash pulse width = 6.0 ns

CHARGE PUMP (CP)

VDD_CP (Pin 13); V_CPis the voltage of the charge pump pin

( C P, Pin 14)

I_CPSink/Source

High Value

Programmable

With CPRSET = 5.1 kΩ; higher I_CPis possible by changing

CPRSET; V_CP= VDD_CP/2 V

With CPRSET = 5.1 kΩ; lower I_CPis possible by changing

CPRSET, V_CP= VDD_CP/2 V

4.5

4.9

5.4

mA

Low Value

0.57 0.61

0.67

Absolute Accuracy

CPRSET Range

I_CPHigh Impedance Mode Leakage

Sink-and-Source Current Matching

I_CPvs. V_CP

2.5

%

V_CP= VDD_CP/2 V

2.7

3.5

2

10

kΩ

µA

%

VDD_CP = 5 V

0.5 V < V_CP< VDD_CP − 0.5 V

V_CP= VDD_CP/2 V

1.5

2

I_CPvs. Temperature

P DIVIDER (PART OF N DIVIDER)

Input Frequency P = 1

Input Frequency P = 2

Input Frequency P = 3

Input Frequency P = 4

Input Frequency P = 5

Input Frequency P = 6

B DIVIDER (PART OF N DIVIDER)

Input Frequency

1500 MHz

3000 MHz

3600 MHz

1500 MHz

3600 MHz

B counter input frequency (N Divider input frequency

divided by P)

M DIVIDER

Input Frequency

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge Pump/

Phase Frequency Detector (In-Band

Means Within the LBW of the PLL)

PLL in-band phase noise floor is estimated by measuring the

in-band phase noise at the output of the VCO and subtracting

20 log(N) (where N is the value of the N divider)

At 61.44 MHz PFD Frequency

At 122.88 MHz PFD Frequency

PLL Figure of Merit (FOM)

−144

−141

−222

dBc/Hz

dBc/Hz Reference slew rate > 0.25 V/ns; FOM +10 log (f_PFD) is an

approximation of the PFD/CP in-band phase noise (in the

flat region) inside the PLL loop bandwidth; when running

closed loop, the phase noise, as observed at the VCO output,

is increased by 20 log(N)

Rev. 0 | Page 5 of 48

AD9525

Data Sheet

PLL DIGITAL LOCK DETECT

Table 8.

Parameter

PLL DIGITAL LOCK DETECT WINDOW¹

Min

Typ

Max

Unit

Test Conditions/Comments

Signal available at the STATUS and REF_MON pins when

selected by appropriate register settings; lock detect window

settings can be varied by changing the CPRSET resistor

Lock Threshold (Coincidence of Edges)

Selected by Reg. 0x010[1:0] and Reg. 0x019[1], which is the

threshold for transitioning from unlock to lock

Low Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 6.0 ns)

4

7

3.5

ns

Reg. 0x010[1:0] = 00b, 01b,11b; Reg. 0x019[1] = 1b

Reg. 0x010[1:0] = 00b, 01b, 11b; Reg. 0x019[1] = 0b

Reg. 0x010[1:0] = 10b; Reg. 0x019[1] = 0b

Selected by Reg. 0x017[1:0] and Reg. 0x019[1], which is the

threshold for transitioning from unlock to lock

Unlock Threshold (Hysteresis)¹

Low Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 6.0 ns)

8.3

16.9

11

ns

Reg. 0x010[1:0] = 00b, 01b, 11b; Reg. 0x019[1] = 1b

Reg. 0x010[1:0] = 00b, 01b, 11b; Reg. 0x019[1] = 0b

Reg. 0x010[1:0] = 10b; Reg. 0x019[1] = 0b

¹For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

CLOCK OUTPUTS

Table 9.

Parameter

Min

Typ

Max

Unit Test Conditions/Comments

LVPECL CLOCK OUTPUTS

Output Frequency, Maximum

Rise Time/Fall Time (20% to 80%)

Duty Cycle

3.6

GHz

ps

105

162

Input duty cycle = 50/50

M = 1

47

45

47

45

32

750

50

49

32

830

53

55

51

55

33

984

%

mV

FOUT = 2800 MHz

FOUT < 3000 MHz

FOUT = 1400 MHz

FOUT < 1500 MHz

FOUT = 933.33 MHz

Voltage across pins, output driver static;

Termination = 50 Ω to VDD3 − 2 V

M = 2, 4, 6

M = 3, 5

Output Differential Voltage,

Magnitude

Common-Mode Output Voltage

VDD3 –

1.42

VDD3 –

1.37

VDD3 –

1.32

V

Output driver static; VDD3 (Pin 3, Pin 36, Pin 41, Pin 46);

Termination = 50 Ω to VDD3 − 2 V

Rev. 0 | Page 6 of 48

Data Sheet

AD9525

TIMING CHARACTERISTICS

Table 10.

Parameter

Min

Typ Max

Unit

Test Conditions/Comments

PROPAGATION DELAY, t_PECL, CLKIN TO LVPECL OUTPUT

For All M Divider Values

Variation with Temperature

OUTPUT SKEW, LVPECL OUTPUTS¹

All LVPECL Outputs

Termination as shown in Figure 35

High frequency clock distribution configuration

461

522 600

388

ps

fs/°C

13.5 25.2

ps

Across temperature and VDD per device

Temperature Coefficient

14

fs/°C

ps

All LVPECL Outputs Across Multiple Parts

OUTPUT SKEW, LVPECL-TO-SYNC_OUT¹

SYNC_OUT LVPECL Mode

144

All LVPECL Outputs

Temperature Coefficient

All LVPECL Outputs Across Multiple Parts

SYNC_OUT CMOS Mode

189 298

543

ps

fs/°C

ps

Across temperature and VDD per device

417

All LVPECL Outputs

All LVPECL Outputs Across Multiple Parts

PROPAGATION DELAY, REF TO LVPECL OUTPUT

1.64 2.34

2.46

ns

ps

Across temperature and VDD per device

267

581 924

REF refers to either REFA/REFA or REFB/REFB pairs

¹The output skew is the difference between any two paths while operating at the same voltage and temperature.

Timing Diagrams

t_CLK

CLK

DIFFERENTIAL

80%

t_PECL

LVPECL

20%

t_CMOS

t_RP

t_FP

Figure 3. LVPECL Timing, Differential

CLK

Figure 2. CLK/

to Clock Output Timing, M Divider = 1

Rev. 0 | Page 7 of 48

AD9525

Data Sheet

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL 122.88 MHZ VCXO)

Table 11.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical setup using

an external 122.88 MHz VCXO (Crystek CVHD-950);

reference = 122.88 MHz; R divider = 1; LBW = 40 Hz

FOUT = 122.88 MHz

FOUT = 61.44 MHz

107

69

108

107

fs rms Integration BW = 1 kHz to 40 MHz

fs rms Integration BW = 12 kHz to 20 MHz

fs rms Integration BW = 1 kHz to 20 MHz

fs rms Integration BW = 12 kHz to 20 MHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL 1475 MHZ VCO)

Table 12.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical setup using

an external 1475 MHz VCO (Bowei Model MVCO-1475);

reference = 122.88 MHz; R divider = 1; PLL LBW = 18 kHz

FOUT = 1474.56 MHz

99

77

74

68

fs rms Integration BW = 1 kHz to 100 MHz

fs rms Integration BW = 10 kHz to 100 MHz

fs rms Integration BW = 10 kHz to 40 MHz

fs rms Integration BW = 12 kHz to 20 MHz

Reference Sideband Spurs

FOUT = 245.76 MHz

−93

104

87

dBc

122.88 MHz

fs rms Integration BW = 1 kHz to 100 MHz

fs rms Integration BW = 10 kHz to 100 MHz

fs rms Integration BW = 12 kHz to 20 MHz

75

Reference Sideband Spurs

−98

dBc

122.88 MHz

Table 13.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical setup using

an external 1475 MHz VCO (Z-Communications CRO1474-LF);

reference = 122.88 MHz; R divider = 1; PLL LBW = 8 kHz

FOUT = 1474.56 MHz

72

40

33

28

fs rms Integration BW = 1 kHz to 100 MHz

fs rms Integration BW = 10 kHz to 100 MHz

fs rms Integration BW = 10 kHz to 40 MHz

fs rms Integration BW = 12 kHz to 20 MHz

Reference Sideband Spurs

FOUT = 245.76 MHz

−94

83

61

dBc

122.88 MHz

fs rms Integration BW = 1 kHz to 100 MHz

fs rms Integration BW = 10 kHz to 40 MHz

fs rms Integration BW = 12 kHz to 20 MHz

46

Reference Sideband Spurs

−93

dBc

122.88 MHz

Rev. 0 | Page 8 of 48

Data Sheet

AD9525

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL 2.05 GHZ VCO)

Table 14.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical setup using

an external 2.05 MHz VCO (Bowei Model MVCO-

2050A); reference = 122.054215 MHz; R divider = 12;

PLL LBW = 5 kHz

FOUT = 2048.867 MHz

19

21

87

−105

fs rms

dBc

Integration BW = 200 kHz to 5 MHz

Integration BW = 200 kHz to 10 MHz

Integration BW = 12 kHz to 20 MHz

10.671MHz

Reference Sideband Spurs

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL 3 GHZ VCO)

Table 15.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical setup using

an external 2950 MHz VCO (Z-Communications Model

CRO-2950); reference = 122.88 MHz; R divider = 1

FOUT = 2949.12 MHz; PLL LBW = 7 kHz

63

38

34

28

−99

62

36

31

25

−100

78

60

44

33

fs rms

dBc

fs rms

dBc

fs rms

dBc

Integration BW = 1 kHz to 100 MHz

Integration BW = 10 kHz to 100 MHz

Integration BW = 10 kHz to 40 MHz

Integration BW = 12 kHz to 20 MHz

122.88 MHz

Integration BW = 1 kHz to 100 MHz

Integration BW = 10 kHz to 100 MHz

Integration BW = 10 kHz to 40 MHz

Integration BW = 12 kHz to 20 MHz

122.88 MHz

Integration BW = 1 kHz to 100 MHz

Integration BW = 10 kHz to 100 MHz

Integration BW = 10 kHz to 40 MHz

Integration BW = 12 kHz to 20 MHz

122.88 MHz

Reference Sideband Spurs

FOUT = 1474.56 MHz; PLL LBW = 7 kHz

Reference Sideband Spurs

FOUT = 491.52 MHz; PLL LBW = 7 kHz

Reference Sideband Spurs

−96

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; CLOCK INPUT TO DISTRIBUTION OUTPUT,

INCLUDING VCO DIVIDER)

Table 16.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 2949.12 MHz, FOUT = 2949.12 MHz

Divider = 1

Distribution section only; does not include PLL and VCO

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 800 kHz Offset

At 1 MHz Offset

At 10 MHz Offset

−112

−122

−133

−141

−146

−148

−149

−151

dBc/Hz

At 100 MHz Offset

Rev. 0 | Page 9 of 48

AD9525

Data Sheet

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

CLK = 1474.56 MHz, FOUT = 1474.56 MHz

Divider = 1

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 800 kHz Offset

At 1 MHz Offset

−114

−125

−134

−144

−149

−151

−154

dBc/Hz

At 10 MHz Offset

CLK = 122.88 MHz, FOUT = 122.88 MHz

Divider = 1

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 800 kHz Offset

At 1 MHz Offset

−134

−145

−153

−159

−161

dBc/Hz

At 10 MHz Offset

PD, RESET, AND REF_SEL PINS

Table 17.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

INPUT CHARACTERISTICS

Logic 1 Voltage

2.0

V

Logic 0 Voltage

0.8

V

Logic 1 Current

Logic 0 Current PD, RESET

1

µA

−112

The minus sign indicates that current is flowing out of

the AD9525, which is due to the internal pull-up

resistor

Logic 0 Current REF_SEL

Capacitance

1

2

µA

pF

RESET TIMING

Pulse Width Low

RESET Inactive to Start of Register

Programming

50

100

ns

STATUS AND REF_MON PINS

Table 18.

Parameter

Min Typ

2.7

Max

Unit

Test Conditions/Comments

OUTPUT CHARACTERISTICS

Output Voltage High, V_OH

Output Voltage Low, V_OL

MAXIMUM TOGGLE RATE

1 mA output load

V

0.4

200

MHz

Applies when mux is set to any divider or counter

output or PFD up/down pulse; usually debug mode

only; beware that spurs can couple to output when any

of these pins is toggling

Rev. 0 | Page 10 of 48

Data Sheet

AD9525

SERIAL CONTROL PORT

Table 19.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CS (INPUT)

CS has an internal 30 kΩ pull-up resistor

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

2.0

V

µA

0.8

2.5

−112

2

The minus sign indicates that current is flowing out of the

AD9525, which is due to the internal pull-up resistor

Input Capacitance

SCLK (INPUT)

pF

SCLK has an internal 30 kΩ pull-down resistor

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO (WHEN INPUT)

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

Output Logic 0 Voltage

TIMING

2.0

2.7

V

µA

pF

0.8

1

112

2

V

nA

pF

0.8

10

20

2

1 mA load current

V

0.4

31

Clock Rate (SCLK, 1/t_SCLK

Pulse Width High, t_HIGH

Pulse Width Low, t_LOW

SDIO to SCLK Setup, t_DS

SCLK to SDIO Hold, t_DH

)

MHz

ns

16

2

1.1

SCLK to Valid SDIO and SDO, t_DV

CS to SCLK Setup and Hold, t_S, t_H

12

ns

2

CS Minimum Pulse Width High, t_PWH3.6

ns

Rev. 0 | Page 11 of 48

AD9525

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 20.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

VDD3 to GND

−0.3 V to +3.6 V

VDD_CP, CP to GND

REFA, REFA, REFB, REFB, REFC to GND

OUT_RSET to GND

CP_RSET to GND

CLKIN, CLKIN to GND

CLKIN to CLKIN

−0.3 V to +5.8 V

−0.3 V to VDD3 + 0.3 V

−1.2 V to +1.2 V

THERMAL RESISTANCE

Table 21. Thermal Resistance (Simulated)

SCLK, SDIO, SDO, CS to GND

−0.3 V to VDD3 + 0.3 V

Airflow

OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,

OUT3, OUT3, OUT4, OUT4, OUT5, OUT5,

OUT6, OUT6, OUT7, OUT7,

Package Velocity

1, 2

1, 3

1, 4

1, 2

Type

(m/sec)

θ_JA

θ_JC

θ_JB

14.7

Ψ_JT

0.2

0.3

0.4

Unit

°C/W

48-Lead

LFCSP

0

27.3

23.9

21.4

2.1

SYNC_OUT, SYNC_OUT to GND

1.0

2.5

RESET, PD, STATUS, REF_MON to GND

Junction Temperature¹

−0.3 V to VDD3 + 0.3 V

150°C

¹Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.

Storage Temperature Range

Lead Temperature (10 sec)

−65°C to +150°C

300°C

²Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

³Per MIL-Std 883, Method 1012.1.

⁴Per JEDEC JESD51-8 (still air).

¹See Table 21 for θ_JA.

ESD CAUTION

Rev. 0 | Page 12 of 48

Data Sheet

AD9525

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

36 VDD3

OUT7

OUT1

35

3

VDD3

34 OUT7

4

5

OUT0

33 REF_MON

AD9525

32

VDD3

6

7

8

9

10

11

12

OUT_RSET

31 SYNC_OUT

30 SYNC_OUT

29

GND

28 SDO

27 SDIO

TOP

VIEW

(Not to Scale)

CLKIN

VDD3

STATUS

REFC

REF_SEL

26

SCLK

25 CS

NOTES

1. THE EXPOSED PAD IS A GROUND CONNECTION ON THE CHIP THAT

MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO

ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE,

AND MECHANICAL STRENGTH BENEFITS.

Figure 4. Pin Configuration

Table 22. Pin Function Descriptions

Pin No. Mnemonic Type Description

1

2

3

4

5

6

7

8

OUT1

O

P

O

I

LVPECL Complementary Output 1.

OUT1

VDD3

OUT0

LVPECL Output 1.

3.3 V Power Supply for Channel OUT0 and Channel OUT1.

LVPECL Complementary Output 0.

OUT0

LVPECL Output 0.

OUT_RSET

CLKIN

Clock Distribution Current Set Resistor. Connect a 4.12 kΩ resistor from this pin to GND.

Along with CLKIN, this pin is the differential input for the clock distribution section.

I

Along with CLKIN, this pin is the differential input for the clock distribution section. If a single-ended input is

connected to the CLKIN pin, connect a 0.1 µF bypass capacitor from CLKIN to ground.

9

VDD3

STATUS

REFC

REF_SEL

VDD_CP

P

O

I

P

3.3 V Power Supply for CLK Inputs, M Divider, and Output Distribution.

Lock Detect and Other Status Signals.

Reference Clock Input C. This pin is a CMOS input for the PLL reference.

Reference Input Select. Logic high = REFB. No internal pull-up or pull-down resistor on this pin.

Power Supply for Charge Pump (CP). VDD3 < VDD_CP < 5.0 V. VDD_CP must still be connected to 3.3 V if the PLL

is not used.

10

11

12

13

14

CP

O

Charge Pump (Output). This pin connects to an external loop filter. This pin can be left unconnected if the

PLL is not used.

15

16

GND

CP_RSET

GND Ground for Charge Pump VDD_CP Supply. Connect to ground.

O

Charge Pump Current Set Resistor. Connect a 5.1 kΩ resistor from this pin to GND. This resistor can be

omitted if the PLL is not used.

17

18

19

20

21

22

23

24

25

26

27

REFA

GND

VDD3

REFB

PD

I

Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference.

GND Ground for PLL Power Supply. Connect to ground.

P

I

3.3 V Power Supply for PLL.

Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference.

Chip Power-Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.

Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor.

Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor.

Serial Control Port Clock Signal. This pin has an internal 30 kΩ pull-down resistor.

Serial Control Port Bidirectional Serial Data In/Out.

I

RESET

CS

I

SCLK

SDIO

I

Rev. 0 | Page 13 of 48

AD9525

Data Sheet

Pin No. Mnemonic Type Description

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

EP

SDO

GND

I

Serial Control Port Unidirectional Serial Data Out.

GND Connect to ground.

SYNC_OUT

VDD3

REF_MON

OUT7

O

P

O

P

O

P

O

P

LVPECL Complementary Output for Programmable Sync Signal.

LVPECL Output for Programmable Sync Signal.

Power Supply for SYNC_OUT Driver.

Reference Monitor (Output). This pin has multiple selectable outputs.

LVPECL Complementary Output 7.

LVPECL Output 7.

3.3 V Power Supply for Channel OUT6 and Channel OUT7.

LVPECL Complementary Output 6.

LVPECL Output 6.

LVPECL Complementary Output 5.

LVPECL Output 5.

3.3 V Power Supply for Channel OUT4 and Channel OUT5.

LVPECL Complementary Output 4.

LVPECL Output 4.

OUT7

VDD3

OUT6

OUT5

VDD3

OUT4

OUT3

LVPECL Complementary Output 3.

LVPECL Output 3.

3.3 V Power Supply for Channel OUT2 and Channel OUT3.

LVPECL Complementary Output 2.

LVPECL Output 2.

OUT3

VDD3

OUT2

O

OUT2

EP, GND

GND Exposed Paddle. The exposed pad is a ground connection on the chip that must be soldered to the analog

ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength

benefits.

Rev. 0 | Page 14 of 48

Data Sheet

AD9525

TYPICAL PERFORMANCE CHARACTERISTICS

6

5

PUMP UP

PUMP DOWN

4

1

3

2

1

0

CH1 500mV Ω

2.5ns/DIV

40.0GS/s

A CH1 40.0mV

0

1

2

3

4

VOLTAGE ON CP PIN (V)

Figure 5. Charge Pump Characteristics at VDD_CP = 3.3 V

Figure 8. LVPECL Output (Differential) at 122.88 MHz

6

5

4

3

2

1

0

2.5

2.3

2.1

1.9

1.7

1.5

1.3

1.1

0.9

0.7

0.5

960mV p-p

780mV p-p

PUMP UP

PUMP DOWN

600mV p-p

400mV p-p

0

500

1000

1500

2000

2500

3000

0

1

2

3

4

5

6

FREQUENCY (MHz)

VOLTAGE ON CP PIN (V)

Figure 6. Charge Pump Characteristics at VDD_CP = 5.0 V

Figure 9. LVPECL Differential Voltage Swing vs. Frequency

–217.5

–218.0

–218.5

–219.0

–219.5

–220.0

–220.5

–221.0

–221.5

–222.0

–222.5

0

0.2

0.4

0.6

0.8

1.0

1.2

SLEW RATE OF REFA (V/ns)

Figure 7. PLL Figure of Merit (FOM) vs. Slew Rate at REFA

Rev. 0 | Page 15 of 48

AD9525

Data Sheet

–20

–30

–80

1: 1kHz, –96.0dBc/Hz

2: 10kHz, –106.3dBc/Hz

3: 100kHz, –137.2dBc/Hz

4: 800kHz, –144.5dBc/Hz

5: 1MHz, –144.6dBc/Hz

6: 10MHz, –147.7dBc/Hz

7: 100MHz, –152.4dBc/Hz

–90

–40

–50

–100

–110

–120

–130

–140

–150

–160

–170

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

–180

1

2

3

5

NOISE:

ANALYSIS RANGE X: START 1kHz

STOP 100MHz

7

4

6

INTG NOISE: –59.5dBc/100MHz

RMS NOISE: 1.5mRAD

86.2mdeg

RMS JITTER: 81.2fsec

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 10. Additive (Residual) Phase Noise, CLK-to-LVPECL at 122.88 MHz,

Divide-by-1

Figure 13. Phase Noise (Absolute), External VCO (Z-Communications Model

CRO-2950) at 2949.12 MHz; PFD = 122.88 MHz; LBW = 8 kHz;

LVPECL Output = 2949.12 MHz

–80

–90

–20

1: 1kHz, –109.3936dBc/Hz

–30

2: 10kHz, –113.5616dBc/Hz

3: 100kHz, –143.3042dBc/Hz

4: 800kHz, –150.5212dBc/Hz

–40

5: 1MHz, –150.7666dBc/Hz

–50

6: 10MHz, –152.9127dBc/Hz

7: 100MHz, –156.0506 dBc/Hz

–100

–110

–120

–130

–140

–150

–160

–170

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

–180

1

2

3

NOISE:

5

ANALYSIS RANGE X: START 1kHz

STOP 100MHz

7

4

6

INTG NOISE: –67.8dBc/100MHz

RMS NOISE: 575.9µRAD

33.0mdeg

RMS JITTER: 62.2fsec

10

100

1k

10k

100k

1M

10M

100M

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 11. Additive (Residual) Phase Noise, CLK-to-LVPECL at 1500 MHz,

Divide-by-1

Figure 14. Phase Noise (Absolute), External VCO (Z-Communications Model

CRO-2950) at 2949.12 MHz; PFD = 122.88 MHz; LBW = 8k Hz;

LVPECL Output = 1474.56 MHz

–20

1: 1kHz, –136.9dBc/Hz

1: 1kHz, –103.4dBc/Hz

–30

2: 10kHz, –150.3dBc/Hz

2: 10kHz, –109.2dBc/Hz

3: 100kHz, –156.4dBc/Hz

–40

–50

3: 100kHz, –130.6dBc/Hz

4: 800kHz, –147.3dBc/Hz

5: 1MHz, –148.5dBc/Hz

6: 10MHz, –152.9dBc/Hz

7: 100MHz, –154.4dBc/Hz

4: 800kHz, –161.1dBc/Hz

5: 1MHz, –160.9dBc/Hz

–50

6: 10MHz, –161.7dBc/Hz

7: 100MHz, –161.8dBc/Hz

–60

NOISE:

–70

ANALYSIS RANGE X: START 12kHz

–80

–90

STOP 20MHz

–80

INTG NOISE: –88.6dBc/20.0MHz

–90

RMS NOISE: 52.8µRAD

3.0mdeg

–100

–110

–120

–130

–140

–150

–160

–170

–180

–100

–110

–120

–130

–140

–150

–160

–170

–180

RMS JITTER: 68.4fsec

1

2

3

5

NOISE:

ANALYSIS RANGE X: START 1kHz

STOP 100MHz

1

7

5

7

4

2

6

INTG NOISE: –63.7dBc/100MHz

3

RMS NOISE: 919.9µRAD

52.7mdeg

4

6

RMS JITTER: 99.3fsec

100

1k

10k

100k

1M

10M

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 12. Phase Noise (Absolute), External VCO

(Bowei Model MVCO-1475) at 1474.56 MHz; PFD = 122.88 MHz;

LBW = 18 kHz; LVPECL Output = 1474.56 MHz

Figure 15. Phase Noise (Absolute), External VCXO (122.88 MHz VCXO)

(Crystek CVHD-950); Reference = 122.88 MHz; R Divider = 1);

LBW = 40 Hz; LVPECL Output = 122.88 MHz

Rev. 0 | Page 16 of 48

Data Sheet

AD9525

–20

–30

–20

–30

1: 1kHz, –85.0dBc/Hz

2: 10kHz, –99.3dBc/Hz

3: 100kHz, –123.0dBc/Hz

4: 800kHz, –140.7dBc/Hz

5: 1MHz, –142.0dBc/Hz

6: 10MHz, –149.0dBc/Hz

7: 100MHz, –153.3dBc/Hz

–40

–50

–60

–70

–80

–90

1

–100

–110

–120

–130

–140

–150

–160

–170

–180

–100

–110

–120

–130

2

3

2

5

–140

NOISE:

5

7

4

3

ANALYSIS RANGE X: START 1kHz

–150

–160

–170

–180

STOP 100MHz

6

4

6

INTG NOISE: –62.1dBc/19.7MHz

RMS NOISE: 1.1µRAD

63.6mdeg

RMS JITTER: 86.2fsec

100

1k

10k

100k

1M

10M

100M

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 16. Phase Noise (Absolute), External VCO 2.05 GHz VCO

(Bowei Model MVCO-2050A); at 2050 MHz; Reference = 122.054215 MHz;

R Divider = 12

Figure 17. Phase Noise (Absolute), External VCO (Z-Communications

CRO1474-LF) at 1474.56 MHz; PFD = 122.88 MHz;

LBW = 15 kHz; LVPECL Output = 1474.56 MHz

Rev. 0 | Page 17 of 48

AD9525

Data Sheet

TERMINOLOGY

Time Jitter

Phase Jitter and Phase Noise

Phase noise is a frequency domain phenomenon. In the time

domain, the same effect is exhibited as time jitter. When observing

a sine wave, the time of successive zero crossings varies. In a square

wave, the time jitter is a displacement of the edges from their

ideal (regular) times of occurrence. In both cases, the variations in

timing from the ideal are the time jitter. Because these variations

are random in nature, the time jitter is specified in seconds root

mean square (rms) or 1 sigma of the Gaussian distribution.

An ideal sine wave can be thought of as having a continuous

and even progression of phase with time from 0° to 360° for

each cycle. Actual signals, however, display a certain amount

of variation from ideal phase progression over time. This

phenomenon is called phase jitter. Although many causes can

contribute to phase jitter, one major cause is random noise,

which is characterized statistically as being Gaussian (normal)

in distribution.

Time jitter that occurs on a sampling clock for a DAC or an

ADC decreases the signal-to-noise ratio (SNR) and dynamic

range of the converter. A sampling clock with the lowest possible

jitter provides the highest performance from a given converter.

This phase jitter leads to a spreading out of the energy of the

sine wave in the frequency domain, producing a continuous

power spectrum. This power spectrum is usually reported as

a series of values whose units are dBc/Hz at a given offset in

frequency from the sine wave (carrier). The value is a ratio

(expressed in decibels) of the power contained within a 1 Hz

bandwidth with respect to the power at the carrier frequency.

For each measurement, the offset from the carrier frequency is

also given.

Additive Phase Noise

Additive phase noise is the amount of phase noise that can be

attributed to the device or subsystem being measured. The phase

noise of any external oscillators or clock sources is subtracted,

making it possible to predict the degree to which the device

impacts the total system phase noise when used in conjunction

with the various oscillators and clock sources, each of which

contributes its own phase noise to the total. In many cases, the

phase noise of one element dominates the system phase noise.

When there are multiple contributors to phase noise, the total is

the square root of the sum of squares of the individual contributors.

It is meaningful to integrate the total power contained within

some interval of offset frequencies (for example, 10 kHz to

10 MHz). This is called the integrated phase noise over that

frequency offset interval; it can be readily related to the time

jitter due to the phase noise within that offset frequency interval.

Phase noise has a detrimental effect on the performance of ADCs,

DACs, and RF mixers. It lowers the achievable dynamic range of

the converters and mixers, although they are affected in somewhat

different ways.

Additive Time Jitter

Additive time jitter is the amount of time jitter that can be attri-

buted to the device or subsystem being measured. The time jitter of

any external oscillators or clock sources is subtracted. This makes it

possible to predict the degree to which the device impacts the total

system time jitter when used in conjunction with the various

oscillators and clock sources, each of which contributes its own

time jitter to the total. In many cases, the time jitter of the external

oscillators and clock sources dominates the system time jitter.

Rev. 0 | Page 18 of 48

Data Sheet

AD9525

DETAILED BLOCK DIAGRAM

REF_SEL

CP

VDD_CP CP_RSET CLKIN CLKIN

AD9525

NINE

DIFFERENTIAL

OUTPUTS

LVPECL

REFA

÷R

A

1, 2, 3... 32

SYNC_OUT

REFB

÷R

B

1, 2, 3... 32

SYNC

GENERATION

CHARGE

PUMP

÷S

PFD

OUT7

÷R

C

÷M

1, 2, 3, 4, 5, 6

REFC

1, 2, 3... 127

OUT6

OUT5

SDIO

SDO

SCLK

CS

OUT4

CONTROL

INTERFACE

(SPI)

OUT3

÷N

RESET

PD

OUT2

÷B

1, 2, 3... 32

OUT1

÷P

STATUS

MONITOR

1, 2, 3, 4, 5, 6

STATUS

OUT0

REF_MON

Figure 18. Detailed Block Diagram

Rev. 0 | Page 19 of 48

AD9525

Data Sheet

THEORY OF OPERATION

The AD9525 PLL is useful for generating clock frequencies from

a supplied reference frequency. In addition, the PLL can be used

to clean up jitter and phase noise on a noisy reference. The exact

choice of PLL parameters and loop dynamics is application specific.

The flexibility and depth of the AD9525 PLL allow the part to

be tailored to function in many different applications and signal

environments.

An important limit to keep in mind is the maximum frequency

allowed into the PFD. The maximum input frequency into the

PFD is a function of the antibacklash pulse setting, as specified

in the phase/frequency detector (PFD) parameter in Table 7.

Charge Pump (CP)

The charge pump is controlled by the PFD. The PFD monitors

the phase and frequency relationship between its two inputs and

tells the CP to pump up or pump down to charge or discharge the

integrating node (part of the loop filter). The integrated and

filtered CP current is transformed into a voltage that drives the

tuning node of the external VCO to move the VCO frequency

up or down. The CP can be set for high impedance (allows

holdover operation), for normal operation (attempts to lock the

PLL loop), for pump-up, or for pump-down (test modes). The CP

current is programmable in eight steps. The exact value of the CP

current LSB is set by the CPRSET resistor, which is nominally

5.1 kΩ. The actual LSB current can be calculated by CP_LSB =

3.06/CPRSET.

The AD9525 includes on-chip PLL blocks that can be used with

an external VCO or VCXO to create a complete phase-locked

loop. The PLL requires an external loop filter, which usually

consists of a small number of capacitors and resistors. The

configuration and components of the loop filter help to establish

the loop bandwidth and stability of the PLL. The external loop

filter that must be connected between CP and the tuning pin of

the VCO/VCXO. This loop filter determines the loop bandwidth

and stability of the PLL. Make sure to select the proper PFD

polarity for the VCO/VCXO being used.

The AD9525 can also be configured as a clock distribution by

CLKIN

shutting down the PLL and using CLKIN and

as the

PLL External Loop Filter

input. The M divider can be used to divide the input frequency

down to the desired output frequency to each of the eight LVPECL

outputs.

An example of an external loop filter for the PLL is shown in

Figure 19. A loop filter must be calculated for each desired PLL

configuration. The values of the components depend on the VCO

frequency, the K_VCO, the PFD frequency, the charge pump

current, the desired loop bandwidth, and the desired phase

margin. The loop filter affects the phase noise, the loop settling

time, and the loop stability. A basic knowledge of PLL theory is

necessary for understanding loop filter design. ADIsimCLK can

help with the calculation of a loop filter according to the application

requirements.

CONFIGURATION OF THE PLL

Configuration of the PLL is accomplished by programming

the various settings for the R divider, N divider, PFD polarity,

and charge pump current. The combination of these settings

and the loop filter determines the PLL loop bandwidth and PLL

stability. These are managed through programmable register

settings and by the design of the external loop filter.

PLL Reference Inputs

Successful PLL operation and satisfactory PLL loop performance

are highly dependent on proper configuration of the PLL settings,

and the design of the external loop filter is crucial to the proper

operation of the PLL.

The AD9525 features two fully differential PLL reference input

circuits. The differential inputs are self-biased, allowing for easy

ac coupling of input signals. All PLL reference inputs are off by

default. The self-bias level of the two sides is offset slightly to

prevent chattering of the input buffer when the reference is ac

coupled and is slow or missing. The input offset increases the

voltage swing required of the driver to overcome the offset. The

input frequency range and common-mode voltages for the

reference inputs are specified in Table 4.

ADIsimCLK™ is a free program that can help with the design

and exploration of the capabilities and features of the AD9525,

including the design of the PLL loop filter. The AD9516 model

found in the latest ADIsimCLK version can be used for modeling

the AD9525 loop filter. It is available at www.analog.com/clocks.

Phase Frequency Detector (PFD)

The reference input receiver is powered down when the PLL is

powered down. It is possible to dc couple to these inputs. If the

differential reference input is driven by a single-ended signal,

The PFD takes inputs from the R divider and the N divider and

produces an output proportional to the phase and frequency

difference between them. The PFD includes a programmable

delay element that controls the width of the antibacklash pulse.

This pulse ensures that there is no dead zone in the PFD transfer

function and minimizes phase noise and reference spurs. The

antibacklash pulse width is set by Register 0x010[1:0].

REFA REFB

the unused side (

or

) should be decoupled via a

suitable capacitor to a quiet ground.

The AD9525 provides a third single-ended CMOS reference

input referred to as REFC.

Rev. 0 | Page 20 of 48

Data Sheet

AD9525

Reference Switchover

M Divider

The AD9525 supports two separate differential reference inputs.

Manual switchover is performed between these inputs either

through Register 0x01A or by using the REF_SEL pin. This

feature supports networking and other applications that require

redundant references.

The M divider is a fixed divide (FD) of 1, 2, 3, 4, 5, or 6.

The maximum input frequency to the M counter is reflected in

the maximum CLKIN input frequency specified in Table 6.

The M divider provides frequency division between the CLKIN

input and the N feedback divider and clock distribution output

channels.

Manual switchover requires that a clock be present on the reference

input that is being switched to or that the switchover deglitching

feature be disabled (Register 0x01A[4]).

The M divider can also be set to static, which is useful for

applications where the only desired output frequency is the

CLK input frequency.

Reference Dividers R

The reference inputs are routed to their respective divider, R. R can

be set to any value from 1 to 32 (Both R = 0 and R = 1 give divide-

by-1.).

P Divider

The P divider is a fixed divide (FD) of 1, 2, 3, 4, 5 or 6.

The maximum input frequency to the P counter is reflected in

the maximum CLKIN input frequency specified in Table 4.

The division is set by the values of R_LOWand R_HIGH. The divider

can be bypassed (equivalent to divide-by-1, divider circuit is

powered down) by setting the bypass bit.

B Divider

For each R divider, the frequency division (R_X) is set by the values

of R_LOWand R_HIGH(four bits each, representing Decimal 0 to

Decimal 15), where

The B divider is a fixed divide (FD) of 1, 2, 3, …or 32.

The maximum input frequency to the B counter is ~1500 MHz,

as specified in Table 7. This is the prescaler input frequency

(external VCO or CLKIN) divided by the P and M counters.

For example, M = 1 and P = 1 mode is not allowed if the

external VCO frequency is greater than 1500 MHz because the

frequency going to the B divider is too high.

Number of Low Cycles = R_LOW+ 1

Number of High Cycles = R_HIGH+ 1

The high and low cycles are cycles of the clock signal currently

routed to the input of the R.

The division is set by the values of B_LOWand B_HIGH. The divider

can be bypassed (equivalent to divide-by-1, divider circuit is

powered down) by setting the bypass bit.

When a divider is bypassed, R_X= 1.

Otherwise, R_X= (R_HIGH+ 1) + (R_LOW+ 1) = R_HIGH+ R_LOW+ 2.

This allows each reference divider to divide by any integer from

1 to 32.

The frequency division, B_X, is set by the values of B_LOWand

B_HIGH(four bits each, representing Decimal 0 to Decimal 15),

where

The output of the R divider goes to a mux to select one of the

references to the PFD inputs. The frequency applied to the PFD

must not exceed the maximum allowable frequency, which

depends on the antibacklash pulse setting (see Table 7).

Number of Low Cycles = B_LOW+ 1

Number of High Cycles = B_HIGH+ 1

The high and low cycles are cycles of the clock signal currently

routed to the input of the B divider.

The R divider has its own reset. The R divider can also be reset

using the shared reset bit of the R and B counters. This reset bit

is not self-clearing.

When a divider is bypassed, B_X= 1.

The R divider in the REFC path has a division ratio programmable

from 1 to 127.

Otherwise, B_X= (B_HIGH+ 1) + (B_LOW+ 1) = B_HIGH+ B_LOW+ 2.

Although manual reset is not normally required, the B counter has

its own reset bit. Note that this reset bit is not self-clearing.

VCO/VCXO, M and N Feedback Dividers

The feedback division is the product of the M divider and the

N divider. The N divider is a combination of a prescaler (P) and

a B divider.

f

_VCO= (f_REF/R) × N × M

where:

M =1, 2, 3, 4, 5, or 6.

N = (P × B).

P =1, 2, 3, 4, 5, or 6.

B = 1, 2, 3, … or 32.

Rev. 0 | Page 21 of 48

AD9525

Data Sheet

Digital Lock Detect (DLD)

VCO

1

ATTENUATOR

CLKIN

V

TUNE

By selecting the proper output through the mux on each pin, the

DLD function is available at the STATUS and REF_MON pins.

The digital lock detect circuit indicates a lock when the time

difference of the rising edges at the PFD inputs is less than a

specified value (the lock threshold). The loss of a lock is indicated

when the time difference exceeds a specified value (the unlock

threshold). Note that the unlock threshold is wider than the

lock threshold, which allows some phase error in excess of the

lock window to occur without chattering on the lock indicator.

50Ω

R2

CP

R1

C3

C2

C1

AD9525

The lock detect window timing depends on the value of the

CPRSET resistor, as well as three settings: the digital lock detect

window bit (Register 0x019[1]), the antibacklash pulse width

bits (Register 0x010[1:0], see Table 8), and the lock detect counter

bits (Register 0x019[3:2]). The lock and unlock detection values in

Table 8 are for the nominal value of CPRSET = 5.11 kΩ. Doubling

the CPRSET value to 10 kΩ doubles the values in Table 8.

1

VCO MANUFACTURERS RECOMMEND EITHER A T OR PI ATTENUATOR

TO PREVENT VCO PULLING. REFER TO MANUFACTURER’S

RECOMMENDATION

Figure 19. CLKIN Configured as Single-Ended VCO

CMOS VCXO

100kΩ

CLKIN

V

TUNE

A lock is not indicated until there is a programmable number

of consecutive PFD cycles with a time difference that is less than

the lock detect threshold. The lock detect circuit continues to

indicate a lock until a time difference greater than the unlock

threshold occurs on a single subsequent cycle. For the lock detect

to work properly, the period of the PFD frequency must be

greater than the unlock threshold. The number of consecutive PFD

cycles required for a lock is programmable (Register 0x018[6:5]).

100kΩ

CLKIN

CP

R2

R

1

C3

C2

C1

AD9525

Note that, in certain low (<500 Hz) loop bandwidth, high phase

margin cases, it is possible that the DLD can chatter during

acquisition. This is normal and occurs because the PFD inputs

are moving slowly in and out of the lock/unlock window during

PLL loop settling. Adjustment of the lock detect counter setting

(Register 0x019[3:2]) can suppress this behavior.

Figure 20. CLKIN Configured as Single-Ended CMOS VCXO

1

PECL VCXO

CLKIN

V

CLKIN

TUNE

External VCXO/VCO Clock Input (CLKIN/

)

CLKIN

This differential input is used to drive the AD9525 clock

distribution section. The pins are internally self-biased, and the

input signal should be ac-coupled via capacitors.

R2

CP

CLKIN

The CLKIN/

input can be used either as a distribution

R1

only input (with the PLL off) or as a feedback input for an external

VCO/VCXO using the internal PLL. Sample configurations

are illustrated in Figure 19 through Figure 21. Refer to the

manufacturer’s recommendation for VCO terminations; a T or

PI attenuator is often recommended, as illustrated in Figure 19.

C3

C2

C1

AD9525

1

PROVIDE THE PROPER VCXO

MANUFACTURER PECL TERMINATION.

For operation using a CMOS input, an external resistive divider

is required to limit the swing on CLKIN (see Table 6 for the

maximum input rating).

Figure 21. CLKIN Configured as Differential LVPECL VCXO

Status Monitor

The AD9525 contains three frequency status monitors that are

used to indicate if the PLL reference (or references, in the case

of single-ended mode) and the VCO have fallen below a threshold.

Rev. 0 | Page 22 of 48

Data Sheet

AD9525

ways to activate safe power-down mode: individually set the

power-down bit for each driver, power down an individual

output channel, or activate sleep mode.

CLOCK DISTRIBUTION

The AD9525 can be used only as a clock fan out buffer by

disabling the PLL circuit blocks except for the clock distribution

section. The clock distribution consists of eight LVPECL clock

output drivers that share a common M divider. See the M Divider

section for more information on the common M divider.

In total power-down mode 0x0230[1] = 1 (power down

distribution reference). This mode must not be used if there is

an external voltage bias network (such as Thevenin equivalent

termination) on the output pins that will cause a dc voltage to

appear at the powered down outputs. However, total power-down

mode is allowed when the LVPECL drivers are terminated using

only pull-down resistors.

Duty Cycle and Duty-Cycle Correction

The duty cycle of the clock signal at the output of a driver is

a result of either or both of the following conditions:

CLKIN CLKIN

input duty cycle. If the CLKIN,

•

The CLKIN,

input is routed directly to the output, the duty cycle of the

CLKIN

SW1B SW1A

output is the same as the CLKIN,

input.

•

The M divider value. An odd M divider value results in

a non-50% duty cycle.

R2

200Ω

R1

200Ω

N1

QN1

OUT

N2

Table 23.Typical Output Duty Cycle with M Divider ≠ 1

QN2

M Divider

Output Duty Cycle (%)

Even

50

Odd = 3

Odd = 5

33.3

40

SW2

4.4mA

LVPECL Output Drivers

Figure 22. LVPECL Output Simplified Equivalent Circuit

The LVPECL differential voltage (V_OD) is selectable (from

~400 mV to 960 mV (see Bit 2 and Bit 1 in Register 0x0F0 to

Register 0x0F7).

SYNC_OUT

SYNC_OUT provides one LVPECL output or two CMOS

output signal that can used to reset or synchronize a converter.

SYNC_OUT functionality block diagram is shown in Figure 23.

The SYNC_OUT signal is derived from the PLL phase detector

reference input clock or feedback (N-divider) clock. A program-

mable 16-bit S divider further divides the selected reference clock.

There are three different modes of operation for SYNC_OUT:

single shot, periodic, or pseudorandom. SYNC_OUT is retimed to

the high speed clock.

The LVPECL output polarity can be set as noninverting or

inverting, which allows for the adjustment of the relative

polarity of outputs within an application without requiring

a board layout change. Each LVPECL output can be powered

down or powered up, as needed. Because of the architecture of

the LVPECL output stages, there is the possibility of electrical

overstress and breakdown under certain power-down conditions.

For this reason, the LVPECL outputs have two power-down modes:

total power-down and safe power-down. The primary power-

down mode is the safe power-down mode. This mode continues

to protect the output devices while powered down. There are three

OUT0 TO OUT7

UP

REF

PFD

CP

÷M

DN

LOW

÷N

11 10 00 01

SELECT REF: REF, FB, PD

DIGITAL LOCK DETECT

SYNC ENABLE

SYNC_OUT

÷S DIGITAL SYNC CONTROL

M DIVIDER OUTPUT

D

SET

CLR

Q

Figure 23. SYNC_OUT Functional Diagram

Rev. 0 | Page 23 of 48

AD9525

Data Sheet

Single Shot Mode

Pseudorandom Mode

In single shot mode one sync pulse occurs after writing SYNC

ENABLE 0x192[4] = 1. An IO_UPDATE is required to complete

a register write. The width of the sync pulse is determined by the

value of the S divider. A divider value of 0x0000 allows a pulse

whose width is equal to one half period of the phase detector rate.

A divider value of 0x0001 allows a pulse whose width is equal

to two half periods of the phase detector rate. In single shot

mode, the sync enable bit is self-clearing and the sync circuits

are ready to receive another sync enable.

Pseudorandom mode is similar to periodic mode but the pulse

is a PN17 sequence that is continuous until SYNC ENABLE is

cleared by a register writing SYNC ENABLE 0x192[4] = 0. An

IO_UPDATE is required to complete a register write. The width

of the sync pulse is equal to one half period the phase detector

rate. The pulse repetition rate is determined by the value of the

S divider. A divider value of 0x0000 allows a pulse rate equal to

the phase detector rate. A divider value of 0x0001 allows pulse

rate equal to two half the phase detector rate.

Periodic Mode

SYNC_OUT Programming

In periodic mode, the pulse is continuous until SYNC ENABLE

is cleared by a register writing SYNC ENABLE 0x192[4] = 0.

An IO_UPDATE is required to complete a register write. The

width of the sync pulse is equal to one half period of the phase

detector rate. The pulse repetition rate is determined by the

value of the S divider. A divider value of 0x0000 allows a pulse

rate equal to the phase detector rate. A divider value of 0x0001

allows a pulse rate equal to two half periods of the phase detector

rate. The SYNC_OUT signal is resampled with the OUT clock

to ensure time alignment and minimum output skew. There is a

possibility in periodic mode that the SYNC_OUT could slip one

half cycle of the OUT clock period.

The procedure to configure the SYNC_OUT depends on the

logic requirement of the converters that require synchroniza-

tion. Analog Devices, Inc., converters are synchronized on the

rise edge of the SYNC pulse.

SYNC_OUT CMOS Driver

The user can also configure the LVPECL SYNC_OUT as a pair

of CMOS outputs. When the output is configured as CMOS,

CMOS Output A and CMOS Output B are automatically turned

on. Either CMOS Output A or Output B can be turned on or off

independently. The user can also select the relative polarity of the

CMOS outputs for any combination of inverting and noninverting

(see Register 0x0F9). The user can power down each CMOS output

as needed to save power. The CMOS driver is in tristate when it is

powered down.

S DIVIDER = 0

t_START

REF CLOCK

SYNC ENABLE = HIGH

(SINGLE SHOT SELF CLEARING)

IO_UPDATE

SYNC_OUT

MODE = SINGLE SHOT

SYNC_OUT

MODE = PERIODIC

SYNC_OUT

MODE = PN17

SYNC ENABLE = LOW

(SINGLE SHOT SELF CLEARING)

IO_UPDATE

t_STOP

Figure 24. SYNC Output Timing

Rev. 0 | Page 24 of 48

Data Sheet

AD9525

SYNC_OUT

CONTROL

USER PROGRAMS

REGISTER VALUE

FOR S DIVIDER

PROGRAM: S DIVIDER,

SYNC MODE

AND SYNC MODE

PROGRAM: SYNC

ENABLE

REQUEST SYNC

PROGRAM: IO UPDATE

DIGITAL LOCK DETECT

IS USED TO PREVENT

OCCURENCE OF SYNC

IF PLL IS UNLOCKED

NO

LOCK

DETECT = HIGH

YES

THE ANALOG CLOCK

TO THE DIGITAL STATE

MACHINE IS

DISABLED IF SYNC

IS DISABLED

ENABLE_ANALOG

SYNC HIGH FOR S DIVIDER + 1

REF CLOCK CYCLES

SYNC LOW

SYNC ENABLE IS SELF

CLEARING IN SINGLE

SHOT MODE. OTHER

MODES REQUIRE A

SPI WRITE TO DISABLE

SYNC_OUT

NO

SYNC ENABLE

LOW?

YES

END SYNC

PROCESS

Figure 25. SYNC_OUT Flowchart

RESET

Hardware Reset via the

RESET MODES

RESET

briefly pulling

The AD9525 has a power-on reset (POR) and several other

ways to apply a reset condition to the chip.

, a hard reset (an asynchronous hard reset is executed by

RESET

low), restores the chip to the on-chip

default register settings. It takes ~2 µs for the outputs to begin

RESET

Power-On Reset

toggling after

is issued.

During chip power-up, a power-on reset pulse is issued when

VDD reaches ~2.6 V (<2.8 V) and restores the chip to the

default on-chip setting. It takes ~70 ms for the outputs to begin

toggling after the power-on reset pulse signal is internally

generated. The default power-on state of the AD9525 is

configured as a buffer.

Soft Reset via the Serial Port

The serial port control register allows for a soft reset by setting

Bit 2 and Bit 5 in Register 0x000. When Bit 5 and Bit 2 are set,

the chip enters a soft reset mode and restores the chip to the on-

chip setting, except for Register 0x000. Except for the self-clearing

bits, Bit 2 and Bit 5, Register 0x000 retains its previous value

prior to reset. These bits are self-clearing. However, the self-clearing

operation does not complete until an additional serial port SCLK

cycle occurs, and the AD9525 is held in reset until that happens.

Rev. 0 | Page 25 of 48

AD9525

Data Sheet

PLL Power-Down

POWER-DOWN MODES

The PLL section of the AD9525 can be selectively powered down.

In this mode, the AD9525 can be used as a 1 to 8 clock buffer by

using the CLKIN as the clock input.

PD

Chip Power-Down via

The AD9525 can be put into a power-down condition by pulling

PD

the

currents inside the AD9525. The chip remains in this power-down

PD

pin low. Power-down turns off most of the functions and

Distribution Power-Down

state until

is brought back to logic high. When taken out of

The distribution section can be powered down by writing

Register 0x230[4] = 1b, which turns off the bias to the distribution

section.

power-down mode, the AD9525 returns to the settings that

were programmed into its registers prior to the power-down,

unless the registers are changed by new programming while

Individual Clock Output Power-Down

PD

the

pin is held low.

Any of the clock distribution outputs can be powered down

into safe power-down mode by individually writing to the

appropriate registers. The register map details the individual

power-down settings for each output. These settings are found

in Register 0x0F0[0] to Register 0x0F7[0].

Powering down the chip shuts down the currents on the chip,

except for the bias current necessary to maintain the LVPECL

outputs in a safe shutdown mode. The LVPECL bias currents are

needed to protect the LVPECL output circuitry from damage that

can be caused by certain termination and load configurations

when tristated. Because this is not a complete power-down, it

can be called sleep mode.

Individual Clock Channel Power-Down

Any of the clock distribution channels can be powered down

individually by writing to the appropriate registers. Powering

down a clock channel is similar to powering down an individual

driver, but it saves more power because additional circuits are also

powered down. Powering down a clock channel also automatically

powers down the drivers connected to it. The register map details

the individual power-down settings for each output channel.

These settings are found in Register 0x0F0[4], Register 0x0F2[4],

Register 0x0F4[4], and Register 0x0F6[4].

PD

When the AD9525 is in a

following state:

power-down, the chip is in the

•

The PLL is off.

The CLKIN input buffer is off, but the CLKIN input dc

bias circuit is on.

The reference input buffer is off, but the dc bias circuit is

still on.

•

All dividers are off.

All LVPECL outputs are in safe off mode.

The serial control port is active, and the chip responds to

commands.

Rev. 0 | Page 26 of 48

Data Sheet

AD9525

SERIAL CONTROL PORT

The AD9525 serial control port is a flexible, synchronous serial

communications port that allows an easy interface with many

industry-standard microcontrollers and microprocessors. The

AD9525 serial control port is compatible with most synchronous

transfer formats, including Motorola® SPI and Intel® SSR protocols.

The serial control port allows read/write access to all registers

that configure the AD9525.

During this period, the serial control port state machine enters

a wait state until all data is sent. If the system controller decides

to abort the transfer before all of the data is sent, the state machine

must be reset, either by completing the remaining transfers or

CS

by returning

low for at least one complete SCLK cycle (but

CS

fewer than eight SCLK cycles). Raising the

pin on a nonbyte

boundary terminates the serial transfer and flushes the buffer.

PIN DESCRIPTIONS

In the streaming mode (see Table 25), any number of data bytes

can be transferred in a continuous stream. The register address

is automatically incremented or decremented (see the MSB/LSB

SCLK (serial clock) is the serial shift clock. This pin is an input.

SCLK is used to synchronize serial control port reads and writes.

Write data bits are registered on the rising edge of this clock,

and read data bits are registered on the falling edge. This pin is

internally pulled down by a 30 kΩ resistor to ground.

CS

First Transfers section).

must be raised at the end of the last

byte to be transferred, thereby ending streaming mode.

Communication Cycle—Instruction Plus Data

SDIO (serial data input/output) is a dual-purpose pin that acts

either as an input only (unidirectional mode) or as an input/

output (bidirectional mode). The AD9525 defaults to the

bidirectional I/O mode (Register 0x000[7] = 0b).

There are two parts to a communication cycle with the AD9525.

The first part writes a 16-bit instruction word into the AD9525,

coincident with the first 16 SCLK rising edges. The instruction

word provides the AD9525 serial control port with information

regarding the data transfer, which is the second part of the

communication cycle. The instruction word defines whether

the upcoming data transfer is a read or a write, the number of

bytes in the data transfer, and the starting register address for

the first byte of the data transfer.

SDO (serial data out) is used only in the unidirectional I/O mode

(Register 0x000[7] = 1b) as a separate output pin for reading back

data.

CS

(chip select bar) is an active low control that gates the read

CS

and write cycles. When

is high, SDO and SDIO are in a high

Write

impedance state. This pin is internally pulled up by a 30 kΩ

resistor to VS.

If the instruction word is for a write operation, the second part

is the transfer of data into the serial control port buffer of the

AD9525. Data bits are registered on the rising edge of SCLK.

AD9525

SERIAL PORT

CONTROL

(SPI)

SDIO

SDO

SCLK

CS

The length of the transfer (one, two, or three bytes or streaming

mode) is indicated by two bits ([W1:W0]) in the instruction

byte. When the transfer is one, two, or three bytes but not

Figure 26. Serial Control Port

CS

streaming,

stall the bus (except after the last byte, where it ends the cycle).

CS

can be raised after each sequence of eight bits to

GENERAL OPERATION OF SERIAL CONTROL PORT

Single byte or multiple byte transfers are supported, as well as

MSB first or LSB first transfer formats. The AD9525 serial control

port can be configured for a single bidirectional I/O pin (SDIO

only) or for two unidirectional I/O pins (SDIO/SDO). By default,

the AD9525 is in bidirectional mode. Short instruction mode

(8-bit instruction) is not supported. Only long instruction mode

(16-bit instruction) is supported.

When the bus is stalled, the serial transfer resumes when

lowered. Raising the

serial control port. During a write, streaming mode does not

skip over reserved or blank registers, and the user can write

0x00 to the reserved register addresses.

is

pin on a nonbyte boundary resets the

CS

Because data is written into a serial control port buffer area,

not directly into the actual control registers of the AD9525, an

additional operation is needed to transfer the serial control port

buffer contents to the actual control registers of the AD9525,

thereby causing them to become active. The update registers

operation (IO_UPDATE) consists of setting Register 0x232[0] =

1b (this bit is self-clearing). Any number of bytes of data can be

changed before executing an update registers. The update registers

operation simultaneously actuates all register changes that have

been written to the buffer since any previous update.

A write or a read operation to the AD9525 is initiated by

CS

pulling

low.

CS

The

stalled high mode is supported in data transfers where

three or fewer bytes of data (plus instruction data) are transferred

CS

(see Table 24). In this mode, the

pin can temporarily return

high on any byte boundary, allowing time for the system controller

CS

to process the next byte.

can go high on byte boundaries only

and can go high during either part (instruction or data) of the

transfer.

Rev. 0 | Page 27 of 48

AD9525

Data Sheet

Read

the range of the 0x232 registers used by the AD9525.

Bits[A12:A10] must always be 0b. For multibyte transfers, this

address is the starting byte address. In MSB first mode, subsequent

bytes decrement the address.

The AD9525 supports only the long instruction mode. If the

instruction word is for a read operation, the next N × 8 SCLK

cycles clock out the data from the address specified in the

instruction word, where N is 1 to 3 as determined by [W1:W0].

If N = 4, the read operation is in streaming mode, continuing

MSB/LSB FIRST TRANSFERS

The AD9525 instruction word and byte data can be MSB first

or LSB first. Any data written to Register 0x000 must be mirrored;

the upper four bits (Bits[7:4]) must mirror the lower four bits

(Bits[3:0]). This makes it irrelevant whether LSB first or MSB

first is in effect. As an example of this mirroring, see the default

setting for Register 0x000, which mirrors Bit 4 and Bit 3. This

sets the long instruction mode, which is the default and the only

mode that is supported.

CS

until

is raised. Streaming mode does not skip over reserved

or blank registers. The readback data is valid on the falling edge

of SCLK.

The default mode of the AD9525 serial control port is the

bidirectional mode. In bidirectional mode, both the sent data

and the readback data appear on the SDIO pin. It is also possible to

set the AD9525 to unidirectional mode (Register 0x000[7] = 1

and Register 0x000[0] = 1). In unidirectional mode, the readback

data appears on the SDO pin.

The default for the AD9525 is MSB first.

When LSB first is set by Register 0x000[1] and Register 0x000[6],

it takes effect immediately because it affects only the operation

of the serial control port and does not require that an update be

executed.

A readback request reads the data that is in the serial control

port buffer area or the data that is in the active registers

(see Figure 27). Readback of the buffer or active registers

is controlled by Register 0x004[0].

When MSB first mode is active, the instruction and data bytes

must be written from MSB to LSB. Multibyte data transfers in

MSB first format start with an instruction byte that includes the

register address of the most significant data byte. Subsequent

data bytes must follow, in order, from the high address to the

low address. In MSB first mode, the serial control port internal

address generator decrements for each data byte of the multibyte

transfer cycle.

The AD9525 uses Register Address 0x000 to Register

Address 0x232.

CS

SCLK/SCL

SDIO/SDA

UPDATE

REGISTERS

SERIAL

CONTROL

PORT

SDO

When LSB first is active, the instruction and data bytes must be

written from LSB to MSB. Multibyte data transfers in LSB first

format start with an instruction byte that includes the register

address of the least significant data byte, followed by multiple

data bytes. In a multibyte transfer cycle, the internal byte address

generator of the serial port increments for each byte.

WRITE REGISTER 0x232 = 0x001

TO UPDATE REGISTERS

Figure 27. Relationship Between Serial Control Port Buffer Registers and

Active Registers

THE INSTRUCTION WORD (16 BITS)

W

The MSB of the instruction word is R/ , which indicates

The AD9525 serial control port register address decrements

from the register address just written toward Register 0x000 for

multibyte I/O operations if the MSB first mode is active (default).

If the LSB first mode is active, the register address of the serial

control port increments from the address just written toward

Register 0x232 for multibyte I/O operations.

whether the instruction is a read or a write. The next two bits

([W1:W0]) indicate the length of the transfer in bytes. The final

13 bits are the address ([A12:A0]) at which to begin the read or

write operation.

For a write, the instruction word is followed by the number of

bytes of data indicated by Bits[W1:W0] (see Table 24).

Streaming mode always terminates when it reaches Register 0x232.

Note that unused addresses are not skipped during multibyte I/O

operations.

Table 24. Byte Transfer Count

W1

W0

Bytes to Transfer

0

1

0

1

0

1

2

3

Table 25. Streaming Mode (No Addresses Are Skipped)

Write Mode Address Direction Stop Sequence

LSB first

MSB first

Increment

Decrement

0x230, 0x231, 0x232, stop

0x001, 0x000, 0x232, stop

Streaming mode

Bits[A12:A0] select the address within the register map that is

written to or read from during the data transfer portion of the

communications cycle. Only Bits[A9:A0] are needed to cover

Rev. 0 | Page 28 of 48

Data Sheet

AD9525

Table 26. Serial Control Port, 16-Bit Instruction Word, MSB First

MSB

LSB

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I1

I0

R/W

W1

W0

A12 = 0

A11 = 0

A10 = 0

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

CS

SCLK DON'T CARE

DON'T CARE

SDIO

R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA

Figure 28. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data

CS

SCLK

DON'T CARE

R/W W1 W0 A12 A11A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DON'T CARE

SDIO

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDO DON'T CARE

16-BIT INSTRUCTION HEADER

REGISTER (N) DATA

REGISTER (N – 1) DATA

REGISTER (N – 2) DATA

REGISTER (N – 3) DATA

DON'T

CARE

Figure 29. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data

t_HIGH

t_DS

t_S

t_C

t_CLK

t_DH

t_LOW

CS

DON'T CARE

SCLK

SDIO

R/W

W1

W0

A12

A11

A10

A9

A8

A7

A6

A5

D4

D3

D2

D1

D0

DON'T CARE

Figure 30. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements

CS

SCLK

t_DV

SDIO

SDO

DATA BIT N

DATA BIT N – 1

Figure 31. Timing Diagram for Serial Control Port Register Read

CS

SCLK DON'T CARE

DON'T CARE

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA

SDIO

Figure 32. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data

Rev. 0 | Page 29 of 48

AD9525

Data Sheet

t_S

t_C

CS

t_CLK

t_HIGH

t_LOW

t_DS

SCLK

SDIO

t_DH

BIT N

BIT N + 1

Figure 33. Serial Control Port Timing—Write

Table 27. Serial Control Port Timing

Parameter

Description

t_DS

t_DH

t_CLK

t_S

Setup time between data and rising edge of SCLK

Hold time between data and rising edge of SCLK

Period of the clock

Setup time between the CS falling edge and SCLK rising edge (start of communication cycle)

Setup time between SCLK rising edge and the CS rising edge (end of communication cycle)

Minimum period that SCLK should be in a logic high state

t_C

t_HIGH

t_LOW

t_DV

Minimum period that SCLK should be in a logic low state

SCLK to valid SDIO and SDO (see Figure 31)

Rev. 0 | Page 30 of 48

Data Sheet

AD9525

CONTROL REGISTERS

CONTROL REGISTER MAP OVERVIEW

Register addresses that are not listed in Table 28 are not used,

and writing to those registers has no effect. Registers that are

marked as reserved should never have their values changed.

When writing to registers with bits that are marked reserved,

the user should take care to always write the default value for

the reserved bits.

Table 28. Control Register Map

Reg.

Default

Addr.

(Hex)

Register

Name

(MSB)

Bit 7

(LSB)

Bit 0

Value

(Hex)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Serial Port Configuration

0x000 SPI mode

serial port

SD0

active

LSB first/

address

increase

Soft reset

Don't care

Soft

reset

LSB first/

address

increase

SD0 active

Don't care

0x00

configuration

Don't

care

Don't care

Soft reset

Don't care

Soft

reset

Don't care

0x00

0x004 Readback

control

Don't

care

Don't care

Don't

care

Don't care

Read back

active regs

PLL Configuration

0x010 PFD charge

pump

PFD

polarity

CP current, Bits[2:0]

CP mode, Bits[1:0]

Antibacklash pulse width,

Bits[1:0]

0x7D

0x011 R dividers

0x012

REFB divider output high cycles, Bits[3:0]

REFB divider output low cycles, Bits[3:0]

REFA divider output low cycles, Bits[3:0]

B divider output low cycles, Bits[3:0]

P divider prescaler, Bits[2:0]

0x00

REFA divider output high cycles, Bits[3:0]

B divider output high cycles, Bits[3:0]

0x013 B divider

0x014 N divider

Don't

care

Don't care

B divider bypass REFB

divider

REFA divider

bypass

0x015 Resets

Don't

care

Reserved

B divider reset

REFB

divider

reset

REFA

divider reset

Reset all

dividers

0x00

0x016 REFC

REFC

enable

REFC divider, Bits[6:0]

0x00

0x017 Status pin

Charge

pump

STATUS pin

divider enable

STATUS output select, Bits[5:0]

pin to

VDD_CP/2

0x018 REF_MON pin

control

Don’t

care

Don’t care

Don't care

Don’t care

Don't care

REF_MON pin control, Bits[4:0]

0x00

0x019 Lock detect

Don't

care

Don’t care

Disable

Lock detect counter, Bits[1:0] Digital lock

detect window

Digital lock

det disable

0x01A

Ref

Enable

Enable REFB

present

monitor

Enable REFA

present monitor switchover (manual

Select REFB

Stay on

REFB

Use REF_SEL

pin for

Enable

switchover

and monitors

FB clock

present

monitor

automatic

reference

switchover

deglitch

register

mode)

reference

switchover

0x01B

0x01C

Reserved

= 0

Reserved = 0

Reserved =

0

Reserved = 0

0x00

0x22

PLL block PD

register

N divider N divider PD

ECL 2

R Divider B ECL 2

CMOS PD

R Divider A R Divider B PD

R

R Channel B

PD

R Channel A

PD

ECL 2

CMOS PD

Divider A

PD

CMOS PD

0x01F

PLL readback

Unused

Selected

reference

Status FB clock

Don't care

Status

REFB

Status REFA

Digital lock

detect (DLD)

N/A

PECL/CMOS Outputs

0x0F0

LVPECL OUT0

Don’t

care

Don’t care

Power

down

OUT0 PECL output level,

Bits[1:0]

Power down

PECL driver

0x04

Channel 0,

Channel 1

0x0F1

0x0F2

LVPECL OUT1

LVPECL OUT2

Don’t

care

Don’t care

Reserved

Don't care

OUT1 PECL output level,

Bits[1:0]

Power down

PECL driver

0x04

Don’t

care

Power

down

OUT2 PECL output level,

Bits[1:0]

Power down

PECL driver

Channel 2,

Channel 3

0x0F3

LVPECL OUT3

Don’t

care

Don’t care

Reserved

Don't care

OUT3 PECL output level,

Bits[1:0]

Power down

PECL driver

0x04

Rev. 0 | Page 31 of 48

AD9525

Data Sheet

Reg.

Addr.

(Hex)

Default

Value

(Hex)

Register

Name

(MSB)

Bit 7

(LSB)

Bit 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0x0F4

LVPECL OUT4

Don't

care

Don't care

Power

down

Don't care

OUT4 PECL output level,

Bits[1:0]

Power down

PECL driver

0x04

Channel 4,

Channel 5

0x0F5

0x0F6

LVPECL OUT5

LVPECL OUT6

Don't

care

Don't care

Reserved

Don't care

OUT5 PECL output level,

Bits[1:0]

Power down

PECL driver

0x04

Don't

care

Power

down

OUT6 PECL output level,

Bits[1:0]

Power down

PECL driver

Channel 6,

Channel 7

0x0F7

0x0F8

LVPECL OUT7

Sync output

Don't

care

Don't care

Reserved

Don't care

OUT7 PECL output level,

Bits[1:0]

Power down

PECL driver

0x04

0x10

Don't

care

Power

down sync

channel

SYNC_OUT PECL output

level, Bits[1:0]

Power down

PECL driver

0x0F9

0x0FA

Sync output,

other control

Don't

care

Don't care

Polarity

CMOS

mode

Enable CMOS drivers,

Bits[1:0]

CMOS mode

Don't care

Sync out

resampling

edge select

0x00

Drivers

reserved

Don't

care

Don't care

Don't

care

Don't care

SYNC Control

0x190 Sync clock

S divider

Sync clock S divider, Bits[7:0]

Sync clock S divider, Bits[15:8]

0x00

0x191 Sync clock

S divider

0x192 Sync clock

control

Don't

care

Don't care

Sync

Sync source, Bits[1:0]

Sync mode, Bits[1:0]

enable

VCO, Reference and CLK1 Inputs

0x1E0

VCO divider

Don't

care

Don't care

M divider, Bits[2:0]

0x00

Other

0x230 Power-down

0x232 IO_UPDATE

Don't

care

Dist all

power-

down

CLKIN power-

down

M

Distribution

reference

PLL power-

down

divider

power-

down

power-down

Don't

care

Don't care

Don't

care

Don't care

IO_UPDATE

0x00

Rev. 0 | Page 32 of 48

Data Sheet

AD9525

REGISTER MAP DESCRIPTIONS

Table 29 through Table 49 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal

address.

Table 29. SPI Mode Serial Port Configuration

Reg.

Addr.

(Hex)

Bits

Bit Name

Description

0x000

7

SDO active

Selects unidirectional or bidirectional data transfer mode.

0: SDIO pin used for write and read; SDO is high impedance (default).

1: SDO used for read; SDIO used for write; unidirectional mode.

SPI MSB or LSB data orientation. (This register is ignored in I²C mode.)

0: data-oriented MSB first; addressing decrements (default).

1: data-oriented LSB first; addressing increments.

Soft reset.

6

5

LSB first/address

increase

Soft reset

1 (self-clearing): soft reset; restores default values to internal registers.

Unused.

4

Unused

[3:0]

Mirror[7:4]

Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is in MSB or LSB first mode

(see Register 0x000[6]). Set bits as follows:

Bit 0 = Bit 7

Bit 1 = Bit 6

Bit 2 = Bit 5

Bit 3 = Bit 4

0x004

0

Read back

active registers

Select register bank used for a readback.

0: reads back buffer registers (default).

1: reads back active registers.

Table 30. PFD Charge Pump

Reg.

Addr.

(Hex) Bits

Bit Name

Description

0x010

7

PFD polarity

Sets the PFD polarity.

0: Positive (higher control voltage produces higher frequency) (default).

1: Negative (higher control voltage produces lower frequency).

Charge pump current (with CPRSET = 5.1 kΩ).

[6:4]

CP current

Bit 6

Bit 5

Bit 4

I_CP(mA)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.6

1.2

1.8

2.4

3.0

3.6

4.2

4.8 (default)

[3:2]

[1:0]

CP mode

Charge pump operating mode.

Bit 3

Bit 2

Charge Pump Mode

0

1

0

1

0

1

High impedance state

Force source current (pump-up)

Force sink current (pump-down)

Normal operation (default)

Antibacklash

pulse width

See Table 7 for the maximum operating frequency for each setting.

Bit 1

Bit 0

Antibacklash Pulse Width Mode (ns)

0

1

0

1

0

1

2.9 (default)

1.3

6.0

2.9

Rev. 0 | Page 33 of 48

AD9525

Data Sheet

Table 31. REFA, REFB, REFC, B, N, and P Dividers

Reg.

Addr.

(Hex) Bits

Bit Name

Description

0x011 [7:4] REFB divider output Divider high cycle word. Normally set to one-half desired divider division minus one:

high cycles