AD9558BCPZ_技术文档

Quad Input Multiservice Line Card Adaptive

Clock Translator with Frame Sync

AD9558

Data Sheet

Pin program function for easy frequency translation

FEATURES

configuration

Supports GR-1244 Stratum 3 stability in holdover mode

Supports smooth reference switchover with virtually

no disturbance on output phase

Software controlled power-down

64-lead, 9 mm × 9 mm, LFCSP package

Supports Telcordia GR-253 jitter generation, transfer, and

tolerance for SONET/SDH up to OC-192 systems

Supports ITU-T G.8262 synchronous Ethernet slave clocks

Supports ITU-T G.823, G.824, G.825, and G.8261

Auto/manual holdover and reference switchover

4 reference inputs (single-ended or differential)

Input reference frequencies: 2 kHz to 1250 MHz

Reference validation and frequency monitoring (1 ppm)

Programmable input reference switchover priority

20-bit programmable input reference divider

6 pairs of clock output pins with each pair configurable as

a single differential LVDS/HSTL output or as 2 single-ended

CMOS outputs

Output frequencies: 352 Hz to 1250 MHz

Programmable 17-bit integer and 24-bit fractional

feedback divider in digital PLL

Programmable digital loop filter covering loop bandwidths

from 0.1 Hz to 5 kHz (2 kHz maximum for <0.1 dB of

peaking)

APPLICATIONS

Network synchronization, including synchronous Ethernet

and SDH to OTN mapping/demapping

Cleanup of reference clock jitter

SONET/SDH clocks up to OC-192, including FEC

Stratum 3 holdover, jitter cleanup, and phase transient

control

Wireless base station controllers

Cable infrastructure

Data communications

GENERAL DESCRIPTION

The AD9558 is a low loop bandwidth clock multiplier that

provides jitter cleanup and synchronization for many systems,

including synchronous optical networks (SONET/SDH). The

AD9558 generates an output clock synchronized to up to four

external input references. The digital PLL allows for reduction

of input time jitter or phase noise associated with the external

references. The digitally controlled loop and holdover circuitry

of the AD9558 continuously generates a low jitter output clock

even when all reference inputs have failed.

Low noise system clock multiplier

Frame sync support

Adaptive clocking

The AD9558 operates over an industrial temperature range of

−40°C to +85°C. If a smaller package is required, refer to the

AD9557 for the two-input/two-output version of the same part.

Optional crystal resonator for system clock input

On-chip EEPROM to store multiple power-up profiles

FUNCTIONAL BLOCK DIAGRAM

STABLE

SOURCE

AD9558

CHANNEL 0

DIVIDER

CLOCK

MULTIPLIER

CHANNEL 1

DIVIDER

÷3 TO ÷11

HF DIVIDER 0

DIGITAL

PLL

ANALOG

PLL

CHANNEL 2

DIVIDER

÷3 TO ÷11

HF DIVIDER 1

REFERENCE INPUT

AND

MONITOR MUX

CHANNEL 3

DIVIDER

FRAME SYNC

SERIAL INTERFACE

STATUS AND

CONTROL PINS

EEPROM

2

(SPI OR I C)

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD9558

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Digital PLL (DPLL) Core .......................................................... 31

Loop Control State Machine..................................................... 34

System Clock (SYSCLK)................................................................ 35

System Clock Inputs................................................................... 35

System Clock Multiplier............................................................ 35

Output PLL (APLL) ....................................................................... 37

Clock Distribution.......................................................................... 38

Clock Dividers ............................................................................ 38

Output Power-Down ................................................................. 38

Output Enable............................................................................. 38

Output Mode .............................................................................. 38

Clock Distribution Synchronization........................................ 38

Frame Synchronization.................................................................. 40

Reference Configuration in Frame Synchronization Mode . 40

Clock Outputs in Frame Synchronization Mode................... 40

Control Registers for Frame Synchronization Mode............. 40

Level Sensitive Mode and One-Shot Mode............................. 40

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Supply Voltage............................................................................... 4

Supply Current.............................................................................. 4

Power Dissipation......................................................................... 5

RESET

, PINCONTROL, M7 to M0).... 5

Logic Inputs (

,

SYNC

Logic Outputs (M7 to M0, IRQ) ................................................ 6

System Clock Inputs (XOA, XOB) ............................................. 6

Reference Inputs ........................................................................... 7

Reference Monitors ...................................................................... 8

Reference Switchover Specifications.......................................... 8

Distribution Clock Outputs ........................................................ 9

Time Duration of Digital Functions ........................................ 10

Digital PLL .................................................................................. 11

Digital PLL Lock Detection ...................................................... 11

Holdover Specifications............................................................. 11

Serial Port Specifications—SPI Mode...................................... 12

Serial Port Specifications—I²C Mode...................................... 13

Jitter Generation ......................................................................... 13

Absolute Maximum Ratings.......................................................... 16

ESD Caution................................................................................ 16

Pin Configuration and Function Descriptions........................... 17

Typical Performance Characteristics ........................................... 20

Input/Output Termination Recommendations.......................... 25

Getting Started................................................................................ 26

Chip Power Monitor and Startup............................................. 26

Multifunction Pins at Reset/Power-Up ................................... 26

Channel Divider 3/OUT5 Programming in Frame

Synchronization Mode .............................................................. 41

Status and Control.......................................................................... 42

Multifunction Pins (M7 to M0) ............................................... 42

Watchdog Timer......................................................................... 43

EEPROM ..................................................................................... 43

Serial Control Port ......................................................................... 49

SPI/IꢀC Port Selection................................................................ 49

SPI Serial Port Operation.......................................................... 49

IꢀC Serial Port Operation.......................................................... 53

Programming the I/O Registers ................................................... 56

Buffered/Active Registers.......................................................... 56

Autoclear Registers..................................................................... 56

Register Access Restrictions...................................................... 56

Thermal Performance.................................................................... 57

Power Supply Partitions................................................................. 58

Recommended Configuration for 3.3 V Switching Supply .. 58

Configuration for 1.8 V Supply................................................ 58

Pin Program Function Description ............................................. 59

Overview of On-Chip ROM Features ..................................... 59

Hard Pin Programming Mode.................................................. 60

Soft Pin Programming Overview............................................. 61

Register Map ................................................................................... 62

Device Register Programming When Using a Register

Setup File ..................................................................................... 26

Register Programming Overview............................................. 26

Theory of Operation ...................................................................... 29

Overview...................................................................................... 29

Reference Clock Inputs.............................................................. 30

Reference Monitors .................................................................... 30

Reference Profiles....................................................................... 30

Reference Switchover................................................................. 30

Rev. A | Page 2 of 104

Data Sheet

AD9558

Register Map Bit Descriptions.......................................................72

Frame Synchronization (Register 0x0640 to

Register 0x0641)..........................................................................86

Serial Port Configuration (Register 0x0000 to

Register 0x0005)..........................................................................72

DPLL Profile Registers (Register 0x0700 to

Register 0x07E6) .........................................................................87

Silicon Revision (Register 0x000A) ..........................................72

Clock Part Serial ID (Register 0x000C to Register 0x000D).72

System Clock (Register 0x0100 to Register 0x0108) ..............73

Operational Controls (Register 0x0A00 to

Register 0x0A10).........................................................................89

Quick In/Out Frequency Soft Pin Configuration

(Register 0x0C00 to Register 0x0C08) .....................................92

General Configuration (Register 0x0200 to

Register 0x0214)..........................................................................74

Status ReadBack (Register 0x0D00 to Register 0x0D14).......93

EEPROM Control (Register 0x0E00 to Register 0x0E03).....97

IRQ Mask (Register 0x020A to Register 0x020F)...................75

DPLL Configuration (Register 0x0300 to Register 0x032E).76

EEPROM Storage Sequences (Register 0x0E10 to

Register 0x0E3C).........................................................................98

Output PLL Configuration (Register 0x0400 to

Register 0x0408)..........................................................................79

Outline Dimensions......................................................................104

Ordering Guide .........................................................................104

Output Clock Distribution (Register 0x0500 to

Register 0x0515)..........................................................................81

Reference Inputs (Register 0x0500 to Register 0x0507) ........85

REVISION HISTORY

4/12—Rev 0 to Rev. A

Changes to Address 0x071A and Address 0x071D, Table 35.... 65

Changes to Address 0x0780, Address 0x0785 to

Address 0x078A, Address 0x079A, Address 0x079D, Table 35... 67

Changes to Address 0x07C0, Address 0x07DA, and

Changed 3 Hz to 352 kHz in Output Frequencies List Item,

Features Section................................................................................. 1

Change to Output Frequency Range Parameter, Min; and System

Clock Input Doubler Duty Cycle Parameter Description, Table 6... 6

Changes to Test Conditions/Comments Column, Table 9 .......... 8

Changes to Output Frequency Parameters, Min, Table 10.......... 9

Changes to Pin 4 and Pin 42, Table 20 .........................................17

Changes to Device Register Programming When Using a

Register Setup File and Register Programming Overview

Sections.............................................................................................26

Changed APLL VCO Lower Frequency and OUT5 Frequency

Range, Figure 35; Changed 225 MHz to 200 MHz and 3.45 GHz

to 3.35 GHz in Overview Section...................................................29

Changes to Reference Profiles Section .........................................30

Changes to Programmable Digital Loop Filter Section .............32

Changes to System Clock Inputs Section.....................................35

Changes to Output PLL (APLL) Section; Changes to Figure 39 ....37

Changes to Figure 40; Changed 1024 to 1023 in Clock Dividers

Section; Changes to Clock Distribution Synchronization

Section ..............................................................................................38

Changes to Multifunction Pins (M7 to M0) and IRQ Pin

Sections.............................................................................................42

Changes to Figure 44 ......................................................................43

Changes to EEPROM Conditional Processing Section and

Address 0x07DD, Table 35............................................................. 68

Change to Address 0x0A01, Bit 7, Table 35................................. 69

Added Address 0x0E3D to Address 0x0E45, Table 35............... 71

Change to Table 38; Added Table 40, Renumbered Sequentially;

Changes to Table 41 ........................................................................ 72

Change to Bit 0, Address 0x0101, Table 43.................................. 73

Changes to Address 0x0304, Table 55 .......................................... 76

Deleted Address 0x0305, Table 55 ................................................ 76

Changes to Table Title, Table 63; Changes to Address 0x0400

and Address 0x0403, Table 64........................................................ 79

Changes to Address 0x0405, Table 64 .......................................... 80

Changes to Descriptions, Address 0x0500, Table 67.................. 81

Changes to Bit 0, Address 0x0501, Table 68 ................................ 82

Changes to Bits[6:4], Address 0x0505 and Changes to

Address 0x0506, Table 70............................................................... 83

Changes to Bits[6:4] and Bit 0, Address 0x050F, Table 73......... 84

Change to Address 0x0704, Table 78; Changes to Bits[3:0] in

Address 0x0707 and Address 070A, Table 79; and Changes to

Address 0x070E, Table 82................................................................ 87

Changes to Address 0x0710, Table 83; and Changes to Bits[3:0],

Address 0x0714, Table 84................................................................. 88

Changes to Bits[1:0], Address 0x0A01, Table 90........................... 89

Changes to Descriptions, Address 0x0A0B, Table 99................. 91

Changes to Bit 4, Address 0x0C06, Table 100 ............................. 93

Changes to Bit 6 and Bit 1, Address 0x0D01, Table 102 ............ 94

Changes to Table Summary, Table 114......................................... 98

Added Table 128............................................................................101

Changes to Table 129....................................................................102

Changes to Table 130....................................................................103

Figure 45............................................................................................46

Added Programming the EEPROM to Configure an M Pin

to Control Synchronization of Clock Distribution Section .........48

Changes to the Power Supply Partitions Section ........................58

Changed 89.5° to 88.5° in DPLL Phase Margin Section ............59

Changes to Address 0x0006, Address 0x0007, and

Address 0x000A, Table 35 ..............................................................62

Changes to Address 0x0304, Table 35 ..........................................63

Changes to Address 0x0405, Table 35 ..........................................64

10/11—Revision 0: Initial Version

Rev. A | Page 3 of 104

AD9558

Data Sheet

SPECIFICATIONS

Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)

values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD= 1.8 V; T_A= 25°C, unless otherwise noted.

SUPPLY VOLTAGE

Table 1.

Parameter

SUPPLY VOLTAGE

DVDD3

DVDD

AVDD3

Min

Typ

Max

Unit

Test Conditions/Comments

3.135

1.71

3.135

1.71

3.30

1.80

3.30

1.80

3.465

1.89

3.465

1.89

V

AVDD

SUPPLY CURRENT

The test conditions for the maximum (max) supply current are the same as the test conditions for the All Blocks Running parameter of

Table 3. The test conditions for the typical (typ) supply current are the same as the test conditions for the Typical Configuration parameter

of Table 3.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY CURRENT FOR TYPICAL

CONFIGURATION

Typical numbers are for the typical configuration listed

in Table 3

I_DVDD3

I_DVDD

I_AVDD3

I_AVDD

12

50

152

19

20

70

230

26

28

92

305

mA

Pin 45, Pin 46, Pin 51, Pin 52, Pin 64

Pin 6, Pin 55, Pin 56

Pin 25, Pin 26, Pin 31

Pin 7, Pin 10, Pin 12, Pin 17, Pin 22, Pin 29, Pin 30, Pin 35,

Pin 37, Pin 38

SUPPLY CURRENT FOR THE ALL BLOCKS

RUNNING CONFIGURATION

Maximum numbers are for all blocks running configuration

in Table 3

I_DVDD3

I_DVDD

I_AVDD3

I_AVDD

23

11

73

168

34

22

108

250

46

32

143

331

mA

Pin 45, Pin 46, Pin 51, Pin 52, Pin 64

Pin 6, Pin 55, Pin 56

Pin 25, Pin 26, Pin 31

Pin 7, Pin 10, Pin 12, Pin 17, Pin 22, Pin 29, Pin 30, Pin 35,

Pin 37, Pin 38

Rev. A | Page 4 of 104

Data Sheet

AD9558

POWER DISSIPATION

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER DISSIPATION

Typical Configuration

0.47

0.74

1.02

W

System clock: 49.152 MHz crystal; DPLL active;

both 19.44 MHz input references in differential mode;

one HSTL driver at 644.53125 MHz;

one 3.3 V CMOS driver at 161.1328125 MHz and 80 pF

capacitive load on CMOS output

All Blocks Running

0.6

1.0

44

1.32

125

W

System clock: 49.152 MHz crystal; DPLL active;

both input references in differential mode;

four HSTL drivers at 750 MHz;

four 3.3 V CMOS drivers at 250 MHz and 80 pF capacitive

load on CMOS outputs

Full Power-Down

mW

Typical configuration with no external pull-up or pull-

down resistors; about 2/3 of this power is on AVDD3

Incremental Power Dissipation

Conditions = typical configuration; table values show the

change in power due to the indicated operation

Input Reference On/Off

Differential Without Divide-by-2

Differential With Divide-by-2

Single-Ended (Without Divide-by-2)

Output Distribution Driver On/Off

LVDS (at 750 MHz)

20

26

5

25

32

7

32

40

9

mW

Additional current draw is in the DVDD3 domain only

12

14

18

17

21

27

22

28

36

mW

Additional current draw is in the AVDD domain only

A single 1.8 V CMOS output with an 80 pF load

A single 3.3 V CMOS output with an 80 pF load

HSTL (at 750 MHz)

1.8 V CMOS (at 250 MHz)

3.3 V CMOS (at 250 MHz)

Other Blocks On/Off

Second RF Divider

Channel Divider Bypassed

36

10

51

17

64

23

mW

Additional current draw is in the AVDD domain only

LOGIC INPUTS (SYNC, RESET, PINCONTROL, M7 TO M0)

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC INPUTS (SYNC, RESET, PINCONTROL)

Input High Voltage (V_IH)

Input Low Voltage (V_IL)

Input Current (I_INH, I_INL)

Input Capacitance (C_IN)

LOGIC INPUTS (M7 to M0)

Input High Voltage (V_IH)

Input ½ Level Voltage (V_IM)

Input Low Voltage (V_IL)

Input Current (I_INH, I_INL)

Input Capacitance (C_IN)

2.1

V

μA

pF

0.8

100

50

3

2.5

1.0

V

μA

pF

2.2

0.6

100

60

3

Rev. A | Page 5 of 104

AD9558

Data Sheet

LOGIC OUTPUTS (M7 TO M0, IRQ)

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC OUTPUTS (M7 to M0, IRQ)

Output High Voltage (V_OH)

Output Low Voltage (V_OL)

IRQ Leakage Current

Active Low Output Mode

Active High Output Mode

DVDD3 − 0.4

V

I_OH= 1 mA

I_OL= 1 mA

Open-drain mode

V_OH= 3.3 V

V_OL= 0 V

0.4

−200

100

ꢀA

SYSTEM CLOCK INPUTS (XOA, XOB)

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SYSTEM CLOCK MULTIPLIER

Output Frequency Range

750

805

MHz

The VCO range may place limitations on

nonstandard system clock input

frequencies

Phase Frequency Detector (PFD) Rate

Frequency Multiplication Range

150

255

MHz

2

Assumes valid system clock and PFD

rates

SYSTEM CLOCK REFERENCE INPUT PATH

Input Frequency Range

Minimum Input Slew Rate

10

20

600

MHz

V/ꢀs

Minimum limit imposed for jitter

performance

Common-Mode Voltage

Differential Input Voltage Sensitivity

1.05

250

1.16

1.25

V

Internally generated

mV p-p Minimum voltage across pins required

to ensure switching between logic

states; the instantaneous voltage on

either pin must not exceed the supply

rails; can accommodate single-ended

input by ac grounding of complementary

input; 1 V p-p recommended for optimal

jitter performance

System Clock Input Doubler Duty Cycle

This is the amount of duty cycle

variation that can be tolerated on the

system clock input to use the doubler

System Clock Input = 50 MHz

System Clock Input = 20 MHz

System Clock Input = 16 MHz to 20 MHz 47

Input Capacitance

45

46

50

3

55

54

53

%

pF

Single-ended, each pin

Input Resistance

4.2

kΩ

CRYSTAL RESONATOR PATH

Crystal Resonator Frequency Range

Maximum Crystal Motional Resistance

10

50

100

MHz

Ω

Fundamental mode, AT cut crystal

Rev. A | Page 6 of 104

Data Sheet

AD9558

REFERENCE INPUTS

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL OPERATION

Frequency Range

Sinusoidal Input

LVPECL Input

10

0.002

750

1250

MHz

The reference input divide-by-2 block must be

engaged for f_IN> 705 MHz

LVDS Input

0.002

40

750

MHz

V/ꢀs

The reference input divide-by-2 block must be

engaged for f_IN> 705 MHz

Minimum limit imposed for jitter performance

Minimum Input Slew Rate

Common-Mode Input Voltage

AC-Coupled

1.9

1.0

2

2.2

2.4

V

Internally generated

DC-Coupled

Differential Input Voltage Sensitivity

mV

Minimum differential voltage across pins is required to

ensure switching between logic levels; instantaneous

voltage on either pin must not exceed the supply rails

f_IN< 800 MHz

240

320

400

mV

kΩ

f_IN= 800 to 1050 MHz

f_IN= 1050 to 1250 MHz

Differential Input Voltage Hysteresis

Input Resistance

58

21

3

100

Input Capacitance

pF

Minimum Pulse Width High

LVPECL

LVDS

390

640

ps

Minimum Pulse Width Low

LVPECL

LVDS

390

640

ps

SINGLE-ENDED OPERATION

Frequency Range (CMOS)

Minimum Input Slew Rate

Input Voltage High (V_IH)

1.2 V to 1.5 V Threshold Setting

1.8 V to 2.5 V Threshold Setting

3.0 V to 3.3 V Threshold Setting

Input Voltage Low (V_IL)

1.2 V to 1.5 V Threshold Setting

1.8 V to 2.5 V Threshold Setting

3.0 V to 3.3 V Threshold Setting

Input Resistance

0.002

40

300

MHz

V/ꢀs

Minimum limit imposed for jitter performance

1.0

1.4

2.0

V

0.35

0.5

1.0

V

kΩ

pF

ns

47

3

Input Capacitance

Minimum Pulse Width High

Minimum Pulse Width Low

1.5

Rev. A | Page 7 of 104

AD9558

Data Sheet

REFERENCE MONITORS

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE MONITORS

Reference Monitor

Loss of Reference Detection Time

1

1.1

10⁵

DPLL PFD Nominal phase detector period = R/f_REF

period

Δf/f_REF

(ppm)

Frequency Out-of-Range Limits

<2

Programmable (lower bound is subject to quality

of the system clock (SYSCLK)); SYSCLK accuracy

must be better than the lower bound

Validation Timer

0.001

65.535

sec

Programmable in 1 ms increments

¹f_REFis the frequency of the active reference; R is the frequency division factor determined by the R-divider.

REFERENCE SWITCHOVER SPECIFICATIONS

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE SWITCHOVER SPECIFICATIONS

Maximum Output Phase Perturbation

(Phase Build-Out Switchover)

Assumes a jitter-free reference; satisfies Telcordia

GR-1244-CORE requirements; select high PM base

loop filter bit (Register 0x070E, Bit 0) is set to 1 for

all active references

50 Hz DPLL Loop Bandwidth

Peak

Steady State

Valid for automatic and manual reference switching

0

100

ps

2 kHz DPLL Loop Bandwidth

Peak

Steady State

Valid for automatic and manual reference switching

0

250

100

ps

Time Required to Switch to

a New Reference

Phase Build-Out Switchover

1.1

DPLL PFD Calculated using the nominal phase detector

period

period (NPDP = R/f_REF); the total time required is

equal to the time plus the reference validation

time and the time required to lock to the new

reference

Rev. A | Page 8 of 104

Data Sheet

AD9558

DISTRIBUTION CLOCK OUTPUTS

Table 10.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

HSTL MODE

Output Frequency

0.000352

1250

250

MHz

ps

OUT5 only; OUT0 to OUT4 minimum output

frequency is 360 kHz

100 Ω termination across output pins

Rise/Fall Time (20% to 80%)¹

Duty Cycle

140

Up to f_OUT= 700 MHz

Up to f_OUT= 750 MHz

Up to f_OUT= 1250 MHz

Differential Output Voltage Swing

Common-Mode Output Voltage

LVDS MODE

45

42

48

43

950

870

52

53

%

mV

700

1200

960

Magnitude of voltage across pins; output driver static

Output driver static

Output Frequency

0.000352

1250

280

MHz

ps

OUT5 only; OUT0 to OUT4 minimum output

frequency is 360 kHz

100 Ω termination across the output pair

Rise/Fall Time (20% to 80%)¹

Duty Cycle

185

Up to f_OUT= 750 MHz

Up to f_OUT= 800 MHz

Up to f_OUT= 1250 MHz

Differential Output Voltage Swing

Balanced, V_OD

44

43

48

47

43

53

%

247

454

50

mV

Voltage swing between output pins; output driver

static

Absolute difference between voltage swing of

normal pin and inverted pin; output driver static

Unbalanced, ΔV_OD

Offset Voltage

Common-Mode, V_OS

Common-Mode Difference, ΔV_OS

Short-Circuit Output Current

CMOS MODE

1.125

1.26

13

1.375

50

24

V

mV

mA

Output driver static

Voltage difference between pins; output driver static

Output driver static

Output Frequency

OUT5 only; OUT0 to OUT4 minimum output

frequency is 360 kHz

1.8 V Supply

0.000352

150

MHz

10 pF load

3.3 V Supply (OUT0 and OUT5)

Strong Drive Strength Setting

Weak Drive Strength Setting

Rise/Fall Time (20% to 80%)¹

1.8 V Supply

0.000352

250

25

MHz

10 pF load

1.5

3

ns

10 pF load

3.3 V Supply

Strong Drive Strength Setting

Weak Drive Strength Setting

Duty Cycle

0.4

8

0.6

ns

10 pF load

1.8 V Mode

3.3 V Strong Mode

3.3 V Weak Mode

50

47

51

%

10 pF load

Output Voltage High (V_OH)

AVDD3 = 3.3 V, I_OH= 10 mA

AVDD3 = 3.3 V, I_OH= 1 mA

AVDD3 = 1.8 V, I_OH= 1 mA

Output Voltage Low (V_OL)

AVDD3 = 3.3 V, I_OL= 10 mA

AVDD3 = 3.3 V, I_OL= 1 mA

AVDD3 = 1.8 V, I_OL= 1 mA

Output driver static; strong drive strength

AVDD3 − 0.3

AVDD3 − 0.1

AVDD − 0.2

V

Output driver static; strong drive strength

0.3

0.1

V

Rev. A | Page 9 of 104

AD9558

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT TIMING SKEW

Between OUT0 and OUT1

10 pF load

10

70

ps

ns

ps

HSTL mode on both drivers; rising edge only; any

divide value

HSTL mode on both drivers; rising edge only; any

divide value

HSTL mode on both drivers; rising edge only; any

divide value

HSTL mode on both drivers; rising edge only; any

divide value

Between OUT0 and OUT3

Between OUT0 and OUT5

105

1.39

1

222

1.76

12

Between OUT1 and OUT2

(OUT1 and OUT2 Share the

Same Divider)

Between OUT3 and OUT4

(OUT3 and OUT4 Share the

Same Divider)

1

24

ps

HSTL mode on both drivers; rising edge only; any

divide value

Across All OUT0 to OUT4 HSTL

105

100

235

ps

HSTL mode on all drivers; rising edge only; any

divide value

LVDS mode on all drivers; rising edge only; any

divide value

Across All OUT0 to OUT4 LVDS

Additional Delay on One Driver by

Changing Its Logic Type

HSTL to LVDS

−5

+1

0

+5

ps

Positive value indicates that the LVDS edge is

delayed relative to HSTL

Positive value indicates that the CMOS edge is

delayed relative to HSTL

HSTL to 1.8 V CMOS

HSTL to 3.3 V CMOS, Strong Mode

OUT0 CMOS to OUT1 HSTL

OUT0 CMOS to OUT3 HSTL

OUT0 CMOS to OUT4 HSTL

OUT0 CMOS to OUT5 HSTL

The CMOS edge is delayed relative to HSTL

3.53

3.55

3.56

4.84

3.59

3.65

3.68

5.1

ns

¹The listed values are for the slower edge (rise or fall).

TIME DURATION OF DIGITAL FUNCTIONS

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

TIME DURATION OF DIGITAL

FUNCTIONS

EEPROM-to-Register Download

Time

Register-to-EEPROM Upload Time

13

138

1

20

ms

Using default EEPROM storage sequence

(see Register 0x0E10 to Register 0x0E3F)

Using default EEPROM storage sequence

(see Register 0x0E10 to Register 0x0E3F)

Time from power-down exit to system clock

lock detect

145

Minimum Power-Down Exit Time

Rev. A | Page 10 of 104

Data Sheet

AD9558

DIGITAL PLL

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL PLL

Phase-Frequency Detector (PFD)

Input Frequency Range

2

100

kHz

Loop Bandwidth

Phase Margin

Closed-Loop Peaking

0.1

30

<0.1

2000

89

Hz

Degrees

dB

Programmable design parameter

Programmable design parameter ;

part can be programmed for <0.1 dB peaking in

accordance with Telcordia GR-253 jitter transfer

1, 2, …, 1,048,576

Reference Input (R) Division Factor

1

2²⁰

2¹⁷

Integer Feedback (N1) Division Factor 180

180, 181, …, 131,072

Fractional Feedback Divide Ratio

0

0.999

Maximum value: 16,777,215/16,777,216

DIGITAL PLL LOCK DETECTION

Table 13.

Parameter

Min

Typ

1

Max

Unit

Test Conditions/Comments

PHASE LOCK DETECTOR

Threshold Programming Range

Threshold Resolution

FREQUENCY LOCK DETECTOR

Threshold Programming Range

Threshold Resolution

0.001

65.5

ns

ps

0.001

16,700

ns

ps

Reference-to-feedback period difference

1

HOLDOVER SPECIFICATIONS

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

HOLDOVER SPECIFICATIONS

Initial Frequency Accuracy

<0.01

ppm

Excludes frequency drift of SYSCLK source;

excludes frequency drift of input reference prior

to entering holdover; compliant with GR-1244

Stratum 3

Rev. A | Page 11 of 104

AD9558

Data Sheet

SERIAL PORT SPECIFICATIONS—SPI MODE

Table 15.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CS

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SCLK

2.0

0.8

60

100

2

V

μA

pF

Internal 30 kΩ pull-down resistor

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO

2.0

0.8

200

1

V

μA

pF

2

As an Input

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

As an Output

2.0

0.8

1

2

V

μA

pF

Output Logic 1 Voltage

Output Logic 0 Voltage

SDO

Output Logic 1 Voltage

Output Logic 0 Voltage

TIMING

DVDD3 − 0.6

V

1 mA load current

0.4

40

V

1 mA load current

SCLK

Clock Rate, 1/t_CLK

Pulse Width High, t_HIGH

Pulse Width Low, t_LOW

SDIO to SCLK Setup, t_DS

SCLK to SDIO Hold, t_DH

SCLK to Valid SDIO and SDO, t_DV

CS to SCLK Setup (t_S)

CS to SCLK Hold (t_C)

CS Minimum Pulse Width High

MHz

ns

10

13

3

6

10

ns

10

0

ns

6

ns

Rev. A | Page 12 of 104

Data Sheet

AD9558

SERIAL PORT SPECIFICATIONS—I²C MODE

Table 16.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SDA, SCL (AS INPUT)

Input Logic 1 Voltage

0.7 ×

V

DVDD3

Input Logic 0 Voltage

0.3 ×

V

DVDD3

Input Current

−10

+10

μA

For V_IN= 10% to 90% DVDD3

Hysteresis of Schmitt Trigger Inputs

0.015 ×

DVDD3

Pulse Width of Spikes That Must Be Suppressed by

the Input Filter, t_SP

50

ns

SDA (AS OUTPUT)

Output Logic 0 Voltage

0.4

V

I_O= 3 mA

Output Fall Time from V_IHminto V_ILmax

20 + 0.1

C_b

250

ns

10 pF ≤ C_b≤ 400 pF

1

TIMING

SCL Clock Rate

Bus-Free Time Between a Stop and Start

Condition, t_BUF

400

kHz

μs

1.3

Repeated Start Condition Setup Time, t_{SU; STA}

Repeated Hold Time Start Condition, t_{HD; STA}

0.6

μs

After this period, the first clock pulse is

generated

Stop Condition Setup Time, t_{SU; STO}

Low Period of the SCL Clock, t_LOW

High Period of the SCL Clock, t_HIGH

SCL/SDA Rise Time, t_R

SCL/SDA Fall Time, t_F

Data Setup Time, t_{SU; DAT}

0.6

1.3

0.6

20 + 0.1 C_b

100

μs

ns

pF

1

300

Data Hold Time, t_{HD; DAT}

Capacitive Load for Each Bus Line, C_b

100

1

400

¹C_bis the capacitance (pF) of a single bus line.

JITTER GENERATION

Jitter generation (random jitter) uses 49.152 MHz crystal for system clock input.

Table 17.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

JITTER GENERATION

System clock doubler enabled;

high phase margin mode enabled;

Register 0x0405 = 0x20; Register 0x0403 =

0x07; Register 0x0400 = 0x81;

in cases where multiple driver types are

listed, both driver types were tested at

those conditions, and the one with higher

jitter is quoted, although there is usually

not a significant jitter difference between

the driver types

f_REF= 19.44 MHz; f_OUT= 622.08 MHz; f_LOOP= 50 Hz

HSTL Driver

Bandwidth: 5 kHz to 20 MHz

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 20 kHz to 80 MHz

Bandwidth: 50 kHz to 80 MHz

Bandwidth: 16 MHz to 320 MHz

304

296

300

266

185

fs rms

Rev. A | Page 13 of 104

AD9558

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

f_REF= 19.44 MHz; f_OUT= 644.53 MHz; f_LOOP= 50 Hz

HSTL and/or LVDS Driver

Bandwidth: 5 kHz to 20 MHz

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 20 kHz to 80 MHz

Bandwidth: 50 kHz to 80 MHz

Bandwidth: 16 MHz to 320 MHz

334

321

319

277

185

fs rms

f_REF= 19.44 MHz; f_OUT= 693.48 MHz; f_LOOP= 50 Hz

HSTL Driver

Bandwidth: 5 kHz to 20 MHz

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 20 kHz to 80 MHz

Bandwidth: 50 kHz to 80 MHz

Bandwidth: 16 MHz to 320 MHz

298

285

286

252

183

fs rms

f_REF= 19.44 MHz; f_OUT= 174.703 MHz; f_LOOP= 1 kHz

HSTL Driver

Bandwidth: 5 kHz to 20 MHz

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 20 kHz to 80 MHz

Bandwidth: 50 kHz to 80 MHz

Bandwidth: 4 MHz to 80 MHz

354

301

321

290

177

fs rms

f_REF= 19.44 MHz; f_OUT= 174.703 MHz; f_LOOP= 100 Hz

LVDS and/or 3.3 V CMOS Driver

Bandwidth: 5 kHz to 20 MHz

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 20 kHz to 80 MHz

Bandwidth: 50 kHz to 80 MHz

Bandwidth: 4 MHz to 80 MHz

306

293

313

283

166

fs rms

f_REF= 25 MHz; f_OUT= 161.1328 MHz; f_LOOP= 100 Hz

HSTL Driver

Bandwidth: 5 kHz to 20 MHz

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 20 kHz to 80 MHz

Bandwidth: 50 kHz to 80 MHz

Bandwidth: 4 MHz to 80 MHz

316

302

324

292

171

fs rms

f_REF= 2 kHz; f_OUT= 70.656 MHz; f_LOOP= 100 Hz;

HSTL and/or 3.3 V CMOS Driver

Bandwidth: 10 Hz to 30 MHz

3.22

ps

rms

Bandwidth: 5 kHz to 20 MHz

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 10 kHz to 400 kHz

Bandwidth: 100 kHz to 10 MHz

338

324

278

210

fs rms

f_REF= 25 MHz; f_OUT= 1 GHz; f_LOOP= 500 Hz

HSTL Driver

Bandwidth: 100 Hz to 500 MHz (Broadband)

1.71

ps

rms

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 20 kHz to 80 MHz

343

338

fs rms

Rev. A | Page 14 of 104

Data Sheet

AD9558

Jitter generation (random jitter) uses 19.2 MHz TCXO for system clock input.

Table 18.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

JITTER GENERATION

System clock doubler enabled; high phase

margin mode enabled; Register 0x0405 = 0x20;

Register 0x0403 = 0x07; Register 0x0400 = 0x81;

in cases where multiple driver types are listed,

both driver types were tested at those conditions,

and the one with higher jitter is quoted, although

there is usually not a significant jitter difference

between the driver types

f_REF= 19.44 MHz; f_OUT= 644.53 MHz; f_LOOP= 0.1 Hz

HSTL Driver

Bandwidth: 5 kHz to 20 MHz

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 20 kHz to 80 MHz

Bandwidth: 50 kHz to 80 MHz

Bandwidth: 16 MHz to 320 MHz

402

393

391

347

179

fs rms

f_REF= 19.44 MHz; f_OUT= 693.48 MHz; f_LOOP= 0.1 Hz

HSTL Driver

Bandwidth: 5 kHz to 20 MHz

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 20 kHz to 80 MHz

Bandwidth: 50 kHz to 80 MHz

Bandwidth: 16 MHz to 320 MHz

379

371

335

175

fs rms

f_REF= 19.44 MHz; f_OUT= 312.5 MHz; f_LOOP= 0.1 Hz

HSTL Driver

Bandwidth: 5 kHz to 20 MHz

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 20 kHz to 80 MHz

Bandwidth: 50 kHz to 80 MHz

Bandwidth: 4 MHz to 80 MHz

413

404

407

358

142

fs rms

f_REF= 25 MHz; f_OUT= 161.1328 MHz; f_LOOP= 0.1 Hz

HSTL Driver

Bandwidth: 5 kHz to 20 MHz

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 20 kHz to 80 MHz

Bandwidth: 50 kHz to 80 MHz

Bandwidth: 4 MHz to 80 MHz

399

391

414

376

190

fs rms

f_REF= 2 kHz; f_OUT= 70.656 MHz; f_LOOP= 0.1 Hz

HSTL and/or 3.3 V CMOS Driver

Bandwidth: 10 Hz to 30 MHz

Bandwidth: 12 kHz to 20 MHz

Bandwidth: 10 kHz to 400 kHz

Bandwidth: 100 kHz to 10 MHz

970

404

374

281

fs rms

Rev. A | Page 15 of 104

AD9558

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 19.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

Analog Supply Voltage (AVDD)

Digital Supply Voltage (DVDD)

Digital I/O Supply Voltage (DVDD3)

Analog Supply Voltage (AVDD3)

Maximum Digital Input Voltage

Storage Temperature Range

Operating Temperature Range

2 V

3.6 V

−0.5 V to DVDD3 + 0.5 V

−65°C to +150°C

−40°C to +85°C

300°C

ESD CAUTION

Lead Temperature

(Soldering 10 sec)

Junction Temperature

150°C

Rev. A | Page 16 of 104

Data Sheet

AD9558

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

IRQ

SCLK/SCL

SDIO/SDA

SDO

1

2

3

4

5

6

7

8

9

48 REFC

47 REFC

46 DVDD3

45 DVDD3

44 REFA

43 REFA

42 SYNC

41 M7

40 PINCONTROL

39 RESET

38 AVDD

37 AVDD

36 NC

CS

DVDD

AVDD

XOA

XOB

AVDD 10

NC 11

AVDD 12

OUT4 13

OUT4 14

OUT3 15

OUT3 16

AD9558

TOP VIEW

(Not to Scale)

35 AVDD

34 NC

33 LF_VCO2

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS).

Figure 2. Pin Configuration

Table 20. Pin Function Descriptions

Input/

Output Pin Type

Pin No. Mnemonic

Description

1

2

IRQ

SCLK/SCL

O

I

3.3 V CMOS

Interrupt Request Line.

Serial Programming Clock (SCLK) in SPI Mode. Data clock for serial programming.

Open-Collector Serial Clock Pin (SCL) in I²C Mode. Requires a pull-up resistor, usually

2.2 kΩ; the resistor size depends on the number of I²C devices on the bus.

3

SDIO/SDA

I/O

3.3 V CMOS

Serial Data Input/Output (SDIO) in SPI Mode. When the device is in 4-wire SPI mode,

data is written via this pin. In 3-wire SPI mode, both data reads and writes occur on

this pin. There is no internal pull-up/pull-down resistor on this pin.

Open-Collector Serial Data Pin (SDA) in I²C Mode. Requires a pull-up resistor, usually

2.2 kΩ; the resistor size depends on the number of I²C devices on the bus.

4

5

SDO

CS

O

I

3.3 V CMOS

Serial Data Output. Use this pin to read data in 4-wire mode. There is no internal pull-up/

pull-down resistor on this pin. This pin is high impedance in the default 3-wire mode.

Chip Select (SPI), Active Low. When programming a device, this pin must be held low.

In systems where more than one AD9558 is present, this pin enables individual

programming of each AD9558. This pin has an internal 10 kΩ pull-up resistor.

6, 55, 56 DVDD

I

Power

Differential

input

1.8 V Digital Supply.

1.8 V Analog (SYSCLK) Power Supply.

System Clock Input. XOA contains internal dc biasing and should be ac-coupled with

a 0.01 ꢀF capacitor, except when using a crystal. If a crystal is used, connect the crystal

across XOA and XOB. Single-ended 1.8 V CMOS is also an option but can introduce

a spur if the duty cycle is not 50%. When using XOA as a single-ended input, connect

a 0.01 ꢀF capacitor from XOB to ground.

7

8

AVDD

XOA

9

XOB

I

Differential

input

Complementary System Clock Input. Complementary signal to XOA. XOB contains

internal dc biasing and should be ac-coupled with a 0.01 ꢀF capacitor, except when

using a crystal. If a crystal is used, connect the crystal across XOA and XOB.

10

11

12, 17,

22, 29,

30

AVDD

NC

AVDD

I

Power

1.8 V Analog (VCO) Power Supply.

No Connection. Do not connect to this pin.

1.8 V Analog (Output Driver) Power Supply.

Rev. A | Page 17 of 104

AD9558

Data Sheet

Input/

Output Pin Type

Pin No. Mnemonic

Description

13

OUT4

O

HSTL, LVDS, or Complementary Output 4. This output can be configured as HSTL, LVDS, or single-ended

1.8 V CMOS

1.8 V CMOS.

14

OUT4

O

HSTL, LVDS,

Output 4. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

or 1.8 V CMOS LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent

termination as described in the Input/Output Termination Recommendations section.

15

16

OUT3

O

HSTL, LVDS, or Complementary Output 3. This output can be configured as HSTL, LVDS,

1.8 V CMOS

or single-ended 1.8 V CMOS.

HSTL, LVDS, or Output 3. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

1.8 V CMOS

LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent

termination as described in the Input/Output Termination Recommendations section.

18

19

OUT2

O

HSTL, LVDS, or Complementary Output 2. This output can be configured as HSTL, LVDS, or

1.8 V CMOS single-ended 1.8 V CMOS.

HSTL, LVDS, or Output 2. This output can be HSTL, LVDS, or single-ended 1.8 V CMOS.

1.8 V CMOS

LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent

termination as described in the Input/Output Termination Recommendations section.

20

21

OUT1

O

HSTL, LVDS, or Complementary Output 1. This output can be configured as HSTL, LVDS, or

1.8 V CMOS

single-ended 1.8 V CMOS.

HSTL, LVDS,

Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

or 1.8 V CMOS LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent

termination as described in the Input/Output Termination Recommendations section.

23

24

OUT5

O

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

Complementary Output 5. This output can be configured as HSTL, LVDS, or single-ended

1.8 V or 3.3 V CMOS.

Output 5. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V

CMOS. LVPECL levels can be achieved by ac coupling and by using the Thevenin-

equivalent termination as described in the Input/Output Termination

Recommendations section.

25, 26

27

AVDD3

OUT0

I

O

Power

3.3 V Analog (Output Driver) Power Supply.

Complementary Output 0. This output can be configured as HSTL, LVDS, or single-

ended 1.8 V or 3.3 V CMOS.

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

28

OUT0

O

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

Output 0. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V

CMOS. LVPECL levels can be achieved by ac coupling and by using the Thevenin-

equivalent termination as described in the Input/Output Termination

Recommendations section.

31

32

AVDD3

LDO_VCO2

I

Power

LDO bypass

3.3V Analog (VCO 2) Power Supply.

Output PLL Loop Filter Voltage Regulator. Connect a 0.47 ꢀF capacitor from this pin

to ground. This pin is also the ac ground reference for the integrated output PLL

external loop filter.

33

LF_VCO2

I/O

I

Loop filter

Power

Loop Filter Node for the Output PLL. Connect an external 6.8 nF capacitor from this

pin to Pin 32 (LDO_VCO2).

No Connect. There is no internal connection for this pin.

1.8 V Analog (APLL) Power Supply.

No Connect. There is no internal connection for this pin.

1.8 V Analog (DCO and TDC) Power Supplies.

Chip Reset. When this active low pin is asserted, the chip goes into reset. This pin has

an internal 50 kΩ pull-up resistor.

34

35

36

37, 38

39

NC

AVDD

NC

AVDD

RESET

I

Power

3.3 V CMOS

40

PINCONTROL

I

3.3 V CMOS

Pin Program Mode Enable Pin. When pulled high during startup, this pin enables pin

programming of the AD9558 configuration during startup. If this pin is low during

startup, the user must program the part via the serial port, or use values that are

stored in the EEPROM.

41

42

M7

I/O

I

3.3 V CMOS

Configurable I/O Pin. Along with pins M6 through M0, this pin is configured through

the AD9558 register space.

Clock Distribution Synchronization Pin. When this pin is activated, output drivers are

held static and then synchronized on a low-to-high transition of this pin. This pin is

used to arm the frame sync function when frame sync mode is enabled and has an

internal 60 kΩ pull-up resistor.

SYNC

Rev. A | Page 18 of 104

Data Sheet

AD9558

Input/

Output Pin Type

Pin No. Mnemonic

Description

43

44

REFA

I

Differential

input

Reference A Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

REFA

I

Differential

input

Power

Complementary Reference A Input. This pin is the complementary input to Pin 43.

45, 46,

51, 52

47

DVDD3

REFC

3.3 V Digital (Reference Input) Power Supply.

Differential

input

Reference C Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

48

49

REFC

REFD

I

Differential

input

Differential

input

Complementary Reference C Input. This pin is the complementary input to Pin 47.

Reference D Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

50

53

REFD

REFB

I

Differential

input

Differential

input

Complementary Reference D Input. This pin is the complementary input to Pin 49.

Reference B Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

54

REFB

I

Differential

input

Complementary Reference B Input. This pin is the complementary input to Pin 53.

57, 58,

59, 60,

61, 62,

63

M0, M1, M2,

M3, M4, M5,

M6

I/O

3.3 V CMOS

Configurable I/O Pins. These pins are configured under program control. The M7 pin

(Pin 41) is the last pin of this group.

64

EP

DVDD3

VSS

I

O

Power

Exposed pad

3.3 V Digital Supply.

The exposed pad must be connected to ground (VSS).

Rev. A | Page 19 of 104

AD9558

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

f_R= input reference clock frequency; f_OUT= output clock frequency; f_SYS= SYSCLK input frequency; f_S= internal system clock frequency;

LF = SYSCLK PLL internal loop filter used. AVDD, AVDD3, and DVDD at nominal supply voltage; f_S= 786.432 MHz, unless otherwise noted.

–60

INTEGRATED RMS JITTER (12kHz TO 20MHz): 296fs

INTEGRATED RMS JITTER (12kHz TO 20MHz): 285fs

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

–100

–110

–120

–130

–140

–150

–160

100

1k

10k

100k

1M

10M

100M

100

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET (Hz)

Figure 3. Absolute Phase Noise (Output Driver = HSTL),

f_R= 19.44 MHz, f_OUT= 622.08 MHz,

Figure 5. Absolute Phase Noise (Output Driver = HSTL),

f_R= 19.44 MHz, f_OUT= 693.482991 MHz,

DPLL Loop BW = 50 Hz, f_SYS= 49.152 MHz Crystal

–60

–70

–80

INTEGRATED RMS JITTER (12kHz TO 20MHz): 320fs

INTEGRATED RMS JITTER (12kHz TO 20MHz): 301fs

–80

–90

–100

–110

–120

–130

–140

–150

–160

–100

–110

–120

–130

–140

–150

–160

100

1k

10k

100k

1M

10M

100M

100

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET (Hz)

Figure 6. Absolute Phase Noise (Output Driver = HSTL),

f_R= 19.44 MHz, f_OUT= 174.703 MHz,

DPLL Loop BW = 1 kHz, f_SYS= 49.152 MHz Crystal

Figure 4. Absolute Phase Noise (Output Driver = HSTL),

f_R= 19.44 MHz, f_OUT= 644.53125 MHz,

DPLL Loop BW = 50 Hz, f_SYS= 49.152 MHz Crystal

Rev. A | Page 20 of 104

Data Sheet

AD9558

–80

–60

–70

INTEGRATED RMS JITTER (12kHz TO 20MHz): 302fs

INTEGRATED RMS JITTER (12kHz TO 20MHz): 393fs

–90

–100

–110

–120

–130

–140

–150

–160

–80

–90

–100

–110

–120

–130

–140

–150

–160

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET (Hz)

Figure 7. Absolute Phase Noise (Output Driver = 3.3.V CMOS),

f_R= 19.44 MHz, f_OUT= 161.1328125 MHz,

Figure 10. Absolute Phase Noise (Output Driver = HSTL),

f_R= 19.44 MHz, f_OUT= 644.53 MHz,

DPLL Loop BW = 100 Hz, f_SYS= 49.152 MHz Crystal

DPLL Loop BW = 0.1 Hz, f_SYS= 19.2 MHz TCXO

–60

–70

–80

–90

–70

–80

INTEGRATED RMS JITTER (12kHz TO 20MHz): 371s

INTEGRATED RMS JITTER (12kHz TO 20MHz): 308fs

–90

–100

–110

–120

–130

–140

–150

–160

–100

–110

–120

–130

–140

–150

–160

10

100

1k

10k

100k

1M

10M

100M

100

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET (Hz)

Figure 8. Absolute Phase Noise (Output Driver = HSTL),

f_R= 2 kHz, f_OUT= 125 MHz,

Figure 11. Absolute Phase Noise (Output Driver = HSTL),

f_R= 19.44 MHz, f_OUT= 693.482991 MHz,

DPLL Loop BW = 100 Hz, f_SYS= 49.152 MHz Crystal

DPLL Loop BW = 0.1 Hz, f_SYS= 19.2 MHz TCXO

–60

–70

–80

INTEGRATED RMS JITTER (12kHz TO 20MHz): 404fs

INTEGRATED RMS JITTER (12kHz TO 20MHz): 343fs

–80

–90

–100

–110

–120

–130

–140

–150

–160

–100

–110

–120

–130

–140

–150

–160

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET (Hz)

Figure 9. Absolute Phase Noise (Output Driver = HSTL),

f_R= 25 MHz, f_OUT= 1 GHz,

Figure 12. Absolute Phase Noise (Output Driver = HSTL),

f_R= 19.44 MHz, f_OUT= 312.5 MHz,

DPLL Loop BW = 500 Hz, f_SYS= 49.152 MHz Crystal

DPLL Loop BW = 0.1 Hz, f_SYS= 19.2 MHz TCXO

Rev. A | Page 21 of 104

AD9558

Data Sheet

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

–70

INTEGRATED RMS JITTER (12kHz TO 20MHz): 391fs

–80

–90

–100

–110

–120

–130

–140

–150

–160

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET (Hz)

FREQUENCY (MHz)

Figure 13. Absolute Phase Noise (Output Driver = 3.3 V CMOS),

f_R= 19.44 MHz, f_OUT=161.1328125 MHz,

Figure 16. Amplitude vs. Toggle Rate,

HSTL Mode (LVPECL-Compatible Mode)

DPLL Loop BW = 0.1 Hz, f_SYS= 19.2 MHz TCXO

1.0

–70

INTEGRATED RMS JITTER (12kHz TO 20MHz): 395fs

–80

–90

0.9

0.8

0.7

0.6

0.5

0.4

LVDS BOOST MODE

LVDS DEFAULT

–100

–110

–120

–130

–140

–150

–160

0

100

200

300

400

500

600

700

800

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET (Hz)

FREQUENCY (MHz)

Figure 17. Amplitude vs. Toggle Rate, LVDS

Figure 14. Absolute Phase Noise (Output Driver = 1.8 V CMOS),

f_R= 2 kHz, f_OUT= 70.656 MHz,

DPLL Loop BW = 0.1 Hz, f_SYS= 19.2 MHz TCXO

–60

3.5

3.0

2.5

2.0

1.5

1.0

INTEGRATED RMS JITTER (12kHz TO 20MHz): 388fs

3.3V CMOS

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

1.8V CMOS

0

50

100

150

200

250

300

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET (Hz)

FREQUENCY (MHz)

Figure 15. Absolute Phase Noise (Output Driver = HSTL),

f_R= 19.44 MHz, f_OUT= 644.53 MHz, f_SYS= 19.2 MHz TCXO

Holdover Mode

Figure 18. Amplitude vs. Toggle Rate with 10 pF Load,

3.3 V (Strong Mode) and 1.8 V CMOS

Rev. A | Page 22 of 104

Data Sheet

AD9558

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

70

60

50

40

30

20

10

0

1.8V CMOS MODE

3.3V CMOS STRONG MODE

3.3V CMOS WEAK MODE

0

50

100

150

200

0

10

20

30

40

50

60

70

80

FREQUENCY (MHz)

Figure 19. Amplitude vs. Toggle Rate with 10 pF Load,

3.3 V (Weak Mode) CMOS

Figure 22. Power Consumption vs. Frequency, One CMOS Driver on Output

Driver Power Supply Only (Pin 12, Pin 17, Pin 22, and Pin 29) for 1.8 V CMOS Mode,

or on Pin 25 and Pin 26 for 3.3 V CMOS Mode

1.0

0.8

110

105

100

95

90

85

80

75

70

65

60

55

50

45

40

35

30

0.6

OUTPUT CHANNEL 1 OR 2:

BOTH HSTL DRIVERS ENABLED

0.4

0.2

OUTPUT CHANNEL 1 OR 2:

ONE HSTL DRIVER ENABLED

0

–0.2

–0.4

–0.6

–0.8

–1.0

OUTPUT CHANNEL 0 OR 3:

HSTL DRIVER ENABLED

–1

0

1

2

3

4

5

0

250

500

750

1000

1250

FREQUENCY (MHz)

TIME (ns)

Figure 23. Output Waveform, HSTL (400 MHz)

Figure 20. Power Consumption vs. Frequency,

HSTL Mode (Single Channel) on 1.8 V Output Driver Power Supply Only

(Pin 12, Pin 17, Pin 22, and Pin29)

0.4

65

60

0.3

0.2

OUTPUT CHANNEL 1 OR 2:

55

BOTH LVDS DRIVERS ENABLED

50

45

40

35

0.1

0

OUTPUT CHANNEL 1 OR 2:

ONE LVDS DRIVER ENABLED

30

25

–0.1

–0.2

–0.3

–0.4

OUTPUT CHANNEL 0 OR 3:

LVDS DRIVER ENABLED

20

15

10

5

0

–1

0

1

2

3

4

0

100

200

300

400

500

600

700

800

FREQUENCY (MHz)

TIME (ns)

Figure 24. Output Waveform, LVDS (400 MHz)

Figure 21. LVDS Power Consumption vs. Frequency on 1.8 V Output Driver

Power Supply Only (Pin 12, Pin 17, Pin 22, and Pin 29)

Rev. A | Page 23 of 104

AD9558

Data Sheet

3

0

3.4

3.0

2.6

2.2

1.8

1.4

1.0

0.6

0.2

–3

–6

–9

–12

–15

–18

–21

–24

–27

–30

LOOP BW = 100Hz;

HIGH PHASE MARGIN;

PEAKING: 0.06dB; –3dB: 69Hz

2pF LOAD

10pF LOAD

LOOP BW = 2kHz;

HIGH PHASE MARGIN;

PEAKING: 0.097dB; –3dB: 1.23kHz

LOOP BW = 5kHz;

HIGH PHASE MARGIN;

PEAKING: 0.14dB; –3dB: 4.27kHz

–0.2

–1

10

100

1k

FREQUENCY OFFSET (Hz)

10k

100k

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

TIME (ns)

Figure 25. Output Waveform,

3.3 V CMOS (100 MHz, Strong Mode)

Figure 28. Closed-Loop Transfer Function for 100 Hz, 2 kHz, and 5 kHz Loop

Bandwidth Settings; High Phase Margin Loop Filter Setting

(This is compliant with Telcordia GR-253 jitter transfer test for loop

bandwidths < 2 kHz.)

1.9

1.7

1.5

1.3

1.1

0.9

0.7

0.5

0.3

0.1

3

0

–3

–6

–9

–12

–15

–18

–21

LOOP BW = 100Hz;

2pF LOAD

10pF LOAD

NORMAL PHASE MARGIN;

–24

PEAKING: 0.09dB; –3dB: 117Hz

LOOP BW = 2kHz;

NORMAL PHASE MARGIN;

–27

PEAKING: 1.6dB; –3dB: 2.69kHz

–0.1

–1

–30

10

100

1k

10k

100k

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

FREQUENCY OFFSET (Hz)

TIME (ns)

Figure 26. Output Waveform, 1.8 V CMOS (100 MHz)

Figure 29. Closed-Loop Transfer Function for 100 Hz and 2 kHz Loop

Bandwidth Settings; Normal Phase Margin Loop Filter Setting

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0

2pF LOAD

10pF LOAD

–5

5

15

25

35

45

55

65

75

85

95

TIME (ns)

Figure 27. Output Waveform, 3.3 V CMOS (20 MHz, Weak Mode)

Rev. A | Page 24 of 104

Data Sheet

AD9558

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

10pF

0.1µF

XOA

DOWNSTREAM

DEVICE

10MHz TO 50MHz FUNDAMENTAL

AT CUT CRYSTAL WITH

WITH HIGH

AD9557/

AD9558

100Ω

IMPEDANCE

AD9558

INPUT AND

HSTL OR

10pF LOAD CAPACITANCE

INTERNAL

0.1µF

LVDS

DC BIAS

XOB

10pF

Figure 33. System Clock Input (XOA, XOB) in Crystal Mode

(The recommended C_LOAD= 10 pF is shown. The values of the 10 pF shunt

capacitors shown here should equal the C_LOADof the crystal.)

Figure 30. AC-Coupled LVDS or HSTL Output Driver

(100 Ω resistor can go on either side of decoupling capacitors and should be

as close as possible to the destination receiver.)

0.1µF

150Ω

300Ω

Z

= 50Ω

3.3V

CMOS

TCXO

0

XOA

LVDS OR 1.8V HSTL

HIGH IMPEDANCE

DIFFERENTIAL

RECEIVER

AD9557/

AD9558

HSTL OR

LVDS

SINGLE-ENDED

(NOT COUPLED)

AD9557/

AD9558

100Ω

0.1µF

Z

= 50Ω

0

XOB

Figure 34. System Clock Input (XOA, XOB) When Using a TCXO/OCXO with

3.3 V CMOS Output

Figure 31. DC-Coupled LVDS or HSTL Output Driver

V

= 3.3V

S

82Ω

Z

= 50Ω

0.1µF

0

3.3V

LVPECL

AD9557/

SINGLE-ENDED

(NOT COUPLED)

AD9558

1.8V

HSTL

Z

= 50Ω

0

127Ω

Figure 32. Interfacing the HSTL Driver to a 3.3 V LVPECL Input

(This method incorporates impedance matching and dc biasing for bipolar

LVPECL receivers. If the receiver is self-biased, the termination scheme shown

in Figure 30 is recommended.)

Rev. A | Page 25 of 104

AD9558

Data Sheet

GETTING STARTED

CHIP POWER MONITOR AND STARTUP

DEVICE REGISTER PROGRAMMING WHEN USING

A REGISTER SETUP FILE

The AD9558 monitors the voltage on the power supplies at

power-up. When DVDD3 is greater than 2.35 V 0.1 V and

DVDD and AVDD are greater than 1.4 V 0.05 V, the device

generates a 20 ms reset pulse. The power-up reset pulse is internal

The evaluation software contains a programming wizard and

a convenient graphical user interface that assists the user in

determining the optimal configuration for the DPLL, APLL,

and SYSCLK based on the desired input and output frequencies.

It generates a register setup file with a .STP extension that is

easily readable using a text editor.

RESET

and independent of the

pin. This internal power-up reset

sequence eliminates the need for the user to provide external power

supply sequencing. Within 45 ns after the leading edge of the

internal reset pulse, the M7 to M0 multifunction pins behave

as high impedance digital inputs and continue to do so until

programmed otherwise. The delay on the M7 to M0 pin function

change is 45 ns for pin reset or soft reset.

After using the evaluation software to create the setup file, use

the following sequence to program the AD9557 once:

1. Register 0x0A01 = 0x20 (set user free run mode).

2. Register 0x0A02 = 0x02 (hold outputs in static SYNC).

(Skip this step if using SYNC on DPLL phase lock or SYNC

on DPLL frequency lock. See Register 0x0500[1:0].)

3. Register 0x0405 = 0x20 (clear APLL VCO calibration).

4. Write the register values in the STP file from Address 0x0000

to Address 0x032E.

During a device reset (either via the power-up reset pulse or the

RESET

pin), the multifunction pins (M7 to M0) behave as high

impedance inputs, but upon removal of the reset condition,

level-sensitive latches capture the logic pattern present on the

multifunction pins.

5. Register 0x0005 = 0x01 (update all registers).

6. Write the rest of the registers in the STP file, starting at

Address 0x0400.

7. Register 0x0405 = 0x21 (calibrate APLLon next I/O update).

8. Register 0x0403 = 0x07 (configure APLL).

9. Register 0x0400 = 0x81 (configure APLL).

10. Register 0x0005 = 0x01 (update all registers).

11. Register 0x0A01[5] = 0b (clear user free run mode).

12. Register 0x0005 = 0x01 (update all registers).

MULTIFUNCTION PINS AT RESET/POWER-UP

The AD9558 requires the user to supply the desired logic state

to the PINCONTROL pin, as well as to the M7 to M0 pins. If

PINCONTROL is high, the part is in hard pin programming

mode. See the Pin Program Function Description section for

details on hard pin programming.

At startup, there are three choices for the M7 to M0 pins: pull-

up, pull-down, and floating. If the PINCONTROL pin is low,

the M7 to M0 pins determine the following configurations:

REGISTER PROGRAMMING OVERVIEW

•

Following a reset, the M1 and M0 pins determine whether

the serial port interface behaves according to the SPI or I²C

protocol. Specifically, M0 = M1 = low selects the SPI

interface, and any other value selects the I²C port. The 3-

level logic of M1 and M0 allows the user to select eight

possible I²C addresses (see Table 24).

This section provides an overview of the register blocks in the

AD9558, describing what they do and why they are important.

Registers Differing from Defaults for Optimal Performance

Ensure that the following registers are programmed to the listed

values for optimal performance:

•

The M3 and M2 pins select which of the eight possible

EEPROM profiles are loaded, or if the EEPROM loading is

bypassed. Leaving M3 and M2 floating at startup bypasses

the EEPROM loading, and the factory defaults are used

instead (see Table 22).

•

Register 0x0405[7:4] = 0x2

Register 0x0403 = 0x07

Register 0x0400 = 0x81

If the silicon revision (Register 0x000A) equals 0x21 or higher,

the values listed here are already the default values.

Rev. A | Page 26 of 104

Data Sheet

AD9558

Program the System Clock and Free Run Tuning Word

Program the Clock Distribution Outputs

The system clock multiplier (SYSCLK) parameters are at

Register 0x0100 to Register 0x0108, and the free run tuning

word is at Register 0x0300 to Register 0x0303. Use the following

steps for optimal performance:

The APLL output goes to the clock distribution block. The

clock distribution parameters reside in Register 0x0500 to

Register 0x0509. They include the following:

•

Output power-down control

Output enable (disabled by default)

Output synchronization

Output mode control

Output divider functionality

1. Set the system clock PLL input type and divider values.

2. Set the system clock period.

It is essential to program the system clock period because

many of the AD9558 subsystems rely on this value.

3. Set the system clock stability timer.

See the Clock Distribution section for more information.

It is highly recommended that the system clock stability

timer be programmed. This is especially important when

using the system clock multiplier and also applies when

using an external system clock source, especially if the

external source is not expected to be completely stable

when power is applied to the AD9558. The system clock

stability timer specifies the amount of time that the system

clock PLL must be locked before the part declares that the

system clock is stable. The default value is 50 ms.

4. Program the free run tuning word.

The free run frequency of the digital PLL (DPLL) determines

the frequency appearing at the APLL input when free run

mode is selected. The free run tuning word is at Register

0x0300 to Register 0x0303. The correct free run frequency

is required for the APLL to calibrate and lock correctly.

5. Set user free run mode (Register 0x0A01[5] = 1b).

Generate the Output Clock

If Register 0x0500[1:0] is programmed for automatic clock

distribution synchronization via the DPLL phase or frequency

lock, the synthesized output signal appears at the clock distribution

outputs. Otherwise, set and then clear the soft sync clock

distribution bit (Register 0x0A02, Bit 1), or use a multifunction

pin input (if programmed for use) to generate a clock

distribution sync pulse, which causes the synthesized output

signal to appear at the clock distribution outputs.

Program the Multifunction Pins (Optional)

This step is required only if the user intends to use any of the

multifunction pins for status or control. The multifunction pin

parameters are at Register 0x0200 to Register 0x0208.

Program the IRQ Functionality (Optional)

Initialize and Calibrate the Output PLL (APLL)

This step is required only if the user intends to use the IRQ feature.

The IRQ monitor registers are at Register 0x0D02 to Register

0x0D09. If the desired bits in the IRQ mask registers at Register

0x020A to Register 0x020F are set high, the appropriate IRQ

monitor bit at Register 0x0D02 to Register 0x0D07 is set high

when the indicated event occurs.

The registers controlling the APLL are at Register 0x0400

to Register 0x0408. This low noise, integer-N PLL multiplies

the DPLL output (which is usually 175 MHz to 200 MHz) to a

frequency in the 3.35 GHz to 4.05 GHz range. After the system

clock is configured and the free run tuning word is set in

Register 0x0300 to Register 0x0303, the user can set the manual

APLL VCO calibration bit (Register 0x0405[0]) and issue an I/O

update (Register 0x0005[0]). This process performs the APLL

VCO calibration. VCO calibration ensures that, at the time of

calibration, the dc control voltage of the APLL VCO is centered in

the middle of its operating range. It is important to remember the

following points when calibrating the APLL VCO:

Individual IRQ events are cleared by using the IRQ clearing

registers at Register 0x0A04 to Register 0x0A09, or by setting

the clear all IRQs bit (Register 0x0A03[1]) to 1b.

The default values of the IRQ mask registers are such that

interrupts are not generated. The IRQ pin mode default is open-

drain NMOS.

Program the Watchdog Timer (Optional)

•

The system clock must be stable.

This step is required only if the user intends to use the watchdog

timer. The watchdog timer control is in Register 0x0210 and

Register 0x0211 and is disabled by default.

The APLL VCO must have the correct frequency from the

30-bit DCO (digitally controlled oscillator) during

calibration.

The watchdog timer is useful for generating an IRQ after a fixed

amount of time. The timer is reset by setting the clear watchdog

timer bit (Register 0x0A03[0]) to 1b.

•

The APLL VCO must be recalibrated any time the APLL

frequency changes.

APLL VCO calibration occurs on the low-to-high transition

of the manual APLL VCO calibration bit, and this bit is not

autoclearing. Therefore, this bit must be cleared (and an I/O

update issued) before another APLL calibration is started.

The best way to monitor successful APLL calibration is to

monitor Bit 2 in Register 0x0D01 (APLL lock).

•

Rev. A | Page 27 of 104

AD9558

Data Sheet

Program the Digital Phase-Locked Loop (DPLL)

Program the Reference Profiles

The DPLL parameters reside in Register 0x0300 to

Register 0x032E. They include the following:

The reference profile parameters reside in Register 0x0700 to

Register 0x07E6. The AD9558 evaluation software contains a

wizard that calculates these values based on the user’s input

frequency. See the Reference Profiles section for details on

programming these functions. They include the following:

•

Free run frequency

DPLL pull-in range limits

DPLL closed-loop phase offset

Phase slew control (for hitless reference switching)

Tuning word history control (for holdover operation)

•

Reference period

Reference period tolerance

Reference validation timer

Selection of high phase margin loop filter coefficients

DPLL loop bandwidth

Reference prescaler (R divider)

Feedback dividers (N1, N2, N3, FRAC1, and MOD1)

Phase and frequency lock detector controls

Program the Reference Inputs

The reference input parameters reside in Register 0x0600 to

Register 0x0602. See the Reference Clock Input section for

details on programming these functions. They include the

following:

•

Reference power-down

Reference logic family

Reference priority

Generate the Reference Acquisition

After the registers are programmed, the user can clear the user

freerun bit (Register 0x0A01[5]) and issue an I/O update, using

Register 0x0005[0] to invoke all of the register settings that are

programmed up to this point.

After the registers are programmed, the DPLL locks to the first

available valid reference that has the highest priority.

Rev. A | Page 28 of 104

Data Sheet

AD9558

THEORY OF OPERATION

XO OR XTAL

XO FREQUENCIES

10MHz TO 180MHz

XTAL: 10MHz TO 50MHz

÷M0 TO ÷M3b ARE

10-BIT INTEGER

DIVIDERS

SYNC

RESET

PINCONTROL

M0 M1 M2 M3 M4 M5 M6 M7 IRQ

1

OUT0

÷M0

2

1

SPI/I C

ROM

AND

FSM

MULTIFUNCTION I/O PINS

(CONTROL AND STATUS

READBACK)

OUT0

REGISTER

SPACE

2

SPI/I C

SERIAL PORT

EEPROM

÷2

×2

RF

FRAME SYNC

MODE ONLY

DIVIDER 1

÷3 TO ÷11

1

OUT1

1

OUT1

÷M1

SYSTEM

REFA

1

OUT2

PFD/CP ÷N3

LF

CLOCK

÷2

MAX 1.25GHz

MULTIPLIER

1

OUT2

1

OUT3

REFB

RF

DIVIDER 2

÷3 TO ÷11

÷M2

1

OUT3

1

OUT4

R DIVIDER

(20-BIT)

FREE RUN

TW

÷M3

÷M3b

×2

REFC

1

OUT4

×2

FRAME SYNC PULSE

17-BIT

INTEGER

TUNING

WORD

CLAMP

AND

DPFD

DIGITAL

LOOP

FILTER

30-BIT

NCO

FRAC1/

MOD1

REFD

÷N1

1

OUT5

HISTORY

24b/24b

RESOLUTION

÷N2

DIGITAL PLL (DPLL)

OUTPUT PLL (APLL)

REF MONITORING

AUTOMATIC

SWITCHING

3.35GHz

TO

4.05GHz

PFD/CP

LF

2kHz TO 8kHz FRAME SYNC SIGNAL

AD9558

LF_VCO2

APLL

STATUS

1

OUT0, OUT1, OUT2, OUT3, OUT4: 360kHz TO 1.25GHz; OUT5: 352Hz TO 1.25GHz

Figure 35. Detailed Block Diagram

section, which has two divide-by-3 to divide-by-11 RF dividers

that are cascaded with 10-bit integer (divide-by-1 to divide-by-

1024) channel dividers.

OVERVIEW

The AD9558 provides clocking outputs that are directly related

in phase and frequency to the selected (active) reference, but

with jitter characteristics that are governed by the system clock,

the DCO, and the output PLL (APLL). The AD9558 supports

up to four reference inputs and input frequencies ranging from

2 kHz to 1250 MHz. The core of this product is a digital phase-

locked loop (DPLL). The DPLL has a programmable digital loop

filter that greatly reduces jitter that is transferred from the active

reference to the output. The AD9558 supports both manual and

automatic holdover. While in holdover, the AD9558 continues to

provide an output as long as the system clock is present. The

holdover output frequency is a time average of the output

frequency history just prior to the transition to the holdover

condition. The device offers manual and automatic reference

switchover capability if the active reference is degraded or fails

completely. The AD9558 also has adaptive clocking capability

that allows the DPLL divider ratios to be changed while the DPLL

is locked.

The XOA and XOB pins provide the input for the system clock.

These pins accept a reference clock in the 10 MHz to 600 MHz

range, or a 10 MHz to 50 MHz crystal connected directly across

the XOA and XOB pins. The system clock provides the clocks to

the frequency monitors, the DPLL, and internal switching logic.

The AD9558 has six output drivers, arranged into four channels.

Each channel has a dedicated 10-bit programmable post divider.

Channel 0 and Channel 3 have one driver each, and Channel 1

and Channel 2 have two drivers each. Each driver is programmable

either as a single differential or dual single-ended CMOS output.

The clock distribution section operates at up to 1250 MHz.

In differential mode, the output drivers run on a 1.8 V power

supply to offer very high performance with minimal power

consumption. There are two differential modes: LVDS and 1.8 V

HSTL. In 1.8 V HSTL mode, the voltage swing is compatible

with LVPECL. If LVPECL signal levels are required, the designer

can ac-couple the AD9558 output and use Thevenin-equivalent

termination at the destination to drive the LVPECL inputs.

The AD9558 has a system clock multiplier, a digital PLL (DPLL),

and an analog PLL (APLL). The input signal goes first to the DPLL,

which performs the jitter cleaning and most of the frequency

translation. The DPLL features a 30-bit digitally controlled

oscillator (DCO) output that generates a signal in the 175 MHz

to 200 MHz range. The DPLL output goes to an analog integer-N

PLL (APLL), which multiplies the signal up to the 3.35 GHz to

4.05 GHz range. That signal is then sent to the clock distribution

In single-ended mode, each differential output driver can

operate as two single-ended CMOS outputs. OUT0 and OUT5

support either 1.8 V or 3.3 V CMOS operation. OUT1 through

OUT4 support only 1.8 V operation.

Rev. A | Page 29 of 104

AD9558

Data Sheet

Reference Validation Timer

REFERENCE CLOCK INPUTS

Each reference input has a dedicated validation timer. The

validation timer establishes the amount of time that a previously

faulted reference must remain unfaulted before the AD9558

declares it valid. The timeout period of the validation timer is

programmable via a 16-bit register. The 16-bit number stored

in the validation register represents units of milliseconds (ms),

which yields a maximum timeout period of 65,535 ms.

Four pairs of pins provide access to the reference clock receivers.

To accommodate input signals with slow rising and falling edges,

both the differential and single-ended input receivers employ

hysteresis. Hysteresis also ensures that a disconnected or

floating input does not cause the receiver to oscillate.

When configured for differential operation, the input receivers

accommodate either ac- or dc-coupled input signals. The input

receivers are capable of accepting dc-coupled LVDS and 2.5 V

and 3.3 V LVPECL signals. The receiver is internally dc biased

to handle ac-coupled operation, but there is no internal 50 Ω or

100 Ω termination.

It is possible to disable the validation timer by programming the

validation timer to 0b. With the validation timer disabled, the

user must validate a reference manually via the manual reference

validation override controls register (Address 0x0A0B).

Reference Validation Override Control

When configured for single-ended operation, the input

receivers exhibit a pull-down load of 45 kΩ (typical). Three

user-programmable threshold voltage ranges are available for

each single-ended receiver.

The user also has the ability to override the reference validation

logic and can either force an invalid reference to be treated as

valid, or force a valid reference to be treated as an invalid

reference. These controls are in Register 0x0A0B to Register

0x0A0D.

REFERENCE MONITORS

The accuracy of the input reference monitors depends on a

known and accurate system clock period. Therefore, the

functioning of the reference monitors is not operable until the

system clock is stable.

REFERENCE PROFILES

The AD9558 has an independent profile for each reference input.

A profile consists of a set of device parameters such as the R divider

and N divider, among others The profiles allow the user to

prescribe the specific device functionality that should take effect

when one of the input references becomes the active reference.

Reference Period Monitor

Each reference input has a dedicated monitor that repeatedly

measures the reference period. The AD9558 uses the reference

period measurements to determine the validity of the reference

based on a set of user-provided parameters in the profile

register area of the register map.

The AD9558 evaluation software includes a frequency planning

wizard that can configure the profile parameters, given the

input and output frequencies.

The user should not change a profile that is currently in use

because unpredictable behavior may result. The user can either

select free run or holdover mode or invalidate the reference

input prior to changing it.

The monitor works by comparing the measured period of a

particular reference input with the parameters stored in the

profile register assigned to that same reference input. The

parameters include the reference period, an inner tolerance,

and an outer tolerance. A 40-bit number defines the reference

period in units of femtoseconds (fs). The 40-bit range allows for

a reference period entry of up to 1.1 ms. A 20-bit number defines

the inner and outer tolerances. The value stored in the register

is the reciprocal of the tolerance specification. For example, a

tolerance specification of 50 ppm yields a register value of

1/(50 ppm) = 1/0.000050 = 20,000 (0x04E20).

REFERENCE SWITCHOVER

An attractive feature of the AD9558 is its versatile reference

switchover capability. The flexibility of the reference switchover

functionality resides in a sophisticated prioritization algorithm

that is coupled with register-based controls. This scheme

provides the user with maximum control over the state machine

that handles reference switchover.

The use of two tolerance values provides hysteresis for the

monitor decision logic. The inner tolerance applies to a

previously faulted reference and specifies the largest period

tolerance that a previously faulted reference can exhibit before it

qualifies as nonfaulted. The outer tolerance applies to an already

nonfaulted reference. It specifies the largest period tolerance

that a nonfaulted reference can exhibit before being faulted.

The main reference switchover control resides in the loop

mode register (Address 0x0A01). The REF switchover mode

bits (Register 0x0A01, Bits[4:2]) allow the user to select one of

the five operating modes of the reference switchover state machine,

as follows:

•

Automatic revertive mode

Automatic non-revertive mode

Manual with automatic fallback mode

Manual with holdover mode

To produce decision hysteresis, the inner tolerance must be less

than the outer tolerance. That is, a faulted reference must meet

tighter requirements to become nonfaulted than a nonfaulted

reference must meet to become faulted.

Full manual mode (without auto-holdover)

Rev. A | Page 30 of 104

Data Sheet

AD9558

In the automatic modes, a fully automatic priority-based algorithm

selects which reference is the active reference. When programmed

for an automatic mode, the device chooses the highest priority

valid reference. When both references have the same priority,

REFA gets preference over REFB. However, the reference position

is used only as a tie-breaker and does not initiate a reference switch.

A diagram of the DPLL core of the AD9558 appears in Figure 36.

The phase/frequency detector, feedback path, lock detectors,

phase offset, and phase slew rate limiting that comprise this

second generation DPLL are all digital implementations.

The start of the DPLL signal chain is the reference signal, f_R,

which is the frequency of the reference input. A reference

prescaler reduces the frequency of this signal by an integer factor,

R + 1, where R is the 20-bit value stored in the appropriate

profile register and 0 ≤ R ≤ 1,048,575. Therefore, the frequency

at the output of the R-divider (or the input to the time-to-digital

converter (TDC)) is

The following list gives an overview of the five operating modes:

•

Automatic revertive mode. The device selects the highest

priority valid reference and switches to a higher priority

reference if it becomes available, even if the reference in use

is still valid. In this mode, the user reference is ignored.

Automatic non-revertive mode. The device stays with the

currently selected reference as long as it is valid, even if

a higher priority reference becomes available. The user

reference is ignored in this mode.

Manual with automatic fallback mode. The device uses the

user reference for as long as it is valid. If it becomes invalid,

the reference input with the highest priority is chosen in

accordance with the priority-based algorithm.

f_R

f_TDC

=

R +1

A TDC samples the output of the R-divider. The TDC/PFD

produces a time series of digital words and delivers them to the

digital loop filter. The digital loop filter offers the following

advantages:

•

Determination of the filter response by numeric

coefficients rather than by discrete component values

The absence of analog components (R/L/C), which

eliminates tolerance variations due to aging

The absence of thermal noise associated with analog

components

The absence of control node leakage current associated

with analog components (a source of reference feed-

through spurs in the output spectrum of a traditional

analog PLL)

•

Manual with holdover mode. The user reference is the

active reference until it becomes invalid. At that point,

the device automatically goes into holdover.

Manual mode without holdover. The user reference is the

active reference, regardless of whether or not it is valid.

The user also has the option to force the device directly into

holdover or free run operation via the user holdover and user

freerun bits. In free run mode, the free run frequency tuning

word register defines the free run output frequency. In holdover

mode, the output frequency depends on the holdover control

settings (see the Holdover section).

The digital loop filter produces a time series of digital words at

its output and delivers them to the frequency tuning input of a

sigma-delta (Σ-Δ) modulator (SDM). The digital words from

the loop filter steer the DCO frequency toward frequency and

phase lock with the input signal (f_TDC).

Phase Build-Out Reference Switching

The AD9558 supports phase build-out reference switching,

which is the term given to a reference switchover that

completely masks any phase difference between the previous

reference and the new reference. That is, there is virtually no

phase change detectable at the output when a phase build-out

switchover occurs.

The DPLL includes a feedback divider that causes the digital

loop to operate at an integer-plus-fractional multiple. The

output of the DPLL is

FRAC1

MOD1

⎡

⎤

f_{OUT _ DPLL}= f_TDC× (N1 + 1) +

⎢

⎣

⎥

⎦

DIGITAL PLL (DPLL) CORE

where N1 is the 17-bit value stored in the appropriate profile

registers (Register 0x0715 to Register 0x0717 for REFA). FRAC1

and MOD1 are the 24-bit numerators and denominators of the

fractional feedback divider block. The fractional portion of the

feedback divider can be bypassed by setting FRAC1 to 0, but

MOD1 should never be 0.

DPLL Overview

SYSTEM

CLOCK

FREE RUN

×2

TW

FROM

REF

INPUT

MUX

R DIVIDER

(20-BIT)

TUNING

WORD

CLAMP

AND

DIGITAL

LOOP

FILTER

+

FRAC1/

MOD1

The DPLL output frequency is usually 175 MHz to 200 MHz for

optimal performance.

÷N1

HISTORY

17-BIT

INTEGER

24-BIT/24-BIT

RESOLUTION

TO APLL

FROM APLL

Figure 36. Digital PLL Core

Rev. A | Page 31 of 104

AD9558

Data Sheet

TDC/PFD

DPLL Digitally Controlled Oscillator Free Run Frequency

The phase-frequency detector (PFD) is an all-digital block. It

compares the digital output from the TDC (which relates to the

active reference edge) with the digital word from the feedback

block. It uses a digital code pump and digital integrator (rather

than a conventional charge pump and capacitor) to generate the

error signal that steers the DCO frequency toward phase lock.

The AD9558 uses a Σ-Δ modulator (SDM) as a digitally controlled

oscillator (DCO). The DCO free run frequency can be calculated

from the following equation:

2

f_{dco _ freerun}= f_SYS

×

FTW0

8 +

2³⁰

Programmable Digital Loop Filter

where FTW0 is the value in Register 0x0300 to Register 0x0303,

and f_SYSis the system clock frequency. See the System Clock

section for information on calculating the system clock frequency.

The AD9558 loop filter is a third order digital IIR filter that is

analogous to the third order analog loop shown in Figure 37.

R

3

Adaptive Clocking

R

C

3

2

1

The AD9558 can support adaptive clocking applications such as

asynchronous mapping and demapping. In these applications,

the output frequency can be dynamically adjusted by up to

100 ppm from the nominal output frequency without manually

breaking the DPLL loop and reprogramming the part. This

function is supported for REFA only, not REFB.

C

2

Figure 37. Third Order Analog Loop Filter

The AD9558 loop filter block features a simplified architecture

in which the user enters the desired loop characteristics directly

into the profile registers. This architecture makes the calculation

of individual coefficients unnecessary in most cases, while still

offering complete flexibility.

The following registers are used in this function:

•

Register 0x0717 (DPLL N1 divider)

Register 0x0718 to Register 0x071A (DPLL FRAC1 divider)

Register 0x071B to Register 0x071D (DPLL MOD1

divider)

The AD9558 has two preset digital loop filters: high (88.5°) phase

margin and normal (70°) phase margin. The loop filter coefficients

are stored in Register 0x0317 to Register 0x0322 for high phase

margin and Register 0x0323 to Register 0x032E for normal phase

margin. The high phase margin loop filter is intended for

applications in which the closed-loop transfer function must

not have greater than 0.1 dB of peaking.

Writing to these registers requires an I/O update by writing

0x01 to Register 0x0005 before the new values take effect.

To make small adjustments to the output frequency, the user

can vary the FRAC1 and issue an I/O update. The advantage to

using only FRAC1 to adjust the output frequency is that the

DPLL does not briefly enter holdover. Therefore, the FRAC1 bit

can be updated as fast as the phase detector frequency of

the DPLL.

Bit 0 of the following registers selects which filter is used for

each profile: Register 0x070E for Profile A, Register 0x074E for

Profile B, Register 0x078E for Profile C, and Register 0x07CE

for Profile D.

The loop bandwidth for each profile is set in the following

registers: Register 0x070F to Register 0x0711 for Profile A,

Register 0x074F to Register 0x0751 for Profile B, Register 0x078F

to Register 0x0791 for Profile C, and Register 0x07CF to

Register 0x07D1 for Profile D.

Writing to the N1 and MOD1 dividers allows for larger changes

to the output frequency. When the AD9558 detects that the N1

or MOD1 values have changed, it automatically enters and exits

holdover for a brief instant without any disturbance in the

output frequency. This limits how quickly the output frequency

can be adapted.

The two preset conditions should cover all of the intended

applications for the AD9558. For special cases where these

conditions must be modified, the tools for calculating these

coefficients are available by contacting Analog Devices directly.

It is important to realize that the amount of frequency adjustment

is limited to 100 ppm before the output PLL (APLL) needs a

recalibration. Variations that are larger than 100 ppm are

possible, but the ability of the AD9558 to maintain lock over

temperature extremes may be compromised.

It is also important to remember that the rate of change in

output frequency depends on the DPLL loop bandwidth.

Rev. A | Page 32 of 104

Data Sheet

AD9558

it removes one drain bucket from the tub. Note that it is not the

polarity of the phase error sample, but its magnitude relative to

the phase threshold value, that determines whether to fill or drain.

If more filling is taking place than draining, the water level in

the tub eventually rises above the high water mark (+1024), which

causes the phase lock detector to indicate lock. If more draining

is taking place than filling, then the water level in the tub eventually

falls below the low water mark (−1024), which causes the phase

lock detector to indicate unlock. The ability to specify the threshold

level, fill rate, and drain rate enables the user to tailor the operation

of the phase lock detector to the statistics of the timing jitter

associated with the input reference signal.

DPLL Phase Lock Detector

The DPLL contains an all-digital phase lock detector. The user

controls the threshold sensitivity and hysteresis of the phase

detector via the profile registers.

The phase lock detector behaves in a manner analogous to

water in a tub (see Figure 38). The total capacity of the tub is

4096 units with −2048 denoting empty, 0 denoting the 50%

point, and +2048 denoting full. The tub also has a safeguard to

prevent overflow. Furthermore, the tub has a low water mark at

−1024 and a high water mark at +1024. To change the water

level, the user adds water with a fill bucket or removes water

with a drain bucket. The user specifies the size of the fill and

drain buckets via the 8-bit fill rate and drain rate values in the

profile registers.

Note that when the AD9558 enters the free run or holdover

mode, the DPLL phase lock detector indicates an unlocked

state. However, when the AD9558 performs a reference switch,

the lock detector state prior to the switch is preserved during

the transition period.

LOCKED

UNLOCKED

2048

1024

LOCK LEVEL

DPLL Frequency Lock Detector

FILL

DRAIN

RATE

0

The operation of the frequency lock detector is identical to that

of the phase lock detector. The only difference is that the fill or

drain decision is based on the period deviation between the

reference and feedback signals of the DPLL instead of the phase

error at the output of the PFD.

UNLOCK LEVEL

–1024

–2048

Figure 38. Lock Detector Diagram

The water level in the tub is what the lock detector uses to

determine the lock and unlock conditions. When the water level

is below the low water mark (−1024), the detector indicates an

unlock condition. Conversely, when the water level is above the

high water mark (+1024), the detector indicates a lock condition.

When the water level is between the marks, the detector simply

holds its last condition. This concept appears graphically in

Figure 38, with an overlay of an example of the instantaneous

water level (vertical) vs. time (horizontal) and the resulting

lock/unlock states.

The frequency lock detector uses a 24-bit frequency threshold

register specified in units of picoseconds (ps). Thus, the frequency

threshold value extends from 0 μs to 16.777215 μs. It represents

the magnitude of the difference in period between the reference

and feedback signals at the input to the DPLL. For example, if

the reference signal is 1.25 MHz and the feedback signal is

1.38 MHz, the period difference is approximately 75.36 ns

(|1/1,250,000 − 1/1,380,000| ≈ 75.36 ns).

Frequency Clamp

The AD9558 DPLL features a digital tuning word clamp that

ensures that the DPLL output frequency stays within a defined

range. This feature is very useful to eliminate undesirable

behavior in cases where the reference input clocks may be

unpredictable. The tuning word clamp is also useful to

guarantee that the APLL never loses lock by ensuring that the

APLL VCO frequency stays within its tuning range.

During any given PFD cycle, the detector either adds water with

the fill bucket or removes water with the drain bucket (one or

the other but not both). The decision of whether to add or

remove water depends on the threshold level specified by the

user. The phase lock threshold value is a 16-bit number stored

in the profile registers and is expressed in picoseconds (ps).

Thus, the phase lock threshold extends from 0 ns to 65.535 ns

and represents the magnitude of the phase error at the output of

the PFD.

Frequency Tuning Word History

The AD9558 has the ability to track the history of the tuning

word samples generated by the DPLL digital loop filter output.

It does so by periodically computing the average tuning word

value over a user-specified interval. This average tuning word is

used during holdover mode to maintain the average frequency

when no input references are present.

The phase lock detector compares each phase error sample at

the output of the PFD to the programmed phase threshold value.

If the absolute value of the phase error sample is less than or

equal to the programmed phase threshold value, the detector

control logic dumps one fill bucket into the tub. Otherwise,

Rev. A | Page 33 of 104

AD9558

Data Sheet

frequency remains constant. The accuracy of the AD9558 in

holdover mode is dependent on the device programming and

availability of tuning word history.

LOOP CONTROL STATE MACHINE

Switchover

Switchover occurs when the loop controller switches directly

from one input reference to another. The AD9558 handles a

reference switchover by briefly entering holdover mode, loading

the new DPLL parameters, and then immediately recovering.

During the switchover event, however, the AD9558 preserves

the status of the lock detectors to avoid phantom unlock

indications.

Recovery from Holdover

When in holdover mode and a valid reference becomes

available, the device exits holdover operation. The loop state

machine restores the DPLL to closed-loop operation, locks to

the selected reference, and sequences the recovery of all the

loop parameters based on the profile settings for the active

reference.

Holdover

Note that, if the user holdover bit is set, the device does not

automatically exit holdover when a valid reference is available.

However, automatic recovery can occur after clearing the user

holdover bit (Bit 6 in Register 0x0A01).

The holdover state of the DPLL is typically used when none of

the input references are present, although the user can also

manually engage holdover mode. In holdover mode, the output

Rev. A | Page 34 of 104

Data Sheet

AD9558

SYSTEM CLOCK (SYSCLK)

SYSTEM CLOCK INPUTS

The XTAL path enables the connection of a crystal resonator

(typically 10 MHz to 50 MHz) across the XOA and XOB input

pins. An internal amplifier provides the negative resistance

required to induce oscillation. The internal amplifier expects an

AT cut, fundamental mode crystal with a maximum motional

resistance of 100 ꢁ. The following crystals, listed in alphabetical

order, may meet these criteria. Analog Devices, Inc., does not

guarantee their operation with the AD9558 nor does Analog

Devices endorse one crystal supplier over another. The AD9558

reference design uses a 49.152 MHz crystal, which is high

performance, low spurious content, and readily available.

Functional Description

The SYSCLK circuit provides a low jitter, stable, high frequency

clock for use by the rest of the chip. The XOA and XOB pins

connect to the internal SYSCLK multiplier. The SYSCLK multiplier

can synthesize the system clock by connecting a crystal resonator

across the XOA and XOB input pins or by connecting a low

frequency clock source. The optimal signal for the system clock

input is either a crystal in the 50 MHz range or an ac-coupled

square wave with a 1 V p-p amplitude.

System Clock Period

•

AVX/Kyocera CX3225SB

ECS ECX-32

Epson/Toyocom TSX-3225

Fox FX3225BS

NDK NX3225SA

Siward SX-3225

For the AD9558 to accurately measure the frequency of incoming

reference signals, the user must enter the system clock period

into the nominal system clock period registers (Register 0x0103

to Register 0x0105). The SYSCLK period is entered in units of

nanoseconds (ns).

System Clock Details

Suntsu SCM10B48-49.152 MHz

There are two internal paths for the SYSCLK input signal: low

frequency non-xtal (LF) and crystal resonator (XTAL).

SYSTEM CLOCK MULTIPLIER

The SYSCLK PLL multiplier is an integer-N design with an

integrated VCO. It provides a means to convert a low frequency

clock input to the desired system clock frequency, f_SYS(750 MHz

to 805 MHz). The SYSCLK PLL multiplier accepts input signals

of between 3.5 MHz and 600 MHz, but frequencies that are in

excess of 150 MHz require the system clock P-divider to ensure

compliance with the maximum PFD rate (150 MHz). The PLL

contains a feedback divider (N) that is programmable for divide

values between 4 and 255.

Using a TCXO for the system clock is a common use for the LF

path. Applications requiring DPLL loop bandwidths of less

than 50 Hz or high stability in holdover require a TCXO. As an

alternative to the 49.152 MHz crystal for these applications, the

AD9558 reference design uses a 19.2 MHz TCXO, which offers

excellent holdover stability and a good combination of low jitter

and low spurious content.

The 1.8 V differential receiver connected to the XOA and XOB

pins is self-biased to a dc level of ~1 V, and ac coupling is strongly

recommended. When a 3.3 V CMOS oscillator is in use, it is

important to use a voltage divider to reduce the input high

voltage to a maximum of 1.8 V. See Figure 34 for details on

connecting a 3.3 V CMOS TCXO to the system clock input.

sysclk _ Ndiv

f_SYS= f_OSC

×

sysclk _ Pdiv

where:

_OSCis the frequency at the XOA and XOB pins.

f

sysclk_Ndiv is the value stored in Register 0x0100.

sysclk_Pdiv is the system clock P divider that is determined by

the setting of Register 0x0101[2:1].

The non-xtal input path permits the user to provide an LVPECL,

LVDS, 1.8 V CMOS, or sinusoidal low frequency clock for

multiplication by the integrated SYSCLK PLL. The LF path handles

input frequencies from 3.5 MHz up to 100 MHz. However,

when using a sinusoidal input signal, it is best to use a frequency

that is in excess of 20 MHz. Otherwise, the resulting low slew

rate can lead to substandard noise performance. Note that the

non-xtal path includes an optional 2× frequency multiplier to

double the rate at the input to the SYSCLK PLL and potentially

reduce the PLL in-band noise. However, to avoid exceeding the

maximum PFD rate of 150 MHz, the 2× frequency multiplier is

only for input frequencies that are below 75 MHz.

If the system clock doubler is used, the value of sysclk_Ndiv

should be half of its original value.

The system clock multiplier features a simple lock detector that

compares the time difference between the reference and feedback

edges. The most common cause of the SYSCLK multiplier not

locking is a non-50% duty cycle at the SYSCLK input while the

system clock doubler is enabled.

The non-xtal path also includes an input divider (M) that is

programmable for divide-by-1, -2, -4, or -8. The purpose of the

divider is to limit the frequency at the input to the PLL to less

than 150 MHz (the maximum PFD rate).

Rev. A | Page 35 of 104

AD9558

Data Sheet

System Clock Stability Timer

stable operating condition is detected, a timer is run for the

duration that is stored in the system clock stability period

registers. If at any time during this waiting period, the condition

is violated, the timer is reset and halted until a stable condition

is reestablished. After the specified period elapses, the AD9558

reports the system clock as stable.

Because the reference monitors depend on the system clock

being at a known frequency, it is important that the system

clock be stable before activating the monitors. At initial power-

up, the system clock status is not known, and, therefore, it is

reported as being unstable. After the part has been programmed,

the system clock PLL (if enabled) eventually locks. When a

Rev. A | Page 36 of 104

Data Sheet

AD9558

OUTPUT PLL (APLL)

A diagram of the output PLL (APLL) is shown in Figure 39.

Calibration of the APLL must be performed at startup and

when the nominal input frequency to the APLL changes by

more than 100 ppm, although the APLL maintains lock

over voltage and temperature extremes without recalibration.

Calibration centers the dc operating voltage at the input to the

APLL VCO.

INTEGER DIVIDER

÷N2

OUTPUT PLL DIVIDER (APLL)

TO CLOCK

DISTRIBUTION

PFD

CP

LF

FROM DPLL

VCO2

3.35GHz TO 4.05GHz

APLL calibration at startup can be accomplished during initial

register loading by following the instructions in the Device

Register Programming When Using a Register Setup File

section of this datasheet.

LF_VCO2

LF CAP

Figure 39. Output PLL Block Diagram

The APLL provides the frequency upconversion from the DPLL

output to the 3.35 GHz to 4.05 GHz range, while also providing

noise filtering on the DPLL output. The APLL reference input is

the output of the DPLL. The feedback divider is an integer divider.

The loop filter is partially integrated with the one external 6.8 nF

capacitor. The nominal loop bandwidth for this PLL is 250 kHz,

with 68 degrees of phase margin.

To recalibrate the APLL VCO after the chip has been running,

the user should first input the new settings (if any). Ensure that

the system clock is still locked and stable, and that the DPLL is

in free run mode with the free run tuning word set to the same

output frequency that is used when the DPLL is locked.

Use the following steps to calibrate the APLL VCO:

1. Ensure that the system clock is locked and stable.

2. Ensure that the DPLL is in user free run mode

(Register 0x0A01[5] = 1b), and the free run tuning word is set.

3. Write Register 0x0405 = 0x20.

4. Write Register 0x0005 = 0x01.

5. Write Register 0x0405 = 0x21.

The frequency wizard that is included in the evaluation software

configures the APLL, and the user should not need to make

changes to the APLL settings. However, there may be special cases

where the user may wish to adjust the APLL loop bandwidth to

meet a specific phase noise requirement. The easiest way to change

the APLL loop BW is to adjust the APLL charge pump current

in Register 0x0400. There is sufficient stability (68ꢂ of phase

margin) in the APLL default settings to permit a broad range of

adjustment without causing the APLL to be unstable. The user

should contact Analog Devices directly if more detail is needed.

6. Write Register 0x0005 = 0x01.

Monitor the APLL status using Bit 2 in Register 0x0D01.

Rev. A | Page 37 of 104

AD9558

Data Sheet

CLOCK DISTRIBUTION

1

OUT0

÷M0

MAX

RF

1.25GHz

FRAME SYNC

MODE ONLY

1

DIVIDER 1

÷3 TO ÷11

OUT1

OUT2

÷M1

÷M2

FROM APLL

(3.35GHz TO 4.05GHz)

1

MAX

1.25GHz

OUT3

RF

DIVIDER 2

÷3 TO ÷11

1

OUT4

1

CHIP RESET

SYNC/SOFT_SYNC

CHANNEL

SYNC

SYNC SIGNAL TO

÷M3

M0 TO M3 DIVIDERS

BLOCK

FRAME SYNC

÷M3b

×2

FRAME SYNC ENGAGED SIGNAL

Fsync_ALIGN_METHOD

FRAME

SYNC

BLOCK

1

OUT5

1

SELECTED INPUT FRAME PULSE

FRAME

SYNC

MONITOR

OUT0, OUT1, OUT2, OUT3, OUT4: 360kHz TO 1.25GHz; OUT5: 352Hz TO 1.25GHz.

Figure 40. Clock Distribution Block Diagram

All CMOS drivers feature a CMOS drive strength that allows

the user to choose between a strong, high performance CMOS

driver, or a lower power setting with less EMI and crosstalk.

The best setting is application dependent.

CLOCK DIVIDERS

The channel divider blocks, M0, M1, M2, M3, and M3b, are

10-bit integer dividers with a divide range of 1 to 1023. The

channel divider block contains duty cycle correction that

guarantees 50% duty cycle for both even and odd divide ratios.

For applications where LVPECL levels are required, the user

should choose the HSTL mode, and ac-couple the output signal.

See the Input/Output Termination Recommendations section

for recommended termination schemes.

OUTPUT POWER-DOWN

The output drivers can be individually powered down.

OUTPUT ENABLE

CLOCK DISTRIBUTION SYNCHRONIZATION

Each of the output channels offers independent control of enable/

disable functionality via the distribution enable register. The

distribution outputs use synchronization logic to control

enable/disable activity to avoid the production of runt pulses

and ensure that outputs with the same divide ratios become

active/inactive in unison.

Divider Synchronization

The dividers in the clock distribution channels can be

synchronized with each other.

At power-up, the clock dividers are held static until a sync signal

is initiated by the channel SYNC block. The following are

possible sources of a SYNC signal, and these settings are found

in Register 0x0500:

OUTPUT MODE

The user has independent control of the operating mode of each of

the four output channels via the output clock distribution registers

(Address 0x0500 to Address 0x0515). The operating mode

control includes

•

Direct sync via Bit 2 of Register 0x0500

Direct sync via a sync op code (0xA1) in the EEPROM

storage sequence during EEPROM loading

DPLL phase or frequency lock

•

Logic family and pin functionality

Output drive strength

Output polarity

Divide ratio

Phase of each output channel

A rising edge of the selected reference input

SYNC

The

A multifunction pin configured for the SYNC signal

The APLL lock detect signal gates the SYNC signal from the

channel sync block shown in Figure 40. The channel dividers

receive a SYNC signal from the channel SYNC block only if the

APLL is calibrated and locked, unless the APLL locked

controlled sync bit (Register 0x0405[3]) is set.

Channel 0 and Channel 3 provide 3.3 V CMOS, in addition

to 1.8 V CMOS modes. Channel 1 and Channel 2 have 1.8 V

CMOS, LVDS, and HSTL modes.

Rev. A | Page 38 of 104

Data Sheet

AD9558

A channel can be programmed to ignore the sync function by

setting the mask Channel x sync bits in Register 0x0500[7:4].

When programmed to ignore the sync, the channel ignores

both the user initiated sync signal and the zero delay initiated

sync signals, and the channel divider starts toggling, provided

that the APLL is calibrated and locked, or if the APLL locked

controlled sync bit (Register 0x0405[3]) is set.

If the output SYNC function is to be controlled using an M pin,

use the following steps:

1. First, enable the M pins by writing Register 0x0200 = 0x01.

2. Issue an I/O update (Register 0x0005 = 0x01).

3. Set the appropriate M pin function.

If this process is not followed, a SYNC pulse is issued

automatically.

Rev. A | Page 39 of 104

AD9558

Data Sheet

FRAME SYNCHRONIZATION

The AD9558 provides frame synchronization fuction/mode.

With this function, the AD9558 can take a pair consisting of a

reference clock and a 2 kHz or 8 kHz frame pulse as input signals

and generate a pair consisting of a synchronized output clock

and an output frame pulse while the output frame pulse is

synchronized with the input frame pulse also. The reference

clock is used to synthesize the output clock and output frame

pulse through DPLL/output PLL/distribution and the input frame

pulse is used to control the phase of the output frame pulse.

CLOCK OUTPUTS IN FRAME SYNCHRONIZATION

MODE

The AD9558 has six outputs (OUT0 to OUT5). In frame sync

mode, the OUT0 and OUT5 form the pair of output clock

(OUT0) and output frame pulse (OUT5). The frequency of

OUT0 is required to have the integer relation with the frequency of

the OUT5 (f_OUT0= M × f_OUT5). The rest of the outputs (OUT1 to

OUT4) do not participate in frame synchronization mode and

are programmed and synchronized with each other the same as

Frame synchronization is not supported in the soft or hard pin

control mode.

SYNC

in normal mode (except for

function). However, OUT1

to OUT4 should not be synchronized with the OUT0/OUT5.

REFERENCE CONFIGURATION IN FRAME

SYNCHRONIZATION MODE

CONTROL REGISTERS FOR FRAME

SYNCHRONIZATION MODE

In frame synchronization mode, four AD9558 reference inputs

(REFA/REFB/REFC/REFD) are arranged into two pairs of signals:

REFA and REFC form a pair of input clock/input frame pulse

with REFA as the input clock, and REFC as the frame pulse.

REFB and REFD form the second pair of input clock/ input

frame pulse with REFB as the input clock and REFD is the frame

pulse. During reference switchover, only two input clocks, REFA

and REFB, are assigned with a priority index. The two frame

pulses, REFC and REFD, are not assigned with the priority index

(the priority register bits in the profiles associated with input

frame pulse are ignored). Each pair of input clock/ frame pulse

participates in the reference selection as a group, and the valid

state and priority of the pair are used in determining the reference

selection. The priority of the pair is indicated by the priority

index of the input clock in the pair.

The frame synchronization function is enabled by setting

Register 0x0640[0] to 1b. When Register 0x0640[0] = 1b, the

following occurs:

•

The frame synchronization control bits (Register

0x0641[3:0]) are enabled.

SYNC

•

The

SYNC

pin switches from

function to frame

SYNC

function. In frame synchronization mode,

cannot be used as clock distribution synchronization

function as it is in normal mode. Instead it is used as the

frame synchronization arm function.

When the AD9558 is in frame synchronization mode, the frame

SYNC

synchronization function can be armed by either the

or the arm soft Fsync bit (Register 0x0641[0]), which is selected

by the Fsync arm method bit (Register 0x0641[1]. A value of 0b

Users have the option to either include or exclude the valid state

of input frame pulse in the reference selection by programming

the validate Fsync reference bit (Register 0x0641[3]). When

Register 0x0641[3] is programmed to 1b, the valid state of the

input frame pulse and the valid state of the paired input clock

are logically ANDed and the result is used to indicate the valid

state of the pair. When validate Fsync ref is programmed to 0b,

the valid state of the input frame pulse is excluded in reference

selection and only the valid state of the input clock in the pair is

used to indicate the valid state of the pair. The valid pair with the

higher priority index is selected as the DPLL reference and input

frame pulse to control the phase of the output frame pulse. If no

pair is valid, the selection does not change and DPLL is switched

to either holdover or free run mode, and the phase of the output

frame pulse is not controlled by any of the input frame pulses.

The five reference switchover modes for frame synchronization

mode is the same as for normal mode.

SYNC

(which is the default) selects the

SYNC

pin as the arm method.

SYNC

= low means armed;

If

is selected as arm method,

if the register is selected as arm method, Register 0x0641[0] = 1b

means armed. ARM means that once armed, the output frame

pulse is edge aligned with the paired output clock edge after the

rising edge of the input frame pulse.

LEVEL SENSITIVE MODE AND ONE-SHOT MODE

The frame synchronization can operate in level sensitive or one-

shot mode as determined by the Fsync one shot bit (Register

0x0641[2]). When in level sensitive mode (Register 0x0641[2] =

0b) and the frame sync ARM signal is high, each rising edge of

the selected input frame pulse signal is used to control the

phase of the output frame pulse. When in one-shot mode, after

the frame sync ARM signal is high, only the immediate next

rising edge of the selected input frame pulse signal is used to

control the phase of the output frame pulse (one time phase

alignment). After that, the phase of the output frame pulse is

not controlled by the selected input frame pulse. Instead, it

follows the phase of the input clock of M3 divider. In either

alignment control mode, the resolution of the phase realignment

between the input frame pulse and the output frame pulse is

one clock cycle of the paired clock output.

Rev. A | Page 40 of 104

Data Sheet

AD9558

This means that in frame synchronization mode, the total divide

ratio between the RF divider and OUT5 is M0 × M3 × M3b.

M3b DIVIDER/OUT5 PROGRAMMING IN FRAME

SYNCHRONIZATION MODE

The other important change is that the sync signal for the M3b

divider is no longer the standard clock distribution sync. It is

controlled by a signal derived from the input frame pulse.

In frame synchronization mode, the clock distribution signal path

for OUT5 is changed, as follows: the OUT5 signal goes from the RF

divider to the M0 divider, and then to the M3 and M3b dividers.

ACTIVE SYNC

OUPUT CLOCK

(OUT0)

FRAME CLOCK INPUT

(REFC/REFD)

ENABLE Fsync

(REGISTER 0x0640[0] = 1b)

FRAME SYNC ARM

(REGISTER OR SYNC PIN)

FRAME CLOCK

(OUT5)

NOTES

1. AFTER THE FRAME SYNC IS ARMED, THE FRAME CLOCK OUTPUT IS SYNCHRONIZED TO THE FRAME CLOCK INPUT.

THE SKEW BETWEEN THE FRAME CLOCK INPUT AND FRAME CLOCK OUTPUT IS 15ns (NOMINAL) PLUS A DELAY OF 0.5 TO 1.5 OUTPUT CLOCK CYCLES.

Figure 41. Frame Synchronization in Level Sensitive Mode

ACTIVE SYNC

OUPUT CLOCK

(OUT0)

FRAME CLOCK INPUT

(REFC/REFD)

ENABLE Fsync

(REGISTER 0x0640[0] = 1b)

FRAME SYNC ARM

(REGISTER OR SYNC PIN)

FRAME CLOCK

(OUT5)

NOTES

1. AFTER THE FRAME SYNC IS ARMED, THE FRAME CLOCK OUTPUT IS SYNCHRONIZED TO THE FRAME CLOCK INPUT.

THE SKEW BETWEEN THE FRAME CLOCK INPUT AND FRAME CLOCK OUTPUT IS 15ns (NOMINAL) PLUS 0.5 TO 1.5 OUTPUT CLOCK CYCLES.

Figure 42. Frame Synchronization in One Shot Mode

ENABLE Fsync

M3 DIVIDER

M3b DIVIDER

OUT5

OUT0

ENABLE

Fsync

RF

DIVIDER 1

FROM

APLL

LOGIC 0

M0 DIVIDER

ENABLE Fsync

CLOCK

DISTRIBUTION

SYNC LOGIC

DELAY

OUTPUT

SYNC

OUTPUT

SYNC

PULSE

LEVEL

(RETIMED)

FRAME SYNC

PULSE GENERATOR

ENABLE Fsync

FRAME SYNC PULSE INPUT (ON REFC OR REFD)

Fsync_arm (FROM EITHER THE SYNC PIN OR THE Arm Soft Fsync BIT IN REGISTER 0x0641[0])

NOTES

1. THE ENABLE Fsync FUNCTION IN THE DIAGRAM IS CONTROLLED BY REGISTER 0x0640[0].

Figure 43. Frame Synchronization Implementation

Rev. A | Page 41 of 104

AD9558

Data Sheet

STATUS AND CONTROL

10—The IRQ pin is Logic 0 when deasserted and Logic 1 when

asserted.

11—The IRQ pin is Logic 1 when deasserted and Logic 0 when

asserted. (This is the default operating mode.)

MULTIFUNCTION PINS (M7 TO M0)

The AD9558 has eight digital CMOS I/O pins (M7 to M0)

that are configurable for a variety of uses. To use these

functions, the user must enable them by writing a 0x01 to

Register 0x0200. The function of these pins is programmable via

the register map. Each pin can control or monitor an assortment

of internal functions based on the contents of Register 0x0201 to

Register 0x0208.

The AD9558 asserts the IRQ pin when any bit in the IRQ monitor

register (Address 0x0D02 to Address 0x0D07) is a Logic 1. Each

bit in this register is associated with an internal function that is

capable of producing an interrupt. Furthermore, each bit of the

IRQ monitor register is the result of a logical AND of the associated

internal interrupt signal and the corresponding bit in the IRQ

mask register (Address 0x020A to Address 0x020E). That is, the

bits in the IRQ mask register have a one-to-one correspondence

with the bits in the IRQ monitor register. When an internal

function produces an interrupt signal and the associated IRQ

mask bit is set, the corresponding bit in the IRQ monitor register

is set. The user should be aware that clearing a bit in the IRQ

mask register removes only the mask associated with the

internal interrupt signal. It does not clear the corresponding bit

in the IRQ monitor register.

To monitor an internal function with a multifunction pin, write

a Logic 1 to the most significant bit of the register associated

with the desired multifunction pin. The value of the seven least

significant bits of the register defines the control function, as

shown in Table 129.

To control an internal function with a multifunction pin, write a

Logic 0 to the most significant bit of the register associated with

the desired multifunction pin. The monitored function depends

on the value of the seven least significant bits of the register, as

shown in Table 130.

If more than one multifunction pin operates on the same

control signal, then internal priority logic ensures that only one

multifunction pin serves as the signal source. The selected pin is

the one with the lowest numeric suffix. For example, if both M0

and M3 operate on the same control signal, then M0 is used as

the signal source and the redundant pins are ignored.

The IRQ pin is the result of a logical OR of all the IRQ monitor

register bits. Thus, the AD9558 asserts the IRQ pin as long as

any IRQ monitor register bit is a Logic 1. Note that it is possible

to have multiple bits set in the IRQ monitor register. Therefore,

when the AD9558 asserts the IRQ pin, it may indicate an interrupt

from several different internal functions. The IRQ monitor

register provides the user with a means to interrogate the

AD9558 to determine which internal function produced the

interrupt.

At power-up, the multifunction pins can be used to force the

device into certain configurations as defined in the initial pin

programming section. This functionality, however, is valid only

during power-up or following a reset, after which the pins can

be reconfigured via the serial programming port or via the

EEPROM.

Typically, when the IRQ pin is asserted, the user interrogates

the IRQ monitor register to identify the source of the interrupt

request. After servicing an indicated interrupt, the user should

clear the associated IRQ monitor register bit via the IRQ

clearing register (Address 0x0A04 to Address 0x0A09). The bits

in the IRQ clearing register have a one-to-one correspondence with

the bits in the IRQ monitor register. Note that the IRQ clearing

register is autoclearing. The IRQ pin remains asserted until the

user clears all of the bits in the IRQ monitor register that

indicate an interrupt.

If the output SYNC function is to be controlled using an M pin,

1. First, enable the M pins by writing Register 0x0200 = 0x01.

2. Issue an I/O update (Register 0x0005 = 0x01).

3. Set the appropriate M pin function.

If this process is not followed, a SYNC pulse is issued automatically.

IRQ Pin

The AD9558 has a dedicated interrupt request (IRQ) pin.

Bits[1:0] of the IRQ pin output mode register (Register 0x0209)

control how the IRQ pin asserts an interrupt based on the value

of the two bits, as follows:

It is also possible to collectively clear all of the IRQ monitor

register bits by setting the clear all IRQs bit in the reset function

register (Register 0x0A03, Bit 1). Note that this is an autoclearing

bit. Setting this bit results in deassertion of the IRQ pin.

Alternatively, the user can program any of the multifunction

pins to clear all IRQs. This allows the user to clear all IRQs by

means of a hardware pin rather than by using a serial I/O port

operation.

00—The IRQ pin is high impedance when deasserted and active

low when asserted and requires an external pull-up resistor.

01—The IRQ pin is high impedance when deasserted and active

high when asserted and requires an external pull-down

resistor.

Rev. A | Page 42 of 104

Data Sheet

AD9558

WATCHDOG TIMER

EEPROM

EEPROM Overview

The watchdog timer is a general purpose programmable timer.

To set the timeout period, the user writes to the 16-bit watchdog

timer register (Address 0x0210 to Address 0x0211). A value of

0b in this register disables the timer. A nonzero value sets the

timeout period in milliseconds (ms), giving the watchdog timer

a range of 1 ms to 65.535 sec. The relative accuracy of the timer

is approximately 0.1% with an uncertainty of 0.5 ms.

The AD9558 contains an integrated 2048-byte, electrically

erasable, programmable read-only memory (EEPROM).

The AD9558 can be configured to perform a download at

power-up via the multifunction pins (M3 and M2), but uploads

and downloads can also be done on demand via the EEPROM

control registers (Address 0x0E00 to Address 0x0E03).

If enabled, the timer runs continuously and generates a timeout

event when the timeout period expires. The user has access to

the watchdog timer status via the IRQ mechanism and the

multifunction pins (M7 to M0). In the case of the multifunction

pins, the timeout event of the watchdog timer is a pulse that lasts

32 system clock periods.

The EEPROM provides the ability to upload and download

configuration settings to and from the register map. Figure 44

shows a functional diagram of the EEPROM.

Register 0x0E10 to Register 0x0E3F represent a 53-byte EEPROM

storage sequence area (referred to as the “scratch pad” in this

section) that enables the user to store a sequence of instructions

for transferring data to the EEPROM from the device settings

portion of the register map. Note that the default values for

these registers provide a sample sequence for saving/retrieving

all of the AD9558 EEPROM-accessible registers. Figure 44 shows

the connectivity between the EEPROM and the controller that

manages data transfer between the EEPROM and the register map.

There are two ways to reset the watchdog timer (thereby

preventing it from causing a timeout event). The first is by

writing a Logic 1 to the autoclearing clear watchdog bit in the

reset functions register (Register 0x0A03, Bit 0). Alternatively,

the user can program any of the multifunction pins to reset the

watchdog timer. This allows the user to reset the timer by means

of a hardware pin rather than by using a serial I/O port operation.

The controller oversees the process of transferring EEPROM data

to and from the register map. There are two modes of operation

handled by the controller: saving data to the EEPROM (upload

mode) or retrieving data from the EEPROM (download mode).

In either case, the controller relies on a specific instruction set.

DATA

EEPROM

ADDRESS

POINTER

M3

M2

EEPROM

CONTROLLER

EEPROM

(0x000 TO 0x1FF)

SCRATCH PAD

ADDRESS

POINTER

DEVICE

SETTINGS

ADDRESS

POINTER

DEVICE

SCRATCH PAD

(EEPROM STORAGE SEQUENCE)

(0x0E10 TO 0x0E45)

SETTINGS

(0x0004 TO 0x0A0D)

SERIAL

INPUT/OUTPUT

PORT

REGISTER MAP

Figure 44. EEPROM Functional Diagram

Rev. A | Page 43 of 104

AD9558

Data Sheet

Table 21. EEPROM Controller Instruction Set

Instruction

Value (Hex)

Bytes

Required

Instruction Type

Description

0x00 to 0x7F

Data

3

A data instruction tells the controller to transfer data to or from the device settings

part of the register map. A data instruction requires two additional bytes that

together, indicate a starting address in the register map. Encoded in the data

instruction is the number of bytes to transfer, which is one more than the

instruction value.

0x80

I/O update

Calibrate

1

When the controller encounters this instruction while downloading from the

EEPROM, it issues a soft I/O update.

When the controller encounters this instruction while downloading from the

EEPROM, it initiates a system clock calibration sequence.

When the controller encounters this instruction while downloading from the

EEPROM, it issues a sync pulse to the output distribution synchronization.

B1 to CF are condition instructions and correspond to Condition 1 through

Condition 31, respectively. B0 is the null condition instruction. See the EEPROM

Conditional Processing section for details.

0xA0

0xA1

Distribution sync

Condition

0xB0 to 0xCF

0xFE

0xFF

Pause

End

1

When the controller encounters this instruction in the EEPROM storage sequence

area while uploading to the EEPROM, it holds both the scratch pad address pointer

and the EEPROM address pointer at its last value. This allows storage of more than

one instruction sequence in the EEPROM. Note that the controller does not copy

this instruction to the EEPROM during upload.

When the controller encounters this instruction in the the EEPROM storage

sequence area while uploading to the EEPROM, it resets both the register area

address pointer and the EEPROM address pointer and then enters an idle state.

When the controller encounters this instruction while downloading from the

EEPROM, it resets the EEPROM address pointer and then enters an idle state.

Note that, in the EEPROM scratch pad, the two registers that

comprise the address portion of a data instruction have the

MSB of the address in the D7 position of the lower register

address. The bit weight increases from left to right, from the

lower register address to the higher register address. Furthermore,

the starting address always indicates the lowest numbered

register map address in the range of bytes to transfer. That is,

the controller always starts at the register map target address

and counts upward regardless of whether the serial I/O port is

operating in I²C, SPI LSB-first, or SPI MSB-first mode.

EEPROM Instructions

Table 21 lists the EEPROM controller instruction set. The

controller recognizes all instruction types whether it is in

upload or download mode, except for the pause instruction,

which is recognized only in upload mode.

The I/O update, calibrate, distribution sync, and end instruc-

tions are mostly self-explanatory. The others, however, warrant

further detail, as described in the following paragraphs.

Data instructions are those that have a value from 0x000 to

0x7FF. A data instruction tells the controller to transfer data

between the EEPROM and the register map. The controller

requires the following two parameters to carry out the data

transfer:

As part of the data transfer process during an EEPROM upload,

the controller calculates a 1-byte checksum and stores it as the

final byte of the data transfer. As part of the data transfer process

during an EEPROM download, however, the controller again

calculates a 1-byte checksum value but compares the newly

calculated checksum with the one that was stored during the

upload process. If an upload/download checksum pair does not

match, the controller sets the EEPROM fault status bit. If the

upload/download checksums match for all data instructions

encountered during a download sequence, the controller sets

the EEPROM complete status bit.

•

The number of bytes to transfer

The register map target address

The controller decodes the number of bytes to transfer directly

from the data instruction itself by adding one to the value of the

instruction. For example, the 1A data instruction has a decimal

value of 26; therefore, the controller knows to transfer 27 bytes

(one more than the value of the instruction). When the

controller encounters a data instruction, it knows to read the

next two bytes in the scratch pad because these contain the

register map target address.

Condition instructions are those that have a value from B0 to

CF. The B1 to CF condition instructions represent Condition 1

to Condition 31, respectively. The B0 condition instruction is

special because it represents the null condition (see the

EEPROM Conditional Processing section).

Rev. A | Page 44 of 104

Data Sheet

AD9558

A pause instruction, like an end instruction, is stored at the

end of a sequence of instructions in the scratch pad. When the

controller encounters a pause instruction during an upload

sequence, it keeps the EEPROM address pointer at its last value.

This way the user can store a new instruction sequence in the

scratch pad and upload the new sequence to the EEPROM. The

new sequence is stored in the EEPROM address locations

immediately following the previously saved sequence. This

process is repeatable until an upload sequence contains an end

instruction. The pause instruction is also useful when used in

conjunction with condition processing. It allows the EEPROM

to contain multiple occurrences of the same registers, with each

occurrence linked to a set of conditions (see the EEPROM

Conditional Processing section).

transfers data associated with an active register, it actually

transfers the buffered contents of the register (refer to the

Buffered/Active Registers section for details on the difference

between buffered and active registers). This allows for the transfer

of nonzero autoclearing register contents.

Note that conditional processing (see the EEPROM Conditional

Processing section) does not occur during an upload sequence.

EEPROM Download

An EEPROM download results in data transfer from the

EEPROM to the device register map. To download data,

the user sets the autoclearing load from the EEPROM bit

(Register 0x0E03, Bit 1). This commands the controller to

initiate the EEPROM download process. During download, the

controller reads the EEPROM data byte-by-byte, incrementing

the EEPROM address pointer as it goes, until it reaches an end

instruction. As the controller reads the EEPROM data, it

executes the stored instructions, which includes transferring

stored data to the device settings portion of the register map

when it encounters a data instruction.

EEPROM Upload

To upload data to the EEPROM, the user must first ensure that

the write enable bit (Register 0x0E00, Bit 0) is set. Then, on

setting the autoclearing save to EEPROM bit (Register 0x0E02,

Bit 0), the controller initiates the EEPROM data storage process.

Uploading EEPROM data requires that the user first write an

instruction sequence into the scratch pad registers. During the

upload process, the controller reads the scratch pad data byte-

by-byte, starting at Register 0x0E10 and incrementing the scratch

pad address pointer, as it goes, until it reaches a pause or end

instruction.

Note that conditional processing (see the EEPROM Conditional

Processing section) is applicable only when downloading.

Automatic EEPROM Download

RESET

Following a power-up, an assertion of the

pin, or a soft

reset (Register 0x0000, Bit 5 = 1), if the PINCONTROL pin is

low, and M3 and M2 are either high or low (see Table 22), the

instruction sequence stored in the EEPROM executes automatically

with one of eight conditions. If M3 and M2 are left floating and

the PINCONTROL pin is low, the EEPROM is bypassed and

the factory defaults are used. In this way, a previously stored set

of register values downloads automatically on power-up or with

a hard or soft reset. See the EEPROM Conditional Processing

section for details regarding conditional processing and the way

it modifies the download process.

As the controller reads the scratch pad data, it transfers the

data from the scratch pad to the EEPROM (byte-by-byte) and

increments the EEPROM address pointer accordingly, unless

it encounters a data instruction. A data instruction tells the

controller to transfer data from the device settings portion of

the register map to the EEPROM. The number of bytes to transfer

is encoded within the data instruction, and the starting address

for the transfer appears in the next two bytes in the scratch pad.

When the controller encounters a data instruction, it stores the

instruction in the EEPROM, increments the EEPROM address

pointer, decodes the number of bytes to be transferred, and

increments the scratch pad address pointer. Then it retrieves the

next two bytes from the scratch pad (the target address) and

increments the scratch pad address pointer by 2. Next, the

controller transfers the specified number of bytes from the

register map (beginning at the target address) to the EEPROM.

Table 22. EEPROM Setup

M3

M2

ID

1

2

3

4

0

5

6

7

8

EEPROM Download?

Yes, EEPROM Condition 1

Yes, EEPROM Condition 2

Yes, EEPROM Condition 3

Yes, EEPROM Condition 4

No

Yes, EEPROM Condition 5

Yes, EEPROM Condition 6

Yes, EEPROM Condition 7

Yes, EEPROM Condition 8

Low

Open

High

Low

Open

High

Low

Open

High

When it completes the data transfer, the controller stores an extra

byte in the EEPROM to serve as a checksum for the transferred

block of data. To account for the checksum byte, the controller

increments the EEPROM address pointer by one more than the

number of bytes transferred. Note that, when the controller

Open

High

Rev. A | Page 45 of 104

AD9558

Data Sheet

EEPROM Conditional Processing

The condition tag board is a table maintained by the EEPROM

controller. When the controller encounters a condition instruc-

tion, it decodes the B1 through CF instructions as Condition = 1

through Condition = 8, respectively, and tags that particular

condition in the condition tag board. However, the B0 condition

instruction decodes as the null condition, for which the controller

clears the condition tag board; and subsequent download

instructions execute unconditionally (until the controller

encounters a new condition instruction).

The condition instructions allow conditional execution of

EEPROM instructions during a download sequence. During

an upload sequence, however, they are stored as is and have

no effect on the upload process.

Note that, during EEPROM downloads, the condition instructions

themselves and the end instruction always execute unconditionally.

Conditional processing makes use of two elements: the condition

(from Condition 1 to Condition 8) and the condition tag board.

The relationships among the condition, the condition tag board,

and the EEPROM controller appear schematically in Figure 45.

During download, the EEPROM controller executes or skips

instructions depending on the value of the condition and the

contents of the condition tag board. Note, however, that the

condition instructions and the end instruction always execute

unconditionally during download. If condition = 0, then all

instructions during download execute unconditionally. If

Condition ≠ 0 and there are any tagged conditions in the condition

tag board, then the controller executes instructions only if the

condition is tagged. If the condition is not tagged, then the

controller skips instructions until it encounters a condition

instruction that decodes as a tagged condition. Note that the

condition tag board allows for multiple conditions to be tagged

at any given moment. This conditional processing mechanism

enables the user to have one download instruction sequence

with many possible outcomes depending on the value of the

condition and the order in which the controller encounters

condition instructions.

The condition is a 4-bit value with 16 possibilities. Condition = 0

is the null condition. When the null condition is in effect, the

EEPROM controller executes all instructions unconditionally.

Condition 9 through Condition 15 are not accessible using the

M pins. The remaining eight possibilities (that is, Condition = 1

through Condition = 8) modify the EEPROM controller’s

handling of a download sequence. The condition originates

from one of two sources (see Figure 45), as follows:

•

FncInit, Bits[3:0], which is the state of the M2 and M3

multifunction pins at power-up (see Table 22)

Register 0x0E01, Bits[3:0]

•

If Register 0x0E01, Bits[3:0] ≠ 0, then the condition is the value

that is stored in Register 0x0E01, Bits[3:0]; otherwise, the condition

is FncInit, Bits[3:0]. Note that a nonzero condition that is present

in Register 0x0E01, Bits[3:0] takes precedence over FncInit,

Bits[3:0].

M3 AND M2 PINS

(3-LEVEL LOGIC)

CONDITION

TAG BOARD

1

2

3

4

5

6

7

EXAMPLE

CONDITION 3 AND

8

9

10 11 12 13 14 15

REGISTER

FncInit, BITS[3:0]

4

0x0E01, BITS[3:0]

CONDITION 13

ARE TAGGED

16 17 18 19 20 21 22 23

24 25 26 27 28 29 30 31

4

IF B1 ≤ INSTRUCTION ≤ CF,

THEN TAG DECODED CONDITION

IF {0E01, BITS[3:0] ≠ 0}

CONDITION = 0E01, BITS[3:0]

ELSE

CONDITION = FncInit, BITS[3:0]

ENDIF

IF INSTRUCTION = B0,

THEN CLEAR ALL TAGS

EEPROM

WATCH FOR

OCCURRENCE OF

CONDITION

4

COND ITION

INSTRUCTIONS

DURING

STORE CONDITION

INSTRUCTIONS AS

DOWNLOAD.

THEY ARE READ FROM

THE SCRATCH PAD.

IF {NO TAGS} OR {CONDITION = 0}

EXECUTE INSTRUCTIONS

ELSE

IF {CONDITION ISTAGGED}

EXECUTE INSTRUCTIONS

ELSE

CONDITION

EXECUTE/SKIP

HANDLER

INSTRUCTION(S)

SKIP INSTRUCTIONS

ENDIF

SCRATCH

PAD

ENDIF

UPLOAD

PROCEDURE

DOWNLOAD

PROCEDURE

EEPROM CONTROLLER

Figure 45. EEPROM Conditional Processing

Rev. A | Page 46 of 104

Data Sheet

AD9558

Table 23 lists a sample EEPROM download instruction sequence.

It illustrates the use of condition instructions and how they alter

the download sequence. The table begins with the assumption

that no conditions are in effect. That is, the most recently executed

condition instruction is either B0 or no conditional instructions

have been processed.

Reprogram the device control registers for the next desired

setup. Then store a new upload sequence in the EEPROM

scratch pad with the following general form:

1. Condition instruction (B0)

2. The next desired condition instruction (B1 to CF, but

different from the one used during the previous upload to

identify a new setup)

3. Data instructions (to save the register contents) along with

any required calibrate and/or I/O update instructions

4. Pause instruction (FE)

Table 23. EEPROM Conditional Processing Example

Instruction Action

0x08

0x01

0x00

0xB1

0x19

0x04

0x00

0xB2

0xB3

0x07

0x05

0x00

0x0A

Transfer the system clock register contents,

regardless of the current condition.

With the upload sequence written to the scratch pad, perform

an EEPROM upload (Register 0x0E02, Bit 0).

Tag Condition 1.

Transfer the clock distribution register contents

only if tag condition = 1.

Repeat the process of programming the device control registers

for a new setup, storing a new upload sequence in the EEPROM

scratch pad (Step 1 through Step 4), and executing an EEPROM

upload (Register 0x0E02, Bit 0) until all of the desired setups

have been uploaded to the EEPROM.

Tag Condition 2.

Tag Condition 3.

Transfer the reference input register contents only

if tag condition = 1, 2, or 3.

Note that, on the final upload sequence stored in the scratch

pad, the pause instruction (FE) must be replaced with an end

instruction (FF).

Calibrate the system clock only if tag condition =

1, 2, or 3.

To download a specific setup on demand, first store the condition

associated with the desired setup in Register 0x0E01, Bits[4:0].

Then perform an EEPROM download (Register 0x0E03, Bit 1).

Alternatively, to download a specific setup at power-up, apply

the required logic levels necessary to encode the desired condition

on the M2 and M3 multifunction pins. Then power up the device;

an automatic EEPROM download occurs. The condition (as

established by the M2 and M3 multifunction pins) guides the

download sequence and results in a specific setup.

0xB0

0x80

Clear the tag condition board.

Execute an I/O update, regardless of the value of

the tag condition.

0x0A

Calibrate the system clock, regardless of the value

of the tag condition.

Storing Multiple Device Setups in EEPROM

Conditional processing makes it possible to create a number of

different device setups, store them in EEPROM, and download

a specific setup on demand. To do so, first program the device

control registers for a specific setup. Then, store an upload

sequence in the EEPROM scratch pad with the following

general form:

Keep in mind that the number of setups that can be stored

in the EEPROM is limited. The EEPROM can hold a total of

2048 bytes. Each nondata instruction requires one byte of

storage. Each data instruction, however, requires N + 4 bytes of

storage, where N is the number of transferred register bytes and

the other four bytes include the data instruction itself (one

byte), the target address (two bytes), and the checksum

calculated by the EEPROM controller during the upload

sequence (one byte).

1. Condition instruction (B1 to CF) to identify the setup with

a specific condition (1 to 31)

2. Data instructions (to save the register contents) along with

any required calibrate and/or I/O update instructions

3. Pause instruction (FE)

With the upload sequence written to the scratch pad, perform

an EEPROM upload (Register 0x0E02, Bit 0).

Rev. A | Page 47 of 104

AD9558

Data Sheet

Programming the EEPROM to Configure an M Pin to

Control Synchronization of Clock Distribution

The default EEPROM loading sequence from Register 0x0E10 to

Register 0x0E16 is unchanged. The following steps must be

inserted into the EEPROM storage sequence:

A special EEPROM loading sequence is required to use the

EEPROM to load the registers and to use an M pin to

enable/disable outputs.

1. R0x0E17 = 0x00 # Write one byte

2. R0x0E18 = 0x02 # at Register 0x0200

3. R0x0E19 = 0x00 #

4. R0x0E1A = 0x80 # Op code for I/O

Update R0x0E1B = 0x10 # Transfer 17 instead of 18 bytes

5. R0x0E1C = 0x02 # Transfer starts at Register address

6. R0x0E1D = 0x01 # 0x0201 instead of 0x0200

To control the output sync function by using an M pin, perform

the following steps:

1. Enable the M pins by writing Register 0x0200 = 0x01.

2. Issue an I/O update (Register 0x0005 = 0x01).

3. Set the appropriate M pin function (see the Clock

Distribution Synchronization section for details).

The rest of the EEPROM loading sequence is the same as the

default EEPROM loading sequence, except that the register

address of the EEPROM storage sequence is shifted down four

bytes from the default. For example,

If this sequence is not performed, a SYNC pulse is issued

automatically.

The following changes write Register 0x0200 first and then issue

an I/O update before writing the remaining M pin configuration

registers in Register 0x0201 to Register 0x0208.

•

R0x0E1E = default value of Register 0x0E1A = 0x2E

R0x0E1F = default value of Register 0x0E1B = 0x03

R0x0E20 = default value of Register 0x0E1C = 0x00

…

R0x0E40 = default value of Register 0x0E1C = 0x3C = 0xFF

(end of data)

Rev. A | Page 48 of 104

Data Sheet

AD9558

SERIAL CONTROL PORT

The AD9558 serial control port is a flexible, synchronous serial

communications port that provides a convenient interface to

many industry-standard microcontrollers and microprocessors.

The AD9558 serial control port is compatible with most

synchronous transfer formats, including IꢀC, Motorola SPI, and

Intel SSR protocols. The serial control port allows read/write

access to the AD9558 register map.

CS

(chip select) pin is an active low control that gates read

The

and write operations. This pin is internally connected to a 30 kΩ

CS

pull-up resistor. When

is high, the SDO and SDIO pins go

into a high impedance state.

SPI Mode Operation

The SPI port supports both 3-wire (bidirectional) and 4-wire

(unidirectional) hardware configurations and both MSB-first

and LSB-first data formats. Both the hardware configuration

and data format features are programmable. By default, the

AD9558 uses the bidirectional MSB-first mode. The reason that

bidirectional is the default mode is so that the user can still

write to the device, if it is wired for unidirectional operation, to

switch to unidirectional mode.

In SPI mode, single or multiple byte transfers are supported.

The SPI port configuration is programmable via Register 0x0000.

This register is integrated into the SPI control logic rather than

in the register map and is distinct from the I²C Register 0x0000.

It is also inaccessible to the EEPROM controller.

Although the AD9558 supports both the SPI and I²C serial port

protocols, only one or the other is active following power-up (as

determined by the M0 and M1 multifunction pins during the

startup sequence). That is, the only way to change the serial port

protocol is to reset the device (or cycle the device power supply).

CS

Assertion (active low) of the

pin initiates a write or read

operation to the AD9558 SPI port. For data transfers of three

bytes or fewer (excluding the instruction word), the device

CS

supports the

stalled high mode (see Table 25). In this mode,

SPI/I²C PORT SELECTION

CS

the

pin can be temporarily deasserted on any byte boundary,

allowing time for the system controller to process the next byte.

Because the AD9558 supports both SPI and IꢀC protocols, the

active serial port protocol depends on the logic state of the

PINCONTROL, M1, and M0 pins. The PINCONTROL pin

must be low, and the state of the M0 and M1 pins determines

the I²C address, or if SPI mode is enabled. See Table 24 for the

I²C address assignments.

CS

can be deasserted only on byte boundaries, however. This

applies to both the instruction and data portions of the transfer.

During stall high periods, the serial control port state machine

enters a wait state until all data is sent. If the system controller

decides to abort a transfer midstream, then the state machine must

CS

be reset either by completing the transfer or by asserting the

pin for at least one complete SCLK cycle (but less than eight

Table 24. SPI/IꢀC Serial Port Setup

M1

M0

SPI/I²C

CS

SCLK cycles). Deasserting the

pin on a nonbyte boundary

Low

SPI

terminates the serial transfer and flushes the buffer.

Low

Open

High

Low

Open

High

Low

I²C, 1101000

I²C, 1101001

I²C, 1101010

I²C, 1101011

I²C, 1101100

I²C, 1101101

I²C, 1101110

I²C, 1101111

In streaming mode (see Table 25), any number of data bytes can

be transferred in a continuous stream. The register address is

Open

High

CS

automatically incremented or decremented. must be deasserted

at the end of the last byte that is transferred, thereby ending the

streaming mode.

Open

High

Table 25. Byte Transfer Count

W1

W0

Bytes to Transfer

SPI SERIAL PORT OPERATION

Pin Descriptions

0

1

2

The SCLK (serial clock) pin serves as the serial shift clock. This

pin is an input. SCLK synchronizes serial control port read and

write operations. The rising edge SCLK registers write data bits,

and the falling edge registers read data bits. The SCLK pin

supports a maximum clock rate of 40 MHz.

1

0

1

3

Streaming mode

Communication Cycle—Instruction Plus Data

The SPI protocol consists of a two-part communication cycle.

The first part is a 16-bit instruction word that is coincident with

the first 16 SCLK rising edges and a payload. The instruction

word provides the AD9558 serial control port with information

The SDIO (serial data input/output) pin is a dual-purpose pin

and acts as either an input only (unidirectional mode) or as

both an input and an output (bidirectional mode). The AD9558

default SPI mode is bidirectional.

W

regarding the payload. The instruction word includes the R/

bit that indicates the direction of the payload transfer (that is, a

read or write operation). The instruction word also indicates

the number of bytes in the payload and the starting register

address of the first payload byte.

The SDO (serial data output) pin is useful only in unidirectional

I/O mode. It serves as the data output pin for read operations.

Rev. A | Page 49 of 104

AD9558

Data Sheet

Write

SPI Instruction Word (16 Bits)

W

If the instruction word indicates a write operation, the payload

is written into the serial control port buffer of the AD9558. Data

bits are registered on the rising edge of SCLK. The length of the

transfer (1, 2, or 3 bytes or streaming mode) depends on the W0

and W1 bits (see Table 25) in the instruction byte. When not

The MSB of the 16-bit instruction word is R/ , which indicates

whether the instruction is a read or a write. The next two bits, W1

and W0, indicate the number of bytes in the transfer (see Table 25).

The final 13 bits are the register address (A12 to A0), which

indicates the starting register address of the read/write operation

(see Table 27).

CS

streaming,

can be deasserted after each sequence of eight

bits to stall the bus (except after the last byte, where it ends the

cycle). When the bus is stalled, the serial transfer resumes when

SPI MSB-/LSB-First Transfers

The AD9558 instruction word and payload can be MSB first or

LSB first. The default for the AD9558 is MSB first. The LSB-first

mode can be set by writing a 1 to Register 0x0000, Bit 6.

Immediately after the LSB-first bit is set, subsequent serial

control port operations are LSB first.

CS

is asserted. Deasserting the

pin on a nonbyte boundary

resets the serial control port. Reserved or blank registers are not

skipped over automatically during a write sequence. Therefore,

the user must know what bit pattern to write to the reserved

registers to preserve proper operation of the part. Generally, it

does not matter what data is written to blank registers, but it is

customary to write 0s.

When MSB-first mode is active, the instruction and data bytes

must be written from MSB to LSB. Multibyte data transfers in

MSB-first format start with an instruction byte that includes the

register address of the most significant payload byte. Subsequent

data bytes must follow in order from high address to low

address. In MSB-first mode, the serial control port internal

address generator decrements for each data byte of the multi-

byte transfer cycle.

Most of the serial port registers are buffered (refer to the

Buffered/Active Registers section for details on the difference

between buffered and active registers). Therefore, data written into

buffered registers does not take effect immediately. An

additional operation is required to transfer buffered serial

control port contents to the registers that actually control the

device. This is accomplished with an I/O update operation,

which is performed in one of two ways. One is by writing a

Logic 1 to Register 0x0005, Bit 0 (this bit is autoclearing). The

other is to use an external signal via an appropriately

programmed multifunction pin. The user can change as many

register bits as desired before executing an I/O update. The I/O

update operation transfers the buffer register contents to their

active register counterparts.

When Register 0x0000, Bit 6 = 1 (LSB first), the instruction and

data bytes must be written from LSB to MSB. Multibyte data

transfers in LSB-first format start with an instruction byte that

includes the register address of the least significant payload byte

followed by multiple data bytes. The serial control port internal

byte address generator increments for each byte of the multibyte

transfer cycle.

For multibyte MSB-first (default) I/O operations, the serial

control port register address decrements from the specified

starting address toward Address 0x0000. For multibyte LSB-first

I/O operations, the serial control port register address

increments from the starting address toward Address 0x1FFF.

Reserved addresses are not skipped during multibyte I/O

operations; therefore, the user should write the default value to

a reserved register and 0s to unmapped registers. Note that it is

more efficient to issue a new write command than to write the

default value to more than two consecutive reserved (or

unmapped) registers.

Read

The AD9558 supports the long instruction mode only. If the

instruction word indicates a read operation, the next N × 8

SCLK cycles clock out the data from the address specified in the

instruction word. N is the number of data bytes read and

depends on the W0 and W1 bits of the instruction word. The

readback data is valid on the falling edge of SCLK. Blank

registers are not skipped over during readback.

A readback operation takes data from either the serial control

port buffer registers or the active registers, as determined by

Register 0x0004, Bit 0.

Table 26. Streaming Mode (No Addresses Are Skipped)

Write Mode Address Direction Stop Sequence

LSB First

MSB First

Increment

Decrement

0x0000 ... 0x1FFF

0x1FFF ... 0x0000

Table 27. Serial Control Port, 16-Bit Instruction Word, MSB First

MSB

LSB

I0

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

A4

I3

I2

I1

R/W

W1

W0

A12

A11

A10

A9

A8

A7

A6

A5

A3

A2

A1

A0

Rev. A | Page 50 of 104

Data Sheet

AD9558

CS

SCLK DON'T CARE

DON'T CARE

SDIO

R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA

Figure 46. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data

CS

SCLK

DON'T CARE

R/W W1 W0 A12 A11A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DON'T CARE

SDIO

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

REGISTER (N) DATA REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA

SDO DON'T CARE

16-BIT INSTRUCTION HEADER

DON'T

CARE

Figure 47. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data

t_DS

t_HIGH

t_S

t_C

t_CLK

t_DH

t_LOW

CS

DON'T CARE

SCLK

SDIO

R/W

W1

W0

A12

A11

A10

A9

A8

A7

A6

A5

D4

D3

D2

D1

D0

DON'T CARE

Figure 48. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements

CS

SCLK

t_DV

SDIO

SDO

DATA BIT N

DATA BIT N – 1

Figure 49. Timing Diagram for Serial Control Port Register Read

CS

SCLK

SDIO

DON'T CARE

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA

Figure 50. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data

Rev. A | Page 51 of 104

AD9558

Data Sheet

t_S

t_C

CS

t_CLK

t_HIGH

t_LOW

t_DS

SCLK

SDIO

t_DH

BIT N

BIT N + 1

Figure 51. Serial Control Port Timing—Write

Table 28. Serial Control Port Timing

Parameter

Description

t_DS

t_DH

t_CLK

t_S

Setup time between data and the rising edge of SCLK

Hold time between data and the rising edge of SCLK

Period of the clock

Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle)

Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle)

Minimum period that SCLK should be in a logic high state

t_C

t_HIGH

t_LOW

t_DV

Minimum period that SCLK should be in a logic low state

SCLK to valid SDIO and SDO (see Figure 49)

Rev. A | Page 52 of 104

Data Sheet

AD9558

The transfer of data is shown in Figure 52. One clock pulse is

I²C SERIAL PORT OPERATION

generated for each data bit transferred. The data on the SDA

line must be stable during the high period of the clock. The

high or low state of the data line can change only when the

clock signal on the SCL line is low.

The I²C interface has the advantage of requiring only two control

pins and is a de facto standard throughout the I²C industry.

However, its disadvantage is programming speed, which is

400 kbps maximum. The AD9558 IꢀC port design is based on the

IꢀC fast mode standard; therefore, it supports both the 100 kHz

standard mode and 400 kHz fast mode. Fast mode imposes a

glitch tolerance requirement on the control signals. That is, the

input receivers ignore pulses of less than 50 ns duration.

SDA

SCL

The AD9558 IꢀC port consists of a serial data line (SDA) and a

serial clock line (SCL). In an IꢀC bus system, the AD9558 is

connected to the serial bus (data bus SDA and clock bus SCL)

as a slave device; that is, no clock is generated by the AD9558.

The AD9558 uses direct 16-bit memory addressing instead of

traditional 8-bit memory addressing.

DATA LINE

STABLE;

CHANGE

OF DATA

ALLOWED

DATA VALID

Figure 52. Valid Bit Transfer

Start/stop functionality is shown in Figure 53. The start

condition is characterized by a high-to-low transition on the

SDA line while SCL is high. The start condition is always

generated by the master to initialize a data transfer. The stop

condition is characterized by a low-to-high transition on the

SDA line while SCL is high. The stop condition is always

generated by the master to terminate a data transfer. Every byte

on the SDA line must be eight bits long. Each byte must be

followed by an acknowledge bit; bytes are sent MSB first.

The AD9558 allows up to seven unique slave devices to occupy

the I²C bus. These are accessed via a 7-bit slave address that is

transmitted as part of an I²C packet. Only the device that has a

matching slave address responds to subsequent I²C commands.

Table 24 lists the supported device slave addresses.

I²C Bus Characteristics

A summary of the various I²C protocols appears in Table 29.

The acknowledge bit (A) is the ninth bit attached to any 8-bit

data byte. An acknowledge bit is always generated by the

receiving device (receiver) to inform the transmitter that the

byte has been received. It is done by pulling the SDA line low

during the ninth clock pulse after each 8-bit data byte.

Table 29. I²C Bus Abbreviation Definitions

Abbreviation

Definition

S

Start

Sr

P

Repeated start

Stop

A

The nonacknowledge bit ( ) is the ninth bit attached to any 8-

A

W

R

Acknowledge

Nonacknowledge

Write

bit data byte. A nonacknowledge bit is always generated by the

receiving device (receiver) to inform the transmitter that the

byte has not been received. It is done by leaving the SDA line

high during the ninth clock pulse after each 8-bit data byte.

Read

SDA

SCL

S

P

START CONDITION

STOP CONDITION

Figure 53. Start and Stop Conditions

MSB

SDA

SCL

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

3 TO 7

8

9

3 TO 7

8

9

10

P

1

2

1

2

S

Figure 54. Acknowledge Bit

Rev. A | Page 53 of 104

AD9558

Data Sheet

per transfer is unrestricted. In write mode, the first two data

Data Transfer Process

bytes immediately after the slave address byte are the internal

memory (control registers) address bytes, with the high address

byte first. This addressing scheme gives a memory address of up

to ꢀ¹⁶− 1 = 65,535. The data bytes after these two memory address

bytes are register data written to or read from the control registers.

In read mode, the data bytes after the slave address byte are

register data written to or read from the control registers.

The master initiates data transfer by asserting a start condition.

This indicates that a data stream follows. All I2C slave devices

connected to the serial bus respond to the start condition.

The master then sends an 8-bit address byte over the SDA line,

W

consisting of a 7-bit slave address (MSB first) plus an R/ bit.

This bit determines the direction of the data transfer, that is,

whether data is written to or read from the slave device (0 =

write, 1 = read).

When all data bytes are read or written, stop conditions are

established. In write mode, the master (transmitter) asserts

a stop condition to end data transfer during the 10^thclock pulse

following the acknowledge bit for the last data byte from the slave

device (receiver). In read mode, the master device (receiver)

receives the last data byte from the slave device (transmitter) but

does not pull SDA low during the ninth clock pulse. This is known

as a nonacknowledge bit. By receiving the nonacknowledge bit,

the slave device knows that the data transfer is finished and

enters idle mode. The master then takes the data line low

during the low period before the 10^thclock pulse, and high

during the 10^thclock pulse to assert a stop condition.

The peripheral whose address corresponds to the transmitted

address responds by sending an acknowledge bit. All other

devices on the bus remain idle while the selected device waits

W

for data to be read from or written to it. If the R/ bit is 0, the

master (transmitter) writes to the slave device (receiver). If the

W

R/ bit is 1, the master (receiver) reads from the slave device

(transmitter).

The format for these commands is described in the Data Transfer

Format section.

Data is then sent over the serial bus in the format of nine clock

pulses, one data byte (eight bits) from either master (write mode)

or slave (read mode) followed by an acknowledge bit from the

receiving device. The number of bytes that can be transmitted

A start condition can be used in place of a stop condition.

Furthermore, a start or stop condition can occur at any time,

and partially transferred bytes are discarded.

MSB

SDA

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

3 TO 7

8

9

3 TO 7

8

9

10

P

1

2

1

2

SCL

S

Figure 55. Data Transfer Process (Master Write Mode, 2-Byte Transfer)

SDA

ACK FROM

MASTER RECEIVER

NON-ACK FROM

MASTER RECEIVER

SCL

3 TO 7

8

9

3 TO 7

8

9

10

P

1

2

1

2

S

Figure 56. Data Transfer Process (Master Read Mode, 2-Byte Transfer)

Rev. A | Page 54 of 104

Data Sheet

AD9558

Data Transfer Format

Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.

S

Slave

address

W

A

RAM address

high byte

A

RAM address

low byte

A

RAM

Data 0

A

RAM

Data 1

A

RAM

Data 2

A

P

Send byte format—the send byte protocol is used to set up the register address for subsequent reads.

Slave address RAM address high byte RAM address low byte

S

W

A

P

Receive byte format—the receive byte protocol is used to read the data byte(s) from RAM starting from the current address.

Slave address RAM Data 0 RAM Data 1 RAM Data 2

S

R

A

P

Read byte format—the combined format of the send byte and the receive byte.

S

Slave

Address

W

A

RAM

Address

High Byte

A

RAM

Address

Low Byte

A

Sr Slave

R

A

RAM

Data 0

A

RAM

Data 1

A

RAM

Data 2

A

P

Address

I²C Serial Port Timing

SDA

t_LOW

t_R

t_{SU; DAT}

t_BUF

t_{HD; STA}

t_R

t_F

t_SP

t_F

SCL

t_{SU; STA}

t_{SU; STO}

t_{HD; STA}

t_HIGH

t_{HD; DAT}

S

Sr

S

P

Figure 57. I²C Serial Port Timing

Table 30. IꢀC Timing Definitions

Parameter

Description

f_SCL

Serial clock

t_BUF

Bus free time between stop and start conditions

Repeated hold time start condition

Repeated start condition setup time

Stop condition setup time

Data hold time

Date setup time

t_{HD; STA}

t_{SU; STA}

t_{SU; STO}

t_{HD; DAT}

t_{SU; DAT}

t_LOW

SCL clock low period

t_HIGH

SCL clock high period

t_R

t_F

Minimum/maximum receive SCL and SDA rise time

Minimum/maximum receive SCL and SDA fall time

t_SP

Pulse width of voltage spikes that must be suppressed by the input filter

Rev. A | Page 55 of 104

AD9558

Data Sheet

PROGRAMMING THE I/O REGISTERS

The register map spans an address range from 0x0000 through

0x0E3C. Each address provides access to 1 byte (eight bits) of

data. Each individual register is identified by its four-digit

hexadecimal address (for example, Register 0x0A10). In some

cases, a group of addresses collectively defines a register.

REGISTER ACCESS RESTRICTIONS

Read and write access to the register map may be restricted

depending on the register in question, the source and direction

of access, and the current state of the device. Each register can

be classified into one or more access types. When more than

one type applies, the most restrictive condition is the one that

applies.

In general, when a group of registers defines a control

parameter, the LSB of the value resides in the D0 position of the

register with the lowest address. The bit weight increases right

to left, from the lowest register address to the highest register

address.

When access is denied to a register, all attempts to read the

register return a 0 byte, and all attempts to write to the register

are ignored. Access to nonexistent registers is handled in the

same way as for a denied register.

Note that the EEPROM storage sequence registers (Address

0x0E10 to Address 0x0E3C) are an exception to the above

convention (see the EEPROM Instructions section).

Regular Access

Registers with regular access do not fall into any other category.

Both read and write access to registers of this type can be from

either the serial ports or the EEPROM controller. However, only

one of these sources can have access to a register at any given

time (access is mutually exclusive). When the EEPROM controller

is active, in either load or store mode, it has exclusive access to

these registers.

BUFFERED/ACTIVE REGISTERS

There are two copies of most registers: buffered and active. The

value in the active registers is the one that is in use. The buffered

registers are the ones that take effect the next time the user

writes 0x01 to the I/O update register (Register 0x0005).

Buffering the registers allows the user to update a group of

registers (like the digital loop filter coefficients) at the same

time, which avoids the potential of unpredictable behavior in

the part. Registers with an L in the option column are live,

meaning that they take effect the moment the serial port

transfers that data byte.

Read-Only Access

An R in the option column of the register map identifies read-

only registers. Access is available at all times, including when

the EEPROM controller is active. Note that read-only registers

(R) are inaccessible to the EEPROM, as well.

AUTOCLEAR REGISTERS

Exclusion from EEPROM Access

An A in the option column of the register map identifies an

autoclear register. Typically, the active value for an autoclear

register takes effect following an I/O update. The bit is cleared

by the internal device logic upon completion of the prescribed

action.

An E in the option column of the register map identifies a

register with contents that are inaccessible to the EEPROM.

That is, the contents of this type of register cannot be

transferred directly to the EEPROM or vice versa. Note that

read-only registers (R) are inaccessible to the EEPROM, as well.

Rev. A | Page 56 of 104

Data Sheet

AD9558

THERMAL PERFORMANCE

Table 31. Thermal Parameters for the 64-Lead LFCSP Package

Symbol

Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board¹

Value²Unit

θ_JA

Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air)

Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)

Junction-to-ambient thermal resistance, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air)

Junction-to-board thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-8 (still air)

Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1

Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air)

21.7

18.9

16.9

11.3

1.2

°C/W

θ_JMA

θ_JB

θ_JC

Ψ_JT

0.1

¹The exposed pad on the bottom of the package must be soldered to ground to achieve the specified thermal performance.

²Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the

application to determine if they are similar to those assumed in these calculations.

The AD9558 is specified for a case temperature (T_CASE). To ensure

that T_CASEis not exceeded, an airflow source can be used. Use

the following equation to determine the junction temperature

on the application PCB:

Values of θ_JAare provided for package comparison and PCB

design considerations. θ_JAcan be used for a first order approx-

imation of T_Jby the equation

T_J= T_A+ (θ_JA× PD)

T_J= T_CASE+ (Ψ_JT× PD)

where T_Ais the ambient temperature (°C).

where:

Values of θ_JCare provided for package comparison and PCB

design considerations when an external heat sink is required.

T_Jis the junction temperature (°C).

T_CASEis the case temperature (°C) measured by the customer at

Values of θ_JBare provided for package comparison and PCB

design considerations.

the top center of the package.

Ψ_JTis the value as indicated in Table 31.

PD is the power dissipation (see Table 3).

Rev. A | Page 57 of 104

AD9558

Data Sheet

POWER SUPPLY PARTITIONS

The AD9558 power supplies are divided into four groups:

DVDD3, DVDD, AVDD3, and AVDD. All power and ground

pins should be connected, even if certain blocks of the chip are

powered down.

The ADP7104 is another good choice for converting 3.3 V to

1.8 V. The close-in noise of the ADP7104 is lower than that of

the ADP222; therefore, it may be better suited for applications

where close-in phase noise is critical and the AD9557 DPLL loop

bandwidth is <50 Hz. In such cases, all 1.8 V supplies can be

connected to one ADP7104.

RECOMMENDED CONFIGURATION FOR 3.3 V

SWITCHING SUPPLY

Use of Ferrite Beads on 1.8 V Supplies

A popular power supply arrangement is to power the AD9558

with the output of a 3.3 V switching power supply.

To ensure the very best output-to-output isolation, one ferrite

bead should be used instead of a bypass capacitor for each of

the following AVDD pins: Pin 12, Pin 22, Pin 29, and Pin 30. The

ferrite beads should be placed in between the 1.8 V LDO output

and each pin listed above. Ferrite beads that have low (<0.7 Ω)

dc resistance and approximately 600 Ω impedance at 100 MHz

are suitable for this application.

When the AD9558 is powered using 3.3 V switching power

supplies, all of the 3.3 V supplies can be connected to the 3.3 V

switcher output, and a 0.1 ꢃF bypass capacitor should be placed

adjacent to each 3.3 V power supply pin.

CONFIGURATION FOR 1.8 V SUPPLY

When 1.8 V supplies are preferred, it is recommended that an

LDO regulator, such as the ADP222, be used to generate the

1.8 V supply from the 3.3 V supply.

See Table 2 for the current consumed by each group. Refer to

Figure 20, Figure 21, and Figure 22 for information on the

power consumption vs. output frequency.

The ADP222 offers excellent power supply rejection in a small

(2 mm × 2 mm) package. It has two 1.8 V outputs. One output

can be used for the DVDD pins (Pin 6, Pin 34, and Pin 35), and

the other output can drive the AVDD pins.

Rev. A | Page 58 of 104

Data Sheet

AD9558

PIN PROGRAM FUNCTION DESCRIPTION

The AD9558 supports both hard pin and soft pin program

function with the on-chip ROM containing the predefined

configurations. When a pin program function is enabled and

initiated, the selected predefined configuration is transferred

from the ROM to the corresponding registers to configure the

part into the desired state.

•

RF divider register

Clock distribution channel divider register

All configurations are set to support one single system clock

frequency as 786.432 MHz (16× the default 49.152 MHz system

clock reference frequency).

Four Different System Clock PLL Configurations

OVERVIEW OF ON-CHIP ROM FEATURES

•

REF = 49.152 MHz XO (×2 on, N = 8)

REF = 49.152 MHz XTAL (×2 on, N = 8)

REF = 24.756 MHz XTAL (×2 on, N = 16)

REF = 98.304 MHz XO (×2 off, N = 8)

Input/Output Frequency Translation Configuration

The AD9558 has one on-chip ROM that contains a total of 256

different input-output frequency translation configurations for

independent selection of 16 input frequencies and 16 output

frequencies. Each input/output frequency translation configuration

assumes that all input frequencies are the same and all the output

frequencies are the same. Each configuration reprograms the

following registers/parameters:

Four Different DPLL Loop Bandwidths

1 Hz, 10 Hz, 50 Hz, 100 Hz

DPLL Phase Margin

•

Normal phase margin (70°)

High phase margin (88.5°)

•

Reference input period register

Reference divider R register

Digital PLL feedback divider register (Fractional Part

FRAC1, Modulus Part MOD1 and Integer Part N1) free run

Tuning word register

The ROM also contains an APLL VCO calibration bit. This bit

is used to program Register 0x0405[0] (from 0) to 1 to generate

a low-high transition to automatically initiate APLL VCO cal.

•

Output PLL feedback divider N2 register

Table 32. Preset Input Frequencies for Hard Pin and Soft Pin Programming

Soft Pin Program

PINCONTROL = Low

Register 0x0C01[3:0]

Hard Pin Program

PINCONTROL = High

Freq ID

Frequency (MHz)

0.008

19.44

25

125

156.7072

622.08

625

644.53125

657.421875

660.184152

669.3266

672.1627

690.569

693.48299

693.482991

698.81236

Frequency Description

8 kHz

19.44 MHz

25 MHz

125 MHz

156..25 MHz × 1027/1024

622.08 MHz

625 MHz

625 MHz × 33/32

657.421875 MHz

657.421875 MHz × 239/238

622.08 MHz × 255/238

622.08 MHz × 255/236

644.53125 MHz × 255/238

644.53125 MHz × 255/237

622.08 × 255/237

M5 Pin

M4 Pin

M0 Pin

B3

0

1

B2

0

1

0

1

B1

0

1

0

1

0

1

0

1

B0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

0

½

1

0

½

1

0

½

1

0

½

1

0

½

1

0

½

1

8

9

0

½

10

11

12

13

14

15

0

½

1

0

Rev. A | Page 59 of 104

AD9558

Data Sheet

Table 33. Preset Output Frequencies for Hard Pin and Soft Pin Programming

Soft Pin Program

PINCONTROL = Low,

Register 0x0C01[3:0]

Hard Pin Program

PINCONTROL = High

Freq ID Frequency (MHz) Frequency Description

M3

0

M2

0

M1

B7

0

B6

0

1

0

1

B5

0

1

0

1

0

1

0

1

B4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

19.44

19.44 MHz

0

½

1

0

½

1

0

½

1

0

½

1

25

25 MHz

2

125

125 MHz

0

3

4

156.7071

622.08

156.25 MHz × 1027/1024

622.08 MHz

½

1

0

½

1

5

625

625 MHz

6

7

8

9

10

11

12

13

14

15

644.53125

657.421875

660.184152

666.5143

669.3266

672.1627

690.5692

693.4830

698.8124

704.380580

625 MHz × 33/32

657.421875 MHz

657.421875 MHz × 239/238

622.08 MHz × 255/238

622.08 MHz × 255/237

622.08 MHz × 255/236

644.53125 MHz × 255/238

644.53125 MHz × 255/237

622.08 MHz × 255/237

657.421875 MHz × 255/238

0

1

½

0

½

1

0

Table 34. System Clock Configuration in Hard Pin and Soft Pin Programming Modes

Equivalent

System Clock

PLL Register

Settings

Hard Pin Program

PINCONTROL = High,

IRQ Pin

Soft Pin Program

PINCONTROL = Low,

Register 0x0C02[1:0]

Freq ID Frequency (MHz) System Clock Configuration

IRQ Pin

Bit 1

Bit 0

0

1

2

3

49.152

24.576

98.304

XTAL mode, doubler on, N = 8

XTAL mode off, doubler on, N = 8

XTAL mode, doubler on, N = 16

XTAL mode off, doubler off, N = 8

0

½

1

N/A

0

1

0

1

0

1

0001, 0000, 1000

The system clock configuration is controlled by the state of the

IRQ pin at startup (see Table 34 for details). The digital PLL

loop bandwidth, reference input frequency accuracy tolerance

ranges, and DPLL phase margin selection are not available in

hard pin programming mode unless the user uses the serial port

to change their default values.

HARD PIN PROGRAMMING MODE

The state of the PINCONTROL pin at power-up controls whether

or not the chip is in hard pin programming mode. Setting the

PINCONTROL pin high disables the I²C protocol, although the

register map can be accessed via the SPI protocol.

The M0, M5, and M4 pins select one of 16 input frequencies, and

the M3 to M1 pins select one of 16 possible output frequencies. See

Table 32 and Table 33 for details.

When in hard pin programming mode, the user must set

Register 0x0200[0] = 1 to activate the IRQ, REF status, and PLL

lock status signals at the multifunction pins.

Rev. A | Page 60 of 104

Data Sheet

AD9558

•

Address 0x0C06[3:2] select one of four DPLL loop

bandwidths.

SOFT PIN PROGRAMMING OVERVIEW

The soft pin program function is controlled by a dedicated

register section (Address 0x0C00 to Address 0x0C08). The

purpose of soft pin program is to use the register bits to mimic

the hard pins for the configuration section. When in soft pin

program mode, both SPI and I²C port are available.

•

Address 0x0C06[4] selects the DPLL phase margin.

Address 0x0C04[3:0] scales the REFA/REFB/REFC/REFD

input frequency down by divide-by-1, divide-by-4, divide-

by-8, divide-by-16 independently. For example, when

Address 0x0C01[3:0] = 0101 to select input frequency as

622.08 MHz for all REFA/REFB/REFC/REFD, setting

Address 0x0C04[1:0] = 0x01 scales down the REFA input

frequency to 155.52 MHz (= 622.08 MHz/4). This is done

by internally scaling the R divider for REFA up by 4× and

the REFA period up by 4×.

•

Address 0x0C00[0] enables accessibility to Address 0x0C01

and Address 0x0C02 (Soft Pin Section 1). This bit must be

set in soft pin mode.

•

Address 0x0C03[0] enables accessibility to Address 0x0C04 to

Address 0x0C06 (Soft Pin Section 2). This bit must be set

in soft pin mode.

•

Address 0x0C05[3:0] scales the Channel 0/1/2/3 output

frequency down by divide-by-1, divide-by-4, divide-by-8,

or divide-by-16. (Channel 2 and Channel 3 are available

only for the AD9558).

•

Address 0x0C01[3:0] select one of 16 input frequencies.

Address 0x0C01[7:4] select one of 16 output frequencies.

Address 0x0C02[1:0] select the system clock configuration.

Address 0x0C06[1:0] select one of four input frequency

tolerance ranges.

Rev. A | Page 61 of 104

AD9558

Data Sheet

REGISTER MAP

Register addresses that are not listed in Table 35 are not used, and writing to those registers has no effect. The user should write the

default value to sections of registers marked reserved. R = read-only. A = autoclear. E = excluded from EEPROM loading. L = live (I/O

update not required for register to take effect or for a read-only register to be updated).

Table 35. Register Map

Reg

Addr

(Hex)

Opt

Name

D7

D6

D5

D4

D3

D2

D1

D0

Def

Serial Control Port Configuration and Part Identification

0x0000

L, E

L

SPI control

I²C control

SDO enable

LSB first/

increment

address

Soft reset

Reserved

00

0x0000

0x0004

Reserved

Soft reset

00

Readback

control

Reserved

Read buffer

register

0x0005

0x0006

0x0007

0x000A

0x000B

0x000C

0x000D

A, L

L

I/O update

00

21

0F

01

00

User scratch

pad

User scratch pad[7:0]

User scratch pad[15:8]

Silicon revision[7:0]

Reserved

L

R, L

Silicon rev

Reserved

Part ID

Clock part family ID[7:0]

Clock part family ID[15:8]

System Clock

0x0100

SYSCLK config

PLL feedback

divider

System clock N divider[7:0]

08

0x0101

Reserved

Load from

ROM

SYSCLK XTAL

enable

SYSCLK P divider[1:0]

SYSCLK

doubler

enable

09

or

19

(reserved)

0x0102

0x0103

0x0104

0x0105

0x0106

0x0107

Reserved

00

0E

67

13

32

00

SYSCLK period

Nominal system clock period (fs), Bits[7:0] (1 ns at 1 ppm accuracy)

Nominal system clock period (fs), Bits[15:8] (1 ns at 1 ppm accuracy)

Reserved

Nominal system clock period (fs), Bits[20:16]

SYSCLK

stability

System clock stability period (ms), Bits[7:0]

System clock stability period (ms), Bits[15:8]

0x0108

A

Reset

SYSCLK

System clock stability period (ms), Bits[19:16]

(not autoclearing)

stab timer

(autoclear)

General Configuration

0x0200

EN_MPIN

Reserved

Enable M pins

and IRQ pin

function

00

0x0201

0x0202

M0FUNC

M1FUNC

input

Function[6:0]

B0

B1

Output/

input

Output/

0x0203

0x0204

0x0205

0x0206

0x0207

0x0208

M2FUNC

M3FUNC

M4FUNC

M5func

Function[6:0]

C0

C1

B2

B3

C2

C3

Output/

M6FUNC

M7FUNC

Rev. A | Page 62 of 104

Data Sheet

AD9558

Reg

Addr

(Hex)

Opt

Name

D7

D6

D5

D4

D3

D2

D1

D0

IRQ pin driver type[1:0]

Def

0x0209

IRQ pin

output mode

Reserved

Status signal

at IRQ pin[1:0]

Use IRQ pin

for status

signal

1F

0x020A

0x020B

IRQ mask

Reserved

SYSCLK

unlocked

SYSCLK

locked

APLL

unlocked

APLL

locked

APLL cal

complete

APLL cal

started

00

Reserved

program

end

Sync

distribution

Watchdog

timer

EEPROM fault

EEPROM

complete

0x020C

0x020D

0x020E

Switching

Closed

Freerun

Holdover

Frequency

unlocked

Frequency

locked

Phase unlocked

Phase locked

00

Reserved

History

updated

Frequency

unclamped

Frequency

clamped

Phase slew

unlimited

Phase slew

limited

Reserved

REFB

validated

REFB

fault

cleared

REFB

fault

Reserved

REFA

validated

REFA fault

cleared

REFA fault

0x020F

REFD

validated

REFD

fault

REFD fault

Reserved

REFC

validated

REFC fault

cleared

REFC fault

00

cleared

0x0210

0x0211

0x0300

0x0301

0x0302

0x0303

0x0304

Watchdog

Timer 1

Watchdog timer (ms), Bits[7:0]

Watchdog timer (ms), Bits[15:8]

00

11

15

64

1B

10

Freerun

frequency TW

30-bit free run frequency tuning word[7:0]

30-bit free run frequency tuning word[15:8]

30-bit free run frequency tuning word[23:16]

30-bit free run frequency tuning word[29:24]

Reserved

Digital

oscillator

control

DCO

4-level

output

Reset SDM

Reserved

(must be 1b)

0x0305

0x0306

0x0307

0x0308

0x0309

0x030A

0x030B

0x030C

0x030D

0x030E

0x030F

0x0310

0x0311

0x0312

0x0313

0x0314

0x0315

0x0316

Reserved

00

51

B8

02

3E

0A

0B

00

0A

00

DPLL

frequency

clamp

Lower limit of pull-in range[7:0]

Lower limit of pull-in range[15:8]

Reserved

Lower limit of pull-in range[19:16]

Upper limit of pull-in range[7:0]

Upper limit of pull-in range[15:8]

Upper limit of pull-in range[19:16]

Closed-loop

phase lock

offset

Fixed phase lock offset (signed; ps), Bits[7:0]

Fixed phase lock offset (signed; ps), Bits[15:8]

Fixed phase lock offset (signed; ps), Bits[23:16]

Fixed phase lock offset (signed; ps), Bits[29:24]

[

0.5 ms]

Reserved

Incremental phase lock offset step size (ps/step), Bits[7:0] (up to 65.5 ns/step)

Incremental phase lock offset step size (ps/step), Bits[15:8] (up to 65.5 ns/step)

Phase slew rate limit (μs/sec), Bits[7:0] (315 μs/sec up to 65.536 ms/sec)

Phase slew rate limit (μs/sec), Bits[15:8] (315 μs/sec up to 65.536 ms/sec)

History accumulation timer (ms), Bits[7:0] (up to 65 seconds)

Phase slew

rate limit

Holdover

history

History accumulation timer (ms), Bits[15:8] (up to 65 seconds)

History mode

Reserved

Single

sample

fallback

Persistent

history

Incremental average

0x0317

0x0318

0x0319

0x031A

0x031B

0x031C

0x031D

0x031E

0x031F

0x0320

0x0321

0x0322

L

Base Loop

Filter A

coefficient set

(high phase

margin)

HPM Alpha-0[7:0]

8C

AD

4C

F5

HPM Alpha-0[15:8]

HPM Alpha-1[6:0]

Reserved

HPM Beta-0[7:0]

HPM Beta-0[15:8]

CB

73

24

D8

59

D2

8D

5A

HPM Beta-1[6:0]

HPM Gamma-0[7:0]

HPM Gamma-0[15:8]

HPM Gamma-1[6:0]

HPM Delta-0[7:0]

HPM Delta-0[15:8]

HPM Delta-1[6:0]

Rev. A | Page 63 of 104

AD9558

Data Sheet

Reg

Addr

(Hex)

Opt

L

Name

D7

D6

D5

D4

D3

D2

D1

D0

Def

24

8C

49

55

C9

7B

9C

FA

55

EA

E2

57

0x0323

0x0324

0x0325

0x0326

0x0327

0x0328

0x0329

0x032A

0x032B

0x032C

0x032D

0x032E

Base loop

Filter A

coefficient set

(normal phase

margin of 70º)

NPM Alpha-0[7:0]

NPM Alpha-0[15:8]

L

Reserved

NPM Alpha-1[6:0]

NPM Beta-0[7:0]

NPM Beta-0[15:8]

NPM Beta-1[6:0]

L

NPM Gamma-0[7:0]

NPM Gamma-0[15:8]

L

NPM Gamma-1[6:0]

L

NPM Delta-0[7:0]

NPM Delta-0[15:8]

L

NPM Delta-1[6:0]

Output PLL (APLL)

0x0400

APLL charge

pump

Output PLL (APLL) charge pump[7:0]

81

0x0401

0x0402

0x0403

0x0404

APLL N divider

Output PLL (APLL) feedback N divider[7:0]

Reserved

14

00

07

00

APLL loop

filter control

APLL loop filter control[7:0]

Reserved

Bypass

internal Rzero

0x0405

APLL VCO

control

Reserved (default: 0x2)

APLL locked

controlled

Reserved

Manual APLL

VCO (not

20

sync disable

autoclearing)

0x0406

0x0407

0x0408

Reserved

00

44

02

RF divider

RF Divider 2[3:0]

Reserved

RF Divider 1[3:0]

RF divider

startup

mode

Reserved

PD RF Divider 2

PD RF Divider 1

Output Clock Distribution

0x0500

Distribution

output sync

Mask

Channel 3

sync

Mask

Channel 2

sync

Mask

Channel 1

sync

Mask

Channel 0

sync

Reserved

Sync

source

selection

OUT0 polarity[1:0]

Automatic sync mode

02

10

0x0501

Channel 0

Enable 3.3 V

CMOS driver

OUT0 format[2:0]

OUT0 drive

strength

Enable OUT0

0x0502

0x0503

Channel 0 (M0) division ratio[7:0]

Channel 0 PD Select RF

Divider 2

Channel 0 divider phase[5:0]

00

Reserved

Channel 0 (M0) division ratio[9:8]

0x0504

0x0505

Reserved

00

10

Channel 1

Channel 2

Channel 3

Reserved

OUT1 format[2:0]

OUT2 format[2:0]

OUT1 polarity[1:0]

OUT1 drive

strength

Enable OUT1

Enable OUT2

0x0506

OUT2 polarity[1:0]

OUT2 drive

strength

10

0x0507

0x0508

Channel 1 (M1) division ratio[7:0]

Channel 1 PD

03

00

Reserved

Select RF

Divider 2

Channel 1 (M1) division ratio[9:8]

0x0509

0x050A

Reserved

Channel 1 divider phase[5:0]

00

10

OUT3 format[2:0]

OUT4 format[2:0]

OUT3 polarity[1:0]

OUT3 drive

strength

Enable OUT3

Enable OUT4

0x050B

Reserved

OUT4 polarity[1:0]

OUT4 drive

strength

10

0x050C

0x050D

Channel 2 (M2) division ratio[7:0]

Channel 2 PD

00

Reserved

Select RF

Divider 2

Channel 2 (M2) division ratio[9:8]

0x050E

0x050F

Reserved

Channel 2 divider phase[5:0]

OUT5 polarity[1:0] OUT5 drive

strength

00

10

Enable 3.3 V

CMOS driver

OUT5 format[2:0]

Enable OUT5

0x0510

0x0511

Channel 3, Divider 1 (M3) division ratio[7:0]

Reserved

03

00

Channel 3, Divider 1 (M3)

division ratio[9:8]

0x0512

0x0513

Channel 3, Divider 2 (M3b) division ratio[7:0]

00

Reserved

Enable

Channnel 3

PD

Select RF

Divider 2

Channel 3, Divider 2 (M3b)

division ratio[9:8]

Channel 3

doubler

0x0514

0x0515

Reserved

Channel 3, Divider 1 phase[5:0]

Channel 3, Divider 2 phase[5:0]

00

Rev. A | Page 64 of 104

Data Sheet

AD9558

Reg

Addr

(Hex)

Opt

Name

D7

D6

D5

D4

D3

D2

D1

D0

Def

Reference Inputs

0x0600

Reference

power-down

Reserved

Reference power-down[3:0]

00

0x0601

Reference

logic type

REFD logic type[1:0]

REFD priority[1:0]

REFC logic type[1:0]

REFC priority[1:0]

REFB logic type[1:0]

REFB priority[1:0]

REFA logic type[1:0]

REFA priority[1:0]

0x0602

0x0603

Reference

priority

00

Reserved

Frame Synchronization Mode

0x0640

0x0641

En frame sync

Reserved

Enable Fsync

00

Frame sync

options

Reserved

Validate

Fsync ref

Fsync one

shot

Fsync

arm

Arm soft Fsync

00

method

Profile A (for REFA)

0x0700

0x0701

0x0702

0x0703

0x0704

0x0705

0x0706

0x0707

0x0708

0x0709

0x070A

0x070B

0x070C

0x070D

0x070E

L

Reference

period (up to

1.1 ms)

Nominal reference period (fs), Bits[7:0] (default: 51.44 ns =1/(19.44 MHz) for default system clock setting)

Nominal period (fs), Bits[15:8]

C9

EA

10

03

00

14

00

0A

00

0A

00

L

Nominal period (fs), Bits[23:16]

Nominal period (fs), Bits[31:24]

Nominal period (fs), Bits[39:32]

Frequency

tolerance

Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%)

Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm)

Reserved

Inner tolerance, Bits[19:16]

Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm) (default: 10%)

Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm)

Reserved

Outer tolerance, Bits[19:16]

Validation timer (ms), Bits[7:0] (up to 65.5 seconds)

Validation

Validation timer (ms), Bits[15:8] (up to 65.5 seconds)

Reserved

Select base

loop filter

Sel high PM

base loop

filter

0x070F

0x0710

0x0711

L

DPLL loop BW

Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz)

Digital PLL loop BW scaling factor[15:8]

Reserved

F4

01

00

BW scaling

factor[16]

0x0712

0x0713

0x0714

L

DPLL

R divider

(20 bits)

R divider[7:0]

R divider[15:8]

C5

00

Reserved

Enable REFA

divide-by-2

R divider[19:16]

0x0715

0x0716

0x0717

DPLL

N divider

(17 bits)

Digital PLL feedback divider—Integer Part N1[7:0]

Digital PLL feedback divider—Integer Part N1[15:8]

Reserved

6B

07

00

Digital PLL

feedback

divider—

Integer Part

N1[16]

0x0718

DPLL

Digital PLL fractional feedback divider—FRAC1[7:0]

04

fractional

feedback

divider

0x0719

0x071A

0x071B

Digital PLL fractional feedback divider—FRAC1[15:8]

Digital PLL fractional feedback divider—FRAC1[23:16]

Digital PLL feedback divider modulus—MOD1[7:0]

00

05

(24 bits)

DPLL

fractional

feedback

divider

modulus

(24 bits)

0x071C

0x071D

Digital PLL feedback divider modulus—MOD1[15:8]

Digital PLL feedback divider modulus—MOD1[23:16]

00

0x071E

0x071F

0x0720

0x0721

0x0722

0x0723

0x0724

0x0725

0x0726

L

Lock detectors

Phase lock threshold (ps), Bits[7:0]

Phase lock threshold (ps), Bits[15:8]

Phase lock fill rate[7:0]

BC

02

0A

BC

02

00

0A

Phase lock drain rate[7:0]

Frequency lock threshold[7:0]

Frequency lock threshold[15:8]

Frequency lock threshold[23:16]

Frequency lock fill rate[7:0]

Frequency lock drain rate[7:0]

Rev. A | Page 65 of 104

AD9558

Data Sheet

Reg

Addr

(Hex)

Opt

Name

D7

D6

D5

D4

D3

D2

D1

D0

Def

Profile B (for REFB)

0x0740

0x0741

0x0742

0x0743

0x0744

0x0745

0x0746

0x0747

0x0748

0x0749

0x074A

0x074B

0x074C

0x074D

0x074E

L

Reference

period (up to

1.1 ms)

Nominal period (fs), Bits[7:0] (default: 125 μs = 1/(8 kHz) for default system clock setting)

Nominal period (fs), Bits[15:8]

00

A2

94

1A

1D

14

00

0A

00

0A

00

L

Nominal period (fs), Bits[23:16]

Nominal period (fs), Bits[31:24]

Nominal period (fs), Bits[39:32]

Frequency

tolerance

Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%)

Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm)

Reserved

Inner tolerance, Bits[19:16]

Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm] (default: 10%)

Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm)

Reserved

Outer tolerance, Bits[19:16]

Validation timer (ms), Bits[7:0] (up to 65.5 seconds)

Validation

Validation timer (ms), Bits[15:8] (up to 65.5 seconds)

Reserved

Select base

loop filter

Sel high PM

base loop

filter

0x074F

0x0750

0x0751

L

DPLL loop BW

F4

01

00

Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz)

Digital PLL loop BW scaling factor[15:8]

Reserved

BW scaling

factor[16]

0x0752

0x0753

0x0754

L

DPLL

R divider

(20 bits)

R divider[7:0]

R divider[15:8]

00

Reserved

Enable REFB

divide-by-2

R divider[19:16]

0x0755

0x0756

0x0757

DPLL

N divider

(17 bits)

Digital PLL feedback divider—Integer Part N1[7:0]

Digital PLL feedback divider—Integer Part N1[15:8]

Reserved

1F

5B

00

Digital PLL

feedback

divider—

Integer Part

N1[16]

0x0758

0x0759

0x075A

DPLL

Digital PLL fractional feedback divider—FRAC1[7:0]

Digital PLL fractional feedback divider—FRAC1[15:8]

Digital PLL fractional feedback divider—FRAC1[23:16]

00

fractional

feedback

divider

(24 bits)

0x075B

0x075C

DPLL

Digital PLL feedback divider modulus—MOD1[7:0]

Digital PLL feedback divider modulus—MOD1[15:8]

01

00

fractional

feedback

divider

modulus

(24 bits)

0x075D

Digital PLL feedback divider modulus—MOD1[23:16]

00

0x075E

0x075F

0x0760

0x0761

0x0762

0x0763

0x0764

0x0765

0x0766

L

Lock detectors

Phase lock threshold (ps), Bits[7:0]

Phase lock threshold(ps), Bits[15:8]

Phase lock fill rate[7:0]

BC

02

0A

BC

02

00

0A

Phase lock drain rate[7:0]

Frequency lock threshold[7:0]

Frequency lock threshold[15:8]

Frequency lock threshold[23:16]

Frequency lock fill rate[7:0]

Frequency lock drain rate[7:0]

Rev. A | Page 66 of 104

Data Sheet

AD9558

Reg

Addr

(Hex)

Opt

Name

D7

D6

D5

D4

D3

D2

D1

D0

Def

Profile C (for REFC)

0x0780

0x0781

0x0782

0x0783

0x0784

0x0785

0x0786

0x0787

0x0788

0x0789

0x078A

0x078B

0x078C

0x078D

0x078E

L

Reference

period (up to

1.1 ms)

C9

EA

10

03

00

14

00

0A

00

0A

00

Nominal period (fs), Bits[7:0] (default: 125 μs = 1/(8 kHz) for default system clock setting)

Nominal period (fs), Bits[15:8]

L

Nominal period (fs), Bits[23:16]

Nominal period (fs), Bits[31:24]

Nominal period (fs), Bits[39:32]

Frequency

tolerance

Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%)

Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm)

Reserved

Inner tolerance, Bits[19:16]

Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm] (default: 10%)

Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm)

Reserved

Outer tolerance, Bits[19:16]

Validation timer (ms), Bits[7:0] (up to 65.5 seconds)

Validation

Validation timer (ms), Bits[15:8] (up to 65.5 seconds)

Reserved

Select base

loop filter

00

Sel high PM

base loop filt

0x078F

0x0790

0x0791

L

DPLL loop BW

Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz)

Digital PLL loop BW scaling factor[15:8]

Reserved

F4

01

00

BW scaling

factor[16]

0x0792

0x0793

0x0794

L

DPLL

R divider

(20 bits)

R divider[7:0]

R divider[15:8]

C5

00

Reserved

Enable REFC

divide-by-2

R divider[19:16]

0x0795

0x0796

0x0797

DPLL

N divider

(17 bits)

Digital PLL feedback divider—Integer Part N1[7:0]

Digital PLL feedback divider—Integer Part N1[15:8]

Reserved

6B

07

00

Digital PLL

feedback

divider—

Integer Part

N1[16]

0x0798

0x0799

0x079A

DPLL

Digital PLL fractional feedback divider—FRAC1[7:0]

Digital PLL fractional feedback divider—FRAC1[15:8]

Digital PLL fractional feedback divider—FRAC1[23:16]

04

00

fractional

feedback

divider

(24 bits)

0x079B

0x079C

0x079D

DPLL

Digital PLL feedback divider modulus—MOD1[7:0]

Digital PLL feedback divider modulus—MOD1[15:8]

Digital PLL feedback divider modulus—MOD1[23:16]

05

00

fractional

feedback

divider

modulus

(24 bits)

0x079E

0x079F

0x07A0

0x07A1

0x07A2

0x07A3

0x07A4

0x07A5

0x07A6

L

Lock detectors

Phase lock threshold (ps), Bits[7:0]

Phase lock threshold (ps), Bits[15:8]

Phase lock fill rate[7:0]

BC

02

0A

BC

02

00

0A

Phase lock drain rate[7:0]

Frequency lock threshold[7:0]

Frequency lock threshold[15:8]

Frequency lock threshold[23:16]

Frequency lock fill rate[7:0]

Frequency lock drain rate[7:0]

Rev. A | Page 67 of 104

AD9558

Data Sheet

Reg

Addr

(Hex)

Opt

Name

D7

D6

D5

D4

D3

D2

D1

D0

Def

DPLL Profile D (for REFD)

0x07C0

0x07C1

0x07C2

0x07C3

0x07C4

0x07C5

0x07C6

0x07C7

0x07C8

0x07C9

0x07CA

0x07CB

0x07CC

0x07CD

0x07CE

L

Reference

period (up to

1.1 ms)

00

A2

94

1A

1D

14

00

0A

00

0A

00

Nominal reference period (fs), Bits[7:0] (default: 51.44 ns =1/(19.44 MHz) for default system clock setting)

Nominal period (fs), Bits[15:8]

L

Nominal period (fs), Bits[23:16]

Nominal period (fs), Bits[31:24]

Nominal period (fs), Bits[39:32]

Tolerance

Validation

Inner tolerance (1 ppm), Bits[7:0] (for reference invalid to valid; 50% down to 1 ppm) (default: 5%)

Inner tolerance (1 ppm), Bits[15:8] (for reference invalid to valid; 50% down to 1 ppm)

Reserved

Inner tolerance, Bits[19:16]

Outer tolerance (1 ppm), Bits[7:0] (for reference valid to invalid; 50% down to 1 ppm) (default: 10%)

Outer tolerance (1 ppm), Bits[15:8] (for reference valid to invalid; 50% down to 1 ppm)

Reserved

Outer tolerance, Bits[19:16]

Validation timer (ms), Bits[7:0] (up to 65.5 seconds)

Validation timer (ms), Bits[15:8] (up to 65.5 seconds]

Reserved

Select base

loop filter

Sel high PM

base loop

filter

0x07CF

0x07D0

0x07D1

L

DPLL loop BW

Digital PLL loop BW scaling factor[7:0] (default: 0x01F4 = 50 Hz)

Digital PLL loop bandwidth BW scaling factor[15:8]

Reserved

F4

01

00

BW scaling

factor[16]

0x07D2

0x07D3

0x07D4

L

DPLL

R divider

(20 bits)

R divider[7:0]

R divider[15:8]

00

Reserved

Enable

REFD

R divider[19:16]

divide-by-2

0x07D5

0x07D6

0x07D7

DPLL

N divider

(17 bits)

Digital PLL feedback divider—Integer Part N1[7:0]

Digital PLL feedback divider—Integer Part N1[15:8]

Reserved

1F

5B

00

Digital PLL

feedback

divider—

Integer Part

N1[16]

0x07D8

0x07D9

0x07DA

DPLL

Digital PLL fractional feedback divider—FRAC1[7:0]

Digital PLL fractional feedback divider—FRAC1[15:8]

Digital PLL fractional feedback divider—FRAC1[23:16]

00

fractional

feedback

divider

(24 bits)

0x07DB

0x07DC

0x07DD

DPLL

Digital PLL feedback divider modulus—MOD1[7:0]

Digital PLL feedback divider modulus—MOD1[15:8]

Digital PLL feedback divider modulus—MOD1[23:16]

01

00

fractional

feedback

divider

modulus

(24 bits)

0x07DE

0x07DF

0x07E0

0x07E1

0x07E2

0x07E3

0x07E4

0x07E5

0x07E6

L

Lock detectors

Phase lock threshold (ps), Bits[7:0]

Phase lock threshold(ps), Bits[15:8]

Phase lock fill rate[7:0]

BC

02

0A

BC

02

00

0A

Phase lock drain rate[7:0]

Frequency lock threshold[7:0]

Frequency lock threshold[15:8]

Frequency lock threshold[23:16]

Frequency lock fill rate[7:0]

Frequency lock drain rate[7:0]

Rev. A | Page 68 of 104

Data Sheet

AD9558

Reg

Addr

(Hex)

Opt

Name

D7

D6

D5

D4

D3

D2

D1

D0

Def

Operational Controls

0x0A00

0x0A01

Power-down

Soft reset

exclude

regmap

DCO PD

SYSCLK

PD

Ref input

PD

TDC PD

APLL PD

Clock dist PD

Full PD

00

Loop mode

Cal/sync

Reserved

User

holdover

User

freerun

REF switchover mode[2:0]

00

User ref in manual

switchover mode

0x0A02

0x0A03

0x0A04

0x0A05

Reserved

Soft sync

clock dist

Reserved

00

A

Clear/reset

functions

Reserved

Clear LF

Reserved

Clear CCI

Reserved

Clear auto

sync

Clear TW

history

Clear all IRQs

Clear watchdog

IRQ clearing

SYSCLK

unlocked

SYSCLK

locked

APLL

unlocked

APLL

locked

APLL cal ended

EEPROM fault

APLL cal

started

program

end

Sync clock

dist

Watchdog

timer

EEPROM

complete

0x0A06

0x0A07

0x0A08

0x0A09

A

Switching

Closed

Freerun

Holdover

Frequency

unlocked

Frequency

locked

Phase

unlocked

Phase

locked

00

Reserved

History

updated

Frequency

unclamped

Frequency

clamped

Phase slew

unlimited

Phase slew

limited

Reserved

REFB

validated

REFB fault

cleared

REFB fault

Reserved

REFA

validated

REFA fault

cleared

REFA fault

REFD

validated

REFD

fault

REFD fault

Reserved

REFC

validated

REFC fault

cleared

REFC fault

cleared

0x0A0A

0x0A0B

0x0A0C

0x0A0D

A

Increment

phase offset

Reserved

Reset

phase

offset

Decrement

phase offset

Increment

phase offset

00

Manual

reference

validation

Reserved

Force

Timeout D

Force

Timeout C

Force

Timeout B

Force

Timeout A

Manual

reference

invalidation

Reserved

REF Mon

Override D

REF Mon

Override C

REF Mon

Override B

REF Mon

Override A

Static

reference

validation

REF Mon

Bypass D

REF Mon

Bypass C

REF Mon

Bypass B

REF Mon

Bypass A

Quick In-Out Frequency Soft Pin Configuration

0x0C00

L, E

Enable

Soft Pin

Section 1

Reserved

En Soft Pin

Section 1

00

0x0C01

0x0C02

0x0C03

L, E

Soft Pin

Section 1

Output frequency selection[3:0]

Input frequency selection[3:0]

00

Reserved

SYSCLK PLL REF selection[1:0]

Enable

Soft Pin

Section 2

Reserved

En Soft Pin

Section 2

0x0C04

0x0C05

0x0C06

L, E

Soft Pin

Section 2

REFD frequency scale[1:0]

REFC frequency

scale[1:0]

REFB frequency scale[1:0]

REFA frequency scale[1:0]

00

Channel 3 output frequency

scale[1:0]

Channel 2 output

frequency scale[1:0]

Channel 1 output frequency

scale[1:0]

Channel 0 output frequency

scale[1:0]

Reserved

Sel high

PM base

loop filter

DPLL BW[1:0]

REF tolerance[1:0]

0x0C07

0x0C08

L, A,

E

Reserved

Soft pin start

transfer

00

L, E

Reserved

Soft pin reset

Rev. A | Page 69 of 104

AD9558

Data Sheet

Reg

Addr

(Hex)

Opt

Name

D7

D6

D5

D4

D3

D2

D1

D0

Def

Read-Only Status (Accessible During EEPROM Transactions)

0x0D00

0x0D01

R, L

EEPROM

Reserved

Pin program

ROM load

process

Fault

detected

Load in

progress

Save in

progress

N/A

SYSCLK and

PLL status

Reserved

DPLL_

APLL_

Lock

All PLLs

locked

APLL VCO

status

APLL cal

in progress

APLL lock

SYSCLK stable

APLL cal ended

SYSCLK

lock detect

N/A

0x0D02

0x0D03

R, L

IRQ monitor

events

Reserved

SYSCLK

unlocked

SYSCLK

locked

APLL

unlocked

APLL

lock detect

APLL cal

started

N/A

Reserved

program

end

Output dist

sync

Watchdog

timer

EEPROM

fault

EEPROM

complete

0x0D04

0x0D05

0x0D06

0x0D07

R, L

Switching

Closed

Freerun

Holdover

Frequency

unlocked

Frequency

locked

Phase

unlocked

Phase

locked

N/A

Reserved

History

updated

Frequency

unclamped

Frequency

clamped

Phase slew

unlimited

Phase slew

limited

Reserved

REFB

validated

REFB fault

cleared

REFB fault

Reserved

REFA

validated

REFA fault

cleared

REFA fault

REFD

validated

REFD

fault

REFD

fault

Reserved

REFC

validated

REFC

fault cleared

REFC

fault

cleared

0x0D08

0x0D09

R

DPLL

Reserved

Offset slew

limiting

Frequency

lock

Phase lock

Loop

switching

Holdover

Active

Freerun

N/A

Reserved

Frequency

clamped

History

available

Reserved

Active

reference

priority

Current active reference

0x0D0A

0x0D0B

R

Reserved

N/A

REFA/REFB

REFC/REFD

B valid

D valid

B fault

D fault

B fast

D fast

B slow

D slow

A valid

C valid

A fault

C fault

A fast

C fast

A slow

C slow

0x0D0C

R

N/A

0x0D0D

0x0D0E

0x0D0F

0x0D10

0x0D11

0x0D12

0x0D13

0x0D14

R

Holdover

history

Tuning word readback[31:0]

N/A

Lock detector

phase tub

Phase tub[7:0]

Reserved

Phase tub[11:8]

Lock detector

frequency tub

Frequency tub[7:0]

Frequency tub[11:8]

Nonvolatile Memory (EEPROM) Control

0x0E00

E

Write protect

Reserved

Write enable

00

0x0E01

0x0E02

E

Condition

Save

Reserved

Conditional value[3:0]

00

A,E

Save to

EEPROM

0x0E03

A,E

Load

Reserved

Load from

EEPROM

00

Rev. A | Page 70 of 104

Data Sheet

AD9558

Reg

Addr

(Hex)

Opt

Name

D7

D6

D5

D4

D3

D2

D1

D0

Def

EEPROM Storage Sequence

0x0E10

0x0E11

0x0E12

0x0E13

0x0E14

0x0E15

0x0E16

0x0E17

0x0E18

0x0E19

0x0E1A

0x0E1B

0x0E1C

0x0E1D

0x0E1E

0x0E1F

0x0E20

0x0E21

0x0E22

0x0E23

0x0E24

0x0E25

0x0E26

0x0E27

0x0E28

0x0E29

0x0E2A

0x0E2B

0x0E2C

0x0E2D

0x0E2E

0x0E2F

0x0E30

0x0E31

0x0E32

0x0E33

0x0E34

0x0E35

0x0E36

0x0E37

0x0E38

0x0E39

0x0E3A

0x0E3B

0x0E3C

E

EEPROM ID

Data: two bytes

Address: 0x0006

01

00

06

08

01

00

80

11

02

00

2E

03

00

08

04

00

15

05

00

80

03

06

00

01

06

40

26

07

00

26

07

40

26

07

80

26

07

C0

80

0D

0A

00

A0

80

FF

00

System

clock

Data: nine bytes

Address: 0x0100

I/O update

General

Action: I/O update

Data: 18 bytes

Address: 0x0200

DPLL

Data: 47 bytes

Address: 0x0300

APLL

Data: nine bytes

Address: 0x0400

Clock dist

I/O update

Data: 22 bytes

Address: 0x0500

Action: I/O update

Data: four bytes

Address: 0x0600

Reference

inputs

Data: two bytes

Address: 0x0640

Profile REFA

Profile REFB

Profile REFC

Profile REFD

I/O update

Data: 39 bytes

Address: 0x0700

Data: 39 bytes

Address: 0x0740

Data: 39 bytes

Address: 0x0780

Data: 39 bytes

Address: 0x07C0

Action: I/O update

Data: 14 bytes

Operational

controls

Address: 0x0A00

Calibrate APLL

I/O update

End of data

Unused

Action: calibrate output PLL

Action: I/O update

Action: End of data

Unused

0x0E3D

to

(available for additional EEPROM instructions)

0xE45

Rev. A | Page 71 of 104

AD9558

Data Sheet

REGISTER MAP BIT DESCRIPTIONS

SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005)

Table 36. Serial Configuration (Note that the contents of Register 0x0000 are not stored to the EEPROM.)

Address

Bits

Bit Name

Description

0x0000

7

SDO enable

Enables SPI port SDO pin.

1 = 4-wire (SDO pin enabled).

0 (default) = 3-wire.

6

LSB first/increment

address

Bit order for SPI port.

1 = least significant bit and byte first.

Register addresses are automatically incremented in multibyte transfers.

0 (default) = most significant bit and byte first.

Register addresses are automatically decremented in multibyte transfers.

5

Soft reset

Device reset (invokes an EEPROM download or pin program ROM download if EEPROM or

pin program is enabled. See the EEPROM and Pin Configuration and Function Descriptions

sections for details.

[4:0] Reserved

Table 37. Readback Control

Reserved.

Address

Bits

[7:1] Reserved

Read buffer register

Bit Name

Description

0x0004

Reserved.

0

For buffered registers, serial port readback reads from actual (active) registers instead of the

buffer.

1 = reads buffered values that take effect on next assertion of I/O update.

0 (default) = reads values currently applied to the device’s internal logic.

Table 38. Soft I/O Update

Address

Bits

[7:1] Reserved

I/O update

Bit Name

Description

0x0005

Reserved.

0

Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the device’s

internal control registers. Unless a register is marked as live (as indicated by an L in the Opt

column of the register map), the user must write to this bit before any register settings can

take effect and before a read-only register can be updated with the most current value.

This is an autoclearing bit.

Table 39. User Scratch Pad

Address

0x0006

0x0007

Bits

Bit Name

Description

[7:0] User scratch pad[7:0]

[7:0] User scratch pad[15:8]

User programmable EEPROM ID registers. These registers enable users to write a unique

code of their choosing to keep track of revisions to the EEPROM register loading. It has no

effect on part operation.

0 = default.

SILICON REVISION (REGISTER 0x000A)

Table 40. Silicon Revision

Address

Bits

Bit Name

Description

0x000A

[7:0] Silicon revision

This read-only register identifies the revision level of the AD9558.

CLOCK PART SERIAL ID (REGISTER 0x000C TO REGISTER 0x000D)

Table 41. Clock Part Family ID

Address

Bits

Bit Name

Description

0x000C

[7:0] Clock part family ID[7:0]

This read-only register (along with Register 0x000D) uniquely identifies an AD9557 or

AD9558. No other part in the ADI AD95xx family has a value of 0x0001 in these two registers.

Default: 0x01 for the AD9557 and AD9558.

0x000D

[7:0] Clock part family ID[15:8] This register is a continuation of Register 0x000C.

Default: 0x00 for the AD9557 and AD9558.

Rev. A | Page 72 of 104

Data Sheet

AD9558

SYSTEM CLOCK (REGISTER 0x0100 TO REGISTER 0x0108)

Table 42. System Clock PLL Feedback Divider (N3 Divider)

Address

Bits

Bit Name

Description

0x0100

[7:0] SYSCLK N3 divider

System clock PLL feedback divider value: 4 ≤ N3 ≤ 255 (default: 0x08).

Table 43. SYSCLK Configuration

Address

Bits

Bit Name

Description

0x0101

[7:5] Reserved

Reserved.

4

3

Load from ROM

(reserved)

This reserved bit has no function.

0 (default) = power-on default and ROM not loaded.

1 = ROM values are loaded into the register space.

SYSCLK XTAL enable

Enables the crystal maintaining amplifier for the system clock input.

1 (default) = crystal mode (crystal maintaining amplifier enabled).

0 = external XO or other system clock source.

[2:1] SYSCLK P divider

System clock input divider.

00 (default) = 1.

01 = 2.

10 = 4.

11 = 8.

0

SYSCLK doubler enable

Enable clock doubler on system clock input to reduce noise.

0 = disable.

1 (default) = enable.

Table 44. Nominal System Clock Period¹

Address

Bits

Bit Name

Description

0x0103

[7:0] Nominal system clock period (fs)

System clock period, Bits[7:0].

Default: 0x0E.

0x0104

0x0105

[7:0]

System clock period, Bits[15:8].

Default: 0x67.

[7:5] Reserved

Reserved.

[4:0] Nominal system clock period (fs)

System clock period, Bits[20:16].

Default: 0x13.

¹Note that the default setting for system clock period is 1.271566 ns, which is the period of 786.432 MHz (= 49.152 MHz × 16).

Table 45. System Clock Stability Period

Address

Bits

Bit Name

Description

0x0106

[7:0] System clock stability period (ms) System clock period, Bits[7:0].

Default: 0x32 (0x000032 = 50 ms).

0x0107

0x0108

[7:0]

System clock period, Bits[15:8].

Default: 0x00.

[7:5] Reserved

Reserved.

4

Reset SYSCLK stability timer

This autoclearing bit resets the system clock stability timer.

[3:0] System clock stability period

System clock period, Bits[19:16].

Default: 0x00.

Rev. A | Page 73 of 104

AD9558

Data Sheet

GENERAL CONFIGURATION (REGISTER 0x0200 TO REGISTER 0x0214)

Multifunction Pin Control (M0 to M7) and IRQ Pin Control (Register 0x0200 to Register 0x0209)

Note that the default setting for the M0 to M5 multifunction pins and the IRQ is that of a 3-level logic input; M6 and M7 are unused inputs at

startup. After startup, M0 to M7 are 2-level inputs or 2-level outputs, based on the settings of Register 0x0200 to Register 0x0208. Setting

Bit 0 in Register 0x0200 to 1 enables M0 to M7 pin functionality.

Table 46. Multifunction Pin (M0 to M7) Control

Address

Bits Bit Name

Description

0x0200

[7:1] Reserved

Reserved.

0

Enable M pins and IRQ pin

function

0 (default) = disables the function of the M pins and IRQ pin control register (Address

0x0201 to Address 0x0209) and the M pins and IRQ pin are in 3-level logic input state.

1 = the M pins and IRQ pin are out of 3-level logic input state. Enables the function of the

M pins and IRQ pin control register (Address 0x0201 to Address 0x0209).

0x0201

7

M0 output/input

In/out control for M0 pin.

0 = input (2-level logic control pin).

1 (default) = output (2-level logic status pin).

[6:0] M0 function

See Table 129 and Table 130. Default: 0xB0 = REFA valid.

In/out control for M1 pin (same as M0).

0x0202

0x0203

0x0204

0x0205

0x0206

0x0207

0x0208

7

M1 output/input

[6:0] M1 function

See Table 129 and Table 130. Default: 0xB1 = REFB valid.

In/out control for M2 pin (same as M0).

7

M2 output/input

[6:0] M2 function

See Table 129 and Table 130. Default: 0xC0 = REFA active.

In/out control for M3 pin (same as M0).

7

M3 output/input

[6:0] M3 function

See Table 129 and Table 130. Default: 0xC1 = REFB active.

In/out control for M3 pin (same as M0).

7

M4 output/input

[6:0] M4 function

See Table 129 and Table 130. Default: 0xB2 = REFC valid.

In/out control for M3 pin (same as M0).

7

M5 output/input

[6:0] M5 function

See Table 129 and Table 130. Default: 0xB3 = REFD valid.

In/out control for M3 pin (same as M0).

7

M6 output/input

[6:0] M6 function

See Table 129 and Table 130. Default: 0xC2 = REFC active.

In/out control for M3 pin (same as M0).

7

M7 output/input

[6:0] M7 function

See Table 129 and Table 130. Default: 0xC3 = REFD active.

Table 47. IRQ Pin Output Mode

Address

Bits Bit Name

Description

0x0209

[7:5] Reserved

Default: 000b

[4:3] Status signal at IRQ pin

This selection is valid only when Address 0x0209[2] = 1

00 = DPLL phase locked

01 = DPLL frequency locked

10 = system clock PLL locked

11 (default) = (DPLL phase locked) AND (system clock PLL locked) AND (APLL locked)

2

Use IRQ pin for status signal

0 = uses IRQ pin to monitor IRQ event

1 (default) = uses IRQ pin to monitor internal status signals

[1:0] IRQ pin driver type

Select the output mode of the IRQ pin

00 = NMOS, open drain (requires an external pull-up resistor)

01 = PMOS, open drain (requires an external pull-down resistor)

10 = CMOS, active high

11 (default) = CMOS, active low

Rev. A | Page 74 of 104

Data Sheet

AD9558

IRQ MASK (REGISTER 0x020A TO REGISTER 0x020F)

The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (0x0D02 to 0x0D09). When set to

Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask bits is Logic 0,

which prevents the IRQ monitor from detecting any internal interrupts.

Table 48. IRQ Mask for SYSCLK

Address

Bits Bit Name

Description

0x020A

[7:6] Reserved

Reserved

5

4

3

2

1

0

SYSCLK unlocked

Enables IRQ for indicating a SYSCLK PLL state transition from locked to unlocked

Enables IRQ for indicating a SYSCLK PLL state transition from unlocked to locked

Enables IRQ for indicating an APLL state transition from locked to unlocked

Enables IRQ for indicating an APLL state transition from unlocked to locked

Enables IRQ for indicating that APLL (LCVCO) calibration has completed

Enables IRQ for indicating that APLL (LCVCO) calibration has begun

SYSCLK locked

APLL unlocked

APLL locked

APLL cal complete

APLL cal started

Table 49. IRQ Mask for Distribution Sync, Watchdog Timer, and EEPROM

Address

Bits Bit Name

Description

0x020B

[7:5] Reserved

Reserved

4

3

2

1

0

Pin program end

Enables IRQ for indicating successful completion of a pin program ROM load

Enables IRQ for indicating a distribution sync event

Enables IRQ for indicating expiration of the watchdog timer

Enables IRQ for indicating a fault during an EEPROM load or save operation

Enables IRQ for indicating successful completion of an EEPROM load or save operation

Sync distribution

Watchdog timer

EEPROM fault

EEPROM complete

Table 50. IRQ Mask for the Digital PLL

Address

Bits Bit Name

Description

0x020C

7

6

5

4

3

2

1

0

Switching

Enables IRQ for indicating that the DPLL is switching to a new reference

Enables IRQ for indicating that the DPLL has entered closed-loop operation

Enables IRQ for indicating that the DPLL has entered free run mode

Enables IRQ for indicating that the DPLL has entered holdover mode

Enables IRQ for indicating that the DPLL lost frequency lock

Enables IRQ for indicating that the DPLL has acquired frequency lock

Enables IRQ for indicating that the DPLL lost phase lock

Enables IRQ for indicating that the DPLL has acquired phase lock

Closed

Freerun

Holdover

Frequency unlocked

Frequency locked

Phase unlocked

Phase locked

Table 51. IRQ Mask for History Update, Frequency Limit and Phase Slew Limit

Address

Bits Bit Name

Description

0x020D

[7:5] Reserved

Reserved

4

3

2

1

History updated

Enables IRQ for indicating the occurrence of a tuning word history update

Enables IRQ for indicating a frequency limit state transition from clamped to unclamped

Enables IRQ for indicating a state transition of the frequency limiter from unclamped to clamped

Frequency unclamped

Frequency clamped

Phase slew unlimited

Enables IRQ for indicating a state transition of the phase slew limiter from slew limiting to not

slew limiting

0

Phase slew limited

Enables IRQ for indicating a state transition of the phase slew limiter from not slew limiting to

slew limiting

Rev. A | Page 75 of 104

AD9558

Data Sheet

Table 52. IRQ Mask for Reference Inputs

Address Bits Bit Name

Description

0x020E

7

6

5

4

3

2

1

0

Reserved

REFB validated

REFB fault cleared

REFB fault

Enables IRQ for indicating that REFB has been validated

Enables IRQ for indicating that REFB has been cleared of a previous fault

Enables IRQ for indicating that REFB has been faulted

Reserved

REFA validated

REFA fault cleared

REFA fault

Enables IRQ for indicating that REFA has been validated

Enables IRQ for indicating that REFA has been cleared of a previous fault

Enables IRQ for indicating that REFA has been faulted

Reserved

[7:0] Reserved

0x020F

Table 53. Watchdog Timer 1¹

Address Bits Bit Name

Description

0x0210

0x0211

[7:0] Watchdog timer (ms)

[7:0]

Watchdog timer, Bits[7:0]; default: 0x00

Watchdog timer, Bits[15:8]; default: 0x00

¹Note that the watchdog timer is expressed in units of milliseconds (ms). The default value is 0 (disabled).

DPLL CONFIGURATION (REGISTER 0x0300 TO REGISTER 0x032E)

Table 54. Free Run Frequency Tuning Word¹

Address Bits Bit Name

Description

0x0300

0x0301

0x0302

0x0303

[7:0] 30-bit free run frequency tuning word Free run frequency tuning word, Bits[7:0]; default: 0x11

[7:0]

Free run frequency tuning word, Bits[15:8]; default: 0x15

Free run frequency tuning word, Bits[23:9]; default: 0x64

Reserved

[7:0]

[7:6] Reserved

[5:0] 30-bit free run frequency word

Free run frequency tuning word, Bits[29:24]; default: 0x1B

¹Note that the default free run tuning word is 0x1B641511, which is used for 8 kHz/19.44 MHz = 622.08 MHz translation.

Table 55. Digital Oscillator Control

Address Bits Bit Name

Description

0x0304 [7:6] Reserved

Default: 00b

5

4

DCO 4-level output

Reserved

0 (default) = DCO 3-level output mode

1 = enables DCO 4-level output mode

Reserved (must be set to 1b)

Reserved (default: 0x0)

[3:0] Reserved

Table 56. DPLL Frequency Clamp

Address

Bits Bit Name

Description

0x0306

[7:0] Lower limit of pull-in range (expressed Lower limit pull-in range, Bits[7:0].

as a 20-bit frequency tuning word)

Default: 0x51.

0x0307

0x0308

[7:0]

Lower limit pull-in range, Bits[15:8].

Default: 0xB8.

Reserved

[7:4]

[3:0]

Default: 0x0.

Lower limit of pull-in range

Lower limit pull-in range, Bits[19:16].

Default: 0x2.

0x0309

0x030A

0x030B

[7:0] Upper limit of pull-in range

(expressed as a 20-bit frequency

Upper limit pull-in range, Bits[7:0].

Default: 0x3E.

tuning word)

[7:0]

Upper limit pull-in range, Bits[15:8].

Default: 0x0A.

Reserved

[7:4]

Default: 0x0.

[3:0] Upper limit of pull-in range

Upper limit pull-in range, Bits[19:16].

Default: 0xB.

Rev. A | Page 76 of 104

Data Sheet

AD9558

Table 57. Fixed Closed-Loop Phase Lock Offset

Address

Bits Bit Name

Description

0x030C

[7:0] Fixed phase lock offset (signed; ps)

Fixed phase lock offset, Bits[7:0].

Default: 0x00.

0x030D

0x030E

0x030F

[7:0]

Fixed phase lock offset, Bits[15:8].

Default 0x00.

Fixed phase lock offset, Bits[23:16].

Default: 0x00.

[7:6] Reserved

Reserved; default: 0x0.

[5:0] Fixed phase lock offset (signed; ps)

Fixed phase lock offset, Bits[29:24].

Default: 0x00.

Table 58. Incremental Closed-Loop Phase Lock Offset Step Size¹

Address

Bits Bit Name

Description

0x0310

[7:0] Incremental phase lock offset

step size (ps)

Incremental phase lock offset step size, Bits[7:0].

Default: 0x00.

This controls the static phase offset of the DPLL while it is locked.

0x0311

[7:0]

Incremental phase lock offset step size, Bits[15:8].

Default: 0x00.

This controls the static phase offset of the DPLL while it is locked.

¹Note that the default incremental closed-loop phase lock offset step size value is 0x0000 = 0 (0 ns).

Table 59. Phase Slew Rate Limit

Address

Bits Bit Name

Description

0x0312

[7:0] Phase slew rate limit (μs/sec)

Phase slew rate limit, Bits[7:0].

Default: 0x00.

This register controls the maximum allowable phase slewing during transients

and reference switching.

The default phase slew rate limit is 0, or disabled. Minimum useful value is 310 μs/sec.

0x0313

[7:0]

Phase slew rate limit, Bits[15:8].

Default: 0x00.

Table 60. History Accumulation Timer

Address Bits Bit Name

[7:0] History accumulation timer (ms)

Description

0x0314

History accumulation timer bits[7:0].

Default: 0x0A. For Register 0x0314 and Register 0x0315, 0x000A = 10 ms.

Maximum is 65 sec. This register controls the amount of tuning word averaging used

to determine the tuning word used in holdover. Never program a timer value of

zero. The default value is 0x000A = 10 decimal, which equates to 10 ms

0x0315

[7:0]

History accumulation timer bits[15:8].

Default: 0x00.

Rev. A | Page 77 of 104

AD9558

Data Sheet

Table 61. History Mode

Address Bits

Bit Name

Description

0x0316 [7:5] Reserved

Reserved.

4

3

Single sample fallback

Persistent history

Controls holdover history. If tuning word history is not available for the reference

that was active just prior to holdover, then:

0 (default) = uses the free run frequency tuning word register value.

1 = uses the last tuning word from the DPLL.

Controls holdover history initialization. When switching to a new reference:

0 (default) = clears the tuning word history.

1 = retain the previous tuning word history.

[2:0] Incremental average

History mode value from 0 to 7 (default: 0).

When set to non-zero, causes the first history accumulation to update prior to the

first complete averaging period. After the first full interval, updates occur only at the

full period.

0 (default) = update only after the full interval has elapsed.

1 = update at 1/2 the full interval.

2 = update at 1/4 and 1/2 of the full interval.

3 = update at 1/8, 1/4, and 1/2 of the full interval.

...

7 = update at 1/256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, and 1/2 of the full interval.

Table 62. Base Digital Loop Filter with High Phase Margin (PM = 88.5°, BW = 0.1 Hz, Third Pole Frequency = 10 Hz, N1 = 1)¹

Address Bits

Bit Name

Description

0x0317

0x0318

0x0319

[7:0] HPM Alpha-0 linear

[7:0]

Alpha-0 coefficient linear bits[7:0]. Default: 0x8C

Alpha-0 coefficient linear bits[15:8]

Reserved

7

Reserved

[6:0] HPM Alpha-1 exponent

[7:0] HPM Beta-0 linear

[7:0]

Alpha-1 coefficient exponent bits[6:0]

Beta-0 coefficient linear bits[7:0]

Beta-0 coefficient linear bits[15:8]

Reserved

0x031A

0x031B

0x031C

7

Reserved

[6:0] HPM Beta-1 exponent

[7:0] HPM Gamma-0 linear

[7:0]

Beta-1 coefficient exponent bits[6:0]

Gamma-0 coefficient linear bits[7:0]

Gamma-0 coefficient linear bits[15:8]

Reserved

0x031D

0x031E

0x031F

7

Reserved

[6:0] HPM Gamma-1 exponent

[7:0] HPM Delta-0 linear

[7:0]

Gamma-1 coefficient exponent bits[6:0]

Delta-0 coefficient linear bits[7:0]

Delta-0 coefficient linear bits[15:8]

Reserved

0x0320

0x0321

0x0322

7

Reserved

[6:0] HPM Delta-1 exponent

Delta-1 coefficient exponent bits[6:0]

¹Note that the base digital loop filter coefficients (α, β, γ, and δ) have the following general form: x(2y), where x is the linear component and y is the exponential

component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 ≤ x ≤ 1. The exponential component (y) is a signed integer.

Rev. A | Page 78 of 104

Data Sheet

AD9558

Table 63. Base Digital Loop Filter with Normal Phase Margin (PM = 70°, BW = 0.1 Hz, Third Pole Frequency = 2 Hz, N1 = 1)¹

Address

0x0323

0x0324

0x0325

Bits

Bit Name

Description

[7:0] NPM Alpha-0 linear

[7:0]

Alpha-0 coefficient linear, Bits[7:0]

Alpha-0 coefficient linear, Bits[15:8]

Reserved

7

Reserved

[6:0] NPM Alpha-1 exponent

[7:0] NPM Beta-0 linear

[7:0]

Alpha-1 coefficient exponent, Bits[6:0]

Beta-0 coefficient linear, Bits[7:0]

Beta-0 coefficient linear, Bits[15:8]

Reserved

0x0326

0x0327

0x0328

7

Reserved

[6:0] NPM Beta-1 exponent

[7:0] NPM Gamma-0 linear

[7:0]

Beta-1 coefficient exponent, Bits[6:0]

Gamma-0 coefficient linear, Bits[7:0]

Gamma-0 coefficient linear, Bits[15:8]

Reserved

0x0329

0x032A

0x032B

7

Reserved

[6:0] NPM Gamma-1 exponent

[7:0] NPM Delta-0 linear

[7:0]

Gamma-1 coefficient exponent, Bits[6:0]

Delta-0 coefficient linear, Bits[7:0]

Delta-0 coefficient linear, Bits[15:8]

Reserved

0x032C

0x032D

0x032E

7

Reserved

[6:0] NPM Delta-1 exponent

Delta-1 coefficient exponent, Bits[6:0]

¹Note that the digital loop filter base coefficients (α, β, γ, and δ) have the following general form: x(2^y), where x is the linear component and y is the exponential

component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 ≤ x ≤ 1. The exponential component (y) is a signed integer.

OUTPUT PLL CONFIGURATION (REGISTER 0x0400 TO REGISTER 0x0408)

Table 64. Output PLL Setting¹

Address

Bits Bit Name

Description

0x0400

[7:0] Output PLL (APLL)

charge pump current

LSB = 3.5 μA

00000001b = 1 × LSB; 00000010b = 2 × LSB; 11111111b = 255 × LSB

Default: 0x81 = 451 μA CP current

0x0401

[7:0] APLL N divider

Division = 14 to 255

Default: 0x14 = divide-by-20

0x0402

0x0403

[7:0] Reserved

Reserved; default: 0x00

[7:6] APLL loop filter control

Pole 2 resistor Rp2; default: 0x07

Rp2 (Ω)

Bit 7

Bit 6

500 (default)

333

250

200

0

1

0

1

0

1

[5:3]

Zero resistor, Rzero

Rzero (Ω)

1500 (default)

1250

Bit 5

Bit 4

Bit 3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1000

930

1250

1000

750

680

Rev. A | Page 79 of 104

AD9558

Data Sheet

Address

Bits Bit Name

Description

Pole 1 Cp1.

Cp1 (pF)

[2:0]

Bit 2

Bit 1

Bit 0

0

20

80

100

20

40

0

1

0

1

0

1

0

1

0

1

0

1

0

1

100

120 (default)

0x0404

0x0405

[7:1] Reserved

Default: 0x00.

0

Bypass internal Rzero

0 (default) = uses the internal Rzero resistor.

1 = bypasses the internal Rzero resistor (makes Rzero = 0 and requires the use of a series

external zero resistor).

[7:4] Reserved

Default: 0x2.

3

APLL locked controlled

sync

0 (default) = the clock distribution sync function is not enabled until the output PLL (APLL) is

calibrated and locked. After APLL calibration and lock, the output clock distribution sync is

armed, and the sync function for the clock outputs is under the control of Register 0x0500.

1 = overrides the lock detector state of the output PLL; allows Register 0x0500 to control

the output sync function, regardless of the APLL lock status.

[2:1] Reserved

Manual APLL

VCO calibration

Default: 00b.

0

1 = initiates VCO calibration. (Calibration occurs on low-to-high transition.)

0 (default) = does nothing. This is not an autoclearing bit.

¹Note that the default APLL loop BW is 180 KHz.

Table 65. Reserved

Address

Bits Bit Name

Description

0x0406

[7:0] Reserved

Default: 0x00

Table 66. RF Divider Setting

Address

Bits Bit Name

Description

0x0407

[7:4] RF Divider 2 division

0000/0001 = 3

0010 = 4

0011 = 5

0100 = 6 (default)

0101 = 7

0110 = 8

0111 = 9

1000 = 10

1001 = 11

[3:0] RF Divider 1 division

0000/0001 = 3

0010 = 4

0011 = 5

0100 = 6 (default)

0101 = 7

0110 = 8

0111 = 9

1000 = 10

1001 = 11

0x0408

[7:5] Reserved

RF divider start-up mode

Reserved. Default: 000b

4

0 (default) = RF dividers are held in power-down until the APLL feedback divider is

detected, which ensures proper RF divider operation when exiting full power-down

1 = RF dividers are not held in power-down until the APLL feedback divider is detected

[3:2] Reserved

Reserved. Default: 00b

1

PD RF Divider 2

0 = enables RF Divider 2

1 (default) = powers down RF Divider 2

0

PD RF Divider 1

0 (default) = enables RF Divider 1

1 = powers down RF Divider 1

Rev. A | Page 80 of 104

Data Sheet

AD9558

OUTPUT CLOCK DISTRIBUTION (REGISTER 0x0500 TO REGISTER 0x0515)

Table 67. Clock Distribution Output Synchronization Settings

Address

Bits Bit Name

Description

0x0500

7

6

5

Mask Channel 3 sync

Masks the synchronous reset to the Channel 3 (M3) divider.

0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.

1 = masked. Setting this bit asynchronously releases Channel 3 from the static SYNC state,

thus allowing the Channel 3 divider to toggle. Channel 3 ignores all SYNC events while

this bit is set. Setting this bit does not enable the output drivers connected to this channel. In

addition, the output distribution sync also depends on the setting of Register 0x0405[3].

Mask Channel 2 sync

Mask Channel 1 sync

Masks the synchronous reset to the Channel 2 (M2) divider.

0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.

1 = masked. Setting this bit asynchronously releases Channel 2 from the static SYNC state,

thus allowing the Channel 2 divider to toggle. Channel 2 ignores all SYNC events while

this bit is set. Setting this bit does not enable the output drivers connected to this channel. In

addition, the output distribution sync also depends on the setting of Register 0x0405[3].

Masks the synchronous reset to the Channel 1 (M2) divider.

0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.

1 = masked. Setting this bit asynchronously releases Channel 1 from the static SYNC state,

thus allowing the Channel 1 divider to toggle. Channel 1 ignores all SYNC events while

this bit is set. Setting this bit does not enable the output drivers connected to this

channel. In addition, the output distribution sync also depends on the setting of Register

0x0405[3].

4

Mask Channel 0 sync

Masks the synchronous reset to the Channel 0 (M0) divider.

0 (default) = unmasked. The output drivers do not toggle until a SYNC pulse occurs.

1 = masked. Setting this bit asynchronously releases Channel 0 from the static SYNC state,

thus allowing the Channel 0 divider to toggle. Channel 0 ignores all SYNC events while

this bit is set. Setting this bit does not enable the output drivers connected to this channel. In

addition, the output distribution sync also depends on the setting of Register 0x0405[3].

3

2

Reserved

Default: 0b.

Sync source selection

Selects the sync source for the clock distribution output channels.

0 (default) = direct. The sync pulse happens on the next I/O update.

1 = active reference.

Note that the output distribution sync also depends on the APLL being calibrated and

locked unless Register 0x0405[3] = 1b.

[1:0] Automatic sync mode

Autosync mode.

00 = disabled. A sync command must be issued manually, or by using the mask sync bits

in this register (Bits[7:4]).

01 = sync on DPLL frequency lock.

10 (default) = sync on DPLL phase lock.

11 = reserved.

Rev. A | Page 81 of 104

AD9558

Data Sheet

Table 68. Distribution OUT0 Setting

Address

Bits Bit Name

Description

0x0501

7

Enable 3.3 V CMOS driver 0 (default) = disables 3.3V CMOS driver; the OUT5 1.8V logic is controlled by Register 0x0501[6:4].

1 = enables 3.3 V CMOS driver as operating mode of OUT0.

This bit should be enabled only if Bits[6:4] are in CMOS mode.

[6:4] OUT0 format

This control is valid when Register 0x0501[7] = 0.

When Register 0x0501[7] = 1, OUT5 is in 3.3 V CMOS mode and these bits are ignored.

Select the operating mode of OUT0.

000 = PD, tristate.

001 (default) = HSTL.

010 = LVDS.

011 = reserved.

100 = CMOS, both outputs active.

101 = CMOS, P output active, N output power-down.

110 = CMOS, N output active, P output power-down.

111 = reserved.

[3:2] OUT0 polarity

Control the OUT0 polarity.

00 (default) = positive, negative.

01 = positive, positive.

10 = negative, positive.

11 = negative, nevative.

1

0

OUT0 drive strength

Controls the output drive capability of OUT0.

0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal.

1 = CMOS: normal drive strength; LVDS: 4.5 mA nominal (LVDS boost mode).

Note that this is only in 3.3 V CMOS mode for CMOS strength.

1.8 V CMOS has only the low drive strength.

Enable OUT0

Enables/disables (1b/0b) OUT0 1.8 V driver (default is disabled).

This bit does not enable/disable OUT0 if Bit 7 of this register is set.

Table 69. Distribution Channel 0 Divider Setting

Address

Bits Bit Name

Description

0x0502

[7:0] Channel 0 (M0)

division ratio

10-bit channel divider bits[7:0] (LSB).

Division equals channel divider, Bits[9:0] + 1.

(Bits[9:0] = 0 is divide-by-1, Bits[9:0] = 1 is divide-by-2…Bits[9:0] = 1023 is divide-by-1024)

0x0503

[7:4] Reserved

Reserved.

3

Channel 0 PD

0 (default) = normal operation.

1 = powers down Channel 0.

2

Select RF Divider 2

1 = selects RF Divider 2 as prescaler for Channel 0 divider.

0 (default) = selects RF Divider 1 as prescaler for Channel 0 divider.

[1:0] Channel 0 (M0)

division ratio

10-bit channel divider, Bits[9:8] (MSB)

0x0504

[7:6] Reserved

Reserved. Default: 00b

[5:0] Channel 0 divider phase

Divider initial phase after sync relative to the divider input clock (from the RF divider

output). LSB is ½ of a period of the divider input clock. Default: 00000b.

Phase = 0 is no phase offset.

Phase = 1 is ½ a period offset.

Rev. A | Page 82 of 104

Data Sheet

AD9558

Table 70. Distribution OUT1 Setting

Address

Bits Bit Name

Reserved

[6:4] OUT1 format

Description

0x0505

7

Reserved; default: 0b

Select the operating mode of OUT1

000 = PD, tristate

001 (default) = HSTL

010 = LVDS

011 = reserved

100 = CMOS, both outputs active

101 = CMOS, P output active, N output power-down

110 = CMOS, N output active, P output power-down

111 = reserved

[3:2] OUT1 polarity

Configure the OUT1 polarity in CMOS mode and are active in CMOS mode only

00 (default) = positive, negative

01 = positive, positive

10 = negative, positive

11 = negative, negative

1

OUT1 drive strength

Controls the output drive capability of OUT1

0 (default) = LVDS: 3.5 mA nominal

1 = LVDS: 4.5 mA nominal (LVDS boost mode)

No CMOS control because OUT1 is 1.8 V CMOS only

0

7

Enable OUT1

Reserved

Setting this bit enables the OUT1 driver (default is disabled)

Reserved; default: 0b

0x0506

[6:4] OUT2 format

Select the operating mode of OUT2

000 = PD, tristate

001 (default) = HSTL

010 = LVDS

011 = reserved

100 = CMOS, both outputs active

101 = CMOS, P output active, N output power-down

110 = CMOS, N output active, P output power-down

111 = reserved

[3:2] OUT2 polarity

Configure the OUT2 polarity in CMOS mode and are active in CMOS mode only

00 (default) = positive, negative

01 = positive, positive

10 = negative, positive

11 = negative, negative

1

0

OUT2 drive strength

Controls the output drive capability of OUT2

0 (default) = LVDS: 3.5 mA nominal

1 = LVDS: 4.5 mA nominal (LVDS boost mode)

No CMOS control because OUT2 is 1.8 V CMOS only

Enable OUT2

Setting this bit enables the OUT2 driver (default is disabled)

Table 71. Distribution Channel 1 Divider Setting

Address

0x0507

0x0508

0x0509

Bits Bit Name

Description

[7:0] Channel 1 divider

The same control for Channel 1 divider as in Register 0x0502 for Channel 0 divider

The same control for Channel 1 divider as in Register 0x0503 for Channel 0 divider

The same control for Channel 1 divider as in Register 0x0504 for Channel 0 divider

Table 72. Clock Distribution Channel 2 and OUT3, OUT4 Driver Settings

Address

0x050A

0x050B

0x050C

0x050D

0x050E

Bits Bit Name

Description

[7:0] OUT3

The same control for OUT3 as in Register 0x0505 for OUT1

The same control for OUT4 as in Register 0x0505 for OUT1

The same control for Channel 2 divider as in Register 0x0502 for Channel 0 divider

The same control for Channel 2 divider as in Register 0x0503 for Channel 0 divider

The same control for Channel 2 divider as in Register 0x0504 for Channel 0 divider

[7:0] OUT4

[7:0] Channel 2 divider

Rev. A | Page 83 of 104

AD9558

Data Sheet

Table 73. Clock Distribution Channel 3 and OUT5 Driver Settings

Address

Bits

Bit Name

Description

0x050F

7

Enable 3.3 V CMOS driver 0 (default) = disable 3.3 V CMOS driver; the OUT5 1.8 V logic is controlled by Register 0x050F[6:4].

1 = enable 3.3 V CMOS driver as operating mode of OUT5.

This bit should be enabled only if Bits[6:4] are in CMOS mode.

[6:4] OUT5 format

This control is valid when Register 0x050F[7] = 0; when Register 0x050F[7] = 1, OUT5 is in 3.3 V

CMOS mode and these bits are ignored.

Select the operating mode of OUT5.

000 = PD, tristate.

001 (default) = HSTL.

010 = LVDS.

011 = reserved.

100 = CMOS, both outputs active.

101 = CMOS, P output active, N output power-down.

110 = CMOS, N output active, P output power-down.

111 = reserved.

[3:2] OUT5 polarity

Control the OUT5 polarity.

00 (default) = positive, negative.

01 = positive, positive.

10 = negative, positive.

11 = negative, negative.

1

0

OUT5 drive strength

Controls the output drive capability of OUT5.

0 (default) = CMOS: low drive strength, LVDS: 3.5 mA nominal.

1 = CMOS: normal drive strength, LVDS: 4.5 mA nominal (LVDS boost mode).

Note that this is only in 3.3 V CMOS mode for CMOS strength.

1.8 V CMOS has only the low drive strength.

OUT5 enable

Enables/disables (1b/0b) OUT5 1.8 V driver (default is disabled).

This bit does not enable/disable OUT5 if Bit 7 of this register is set.

0x0510

0x0511

0x0512

0x0513

[7:0] Channel 3, Divider 1 (M3) 10-bit channel divider, Bits[7:0] (LSB) (default: 0x03).

division ratio

Division equals channel divider, Bits[9:0] + 1.

(Bits[9:0] = 0 is divide-by-1, Bits[9:0] = 1 is divide-by-2…Bits[9:0] = 1023 is divide-by-1024).

[7:2] Reserved

Reserved.

[1:0] Channel 3, Divider 1 (M3) 10-bit channel divider, Bits[9:8] (MSB) (default: 0x00).

division ratio

[7:0] Channel 3, Divider 2

(M3b) division ratio

10-bit channel divider, Bits[7:0] (LSB).

Division equals channel divider bits[9:0] + 1 .

(Bits[9:0] = 0 is divide-by-1, Bits[9:0] = 1 is divide-by-2…Bits[9:0] = 1023 is divide-by-1024).

[7:4] Reserved

Reserved.

4

Channel 3 doubler

0 (default) = normal operation.

1 = enables Channel 3 clock doubler. This bit activates an internal clock doubler that doubles

the frequency of the Channel 3 divider. In this mode, Channel 3, Divider 2 is bypassed.

3

2

PD Channel 3

0 (default) = normal operation.

1 = powers down Channel 3.

Select RF divider

for Channel 2

1 = selects RF Divider 2 as prescaler for the Channel 3 divider.

0 (default) = selects RF Divider 1 as a prescaler for the Channel 3 divider.

[1:0] Channel 3, Divider 2

(M3b) division ratio

10-bit channel divider, Bits[9:8] (MSB).

0x0514

0x0515

[7:0] Channel 3, Divider 1 (M3) The same control for Channel 3, Divider 1 phase as found in Register 0x0504 for Channel 0

phase

divider phase (default: 0x00).

[7:0] Channel 3, Divider 2

(M3b) phase

The same control for Channel 3, Divider 2 phase as found in Register 0x0504 for Channel 0

divider phase (default: 0x00).

Rev. A | Page 84 of 104

Data Sheet

AD9558

REFERENCE INPUTS (REGISTER 0x0500 TO REGISTER 0x0507)

Table 74. Reference Power-Down¹

Address

Bits

[7:4]

3

Bit Name

Description

0x0600

Reserved

Default: 0x0

REFD power-down

REFC power-down

REFB power-down

REFA power-down

Power down REFD input receiver (default: not powered down).

Power down REFC input receiver (default: not powered down).

Power down REFB input receiver (default: not powered down).

Power down REFA input receiver (default: not powered down).

2

1

0

¹When all bits are set the reference receiver section enters a deep sleep mode.

Table 75. Reference Logic Family

Address

Bits

Bit Name

Description

0x0601

[7:6]

REFD logic family

Select logic family for REFD input receiver; only REFD_P is used in CMOS mode

00 (default) = differential

01 = 1.2 V to 1.5 V CMOS

10 = 1.8 V to 2.5 V CMOS

11 = 3.0 V to 3.3 V CMOS

[5:4]

[3:2]

[1:0]

REFC logic family

REFB logic family

REFA logic family

Same as Register 0x0601[7:6] for REFC

Same as Register 0x0601[7:6] for REFB

Same as Register 0x0601[7:6] for REFA

Table 76. Reference Priority Setting

Address

Bits

Bit Name

Description

0x0602

[7:6]

REFD priority family

User-assigned priority level (0 to 3) of the reference associated with REFB, which ranks that

reference relative to the others.

00 (default) = 0.

01 = 1.

10 = 2.

11 = 3.

[5:4]

[3:2]

[1:0]

REFC priority family

REFB priority family

REFA priority family

Same as Register 0x0602[7:6] for REFC.

Same as Register 0x0602[7:6] for REFB.

Same as Register 0x0602[7:6] for REFA.

Rev. A | Page 85 of 104

AD9558

Data Sheet

FRAME SYNCHRONIZATION (REGISTER 0x0640 TO REGISTER 0x0641)

Table 77. Frame Sync Setting

Address

Bit(s)

[7:1]

0

Bit Name

Reserved

Description

0x0640

Reserved; default: 0x00.

Enable Fsync

Enable frame synchronization.

0 (default) = frame synchronization disabled.

1 = frame synchronization enabled.

0x0641

[7:4]

3

Reserved

Reserved; default: 0x00.

Validate Fsync ref

Setting this bit forces the reference validation logic to declare REFA valid only if the

REFB (the sync pulse) input is also valid. This bit can be thought as a logical AND of

REFA VALID and REFB VALID signals . If REFC is selected, this bit requires that REFD

(the sync pulse) input also be valid before declaring REFC valid.

0 (default) = only the selected reference input must be valid.

1 = the sync pulse input must also be valid to validate the selected input.

2

Fsync one shot

Selects one-shot or level-sensitve frame sync function.

0 (default) = use level-sensitive frame sync. Frame sync occurs on every edge of the

frame pulse.

1 = use one-shot frame sync. Frame sync occurs only on the first frame sync pulse

(on REFB or REFD). User must re-arm by raising the SYNC pin high and then low, or

by clearing and resetting the arm soft Fsync bit. As with all buffered regsiters, an

I/O update is required (Register 0x0005[0] = 0x01) after writing this register.

1

0

Fsync arm method

Arm soft Fsync

Selects which signal is used to arm the frame sync

0 (default) = use SYNC pin.

1 = use arm soft Fsync (Register 0x0641[0]).

Arms frame sync after I/O update. Next pulse on REFB or REFD is the sync pulse. The

Fsync arm method bit must also be set for this bit to take effect.

0 = (default); frame sync unarmed.

1 = frame sync armed.

Rev. A | Page 86 of 104

Data Sheet

AD9558

DPLL PROFILE REGISTERS (REGISTER 0x0700 TO REGISTER 0x07E6)

Note that the default values of the REFA and REFC profiles are as follows: input frequency=19.44 MHz, output frequency = 622.08 MHz/

155.52 MHz, loop bandwidth = 400 Hz, normal phase margin, inner tolerance = 5%, and outer tolerance = 10%.

The default values of the REFB and REFD profiles are as follows: input frequency = 8 kHz, output frequency = 622.08 MHz/155.52 MHz,

loop bandwidth = 100 Hz, normal phase margin, inner tolerance = 5%, and outer tolerance = 10%.

REFA Profile (Register 0x0700 to Register 0x0726)

Table 78. Reference Period—REFA Profile

Address

0x0700

0x0701

0x0702

0x0703

0x0704

Bits

Bit Name

Description

[7:0] Nominal reference period (fs) Nominal reference period bits[7:0] (default: 0xC9).

[7:0]

Nominal reference period bits[15:8] (default: 0xEA).

Nominal reference period bits[23:16] (default: 0x10).

Nominal reference period bits[31:24] (default: 0x03).

Nominal reference period bits[39:32] (default: 0x00).

Default for Register 0x0700 to Register 0x0704 = 0x000310EAC9 = 51.44 ns (1/19.44 MHz).

Table 79. Reference Period Tolerance—REFA Profile

Address

0x0705

0x0706

0x0707

Bits

Bit Name

Description

[7:0] Inner tolerance

[7:0]

Input reference frequency monitor inner tolerance, Bits[7:0] (default: 0x14).

Input reference frequency monitor inner tolerance, Bits[15:8] (default: 0x00).

Default: 0x0.

[7:4] Reserved

[3:0] Inner tolerance

Input reference frequency monitor inner tolerance, Bits[19:16].

Default for Register 0x0705 to Register 0x707 = 0x000014 = 20 (5% or 50,000 ppm).

The Stratum 3 clock requires inner tolerance of 9.2 ppm and outer tolerance of

12 ppm; an SMC clock requires an outer tolerance of 48 ppm.

The allowable range for the inner tolerance is 0x00A (10%) to 0x8FF (1 ppm).

The tolerance of the input frequency monitor is only as accurate as the system clock

frequency.

0x0708

0x0709

0x070A

[7:0] Outer tolerance

[7:0]

Input reference frequency monitor outer tolerance, Bits[7:0] (default: 0x0A).

Input reference frequency monitor outer tolerance, Bits[15:8] (default: 0x00).

Reserved.

[7:4] Reserved

[3:0] Outer tolerance

Input reference frequency monitor outer tolerance, Bits[19:16].

Default for Register 0x0708 to Register 0x70A = 0x00000A = 10 (10% or 100,000 ppm).

The Stratum 3 clock requires an inner tolerance of 9.2 ppm and outer tolerance of

12 ppm; an SMC clock requires outer tolerance of 48 ppm.

The outer tolerance register setting should always be smaller than the inner tolerance.

Table 80. Reference Validation Timer—REFA Profile

Address

Bits

Bit Name

Description

0x070B

[7:0] Validation timer (ms)

Validation timer, Bits[7:0] (default: 0x0A).

This is the amount of time a reference input must be valid before it is declared valid by

the reference input monitor (default: 10 ms).

0x070C

[7:0]

Validation timer, Bits[15:8] (default: 0x00).

Table 81. Reserved Register

Address

Bits

Bit Name

Description

0x070D

[7:0] Reserved

Reserved. Default: 0x00.

Table 82. DPLL Base Loop Filter Selection—REFA Profile

Address Bits Bit Name Description

0x070E [7:1] Reserved

Sel high PM base loop filter

Reserved. Default: 0x00.

0

0 = base loop filter with normal (70°) phase margin (default).

1 = base loop filter with high (88.5°) phase margin.

(≤0.1 dB peaking in the closed-loop transfer function for loop BWs ≤ 2 kHz. Setting this

bit is also recommended for loop BW > 2kHz.)

Rev. A | Page 87 of 104

AD9558

Data Sheet

Table 83. DPLL Loop BW Scaling Factor—REFA Profile¹

Address Bits Bit Name

Description

0x070F

0x0710

[7:0] DPLL loop BW scaling factor

(unit of 0.1 Hz)

Digital PLL loop bandwidth scaling factor, Bits[7:0] (default: 0xF4).

[7:0]

Digital PLL loop bandwidth scaling factor, Bits[15:8] (default: 0x01).

The default for Register 0x070F to Register 0x0710 = 0x01F4 = 500 (50 Hz loop bandwidth).

The loop bandwidth should always be less than the DPLL phase detector frequency

divided by 20.

0x0711

[7:1] Reserved

BW scaling factor

Default: 0x00.

0

Digital PLL loop bandwidth scaling factor, Bit 16 (default: 0b).

¹Note that the default DPLL loop BW is 50.4 Hz.

Table 84. R-Divider—REFA Profile¹

Address Bits Bit Name

Description

0x0712

0x0713

0x0714

[7:0] R divider

[7:0]

DPLL integer reference divider (minus 1), Bits[7:0] (default: 0xC5)

DPLL integer reference divider, Bits[15:8] (default: 0x00)

Reserved. Default: 0x0

[7:5] Reserved

4

Enable REFA div2

Enables the reference input divide-by-2 for REFA

0 = bypass the divide-by-2 (default)

1 = enable the divide-by-2

[3:0] R divider

DPLL integer reference divider, Bits[19:16] (default: 0x0).

The default for Register 0x0712 to Register 0x0714 = 0x000C5 = 197 (which equals R = 198).

¹Note that the value stored in the R-divider register yields an actual divide ratio of one more than the programmed value.

Table 85. Integer Part of Fractional Feedback Divider N1—REFA Profile¹

Address Bits Bit Name

Description

0x0715

0x0716

0x0717

[7:0] Integer Part N1

[7:0]

DPLL integer feedback divider (minus 1), Bits[7:0] (default: 0x6B).

DPLL integer feedback divider, Bits[15:8] (default: 0x07).

Reserved. Default: 0x00.

[7:1] Reserved

0

Integer Part N1

DPLL integer feedback divider, Bit 16 (default: 0b).

The default for Register 0x0715 to Register 0x717 = 0x0076B (which equals N1 = 1900).

¹Note that the value stored in the N1-divider register yields an actual divide ratio of one more than the programmed value.

Table 86. Fractional Part of Fractional Feedback Divider FRAC1—REFA Profile

Address Bits Bit Name

Description

0x0718

0x0719

0x071A

[7:0] Digital PLL fractional feedback The numerator of the fractional-N feedback divider, Bits[7:0] (default: 0x04)

divider—FRAC1

[7:0]

The numerator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)

The numerator of the fractional-N feedback divider, Bits[23:16] (default: 0x00)

Table 87. Modulus of Fractional Feedback Divider MOD1—REFA Profile

Address Bits Bit Name

Description

0x071B

0x071C

0x071D

[7:0] Digital PLL feedback divider

The denominator of the fractional-N feedback divider, Bits[7:0] (default: 0x05)

The denominator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)

The denominator of the fractional-N feedback divider, Bits[23:16] (default: 0x00)

modulus—MOD1

[7:0]

Table 88. Phase and Frequency Lock Detector Controls—REFA Profile

Address Bits Bit Name

Description

0x071E

0x071F

0x0720

0x0721

0x0722

0x0723

0x0724

0x0725

0x0726

[7:0] Phase lock threshold

Phase lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps

Phase lock threshold, Bits[15:8] (default: 0x02)

[7:0]

[7:0] Phase lock fill rate

[7:0] Phase lock drain rate

[7:0] Frequency lock threshold

[7:0]

Phase lock fill rate, Bits[7:0] (default:0x0A = 10 code/PFD cycle)

Phase lock drain rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)

Frequency lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps

Frequency lock threshold, Bits[15:8] (default: 0x02)

Frequency lock threshold, Bits[23:16] (default: 0x00)

Frequency lock fill rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)

Frequency lock drain rate bits[7:0] (default: 0x0A = 10 code/PFD cycle)

Rev. A | Page 88 of 104

[7:0]

[7:0] Frequency lock fill rate

[7:0] Frequency lock drain rate

Data Sheet

AD9558

REFB Profile (Register 0x0740 to Register 0x0766)

REFB Profile Register 0x0740 to Register 0x0766 are identical to REFA Profile Register 0x0700 to Register 0x0726.

REFC Profile (Register 0x0780 to Register 0x07A6)

REFC Profile Register 0x0780 to Register 0x07A6 are identical to REFA Profile Register 0x0700 Register 0x0726.

REFD Profile (Register 0x07C0 to Register 0x07E6)

REFD Profile Register 0x07C0 to Register 0x07E6 are identical to REFA Profile Register 0x0700 to Register 0x0726.

OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A10)

Table 89. General Power-Down

Address Bits Bit Name

Description

0x0A00

7

6

5

3

2

1

0

Soft reset exclude regmap

DCO power-down

Resets device but retains programmed register values (default: not reset)

Places DCO in deep sleep mode (default: not powered down)

SYSCLK power-down

Places SYSCLK input and PLL in deep sleep mode (default: not powered down)

Reference input power-down Places reference clock inputs in deep sleep mode (default: not powered down)

TDC power-down

APLL power-down

Clock dist power-down

Full power-down

Places the time-to-digital converter in deep sleep mode (default: not powered down)

Places the output PLL in deep sleep mode (default: not powered down)

Places the clock distribution outputs in deep sleep mode (default: not powered down)

Places the entire device in deep sleep mode (default: not powered down)

Table 90. Loop Mode

Address Bits Bit Name

Description

0x0A01

7

6

Reserved

Reserved.

User holdover

Forces the device into holdover mode (default: not forced holdover mode).

If a tuning word history is available, then the history tuning word specifies the DCO

output frequency. Otherwise, the free run frequency tuning word register specifies the

DCO output frequency.

The phase and frequency lock detectors are forced into the unlocked state.

5

User freerun

Forces the device into user free run mode (default is not forced user free run mode).

The free run frequency tuning word register specifies the DCO output frequency. When

the user freerun bit is set, it overrides the user holdover bit (Address 0x0A01, Bit 6).

[4:2] REF switchover mode

Selects the operating mode of the reference switching state machine.

Reference Switchover Mode, Bits[2:0]

Register 0x0A01[4:2]

Reference Selection Mode

000 (default)

001

010

Automatic revertive mode

Automatic nonrevertive mode

Manual reference select

(with automatic fallback mode)

Manual reference select mode

(with auto-holdover)

Full manual mode (no auto-holdover)

Not used

011

100

101

110

111

Not used

[1:0] User reference in manual

switchover mode

Input reference when REF switchover mode bits (Register 0x0A01, Bits[4:2]) = 010, 011, or 100.

00 (default) = Input Reference A.

01 = Input Reference B.

10 = Input Reference C.

11 = Input Reference D.

Table 91. Cal/Sync Distribution

Address Bits Bit Name

Description

0x0A02

[7:2] Reserved

Default: 0x00

1

Soft sync clock distribution

Setting this bit initiates synchronization of the clock distribution output (default: 0b).

Nonmasked outputs stall when value is 1b; restart is initialized on 1b to 0b transition.

0

Reserved

Default: 0b.

Rev. A | Page 89 of 104

AD9558

Data Sheet

Reset Functions (Register 0x0A03)

Table 92. Reset Functions¹

Address

Bits Bit Name

Description

0x0A03

(autoclear)

7

6

5

4

3

2

1

Reserved

Default: 0b.

Clear LF

Setting this bit clears the digital loop filter (intended as a debug tool).

Setting this bit clears the CCI filter (intended as a debug tool).

Default: 0b.

Clear CCI

Reserved

Clear auto sync

Clear TW history

Clear all IRQs

Setting this bit resets the automatic synchronization logic (see Register 0x0500).

Setting this bit resets the tuning word history logic (part of holdover functionality).

Setting this bit clears the entire IRQ monitor register (Register 0x0D02 to Register 0x0D07).

It is the equivalent of setting all the bits of the IRQ clearing register (Register 0x0A04 to

Register 0x0A0D).

0

Clear watchdog timer Setting this bit resets the watchdog timer (see Register 0x0211 and Register 0x0212). If the

timer times out, it starts a new timing cycle. If the timer has not yet timed out, it restarts at

time zero without causing a timeout event. Continuously resetting the watchdog timer at

intervals less than its timeout period prevents the watchdog timer from generating a timeout

event.

¹Note that all bits in this register are autoclearing.

IRQ Clearing (Register 0x0A04 to Register 0x0A09)

The IRQ clearing registers are identical in format to the IRQ monitor registers (Register 0x0D02 to Register 0x0D09). When set to logic 1,

an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ

clearing register is an autoclearing register.

Table 93. IRQ Clearing for SYSCLK

Address

Bits Bit Name

Description

0x0A04

[7:6] Reserved

Reserved

5

4

3

2

1

0

SYSCLK unlocked

Clears SYSCLK unlocked IRQ

Clears SYSCLK locked IRQ

Clears Output PLL unlocked IRQ

Clears Output PLL locked IRQ

Clears APLL calibration complete IRQ

Clears APLL calibration started IRQ

SYSCLK locked

APLL unlocked

APLL locked

APLL Cal ended

APLL Cal started

Table 94. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM

Address

Bits Bit Name

Description

0x0A05

[7:5] Reserved

Reserved

4

3

2

1

0

Pin program end

Clears pin program end IRQ

Clears distribution sync IRQ

Clears watchdog timer IRQ

Clears EEPROM fault IRQ

Clears EEPROM complete IRQ

Sync clock distribution

Watchdog timer

EEPROM fault

EEPROM complete

Table 95. IRQ Clearing for the Digital PLL

Address

Bits Bit Name

Description

0x0A06

7

6

5

4

3

2

1

0

Switching

Clears switching IRQ

Clears closed IRQ

Closed

Freerun

Clears free run IRQ

Holdover

Clears holdover IRQ

Frequency unlocked

Frequency locked

Phase unlocked

Phase locked

Clears frequency unlocked IRQ

Clears frequency locked IRQ

Clears phase unlocked IRQ

Clears phase locked IRQ

Rev. A | Page 90 of 104

Data Sheet

AD9558

Table 96. IRQ Clearing for History Update, Frequency Limit, and Phase Slew Limit

Address Bits

Bit Name

Description

0x0A07

[7:5]

Reserved

4

3

2

1

0

History updated

Frequency unclamped

Frequency clamped

Phase slew unlimited

Phase slew limited

Clears history updated IRQ

Clears frequency unclamped IRQ

Clears frequency clamped IRQ

Clears phase slew unlimited IRQ

Clears phase slew limited IRQ

Table 97. IRQ Clearing for Reference Inputs

Address Bits

Bit Name

Description

0x0A08

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Reserved

REFB validated

REFB fault cleared

REFB fault

Clears REFB validated IRQ

Clears REFB fault cleared IRQ

Clears REFB fault IRQ

Reserved

REFA validated

REFA fault cleared

REFA fault

Clears REFA validated IRQ

Clears REFA fault cleared IRQ

Clears REFA fault IRQ

Reserved

0x0A09

Reserved

REFD validated

REFD fault cleared

REFD fault

Clears REFD validated IRQ

Clears REFD fault cleared IRQ

Clears REFD fault IRQ

Reserved

REFC validated

REFC fault cleared

REFC fault

Clears REFC validated IRQ

Clears REFC fault cleared IRQ

Clears REFC fault IRQ

Table 98. Incremental Phase Offset Control

Address Bits Bit Name

0x0A0A [7:3] Reserved

Description

Reserved.

2

Reset phase offset

Resets the incremental phase offset to zero.

This is an autoclearing bit.

1

Decrement phase offset

Increment phase offset

Decrements the incremental phase offset by the amount specified in the incremental

phase lock offset step size registers (Register 0x0312 to Register 0x0313).

This is an autoclearing bit.

0

Increments the incremental phase offset by the amount specified in the incremental

phase lock offset step size registers (Register 0x0312 to Register 0x0313).

This is an autoclearing bit.

Table 99. Reference Validation Override Controls

Address Bits

Bit Name

Description

0x0A0B [7:4] Reserved

Reserved.

3

2

1

0

Force Timeout D

Setting this autoclearing bit emulates timeout of the validation timer for Reference D

and allows the user to make REFD valid immediately.

Force Timeout C

Force Timeout B

Force Timeout A

Setting this autoclearing bit emulates timeout of the validation timer for Reference C

and allows the user to make REFC valid immediately.

Setting this autoclearing bit emulates timeout of the validation timer for Reference B

and allows the user to make REFB valid immediately.

Setting this autoclearing bit emulates timeout of the validation timer for Reference A

and allows the user to make REFA valid immediately.

0x0A0C

[7:4] Reserved

Reserved.

3

2

1

0

Ref Mon Override D

Overrides the reference monitor REF FAULT signal for Reference D (default: 0).

Overrides the reference monitor REF FAULT signal for Reference C (default: 0).

Overrides the reference monitor REF FAULT signal for Reference B (default: 0).

Ref Mon Override C

Ref Mon Override B

Ref Mon Override A

Overrides the reference monitor REF FAULT signal for Reference A (default: 0).

Rev. A | Page 91 of 104

AD9558

Data Sheet

Address Bits

Bit Name

Description

0x0A0D

[7:4] Reserved

Reserved.

3

2

1

0

Ref Mon Bypass D

Bypasses the reference monitor for Reference D (default: 0).

Bypasses the reference monitor for Reference C (default: 0).

Bypasses the reference monitor for Reference B (default: 0).

Bypasses the reference monitor for Reference A (default: 0).

Ref Mon Bypass C

Ref Mon Bypass B

Ref Mon Bypass A

QUICK IN/OUT FREQUENCY SOFT PIN CONFIGURATION (REGISTER 0x0C00 TO REGISTER 0x0C08)

Table 100. Soft Pin Program Setting¹

Address Bits

Bit Name

Description

0x0C00

[7:1] Reserved

Reserved.

0

Enable Soft Pin Section 1

0 (default) = disables the function of soft pin registers in Soft Pin Section 1 (Register

0x0C01 and Register 0x0C02).

1 = enables the function of soft pin registers in Soft Pin Section 1 (Register 0x0C01 to

Register 0x0C02) when the PINCONTROL pin is low at startup and/or reset.

The register in Soft Pin Section 1 configures the part into one of 256 preconfigured

input-to-output frequency translations stored in the on-chip ROM.

The registers in Soft Pin Section 1 (Register 0x0C00 to Register 0x0C02) are ignored

when the PINCONTROL pin is high at power-up and/or reset (which means the hard pin

program is enabled).

0x0C01

0x0C02

[7:4] Output frequency selection

[3:0] Input frequency selection

[7:2] Reserved

Selects one of 16 predefined output frequencies as ouptut freqeuncy of the desired

frequency translation and reprograms the free run TW, N2, RF divider, and M0 to M3b

dividers with the value stored in the ROM.

Selects one of 16 predefined input frequencies as the input frequency of the desired

frequency translation and reprograms the reference period, R divider, N1, FRAC1, and

MOD1 in four REF profiles with the value stored in the ROM.

Reserved.

[1:0] System clock PLL ref

selection

Selects one of the four predefined system PLL references for the desired frequency

translation and reprograms the system PLL configuration with the value stored in the

ROM. To load values from the ROM, the user must write Register 0x0C07[0] = 1 after writing

this.

Equivalent System Clock PLL Settings,

Register 0x0C02[1:0] Register 0x0100 to Register 0x101[3:0]

System PLL Ref

Bit 1

Bit 0

12 Bits

1

0

1

0

1

0

1

24.576 MHz XTAL, ×2 on, N = 8

49.152 MHz XTAL, ×2 on, N = 8

24.576 MHz XO, ×2 off, N = 16

49.152 MHz XO, ×2 off, N = 8

2

3

4

0x0C03

0x0C04

[7:1] Reserved

Reserved.

0

Enable Soft Pin Section 2

0 (default) = disables the function of soft pin registers in Soft Pin Section 2 (Register

0x0C04 to Register 0x0C06).

1 = enables the function of soft pin registers in Soft Pin Section 2 (Register 0x0C04 to

Register 0x0C06) when PINCONTROL pin is low.

[7:4] Reserved

Reserved.

[3:2] REFB frequency scale

Scales the the selected input frequency (defined by Register 0x0C01[3:0]) for REFB.

00 (default) = divide-by-1.

01 = divide-by-4.

10 = divide-by-8.

11 = divide-by-16.

For example, if the selected input frequency is 622.08 MHz and Register 0x0C04[3:2] =

11, the new input frequency should be 622.08 MHz/16 = 38.8 MHz

[1:0] REFA frequency scale

Scales the the selected input frequency (defined by Register 0x0C01[3:0]) for REFA.

00 (default) = divide-by-1.

01 = divide-by-4.

10 = divide-by-8.

11 = divide-by-16.

Rev. A | Page 92 of 104

Data Sheet

AD9558

Address Bits

Bit Name

Description

0x0C05

[7:4] Reserved

Reserved.

[3:2] Channel 1 output frequency

scale

Scales the selected output frequency (defined by Register 0x0C01[7:4]) for the Channel

Divider 1 output.

00 (default) = divide-by-1.

01 = divide-by-4.

10 = divide-by-8.

11 = divide-by-16.

[1:0] Channel 0 output frequency

scale

Scale the selected output frequency (defined by Register 0x0C01[7:4]) for the Channel

Divider 0 output.

00 (default) = divide-by-1.

01 = divide-by-4.

10 = divide-by-8.

11 = divide-by-16.

0x0C06

[7:5] Reserved

Reserved.

4

Sel high PM base loop filter

0 = base loop filter with normal (70°) phase margin (default).

1 = base loop filter with high (88.5°) phase margin.

(< 0.1 dB peaking in closed-loop transfer function).

[3:2] DPLL loop BW

Scale the DPLL loop BW while in soft pin mode.

00 (default) = 50 Hz.

01 = 1 Hz.

10 = 10 Hz.

11 =100 Hz.

[1:0] Reference input frequency

tolerance

Scales the input frequency tolerance while in soft pin mode.

00 (default) = outer tolerance: 10%; inner tolerance: 8% (for general conditions).

01 = outer tolerance: 12 ppm; inner tolerance: 9.6 ppm (for Stratum 3).

10 = outer tolerance: 48 ppm; inner tolerance: 38 ppm (for SMC clock standard).

11 = outer tolerance: 200 ppm; inner tolerance: 160 ppm (for XTAL system clock).

0x0C07

0x0C08

[7:1] Reserved

Reserved.

0

Soft pin start transfer

Autoclearing register. 1 = initiates ROM download without resetting the part/register map.

After ROM download is complete, this register is reset.

[7:1] Reserved

Soft pin reset

Reserved.

0

Autoclearing register; resets the part like soft reset (Register 0x0000[5]), except that this

reset function initiates a soft pin ROM download without resetting the part/register map.

After ROM download is complete, this register is pulled back to zero.

¹All bits in Register 0x0C00 to Register 0x0C06 take effect only with either a soft pin start transfer (Register 0x0C07) or soft pin reset (Register 0x0C08).

STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D14)

All bits in Register 0x0D00 to Register 0x0D14 are read only. To show the latest status, these registers require an I/O update (Register 0x0005 =

0x01) immediately before being read.

Table 101. EEPROM Status

Address Bits

Bit Name

Description

0x0D00

[7:4]

Reserved

Reserved.

3

2

1

0

Pin program ROM load process The control logic sets this bit when data is being read from the ROM.

Fault detected

Load in progress

Save in progress

An error occurred while saving data to or loading data from the EEPROM.

The control logic sets this bit while data is being read from the EEPROM.

The control logic sets this bit while data is being written to the EEPROM.

Rev. A | Page 93 of 104

AD9558

Data Sheet

Table 102. SYSCLK Status

Address Bits

Bit Name

Description

0x0D01

7

6

Reserved

Reserved.

DPLL_APLL_Lock

Indicates the status of the DPLL and APLL.

0 = either the DPLL or the APLL is unlocked.

1 = both the DPLL and APLL are locked.

5

4

All PLLs locked

Indicates the status of the system clock PLL, APLL, and DPLL.

0 = system clock PLL or APLL or DPLL is unlocked.

1 = all three PLLs (system clock PLL, APLL, and DPLL) are locked.

APLL VCO status

1 = OK.

0 = off/clocks are missing.

3

2

APLL cal in process

APLL lock

The control logic holds this bit set while the amplitude calibration of the APLL VCO is in progress.

Indicates the status of the APLL.

0 = unlocked.

1 = locked.

1

0

System clock stable

SYSCLK lock detect

The control logic sets this bit when the device considers the system clock to be stable (see

the System Clock Stability Timer section).

0 = not stable (the system clock stability timer has not expired yet).

1 = stable (the system clock stability timer has expired).

Indicates the status of the system clock PLL.

0 = unlocked.

1 = locked.

IRQ Monitor (Register 0x0D02 to Register 0x0D09)

If not masked via the IRQ mask registers (Register 0x0209 to Register 0x020F), the appropriate IRQ monitor bit is set to a Logic 1 when

the indicated event occurs. These bits can be cleared only via the IRQ clearing registers (Register 0x0A04 to Register 0x0A09), the reset all

IRQs bit (Register 0x0A03[1]), or a device reset.

Table 103. IRQ Monitor for SYSCLK

Address Bits

Bit Name

Description

0x0D02

[7:6]

5

Reserved

SYSCLK unlocked

SYSCLK locked

APLL unlocked

APLL locked

Indicates a SYSCLK PLL state transition from locked to unlocked

Indicates a SYSCLK PLL state transition from unlocked to locked

Indicates an output PLL state transition from locked to unlocked

Indicates an output PLL state transition from unlocked to locked

Indicates that APLL calibration is complete

Indicates that APLL in APLL calibration has begun

4

3

2

1

APLL cal ended

APLL cal started

0

Table 104. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM

Address Bit

Bit Name

Description

0x0D03 [7:5]

Reserved

4

3

2

1

0

Pin program end

Indicates successful completion of a ROM load operation

Output distribution sync Indicates a distribution sync event

Watchdog timer

EEPROM fault

Indicates expiration of the watchdog timer

Indicates a fault during an EEPROM load or save operation

Indicates successful completion of an EEPROM load or save operation

EEPROM complete

Rev. A | Page 94 of 104

Data Sheet

AD9558

Table 105. IRQ Monitor for the Digital PLL

Address

Bits

Bit Name

Description

0x0D04

7

Switching

Indicates that the DPLL is switching to a new reference

Indicates that the DPLL has entered closed-loop operation

Indicates that the DPLL has entered free run mode

Indicates that the DPLL has entered holdover mode

Indicates that the DPLL has lost frequency lock

Indicates that the DPLL has acquired frequency lock

Indicates that the DPLL has lost phase lock

Indicates that the DPLL has acquired phase lock

6

Closed

5

Freerun

4

Holdover

3

Frequency unlocked

Frequency locked

Phase unlocked

Phase locked

2

1

0

Table 106. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit

Address

Bits

Bit Name

Description

0x0D05

[7:5] Reserved

Reserved

4

3

2

1

0

History updated

Indicates the occurrence of a tuning word history update

Indicates a frequency limiter state transition from clamped to unclamped

Indicates a frequency limiter state transition from unclamped to clamped

Frequency unclamped

Frequency clamped

Phase slew unlimited

Phase slew limited

Indicates a phase slew limiter state transition from slew limiting to not slew limiting

Indicates a phase slew limiter state transition from not slew limiting to slew limiting

Table 107. IRQ Monitor for Reference Inputs

Address

Bits

Bit Name

Description

0x0D06

7

Reserved

6

REFB validated

REFB fault cleared

REFB fault

Indicates that REFB has been validated

Indicates that REFB has been cleared of a previous fault

Indicates that REFB has been faulted

Reserved

5

4

3

Reserved

2

REFA validated

REFA fault cleared

REFA fault

Indicates that REFA has been validated

Indicates that REFA has been cleared of a previous fault

Indicates that REFA has been faulted

Reserved

1

0

0x0D07

7

Reserved

6

REFD validated

REFD fault cleared

REFD fault

Indicates that REFD has been validated

Indicates that REFD has been cleared of a previous fault

Indicates that REFD has been faulted

5

4

3

Reserved

2

REFC validated

REFC fault cleared

REFC fault

Indicates that REFC has been validated

1

Indicates that REFC has been cleared of a previous fault

Indicates that REFC has been faulted

0

Rev. A | Page 95 of 104

AD9558

Data Sheet

DPLL Status, Input Reference Status, Holdover History, and DPLL Lock Detect Tub Levels (Register 0x0D08 to Register 0x0D14)

Table 108. DPLL Status¹

Address

Bits

Bit Name

Description

0x0D08

7

Reserved

6

Offset slew limiting

Frequency lock

Phase lock

Loop switching

Holdover

The current closed-loop phase offset is rate limited

The DPLL has achieved frequency lock

The DPLL has achieved phase lock

5

4

3

The DPLL is in the process of a reference switchover

The DPLL is in holdover mode

2

1

Active

The DPLL is active (that is, operating in a closed-loop condition)

The DPLL is free run (that is, operating in an open-loop condition)

Default: 0b

0

Freerun

0x0D09

[7:6] Reserved

5

4

Frequency clamped

History available

The upper or lower frequency tuning word clamp is in effect

There is sufficient tuning word history available for holdover operation

[3:2] Active reference priority

Priority value of the currently active reference

00 = highest priority

…

11 = lowest priority

[1:0] Current active reference

Index of the currently active reference

00 = Reference A

01 = Reference B

10 = Reference C

11 = Reference D

¹Note that the user must issue an I/O update by writing 0x01 to Register 0x0005 to update the status of these registers.

Table 109. Reserved Register

Address

Bits

Bit Name

Description

0x0D0A

[7:0] Reserved

Reserved.

Table 110. Input Reference Status¹

Address

Bits

Bit Name

B valid

B fault

B fast

Description

0x0D0B

7

REFB is valid for use. (It is unfaulted, and its validation timer has expired.)

REFB is not valid for use.

6

5

This bit indicates that the frequency of REFB is higher than allowed by its profile settings.

This bit indicates that the frequency of REFB is lower than allowed by its profile settings.

REFA is valid for use. (It is unfaulted, and its validation timer has expired.)

REFA is not valid for use.

4

B slow

A valid

A fault

A fast

3

2

1

This bit indicates that the frequency of REFA is higher than allowed by its profile settings.

This bit indicates that the frequency of REFA is lower than allowed by its profile settings.

Same as Register 0xDOB[7:4] but for REFD instead of REFB .

Same as Register 0xDOB[3:0] but for REFC instead of REFA.

0

A slow

0x0D0C

[7:4]

[3:0]

¹Note that the user must issue an I/O update by writing 0x01 to Register 0x0005 to update the status of these registers.

Table 111. Holdover History¹

Address

0x0D0D

0x0D0E

0x0D0F

0x0D10

Bits

Bit Name

Description

[7:0] Holdover history

Tuning word readback bits[7:0]

Tuning word readback bits[15:8]

Tuning word readback bits[23:9]

Tuning word readback bits[29:24]

[7:0]

¹Note that these registers contain the current 30-bit DCO frequency tuning word generated by the tuning word history logic.

Rev. A | Page 96 of 104

Data Sheet

AD9558

Table 112. Digital PLL Lock Detect Tub Levels¹

Address

Bits

Bit Name

Description

0x0D11

[7:0]

Phase tub

Read-only digital PLL lock detect bathtub level, Bits[7:0]; see the DPLL Frequency Lock Detector

section for details.

0x0D12

[7:4]

[3:0]

Reserved.

Read-only digital PLL lock detect bathtub level, Bits[11:8]; see the DPLL Frequency Lock

Detector section for details.

0x0D13

0x0D14

[7:0]

Frequency tub

Read-only digital PLL lock detect bathtub level, Bits[7:0]; see the DPLL Phase Lock Detector

section for details.

[7:4]

[3:0]

Reserved

Reserved.

Frequency tub

Read-only digital PLL lock detect bathtub level, Bits[11:8]; see the DPLL Phase Lock Detector

section for details.

¹These registers contain the current digital PLL lock detection bathtub levels.

EEPROM CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E03)

Table 113. EEPROM Control

Address Bits

Bit Name

Description

0x0E00

[7:1]

0

Reserved

Reserved.

Write enable

EEPROM write enable/protect.

0 (default) = EEPROM write protected.

1 = EEPROM write enabled.

0x0E01

0x0E02

[7:4]

[3:0]

[7:1]

0

Reserved

Reserved.

Conditional value

Reserved

When set to a non-zero value, it establishes the condition for EEPROM downloads. Default: 0b.

Reserved.

Save to EEPROM

Upload data to the EEPROM based on the EEPROM Storage Sequence (Register 0x0E10 to

Register 0x0E3C) section.

0x0E03

[7:2]

1

Reserved

Reserved.

Load from EPROM

Reserved

Downloads data from the EEPROM.

Reserved.

0

Rev. A | Page 97 of 104

AD9558

Data Sheet

EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3C)

The default settings of Register 0x0E10 to Register 0x0E3C contain the default EEPROM instruction sequence. The tables in this section

provide descriptions of the register defaults, based on the assumption that the controller has been instructed to carry out an EEPROM

storage sequence in which all of the registers are stored and loaded by the EEPROM.

Table 114. EEPROM Storage Sequence for System Clock Settings

Address Bits

Bit Name

Description

0x0E10

[7:0]

EEPROM ID

The default value of this register is 0x01, which the controller interprets as a data instruction. Its decimal

value is 1, so this tells the controller to transfer two bytes of data (1 + 1), beginning at the address that is

specified by the next two bytes. The controller stores 0x01 in the EEPROM and increments the EEPROM

address pointer.

0x0E11

0x0E12

0x0E13

[7:0]

The default value of these two registers is 0x0006. Note that Register 0x0E11 and Register 0x0E12 are

the most significant and least significant bytes of the target address, respectively. Because the previous

register contains a data instruction, these two registers define a starting address (in this case, 0x0006).

The controller stores 0x0006 in the EEPROM and increments the EEPROM pointer by 2. It then transfers

two bytes from the register map (beginning at Address 0x0006) to the EEPROM and increments the

EEPROM address pointer by 3 (two data bytes and one checksum byte). The two bytes transferred

correspond to the system clock parameters in the register map.

System clock The default value of this register is 0x08, which the controller interprets as a data instruction. Its decimal

value is 8, so this tells the controller to transfer nine bytes of data (8 + 1), beginning at the address that

is specified by the next two bytes. The controller stores 0x08 in the EEPROM and increments the

EEPROM address pointer.

0x0E14

0x0E15

0x0E16

[7:0]

The default value of these two registers is 0x0100. Note that Register 0x0E14 and Register 0x0E15 are

the most significant and least significant bytes of the target address, respectively. Because the previous

register contains a data instruction, these two registers define a starting address (in this case, 0x0100).

The controller stores 0x0100 in the EEPROM and increments the EEPROM pointer by 2. It then transfers

nine bytes from the register map (beginning at Address 0x0100) to the EEPROM and increments the

EEPROM address pointer by 10 (nine data bytes and one checksum byte). The nine bytes transferred

correspond to the system clock parameters in the register map.

I/O update

The default value of this register is 0x80, which the controller interprets as an I/O update instruction.

The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.

Table 115. EEPROM Storage Sequence for General Configuration Settings

Address Bits

Bit Name

Description

0x0E17

[7:0]

General

The default value of this register is 0x11, which the controller interprets as a data instruction. Its decimal

value is 17, which tells the controller to transfer 18 bytes of data (17 + 1), beginning at the address that

is specified by the next two bytes. The controller stores 0x11 in the EEPROM and increments the

EEPROM address pointer.

0x0E18

0x0E19

[7:0]

The default value of these two registers is 0x0200. Note that Register 0x0E18 and Register 0x0E19 are

the most significant and least significant bytes of the target address, respectively. Because the previous

register contains a data instruction, these two registers define a starting address (in this case, 0x0200).

The controller stores 0x0200 in the EEPROM and increments the EEPROM pointer by 2. It then transfers

18 bytes from the register map (beginning at Address 0x0200) to the EEPROM and increments the EEPROM

address pointer by 19 (18 data bytes and one checksum byte). The 18 bytes transferred correspond to

the general configuration parameters in the register map.

Table 116. EEPROM Storage Sequence for DPLL Settings

Address

Bits

Bit Name

Description

0x0E1A

[7:0] DPLL

The default value of this register is 0x2E, which the controller interprets as a data instruction. Its decimal

value is 46, which tells the controller to transfer 47 bytes of data (46 + 1), beginning at the address that

is specified by the next two bytes. The controller stores 0x2E in the EEPROM and increments the EEPROM

address pointer.

0x0E1B

0x0E1C

[7:0]

The default value of these two registers is 0x03. Note that Register 0x0E1B and Register 0x0E1C are the

most significant and least significant bytes of the target address, respectively. Because the previous

register contains a data instruction, these two registers define a starting address (in this case, 0x0300).

The controller stores 0x0300 in the EEPROM and increments the EEPROM pointer by 2. It then transfers

47 bytes from the register map (beginning at Address 0x0300) to the EEPROM and increments the EEPROM

address pointer by 48 (47 data bytes and one checksum byte). The 47 bytes transferred correspond to

the DPLL parameters in the register map.

Rev. A | Page 98 of 104

Data Sheet

AD9558

Table 117. EEPROM Storage Sequence for Output PLL Settings

Address

Bits

Bit Name

Description

0x0E1D

[7:0] APLL

The default value of this register is 0x08, which the controller interprets as a data instruction. Its

decimal value is 8, which tells the controller to transfer nine bytes of data (8 + 1), beginning at the

address that is specified by the next two bytes. The controller stores 0x08 in the EEPROM and

increments the EEPROM address pointer.

0x0E1E

0x0E1F

[7:0]

The default value of these two registers is 0x0400. Note that Register 0x0E1E and Register 0x0E1F

are the most significant and least significant bytes of the target address, respectively. Because the

previous register contains a data instruction, these two registers define a starting address (in this

case, 0x0400). The controller stores 0x0400 in the EEPROM and increments the EEPROM pointer by 2.

It then transfers nine bytes from the register map (beginning at Address 0x0400) to the EEPROM

and increments the EEPROM address pointer by 10 (nine data bytes and one checksum byte). The

nine bytes transferred correspond to APLL parameters in the register map.

Table 118. EEPROM Storage Sequence for Clock Distribution Settings

Address

Bits

Bit Name

Description

0x0E20

[7:0] Clock distribution The default value of this register is 0x15, which the controller interprets as a data instruction. Its

decimal value is 21, which tells the controller to transfer 22 bytes of data (21+1), beginning at the

address that is specified by the next two bytes. The controller stores 0x15 in the EEPROM and

increments the EEPROM address pointer.

0x0E21

0x0E22

[7:0]

The default value of these two registers is 0x0500. Note that Register 0x0E21 and Register 0x0E22

are the most significant and least significant bytes of the target address, respectively. Because the

previous register contains a data instruction, these two registers define a starting address (in this

case, 0x0500). The controller stores 0x0500 in the EEPROM and increments the EEPROM pointer by 2.

It then transfers 22 bytes from the register map (beginning at Address 0x0500) to the EEPROM and

increments the EEPROM address pointer by 23 (22 data bytes and one checksum byte). The

22 bytes transferred correspond to the clock distribution parameters in the register map.

[7:0]

0x0E23

[7:0] I/O update

The default value of this register is 0x80, which the controller interprets as an I/O update

instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address

pointer.

Table 119. EEPROM Storage Sequence for Reference Input Settings

Address

Bits

Bit Name

Description

0x0E24

[7:0] Reference inputs

The default value of this register is 0x03, which the controller interprets as a data instruction. Its

decimal value is 3, so this tells the controller to transfer four bytes of data (3 + 1), beginning at the

address that is specified by the next two bytes. The controller stores 0x03 in the EEPROM and

increments the EEPROM address pointer.

0x0E25

0x0E26

[7:0]

The default value of these two registers is 0x0600. Note that Register 0x0E25 and Register 0x0E26

are the most significant and least significant bytes of the target address, respectively. Because the

previous register contains a data instruction, these two registers define a starting address (in this

case, 0x0600). The controller stores 0x0600 in the EEPROM and increments the EEPROM pointer by 2.

It then transfers four bytes from the register map (beginning at Address 0x0600) to the EEPROM

and increments the EEPROM address pointer by 5 (four data bytes and one checksum byte). The

four bytes that are transferred correspond to the reference inputs parameters in the register map.

Table 120. EEPROM Storage Sequence for Frame Sync Settings

Address

Bit

Bit Name

Description

0x0E27

[7:0] Frame sync

The default value of this register is 0x01, which the controller interprets as a data instruction. Its

decimal value is 1, which tells the controller to transfer two bytes of data (1 + 1), beginning at the

address specified by the next two bytes. The controller stores 0x01 in the EEPROM and increments

the EEPROM address pointer.

0x0E28

0x0E29

[7:0]

The default value of these two registers is 0x0640. Note that Register 0x0E28 and Register 0x0E29

are the most significant and least significant bytes of the target address, respectively. Because the

previous register contains a data instruction, these two registers define a starting address (in this

case, 0x0640). The controller stores 0x0640 in the EEPROM and increments the EEPROM pointer by 2.

It then transfers two bytes from the register map (beginning at Address 0x0640) to the EEPROM

and increments the EEPROM address pointer by 3 (two data bytes and one checksum byte). The

two bytes transferred correspond to the reference inputs parameters in the register map.

Rev. A | Page 99 of 104

AD9558

Data Sheet

Table 121. EEPROM Storage Sequence for REFA Profile Settings

Address

Bits

Bit Name

Description

0x0E2A

[7:0] REFA Profile The default value of this register is 0x26, which the controller interprets as a data instruction. Its decimal

value is 38, so this tells the controller to transfer 39 bytes of data (38 + 1), beginning at the address that

is specified by the next two bytes. The controller stores 0x26 in the EEPROM and increments the EEPROM

address pointer.

0x0E2B

0x0E2C

[7:0]

The default value of these two registers is 0x0700. Note that Register 0x0E2B and Register 0x0E2C are

the most significant and least significant bytes of the target address, respectively. Because the previous

register contains a data instruction, these two registers define a starting address (in this case, 0x0700).

The controller stores 0x0700 in the EEPROM and increments the EEPROM pointer by 2. It then transfers

39 bytes from the register map (beginning at Address 0x0700) to the EEPROM and increments the

EEPROM address pointer by 40 (39 data bytes and one checksum byte). The 39 bytes transferred

correspond to the REFA profile parameters in the register map.

[7:0]

Table 122. EEPROM Storage Sequence for REFB Profile Settings

Address

Bits

Bit Name

Description

0x0E2D

[7:0] REFB profile The default value of this register is 0x26, which the controller interprets as a data instruction. Its decimal

value is 38, so this tells the controller to transfer 39 bytes of data (38 + 1), beginning at the address that is

specified by the next two bytes. The controller stores 0x26 in the EEPROM and increments the EEPROM

address pointer.

0x0E2E

0x0E2F

[7:0]

The default value of these two registers is 0x0740. Note that Register 0x0E2E and Register 0x0E2F are the

most significant and least significant bytes of the target address, respectively. Because the previous register

contains a data instruction, these two registers define a starting address (in this case, 0x0740). The controller

stores 0x0740 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 39 bytes from the

register map (beginning at Address 0x0740) to the EEPROM and increments the EEPROM address pointer

by 40 (39 data bytes and one checksum byte). The 39 bytes transferred correspond to the REFB profile

parameters in the register map.

[7:0]

Table 123. EEPROM Storage Sequence for REFC Profile Settings

Address

Bits

Bit Name

Description

0x0E30

[7:0] REFC profile The default value of this register is 0x26, which the controller interprets as a data instruction. Its decimal

value is 38, so this tells the controller to transfer 39 bytes of data (38 + 1), beginning at the address that is

specified by the next two bytes. The controller stores 0x26 in the EEPROM and increments the EEPROM

address pointer.

0x0E31

0x0E32

[7:0]

The default value of these two registers is 0x0780. Note that Register 0x0E31 and Register 0x0E32 are

the most significant and least significant bytes of the target address, respectively. Because the previous

register contains a data instruction, these two registers define a starting address (in this case, 0x0780).

The controller stores 0x0780 in the EEPROM and increments the EEPROM pointer by 2. It then transfers

39 bytes from the register map (beginning at Address 0x0780) to the EEPROM and increments the

EEPROM address pointer by 40 (39 data bytes and one checksum byte). The 39 bytes transferred

correspond to the REFC profile parameters in the register map.

[7:0]

Table 124. EEPROM Storage Sequence for REFD Profile Settings

Address

Bits

Bit Name

Description

0x0E33

[7:0] REFD profile The default value of this register is 0x26, which the controller interprets as a data instruction. Its decimal

value is 38, so this tells the controller to transfer 39 bytes of data (38 + 1), beginning at the address that is

specified by the next two bytes. The controller stores 0x26 in the EEPROM and increments the EEPROM

address pointer.

0x0E34

0x0E35

[7:0]

The default value of these two registers is 0x07C0. Note that Register 0x0E34 and Register 0x0E35 are

the most significant and least significant bytes of the target address, respectively. Because the previous

register contains a data instruction, these two registers define a starting address (in this case, 0x07C0).

The controller stores 0x07C0 in the EEPROM and increments the EEPROM pointer by 2. It then transfers

39 bytes from the register map (beginning at Address 0x07C0) to the EEPROM and increments the EEPROM

address pointer by 40 (39 data bytes and one checksum byte). The 39 bytes transferred correspond to

the REFD profile parameters in the register map.

[7:0]

Rev. A | Page 100 of 104

Data Sheet

AD9558

Table 125. EEPROM Storage Sequence for Operational Control Settings

Address

Bits Bit Name

Description

0x0E37

[7:0] Operational controls The default value of this register is 0x0D, which the controller interprets as a data instruction.

Its decimal value is 13, so this tells the controller to transfer 14 bytes of data (13 + 1), beginning

at the address specified by the next two bytes. The controller stores 0x0D in the EEPROM and

increments the EEPROM address pointer.

0x0E38

0x0E39

[7:0]

The default value of these two registers is 0x0A00. Note that Register 0x0E38 and Register 0x0E39

are the most significant and least significant bytes of the target address, respectively. Because

the previous register contains a data instruction, these two registers define a starting address

(in this case, 0x0A00). The controller stores 0x0A00 in the EEPROM and increments the EEPROM

pointer by 2. It then transfers 14 bytes from the register map (beginning at Address 0x0A00) to

the EEPROM and increments the EEPROM address pointer by 15 (14 data bytes and one checksum

byte). The 14 bytes transferred correspond to the operational controls parameters in the register map.

[7:0]

Table 126. EEPROM Storage Sequence for APLL Calibration

Address

Bits Bit Name

Description

0x0E3A

[7:0] Calibrate APLL

The default value of this register is 0xA0, which the controller interprets as a calibrate instruction. The

controller stores 0xA0 in the EEPROM and increments the EEPROM address pointer.

0x0E3B

[7:0] I/O update

The default value of this register is 0x80, which the controller interprets as an I/O update instruction.

The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.

Table 127. EEPROM Storage Sequence for End of Data

Address

Bits Bit Name

Description

0x0E3C

[7:0] End of data

The default value of this register is 0xFF, which the controller interprets as an end instruction. The

controller stores this instruction in the EEPROM, resets the EEPROM address pointer, and enters

an idle state.

Note that if this is a pause rather than an end instruction, the controller actions are the same

except that the controller increments the EEPROM address pointer rather than resetting it.

Table 128. Available for Additional EEPROM Instructions

Address

Bits Bit Name

Description

0x0E3D

[7:0] Unused

This area is available for additional EEPROM instructions.

to 0xE45

Rev. A | Page 101 of 104

AD9558

Data Sheet

Table 129. Multifunction Pin Output Functions (D7 = 1)

Register Value

Output Function

Equivalent Status Register

None

0x80

Static Logic 0

0x81

Static Logic 1

None

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

System clock divided by 32

Watchdog timer output

EEPROM upload in progress

EEPROM download in progress

EEPROM fault detected

SYSCLK PLL lock detected

SYSCLK PLL stable

Output PLL locked

APLL calibration in process

APLL input reference present

All PLLs locked

None

Register 0x0D00, Bit 0

Register 0x0D00, Bit 1

Register 0x0D00, Bit 2

Register 0x0D01, Bit 0

Register 0x0D01, Bit 1

Register 0x0D01, Bit 2

Register 0x0D01, Bit 3

Register 0x0D01, Bit 4

Register 0x0D01, Bit 5

0x8A

0x8B

0x8C

(DPLL phase lock) and (APLL lock) and (sys PLL lock)

(DPLL phase lock) and (APLL lock)

Reserved

0x8D

0x8E

Register 0x0D01, Bit 6

0x8F

Reserved

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98

0x99

0x9A to 0x9F

0xA0

0xA1

DPLL free run

DPLL active

DPLL in holdover

Register 0x0D08, Bit 0

Register 0x0D08, Bit 1

Register 0x0D08, Bit 2

Register 0x0D08, Bit 3

Register 0x0D08, Bit 4

Register 0x0D08, Bit 5

Register 0x0D08, Bit 6

Register 0x0D09, Bit 5

Register 0x0D09, Bit 4

Register 0x0D05, Bit 4

DPLL in reference switchover

DPLL phase locked

DPLL frequency locked

DPLL phase slew limited

DPLL frequency clamped

Tuning word history available

Tuning word history updated

Reserved

Reference A fault

Reference B fault

Reference C fault

Reference D fault

Register 0x0D0B, Bit 2

Register 0x0D0B, Bit 6

Register 0x0D0C, Bit 2

Register 0x0D0C, Bit 6

0xA2

0xA3

0xA4 to Ax2F

0xB0

0xB1

0xB2

0xB3

Reserved

Reference A valid

Reference B valid

Reference C valid

Register 0x0D0B, Bit 3

Register 0x0D0B, Bit 7

Register 0x0D0C, Bit 3

Register 0x0D0C, Bit 7

Reference D valid

0xB4 to 0xBF

0xC0

0xC1

0xC2

0xC3

0xC4 to 0xCF

0xD0

0xD1

Reserved

Reference A active

Reference B active

Reference C active

Reference D active

Reserved

Clock distribution sync pulse

Soft pin configuration in progress

Reserved

Register 0x0D09, Bits[1:0]

Register 0x0D03, Bit 3

Register 0x0D03, Bit 4

0xD2 to 0FF

Rev. A | Page 102 of 104

Data Sheet

AD9558

Table 130. Multifunction Pin Input Functions (D7 = 0)

Register Value

Input Function

Equivalent Control Register

0x00

0x01

Reserved, high-Z input

I/O update

Register 0x0005, Bit 0

Register 0x0A00, Bit 0

Register 0x0A03, Bit 0

Register 0x0A03, Bit 1

Register 0x0A03, Bit 2

0x02

0x03

0x04

0x05

0x06 to 0x0E

0x10

0x11

0x12

0x13

0x14

0x15 to 0x1F

0x20

0x21

0x22

0x23

0x24 to 0x2F

0x30

0x31

0x32

0x33

0x34 to 0x3F

0x40

0x41

0x42

0x43

0x44

0x45

Full power-down

Clear watchdog

Clear all IRQs

Tuning word history reset

Reserved

User holdover

User free run

Register 0x0A01, Bit 6

Register 0x0A01, Bit 5

Register 0x0A0A, Bit 2

Register 0x0A0A, Bit 0

Register 0x0A0A, Bit 1

Reset incremental phase offset

Increment incremental phase offset

Decrement incremental phase offset

Reserved

Override Reference Monitor A

Override Reference Monitor B

Override Reference Monitor C

Override Reference Monitor D

Reserved

Force Validation Timeout A

Force Validation Timeout B

Force Validation Timeout C

Force Validation Timeout D

Reserved

Enable OUT0

Enable OUT1

Enable OUT2

Enable OUT3

Enable OUT4

Enable OUT5

Register 0x0A0C, Bit 0

Register 0x0A0C, Bit 1

Register 0x0A0C, Bit 2

Register 0x0A0C, Bit 3

Register 0x0A0B, Bit 0

Register 0x0A0B, Bit 1

Register 0x0A0B, Bit 2

Register 0x0A0B, Bit 3

Register 0x0501, Bit 0

Register 0x0505, Bit 0

Register 0x0506, Bit 0

Register 0x050A, Bit 0

Register 0x050B, Bit 0

Register 0x050F, Bit 0

0x46

0x47

0x48 to 0x7F

Enable OUT0, OUT1, OUT2, OUT3, OUT4, OUT5

Soft sync clock distribution outputs

Reserved

Register 0x0501/0x0505/0x0506/0x050A/0x050B/0x050F, Bit 0

Register 0x0A02, Bit 1

Rev. A | Page 103 of 104

AD9558

Data Sheet

OUTLINE DIMENSIONS

0.60 MAX

9.00

BSC SQ

0.60

MAX

PIN 1

INDICATOR

64

49

1

48

PIN 1

INDICATOR

0.50

BSC

5.25

5.10 SQ

4.95

8.75

BSC SQ

TOP VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.50

0.40

0.30

33

32

16

17

0.25 MIN

7.50

REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

0.30

0.23

0.18

SEATING

PLANE

0.20 REF

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 58. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-5)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

AD9558BCPZ

AD9558BCPZ-REEL7

AD9558/PCBZ

−40°C to +85°C

64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board

CP-64-5

¹Z = RoHS Compliant Part.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D09758-0-4/12(A)

Rev. A | Page 104 of 104


型号：	AD9558BCPZ
厂家：	ADI
描述：	Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync
文件：	总104页 (文件大小：1444K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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