AD9577-EVALZ_技术文档

Clock Generator with Dual PLLs,

Spread Spectrum, and Margining

AD9577

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAM

REFSEL

Fully integrated dual PLL/VCO cores

1 integer-N and 1 fractional-N PLL

XT1

OSC

XT2

XTAL

CMOS

Continuous frequency coverage from 11.2 MHz to 200 MHz

Most frequencies from 200 MHz to 637.5 MHz available

PLL1 phase jitter (12 kHz to 20 MHz): 460 fs rms typical

PLL2 phase jitter (12 kHz to 20 MHz)

REFOUT

REFCLK

DIVIDE

1 OR 2

LDO

PLL1

Integer-N mode: 470 fs rms typical

Fractional-N mode: 660 fs rms typical

VCO

LVPECL/LVDS

OR 2 × CMOS

2.15GHz

TO

Input crystal or reference clock frequency

Optional reference frequency divide-by-2

I²C programmable output frequencies

Up to 4 LVDS/LVPECL or up to 8 LVCMOS output clocks

1 CMOS buffered reference clock output

Spread spectrum: downspread [0, −0.5]%

2 pin-controlled frequency maps: margining

Integrated loop filters

2.55GHz

LVPECL/LVDS

OR 2 × CMOS

FEEDBACK

DIVIDER

LDO

PLL2

VCO

2.15GHz

TO

LVPECL/LVDS

OR 2 × CMOS

2.55GHz

Space saving, 6 mm × 6 mm, 40-lead LFCSP package

1.02 W power dissipation (LVDS operation)

1.235 W power dissipation (LVPECL operation)

3.3 V operation

LVPECL/LVDS

OR 2 × CMOS

FEEDBACK

DIVIDER

SCL

SDA

2

I C

CONTROL

MARGIN

APPLICATIONS

AD9577

SSCG

SPREAD SPECTRUM,

SDM

MAX_BW

Low jitter, low phase noise multioutput clock generator for

data communications applications including Ethernet,

Fibre Channel, SONET, SDH, PCI-e, SATA, PTN, OTN,

ADC/DAC, and digital video

Figure 1.

feedback divider, and two independently programmable output

dividers. By connecting an external crystal or applying a reference

clock to the REFCLK pin, frequencies of up to 637.5 MHz can

be synchronized to the input reference. Each output divider and

feedback divider ratio is I²C programmed for the required

output rates.

Spread spectrum clocking

GENERAL DESCRIPTION

The AD9577 provides a multioutput clock generator function,

along with two on-chip phase-locked loop cores, PLL1 and PLL2,

optimized for network clocking applications. The PLL designs

are based on the Analog Devices, Inc., proven portfolio of high

performance, low jitter frequency synthesizers to maximize

network performance. The PLLs have I²C programmable output

frequencies and formats. The fractional-N PLL can support

spread spectrum clocking for reduced EMI radiated peak power.

Both PLLs can support frequency margining. Other applications

with demanding phase noise and jitter requirements can benefit

from this part.

A second fractional-N PLL (PLL2) with a programmable modulus

allows VCO frequencies that are fractional multiples of the

reference frequency to be synthesized. Each output divider

and feedback divider ratio can be programmed for the required

output rates, up to 637.5 MHz. This fractional-N PLL can also

operate in integer-N mode for the lowest jitter.

Up to four differential output clock signals can be configured

as either LVPECL or LVDS signaling formats. Alternatively,

the outputs can be configured for up to eight CMOS outputs.

Combinations of these formats are supported. No external loop

filter components are required, thus conserving valuable design

time and board space. The AD9577 is available in a 40-lead, 6 mm ×

6 mm LFCSP package and can operate from a single 3.3 V supply.

The operating temperature range is −40°C to +85°C.

The first integer-N PLL section (PLL1) consists of a low noise phase

frequency detector (PFD), a precision charge pump (CP), a low

phase noise voltage controlled oscillator (VCO), a programmable

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9577

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Example Application.................................................................. 28

Functional Description.................................................................. 29

Reference Input and Reference Dividers................................. 29

Output Channel Dividers.......................................................... 30

Outputs ........................................................................................ 30

Reference Output Buffer ........................................................... 31

PLL1 Integer-N PLL................................................................... 31

PLL1 Phase Frequency Detector (PFD) and Charge Pump . 32

PLL1 VCO................................................................................... 32

PLL1 Feedback Divider ............................................................. 32

Setting the Output Frequency of PLL1.................................... 32

PLL2 Integer/Fractional-N PLL ............................................... 32

PLL2 Phase Frequency Detector (PFD) and Charge Pump . 33

PLL2 Loop Bandwidth............................................................... 33

PLL2 VCO................................................................................... 33

PLL2 Feedback Divider ............................................................. 33

PLL2 Σ-Δ Modulator ................................................................. 33

Spur Mechanisms ....................................................................... 33

Optimizing PLL Performance .................................................. 34

Setting the Output Frequency of PLL2.................................... 34

Margining.................................................................................... 35

Spread Spectrum Clock Generation (SSCG).......................... 35

I²C Interface Timing and Internal Register Description........... 38

Default Frequency Map and Output Formats ........................ 40

I²C Interface Operation ............................................................. 40

Typical Application Circuits ..................................................... 42

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

PLL1 Characteristics .................................................................... 3

PLL1 Clock Output Jitter............................................................. 5

PLL2 Fractional-N Mode Characteristics ................................. 6

PLL2 Integer-N Mode Characteristics....................................... 7

PLL2 Clock Output Jitter............................................................. 9

CMOS Reference Clock Output Jitter...................................... 11

Timing Characteristics .............................................................. 12

Clock Outputs............................................................................. 13

Power............................................................................................ 14

Crystal Oscillator........................................................................ 15

Reference Input........................................................................... 15

Control Pins ................................................................................ 15

Absolute Maximum Ratings.......................................................... 16

Thermal Characteristics ............................................................ 16

ESD Caution................................................................................ 16

Pin Configuration and Function Descriptions........................... 17

Typical Performance Characteristics ........................................... 19

REFOUT and PLL1 Phase Noise Performance ...................... 19

PLL2 Phase Noise Performance................................................ 20

Output Jitter ................................................................................ 21

Typical Output Signal ................................................................ 22

Typical Spread Spectrum Performance Characteristics........ 24

Terminology .................................................................................... 25

Detailed Block Diagram ................................................................ 27

Power and Grounding Considerations and Power Supply

Rejection...................................................................................... 43

Outline Dimensions....................................................................... 44

Ordering Guide .......................................................................... 44

REVISION HISTORY

10/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

Data Sheet

AD9577

SPECIFICATIONS

Typical (typ) is given for V_S= 3.3 V, T_A= 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full

V_S(3.0 V to 3.6 V) and T_A(−40°C to +85°C) variation. AC coupling capacitors of 0.1 μF used where appropriate. A Fox Electronics

FX532A 25 MHz crystal is used throughout, unless otherwise stated.

PLL1 CHARACTERISTICS

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments¹

NOISE CHARACTERISTICS

Phase Noise (106.25 MHz LVPECL Output)

Na = 102, Vx = 4, Dx = 6, f_PFD= 25 MHz

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

−121

−127

−128

−150

−156

−158

dBc/Hz

Phase Noise (156.25 MHz LVPECL Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (625 MHz LVPECL Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (106.25 MHz LVDS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (156.25 MHz LVDS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (625 MHz LVDS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

Na = 100, Vx = 4, Dx = 4, f_PFD= 25 MHz

Na = 100, Vx = 2, Dx = 2, f_PFD= 25 MHz

Na = 102, Vx = 4, Dx = 6, f_PFD= 25 MHz

Na = 100, Vx = 4, Dx = 4, f_PFD= 25 MHz

Na = 100, Vx = 2, Dx = 2, f_PFD= 25 MHz

−117

−124

−147

−156

dBc/Hz

−105

−112

−135

−150

dBc/Hz

−119

−127

−128

−148

−156

dBc/Hz

−116

−124

−145

−155

dBc/Hz

−104

−111

−112

−134

−149

dBc/Hz

At 10 MHz

At 30 MHz

Rev. 0 | Page 3 of 44

AD9577

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments¹

Phase Noise (106.25 MHz CMOS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (156.25 MHz CMOS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (155.52 MHz LVPECL Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (622.08 MHz LVPECL Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (155.52 MHz LVDS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (622.08 MHz LVDS Output)

At 1 kHz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

Phase Noise (155.52 MHz CMOS Output)

Na = 102, Vx = 4, Dx = 6, f_PFD= 25 MHz

Na = 100, Vx = 4, Dx = 4, f_PFD= 25 MHz

Na = 112, Vx = 2, Dx = 7, f_PFD= 19.44 MHz

Na = 128, Vx = 2, Dx = 2, f_PFD= 19.44 MHz

Na = 112, Vx = 2, Dx = 7, f_PFD= 19.44 MHz

Na = 128, Vx = 2, Dx = 2, f_PFD= 19.44 MHz

Na = 112, Vx = 2, Dx = 7, f_PFD= 19.44 MHz

−118

−127

−149

−156

−157

dBc/Hz

−115

−124

−146

−155

dBc/Hz

−117

−122

−123

−148

−156

dBc/Hz

−105

−110

−136

−150

dBc/Hz

−117

−122

−123

−146

−155

dBc/Hz

−105

−110

−134

−149

−150

dBc/Hz

At 1 kHz

−117

−122

−123

−147

−155

dBc/Hz

At 10 kHz

At 100 kHz

At 1 MHz

At 10 MHz

At 30 MHz

¹x indicates either 0 or 1 for any given test condition.

Rev. 0 | Page 4 of 44

Data Sheet

AD9577

PLL1 CLOCK OUTPUT JITTER

Table 2.

Parameter¹

Min Typ Max Unit

Test Conditions/Comments²

LVPECL INTEGRATED RANDOM PHASE JITTER

RMS Jitter (625 MHz Output)

25 MHz crystal used

460 750

430 650

460 750

fs rms 12 kHz to 20 MHz, Na = 100, Vx = 2, Dx = 2

fs rms 50 kHz to 80 MHz, Na = 100, Vx = 2, Dx = 2

fs rms 12 kHz to 20 MHz, Na = 100, Vx = 4, Dx = 4

fs rms 12 kHz to 20 MHz, Na = 102, Vx = 4, Dx = 6

25 MHz crystal used

fs rms 12 kHz to 20 MHz, Na = 100, Vx = 2, Dx = 2

fs rms 50 kHz to 80 MHz, Na = 100, Vx = 2, Dx = 2

fs rms 12 kHz to 20 MHz, Na = 100, Vx = 4, Dx = 4

fs rms 12 kHz to 20 MHz, Na = 102, Vx = 4, Dx = 6

25 MHz crystal used, 50 Ω load

RMS Jitter (156.25 MHz Output)

RMS Jitter (106.25 MHz Output)

LVDS INTEGRATED RANDOM PHASE JITTER

RMS Jitter (625 MHz Output)

470 820

450 790

470 790

RMS Jitter (156.25 MHz Output)

RMS Jitter (106.25 MHz Output)

CMOS INTEGRATED RANDOM PHASE JITTER

RMS Jitter (100 MHz Output)

RMS Jitter (33.3 MHz Output)

470 920

420 700

f_Srms

12 kHz to 20 MHz, Na = 96, Vx = 4, Dx = 6

12 kHz to 5 MHz, Na = 88, Vx = 6, Dx = 11

19.44 MHz crystal used

LVPECL INTEGRATED RANDOM PHASE JITTER

RMS Jitter (622.08 MHz Output)

500 680

460 590

480 680

fs rms 12 kHz to 20 MHz, Na = 128, Vx = 2, Dx = 2

fs rms 50 kHz to 80 MHz, Na = 128, Vx = 2, Dx = 2

fs rms 12 kHz to 20 MHz, Na = 112, Vx = 2, Dx = 7

19.44 MHz crystal used

fs rms 12 kHz to 20 MHz, Na = 128, Vx = 2, Dx = 2

fs rms 50 kHz to 80 MHz, Na = 128, Vx = 2, Dx = 2

fs rms 12 kHz to 20 MHz, Na = 112, Vx = 2, Dx = 7

19.44 MHz crystal used, 50 Ω load

fs rms 12 kHz to 20 MHz, Na = 112, Vx = 2, Dx = 7

fs rms 12 kHz to 5 MHz, Na = 112, Vx = 2, Dx = 28

25 MHz crystal used, Na = 96, Vx = 4, Dx = 6

ps p-p 10,000 cycles, average of 25 measurements

ps rms 10,000 cycles, average of 25 measurements

ps p-p 1,000 cycles, average of 25 measurements

ps rms 1,000 cycles, average of 25 measurements

25 MHz crystal used, Na = 96, Vx = 4, Dx = 6

RMS Jitter (155.52 MHz Output)

LVDS INTEGRATED RANDOM PHASE JITTER

RMS Jitter (622.08 MHz Output)

520 780

480 710

480 750

RMS Jitter (155.52 MHz Output)

CMOS INTEGRATED RANDOM PHASE JITTER

RMS Jitter (155.52 MHz Output)

RMS Jitter (38.88 MHz Output)

470 700

440 650

LVPECL PERIOD AND CYCLE-TO-CYCLE JITTER (100 MHz OUTPUT)

Output Peak-to-Peak Period Jitter

Output RMS Period Jitter

Output Peak-to-Peak, Cycle-to-Cycle Jitter

Output RMS Cycle-to-Cycle Jitter

13

2

19

3

LVDS PERIOD AND CYCLE-TO-CYCLE JITTER (100 MHz OUTPUT)

Output Peak-to-Peak Period Jitter

Output RMS Period Jitter

Output Peak-to-Peak, Cycle-to-Cycle Jitter

Output RMS Cycle-to-Cycle Jitter

17

2

25

4

ps p-p 10,000 cycles, average of 25 measurements

ps rms 10,000 cycles, average of 25 measurements

ps p-p 1,000 cycles, average of 25 measurements

ps rms 1,000 cycles, average of 25 measurements

CMOS PERIOD AND CYCLE-TO-CYCLE JITTER (100 MHz OUTPUT)

25 MHz crystal used, 50 Ω load, Na = 96,

Vx = 4, Dx = 6

Output Peak-to-Peak Period Jitter

Output RMS Period Jitter

Output Peak-to-Peak Cycle-to-Cycle Jitter

Output RMS Cycle-to-Cycle Jitter

25

3

36

6

ps p-p 10,000 cycles, average of 25 measurements

ps rms 10,000 cycles, average of 25 measurements

ps p-p 1,000 cycles, average of 25 measurements

ps rms 1,000 cycles, average of 25 measurements

¹All period and cycle-to-cycle jitter measurements are made with a Tektronix DPO70604 oscilloscope.

²x indicates either 0 or 1 for any given test condition.

Rev. 0 | Page 5 of 44

AD9577

Data Sheet

PLL2 FRACTIONAL-N MODE CHARACTERISTICS

Table 3. Bleed = 1

Parameter

Min Typ

Max Unit

Test Conditions/Comments¹

NOISE CHARACTERISTICS

25 MHz crystal used

Phase Noise (155.52 MHz LVPECL Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (622.08 MHz LVPECL Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (155.52 MHz LVDS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (622.08 MHz LVDS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (155.52 MHz CMOS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

Nb = 87, FRAC = 57, MOD = 625, Vx = 2, Dx = 7

Nb = 99, FRAC = 333, MOD = 625, Vx = 2, Dx = 2

Nb = 87, FRAC = 57, MOD = 625, Vx = 2, Dx = 7

Nb = 99, FRAC = 333, MOD = 625, Vx = 2, Dx = 2

Nb = 87, FRAC = 57, MOD = 625, Vx = 2, Dx = 7

−107

−115

−122

−146

−153

−152

dBc/Hz

−95

dBc/Hz

−103

−109

−133

−148

−150

−107

−114

−122

−145

−154

dBc/Hz

−95

dBc/Hz

−103

−109

−132

−147

−149

−107

−114

−122

−146

−154

dBc/Hz

@ 10 MHz

@ 30 MHz

SPREAD SPECTRUM

Modulation Range

Modulation Frequency

Peak Power Reduction

+0.1

31.25

10

−0.5

%

kHz

dB

Downspread, triangle modulation profile

Programmable

First harmonic of 100 MHz output, triangle modulation

profile, spectrum analyzer resolution bandwidth = 20 kHz

¹x indicates either 2 or 3 for any given test condition.

Rev. 0 | Page 6 of 44

Data Sheet

AD9577

PLL2 INTEGER-N MODE CHARACTERISTICS

Table 4. Bleed = 0

Parameter

Min Typ

Max

Unit

Test Conditions/Comments¹

NOISE CHARACTERISTICS

Phase Noise (106.25 MHz LVPECL Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (156.25 MHz LVPECL Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (625 MHz LVPECL Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (106.25 MHz LVDS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (156.25 MHz LVDS Output)

@ 1 kHz

@ 10 kHz

Nb = 102, Vx = 4, Dx = 6, f_PFD= 25 MHz

Nb = 100, Vx = 4, Dx = 4, f_PFD= 25 MHz

Nb = 100, Vx = 2, Dx = 2, f_PFD= 25 MHz

Nb = 102, Vx = 4, Dx = 6, f_PFD= 25 MHz

Nb = 100, Vx = 4, Dx = 4, f_PFD= 25 MHz

Nb = 100, Vx = 2, Dx = 2, f_PFD= 25 MHz

Nb = 102, Vx = 4, Dx = 6, f_PFD= 25 MHz

−116

−123

−127

−148

−156

−158

dBc/Hz

−113

−120

−124

−146

−156

dBc/Hz

−101

−108

−112

−134

−149

−150

dBc/Hz

−117

−123

−127

−147

−156

dBc/Hz

−113

−120

−124

−145

−155

dBc/Hz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (625 MHz LVDS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

−101

−108

−112

−133

−148

−149

dBc/Hz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (106.25 MHz CMOS Output)

@ 1 kHz

−117

−123

−127

−147

−156

−157

dBc/Hz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Rev. 0 | Page 7 of 44

AD9577

Data Sheet

Parameter

Min Typ

Max

Unit

Test Conditions/Comments¹

Phase Noise (156.25 MHz CMOS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (155.52 MHz LVPECL Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (622.08 MHz LVPECL Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (155.52 MHz LVDS Output)

@ 1 kHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (622.08 MHz LVDS Output)

@ 1 kHz

Nb = 100, Vx = 4, Dx = 4, f_PFD= 25 MHz

Nb = 112, Vx = 2, Dx = 7, f_PFD= 19.44 MHz

Nb = 128, Vx = 2, Dx = 2, f_PFD= 19.44 MHz

Nb = 112, Vx = 2, Dx = 7, f_PFD= 19.44 MHz

Nb = 128, Vx = 2, Dx = 2, f_PFD= 19.44 MHz

Nb = 112, Vx = 2, Dx = 7, f_PFD= 19.44 MHz

−113

−119

−123

−145

−154

−155

dBc/Hz

−112

−118

−126

−147

−155

−156

dBc/Hz

−100

−106

−112

−134

−149

−150

dBc/Hz

−113

−118

−126

−145

−154

−155

dBc/Hz

−101

−106

−112

−133

−148

−150

dBc/Hz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

Phase Noise (155.52 MHz CMOS Output)

@ 1 kHz

−113

−118

−126

−146

−155

dBc/Hz

@ 10 kHz

@ 100 kHz

@ 1 MHz

@ 10 MHz

@ 30 MHz

¹x indicates either 2 or 3 for any given test condition.

Rev. 0 | Page 8 of 44

Data Sheet

AD9577

PLL2 CLOCK OUTPUT JITTER

Table 5. Bleed = 0 for Integer-N Mode, Bleed = 1 for Fractional-N Mode

Parameter¹

Min Typ Max Unit

Test Conditions/Comments²

LVPECL INTEGRATED RANDOM PHASE JITTER

RMS Jitter (622.08 MHz Output)

25 MHz crystal used

660 1200 fs rms 12 kHz to 20 MHz, fractional-N operation,

Nb = 99, FRAC = 333, MOD = 625, Vx = 2,

Dx = 2

500 900

fs rms 50 kHz to 80 MHz, fractional-N operation,

Nb = 99, FRAC = 333, MOD = 625, Vx = 2,

Dx = 2

RMS Jitter (625 MHz Output)

470 800

380 650

fs rms 12 kHz to 20 MHz, integer-N operation,

Nb = 100, Vx = 2, Dx = 2

fs rms 50 kHz to 80 MHz, integer-N operation,

Nb = 100, Vx = 2, Dx = 2

RMS Jitter (155.52 MHz Output)

RMS Jitter (156.25 MHz Output)

630 1100 fs rms 12 kHz to 20 MHz, fractional-N operation,

Nb = 87, FRAC = 57, MOD = 625, Vx = 2,

Dx = 7

470 800

fs rms 12 kHz to 20 MHz, integer-N operation,

Nb = 100, Vx = 4, Dx = 4

LVDS INTEGRATED RANDOM PHASE JITTER

RMS Jitter (622.08 MHz Output)

25 MHz crystal used

660 1200 fs rms 12kHz to 20 MHz, fractional-N operation,

Nb = 99, FRAC = 333, MOD = 625, Vx = 2,

Dx = 2

510 900

fs rms 50 kHz to 80 MHz, fractional-N operation,

Nb = 99, FRAC = 333, MOD = 625, Vx = 2,

Dx = 2

RMS Jitter (625 MHz Output)

470 820

380 650

fs rms 12 kHz to 20 MHz, integer-N operation,

Nb = 100, Vx = 2, Dx = 2

fs rms 50 kHz to 80 MHz, integer-N operation,

Nb = 100, Vx = 2, Dx = 2

RMS Jitter (155.52 MHz Output)

RMS Jitter (156.25 MHz Output)

620 1100 fs rms 12 kHz to 20 MHz, fractional-N operation,

Nb = 87, FRAC = 57, MOD = 625, Vx = 2,

Dx = 7

480 800

fs rms 12 kHz to 20 MHz, integer-N operation,

Nb = 100, Vx = 4, Dx = 4

CMOS INTEGRATED RANDOM PHASE JITTER

RMS Jitter (155.52 MHz Output)

25 MHz crystal used, 50 Ω load

630 1100 fs rms 12 kHz to 20 MHz, fractional-N operation,

Nb = 87, FRAC = 57, MOD = 625, Vx = 2,

Dx = 7

RMS Jitter (100 MHz Output)

RMS Jitter (33.33 MHz Output)

490 800

450 700

fs rms 12 kHz to 20 MHz, integer-N operation,

Nb = 96, Vx = 4, Dx = 6

fs rms 12 kHz to 5 MHz, integer-N operation,

Nb = 88, Vx = 6, Dx = 11

LVPECL INTEGRATED RANDOM PHASE JITTER

RMS Jitter (622.08 MHz Output)

19.44 MHz crystal used

fs rms 12 kHz to 20 MHz, integer-N operation,

Nb = 128, Vx = 2, Dx = 2

fs rms 50 kHz to 80 MHz, integer-N operation,

Nb = 128, Vx = 2, Dx = 2

fs rms 12 kHz to 20 MHz, integer-N operation,

Nb = 112, Vx = 2, Dx = 7

510 800

380 650

470 800

RMS Jitter (155.52 MHz Output)

LVDS INTEGRATED RANDOM PHASE JITTER

RMS Jitter (622.08 MHz Output)

19.44 MHz crystal used

fs rms 12 kHz to 20 MHz, integer-N operation,

Nb = 128, Vx = 2, Dx = 2

fs rms 50 kHz to 80 MHz, integer-N operation,

Nb = 128, Vx = 2, Dx = 2

fs rms 12 kHz to 20 MHz, integer-N operation,

Nb = 112, Vx = 2, Dx = 7

530 900

390 700

480 750

RMS Jitter (155.52 MHz Output)

Rev. 0 | Page 9 of 44

AD9577

Data Sheet

Parameter¹

Min Typ Max Unit

Test Conditions/Comments²

19.44 MHz crystal used, 50 Ω load

CMOS INTEGRATED RANDOM PHASE JITTER

RMS Jitter (155.52 MHz Output)

470 700

430 650

fs rms 12 kHz to 20 MHz, integer-N operation,

Nb = 112, Vx = 2, Dx = 7

fs rms 12 kHz to 5 MHz, integer-N operation,

Nb = 112, Vx = 2, Dx = 28

RMS Jitter (38.88 MHz Output)

LVPECL PERIOD AND CYCLE-TO-CYCLE JITTER (100 MHz OUTPUT)

25 MHz crystal used, integer-N

operation, Nb = 96, Vx = 4, Dx = 6

Output Peak-to-Peak Period Jitter

Output RMS Period Jitter

Output Peak-to-Peak, Cycle-to-Cycle Jitter

Output RMS Cycle-to-Cycle Jitter

13

2

19

3

ps p-p 10,000 cycles, average of 25 measurements

ps rms 10,000 cycles, average of 25 measurements

ps p-p 1,000 cycles, average of 25 measurements

ps rms 1,000 cycles, average of 25 measurements

LVDS PERIOD AND CYCLE-TO-CYCLE JITTER (100 MHz OUTPUT)

25 MHz crystal used, integer-N

operation, Nb = 96, Vx = 4, Dx = 6

Output Peak-to-Peak Period Jitter

Output RMS Period Jitter

Output Peak-to-Peak, Cycle-to-Cycle Jitter

Output RMS Cycle-to-Cycle Jitter

17

2

26

4

ps p-p 10,000 cycles, average of 25 measurements

ps rms 10,000 cycles, average of 25 measurements

ps p-p 1,000 cycles, average of 25 measurements

ps rms 1,000 cycles, average of 25 measurements

CMOS PERIOD AND CYCLE-TO-CYCLE JITTER (100 MHz OUTPUT)

25 MHz crystal used, 50 Ω load, integer-N

operation, Nb = 96, Vx = 4, Dx = 6

Output Peak-to-Peak Period Jitter

Output RMS Period Jitter

Output Peak-to-Peak, Cycle-to-Cycle

Output RMS Cycle-to-Cycle Jitter

25

3

36

6

ps p-p 10,000 cycles, average of 25 measurements

ps rms 10,000 cycles, average of 25 measurements

ps p-p 1,000 cycles, average of 25 measurements

ps rms 1,000 cycles, average of 25 measurements

LVPECL PERIOD AND CYCLE-TO-CYCLE JITTER (100 MHz OUTPUT)

25 MHz crystal used, SSCG on, Nb = 100,

FRAC = 0, MOD = 1000, Vx = 5, Dx = 5,

CkDiv = 7, NumSteps = 59, FracStep = −8,

f_OUT= 100 MHz with −0.5% downspread

at 30.2 kHz

Output Peak-to-Peak Period Jitter

Output RMS Period Jitter

Output Peak-to-Peak, Cycle-to-Cycle Jitter

Output RMS Cycle-to-Cycle Jitter

60

15

20

3

ps p-p 10,000 cycles, average of 25 measurements

ps rms 10,000 cycles, average of 25 measurements

ps p-p 1,000 cycles, average of 25 measurements

ps rms 1,000 cycles, average of 25 measurements

LVDS PERIOD AND CYCLE-TO-CYCLE JITTER (100 MHz OUTPUT)

25 MHz crystal used, SSCG on, Nb = 100,

FRAC = 0, MOD = 1000, Vx = 5, Dx = 5,

CkDiv = 7, NumSteps = 59, FracStep = −8,

f_OUT= 100 MHz with −0.5% downspread

at 30.2 kHz

Output Peak-to-Peak Period Jitter

Output RMS Period Jitter

Output Peak-to-Peak, Cycle-to-Cycle Jitter

Output RMS Cycle-to-Cycle Jitter

63

15

25

4

ps p-p 10,000 cycles, average of 25 measurements

ps rms 10,000 cycles, average of 25 measurements

ps p-p 1,000 cycles, average of 25 measurements

ps rms 1,000 cycles, average of 25 measurements

CMOS PERIOD AND CYCLE-TO-CYCLE JITTER (100 MHz OUTPUT)

25 MHz crystal used, SSCG on, 50 Ω load,

Nb = 100, FRAC = 0, MOD = 1000, Vx = 5,

Dx = 5, CkDiv = 7, NumSteps = 59,

FracStep = −8, f_OUT= 100 MHz with

−0.5% downspread at 30.2 kHz

Output Peak-to-Peak Period Jitter

Output RMS Period Jitter

Output Peak-to-Peak, Cycle-to-Cycle Jitter

Output RMS Cycle-Cycle Jitter

70

15

36

6

ps p-p 10,000 cycles, average of 25 measurements

ps rms 10,000 cycles, average of 25 measurements

ps p-p 1,000 cycles, average of 25 measurements

ps rms 1,000 cycles, average of 25 measurements

Rev. 0 | Page 10 of 44

Data Sheet

AD9577

Parameter¹

Min Typ Max Unit

Test Conditions/Comments²

LVPECL PERIOD AND CYCLE-TO-CYCLE JITTER (100.12 MHz OUTPUT)

25 MHz crystal used, fractional-N

operation, Nb = 100, FRAC = 15,

MOD = 125, Vx = 5, Dx = 5

Output Peak-to-Peak Period Jitter

Output RMS Period Jitter

Output Peak-to-Peak, Cycle-to-Cycle Jitter

Output RMS Cycle-to-Cycle Jitter

13

2

20

3

ps p-p 10,000 cycles, average of 25 measurements

ps rms 10,000 cycles, average of 25 measurements

ps p-p 1,000 cycles, average of 25 measurements

ps rms 1,000 cycles, average of 25 measurements

LVDS PERIOD AND CYCLE-TO-CYCLE JITTER (100.12 MHz OUTPUT)

25 MHz crystal used, fractional-N

operation, Nb = 100, FRAC = 15,

MOD = 125, Vx = 5, Dx = 5

Output Peak-to-Peak Period Jitter

Output RMS Period Jitter

Output Peak-to-Peak, Cycle-to-Cycle Jitter

Output RMS Cycle-to-Cycle Jitter

17

2

26

4

ps p-p 10,000 cycles, average of 25 measurements

ps rms 10,000 cycles, average of 25 measurements

ps p-p 1,000 cycles, average of 25 measurements

ps rms 1,000 cycles, average of 25 measurements

CMOS PERIOD AND CYCLE-TO-CYCLE JITTER (100.12 MHz OUTPUT)

25 MHz crystal used, 50 Ω load,

fractional-N operation, Nb = 100,

FRAC = 15, MOD = 125, Vx = 5, Dx = 5

Output Peak-to-Peak Period Jitter

Output RMS Period Jitter

Output Peak-to-Peak, Cycle-to-Cycle Jitter

Output RMS Cycle-to-Cycle Jitter

25

3

36

6

ps p-p 10,000 cycles, average of 25 measurements

ps rms 10,000 cycles, average of 25 measurements

ps p-p 1,000 cycles, average of 25 measurements

ps rms 1,000 cycles, average of 25 measurements

¹All period and cycle-to-cycle jitter measurements are made with a Tektronix DPO70604 oscilloscope.

²x indicates either 2 or 3 for any given test condition.

CMOS REFERENCE CLOCK OUTPUT JITTER

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

JITTER INTEGRATION BANDWIDTH

12 kHz to 5 MHz

200 kHz to 5 MHz

Jitter measurement at 25 MHz is equipment limited

25 MHz

680

670

1000

950

fs rms

Rev. 0 | Page 11 of 44

AD9577

Data Sheet

TIMING CHARACTERISTICS

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL (see Figure 2)

Termination = 200 Ω to 0 V, ac-coupled to 50 Ω

oscilloscope; C_LOAD= 5 pF

Output Rise Time, t_RP

Output Fall Time, t_FP

Skew

170

225

230

20

300

310

ps

20% to 80%, measured differentially

80% to 20%, measured differentially

Between the outputs of the same PLL at the

same frequency. SyncCh01/SyncCh23 set to 1

LVDS (see Figure 3)

Output Rise Time, t_RL

Output Fall Time, t_FL

Skew

Termination = 100 Ω differential; C_LOAD= 5 pF

20% to 80%, measured differentially

80% to 20%, measured differentially

Between the outputs of the same PLL at the

same frequency; SyncCh01/SyncCh23 set to 1

180

250

260

20

340

330

ps

CMOS (see Figure 4)

Output Rise Time, t_RC

250

350

680

700

20

950

ps

Termination is high impedance active probe,

total C_LOAD= 5 pF, R_LOAD= 20 kΩ, 20% to 80%

Termination is high impedance active probe,

total C_LOAD= 5 pF, R_LOAD= 20 kΩ, 80% to 20%

Between the outputs of the same PLL at the

same frequency; SyncCh01/SyncCh23 set to 1

Output Fall Time, t_FC

Skew

1000 ps

ps

Timing Diagrams

SINGLE-ENDED

DIFFERENTIAL

80%

V_OD

50%

20%

CMOS

LVPECL

t_RC

t_FC

t_RP

t_FP

Figure 2. LVPECL Timing, Differential

Figure 4. CMOS Timing, Single-Ended, 5 pF Load

DIFFERENTIAL

80%

V_OD

50%

20%

LVDS

t_RL

t_FL

Figure 3. LVDS Timing, Differential

Rev. 0 | Page 12 of 44

Data Sheet

AD9577

CLOCK OUTPUTS

AC coupling capacitors of 0.1 μF used where appropriate.

Table 8.

Parameter

Min

Typ

Max

Unit Test Conditions/Comments

LVPECL CLOCK OUTPUTS

Output Frequency

637.5

MHz Load is 200 Ω to GND at output pins, then

ac-coupled to 50 Ω terminated measurement

equipment.

Output Voltage Swing, V_OD

610

45

740

950

55

mV

Load is 200 Ω to GND at output pins, then

ac-coupled to 50 Ω terminated measurement

equipment. For differential amplitude, see

Figure 2.

Load is 200 Ω to GND at output pins, then

ac-coupled to 50 Ω terminated measurement

equipment.

Load is 127 Ω/83 Ω potential divider across

supply dc-coupled into 1 MΩ terminated

measurement equipment, outputs static.

Load is 127 Ω/83 Ω potential divider across

supply dc-coupled into 1 MΩ terminated

measurement equipment, outputs static.

Duty Cycle

%

V

Output High Voltage, V_OH

Output Low Voltage, V_OL

V_S− 1.24 V_S− 0.94 V_S− 0.83

V_S− 2.07 V_S− 1.75 V_S− 1.62

V

LVDS CLOCK OUTPUTS

Output Frequency

637.5

MHz Load is ac-coupled to measurement

equipment that provides 100 Ω differential

input termination.

Differential Output Voltage, V_OD

250

350

475

mV

Load is ac-coupled to measurement

equipment that provides 100 Ω differential

input termination. For differential amplitude,

see Figure 3.

Delta V_OD

25

mV

%

Load is ac-coupled to measurement

equipment that provides 100 Ω differential

input termination.

Load is ac-coupled to measurement

equipment that provides 100 Ω differential

input termination.

Duty Cycle

45

55

Output Offset Voltage, V_OS

Delta V_OS

1.125

1.25

13

1.375

25

V

Load is dc-coupled to a 100 Ω differential

resistor into 1 MΩ terminated measurement

equipment, outputs static.

Load is dc-coupled to a 100 Ω differential

resistor into 1 MΩ terminated measurement

equipment, outputs static.

Load is dc-coupled to a 100 Ω differential

resistor into 1 MΩ terminated measurement

equipment, output shorted to GND.

mV

mA

Short-Circuit Current, I_SA, I_SB

24

CMOS CLOCK OUTPUTS

Output Frequency

Output High Voltage, V_OH

Output Low Voltage, V_OL

Duty Cycle

200

MHz

V

V_S− 0.15

45

Sourcing 1.0 mA current, outputs static.

Sinking 1.0 mA current, outputs static.

Termination is high impedance active probe;

total C_LOAD= 5 pF, R_LOAD= 20 kΩ.

0.1

55

%

Rev. 0 | Page 13 of 44

AD9577

Data Sheet

POWER

Table 9.

Parameter

Min Typ

3.0 3.3

Max

Unit Test Conditions/Comments

POWER SUPPLY

LVPECL POWER DISSIPATION

3.6

V

1235 1490 mW

Typical part configuration, both PLLs enabled for integer-N operation,

f_OUT0= 156.25 MHz, f_OUT1= 125 MHz, f_OUT2= 100 MHz, f_OUT3= 33.33 MHz,

Na = 100, V0 = 4, D0 = 4, V1 = 4, D1 = 5, Nb = 96, V2 = 4, D2 = 6, V3 = 4,

D3 = 18, 25 MHz crystal used, load is 200 Ω to GND at output pins, then

ac-coupled to 50 Ω terminated measurement equipment

1270 1530 mW

Worst-case part configuration, PLL2 in fractional-N mode, with SSCG

enabled, f_OUT0= 379.16 MHz, f_OUT1= 379.16 MHz, f_OUT2= 359.33 MHz,

f

_OUT3= 359.33 MHz, Na = 91, V0 = 3, D0 = 2, V1 = 3, D1 = 2, Nb = 86,

V2 = 3, D2 = 2, V3 = 3, D3 = 2, FRAC = 300, MOD = 1250, CkDiv = 5,

NumSteps = 77, FracStep = −7, −0.5% downspread at 32 kHz,

25 MHz crystal used, load is 200 Ω to GND at output pins, then

ac-coupled to 50 Ω terminated measurement equipment

LVDS POWER DISSIPATION

1020 1200 mW

1085 1290 mW

Typical part configuration, both PLLs enabled for integer-N operation,

f

_OUT0= 156.25 MHz, f_OUT1= 125 MHz, f_OUT2= 100 MHz, f_OUT3= 33.33 MHz,

Na = 100, V0 = 4, D0 = 4, V1 = 4, D1 = 5, Nb = 96, V2 = 4, D2 = 6, V3 = 4,

D3 = 18, 25 MHz crystal used, load ac-coupled to measurement

equipment that provides 100 Ω differential input termination

Worst-case part configuration, PLL2 in fractional-N mode, with SSCG

enabled, f_OUT0= 379.16 MHz, f_OUT1= 379.16 MHz, f_OUT2= 359.33 MHz,

f_OUT3= 359.33 MHz, Na = 91, V0 = 3, D0 = 2, V1 = 3, D1 = 2, Nb = 86,

V2 = 3, D2 = 2, V3 = 3, D3 = 2, FRAC = 300, MOD = 1250, CkDiv = 5,

NumSteps = 77, FracStep = −7, −0.5% downspread at 32 kHz,

25 MHz crystal used, load ac-coupled to measurement equipment

that provides 100 Ω differential input termination

CMOS POWER DISSIPATION

1065 1380 mW

1190 1510 mW

Typical part configuration, both PLLs enabled for integer-N operation,

f_OUT0= 156.25 MHz, f_OUT1= 125 MHz, f_OUT2= 100 MHz, f_OUT3= 33.33 MHz,

Na = 100, V0 = 4, D0 = 4, V1 = 4, D1 = 5, Nb = 96, V2 = 4, D2 = 6, V3 = 4,

D3 = 18, 25 MHz crystal used, eight single-ended outputs active,

C_LOAD= 5 pF

Worst-case part configuration, PLL2 in fractional-N mode, with SSCG

enabled, f_OUT0= 189.58 MHz, f_OUT1= 189.58 MHz, f_OUT2= 179.66 MHz,

f_OUT3= 179.66 MHz, Na = 91, V0 = 3, D0 = 4, V1 = 3, D1 = 4, Nb = 86,

V2 = 3, D2 = 4, V3 = 3, D3 = 4, FRAC = 300, MOD = 1250, CkDiv = 5,

NumSteps = 77, FracStep = −7, −0.5% downspread at 32 kHz,

25 MHz crystal used, eight single-ended outputs active, C_LOAD= 5 pF

POWER CHANGES

Reduction in power due to turning off a channel of one VCO divider,

one output divider, and one output buffer; data for Channel 1, with

typical part configuration, both PLLs enabled for integer-N operation,

f_OUT0= 156.25 MHz, f_OUT1= 125 MHz, f_OUT2= 100 MHz, f_OUT3= 33.33 MHz,

Na = 100, V0 = 4, D0 = 4, V1 = 4, D1 = 5, Nb = 96, V2 = 4, D2 = 6, V3 = 4,

D3 = 18, 25 MHz crystal used

Power-Down 1 LVPECL Channel 160

205

155

170

mW

Load 200 Ω to GND at output pins, and ac-coupled to 50 Ω terminated

measurement equipment

Load ac-coupled to measurement equipment that provides 100 Ω

differential input termination

Power-Down 1 LVDS Channel

Power-Down 1 CMOS Channel

105

130

Eight single-ended outputs active, C_LOAD= 5 pF

Rev. 0 | Page 14 of 44

Data Sheet

AD9577

CRYSTAL OSCILLATOR

Table 10.

Parameter

CRYSTAL SPECIFICATION

Frequency

Min

Typ

Max

Unit

Test Conditions/Comments

Fundamental mode

Reference divider, R = 1, only

19.44

25

27

50

MHz

Ω

ESR

Load Capacitance

Phase Noise

Stability

14

−135

pF

dBc/Hz

ppm

1 kHz offset

−50

+50

REFERENCE INPUT

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLOCK INPUT (REFCLK)

Input Frequency

19.44

38.88

2.0

25

50

27

54

MHz

V

μA

pF

Reference divider, R = 1

Reference divider, R = 2

Input High Voltage

Input Low Voltage

Input Current

0.8

+1.0

−1.0

Input Capacitance

2

CONTROL PINS

Table 12.

Parameter

Min

Typ Max

Unit Test Conditions/Comments

INPUT CHARACTERISTICS

SSCG, MAX_BW, and MARGIN

SSCG, MAX_BW, and MARGIN have a 30 kΩ internal

pull-down resistor

Logic 1 Voltage

Logic 0 Voltage

Logic 1 Current

2.0

V

μA

0.8

240

40

Logic 0 Current

REFSEL

REFSEL has a 30 kΩ internal pull-up resistor

Logic 1 Voltage

2.0

V

Logic 0 Voltage

Logic 1 Current

Logic 0 Current

0.8

70

240

V

μA

I²C DC CHARACTERISTICS

Input Voltage High

Input Voltage Low

Input Current

Output Low Voltage

I²C TIMING CHARACTERISTICS

SCL Clock Frequency

SCL Pulse Width High

High, t_HIGH

LVCMOS; the SCL and SDA pins only, see Figure 48

0.7 Vcc

−10

V

μA

V

0.3 Vcc

+10

0.4

V_IN= 0.1 V_CCor V_IN= 0.9 V_CC

V_OLwith a load current of I_OL= 3.0 mA

LVCMOS; the SCL and SDA pins only, see Figure 48

400

kHz

600

1300

ns

Low, t_LOW

Start Condition

Hold Time, t_{HD; STA}

Setup Time, t_{SU; STA}

Data

600

ns

Setup Time, t_{SU; DAT}

Hold Time, t_{HD; DAT}

Stop Condition Setup Time, t_{SU; STO}

100

300

600

1300

ns

Bus Free Time Between a Stop and a Start, t_BUF

Rev. 0 | Page 15 of 44

AD9577

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 13.

THERMAL CHARACTERISTICS

Thermal impedance measurements were taken on a 4-layer

board in still air in accordance with EIA/JESD51-7.

Parameter

Rating

V_Sto GND

−0.3 V to +3.6 V

REFCLK to GND

LDO to GND

XT1, XT2 to GND

SSCG, MAX_BW, MARGIN, SCL, SDA,

REFSEL to GND

−0.3 V to V_S+ 0.3 V

−0.3V to V_S+ 0.3 V

−0.3 V to V_S+ 0.3 V

Table 14. Thermal Resistance

Package Type

40-Lead LFCSP

θ_JA

Unit

27.5

°C/W

REFOUT, OUTxP, OUTxN to GND

Junction Temperature¹

−0.3 V to V_S+ 0.3 V

150°C

ESD CAUTION

Storage Temperature

Lead Temperature (10 sec)

−65°C to+150°C

300°C

¹See the Thermal Characteristics section for θ_JA

.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 16 of 44

Data Sheet

AD9577

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

VSCA

VSI2C

REFOUT

VSREFOUT

VSX

REFCLK

XT2

XT1

REFSEL

1

2

3

4

5

6

7

8

9

30 VSOB1A

29 OUT1P

28 OUT1N

27 VSFA

26 SSCG

25 VSM

INDICATOR

AD9577

TOP VIEW

(Not to Scale)

24 VSFB

23 OUT3P

22 OUT3N

21 VSOB3B

VSCB 10

NOTES

1. THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION

AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO FUNCTION

PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND (GND). IT IS

RECOMMENDED THAT A MINIMUM OF NINE VIAS BE USED TO CONNECT THE

PADDLE TO THE PRINTED CIRCUIT BOARD (PCB) GROUND PLANE.

Figure 5. Pin Configuration

Table 15. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

VSCA

VSI2C

PLL1 Power Supply.

I²C Digital Power Supply.

3

4

5

6

7, 8

9

10

REFOUT

VSREFOUT

VSX

REFCLK

XT2, XT1

REFSEL

VSCB

CMOS Reference Output.

Reference Output Buffer Power Supply.

Crystal Oscillator and Input Reference Power Supply.

Reference Clock Input. Tie low when not in use.

External 19.44 MHz to 27 MHz Crystal. Leave unconnected when not in use.

Logic Input. Use this pin to select the reference source. Internal 30 kΩ pull-up resistor.

PLL2 Analog Power Supply.

11

12

13

14

TST1B

TST2B

LDO

Test Pin. Connect this pin to Pin 13 (LDO).

This pin is for bypassing the PLL2 LDO to ground with a 220 nF capacitor.

PLL2 VCO Power Supply.

VSVB

15, 16, 35, 36

GND

Ground.

17

18

19

20

21

22

23

24

25

26

27

28

29

OUT2N

OUT2P

VSOB2B

MARGIN

VSOB3B

OUT3N

OUT3P

VSFB

VSM

SSCG

VSFA

OUT1N

OUT1P

LVPECL/LVDS/CMOS Clock Output.

Output Port OUT2 Power Supply.

Logic 1 sets the margining frequency on the clock output pins. Internal 30 kΩ pull-down resistor.

Output Port OUT3 Power Supply.

LVPECL/LVDS/CMOS Clock Output.

PLL2 Analog Power Supply.

PLL2 Digital Power Supply.

Logic 1 enables spread spectrum operation of PLL2. Internal 30 kΩ pull-down resistor.

PLL1 Analog Power Supply.

LVPECL/LVDS/CMOS Clock Output.

Rev. 0 | Page 17 of 44

AD9577

Data Sheet

Pin No.

30

31

Mnemonic

VSOB1A

SDA

Description

Output Port OUT1 Power Supply.

Serial Data Line for I²C.

32

33

34

37

VSOB0A

OUT0N

OUT0P

SCL

Output Port OUT0 Power Supply.

LVPECL/LVDS/CMOS Clock Output.

Serial Clock for I²C.

38

VSVA

PLL1 VCO Power Supply.

39

TST2A

Test Pin. Connect this pin to the printed circuit board (PCB) ground plane.

40

MAX_BW

Logic 1 widens the loop bandwidth of the fractional-N PLL during spread spectrum. Internal 30 kΩ pull-

down resistor.

EPAD

The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For

the device to function properly, the paddle must be attached to ground (GND). It is recommended that

a minimum of nine vias be used to connect the paddle to the printed circuit board (PCB) ground plane.

Rev. 0 | Page 18 of 44

Data Sheet

AD9577

TYPICAL PERFORMANCE CHARACTERISTICS

REFOUT AND PLL1 PHASE NOISE PERFORMANCE

–100

–110

–120

–130

–140

–150

–160

–100

–110

–120

–130

–140

–150

–160

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 6. Phase Noise, REFOUT Output, 25 MHz (f_XTAL= 25 MHz)

Figure 9. Phase Noise, PLL1, OUT0 LVPECL, 100 MHz, Integer-N Mode

(f_XTAL= 25 MHz, Na = 100, V0 = 5, D0 = 5)

–100

–110

–120

–130

–140

–150

–160

–110

–120

–130

–140

–150

–160

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 7. Phase Noise, PLL1, OUT0 LVPECL, 106.25 MHz, Integer-N Mode

(f_XTAL= 25 MHz, Na = 102, V0 = 4, D0 = 6)

Figure 10. Phase Noise, PLL1, OUT0 LVPECL, 125 MHz, Integer-N Mode

(f_XTAL= 25 MHz, Na = 100, V0 = 4, D0 = 5)

–80

–90

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

–100

–110

–120

–130

–140

–150

–160

–170

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 8. Phase Noise, PLL1, OUT0 LVPECL, 156.25 MHz Integer-N Mode

(f_XTAL= 25 MHz, Na = 100, V0 = 4, D0 = 4)

Figure 11. Phase Noise, PLL1, OUT0 LVPECL, 625 MHz, Integer-N Mode

(f_XTAL= 25 MHz, Na = 100, V0 = 2, D0 = 2)

Rev. 0 | Page 19 of 44

AD9577

Data Sheet

PLL2 PHASE NOISE PERFORMANCE

–110

–120

–130

–140

–150

–160

–120

–130

–140

–150

–160

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 12. Phase Noise, PLL2, OUT2 LVPECL, 100 MHz, Integer-N Mode

(f_XTAL= 25 MHz, Nb = 100, V2 = 5, D2 = 5)

Figure 15. Phase Noise, PLL2, OUT2 LVPECL, 106.25 MHz, Integer-N Mode

(f_XTAL= 25 MHz, Nb = 102, V2 = 4, D2 = 6)

–100

–110

–120

–130

–140

–150

–160

–90

–100

–110

–120

–130

–140

–150

–160

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 13. Phase Noise, PLL2, OUT2 LVPECL, 156.25 MHz, Integer-N Mode

(f_XTAL= 25 MHz, Nb = 100, V2 = 4, D2 = 4)

Figure 16. Phase Noise, PLL2, OUT2 LVPECL, 625 MHz, Integer-N Mode

(f_XTAL= 25 MHz, Nb = 100, V2 = 2, D2 = 2)

–100

–110

–120

–130

–140

–150

–160

–90

–100

–110

–120

–130

–140

–150

–160

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 14. Phase Noise, PLL2, OUT2 LVPECL, 155.52 MHz, Fractional-N Mode

(f_XTAL= 25 MHz, Nb = 99, FRAC = 333, MOD = 625, V2 = 2, D2 = 8), Spurs

Disabled

Figure 17. Phase Noise, PLL2, OUT2 LVPECL, 622.08 MHz, Fractional-N Mode

(f_XTAL= 25 MHz, Nb = 99, FRAC = 333, MOD = 625, V2 = 2, D2 = 2), Spurs

Disabled

Rev. 0 | Page 20 of 44

Data Sheet

AD9577

OUTPUT JITTER

480

500

490

480

470

460

450

440

475

470

465

460

455

450

445

440

435

430

86 87 88 89 90 91 92 93 94 95 96 97 98 99 100101102

85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103

Nb

Na

Figure 18. Typical Integrated Random Phase Jitter in fs rms for PLL1 and

OUT0P LVPECL as Feedback Divider Value Na Swept (f_XTAL= 25 MHz, V0 = 5,

D0 = 5)

Figure 19. Typical Integrated Random Phase Jitter in fs rms for PLL2 and

OUT2P LVPECL as Feedback Divider Value Nb Swept

(f_XTAL= 25 MHz, V2 = 5, D2 = 5, Integer-N Mode)

Rev. 0 | Page 21 of 44

AD9577

Data Sheet

TYPICAL OUTPUT SIGNAL

5ns/DIV

1ns/DIV

Figure 20 Typical LVPECL Differential Output Trace, 156.25 MHz

Figure 23. Typical LVPECL Differential Output Trace, 625 MHz

5ns/DIV

1ns/DIV

Figure 21. Typical LVDS Differential Output Trace, 156.25 MHz

Figure 24. Typical LVDS Differential Output Trace, 625 MHz

10ns/DIV

1ns/DIV

Figure 25. Typical REFOUT Output Trace, 25 MHz

Figure 22. Typical CMOS Output Trace, 200MHz

Rev. 0 | Page 22 of 44

Data Sheet

AD9577

900

800

700

600

500

400

3.5

3.4

3.3

3.2

3.1

3.0

2.9

2.8

2.7

0.5pF LOAD

5.2pF LOAD

10.5pF LOAD

2.6

2.5

0

100

200

300

400

500

600

0

20

40

60

80

100 120 140 160 180 200

FREQUENCY (MHz)

Figure 28. LVDS Differential, Peak-to-Peak Output Swing vs. Frequency

Figure 26. CMOS Single-Ended, Peak-to-Peak Output Swing vs. Frequency,

for Loads of 0.5 pF, 5.2 pF, and 10.5 pF, Measured with a Tektronix P7313

Active Probe

1.8

1.7

1.6

1.5

1.4

1.3

1.2

0

100

200

300

400

500

600

FREQUENCY (MHz)

Figure 27. LVPECL Differential, Peak-to-Peak Output Swing vs. Frequency

Rev. 0 | Page 23 of 44

AD9577

Data Sheet

TYPICAL SPREAD SPECTRUM PERFORMANCE CHARACTERISTICS

100.1

100.0

99.9

99.8

99.7

99.6

99.5

99.4

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

TIME (10µs/DIV)

695

697

699

701

FREQUENCY (MHz)

Figure 29. Typical Spread Spectrum Frequency Modulation Profile OUT2,

Nb = 96, FRAC = 0, MOD = 1000, CkDiv = 7, NumSteps = 59, FracStep = −8,

f_OUT= 100 MHz with −0.5% Downspread at 30.2 kHz, MAX_BW set to 0

Figure 31. Typical Nonspread and Spread Spectrum Power Spectra, OUT2,

Nb = 96, FRAC = 0, MOD = 1000, CkDiv = 7, NumSteps = 59, FracStep = −8,

f_OUT= 100 MHz with −0.5% Downspread at 30.2 kHz, MAX_BW set to 0,

Seventh Harmonic Shown, Spectrum Analyzer Resolution Bandwidth =

120 kHz, Maximum Hold On

10

UNMODULATED

CLOCK SPECTRUM

0

MODULATED

CLOCK

–10

–20

–30

–40

–50

–60

–70

–80

99.00

99.25

99.50

99.75

100.00

100.25

100.50

FREQUENCY (MHz)

Figure 30. Typical Nonspread and Spread Spectrum Power Spectra, OUT2,

Nb = 96, FRAC = 0, MOD = 1000, CkDiv = 7, NumSteps = 59, FracStep = −8,

f_OUT= 100 MHz with −0.5% Downspread at 30.2 kHz, MAX_BW set to 0,

First Harmonic Shown, Spectrum Analyzer Resolution Bandwidth =10 kHz,

Maximum Hold On

Rev. 0 | Page 24 of 44

Data Sheet

AD9577

TERMINOLOGY

Additive Time Jitter

Phase Jitter and Phase Noise

It is the amount of time jitter that is attributable to the device

or subsystem being measured. The time jitter of any external

oscillators or clock sources has been subtracted. This makes it

possible to predict the degree to which the device will affect the

total system time jitter when used in conjunction with the

various oscillators and clock sources, each of which contributes

its own time jitter to the total. In many cases, the time jitter of

the external oscillators and clock sources dominates the system

time jitter.

An ideal sine wave can be thought of as having a continuous

and even progression of phase with time from 0° to 360° for each

cycle. Actual signals, however, display a certain amount of

variation from ideal phase progression over time, which is

called phase jitter. Although many causes can contribute

to phase jitter, one major cause is random noise, which is

characterized statistically as being Gaussian (normal) in

distribution.

This phase jitter leads to a spreading out of the energy of the

sine wave in the frequency domain, producing a continuous

power spectrum. This power spectrum is usually reported as

a series of values whose units are dBc/Hz at a given offset in

frequency from the sine wave (carrier). The value is a ratio

(expressed in dB) of the power contained within a 1 Hz band-

width with respect to the power at the carrier frequency. For each

measurement, the offset from the carrier frequency is also given.

Random Jitter Measurement

On the AD9577, the rms jitter measurements are made by

integrating the phase noise, with spurs disabled. There are two

reasons for this. First, because the part is highly configurable, any

measured spurs are a function of the current programmed state

of the device. For example, there may be a small reference spur at

the PFD frequency present on the output spectrum. If the PFD

operates at 19.44 MHz (which is common for telecommunications

applications), the resulting jitter falls within the normal 12 kHz

to 20 MHz integration bandwidth. When the PFD operates

above 20 MHz, the deterministic jitter is not included in the

measurement. As another example, for PLL2, the value of the

chosen FRAC and MOD values affects the amplitude and

location of a spur, and therefore, it is not possible to configure

the PLL to provide a general measurement that includes spurs.

It is meaningful to integrate the total power contained within

some interval of offset frequencies (for example, 12 kHz to

20 MHz). This is called the integrated phase noise over that

frequency offset interval and can be readily related to the time

jitter due to the phase noise within that offset frequency interval.

Phase noise has a detrimental effect on error rate performance

by increasing eye closure at the transmitter output and reducing

the jitter tolerance/sensitivity of the receiver.

The second, and more significant reason, is due to the statistical

nature of spurious components. The jitter performance information

of the clock generator is required so that a jitter budget for the

complete communications channel can be established. By

knowing the jitter characteristics at the ultimate receiver, the

data bit error rate (BER) can be estimated to ensure robust data

transfer. The received jitter characteristic consists of random

jitter (RJ), due to random perturbations such as thermal noise,

and deterministic jitter (DJ), due to deterministic perturbations

such as crosstalk spurs. To make an estimate of the BER, the

total jitter peak-to-peak (TJ p-p) value must be known. It is the

total jitter value that determines the amount of eye closure at

the receiver and, consequently, the bit error rate. The TJ p-p

value is specified for a given number of clock edges. For

example, in networking applications, the TJ is specified for 1¹²

clock edges. The equation for the total jitter peak-to-peak is

Time Jitter

Phase noise is a frequency domain phenomenon. In the

time domain, the same effect is exhibited as time jitter. When

observing a sine wave, the time of successive zero crossings

vary. In a square wave, the time jitter is seen as a displacement

of the edges from their ideal (regular) times of occurrence. In

both cases, the variations in timing from the ideal are the time

jitter. Because these variations are random in nature, the time

jitter is specified in units of seconds root mean square (rms) or

1 sigma of the Gaussian distribution.

Additive Phase Noise

It is the amount of phase noise that is attributable to the device

or subsystem being measured. The phase noise of any external

oscillators or clock sources has been subtracted. This makes it

possible to predict the degree to which the device affects the

total system phase noise when used in conjunction with the

various oscillators and clock sources, each of which contributes

its own phase noise to the total. In many cases, the phase noise

of one element dominates the system phase noise.

TJ p-p = DJ p-p + 2 × Q × RJ rms

(1)

where the Q factor represents the ratio of the expected peak

deviation to the standard deviation in a Gaussian process for a

given population (of edge crossings). For 1¹²clock edges, Q is

7.03; therefore, for networking applications, the total jitter peak-

to-peak is estimated by

TJ p-p = DJ p-p + 14.06 × RJ rms

(2)

Rev. 0 | Page 25 of 44

AD9577

Data Sheet

Therefore, to accurately estimate the TJ p-p, separate

disabled. Due to the 14.06 factor in Equation 2, the spurious DJ

components on the clock output only have a small impact on

the TJ p-p measurement and, consequently, the system BER

performance. Therefore, it is clear that the DJ component (that

is, the spur) should not be added to the rms value of the random

jitter directly. However, if the phase noise jitter measurement

was preformed with spurs enabled, this is exactly what the

measurement would be reporting. For more background

information, see Fibre Channel, Methodologies for Jitter and

Signal Quality Specification-MJSQ, Rev. 14, June 9, 2004.

measurements of the rms value of the random jitter (RJ rms)

and the peak-to-peak value of the deterministic jitter (DJ p-p)

must be taken. To measure the RJ rms of the clock signal,

integrate the clock phase noise over the desired bandwidth, with

spurs disabled (that is, removed) from the measurement. If the

DJ spurs were included in the measurement, the DJ

contribution would also be multiplied by 14.06 in Equation 2,

leading to a grossly pessimistic estimate of the total jitter. This is

why it is important to measure the integrated jitter with spurs

Rev. 0 | Page 26 of 44

Data Sheet

AD9577

DETAILED BLOCK DIAGRAM

REFSEL

22pF

XT1

AD9577

XTAL

OSC

22pF

XT2

CMOS

REFOUT

REFCLK

DIVIDE

1 OR 2

VCO

DIVIDERS

OUTPUT

DIVIDERS

OUTPUT

BUFFERS

LDO1

PLL1

V0

D0

FORMAT1

SCL

SDA

2

I C

VCO

2.15GHz

TO

CONTROL

LVPECL/LVDS

OR 2 × CMOS

DIVIDE BY

2 TO 6

DIVIDE BY

1 TO 32

2.55GHz

V1

D1

LVPECL/LVDS

OR 2 × CMOS

DIVIDE BY

2 TO 6

DIVIDE BY

1 TO 32

DIVIDE BY

80 TO 131

MARGIN

SSCG

FEEDBACK

DIVIDER

N

A

MAX_BW

VCO

DIVIDERS

OUTPUT

DIVIDERS

OUTPUT

BUFFERS

LDO2

PLL2

V2

D2

FORMAT2

VCO

2.15GHz

TO

LVPECL/LVDS

OR 2 × CMOS

DIVIDE BY

2 TO 6

DIVIDE BY

1 TO 32

2.55GHz

V3

D3

LVPECL/LVDS

OR 2 × CMOS

DIVIDE BY

2 TO 6

DIVIDE BY

1 TO 32

DIVIDE BY

80 TO 131

FEEDBACK

DIVIDER

N

B

14× VS

3-BIT

SDM

FRAC

FRAC_TRIWAVE

0

1

4× GND +

PADDLE

MOD

SSCG

LDO

f_PFD

220nF

SSCG

CKDIV

FRAC

FRACSTEP

NUMSTEPS

FRAC_TRIWAVE

TRIWAVE

GENERATOR

Figure 32. Detailed Block Diagram

Rev. 0 | Page 27 of 44

AD9577

Data Sheet

EXAMPLE APPLICATION

REFSEL

25MHz XTAL

REFCLK

XTAL

OSC

CMOS

25MHz

CMOS

DIVIDE

1 OR 2

LDO

PLL1

VCO

2.15GHz

TO

156.25MHz

LVPECL

2.55GHz

125MHz

LVPECL

FEEDBACK

DIVIDER

LDO

PLL2

VCO

2.15GHz

TO

100MHz LVDS

2.55GHz

33.33MHz

2 × CMOS

FEEDBACK

DIVIDER

SCL

SDA

2

I C

CONTROL

MARGIN

AD9577

SSCG

SPREAD SPECTRUM,

SDM

MAX_BW

NOTE THAT ANY FREQUENCIES MAY BE PROGRAMMED.

Figure 33. Example Application

Achievable application frequencies include (but are not limited to) those listed in Table 16.

Table 16. Typical Application Frequencies

Applications

Frequency (MHz)

Ethernet

25, 62.5, 100, 125, 250

10G Ethernet

FB-DIMM

155.52, 156.25, 187.5, 161.1328125, 312.5, 622.08, 625

133.333, 166.666, 200

Fibre Channel

10G Fibre Channel

Inifiniband

53.125, 106.25, 212.5, 318.75, 425

159.375

125

SAS, SATA

Telecomm

PCI Express

PCI, PCI-X

37.5, 75, 100, 120, 150; the AD9577 also meets the −0.5% downspread requirement

19.44, 38.88, 77.76, 155.52, 311.04, 622.08, 627.32962

100, 125, 250; the AD9577 also meets the −0.5% downspread requirement

33.33, 66.66, 100, 133.33, 200

Video

Wireless Infrastructure

13.5, 14.318, 17.7, 18, 27, 72, 74.25, 74.25/1.001, 148.5, 148.5/1.001

61.44, 122.88, 368.64

Rev. 0 | Page 28 of 44

Data Sheet

AD9577

FUNCTIONAL DESCRIPTION

On the AD9577, parameters can be programmed over an I²C

bus to provide custom output frequencies, output formats, and

feature selections. However, this programming must be repeated

after every power cycle of the part.

The PLL2 can operate to modulate the output frequency between its

nominal value and a value that is up to −0.5% lower. This provides

spread spectrum modulation up to −0.5% downspread. Spread

spectrum frequency modulation can reduce the peak power output

of the clock source and any circuitry that it drives and lead to

reduced EMI emissions. In the AD9577, the frequency modulation

profile is triangular. The modulation frequency and modulation

range parameters are all programmable.

The AD9577 contains two PLLs, PLL1 and PLL2, used for

independent clock frequency generation, as shown in Figure 32.

A shared crystal oscillator and reference clock input cell drive

both PLLs. The reference clock of the PLLs can be selected as

either the crystal oscillator output or the reference input clock.

A reference divider precedes each PLL. When the crystal oscillator

input is selected, these dividers must be set to divide by 1. When

the reference input is selected, these dividers can be set to

divide by 1 or divide by 2, provided that the resulting input

frequency to the PLLs is within the permitted 19.44 MHz to

27 MHz range. Both reference dividers are set to divide by the

same value. Each PLL drives two output channels, producing

four output ports in total for the IC. Each output channel

consists of a VCO divider block, followed by an output divider

block. The output divider blocks each drive with an output

buffer port. Each output buffer port can be configured as a

differential LVDS output, a differential LVPECL output, or two

LVCMOS outputs. Additionally, a CMOS-buffered version

reference clock frequency is available.

Both PLLs can be programmed to generate a second independent

frequency map under the control of the MARGIN pin. This

feature can be used to test the frequency robustness of a system.

REFERENCE INPUT AND REFERENCE DIVIDERS

The reference input section is shown in Figure 34. When the

REFSEL pin is pulled high, the crystal oscillator circuit is enabled.

The crystal oscillator circuit needs an external crystal cut to

resonate in fundamental mode in the 19.44 MHz to 27 MHz

range, with 25 MHz being used in most networking applications.

The total load capacitance presented to the crystal should add

up to 14 pF. In the example shown in Figure 34, parasitic trace

capacitance of 1.5 pF and an AD9577 input pin capacitance of

1.5 pF are assumed, with the series combination of the two

22 pF capacitances providing an additional 11 pF. When the

REFSEL pin is pulled low, the crystal oscillator powers down,

and the REFCLK pin must provide a good quality reference clock

instead. Either a dc-coupled LVCMOS level signal or an ac-coupled

square wave can drive this single-ended input, provided that an

external potential divider is used to bias the input at V_S/2.

The upper PLL in Figure 32, PLL1, is an integer-N PLL. By

setting the feedback divider value (Na), the VCO output

frequency can tuned over the 2.15 GHz to 2.55 GHz range to

integer multiples of the PFD input frequency. By setting each of

the VCO divider (V0 and V1) and output divider (D0 and D1)

values, the VCO frequency can be divided down to the required

output frequency, independently, for each of the output ports,

OUT0 and OUT1. The loop filter required for this PLL is

integrated on chip.

The output of the crystal oscillator and reference input circuitry

is routed to a reference divider circuit to further divide down

the reference input frequency to the PLLs by 1 or 2. When the

crystal oscillator circuit is used, the dividers must be set to

divide by 1. The input frequency to the PLLs must be in the

19.44 MHz to 27 MHz range. The divide ratio is set to 1 by

programming the value of R, Register G0[1], to 0. The divide

ratio is set to 2 by programming the value of R to 1.

The lower PLL in Figure 32, PLL2, is a fractional-N PLL. This

PLL can optionally operate as an integer-N PLL for optimum

jitter performance. By setting the feedback divider value (Nb)

and the Σ-Δ modulator fractional (FRAC) and modulus (MOD)

values, the VCO output frequency can tune over the 2.15 GHz

to 2.55 GHz range. The VCO frequency is a fractional multiple

of the PFD input frequency. In this way, the VCO frequency can

tune to obtain frequencies that are not constrained to integer

multiples of the PFD frequency. By setting each of the VCO divider

(V2 and V3) and output divider (D2 and D3) values, the VCO

frequency can be divided down to the required output frequency,

independently, for each of the output ports, OUT2 and OUT3.

The loop filters required for this PLL are integrated on chip.

REFSEL

22pF

XTAL

OSC

DIVIDE

1 OR 2

TO PLLs

22pF

REFCLK

Figure 34. Reference Input Section and Reference Dividers

Table 17. REFSEL (Pin 9) Definition

REFSEL

Reference Source

0

1

REFCLK input

Crystal oscillator

Table 18. Reference Divider Setting

R, Register G0[1]

Reference Divide Ratio

0

1

Divide by 1

Divide by 2

Rev. 0 | Page 29 of 44

AD9577

Data Sheet

OUTPUT CHANNEL DIVIDERS

OUTPUTS

Between each VCO and its associated chip outputs, there are

two divider stages: a VCO divider that has a divide ratio between

2 and 6 and an output divider that can be set to divide between

1 and 32. This cascade of dividers allows a minimum output

channel divide ratio of 2 and a maximum of 192. With VCO

frequencies ranging between 2.15 GHz and 2.55 GHz, the part

can be programmed to spot frequencies over a continuous

frequency range of from 11.2 MHz to 200 MHz, and it can be

programmed to spot frequencies over a continuous frequency

range of 200 MHz and 637.5 MHz, with only a few small gaps.

Each output port can be individually configured as either

differential LVPECL, differential LVDS, or two single-ended

LVCMOS clock outputs. The simplified equivalent circuit of the

LVDS outputs is shown in Figure 36.

3.5mA

OUTxP

OUTxN

Table 19. Divider Ratio Setting Registers

3.5mA

Divide

Divider

I²C Registers Parameter Range

Figure 36. LVDS Outputs Simplified Equivalent Circuit

Channel 0 VCO divider

Channel 1 VCO divider

Channel 2 VCO divider

Channel 3 VCO divider

Channel 0 output divider ADV0[4:0]

Channel 1 output divider ADV1[4:0]

Channel 2 output divider BDV0[4:0]

Channel 3 output divider BDV1[4:0]

ADV0[7:5]

ADV1[7:5]

BDV0[7:5]

BDV1[7:5]

V0

V1

V2

V3

D0

D1

D2

D3

2 to 6

1 to 32¹

The simplified equivalent circuit of the LVPECL outputs is

shown in Figure 37.

3.3V

OUTxP

OUTxN

¹Set to 00000 for divide by 32.

Asserting the SyncCh01 or SyncCh23 bits (Register ADV2[0]

or Register BDV2[0]) allows each PLL output channel to use a

common VCO divider. This feature allows the OUT0/OUT1 and

OUT2/OUT3 output ports to have minimal skew when their

relative output channel divide ratio is an integer multiple.

Duty-cycle correction circuitry ensures that the output duty cycle

remains at 50%.

GND

Figure 37. LVPECL Outputs Simplified Equivalent Circuit

Output channels (consisting of a VCO divider, output divider, and

an output buffer) can be individually powered down to save power.

Setting PDCH0, PDCH1, PDCH2, and PDCH3 (Register BP0[1:0]

and Register DR1[7:6]) powers down the appropriate channel.

VCO

DIVIDER

OUTPUT

DIVIDER

OUT0

V0[2:0]

D0[4:0]

Output buffer combinations of LVDS, LVPECL, and CMOS can be

selected by setting DR1[5:0] as is shown in Table 20 and Table 21.

VCO

DIVIDER

OUTPUT

DIVIDER

OUT1

Table 20. PLL1 Output Driver Format Control Bits,

Register DR1[2:0]

V1[2:0]

D1[4:0]

VCO

DIVIDER

OUTPUT

DIVIDER

OUT2

OUT3

FORMAT1 (PLL1)

Register DR1[2:0]

OUT1P/OUT1N OUT0P/OUT0N

V2[2:0]

D2[4:0]

000

001

010

011

100

101

110

111¹

LVPECL

LVDS

2 × CMOS

LVPECL

LVDS

LVPECL

2 × CMOS

LVDS

2 × CMOS

VCO

DIVIDER

OUTPUT

DIVIDER

V3[2:0]

D3[4:0]

Figure 35. Output Channel Divider Signal Path

LVPECL

2 × CMOS

¹This indicates that the CMOS outputs are in phase; otherwise, they are in

antiphase.

Rev. 0 | Page 30 of 44

Data Sheet

AD9577

Table 21.PLL2 Output Driver Format Control Bits,

Register DR1[5:3]

In ac-coupled applications, the LVPECL output stage needs a

pair of 200 Ω pull-down resistors to GND to provide a dc path for

the output stage emitter followers (see Figure 41). The receiver must

provide an additional 50 Ω single-ended input termination.

FORMAT2 (PLL2)

Register DR1[5:3]

OUT3P/OUT3N

LVPECL

OUT2P/OUT2N

LVPECL

000

001

010

011

100

101

110

111¹

V

TERM

LVDS

2 × CMOS

LVPECL

2 × CMOS

LVDS

50Ω

0.1µF

50Ω

LVPECL

0.1µF

LVDS

LVPECL

2 × CMOS

200Ω

¹This indicates that the CMOS outputs are in phase; otherwise, they are in

antiphase.

Figure 41. LVPECL AC-Coupled Termination

LVDS uses a current mode output stage. The normal value

(default) for this current is 3.5 mA, which yields a 350 mV

output swing across a 100 Ω resistor. The LVDS outputs meet or

exceed all ANSI/TIA/EIA-644 specifications. The LVDS output

buffer should be terminated with a 100 Ω differential resistor

between the receiver input ports (see Figure 38). A recommended

termination circuit for the LVDS outputs is shown in Figure 38.

REFERENCE OUTPUT BUFFER

A CMOS buffered copy of the reference input circuit signal is

available at the REFOUT pin. This buffer can be optionally

powered down by setting Register DR2[0], PDRefOut to Logic 0.

PLL1 INTEGER-N PLL

The upper PLL in Figure 32, PLL1, is an integer-N PLL with a

loop bandwidth of 140 kHz. The input frequency to the PLL

from the reference circuit is f_PFD. The VCO frequency, f_VCO1, is

programmed by setting the value for Na, according to

50Ω

LVDS

100Ω

LVDS

50Ω

Figure 38. LVDS Output Termination

f

_VCO1= f_PFD× Na

(3)

See the AN-586 Application Note, LVDS Outputs for High Speed

A/D Converters, for more information about LVDS.

where Na is programmable in the 80 to 131 range. The VCO

output frequency can tune over the 2.15 GHz to 2.55 GHz range to

integer multiples of the PFD input frequency only.

In a dc-coupled application, the LVPECL output buffer should

be terminated via a pair of 50 Ω resistors to a voltage of V_CC− 2 V.

This can be implemented by using potential dividers of 127 Ω

and 83 Ω between the supplies, as shown in Figure 39.

3.3V

By setting each of the VCO divider (V0 and V1) and output

divider (D0 and D1) values, the VCO frequency can be divided

down to the required output frequency, independently, for each

of the output ports, OUT0 and OUT1. The f_OUT0frequency

presented to OUT0 can be set according to

3.3V

127Ω

50Ω

Na

V0 × D0

(4)

f_{OUT 0}= f_PFD

×

SINGLE-ENDED

(NOT COUPLED)

LVPECL

The frequency f_OUT1presented to OUT1 can be set according to

50Ω

Na

83Ω

V

= V – 2V

DD

(5)

T

f_OUT1= f_PFD×

V1× D1

The loop filters required for this PLL are integrated on chip.

Figure 39. LVPECL DC-Coupled Termination

An alternative LVPECL termination scheme for dc-coupled

applications is shown Figure 40.

50Ω

LVPECL

50Ω

Figure 40. LVPECL DC-Coupled Y-Termination

Rev. 0 | Page 31 of 44

AD9577

Data Sheet

To determine if both 156.25 MHz and 100 MHz can be derived

from a common f_VCO1frequency in the 2.15 GHz to 2.55 GHz

range, use the lowest common multiple (LCM) of 156.25 MHz

and 100 MHz to determine the lowest VCO frequency that can

be divided down to provide both of these frequencies.

PLL1 PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD determines the phase difference error between the

reference divider output and the feedback divider output clock

edges. The outputs of this circuit are pulse-width modulated up

and down signal pulses. These pulses drive the charge pump

circuit. The amount of charge delivered from the charge pump to

the loop filter is determined by the instantaneous phase error. The

action of the closed loop is to drive the frequency and phase error

at the input of the PFD toward zero. Figure 42 shows a block

diagram of the PFD/CP circuitry.

LCM(156.25 MHz, 100 MHz) = 2.5 GHz

(6)

Therefore, set the VCO frequency to 2.5 GHz. With f_PFD

25 MHz, from Equation 3, Na must be set to 100.

=

For 156.25 MHz on Port 0, set

V0 × D0 = 16

(7)

(8)

3.3V

This can be achieved by setting V0 to 4 and D0 to 4. For

100 MHz on Port 1, set

CHARGE

PUMP

UP

HIGH

D1 Q1

CLR1

V1 × D1 = 25

REFCLK

This can be achieved by setting V1 to 5 and D1 to 5. With a

reference frequency of 25 MHz, the reference divider value, R,

must be set to 1 by setting Register G0[1] to 0. Table 22

summarizes the register settings for this configuration.

CP

Table 22. Register Settings for Example PLL1 Configuration

CLR2

D2 Q2

DOWN

HIGH

Parameter

DivideValue

I²C Register

AF0[5:0]

Register Value

010100

100

00100

101

FEEDBACK

DIVIDER

Na

V0

D0

V1

D1

R

100

4

5

ADV0[7:5]

ADV0[4:0]

ADV1[7:5]

ADV1[4:0]

G0[1]

GND

Figure 42. PFD Circuit Showing Simplified Charge Pump

00101

1

PLL1 VCO

1

PLL1 incorporates a low phase noise LC-tank VCO. This VCO

has 32 frequency bands spanning from 2.15 GHz to 2.55 GHz.

At power-up, a VCO calibration cycle begins and the correct band

is selected based on the feedback divider setting (Na). Whenever a

new feedback divider setting is called for, the VCO calibration

process must run by writing 1 followed by 0 to the NewAcq bit,

Register X0[0].

PLL2 INTEGER/FRACTIONAL-N PLL

The lower PLL in Figure 32, PLL2, is a fractional-N PLL. The

input frequency to the PLL from the reference circuit is f_PFD

.

The VCO frequency, f_VCO2, is programmed by setting the values

for Nb, FRAC, and MOD according to

FRAC

MOD

PLL1 FEEDBACK DIVIDER

(9)

f_VCO2= f _PFD×(Nb +

)

The feedback divider ratio, Na, is used to set the PLL1 VCO

frequency according to Equation 3. Note that the Na value is set

by adding the offset value of 80 to the value programmed to

Register AF0[5:0], where 80 is the minimum divider Na value.

The maximum Na value is 131. For example, to set Na to 85, the

AF0[5:0] register is set to 5.

where Nb is programmable in the 80 to 131 range. To provide

the greatest flexibility and accuracy, both the FRAC and MOD

values can be programmed to a resolution of 12 bits, where

FRAC < MOD. The VCO output frequency can tune over the

2.15 GHz to 2.55 GHz range to fractional multiples of the PFD

input frequency.

SETTING THE OUTPUT FREQUENCY OF PLL1

By setting each of the VCO divider (V2 and V3) and output

divider (D2 and D3) values, the VCO frequency can be divided

down to the required output frequency, independently, for each

of the output ports, OUT2 and OUT3. The f_OUT2frequency

presented to OUT2 can be set according to

For example, set the output frequency (f_OUT0) on Port 0 to

156.25 MHz, the output frequency (f_OUT1) on Port 1 to 100 MHz,

and both the reference frequency (f_REF) and the PFD frequency

(f_PFD) to 25 MHz.

The frequency f_OUT0presented to OUT0 can be set according to

Equation 4.

FRAC

MOD

V2×D2

(Nb +

)

f_OUT2= f_PFD

×

(10)

The frequency f_OUT1presented to OUT1 can be set according to

Equation 5.

Rev. 0 | Page 32 of 44

Data Sheet

AD9577

The f_OUT3frequency presented to OUT3 can be set according to

synthesized. By setting the FRAC and MOD values of the SDM, the

PLL2 VCO frequency can be set according to Equation 9. The SDM

must be turned on by setting PD_SDM to 0, Register ABF0[4].

FRAC

MOD

V3×D3

(Nb +

)

f_OUT3= f_PFD

×

(11)

12-Bit Programmable Modulus (MOD) and Fractional

(FRAC) Values

The loop filters required for this PLL are integrated on chip.

Unlike most other fractional-N PLLs, the AD9577 allows users to

program the modulus over a 12-bit range, which means they can

set up the part in many different configurations. It also usually

means that, in most applications, it is possible to design the PLL

to achieve the desired output frequency multiplication with 0 ppm

frequency error. The MOD value is set by setting Register BF1[3:0]

and Register BF2[7:0]. The FRAC value is set by setting

Register BF0[7:0] and Register BF1[7:4].

By setting the FRAC value to 0, powering down the SDM by setting

Register ABF0[4] to 1, and turning the bleed current off by setting

Register BP0[2] = 0, PLL2 can operate as an integer-N PLL.

Equation 10 and Equation 11 are still used to set the output

frequencies for f_OUT2and f_OUT3. Operation in this mode provides

improved performance in terms of phase noise, spurs, and jitter.

PLL2 PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

Bleed Current

The PLL2 PFD and charge pump is the same as that described

in the PLL1 Phase Frequency Detector (PFD) and Charge Pump

section. When operating in fractional-N mode, a charge pump

bleed current should be enabled to linearize the PLL transfer

function and, therefore, to minimize spurs due to the operation

of the Σ-Δ modulator. Bleed is enabled by setting Register BP0[2].

When the SDM is operational (Register ABF0[4] set to 0), bleed

current should be enabled (Register BP0[2] set to 1), which

increases the in-band phase noise but reduces the fractional spur

amplitudes. All fractional-N jitter data is reported with bleed = 1.

If bleed = 0 in fractional-N mode, the rms jitter decreases

significantly; however, the fractional spur amplitudes increase.

When PLL2 operates in integer-N mode, the bleed current

should be disabled to improve the PLLs in-band phase noise.

PLL2 LOOP BANDWIDTH

The normal PLL loop bandwidth is 50 kHz. When the SSCG input

pin is asserted, the loop bandwidth switches from 50 kHz to

125 kHz, which prevents the triangle-wave modulation waveform

from being overly filtered by the PLL. When the MAX_BW input

pin is set high, it forces the PLL bandwidth to be 250 kHz

instead of 125 kHz.

SPUR MECHANISMS

This section describes the three different spur mechanisms that

arise with a fractional-N PLL: fractional spurs, integer boundary

spurs, and reference spurs.

Fractional Spurs

PLL2 VCO

The fractional interpolator in the AD9577 is a third-order SDM

with a modulus that is programmable to any integer value from

50 to 4095. The SDM is clocked at the PFD reference rate (f_PFD) that

allows PLL output frequencies to be synthesized at a channel step

resolution of f_PFD/MOD. The quantization noise from the Σ-Δ

modulator appears as fractional spurs. The interval between spurs

is f_PFD/L, where L is the repeat length of the code sequence in the

digital Σ-Δ modulator. For the third-order modulator used in the

AD9577, the repeat length depends on the value of MOD, as

listed in Table 23.

PLL2 incorporates a low phase noise LC-tank VCO. This VCO

has 32 frequency bands spanning from 2.15 GHz to 2.55 GHz.

At power-up, a VCO calibration cycle begins and the correct band

is selected based on the feedback divider setting (Nb). Whenever a

new feedback divider setting is called for, the VCO calibration

process must run by writing 1 followed by 0 to the NewAcq bit,

Register X0[0].

PLL2 FEEDBACK DIVIDER

The Nb feedback divider ratio is used to set the PLL2 VCO

frequency according to Equation 9. Note that the Nb value is set

by adding the decimal value programmed to Register BF3[5:0]

to a decimal value of 80, where the minimum divider Nb value

is 80. The maximum Nb value is 131. For example, to set Nb to 85,

Register BF3[5:0] is set to 5.

Table 23. Fractional Spur Frequencies

Repeat

Length

Condition

Spur Interval

If MOD is divisible by 2, but not 3

If MOD is divisible by 3, but not 2

If MOD is divisible by 6

Otherwise

2 × MOD f_PFD/(2 × MOD)

3 × MOD f_PFD/(3 × MOD)

6 × MOD f_PFD/(6 × MOD)

PLL2 Σ-Δ MODULATOR

MOD

f_PFD/MOD

When operating in fractional-N mode only, PLL2 uses a third-

order, multistage noise shaping (MASH) Σ-Δ modulator (SDM)

to adjust the feedback divider ratio. The programmed Nb value

can be adjusted over the −4 to +3 range on every rising clock

edge from the feedback divider output (typically 25 MHz for

networking applications). In this way, the average feedback divide

ratio is adjusted to be a noninteger value, allowing for a VCO

frequency that is a fractional multiple of the PFD frequency to be

Rev. 0 | Page 33 of 44

AD9577

Data Sheet

Integer Boundary Spurs

SETTING THE OUTPUT FREQUENCY OF PLL2

Another mechanism for fractional spur creation is the interactions

between the RF VCO frequency and the reference frequency.

When these frequencies are not integer related (the point of a

fractional-N synthesizer), spur sidebands appear on the VCO

output spectrum at an offset frequency that corresponds to the

beat note or difference frequency, between an integer multiple

of the reference and the VCO frequency. These spurs are attenuated

by the loop filter and are more noticeable on channels close to

integer multiples of the reference where the difference frequency

can be inside the loop bandwidth; therefore, the name integer

boundary spurs.

For example, to set the output frequency (f_OUT2) on Port 2 to

155.52 MHz and the output frequency (f_OUT3) on Port 3 to

38.88 MHz using a reference frequency (f_REF) and PFD

frequency (f_PFD) of 25 MHz, do the following.

The frequency f_OUT2presented to OUT2 can be set according to

Equation 10.

The frequency f_OUT3presented to OUT3 can be set according to

Equation 11.

In this case, both 155.52 MHz and 38.88 MHz can be derived

from the same VCO frequency because they are related by a

factor of 4.

Reference Spurs

The next step is to determine what the required values of f_VCO2

V2, and D2 are to divide down to 155.52 MHz. Table 24 shows

the available options.

,

Reference spurs occur for both integer-N and fractional-N

operation. Reference spurs are generally not a problem in

fractional-N synthesizers because the reference offset is far

outside the loop bandwidth. However, any reference feed-

through mechanism that bypasses the loop may cause a problem.

Feedthrough of low levels of on-chip reference switching noise,

through the reference input or output pins back to the VCO, can

result in noticeable reference spur levels. In addition, coupling

of the reference frequency to the output clocks can result in beat

note spurs. PCB layout needs to ensure adequate isolation between

VCO/LDO supplies, the output traces, and the input or output

reference to avoid a possible feedthrough path on the board. If

the reference output clock (REFCLK) is not required, it should

be powered down to minimize potential board coupling. The

SDM digital circuitry is clocked by the reference clock. The

SDM is enabled when PLL2 is in fractional-N mode. When PLL2

is in fractional-N mode, the switching noise at the reference

frequency may result in increased spurs levels at the outputs.

Table 24. Suitable Values of f_VCO2and V2 × D2, to Achieve

f_OUT2= 155.52 MHz

f_OUT2(MHz)

V2 × D2

f_VCO2(GHz)

2.17728

2.3328

155.52

14

15

155.52

16

2.48832

Choose a f_VCO2value of 2.48832 GHz. Next, determine that the

multiplication ratio (Nb + FRAC/MOD) required to multiply a

f_PFDof 25 MHz up to 2.48832 GHz is 99.5328. Therefore, Nb must

be set to 99 and (FRAC/MOD) = 0.5328. To convert 0.5328 to a

fraction, 0.5328 can be the same as 5328/10000. This fraction

can then be reduced to the lowest terms by dividing both the

numerator and denominator by 16, where 16 is the greatest

common divisor (GCD) of the 5328 and 10,000. This results in

a solution for FRAC/MOD = 333/625.

OPTIMIZING PLL PERFORMANCE

For 155.52 MHz on Port 2, set V2 × D2 = 16. This can be achieved

by setting V2 to 4 and D2 to 4. For 38.88 MHz on Port 3, set V3

× D3 = 64. This can be achieved by setting V3 to 4 and D3 to

16. With a reference frequency of 25 MHz, the reference divider

value, R, must be set to 1 by setting Register G0[1] to 0. Because

both channels use VCO divide values of 4on V2 and V3, SyncCh23,

Register BDV2[0], can be set to 1 to ensure that the clock edges

on Port 2 and Port 3 are synchronized. Table 25 summarizes the

register setting for this configuration.

Because the AD9577 can be configured in many ways, some guide-

lines should be followed to ensure that the high performance is

maintained. For both PLLs, there can be a small advantage in

choosing a lower VCO frequency because the VCO phase noise

tends to be slightly better at lower frequencies. Both VCOs should

not operate at the same frequency because this degrades jitter

performance. The two VCO frequencies should differ by at least

2 MHz. The following guidelines apply to PLL2 operating in

fractional-N mode only. If possible, denominators that have factors

of 2, 3, or 6 should be avoided because they can produce slightly

higher subfractional spur components. Avoid low and high

fractions (that is, FRAC/MOD close to 1/MOD or (MOD − 1)/

MOD) because these are more susceptible to larger fractional

spur components and integer boundary spurs. Avoid creating a

low valued beat frequency between the output frequency and the

PFD frequency to minimize the risk of low offset beat frequency

spurs. For example, setting f_PFD= 25 MHz, and f_OUT= 100.01 MHz

can create an output spur at 10 kHz offset to 100.01 MHz,

Table 25. Registers Setting for Example PLL2 Configuration

Parameter Value

I²C Register

BF3[5:0]

Register Value

010011

000101001101

001001110001

100

00100

100

10000

0000

Nb

99

333

625

4

FRAC

MOD

V2

BF0[7:0], BF1[7:4]

BF1[3:0], BF2[7:0]

BDV0[7:5]

BDV0[4:0]

BDV1[7:5]

BDV1[4:0]

G0[1]

D2

4

V3

4

D3

R

16

1

depending on board layout. Choosing a smaller MOD value results

in fractional spurs that are at a higher frequency and, consequently,

are better filtered by the PLL loop filter bandwidth of 50 kHz.

SyncCh23

1

BDV2[0]

1

Rev. 0 | Page 34 of 44

Data Sheet

AD9577

f_VCO

MARGINING

VCO

FREQUENCY

By asserting the MARGIN pin, a second full frequency map can

be applied to the output ports. The values for the Na, V0, D0,

V1, and D1 parameters, and the Nb, FRAC, MOD, V2, D2, V3,

D3 parameters must be programmed over the I²C, although default

values exist. There are some limitations: the output buffer signal

formats cannot be changed, and the PLL2 fractional-N settings,

such as power-down of the SDM, and bleed settings cannot be

changed. The margining feature can be used to set higher than

nominal frequencies on each of the ports to test system robustness.

f_VCO– 0.5%

TIME

VCO

2.15GHz

TO

f_PFD

2.55GHz

DIVIDE BY

80 TO 131

FEEDBACK

DIVIDER

N

B

3-BIT

SDM

When the MARGIN pin signal level is changed, a new frequency

acquisition is performed.

FRAC

FRAC_TRIWAVE

0

1

MOD

SPREAD SPECTRUM CLOCK GENERATION (SSCG)

SSCG

By asserting the SSCG (spread spectrum clock generator) pin,

PLL2 operates in spread spectrum mode, and the output

frequency modulates with a triangular profile. As the clock

signal energy spreads out over a range of frequencies, it reduces

the peak power at any one frequency when observed with a

spectrum analyzer through a resolution bandwidth filter. This

result improves the radiated emissions from the part and from

the devices that receive its clock.

FRAC_TRIWAVE = 3072

FRAC_TRIWAVE = 1029

TIME

f_PFD

SSCG

CKDIV

FRAC_TRIWAVE

TRIWAVE

FRAC

FRACSTEP

NUMSTEPS

GENERATOR

The triangular-wave modulation is implemented by controlling

the divide ratio of the feedback divider. This is achieved by

ramping the fractional word to the SDM. Figure 43 shows an

example implementation. The PFD frequency, f_PFD, is 25 MHz.

The starting VCO frequency, f_VCO, is 25 MHz × (99 + 3072/4096),

giving 2.49375 GHz. By continuously ramping the FRAC word

down and up, this frequency is periodically reduced to 25 MHz ×

(99 + 1029/4096) = 2.481281 GHz. This results in a triangular

frequency modulation profile, with a peak downspread (that is,

peak percentage frequency reduction) of −0.5%. By controlling

the step size, number of steps, and the step rate, the modulation

frequency is adjusted.

Figure 43. Spread Spectrum Clock Generator with Triangular Wave

Modulation, f_PFD= 25 MHz

Basic Spread Spectrum Programming

The SSCG is highly programmable; however, most applications

require that the frequency modulation rate be between 30 kHz

and 33 kHz and that the peak frequency deviation be −0.5%

downspread. The AD9577 supports downspread only, with a

maximum deviation of −0.5%.

The key parameters (which are not themselves registers) that

define the frequency modulation profile include the following:

•

f_MOD, which is the frequency of the modulation waveform.

FracRange, which determines the peak frequency deviation

by setting the maximum change in the FRAC value from

the nominal.

The following equations determine the value of these parameters:

FracRange = FracStep × NumSteps

(12)

f_PFD

f_MOD

=

(13)

2× NumSteps×CkDiv

where the following are programmable registers:

•

NumSteps is the number of fractional word steps in half the

triwave period.

FracStep is the value of the fractional word increment/

decrement, while traversing the tri-wave.

CkDiv is the integer value by which the reference clock

frequency is divided to determine the update rate of the

triangular-wave generator, that is, the step update rate.

•

f_PFDis the PFD frequency.

Rev. 0 | Page 35 of 44

AD9577

Data Sheet

Table 26 shows the relevant register names and programmable

ranges.

Table 27. CkDiv and FracStep Values Used in Worked Example

Ideal

CkDiv

FracStep

−1.5675

−2.35125

−3.135

−3.91875

−4.7025

−5.48625

−6.27

Rounded FracStep

FracStep Error

21.6%

17.6%

4.5%

2.0%

6.0%

9.7%

4.5%

0.77%

2.0%

Table 26. Registers Used to Program SSCG Operation

2

3

4

5

6

7

8

9

−2

−3

−4

−5

−6

−7

−8

Parameter

NumSteps

FracStep

CkDiv

Register Name

BS2[7:0], BS3[7]

BS1[7:0]

Range

+1 to +511

−128 to 0

+2 to +127

BS3[6:0]

Because the register values need to be expressed as integers,

there are no guaranteed exact solutions; therefore, some

approximations and trade-offs must be made. The fact that

neither FracRange nor f_MODneeds to be exact is exploited.

Note that the SSCG pin must be toggled every time the SSCG

parameters are adjusted for the changes to take effect.

−7.05375

−7.8375

10

Both CkDiv and NumSteps must be integers. To minimize error,

CkDiv = 9 and FracStep = −7 was chosen. With a target for

FracRange = −313.5, Equation 12 is used to find the ideal value of

NumSteps = 44.79, which is rounded to 45. From Equation 12,

the actual used value for FracRange is

Worked Example: Programming for f_MOD= 31.25 kHz,

Downspread = −0.5%, f_PFD= 25 MHz

Assume Nb = 100, MOD = 625, and FRAC = 198. In addition, a

large number of frequency steps are desired to cover −0.5%. The

objective is to find values for FracStep, NumSteps, and CkDiv

that result in the required frequency modulation profile.

FracRange = −7 × 45 = −315

The accuracy of this solution needs to be verified. Putting the

derived values into Equation 13 gives

The total feedback divider ratio is

25 MHz

f_PFD

2×NumSteps×CkDiv 2×45×9

f _MOD

=

= 30.86 kHz

FRAC

MOD

N_TOT= Nb +

= 100 + 198/625 = 62,698/625

In addition, the percentage frequency deviation is obtained as

FracRange is set to −0.5% of 62,698, which results in an ideal

value of −313.5.

100× FracRange

FrequencyDeviation =

MOD × N_TOT

By rearranging Equation 12 and Equation 13, it results in

100× −315

=

= −0.502%

⎛

⎜

⎝

⎞

⎟

⎠

2× FracRange × f_MOD

62698

625

FracStep = CkDiv ×

(14)

625×

f_PFD

Putting in the values for FracRange, f_MOD, and f_PFDfrom the

previous information, the following results:

The f_MODand the percentage frequency deviation are very close to

the target values. The register settings required for this example

are detailed in Table 29.

FracStep = CkDiv × (−0.78375)

(15)

SSCG Register Summary

An approximate solution must be found to Equation 15 that

produces an integer value for CkDiv, which gives a value that is

very close to an integer for FracStep. In this case, considering

CkDiv values in the range of 2 to 10 gives the FracStep values

shown in Table 27.

Table 28 summarizes the programmable registers required to set

up SSCG.

Table 28. Register Values for SSCG

Parameter

NumSteps

FracStep

CkDiv

FRAC

MOD

Register Names

BS2[7:0], BS3[7]

BS1[7:0]

Range

+1 to +511

−128 to 0

+2 to +127

0 to +4094

0 to +4095

0 to +51

BS3[6:0]

BF0[7:0], BF1[7:4]

BF1[3:0], BF2[7:0]

BF3[5:0]

Nb

Rev. 0 | Page 36 of 44

Data Sheet

AD9577

MAX_BW

The normal bandwidth of PLL2 is 50 kHz. This low bandwidth

is required to filter the SDM phase noise. When SSCG is activated,

the bandwidth is increased to 125 kHz. There is a trade-off in

setting the PLL bandwidth between allowing the triangular-wave

modulation (that is, its higher order harmonics) to pass through

the PLL unattenuated and passing more SDM phase noise through

to the PLL output. Bringing the MAX_BW pin high changes the

PLL bandwidth to 250 kHz from its default value of 125 kHz

during SSCG operation. Increasing the PLL bandwidth results

in more SDM phase noise being passed unfiltered through to the

PLL output, but more of the triangular-wave harmonics are also

passed through, improving the triangular-wave accuracy.

Table 29. Register Values for SSCG Example

Parameter

NumSteps

FracStep

CkDiv

FRAC

MOD

Register Name

BS2[7:0], BS3[7]

BS1[7:0]

Range

Value (Decimal)

Value(Binary)

00101101

11111001

+1 to +511

−128 to 0

+2 to +127

0 to +4094

0 to +4095

0 to +63

+45

−7

+9

+198

+625

80 + 20 = 100

BS3[6:0]

0001001

BF0[7:0], BF1[7:4]

BF1[3:0], BF2[7:0]

BF3[5:0]

000011000110

001001110001

010100

Nb

Rev. 0 | Page 37 of 44

AD9577

Data Sheet

I²C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION

R/W

CTRL

SLAVE ADDRESS [6:0]

1

0

X

0 = WR

1 = RD

Figure 44. Slave Address Configuration

S

SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S)

DATA A(S)

P

Figure 45. I²C Write Data Transfer

S

SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S)

S

SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M)

DATA A(M) P

S = START BIT

P = STOP BIT

A(M) = LACK OF ACKNOWLEDGE BY MASTER

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

Figure 46. I²C Read Data Transfer

START BIT

STOP BIT

SLAVE ADDRESS

SUB ADDRESS

DATA

SDA

SCL

A6

A5

A7

A0

D7

D0

S

P

WR

ACK

SLADDR[4:0]

SUB ADDR[6:1]

DATA[6:1]

Figure 47. I²C Data Transfer Timing

t_F

t_SU;DAT

t_HD;STA

t_BUF

t_R

SDA

SCL

t_SU;STO

t_R

t_F

t_LOW

t_HIGH

t_HD;STA

t_SU;STA

S

P

S

t_HD;DAT

Figure 48. I²C Port Timing Diagram

Rev. 0 | Page 38 of 44

Data Sheet

AD9577

Table 30. Internal Register Map

Register

Name

R/W Addr D7

D6

0

D5

0

D4

0

D3

0

D2

D1

D0

C0

W

0x40

0x1F

0x11

0x18

0x1C

0x19

0x1A

0x1B

0x1D

0x22

0x23

0x24

0x25

0x26

0x27

0x2A

0x2B

0x2C

0x30

0x31

0

EnI2C

0

X0

0

NewAcq

PDCH0

BP0

0

Bleed

PDCH1

AF0

0

Na[5:0], PLL1 feedback divider ratio

Nb[5:0], PLL2 feedback divider ratio

BF3

0

BF0

FRAC[11:4], SDM fractional word

MOD[11:8], SDM modulus

BF1

FRAC[3:0], SDM fractional word

BF2

MOD[7:0], SDM modulus

0

ABF0

ADV0

ADV1

ADV2

BDV0

BDV1

BDV2

BS1

1

0

1

0

PD_SDM

0

V0[2:0], Channel 0 VCO divider

V1[2:0], Channel 1 VCO divider

D0[4:0], Channel 0 output divider value

D1[4:0], Channel 1 output divider value

0

SyncCh01

SyncCh23

V2[2:0], Channel 2 VCO divider

V3[2:0], Channel 3 VCO divider

D2[4:0], Channel 2 output divider value

D3[4:0], Channel 3 output divider value

0

FracStep[7:0], SSCG fractional step size

NumSteps[8:1], number of fractional word increments/decrements per half triangular-wave cycle

BS2

BS3

NumSteps[0]

0

CkDiv[6:0], reference divider output is divided by this integer to determine SSCG update rate

Na[5:0], PLL1 feedback divider ratio divider; MARGIN = 1

AM0

AM1

0

V0[2:0], Channel 0 VCO divider;

MARGIN = 1

D0[4:0], Channel 0 output divider value; MARGIN = 1

AM2

W

0x32

V1[2:0], Channel 1 VCO divider;

MARGIN = 1

D1[4:0], Channel 1 output divider value; MARGIN = 1

BM0

BM1

BM2

BM3

BM4

W

0x33

0x34

0x35

0x36

0x37

0

Nb[5:0], PLL2 feedback divider ratio divider; MARGIN = 1

FRAC[11:4], SDM fractional word; MARGIN = 1

FRAC[3:0], SDM fractional word; MARGIN = 1

MOD[11:8], SDM modulus; MARGIN = 1

MOD[7:0], SDM modulus; MARGIN = 1

V3[2:0], Channel 3 VCO divider;

MARGIN = 1

D3[4:0], Channel 3 output divider value; MARGIN = 1

BM5

DR1

W

0x38

0x3A

V2[2:0], Channel 2 VCO divider;

MARGIN = 1

D2[4:0], Channel 2 output divider value; MARGIN = 1

PDCH3

PDCH2

FORMAT2[2:0], output format selection

FORMAT1[2:0], output format selection for

for PLL2 (see Table 21)

PLL1 (see Table 20)

DR2

G0

W

0x3B

0x3D

0

PDRefOut

0

PDPLL1, power-

down PLL1

PDPLL2, power-

down PLL2

R; 0 =

divide by 1

Rev. 0 | Page 39 of 44

AD9577

Data Sheet

Parameter

Value

Notes

DEFAULT FREQUENCY MAP AND OUTPUT

FORMATS

The power-up operation (without I²C programming) of the

AD9577 is represented by a default frequency map and output

formats (see Table 31).

Margining

These parameters are

applied only when the

MARGIN pin = high

f_OUT0= 156.25 MHz,

f_OUT1= 125 MHz

PLL1

Na

V0

D0

V1

D1

f_OUT0

f_OUT1

PLL2

80 + 20 = 100

4

Table 31. Default Parameter Values, f_PFD= 25 MHz

Parameter

Value

Notes

PLL1

f_OUT0= 156.25 MHz,

f_OUT1= 125 MHz

5

Na

V0

80 + 20 = 100

4

156.25 MHz

125 MHz

D0

4

f_OUT2= 212.5 MHz,

f_OUT3= 106.25 MHz

V1

4

D1

5

000

0

Nb

80 + 22 = 102

FORMAT1

SyncCh01

PLL2

OUT0/OUT1 are LVPECL

FRAC

MOD

V2

D2

V3

0

2

6

4

6

f_OUT2= 100 MHz,

f_OUT3= 33.333 MHz

Nb

FRAC

MOD

80 + 16 = 96

0

D3

PD_SDM

Bleed

V2

D2

V3

1

0

4

6

I²C INTERFACE OPERATION

The AD9577 is programmed by a 2-wire, I²C-compatible serial bus

driving multiple peripherals. Two inputs, serial data (SDA) and

serial clock (SCL), carry information between any devices

connected to the bus. Each slave device is recognized by a unique

address. The slave address consists of the 7 MSBs of an 8-bit

word. The 7-bit slave address of the AD9577 is 1000000. The LSB

of the word sets either a read or write operation (see Figure 44).

Logic 1 corresponds to a read operation, and Logic 0

corresponds to a write operation.

4

D3

18

000

0

FORMAT2

SyncCh23

SSCG

FracStep

NumSteps

CkDiv

OUT2/OUT3 are LVPECL

0

To control the device on the bus, do the following protocol.

First, the master initiates a data transfer by establishing a start

condition, defined by a high-to-low transition on SDA while

SCL remains high, which indicates that an address/data stream

follows. All peripherals respond to the start condition and shift

Control

EnI2C

0

NewAcq

PDCH0

PDCH1

PDCH2

PDCH3

PDRefOut

PDPLL1

PDPLL2

R

W

the next eight bits (the 7-bit address and the R/ bit). The bits

are transferred from MSB to LSB. The peripheral that recognizes

the transmitted address responds by pulling the data line low

during the ninth clock pulse, which is known as the acknowledge

bit. All other devices withdraw from the bus at this point and

maintain an idle condition. The idle condition is where the device

monitors the SDA and SCL lines waiting for the start condition

W

and correct transmitted address. The R/ bit determines the

direction of the data. Logic 0 on the LSB of the first byte means

that the master writes information to the peripheral, and Logic 1

on the LSB of the first byte means that the master reads

information from the peripheral.

Rev. 0 | Page 40 of 44

Data Sheet

AD9577

The AD9577 acts as a standard slave device on the bus. The data

on the SDA pin is eight bits long supporting the 7-bit addresses

To overwrite any of the default register values, complete the

following steps:

W

plus the R/ bit. The AD9577 has 31 subaddresses to enable

1. Enable the overwriting of registers by setting EnI2C,

Register C0[1].

2. Only write to registers that need modification from their

the user-accessible internal registers (see Table 30). Therefore, it

interprets the first byte as the device address and the second byte as

the starting subaddress. Auto-increment mode is supported, which

allows data to be read from or written to the starting subaddress

and each subsequent address without manually addressing the

subsequent subaddress. A data transfer is always terminated by

a stop condition. The user can also access any unique subaddress

register on a one-by-one basis without updating all registers.

default value.

3. After all the registers have been set, a new acquisition is

initiated by toggling NewAcq, Register X0[0] from low to high

to low.

An example set of I²C commands follows. These enable the I²C

registers and program the output frequencies of both PLLs. f_PFD

is 25 MHz. A leading W represents a write command.

Stop and start conditions can be detected at any stage of the data

transfer. If these conditions are asserted out of sequence with

normal read and write operations, they cause an immediate jump

to the idle condition. During a given SCL high period, one start

condition, one stop condition, or a single stop condition followed

by a single start condition should be issued. If an invalid subaddress

is issued, the AD9577 does not issue an acknowledge and returns

to the idle condition. If the highest subaddress is exceeded while

reading back in auto-increment mode, the highest subaddress

register contents continue to be output until the master device

issues a no acknowledge, which indicates the end of a read. In a no

acknowledge condition, the SDA line is not pulled low on the ninth

pulse. See Figure 45 and Figure 46 for sample read and write data

transfers, and see Figure 47 for a more detailed timing diagram.

Table 32. I²C Programming Example Register Writes

Write/Read

Register Name

Data (Hex)

Operation

W

C0

AF0

ADV0

ADV1

BF3

BF0

BF1

BF2

ABF0

BP0

02

0A

A6

CC

15

14

D2

71

C0

04

44

B0

01

00

Enable I²C registers

Na = 80 + 10 = 90; f_VCO1= 2.25 GHz

Channel 0 divides by 5 × 6 = 30; f_OUT0= 75 MHz

Channel 1 divides by 6 × 12 = 72; f_OUT1= 31.25 MHz

Nb = 80 + 21 = 101; F_VCO2= 2.53832 GHz

FRAC = 333

FRAC = 333, MOD = 625

MOD = 625

Power-up SDM, release SDM reset

Turn on Bleed

Channel 2 divides by 2 × 4 = 8; f_OUT2= 317.29 MHz

Channel 3 divides by 5 × 16 = 80; f_OUT3= 31.729 MHz

Force new acquisition by toggling NewAcq

BDV0

BDV1

X0

Rev. 0 | Page 41 of 44

AD9577

Data Sheet

TYPICAL APPLICATION CIRCUITS

R

= 100Ω

T

V

S

C

D

10kΩ

V

S

10kΩ

V

C

S

D

1

30

C

D

V

S

VSCA

VSOB1A

OUT1P

OUT1N

VSFA

VSI2C

REFOUT

VSREFOUT

VSX

100Ω DIFFERENTIAL

TRANSMISSION LINE

R

= 100Ω

T

V

S

SSCG

AD9577

V

S

VSM

REFCLK

XT2

22pF

VSFB

XT1

OUT3P

OUT3N

VSOB3B

100Ω DIFFERENTIAL

R

= 100Ω

T

TRANSMISSION LINE

REFSEL

VSCB

V

S

V

S

21

10

C

D

C

D

220nF

DO NOT CONNECT OTHER TRACES

TO PIN 15, PIN 16, PIN 35, AND PIN 36.

CAPACITORS C CONSIST OF

D

100nF IN PARALLEL WITH 10nF.

C

D

V

S

R

= 100Ω

T

Figure 49. Typical LVDS Application Circuit

Rev. 0 | Page 42 of 44

Data Sheet

AD9577

127Ω

83Ω

V

S

V

S

C

D

10kΩ

V

S

10kΩ

V

C

S

D

V

S

1

30

C

D

V

S

VSCA

VSOB1A

OUT1P

OUT1N

VSFA

127Ω

83Ω

127Ω

83Ω

50Ω

VSI2C

REFOUT

VSREFOUT

VSX

V

S

SSCG

AD9577

V

S

REFCLK

XT2

VSM

22pF

S

VSFB

127Ω

83Ω

127Ω

83Ω

50Ω

XT1

OUT3P

OUT3N

VSOB3B

REFSEL

VSCB

V

S

21

10

C

D

C

D

220nF

DO NOT CONNECT OTHER TRACES

TO PIN 15, PIN 16, PIN 35, AND PIN 36.

CAPACITORS C CONSIST OF

D

100nF IN PARALLEL WITH 10nF.

C

D

V

S

127Ω

83Ω

V

S

83Ω

Figure 50. Typical LVPECL Application Circuit

POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION

Many applications seek high speed and performance under less

than ideal operating conditions. In these application circuits,

the implementation and construction of the PCB is as important

as the circuit design. Proper RF techniques must be used for

device selection, placement, and routing, as well as for power

supply bypassing and grounding to ensure optimum performance.

Each power supply pin should have independent decoupling and

connections to the power supply plane. It is recommended that the

device exposed paddle be directly connected to the ground plane

by a grid of at least nine vias. Care should be taken to ensure that

the output traces cannot couple onto the reference or crystal input

circuitry.

Rev. 0 | Page 43 of 44

AD9577

Data Sheet

OUTLINE DIMENSIONS

6.10

6.00 SQ

5.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

31

30

40

1

0.50

BSC

*

4.70

EXPOSED

PAD

4.60 SQ

4.50

21

20

10

11

0.45

0.40

0.35

0.20 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5

WITH EXCEPTION TO EXPOSED PAD DIMENSION.

Figure 51. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

6 mm × 6 mm Body, Very Very Thin Quad

(CP-40-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

Ordering Quantity

AD9577BCPZ

AD9577BCPZ-RL

AD9577BCPZ-R7

AD9577-EVALZ

−40°C to +85°C

40-Lead LFCSP_WQ

CP-40-7

40-Lead LFCSP_WQ, 13”Tape Reel

40-Lead LFCSP_WQ, 7”Tape Reel

Evaluation Board

2,500

750

¹Z = RoHS Compliant Part.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D09284-0-10/11(0)

Rev. 0 | Page 44 of 44


型号：	AD9577-EVALZ
厂家：	ADI
描述：	Clock Generator with Dual PLLs 时钟发生器，提供双PLL 时钟发生器
文件：	总44页 (文件大小：641K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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