AD9609BCPZRL7-65 [ADI]
10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter;
| 型号： | AD9609BCPZRL7-65 |
| 厂家： | 
ADI |
| 描述： | 10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter 转换器 |
| 文件： | 总32页 (文件大小：1122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
Data Sheet
AD9609
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
GND
SDIO SCLK CSB
DRVDD
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
61.5 dBFS at 9.7 MHz input
61.0 dBFS at 200 MHz input
SFDR
RBIAS
VCM
SPI
OR
PROGRAMMING DATA
D9 (MSB)
VIN+
VIN–
ADC
CORE
75 dBc at 9.7 MHz input
D0 (LSB)
DCO
73 dBc at 200 MHz input
Low power
45 mW at 20 MSPS
VREF
SENSE
AD9609
REF
SELECT
76 mW at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = 0.10 LSB
DIVIDE
BY
MODE
DCS
CONTROLS
1 TO 8
CLK+ CLK–
PDWN DFS MODE
Serial port control options
Figure 1.
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data alignment
PRODUCT HIGHLIGHTS
1. The AD9609 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The sample-and-hold circuit maintains excellent performance
for input frequencies up to 200 MHz and is designed for low
cost, low power, and ease of use.
APPLICATIONS
Communications
3. A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO and data output
(D9 to D0) timing and offset adjustments, and voltage
reference modes.
4. The AD9609 is packaged in a 32-lead RoHS compliant
LFCSP that is pin compatible with the AD9629 12-bit ADC
and the AD9649 14-bit ADC, enabling a simple migration
path between 10-bit and 14-bit converters sampling from
20 MSPS to 80 MSPS.
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging
Rev. C
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Tel: 781.329.4700 ©2009–2018 Analog Devices, Inc. All rights reserved.
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AD9609
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Voltage Reference ....................................................................... 19
Clock Input Considerations...................................................... 20
Power Dissipation and Standby Mode .................................... 22
Digital Outputs ........................................................................... 22
Timing.......................................................................................... 23
Built-In Self-Test (BIST) and Output Test .................................. 24
Built-In Self-Test (BIST) ............................................................ 24
Output Test Modes..................................................................... 24
Serial Port Interface (SPI).............................................................. 25
Configuration Using the SPI..................................................... 25
Hardware Interface..................................................................... 26
Configuration Without the SPI ................................................ 26
SPI Accessible Features.............................................................. 26
Memory Map .................................................................................. 27
Reading the Memory Map Register Table............................... 27
Open Locations .......................................................................... 27
Default Values............................................................................. 27
Memory Map Register Table..................................................... 28
Memory Map Register Descriptions........................................ 30
Applications Information .............................................................. 31
Design Guidelines ...................................................................... 31
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
AD9609-80 .................................................................................. 11
AD9609-65 .................................................................................. 13
AD9609-40 .................................................................................. 14
AD9609-20 .................................................................................. 15
Equivalent Circuits ......................................................................... 16
Theory of Operation ...................................................................... 17
Analog Input Considerations.................................................... 17
REVISION HISTORY
10/2009—Revision 0: Initial Version
11/2018—Rev. B to Rev. C
Updated Outline Dimensions....................................................... 32
Changes to Ordering Guide .......................................................... 32
2/2017—Rev. A to Rev. B
Added Endnote 1, Table 17 ........................................................... 28
Changes to Power and Ground Recommendations Section..... 31
Added Soft Reset Section............................................................... 31
6/2015—Rev. 0 to Rev. A
Change to Product Highlights Section .......................................... 1
Changes to Figure 3 and Table 8 ................................................... 10
Updated Outline Dimensions....................................................... 32
Changes to Ordering Guide .......................................................... 32
Rev. C | Page 2 of 32
Data Sheet
AD9609
GENERAL DESCRIPTION
The AD9609 is a monolithic, single channel 1.8 V supply, 10-bit,
20/40/65/80 MSPS analog-to-digital converter (ADC). It features
a high performance sample-and-hold circuit and on-chip voltage
reference.
A differential clock input with selectable internal 1 to 8 divide ratio
controls all internal conversion cycles. An optional duty cycle
stabilizer (DCS) compensates for wide variations in the clock duty
cycle while maintaining excellent overall ADC performance.
The product uses multistage differential pipeline architecture
with output error correction logic to provide 10-bit accuracy at
80 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.
The digital output data is presented in offset binary, gray code, or
twos complement format. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic. Both 1.8 V and
3.3 V CMOS levels are supported.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as programmable clock and data
alignment and programmable digital test pattern generation. The
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The AD9609 is available in a 32-lead RoHS-compliant LFCSP
and is specified over the industrial temperature range (−40°C
to +85°C).
Rev. C | Page 3 of 32
AD9609
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 1.
AD9609-20/AD9609-40
AD9609-65
Typ
AD9609-80
Typ
Parameter
Temp Min
Typ
Max
Min
Max
Min
Max
Unit
RESOLUTION
Full
10
10
10
Bits
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Full
Full
Full
Full
25°C
Full
25°C
Guaranteed
Guaranteed
Guaranteed
−0.45 +0.05
−1.5
+0.55
−0.45 +0.05 +0.55 −0.45 +0.05 +0.55 % FSR
−1.5 −1.5 % FSR
0.25 LSB
Differential Nonlinearity (DNL)2
0.15/ 0.25
0.25
0.45
0.05/ 0.08
0.15
0.07
LSB
0.45 LSB
LSB
Integral Nonlinearity (INL)2
0.35
0.15
2
0.15
2
0.15
2
TEMPERATURE DRIFT
Offset Error
Full
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation Error at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
Full
Full
0.984 0.996
2
1.008
0.984 0.996 1.008 0.984 0.996 1.008
V
mV
2
2
25°C
0.06
0.08
0.08
LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance3
Input Common-Mode Voltage
Input Common-Mode Range
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Full
Full
Full
Full
Full
2
6
0.9
2
6
0.9
2
6
0.9
V p-p
pF
V
0.5
1.3
0.5
1.3
0.5
1.3
V
7.5
7.5
1.8
7.5
1.8
kΩ
Full
Full
1.7
1.7
1.8
1.9
3.6
1.7
1.7
1.9
3.6
1.7
1.7
1.9
3.6
V
V
Supply Current
IAVDD2
IDRVDD2 (1.8 V)
IDRVDD2 (3.3 V)
Full
Full
Full
24.9/29.7
1.4/2.2
27.0/32.0
37.1
3.6
39.5
41.8
4.3
45
mA
mA
mA
2.5/4.1
6.6
7.9
POWER CONSUMPTION
DC Input
Sine Wave Input2 (DRVDD = 1.8 V)
Sine Wave Input2 (DRVDD = 3.3 V)
Standby Power4
Full
Full
Full
Full
Full
45.2/54.7
46.3/57.4
53.1/67.0
34
67.7
73.3
88.6
34
76.3
83.0
89.5
34
mW
mW
mW
mW
mW
52.0/61.0
78.0
92
Power-Down Power
0.5
0.5
0.5
1 Measured with 1.0 V external reference.
2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4 Standby power is measured with a dc input and the CLK active.
Rev. C | Page 4 of 32
Data Sheet
AD9609
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 2.
AD9609-20/AD9609-40
AD9609-65
Min Typ Max
AD9609-80
Min Typ Max Unit
Parameter1
Temp Min
Typ
Max
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 30.5 MHz
25°C
25°C
Full
25°C
Full
25°C
61.7
61.7
61.5
61.5
61.5
61.5
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
61.2
61.0
60.5
fIN = 70 MHz
61.6
61.5
61.0
61.5
61.0
61.0
60.5
fIN = 200 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 9.7 MHz
fIN = 30.5 MHz
25°C
25°C
Full
25°C
Full
61.6
61.5
61.4
61.3
61.4
61.4
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
60.7/60.9
fIN = 70 MHz
61.5
61.4
60
61.4
60
fIN = 200 MHz
25°C
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
25°C
25°C
25°C
25°C
9.9
9.9
9.9
9.9
9.9
9.9
9.6
9.9
9.9
9.9
9.6
Bits
Bits
Bits
Bits
WORST SECOND OR THIRD HARMONIC
fIN = 9.7 MHz
fIN = 30.5 MHz
25°C
25°C
Full
25°C
Full
−81
−80
−78
−80
−78
−80
dBc
dBc
dBc
dBc
−67
−65.5
fIN = 70 MHz
−82
−78
−73
−78
−73
−68 dBc
fIN = 200 MHz
25°C
dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 30.5 MHz
25°C
25°C
Full
25°C
Full
78
80.5
75
75
75
75
dBc
dBc
dBc
dBc
dBc
dBc
67
65.5
fIN = 70 MHz
78
75
73
75
73
68
fIN = 200 MHz
25°C
WORST OTHER (HARMONIC OR SPUR)
fIN = 9.7 MHz
fIN = 30.5 MHz
25°C
25°C
Full
−82
−82
−80
−80
−80
−80
dBc
dBc
dBc
−74
−72
fIN = 70 MHz
25°C
Full
25°C
−82
−80
−80
−80
−80
dBc
−73 dBc
dBc
fIN = 200 MHz
TWO-TONE SFDR
fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS)
ANALOG INPUT BANDWIDTH
25°C
25°C
78
78
dBc
700
700
700
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. C | Page 5 of 32
AD9609
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 3.
AD9609-20/AD9609-40/AD9609-65/AD9609-80
Parameter
Temp
Min
Typ
Max
Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
High Level Input Current
Low Level Input Current
Input Resistance
CMOS/LVDS/LVPECL
0.9
Full
Full
Full
Full
Full
Full
Full
V
0.2
GND − 0.3
−10
−10
8
3.6
AVDD + 0.2
+10
+10
12
V p-p
V
µA
µA
kΩ
pF
10
4
Input Capacitance
LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Full
Full
Full
Full
Full
Full
1.2
0
−50
−10
DRVDD + 0.3
0.8
−75
+10
V
V
µA
µA
kΩ
pF
30
2
Input Capacitance
LOGIC INPUTS (CSB)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Full
Full
Full
Full
Full
Full
1.2
0
−10
40
DRVDD + 0.3
0.8
+10
135
V
V
µA
µA
kΩ
pF
26
2
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage, IOH = 50 µA
High Level Output Voltage, IOH = 0.5 mA
Low Level Output Voltage, IOL = 1.6 mA
Low Level Output Voltage, IOL = 50 µA
DRVDD = 1.8 V
Full
Full
Full
Full
3.29
3.25
V
V
V
V
0.2
0.05
High Level Output Voltage, IOH = 50 µA
High Level Output Voltage, IOH = 0.5 mA
Low Level Output Voltage, IOL = 1.6 mA
Low Level Output Voltage, IOL = 50 µA
Full
Full
Full
Full
1.79
1.75
V
V
V
V
0.2
0.05
1 Internal 30 kΩ pull-down.
2 Internal 30 kΩ pull-up.
Rev. C | Page 6 of 32
Data Sheet
AD9609
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 4.
AD9609-20/AD9609-40
AD9609-65
AD9609-80
Max Min Typ Max Unit
Parameter
Temp Min
Typ
Max
Min
Typ
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
CLK Period—Divide-by-1 Mode (tCLK
CLK Pulse Width High (tCH)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
Full
Full
Full
625
20/40
625
65
625
80
MHz
MSPS
ns
ns
ns
3
3
3
12.5
50/25
)
15.38
25.0/12.5
1.0
0.1
7.69
1.0
0.1
6.25
1.0
0.1
Full
Full
ps rms
Full
Full
Full
Full
Full
Full
Full
3
3
0.1
8
350
600/400
2
3
3
3
3
ns
ns
ns
Cycles
µs
DCO Propagation Delay (tDCO
DCO to Data Skew (tSKEW
)
)
0.1
8
350
300
2
0.1
8
350
260
2
Pipeline Delay (Latency)
Wake-Up Time2
Standby
ns
OUT-OF-RANGE RECOVERY TIME
Cycles
1 Conversion rate is the clock rate after the CLK divider.
2 Wake-up time is dependent on the value of the decoupling capacitors.
N – 1
N + 4
tA
N + 5
N
N + 3
VIN
N + 1
N + 2
tCH
tCLK
CLK+
CLK–
tDCO
DCO
tSKEW
DATA
N – 8
N – 7
N – 6
N – 5
N – 4
tPD
Figure 2. CMOS Output Data Timing
Rev. C | Page 7 of 32
AD9609
Data Sheet
TIMING SPECIFICATIONS
Table 5.
Parameter
Conditions
Min
Typ
Max
Unit
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
10
ns
Rev. C | Page 8 of 32
Data Sheet
AD9609
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
Rating
The exposed paddle is the only ground connection for the chip.
The exposed paddle must be soldered to the AGND plane of the
user’s circuit board. Soldering the exposed paddle to the user’s
board also increases the reliability of the solder joints and
maximizes the thermal capability of the package.
AVDD to AGND
DRVDD to AGND
VIN+, VIN− to AGND
CLK+, CLK− to AGND
VREF to AGND
SENSE to AGND
VCM to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to AGND
SDIO/PDWN to AGND
MODE/OR to AGND
D0 through D9 to AGND
DCO to AGND
Operating Temperature Range (Ambient)
Maximum Junction Temperature Under Bias
Storage Temperature Range (Ambient)
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
Table 7. Thermal Resistance
Airflow
Velocity
(m/sec)
Package
Type
1, 2
1, 3
1, 4
1,2
θJA
θJC
3.1
θJB
20.7
ΨJT
0.3
0.5
0.8
Unit
°C/W
°C/W
°C/W
32-Lead LFCSP
5 mm × 5 mm
0
1.0
2.5
37.1
32.4
29.1
1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-Std 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
150°C
−65°C to +150°C
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes, reduces the θJA.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. C | Page 9 of 32
AD9609
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK+
CLK–
AVDD
1
2
3
4
5
6
24 AVDD
23
22 DCO
MODE/OR
AD9609
TOP VIEW
(Not to Scale)
CSB
SCLK/DFS
SDIO/PDWN
21 D9 (MSB)
20
19
D8
D7
NIC 7
NIC 8
18 D6
17 D5
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PADDLE. THE EXPOSED PADDLE IS THE ONLY GROUND CONNECTION.
IT MUST BE SOLDEREDTO THE ANALOG GROUND OF THE PCB
TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION,
NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
0
EPAD
Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog
ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength
benefits.
1, 2
3, 24, 29, 32
CLK+, CLK−
AVDD
Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.
1.8 V Supply Pin for ADC Core Domain.
4
5
CSB
SCLK/DFS
SPI Chip Select. Active low enable, 30 kΩ internal pull-up.
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
6
SDIO/PDWN
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-
down. See Table 15 for details.
7 to 10
NIC
No Internal Connection.
ADC Digital Outputs.
11 to 12, 14 to 21 D0 (LSB) to
D9 (MSB)
13
22
23
DRVDD
DCO
MODE/OR
1.8 V to 3.3 V Supply Pin for Output Driver Domain.
Data Clock Digital Output.
Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR).
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100b).
Chip stand-by (SPI Register 0x08, Bits[7:5] = 101b).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b).
Out-of-range (OR) digital output only in non-SPI mode.
25
26
27
28
VREF
SENSE
VCM
RBIAS
VIN−, VIN+
1.0 V Voltage Reference Input/Output. See Table 10.
Reference Mode Selection. See Table 10.
Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
ADC Analog Inputs.
30, 31
Rev. C | Page 10 of 32
Data Sheet
AD9609
TYPICAL PERFORMANCE CHARACTERISTICS
AD9609-80
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
0
0
80MSPS
80MSPS
30.5MHz @ –1dBFS
SNR = 60.5dB (61.5dBFS)
SFDR = 83.5dBc
9.7MHz @ –1dBFS
SNR = 60.5dB (61.5dBFS)
SFDR = 80.3dBc
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. AD9609-80 Single-Tone FFT with fIN = 9.7 MHz
Figure 7. AD9609-80 Single-Tone FFT with fIN = 30.5 MHz
0
0
80MSPS
80MSPS
200MHz @ –1dBFS
SNR = 60.1dB (60.1dBFS)
SFDR = 74.176dBc
70.3MHz @ –1dBFS
SNR = 60.4dB (61.4dBFS)
SFDR = 82.2dBc
–20
–40
–20
–40
–60
–60
2
–80
–80
3
+
6
5
4
–100
–120
–100
–120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. AD9609-80 Single-Tone FFT with fIN = 70.3 MHz
Figure 8. AD9609-80 Single-Tone FFT with fIN = 200 MHz
0
80MSPS
–10
30.5MHz @ –7dBFS
32.5MHz @ –7dBFS
SFDR = 78dBc
–15
–30
–45
–60
–30
–50
SFDR (dBc)
IMD3 (dBc)
F1 + F2
2F1 – F2
2F2 + F1
–75
–90
–70
SFDR (dBFS)
IMD3 (dBFS)
F2 – F1
2F1 – F2
–90
–105
–120
–110
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
4
8
12
16
20
24
28
32
36
40
INPUT AMPLITUDE (dBFS)
FREQUENCY (MHz)
Figure 9. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 30.5 MHz
and fIN2 = 32.5 MHz
Figure 6. AD9609-80 Two-Tone FFT with fIN1 = 30.5 MHz and fIN2 = 32.5 MHz
Rev. C | Page 11 of 32
AD9609
Data Sheet
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
85
80
75
70
65
60
55
50
0.20
0.16
0.12
0.08
0.04
0
SFDR (dBc)
–0.04
–0.08
–0.12
–0.16
–0.20
SNR (dBFS)
0
50
100
150
200
24
224
424
624
824
1024
AIN FREQUENCY (MHz)
OUTPUT CODE
Figure 10. AD9609-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale
Figure 13. DNL Error with fIN = 9.7 MHz
85
1.0
0.8
SFDR (dBc)
80
0.6
0.4
75
70
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
65
SNR (dBFS)
60
0
10
20
30
40
50
60
70
80
24
224
424
624
824
1024
SAMPLE RATE (MHz)
OUTPUT CODE
Figure 14. INL with fIN = 9.7 MHz
Figure 11. AD9609-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz
90
80
SFDRFS
70
SNRFS
60
50
40
SFDR
30
20
SNR
10
0
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBc)
Figure 12. AD9609-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
Rev. C | Page 12 of 32
Data Sheet
AD9609
AD9609-65
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
0
65MSPS
9.7MHz @ –1dBFS
–10
SNR = 60.6dB (61.6dBFS)
SFDR = 83.1dBc
–20
–30
–40
SFDR (dBc)
–50
–60
IMD3 (dBc)
–70
–80
SFDR (dBFS)
–90
–100
IMD3 (dBFS)
–120
–110
–60
0
5
10
15
20
25
30
–54
–48
–42
–36
–30
–24
–18
–12
–6
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 15. AD9609-65 Single-Tone FFT with fIN = 9.7 MHz
Figure 18. AD9609-65 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
0
85
65MSPS
70.3MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
SFDR = 83.4dBc
80
–20
SFDR (dBc)
75
70
–40
–60
65
SNR (dBFS)
–80
60
55
50
–100
–120
0
5
10
15
20
25
30
0
50
100
150
200
FREQUENCY (MHz)
AIN FREQUENCY (MHz)
Figure 16. AD9609-65 Single-Tone FFT with fIN = 70.3 MHz
Figure 19. AD9609-65 SNR/SFDR vs. Input Frequency (AIN) with
2 V p-p Full Scale
0
65MSPS
30.5MHz @ –1dBFS
–20
SNR = 60.6dB (61.6dBFS)
SFDR = 83.9dBc
–40
–60
–80
–100
–120
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 17. AD9609-65 Single-Tone FFT with fIN = 30.5 MHz
Rev. C | Page 13 of 32
AD9609
Data Sheet
AD9609-40
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
0
90
80
70
60
50
40
30
20
10
0
40MSPS
SFDRFS
SNRFS
9.7MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
SFDR = 82.0dBc
–20
–40
–60
SFDR
–80
SNR
–100
–120
0
5
10
FREQUENCY (MHz)
15
20
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBc)
Figure 22. AD9609-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
Figure 20. AD9609-40 Single-Tone FFT with fIN = 9.7 MHz
0
40MSPS
30.5MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
SFDR = 83.8dBc
–20
–40
–60
–80
–100
–120
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
Figure 21. AD9609-40 Single-Tone FFT with fIN = 30.5 MHz
Rev. C | Page 14 of 32
Data Sheet
AD9609
AD9609-20
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
0
90
80
70
60
50
40
30
20
10
0
20MSPS
SFDR (dBFS)
9.7MHz @ –1dBFS
SNR = 60.6dBFS (61.6dBFS)
SFDR = 81.3dBc
–20
SNR (dBFS)
–40
–60
SFDR (dBc)
SNR (dBc)
–80
–100
–120
–10
0
2
4
6
8
10
–60
–50
–40
–30
–20
0
FREQUENCY (MHz)
INPUT AMPLITUDE (dBc)
Figure 23. AD9609-20 Single-Tone FFT with fIN = 9.7 MHz
Figure 25. AD9609-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
0
20MSPS
30.5MHz @ –1dBFS
SNR = 60.6dBFS (61.6dBFS)
SFDR = 84.0dBc
–20
–40
–60
–80
–100
–120
0
2
4
6
8
10
FREQUENCY (MHz)
Figure 24. AD9609-20 Single-Tone FFT with fIN = 30.5 MHz
Rev. C | Page 15 of 32
AD9609
Data Sheet
EQUIVALENT CIRCUITS
DRVDD
AVDD
VIN±
Figure 26. Equivalent Analog Input Circuit
Figure 30. Equivalent D0 to D9 and OR Digital Output Circuit
DRVDD
AVDD
SCLK/DFS,
350Ω
MODE,
375Ω
VREF
SDIO/PDWN
30kΩ
7.5kΩ
Figure 27. Equivalent VREF Circuit
Figure 31. Equivalent SCLK/DFS, MODE, and SDIO/PDWN Input Circuit
DRVDD
AVDD
AVDD
30kΩ
350Ω
375Ω
CSB
SENSE
Figure 32. Equivalent CSB Input Circuit
Figure 28. Equivalent SENSE Circuit
5Ω
CLK+
15kΩ
0.9V
AVDD
15kΩ
5Ω
CLK–
375Ω
RBIAS
AND VCM
Figure 29. Equivalent Clock Input Circuit
Figure 33. Equivalent RBIAS and VCM Circuit
Rev. C | Page 16 of 32
Data Sheet
AD9609
THEORY OF OPERATION
high IF frequencies. Either a shunt capacitor or two single-ended
capacitors can be placed on the inputs to provide a matching
passive network. This ultimately creates a low-pass filter at the
input to limit unwanted broadband noise. See the AN-742
Application Note, the AN-827 Application Note, and the Analog
Dialogue article “Transformer-Coupled Front-End for Wideband
A/D Converters” (Volume 39, April 2005) for more information. In
general, the precise values depend on the application.
The AD9609 architecture consists of a multistage, pipelined ADC.
Each stage provides sufficient overlap to correct for flash errors in
the preceding stage. The quantized outputs from each stage are
combined into a final 10-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate with a
new input sample while the remaining stages operate with pre-
ceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
Input Common Mode
The analog inputs of the AD9609 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide a
dc bias externally. Setting the device so that VCM = AVDD/2 is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 35 and Figure 36.
100
The output staging block aligns the data, corrects errors, and
passes the data to the CMOS output buffers. The output buffers
are powered from a separate (DRVDD) supply, allowing adjust-
ment of the output voltage swing. During power-down, the
output buffers go into a high impedance state.
90
80
SFDR (dBc)
ANALOG INPUT CONSIDERATIONS
70
The analog input to the AD9609 is a differential switched-
capacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
SNR (dBFS)
60
50
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
INPUT COMMON-MODE VOLTAGE (V)
Figure 35. SNR/SFDR vs. Input Common-Mode Voltage,
fIN = 32.1 MHz, fS = 80 MSPS
H
100
90
80
70
60
50
CPAR
H
VIN+
CSAMPLE
S
S
S
S
CSAMPLE
SFDR (dBc)
SNR (dBFS)
VIN–
H
CPAR
H
Figure 34. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample-and-hold mode (see Figure 34). When the input circuit
is switched to sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current injected from the output
stage of the driving source. In addition, low Q inductors or ferrite
beads can be placed on each leg of the input to reduce high diffe-
rential capacitance at the analog inputs and, therefore, achieve
the maximum bandwidth of the ADC. Such use of low Q inductors
or ferrite beads is required when driving the converter front end at
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
INPUT COMMON-MODE VOLTAGE (V)
Figure 36. SNR/SFDR vs. Input Common-Mode Voltage,
fIN = 10.3 MHz, fS = 20 MSPS
An on-board, common-mode voltage reference is included in
the design and is available from the VCM pin. The VCM pin
must be decoupled to ground by a 0.1 µF capacitor, as described
in the Applications Information section.
Rev. C | Page 17 of 32
AD9609
Data Sheet
Differential Input Configurations
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9609. For applications above
~10 MHz where SNR is a key parameter, differential double balun
coupling is the recommended input configuration (see Figure 40).
Optimum performance is achieved while driving the AD9609 in a
differential input configuration. For baseband applications, the
AD8138, ADA4937-2, and ADA4938-2 differential drivers provide
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the ADA4938-2 is easily set
with the VCM pin of the AD9609 (see Figure 37), and the driver
can be configured in a Sallen-Key filter topology to provide
band limiting of the input signal.
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use the AD8352 differential driver.
An example is shown in Figure 41. See the AD8352 data sheet
for more information.
200Ω
33Ω
VIN–
VIN
76.8Ω
AVDD
In any configuration, the value of Shunt Capacitor C is dependent
on the input frequency and source impedance and may need to
be reduced or removed. Table 9 displays the suggested values to set
the RC network. However, these values are dependent on the
input signal and should be used only as a starting guide.
90Ω
10pF
ADC
ADA4938-2
33Ω
0.1µF
120Ω
VCM
VIN+
200Ω
Figure 37. Differential Input Configuration Using the ADA4938-2
Table 9. Example RC Network
For baseband applications below ~10 MHz where SNR is a key
parameter, differential transformer-coupling is the recommended
input configuration. An example is shown in Figure 38. To bias
the analog input, the VCM voltage can be connected to the
center tap of the secondary winding of the transformer.
R Series
(Ω Each)
Frequency Range (MHz)
0 to 70
C Differential (pF)
33
22
Open
70 to 200
125
Single-Ended Input Configuration
VIN+
R
A single-ended input can provide adequate performance in cost-
sensitive applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode swing.
If the source impedances on each input are matched, there should
be little effect on SNR performance. Figure 39 shows a typical
single-ended input configuration.
2V p-p
49.9Ω
C
ADC
R
VCM
VIN–
0.1µF
Figure 38. Differential Transformer-Coupled Configuration
10µF
AVDD
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies below
a few megahertz (MHz). Excessive signal power can also cause
core saturation, which leads to distortion.
1kΩ
R
VIN+
1V p-p
0.1µF
49.9Ω
1kΩ
AVDD
ADC
C
1kΩ
R
VIN–
10µF
0.1µF
1kΩ
Figure 39. Single-Ended Input Configuration
0.1µF
R
0.1µF
VIN+
2V p-p
25Ω
25Ω
P
A
S
S
P
C
ADC
0.1µF
0.1µF
R
VCM
VIN–
Figure 40. Differential Double Balun Input Configuration
V
CC
0.1µF
0Ω
0.1µF
16
1
8, 13
11
0.1µF
0.1µF
ANALOG INPUT
R
R
VIN+
VIN–
2
200Ω
C
ADC
AD8352
10
R
R
G
C
D
D
3
4
5
200Ω
VCM
14
0.1µF
ANALOG INPUT
0Ω
0.1µF
0.1µF
Figure 41. Differential Input Configuration Using the AD8352
Rev. C | Page 18 of 32
Data Sheet
AD9609
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9609. The VREF can be configured using either the internal
1.0 V reference or an externally applied 1.0 V reference voltage.
The various reference modes are summarized in the sections that
follow. The Reference Decoupling section describes the best
practices for PCB layout of VREF.
INTERNAL VREF = 0.996V
Internal Reference Connection
A comparator within the AD9609 detects the potential at the
SENSE pin and configures the reference into two possible modes,
which are summarized in Table 10. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 42), setting VREF to 1.0 V.
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
LOAD CURRENT (mA)
Figure 43. VREF Accuracy vs. Load Current
VIN+
VIN–
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 44 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
ADC
CORE
VREF
4
1.0µF
0.1µF
3
SELECT
LOGIC
2
SENSE
VREF ERROR (mV)
1
0
0.5V
–1
–2
–3
–4
–5
–6
ADC
Figure 42. Internal Reference Configuration
In either internal or external reference mode, the maximum input
range of the ADC can be varied by configuring SPI Address 0x18
as shown in Table 11, resulting in a selectable differential span
from 1 V p-p to 2 V p-p.
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
If the internal reference of the AD9609 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 43 shows
how the internal reference voltage is affected by loading.
Figure 44. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 27). The internal buffer generates the posi-
tive and negative full-scale references for the ADC core. Therefore,
the external reference must be limited to a maximum of 1.0 V.
Table 10. Reference Configuration Summary
Selected Mode
SENSE Voltage (V) Resulting VREF (V)
Resulting Differential Span (V p-p)
Fixed Internal Reference
Fixed External Reference
AGND to 0.2
AVDD
1.0 internal
1.0 applied to external VREF pin
2.0
2.0
Table 11. Scaled Differential Span Summary
Selected Mode
Resulting VREF (V)
SPI Register 0x18 (Hex)
Resulting Differential Span (V p-p)
Fixed Internal or External Reference
Fixed Internal or External Reference
Fixed Internal or External Reference
Fixed Internal or External Reference
Fixed Internal or External Reference
1.0 (internal or external)
1.0 (internal or external)
1.0 (internal or external)
1.0 (internal or external)
1.0 (internal or external)
0xC0
0xC8
0xD0
0xD8
0xE0
1.0
1.14
1.33
1.6
2.0
Rev. C | Page 19 of 32
AD9609
Data Sheet
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 48. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516-4/AD9517-4 clock drivers
offer excellent jitter performance.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9609 sample clock inputs,
CLK+ and CLK−, with a differential signal. The signal is typically
ac-coupled into the CLK+ and CLK− pins via a transformer or
capacitors. These pins are biased internally (see Figure 45) and
require no external bias.
AVDD
0.1µF
0.1µF
CLOCK
INPUT
CLK+
AD951x
PECL DRIVER
0.9V
100Ω
ADC
0.1µF
0.1µF
CLOCK
INPUT
CLK+
CLK–
CLK–
240Ω
240Ω
50kΩ
50kΩ
2pF
2pF
Figure 48. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 49. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516-4/
AD9517-4 clock drivers offer excellent jitter performance.
Figure 45. Equivalent Clock Input Circuit
Clock Input Options
The AD9609 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of great concern, as described in the Jitter Considerations section.
0.1µF
0.1µF
CLOCK
INPUT
CLK+
AD951x
LVDS DRIVER
100Ω
ADC
Figure 46 and Figure 47 show two preferred methods for clock-
ing the AD9609 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF transformer or an RF balun.
0.1µF
0.1µF
CLOCK
INPUT
CLK–
50kΩ
50kΩ
Figure 49. Differential LVDS Sample Clock (Up to 625 MHz)
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is
recommended for clock frequencies from 10 MHz to 200 MHz.
The back-to-back Schottky diodes across the transformer/
balun secondary limit clock excursions into the AD9609 to
approximately 0.8 V p-p differential.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 50).
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9609 while
preserving the fast rise and fall times of the signal that are
critical to a low jitter performance.
V
CC
OPTIONAL
100Ω
0.1µF
1
0.1µF
1kΩ
1kΩ
AD951x
CMOS DRIVER
CLOCK
INPUT
CLK+
50Ω
ADC
CLK–
®
Mini-Circuits
0.1µF
ADT1-1WT, 1:1 Z
0.1µF
0.1µF
XFMR
CLOCK
INPUT
1
50Ω RESISTOR IS OPTIONAL.
CLK+
100Ω
50Ω
ADC
Figure 50. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
0.1µF
CLK–
Input Clock Divider
SCHOTTKY
DIODES:
HSMS2822
0.1µF
The AD9609 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. Optimum
performance can be obtained by enabling the internal duty cycle
stabilizer (DCS) when using divide ratios other than 1, 2, or 4.
Figure 46. Transformer-Coupled Differential Clock (Up to 200 MHz)
1nF
50Ω
1nF
0.1µF
0.1µF
CLOCK
INPUT
CLK+
ADC
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 47. Balun-Coupled Differential Clock (Up to 625 MHz)
Rev. C | Page 20 of 32
Data Sheet
AD9609
Clock Duty Cycle
Jitter Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive
to clock duty cycle. Commonly, a 5% tolerance is required on
the clock duty cycle to maintain dynamic performance
characteristics.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR from the low frequency
SNR (SNRLF) at a given input frequency (fINPUT) due to jitter
(tJRMS) can be calculated by
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 (−SNR /10)
]
LF
The AD9609 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9609. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS on,
as shown in Figure 51.
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 52.
80
75
70
65
0.05ps
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 µs to 5 µs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
0.2ps
60
55
50
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
45
80
75
70
1
10
100
1k
FREQUENCY (MHz)
Figure 52. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal when
aperture jitter may affect the dynamic range of the AD9609. To
avoid modulating the clock signal with digital noise, keep power
supplies for clock drivers separate from the ADC output driver
supplies. Low jitter, crystal-controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), it should be retimed by
the original clock at the last step.
DCS ON
65
60
55
DCS OFF
50
45
40
For more information, see the AN-501 Application Note and
the AN-756 Application Note.
10
20
30
40
50
60
70
80
POSITIVE DUTY CYCLE (%)
Figure 51. SNR vs. DCS On/Off
Rev. C | Page 21 of 32
AD9609
Data Sheet
Low power dissipation in power-down mode is achieved by
POWER DISSIPATION AND STANDBY MODE
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
As shown in Figure 53, the analog core power dissipated by the
AD9609 is proportional to its sample rate. The digital power
dissipation of the CMOS outputs are determined primarily by
the strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details.
where N is the number of output bits (22, in the case of the
AD9609).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is estab-
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
DIGITAL OUTPUTS
The AD9609 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families. Output data can also be
multiplexed onto a single output bus to reduce the total number
of traces required.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 53 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
The CMOS output drivers are sized to provide sufficient output
current to drive a wide variety of logic families. However, large
drive currents tend to cause current glitches on the supplies and
may affect converter performance.
85
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
80
75
70
The output data format can be selected to be either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 12).
65
AD9609-80
60
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
55
50
45
40
35
AD9609-65
AD9609-40
Table 12. SCLK/DFS and SDIO/PDWN Mode Selection
(External Pin Mode)
AD9609-20
20 30
Voltage at Pin SCLK/DFS
SDIO/PDWN
10
40
50
60
70
80
CLOCK RATE (MSPS)
AGND
Offset binary (default) Normal operation
(default)
Figure 53. AD9609 Analog Core Power vs. Clock Rate
DRVDD
Twos complement
Outputs disabled
In SPI mode, the AD9609 can be placed in power-down mode
directly via the SPI port, or by using the programmable external
MODE pin. In non-SPI mode, power-down is achieved by assert-
ing the PDWN pin high. In this state, the ADC typically dissipates
500 µW. During power-down, the output drivers are placed in a
high impedance state. Asserting PDWN low (or the MODE pin
in SPI mode) returns the AD9609 to its normal operating mode.
Note that PDWN is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
Digital Output Enable Function (OEB)
When using the SPI interface, the data outputs and DCO can be
independently three-stated by using the programmable external
MODE pin. The MODE pin (OEB) function is enabled via
Bits[6:5] of Register 0x08.
If the MODE pin is configured to operate in traditional OEB
mode, and the MODE pin is low, the output data drivers and
DCOs are enabled. If the MODE pin is high, the output data
drivers and DCOs are placed in a high impedance state. This
OEB function is not intended for rapid access to the data bus.
Note the MODE pin is referenced to the digital output driver
supply (DRVDD) and should not exceed that supply voltage.
Rev. C | Page 22 of 32
Data Sheet
AD9609
The lowest typical conversion rate of the AD9609 is 3 MSPS. At
clock rates below 3 MSPS, dynamic performance can degrade.
TIMING
The AD9609 provides latched data with a pipeline delay of eight
clock cycles. Data outputs are available one propagation delay
(tPD) after the rising edge of the clock signal.
Data Clock Output (DCO)
The AD9609 provides a data clock output (DCO) signal intended
for capturing the data in an external register. The CMOS data
outputs are valid on the rising edge of DCO, unless the DCO
clock polarity has been changed via the SPI. See Figure 2 for a
graphical timing description.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9609. These transients
can degrade converter dynamic performance.
Table 13. Output Data Format
Input (V)
Condition (V)
< −VREF − 0.5 LSB
= −VREF
Offset Binary Output Mode
00 0000 0000
00 0000 0000
10 0000 0000
11 1111 1111
Twos Complement Mode
10 0000 0000
10 0000 0000
00 0000 0000
01 1111 1111
OR
1
0
0
0
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
11 1111 1111
01 1111 1111
1
Rev. C | Page 23 of 32
AD9609
Data Sheet
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9609 includes a built-in test feature designed to enable
verification of the integrity of each channel as well as to facili-
tate board level debugging. A built-in self-test (BIST) feature that
verifies the integrity of the digital datapath of the AD9609 is
included. Various output test options are also provided to place
predictable values on the outputs of the AD9609.
Bit 2 (BIST INIT) of Register 0x0E. At the completion of the BIST,
Bit 0 of Register 0x24 is automatically cleared. The PN sequence
can be continued from its last value by writing a 0 in Bit 2 of
Register 0x0E. However, if the PN sequence is not reset, the
signature calculation does not equal the predetermined value at
the end of the test. At that point, the user needs to rely on
verifying the output data.
BUILT-IN SELF-TEST (BIST)
OUTPUT TEST MODES
The BIST is a thorough test of the digital portion of the selected
AD9609 signal path. Perform the BIST test after a reset to ensure
that the part is in a known state. During BIST, data from an internal
pseudorandom noise (PN) source is driven through the digital
datapath of both channels, starting at the ADC block output.
At the datapath output, CRC logic calculates a signature from
the data. The BIST sequence runs for 512 cycles and then stops.
Once completed, the BIST compares the signature results with a
pre-determined value. If the signatures match, the BIST sets Bit 0
of Register 0x24, signifying the test passed. If the BIST test failed,
Bit 0 of Register 0x24 is cleared. The outputs are connected during
this test, so the PN sequence can be observed as it runs. Writing
0x05 to Register 0x0E runs the BIST. This enables the Bit 0 (BIST
enable) of Register 0x0E and resets the PN sequence generator,
The output test options are described in Table 17 at Address 0x0D.
When an output test mode is enabled, the analog section of the
ADC is disconnected from the digital back-end blocks and the
test pattern is run through the output formatting block. Some of
the test patterns are subject to output formatting, and some are
not. The PN generators from the PN sequence tests can be reset
by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be
performed with or without an analog signal (if present, the analog
signal is ignored), but they do require an encode clock. For more
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
Rev. C | Page 24 of 32
Data Sheet
AD9609
SERIAL PORT INTERFACE (SPI)
The AD9609 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
gives the user added flexibility and customization, depending
on the application. Addresses are accessed via the serial port and
can be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, which are
documented in the Memory Map section. For detailed operational
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 54 and
Table 5.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device; this is
called streaming. The CSB can stall high between bytes to allow for
additional external timing. When CSB is tied high, SPI functions
are placed in high impedance mode. This mode turns on any
SPI pin secondary functions.
CONFIGURATION USING THE SPI
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits, as shown in Figure 54.
Three pins define the SPI of this ADC: SCLK, SDIO, and CSB
(see Table 14). The SCLK (a serial clock) is used to synchronize
the read and write data presented from and to the ADC. SDIO
(serial data input/output) is a dual-purpose pin that allows data to
be sent and read from the internal ADC memory map registers.
The CSB (chip select bar) is an active-low control that enables
or disables the read and write cycles.
All data is composed of 8-bit words. The first bit of the first byte
in a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. This allows the serial
data input/output (SDIO) pin to change direction from an input
to an output at the appropriate point in the serial frame.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Table 14. Serial Port Interface Pins
Pin
Function
SCLK Serial clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
SDIO Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Data can be sent in MSB-first mode or in LSB-first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
CSB
Chip select bar. An active-low control that gates the read
and write cycles.
tHIGH
tDS
tCLK
tH
tS
tDH
tLOW
CSB
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
Figure 54. Serial Port Interface Timing Diagram
Rev. C | Page 25 of 32
AD9609
Data Sheet
HARDWARE INTERFACE
CONFIGURATION WITHOUT THE SPI
The pins described in Table 14 constitute the physical interface
between the programming device of the user and the serial port
of the AD9609. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
In applications that do not interface to the SPI control registers,
the SDIO/PDWN pin and the SCLK/DFS pin serve as standalone
CMOS-compatible control pins. When the device is powered up, it
is assumed that the user intends to use the pins as static control
lines for the power-down and output data format feature control.
In this mode, connect the CSB chip select to DRVDD, which
disables the serial port interface.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Table 15. Mode Selection
External
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
Pin
SDIO/PDWN DRVDD
AGND (default)
DRVDD
AGND (default)
Voltage
Configuration
Chip power-down mode
Normal operation (default)
Twos complement enabled
Offset binary enabled
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9609 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
SCLK/DFS
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9609 part-specific features are described in
detail in Table 17.
SDIO/PDWN and SCLK/DFS serve a dual function when the
SPI interface is not being used. When the pins are strapped to
DRVDD or ground during device power-on, they are associated
with a specific function. The Digital Outputs section describes
the strappable functions supported on the AD9609.
Table 16. Features Accessible Using the SPI
Feature
Description
Modes
Allows the user to set either power-down mode
or standby mode
Clock
Offset
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the
converter offset
Test I/O
Allows the user to set test modes to have known
data on output bits
Output Mode Allows the user to set up outputs
Output Phase Allows the user to set the output clock polarity
Output Delay Allows the user to vary the DCO delay
VREF
Allows the user to set the reference voltage
Rev. C | Page 26 of 32
Data Sheet
AD9609
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
DEFAULT VALUES
Each row in the memory map register table (see Table 17)
contains eight bit locations. The memory map is roughly
divided into four sections: the chip configuration registers
(Address 0x00 to Address 0x02); the device index and transfer
register (Address 0xFF); the program registers, including setup,
control, and test (Address 0x08 to Address 0x2A); and the
AD9609-specific customer SPI control register (Address 0x101).
After the AD9609 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table (see Table 17).
Logic Levels
An explanation of logic level terminology follows:
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
Table 17 documents the default hexadecimal value for each
hexadecimal address shown. The column with the heading Bit 7
(MSB) is the start of the default hexadecimal value given. For
example, Address 0x2A, the OR/MODE select register, has a hexa-
decimal default value of 0x01. This means that in Address 0x2A,
Bits[7:1] = 0, and Bit 0 = 1. This setting is the default OR/MODE
setting. The default value results in the programmable external
MODE/OR pin (Pin 23) functioning as an out-of-range digital
output. For more information on this function and others, see the
AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
This application note details the functions controlled by Register
0x00 to Register 0xFF. The remaining register, Register 0x101, is
documented in the Memory Map Register Descriptions section
that follows Table 17.
•
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simulta-
neously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and then the bit autoclears.
OPEN LOCATIONS
All address and bit locations that are not included in the SPI map
are not currently supported for this device. Unused bits of a valid
address location should be written with 0s. Writing to these loca-
tions is required only when part of an address location is open
(for example, Address 0x2A). If the entire address location is
open, it is omitted from the SPI map (for example, Address 0x13)
and should not be written.
Rev. C | Page 27 of 32
AD9609
Data Sheet
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17.
Default
Value
(Hex)
Addr
(Hex)
Bit 7
(MSB)
Bit 0
(LSB)
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
Chip Configuration Registers
0x00
SPI port
configuration
0
LSB
first
1
1
Soft
LSB
first
0
0x18
The nibbles are
mirrored so that LSB
or MSB first mode
registers correctly,
regardless of shift
mode
Soft
reset1
reset1
0x01
0x02
Chip ID
8-bit chip ID, Bits[7:0]
AD9609 = 0x71
Read only
Read only
Unique chip ID used
to differentiate
devices; read only
Unique speed grade
ID used to
differentiate
Chip grade
Speed grade ID, Bits[6:4]
(identify device variants of
chip ID)
Open
Open
20 MSPS = 000
devices; read only
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011
Device Index and Transfer Register
0xFF
Transfer
Open
Open Open
Open
Open
Open Open
Open Open
Open
Transfer
0x00
0x00
Synchronously
transfers data from
the master shift
register to the slave
Program Registers
0x08
Modes
External
Pin 23
mode
External Pin 23
function when
high
00 = chip run
01 = full power-down
10 = standby
Determines various
generic modes of
chip operation
input
enable
00 = full power
down
11 = chip wide digital
reset
01 = standby
10 = normal
mode: output
disabled
11 = normal
mode: output
enabled
0x09
0x0B
Clock
Open
Open Open
Open
Open
Duty cycle
stabilize
0x01
0x00
Enable internal duty
cycle stabilizer (DCS)
The divide ratio is
the value plus 1
Clock divide
Clock divider, Bits[2:0]
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Open
0x0D
Test mode
User test mode
00 = single
01 = alternate
10 = single once
11 = alternate once
Reset
PN
long
gen
Reset
PN
short
gen
Output test mode, Bits[3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0x00
When set, the test
data is placed on
the output pins in
place of normal
data
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = 1/0 word toggle
1000 = user input
1001 = 1/0 bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
0x0E
BIST enable
Open
Open Open
Open
Open BIST
INIT
BIST enable
0x00
When Bit 0 is set,
the built in self-test
Open
Rev. C | Page 28 of 32
Data Sheet
AD9609
Default
Value
(Hex)
Addr
(Hex)
Bit 7
(MSB)
Bit 0
(LSB)
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
function is initiated.
0x10
0x14
Offset adjust
Output mode
8-bit device offset adjustment, Bits[7:0] (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)
0x00
0x00
Device offset trim
00 = 3.3 V CMOS
10 = 1.8 V CMOS
Open
Output
disable
Open Output
invert
00 = offset binary
01 = twos complement
10 = gray code
Configures the
outputs and the
format of the data
11 = offset binary
0x15
Output adjust
3.3 V DCO
1.8 V DCO
3.3 V data
1.8 V data
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
0x22
Determines CMOS
output drive
strength properties
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes
(default)
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
11 = 4 stripes
0x16
Output phase
DCO
Open Open
Open
Open
Input clock phase adjust, Bits[2:0]
(Value is number of input clock
cycles of phase delay)
0x00
On devices that
utilize global clock
divide, determines
which phase of the
divider output is
used to supply the
output clock;
Output
polarity
0 =
normal
1 =
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
inverted
internal latching is
unaffected
0x17
Output delay
Enable
DCO
delay
Open Enable
data
Open
DCO/data delay[2:0]
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
0x00
Sets the fine output
delay of the output
clock but does not
change internal
timing
delay
0x18
VREF
Reserved =11
Internal VREF adjustment,
Bits[2:0]
000 = 1.0 V p-p
001 = 1.14 V p-p
010 = 1.33 V p-p
011 = 1.60 V p-p
100 = 2.0 V p-p
Open
0xE0
Selects and/or
adjusts the VREF
full-scale span
0x19
0x1A
0x1B
0x1C
0x24
USER_PATT1_LSB
B7
B6
B5
B4
B3
B2
B1
B9
B1
B9
B0
B8
B0
B8
0x00
0x00
0x00
0x00
0x00
User-defined
pattern, 1 LSB
User-defined
pattern, 1 MSB
User-defined
pattern, 2 LSB
User-defined
pattern, 2 MSB
Least significant
byte of BIST
USER_PATT1_MSB B15
USER_PATT2_LSB B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
USER_PATT2_MSB B15
BIST signature LSB
B14
B13
B12
B11
B10
BIST signature, Bits[7:0]
signature, read only
0x2A
OR/MODE select
Open
Open Open
Open
Open
Open
Open
Open
0 = MODE
1 = OR
(default)
0x01
Selects I/O
functionality in
conjunction with
Address 0x08 for
MODE (input) or OR
(output) on external
Pin 23
1.1. AD9609-Specific Customer SPI Control
0x101 USR2
1
Open
Enable Run
GCLK
detect
Disable SDIO
pull-down
0x88
Enables internal
oscillator for clock
rates <5 MHz
GCLK
1 See the Soft Reset section for limitations on the use of soft reset.
Rev. C | Page 29 of 32
AD9609
Data Sheet
Bit 2—Run GCLK
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
This bit enables the GCLK oscillator. For some applications
with encode rates below 10 MSPS, it may be preferable to set
this bit high to supersede the GCLK detector.
USR2 (Register 0x101)
Bit 0—Disable SDIO Pull-Down
Bit 3—Enable GCLK Detect
This bit can be set high to disable the internal 30 kΩ pull-down
on the SDIO pin, which can be used to limit the loading when
many devices are connected to the SPI bus.
Normally set high, this bit enables a circuit that detects encode
rates below about 5 MSPS. When a low encode rate is detected,
an internal oscillator, GCLK, is enabled ensuring the proper
operation of several circuits. If set low, the detector is disabled.
Rev. C | Page 30 of 32
Data Sheet
AD9609
APPLICATIONS INFORMATION
To maximize the coverage and adhesion between the ADC and
the PCB, a silkscreen should be overlaid to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the ADC and the PCB during the reflow
process. Using one continuous plane with no partitions guarantees
only one tie point between the ADC and the PCB. For detailed
information about packaging and PCB layout of chip scale
packages, see the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP).
DESIGN GUIDELINES
Before starting design and layout of the AD9609 as a system, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9609, it is strongly
recommended that two separate supplies be used. Use one 1.8 V
supply for analog (AVDD); use a separate 1.8 V to 3.3 V supply for
the digital output supply (DRVDD). If a common 1.8 V AVDD
and DRVDD supply must be used, the AVDD and DRVDD
domains must be isolated with a ferrite bead or filter choke and
separate decoupling capacitors. Several different decoupling
capacitors can be used to cover both high and low frequencies.
Locate these capacitors close to the point of entry at the PCB
level and close to the pins of the part, with minimal trace length.
Encode Clock
For optimum dynamic performance a low jitter encode clock
source with a 50% duty cycle 5% should be used to clock the
AD9609.
VCM
The VCM pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 38.
A single PCB ground plane should be sufficient when using the
AD9609. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
RBIAS
The AD9609 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
When powering down the AD9609, power off AVDD and
DRVDD simultaneously, or DRVDD must be removed before
AVDD.
Reference Decoupling
Externally decoupled the VREF pin to ground with a low ESR, 1.0
μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor.
Exposed Paddle Thermal Heat Sink Recommendations
The exposed paddle (Pin 0) is the only ground connection for
the AD9609; therefore, it must be connected to analog ground
(AGND) on the customer’s PCB. To achieve the best electrical
and thermal performance, mate an exposed (no solder mask)
continuous copper plane on the PCB to the AD9609 exposed
paddle, Pin 0.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9609 to keep these signals from transitioning at the converter
inputs during critical sampling periods.
The copper plane should have several vias to achieve the
lowest possible resistive thermal path for heat dissipation to
flow through the bottom of the PCB. Fill or plug these vias
with nonconductive epoxy.
Soft Reset
In applications with DRVDD ≥ 2.75 V, do not perform soft reset
(Register 0x00 Bit 2 and Bit 5 = 1). Soft reset restores AD9609
defaults already available at power-up and is not needed.
Rev. C | Page 31 of 32
AD9609
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
AREA
PIN 1
25
32
IONS
INDICATOR AR EA OP T
(SEE DETAIL A)
24
1
0.50
BSC
3.65
EXPOSED
PAD
3.50 SQ
3.45
8
17
9
16
0.50
0.40
0.30
0.20 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
3.50 REF
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
SECTION OF THIS DATA SHEET.
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD
Figure 55. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature Range
Package Description
Package Option
CP-32-11
CP-32-11
CP-32-11
CP-32-11
CP-32-11
CP-32-11
CP-32-11
CP-32-11
AD9609BCPZ-80
AD9609BCPZRL7-80
AD9609BCPZ-65
AD9609BCPZRL7-65
AD9609BCPZ-40
AD9609BCPZRL7-40
AD9609BCPZ-20
AD9609BCPZRL7-20
AD9609-80EBZ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
AD9609-65EBZ
Evaluation Board
AD9609-40EBZ
Evaluation Board
AD9609-20EBZ
Evaluation Board
1 Z = RoHS Compliant Part.
2 For the AD9609BCPZ models, the exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND.
©2009–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08541-0-11/18(C)
Rev. C | Page 32 of 32
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