AD9623AR [ADI]

IC OP-AMP, 10000 uV OFFSET-MAX, 270 MHz BAND WIDTH, PDSO8, SOIC-8, Operational Amplifier;


型号：	AD9623AR
厂家：	ADI
描述：	IC OP-AMP, 10000 uV OFFSET-MAX, 270 MHz BAND WIDTH, PDSO8, SOIC-8, Operational Amplifier 放大器光电二极管
文件：	总6页 (文件大小：139K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Wideband Voltage

Feedback Amplifier

AD9623*

CO NNECTIO N D IAGRAM

FEATURES

270 MHz Sm all Signal Bandw idth

190 MHz Large Signal BW (4 V p-p)

High Slew Rate: 2100 V/ ␮s

Low Distortion: –64 dB @ 20 MHz

Fast Settling: 15 ns to 0.01%

2.6 nV/ √Hz Spectral Noise Density

؎3 V Supply Operation

NC #

–INPUT

+INPUT

OUTPUT

–V

AD9623

APPLICATIONS

ADC Input Driver

Differential Am plifiers

IF/ RF Am plifiers

# OPTIONAL CAPACITOR CB CONNECTED HERE

DECREASES SETTLING TIME (SEE TEXT).

Pulse Am plifiers

Professional Video

DAC Current-to-Voltage

Baseband and Video Com m unications

Active Filters/ lntegrators/ Log Am ps

Other members of the AD962X amplifier family are the

AD9621 (G = +1), AD9622 (G = +2), and the AD9624

(G = +6). A separate data sheet is available from Analog

Devices for each model. Each generic device has been designed

for a different minimum stable gain setting, allowing users flex-

ibility in optimizing system performance. Dynamic performance

specifications such as slew rate, settling time, and distortion vary

from model to model. T he table below summarizes key perfor-

mance attributes for the AD962X family and can be used as a

selection guide.

GENERAL D ESCRIP TIO N

T he AD9623 is one of a family of very high speed and wide

bandwidth amplifiers utilizing a voltage feedback architecture.

T hese amplifiers define a new level of performance for voltage

feedback amplifiers, especially in the categories of large signal

bandwidth, slew rate, settling, low distortion, and low noise.

Proprietary design architectures have resulted in an amplifier

family that combines the most attractive attributes of both cur-

rent feedback and voltage feedback amplifiers. T he AD9623

exhibits extraordinarily accurate and fast pulse response charac-

teristics (8 ns settling to 0.1%) as well as extremely wide small

and large signal bandwidth previously found only in current

feedback amplifiers. When combined with balanced high imped-

ance inputs and low input noise current more common to volt-

age feedback architectures, the AD9623 offers performance not

previously available in a monolithic operational amplifier.

T he AD9623 is offered in industrial and military temperature

ranges. Industrial versions are available in plastic DIP, SOIC,

and cerdip; MIL versions are packaged in cerdips.

P RO D UCT H IGH LIGH TS

1. Wide Large Signal Bandwidth

2. High Slew Rate

3. Fast Settling

4. Low Distortion

*P r otected by U.S. P atent 5,150,074 and other s pending.

5. Output Short-Circuit Protected

6. Low Intermodulation Distortion of High Frequencies

P aram eter

AD 9621

AD 9622

AD 9623

AD 9624

Units

Minimum Stable Gain

V/V

MHz

V/µs

Harmonic Distortion (20 MHz)

Large Signal Bandwidth (4 V p-p)

SSBW (0.5 V p-p)

–52

130

350

1200

2.4

–66

160

220

1500

1.7

–64

190

270

2100

1.6

–66

200

300

2200

1.5

Slew Rate

Rise/Fall T ime (0.5 V Step)

Settling T ime (to 0.1%/0.01%)

Input Noise (0.1 MHz – 200 MHz)

7/11

8/14

µV rms

REV. 0

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700 Fax: 617/ 326-8703

AD9623–SPECIFICATIONS

DC ELECTRICAL CHARACTERISTICS ^{(؎V = ؎5 V, R}_LOAD= 100 ⍀; A = +4; R = 270 ⍀, unless otherwise noted)

Test

AD 9623AN/AQ/AR

AD 9623SQ

Typ Max Units

P aram eter

Conditions

Tem p

Level

Min

Typ Max

Min

DC SPECIFICAT IONS¹

Input Offset Voltage

+25°C

Full

+25°C

Full

+25°C

Full

–8

–10

±2

+10

–8

–10

±2

+10 mV

Input Bias Current

µA

nA/°C

µA

Bias Current T C

Input Offset Current

±0.3 +2

2.0

600

±0.3 +2

2.0

600

–2

–3

–2

–3

µA

Offset Current T C

Input Resistance

Input Capacitance

Common-Mode Range

Common-Mode Rejection Ratio

Open-Loop Gain

Output Voltage Range

Output Current

Full

nA/°C

kΩ

+25°C

Full

+25°C

Full

1.2

±3.0 ±3.4

∆V_CM= 1 V

V_OUT= ±2 V p-p

Ω

±3.0 ±3.4

Full

+25°C

0.3

Output Resistance

FREQUENCY DOMAIN

Bandwidth (–3 dB)

Small Signal

Large Signal

V_OUT= 0.4 V p-p

V_OUT= 4 V p-p

Full Spectrum

DC to 100 MHz

0.3 to 100 MHz

2 V p-p; 20 MHz

@ 20 MHz

Full

+25°C

Full

+25°C

Full

190

270

190

0.1

190

270

190

0.1

MHz

Degree

Amplitude of Peaking

Amplitude of Roll-off

Phase Nonlinearity

2nd Harmonic Distortion

3rd Harmonic Distortion

Common-Mode Rejection Ratio

Spectral Input Noise Voltage

Spectral Input Noise Current

Average Equivalent Integrated

Input Noise Voltage

1.2

0.7

1.2

0.7

1.0

–64 –56

–72 –65

+21

2.6

2.5

–64 –56 dBc

–72 –65 dBc

+21

2.6

2.5

Full

+25°C

1 to 200 MHz

nV/

√

pA/√

0.1 to 200 MHz

+25°C

µV rms

T IME DOMAIN

Slew Rate

Rise/Fall T ime

V_OUT= 5 V Step

V_OUT= 0.5 V Step +25°C

V_OUT= 5 V Step

V_OUT= 2 V Step

Full

1500 2100

V/µs

1.6

2.4

1.6

2.4

Full

3.1

Overshoot

Settling T ime

T o 0.1%

V_OUT= 2 V Step

V_OUT= 4 V Step

2ϫ to ±2 mV

R_L= 150 Ω

+25°C

Full

150

0.01

<0.01

150

0.01

<0.01

Degree

T o 0.01%

T o 0.1%²

+25°C

T o 0.01%²

Overdrive Recovery

Differential Gain (4.3 MHz)

Differential Phase (4.3 MHz)

R_L= 150 Ω

POWER SUPPLY REQUIREMENT S¹

Supply Voltage (±V_S)

Quiescent Current

+I_S

–I_S

Full

3.0

5.0

5.5

3.0

5.0

5.5

+V_S= +5 V

–V_S= –5 V

∆V_S= 1 V

Full

+25°C

Power Supply Rejection Ratio

NOT ES

¹Measured at A_V= 21.

²Measured with a 0.001 µF C_Bcapacitor connected across Pins 1 and 8.

Specifications subject to change without notice.

–2–

REV. 0

AD9623

ABSO LUTE MAXIMUM RATINGS¹

TH EO RY O F O P ERATIO N

Supply Voltages (±V_S) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6 V

Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±V_S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

Continuous Output Current². . . . . . . . . . . . . . . . . . . . . 90 mA

Operating T emperature Ranges

AN, AQ, AR . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

SQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Storage T emperature

T he AD9623 is a wide bandwidth voltage feedback amplifier

that is guaranteed for minimum gain stability of +4. Since its

open-loop frequency response follows the conventional 6 dB/

octave roll-off, its gain bandwidth product is basically constant.

Increasing its closed-loop gain results in a corresponding de-

crease in small signal bandwidth. T he AD9623 typically main-

tains a 60 degree unity loop gain phase margin. T his high

margin minimizes the effects of signal and noise peaking.

Ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C

Junction T emperature

Feedback Resistor Choice

At minimum stable gain (+4), the AD9623 provides optimum

dynamic performance with R_F390 Ω. When using this value

and following the high speed layout guidelines, a shunt capacitor

(C_F) should not be required. T his value for R_Fprovides the best

combination of wide bandwidth, low peaking, and distortion.

Ceramic³. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C

Plastic³. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Lead Soldering T emperature (1 minute)⁴. . . . . . . . . . +220°C

NOT ES

¹Absolute maximum ratings are limiting values to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional

operability is not necessarily implied. Exposure to absolute maximum rating

conditions for an extended period of time may affect device reliability.

²Output is short-circuit protected; for maximum reliability, 90 mA continuous

current should not be exceeded.

However, if improved gain flatness is desired, a shunt capacitor

(C_F) will provide extra phase margin. T his reduces both over-

shoot and peaking with only a slight reduction of bandwidth.

See Figure 1.

As an example, if the amplifier exhibits (worst case) peaking of

1 dB with R_GʈR_F= 98 Ω (A_V= 4), then using an effective C_Fof

≈ 0.5–1 pF across R_Fwill reduce this peaking to 0 dB. In addition,

overshoot, noise, and settling time (0.01%) will also improve.

T his comes at the expense of slightly decreased closed-loop

bandwidth due to the R_Fϫ C_Ftime constant created.

³T ypical thermal impedances (part soldered onto board; no air flow):

Ceramic DIP: θ_JA= 100°C/W; θ_JC= 30°C/W

Plastic SOIC: θ_JA= 125°C/W; θ_JC= 45°C/W

Plastic DIP:

θ_JA= 90°C/W; θ_JC= 45°C/W

⁴T emperature shown is for surface mount devices, mounted by vapor phase

soldering. T hroughhole devices (ceramic and plastic DIPs) can be soldered at

+300°C for 10 seconds.

If total input capacitance greatly exceeds 3 pF (due to source

drive or long input traces to the amplifier), then added shunt

capacitance (C_F) will be necessary to maintain stability for

minimum gain.

O RD ERING GUID E

Tem perature

Range

P ackage

D escription

P ackage

O ption

Model

Likewise, if larger R_G/R_Fminimum-gain setting resistors are

used, C_Fwill be necessary. As a rule of thumb, if the product of

R_FʈR_Gϫ C_I≤ 300 ϫ 10^–12seconds, then C_Fis not required (for

maximum bandwidth at minimum gain) and the amplifier’s

phase margin will maintain about 60°.

AD9623AN

AD9623AQ

AD9623AR

AD9623SQ

–40°C to +85°C

8-Pin Plastic DIP N-8

8-Pin Cerdip

8-Pin SOIC

Q-8

R-8

Q-8

–55°C to +125°C 8-Pin Cerdip

For R_FʈR_G>150 Ω, use a C_Fequal to C_Iϫ R_G/R_F. For C_I

(total) @ 2 pF, requires C_Fto be 0.5 pF. T his can be achieved

by two 1 pF capacitors in series, or by using a resistor divider

network at the amplifier’s output in conjunction with a larger

capacitor. Increasing C_Fmuch beyond these guidelines will also

cause amplifier instability.

EXP LANATIO N O F TEST LEVELS

Test Level

– 100% production tested.

II – 100% production tested at +25°C, and sample tested at

specified temperatures. AC testing of “A” grade devices

done on sample basis.

III – Sample tested only.

IV – Parameter is guaranteed by design and characterization

testing.

P ulse Response

Unlike a traditional voltage feedback amplifier in which slew

speed is usually dictated by its front end dc quiescent current

and gain bandwidth product, the AD9623 provides “on de-

mand” transconductance current that increases proportionally

to the input “step” signal amplitude. T his results in slew speeds

(2100 V/µs) comparable to wideband current feedback designs.

T his, combined with relatively low input noise current

– Parameter is a typical value only.

VI – All devices are 100% production tested at +25°C. 100%

production tested at temperature extremes for extended

temperature devices; sample tested at temperature ex-

tremes for commercial/industrial devices.

(2.5 pA/√Hz), gives the AD9623 the best attributes of both volt-

age and current feedback amplifiers.

OUTPUT

Bootstr ap Capacitor (C_B)

54mils

In most applications, the C_Bcapacitor should not be required.

Under certain conditions, it can be used to further enhance set-

tling time performance.

– INPUT

CB+

–V

46.5mm

CB–

–INPUT +INPUT

46.5mils

Chip Layout

REV. 0

–3–

AD9623

6.8µF

0.1µF

(OPTIONAL)

OUT

500

Ω

0.1µF

500

Ω

–R

= 1+

OUT

6.8µF

–V

Figure 1. Transim pedance

Configuration

Figure 2. Inverting Gain Connection

Diagram

Figure 3. Noninverting Gain Connection

Diagram

Layout Consider ations

T he C_Bcapacitor (0.001 µF) connects to the internal high im-

pedance nodes of the amplifier. Using this capacitor will reduce

the large signal (4 V) step output settling time by 3 ns to 5 ns

for 0.05% or greater accuracy. For settling accuracy less than

0.05% or for smaller step sizes, its effect will be less apparent.

As with all wide bandwidth components, printed circuit layout

is critical to obtain best dynamic performance with the AD9623.

T he ground plane in the area of the amplifier and its associated

components should cover as much of the component side of the

board as possible (or first interior layer of a multilayer surface

mount board).

Under heavy slew conditions, this capacitor forces the internal

signal (initial step) amplitude to be controlled by the “on”

(slewed) transistor, preventing its complement from completely

turning off. T his allows for faster settling time of these (internal)

nodes and thus, the output also.

T he ground plane should be removed in the area of the inputs

and R_Fand R_Gto minimize stray capacitance at the input. T he

same precaution should be used for C_B, if used. Each power

supply trace should be decoupled close to the package with a

0.1 µF ceramic capacitor, plus a 6.8 µF tantalum nearby.

In the frequency domain, total (high frequency) distortion will

be approximately the same with or without C_B. T ypically, the

3rd harmonic will be greater than the 2nd without C_B. T his will

be reversed with C_Bin place.

All lead lengths for input, output, and feedback resistor should

be kept as short as possible. All gain setting resistors should be

chosen for low values of parasitic capacitance and inductance,

i.e., microwave resistors and/or carbon resistors.

AP P LICATIO NS

T he AD9623 is a voltage feedback amplifier and is well suited

for such applications as active filters, and log amplifiers. T he

device’s wide bandwidth (270 MHz), phase margin (60°), low

noise current (2.6 pA /√Hz), and slew rate (2100 V/µs) give

higher performance capabilities to these applications over previ-

ous voltage feedback designs.

Microstrip techniques should be used for lead lengths in excess

of one inch. Sockets should be avoided if at all possible because

of their high series inductance. If sockets are necessary, indi-

vidual pin sockets such as AMP p/n 6-330808-3 should be used.

T hese contribute far less stray reactance than molded socket

assemblies.

Its settling time of 15 ns to 0.01% and 8 ns to 0.1%, and its low

harmonic distortion make it a good for choice for ADC signal

amplification. With superb linearity at relatively high signal fre-

quencies, it is an ideal driver for ADCs up to 14 bits.

An evaluation board is available from Analog Devices for a

nominal charge.

–4–

REV. 0

AD9623

Typical Performance ^{(R = 100 Ω; A = +4, unless otherwise noted)}

–

+90

+180

GAIN

+75

+60

+135

+90

+45

+135

+90

–2

–4

–6

–8

–2

–4

–6

–8

= –3

+45

+30

+15

+45

PHASE

= 6

= 4

–45

–90

–135

–180

–45

–90

–15

–30

–135

–180

= 6,12

= –6

–45

–60

= 12

–20

10k

100k

10M

100M

600M

50 100 150 200 250 300 350 400 450 500

FREQUENCY – MHz

100 150 200 250 300 350 400 450 500

FREQUENCY – MHz

FREQUENCY – Hz

Figure 4. Open-Loop Gain and Phase

Figure 5. Inverting Frequency

Response

Figure 6. Noninverting Frequency

Response

+20

+25

+30

–50

= 2Vp-p

OUT

–60

–70

–80

2nd HARMONIC

= 100Ω

+35

+40

2nd HARMONIC

= 500

Ω

+45

+50

–90

–100

–110

–120

3rd HARMONIC

OUT

Ω

= 100

+55

3rd HARMONIC

+60

CMRR

Ω

= 500

+65

PSRR

+70

10 100 1k 10k 100k 1M 10M 100M 1G

FREQUENCY – Hz

40 60

100

FREQUENCY – MHz

Figure 7. Harm onic Distortion

vs. Frequency

Figure 8. Third Order Intercept

Figure 9. CMRR and PSRR vs.

Frequency

+180

+0.1

AV = 4

_FB= 390

R_FF= 130

+135

+90

+0.08

+0.06

TEST CIRCUIT

100

+0.08

+0.06

V_OUT= 2V STEP

Ω

–2

–4

–6

Ω

6pF

+45

+0.04

+0.02

+0.04

+0.02

Ω

R_LOAD= 500

–45

–90

–0.02

TEST CIRCUIT

100

–135

–180

–0.04

–0.06

–0.04

–0.06

V_OUT= 2V STEP

Ω

6pF

R_LOAD= 50

Ω

–0.08

–0.1

–0.08

–0.1

–8

10K

100K

50 100 150 200 250 300 350 400 450 500

FREQUENCY – MHz

100

TIME – ns

Figure 10. Frequency Response

vs. R_LOAD

Figure 11. Short-Term Settling Tim e

Figure 12. Long-Term Settling Tim e

VOLTAGE

R_S

C_L

390

130

CURRENT

t_SETTLING

VOLTAGE

CURRENT

C_LOAD– pF

100

FREQUENCY – Hz

3.5

4.0

4.5

5.0

5.5

SUPPLY VOLTAGE – ±Volts

Figure 13. Input Spectral Noise

Density

Figure 14. Output Level and Sup-

ply Current vs. Supply Voltage

Figure 15. Settling Tim e vs.

Capacitive Load

REV. 0

–5–

AD9623

0.2V

TO 0.01%

_LOAD= 100

_OUT= 2V_p-p

Ω

R_LOAD= 100Ω

_OUT= 5V_p-p

Ω

= 100

LOAD

= 0.4V

OUT

p-p

–2V

–0.2V

INPUT RISE/FALL TIME = 1.6ns

5ns/DIV

INPUT RISE/FALL TIME = 1.6ns

5ns/DIV

NONINVERTING GAIN

Figure 16. Large Signal Pulse

Response

Figure 17. Sm all Signal Pulse

Response

Figure 18. Settling Tim e vs.

Noninverting Gain

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

P lastic D IP (Suffix N)

Cer dip (Suffix Q )

0.005 (0.13) MIN

0.055 (1.4) MAX

0.240 (6.096)

0.260 (6.604)

PIN 1

0.310 (7.87)

0.220 (5.59)

0.290 (7.366)

0.310 (7.874)

0.360 (9.144)

0.400 (10.16)

0.320 (8.13)

0.290 (7.37)

0.405 (10.29) MAX

0.120 (3.048)

0.140 (3.556)

0.200

(5.08)

MAX

0.060 (1.52)

0.015 (0.38)

0.200

(5.08)

MAX

0.140

(3.556)

MIN

0.015 (0.38)

0.008 (0.20)

0.015 (0.381)

0.008 (0.204)

0.150

(3.81)

MIN

0.200 (5.08)

0.125 (3.18)

0.045 (1.143)

0.065 (2.667)

0.016 (0.406)

0.020(0.508)

0°-15°

0.070 (1.78)

0.030 (0.76)

0° TO 15°

0.023 (0.58)

0.014 (0.36)

SEATING

PLANE

0.100

(2.54)

0.100

(2.54)

BSC

SEATING

PLANE

P lastic SO IC (Suffix R)

0.196 (5.00)

0.188 (4.75)

0.158 (4.00)

0.150 (3.80)

0.244 (6.20)

0.228 (5.80)

0.050

(1.27)

TYP

0.018 (0.46)

0.014 (0.36)

0.206 (5.20)

0.181 (4.60)

0.069 (1.75)

0.053 (1.35)

0.045 (1.15)

0.020 (0.50)

0.010 (0.25)

0.004 (0.10)

0.015 (0.38)

0.007 (0.18)

–6–

REV. 0

AD9623AR [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E