AD9623 [ADI]
Wideband Voltage Feedback Amplifier; 宽带电压反馈放大器
| 型号： | AD9623 |
| 厂家： | 
ADI |
| 描述： | Wideband Voltage Feedback Amplifier |
| 文件： | 总6页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wideband Voltage
Feedback Amplifier
a
AD9621*
CONNECTION DIAGRAM
FEATURES
350 MHz Small Signal Bandwidth
130 MHz Large Signal BW (4 V p-p)
High Slew Rate: 1200 V/s
Fast Settling: 11 ns to 0.01%/7 ns to 0.1%
؎3 V Supply Operation
1
2
3
4
8
7
6
5
NC #
–INPUT
+INPUT
NC #
+V
S
OUTPUT
NC
APPLICATIONS
ADC Input Driver
–V
S
AD9621
Differential Amplifiers
IF/RF Amplifiers
# OPTIONAL CAPACITOR CB CONNECTED HERE
DECREASES SETTLING TIME
Pulse Amplifiers
Professional Video
DAC Current-to-Voltage
Baseband and Video Communications
Pin Diode Receivers
Active Filters/lntegrators/Log Amps
GENERAL DESCRIPTION
Other members of the AD962X amplifier family are the
AD9622 (G = +2), AD9623 (G = +4), and the AD9624
(G = +6). A separate data sheet is available from Analog De-
vices for each model. Each generic device has been designed for
a different minimum stable gain setting, allowing users flexibility
in optimizing system performance. Dynamic performance speci-
fications such as slew rate, settling time, and distortion vary
from model to model. The table below summarizes key perfor-
mance attributes for the AD962X family and can be used as a
selection guide.
The AD9621 is one of a family of very high speed and wide
bandwidth amplifiers utilizing a voltage feedback architecture.
These amplifiers define a new level of performance for voltage
feedback amplifiers, especially in the categories of large signal
bandwidth, slew rate, settling, and low noise.
Proprietary design architectures have resulted in an amplifier
family that combines the most attractive attributes of both cur-
rent feedback and voltage feedback amplifiers. The AD9621 ex-
hibits extraordinarily accurate and fast pulse response
characteristics (7 ns settling to 0.1%) as well as extremely wide
small and large signal bandwidth previously found only in cur-
rent feedback amplifiers. When combined with balanced high
impedance inputs and low input noise current more common to
voltage feedback architectures, the AD9621 offers performance
not previously available in a monolithic operational amplifier.
The AD9621 is offered in industrial and military temperature
ranges. Industrial versions are available in plastic DIP, SOIC,
and cerdip; MIL versions are packaged in cerdips.
PRODUCT HIGHLIGHTS
1. Wide Large Signal Bandwidth
2. High Slew Rate
*Protected by U.S. Patent 5,150,074 and others pending.
3. Fast Settling
4. Output Short-Circuit Protected
Parameter
AD9621
AD9622
AD9623
AD9624
Units
Minimum Stable Gain
+1
+2
+4
+6
V/V
dB
MHz
MHz
V/µs
ns
Harmonic Distortion (20 MHz)
Large Signal Bandwidth (4 V p-p)
SSBW (0.5 V p-p)
–52
130
350
1200
2.4
–66
160
220
1500
1.7
–64
190
270
2100
1.6
–66
200
300
2200
1.5
Slew Rate
Rise/Fall Time (0.5 V Step)
Settling Time (to 0.1%/0.01%)
Input Noise (0.1 MHz – 200 MHz)
7/11
80
8/14
49
8/14
36
8/14
32
ns
µV rms
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD9621–SPECIFICATIONS
DC ELECTRICAL CHARACTERISTICS (؎VS = ؎5 V, RLOAD = 100 Ω; AV = 1, unless otherwise noted)
Test
AD9621AN/AQ/AR
AD9621SQ
Parameter
Conditions
Temp Level
Min
Typ Max Min Typ Max Units
DC SPECIFICATIONS1
Input Offset Voltage
+25°C
Full
+25°C
Full
Full
+25°C
Full
I
VI
I
–12
–15
±2
7
+12
+15
16
–12
–15
±2
7
+12 mV
+15 mV
Input Bias Current
16
+20 µA
nA/°C
µA
VI
V
I
VI
V
V
V
VI
I
V
VI
VI
V
–20
+20
–20
Input Bias Current TC
Input Offset Current
35
35
–2.0 ±0.3 +2.0 –2.0
–3.0 +3.0 –3.0
+2.0 µA
+3.0 µA
Offset Current TC
Input Resistance
Input Capacitance
Common-Mode Range
Common-Mode Rejection Ratio
Open Loop Gain
Output Voltage Range
Output Current
Full
2.5
500
1.2
2.5
500
1.2
nA/°C
+25°C
+25°C
Full
+25°C
+25°C
Full
kΩ
pF
V
dB
dB
V
±3.0 ±3.4
46
±3.0 ±3.4
46
∆VCM = 1 V
49
56
49
56
V
OUT = ±2 V p-p
±3.0 ±3.4
60
±3.0 ±3.4
60
Full
+25°C
70
0.3
70
0.3
mA
Ω
Output Resistance
FREQUENCY DOMAIN
Bandwidth (–3 dB)
Small Signal
Large Signal
V
V
OUT ≤ 0.4 V p-p
OUT ≤ 4.0 V p-p
Full
Full
Full
Full
+25°C
Full
Full
+25°C
+25°C
+25°C
II
V
II
II
V
II
II
V
V
V
230
350
130
0.1
0
230
350
130
0.1
0
MHz
MHz
dB
dB
Degree
Amplitude of Peaking
Amplitude of Roll-off
Phase Nonlinearity
2nd Harmonic Distortion
3rd Harmonic Distortion
Common-Mode Rejection Mode
Spectral Input Noise Voltage
Spectral Input Noise Current
Average Equivalent Integrated
Input Noise Voltage
Full Spectrum
≤ 100 MHz
DC to 100 MHz
2 V p-p; 20 MHz
2 V p-p; 20 MHz
@ 20 MHz
1.2
0.6
1.2
0.6
1.1
1.1
–55 –44
–52 –43
+28
5.6
3.6
–55 –44 dBc
–52 –43 dBc
+28
5.6
3.6
dB
nV/√Hz
pA/√Hz
1 to 200 MHz
1 to 200 MHz
0.1 to 200 MHz
+25°C
V
80
80
µV rms
TIME DOMAIN
Slew Rate
Rise/Fall Time
V
V
V
V
OUT = 5 V Step
OUT = 0.5 V Step +25°C
OUT = 5 V Step
OUT = 2 V Step
Full
IV
V
IV
IV
850
1200
2.4
4.8
0
850
1200
2.4
4.8
0
V/µs
ns
ns
Full
Full
7
15
7
15
Overshoot
%
Settling Time
To 0.1%
V
V
OUT = 2 V Step
OUT = 2 V Step
+25°C
Full
V
IV
V
V
V
V
V
7
11
9
13
50
0.01
<0.01
7
11
9
13
50
0.01
<0.01
ns
ns
ns
ns
ns
%
Degree
To 0.01%
15
15
To 0.1%2
VOUT = 4 V Step
VOUT = 4 V Step
1.5x to ±2 mV
RL = 150 Ω
+25°C
+25°C
+25°C
+25°C
+25°C
T0 0.012
Overdrive Recovery
Differential Gain (4.3 MHz)
Differential Phase (4.3 MHz)
RL = 150 Ω
POWER SUPPLY REQUIREMENTS1
Supply Voltage (±VS)
Quiescent Current
+IS
–IS
Full
IV
3.0
54
5.0
5.5
3.0
54
5.0
5.5
V
+VS = +5 V
–VS = –5 V
∆VS = 0.5 V
Full
Full
+25°C
VI
VI
I
23
23
66
29
29
23
23
66
29
29
mA
mA
dB
Power Supply Rejection Ratio
NOTES
1Measured at AV = 21.
2Measured with a 0.001 µF CB capacitor connected across Pins 1 and 8.
Specifications subject to change without notice.
–2–
REV. 0
AD9621
ABSOLUTE MAXIMUM RATINGS1
THEORY OF OPERATION
Supply Voltages (±VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6 V
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .6 V
Continuous Output Current2 . . . . . . . . . . . . . . . . . . . . . 90 mA
Operating Temperature Ranges
AN, AQ, AR . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
SQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature
The AD9621 is a wide bandwidth, unity gain stable voltage
feedback amplifier. Since its open-loop frequency response fol-
lows the conventional 6 dB/octave roll-off, its gain bandwidth
product is basically constant. Increasing its closed-loop gain re-
sults in a corresponding decrease in small signal bandwidth. The
AD9621 typically maintains a 55 degree unity loop gain phase
margin. This high margin minimizes the effects of signal and
noise peaking.
Ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C
Junction Temperature
Feedback Resistor Choice
At minimum stable gain (+1), the AD9621 provides optimum
dynamic performance with RF 51 Ω. This resistor acts only as
a parasitic suppressor against damped RF oscillations that can
occur due to lead (input, feedback) inductance and parasitic ca-
pacitance. For settling accuracy to 0.1% or less, this resistor
should not be required if layout guidelines are closely followed.
This value for RF provides the best combination of wide band-
width, low parasitic peaking, and fast settling time.
Ceramic3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Plastic3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Soldering Temperature (1 minute)4 . . . . . . . . . . +220°C
NOTES
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2Output is short-circuit protected; for maximum reliability, 90 mA continuous
current should not be exceeded.
When the AD9621 is used in the transimpedance (I-to-V)
mode, such as for photo-diode detection, the value for RF and
diode capacitance (CI) are usually known. See Figure 1. Gener-
ally, the value of RF selected will be in the kΩ range, and a shunt
capacitor (CF) across RF will be required to maintain good am-
plifier stability. The value of CF required to maintain < 1 dB of
peaking can be estimated as:
3Typical thermal impedances (part soldered onto board; no air flow):
Ceramic DIP: θJA = 100°C/W; θJC = 30°C/W
Plastic SOIC: θJA = 125°C/W; θJC = 45°C/W
Plastic DIP:
θJA = 90°C/W; θJC = 45°C/W
4Temperature shown is for surface mount devices, mounted by vapor phase
soldering. Throughhole devices (ceramic and plastic DIPs) can be soldered at
+300°C for 10 seconds.
2
CF [(2ωοCI RF −1)ωο2RF
]
1 2
ORDERING GUIDE
|
RF ≥1kΩ
Temperature
Range
Package
Description
Package
Option
Model
where ωo is equal to the unity gain bandwidth product of the
amplifier in RAD/sec, and CI is the equivalent total input ca-
pacitance at the inverting input. Typically ωo is 700 × 106
RAD/sec (See Open Loop Frequency Response curve).
AD9621AN –40°C to +85°C
AD9621AQ –40°C to +85°C
8-Pin Plastic DIP N-8
8-Pin Cerdip
8-Pin SOIC
Q-8
R-8
Q-8
AD9621AR
AD9621SQ
–40°C to +85°C
As an example, choosing RF of 10 kΩ and CI of 5 pF, requires
CF to be 1.1 pF (Note: CI includes both the source and parasitic
circuit capacitance). The bandwidth of the amplifier can be esti-
mated using the CF calculated as:
–55°C to +125°C 8-Pin Cerdip
EXPLANATION OF TEST LEVELS
Test Level
I
– 100% production tested.
1. 6
2 π RF C F
f3 dB
II – 100% production tested at +25°C, and sample tested at
specified temperatures. AC testing of “A” grade devices
done on sample basis.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
For general voltage gain applications, the amplifier bandwidth
can be estimated as:
ωο
f3 dB
V
– Parameter is a typical value only.
RF
RG
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
1+
This estimation loses accuracy for gains approaching +2/–1 or
lower due to the amplifier’s damping factor. For these “low
gain” cases, the bandwidth will actually extend beyond the cal-
culated value. See Closed Loop BW plots.
OUTPUT
+V
S
As a rule of thumb, capacitor CF will not be required if:
54mils
CB+
–V
S
NG
4ωο
R
RG C ≤
(
)
F
I
CB–
–INPUT +INPUT
46.5mils
where NG is the Noise Gain (l + RF/RG) of the circuit. For most
voltage gain applications, this should be the case.
Chip Layout
REV. 0
–3–
AD9621
+V
+V
S
S
6.8µF
6.8µF
0.1µF
0.1µF
R
R
G
7
4
7
4
F
3
2
3
2
C
(OPTIONAL)
C (OPTIONAL)
B
8
8
V
B
IN
6
6
V
V
OUT
OUT
C
C
F
F
1
1
R
G
V
IN
RF
R
R
F
F
0.1µF
0.1µF
R
500Ω
500Ω
G
CF
–R
R
R
R
F
F
A
=
A
= 1+
V
V
G
G
VOUT
CI
6.8µF
6.8µF
–V
–V
S
S
Figure 1. Transimpedance
Configuration
Figure 2. Inverting Gain Connection
Diagram
Figure 3. Noninverting Gain Connection
Diagram
phase margin (55°), low noise current (3.6 pA/√Hz), and slew
Pulse Response
rate (1200 V/µs) give higher performance capabilities to these
Unlike a traditional voltage feedback amplifier in which slew
speed is dictated by its front end dc quiescent current and gain
bandwidth product, the AD9621 provides “on demand” trans-
conductance current that increases proportionally to the input
“step” signal amplitude. This results in slew speeds (1200 V/µs)
comparable to wideband current feedback designs. This, com-
bined with relatively low input noise current (3.6 pA/√Hz), gives
the AD9621 the best attributes of both voltage and current feed-
back amplifiers.
applications over previous voltage feedback designs.
With a settling time of 11 ns to 0.01% and 7 ns to 0.1%, the de-
vice is an excellent choice for DAC I/V conversion. The same
characteristics, along with low harmonic distortion, make it a
good choice for ADC buffering/amplification. With its superb
linearity at relatively high signal frequencies, it is an ideal driver
for ADCs up to 14 bits.
Layout Considerations
Bootstrap Capacitor (CB)
As with all wide bandwidth components, printed circuit layout
is critical to obtain best dynamic performance with the AD9621.
The ground plane in the area of the amplifier and its associated
components should cover as much of the component side of the
board as possible (or first interior layer of a multi layer surface
mount board).
In most applications, the CB capacitor will not be required.
Under certain conditions, it can be used to further enhance set-
tling time performance.
The CB capacitor (0.001 µF) connects to the internal high im-
pedance nodes of the amplifier. Using this capacitor will reduce
the large signal (4 V) step output settling time by 3 to 5 ns for
0.05% or greater accuracy. For settling accuracy less than
0.05% or for smaller step sizes, its effect will be less apparent.
The ground plane should be removed in the area of the inputs
and RF and RG to minimize stray capacitance at the input. The
same precaution should be used for CB, if used. Each power
supply trace should be decoupled close to the package with a
0.1 µF ceramic capacitor, plus a 6.8 µF tantalum nearby.
Under heavy slew conditions, this capacitor forces the internal
signal (initial step) amplitude to be controlled by the “on”
(slewed) transistor, preventing its complement from completely
turning off. This allows for faster settling time of these internal
nodes and also the output.
All lead lengths for input, output, and feedback resistor should
be kept as short as possible. All gain setting resistors should be
chosen for low values of parasitic capacitance and inductance,
i.e., microwave resistors and/or carbon resistors.
In the frequency domain, total (high frequency) distortion will
be approximately the same with or without CB. Typically, the
3rd harmonic will be greater than the 2nd without CB. This will
be reversed with CB in place.
Microstrip techniques should be used for lead lengths in excess
of one inch. Sockets should be avoided if at all possible because
of their high series inductance. If sockets are necessary, indi-
vidual pin sockets such as AMP p/n 6-330808-3 should be used.
These contribute far less stray reactance than molded socket
assemblies.
APPLICATIONS
The AD9621 is a voltage feedback amplifier and is well suited
for such applications as photo-detector preamp, active filters,
and log amplifiers. The device’s wide bandwidth (350 MHz),
An evaluation board is available from Analog Devices for a
nominal charge.
–4–
REV. 0
AD9621
Typical Performance
(RL = 100 Ω; AV = +1, unless otherwise noted)
–
80
60
40
20
0
+180
+2
+90
+75
+60
+45
+30
+15
0
+2
+180
+135
+90
+135
GAIN
+90
0
–2
–4
–6
–8
0
+45
+45
0
0
–2
–45
AV = 1
–45
–90
AV = –1
–90
PHASE
–4
–6
–8
–15
–30
–135
–180
–135
–180
AV = 2
–45
–60
AV = 4
A
V = –2
–20
10k
100k
1M
10M
100M
600M
100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
50
50 100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
FREQUENCY – Hz
Figure 4. Open-Loop Gain and
Phase
Figure 5. Inverting Frequency
Response
Figure 6. Noninverting Frequency
Response
–50
40
+20
+25
+30
2ndHARMONIC
50
–60
OUT
RL=100Ω
VOUT = 2Vp-p
50
30
–70
+35
+40
–80
2nd HARMONIC
20
10
+45
RL = 500Ω
–90
+50
3rd HARMONIC
CMRR
R
L = 100Ω
–100
–110
–120
+55
+60
3rd HARMONIC
PSRR
+65
RL = 500Ω
0
+70
1
2
4
6
10
20
40 60
10
100
1
1
10 100
1k 10k 100k 1M 10M 100M 1G
FREQUENCY – Hz
FREQUENCY – MHz
FREQUENCY – MHz
Figure 7. Harmonic Distortion
vs. Frequency
Figure 8. Third Order Intercept
Figure 9. CMRR and PSRR vs.
Frequency
+2
+180
+0.1
+0.1
+135
+90
+0.08
+0.06
TEST CIRCUIT
VOUT = 2V STEP
+0.08
+0.06
0
–2
–4
–6
100Ω
6pF
+45
0
+0.04
+0.02
+0.04
+0.02
RLOAD = 500Ω
–45
–90
0
0
–0.02
–0.02
RLOAD = 50Ω
MEASURING
POINT
–135
–180
–0.04
–0.06
VOUT = 2V STEP
–0.04
–0.06
TEST CIRCUIT
AV = 1
F = 51Ω
+2V
6pF
R
0
100Ω
–0.08
–0.1
–0.08
–0.1
–8
50 100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
0
10
20
30
40
50
10K
100K
1
10
100
1K
TIME – ns
TIME – ns
Figure 10. Frequency Response
vs. RLOAD
Figure 11. Short-Term Settling
Time
Figure 12. Long-Term Settling Time
50
40
30
30
26
10
8
10
8
27
23
19
4
3
2
VOLTAGE
6
4
6
4
VOLTAGE
RS
1k
RS
22
18
CL
51
CURRENT
20
10
0
tSETTLING
2
1
2
1
CURRENT
14
10
1
10
100
3.5
4.0
4.5
5.0
5.5
2
3
4
5
6
10
10
10
10
FREQUENCY – Hz
10
CLOAD – pF
SUPPLY VOLTAGE – ±Volts
Figure 15. Settling Time vs.
Capacitive Load
Figure 14. Output Level and
Supply Current vs. Supply Voltage
Figure 13. Input Spectral Noise
Density
REV. 0
–5–
AD9621
50
0.2V
2V
TO 0.01%
40
30
RLOAD = 100Ω
VOUT = 2V p-p
0
0
R
V
= 100Ω
RLOAD = 100Ω
LOAD
= 0.4V
VOUT = 5V p-p
OUT
p-p
20
10
–0.2V
–2V
INPUT RISE/FALL TIME = 0.3ns
5ns/DIV
INPUT RISE/FALL TIME = 1.6ns
5ns/DIV
1
3
5
NONINVERTING GAIN
Figure 16. Large Signal Pulse
Response
Figure 17. Small Signal Pulse
Response
Figure 18. Settling Time vs.
Noninverting Gain
MECHANICAL INFORMATION
Dimensions shown in inches and (mm).
Cerdip (Suffix Q)
Plastic DIP (Suffix N)
0.055 (1.4) MAX
0.005 (0.13) MIN
8
5
0.240 (6.096)
0.260 (6.604)
PIN 1
8
5
PIN 1
0.310 (7.87)
0.220 (5.59)
1
4
1
4
0.290 (7.366)
0.310 (7.874)
0.320 (8.13)
0.290 (7.37)
0.360 (9.144)
0.400 (10.16)
0.405 (10.29) MAX
0.120 (3.048)
0.140 (3.556)
0.200
(5.08)
MAX
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.015 (0.38)
0.008 (0.20)
0.140
(3.556)
MIN
0.015 (0.381)
0.008 (0.204)
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.045 (1.143)
0.065 (2.667)
0.016 (0.406)
0.020(0.508)
0°-15°
0.070 (1.78)
0.030 (0.76)
0
° TO 15°
0.023 (0.58)
0.014 (0.36)
SEATING
PLANE
0.100
(2.54)
BSC
0.100
(2.54)
BSC
SEATING
PLANE
Plastic SOIC (Suffix R)
0.196 (5.00)
0.188 (4.75)
0.244 (6.20)
0.228 (5.80)
0.158 (4.00)
0.150 (3.80)
TOP
VIEW
0.180 (0.46)
0.014 (0.36)
0.050
(1.27)
TYP
0.206 (5.20)
0.181 (4.60)
0.069 (1.75)
0.053 (1.35)
0.010 (0.25)
0.004 (0.10)
0.045 (1.15)
0.020 (0.50)
0.015 (0.38)
0.007 (0.18)
–6–
REV. 0
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