AD9637BCPZ-40_技术文档

Octal, 12-Bit, 40/80 MSPS, Serial LVDS,

1.8 V Analog-to-Digital Converter

Data Sheet

AD9637

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

PDWN

ADC

DRVDD

Low power: 60 mW per channel at 80 MSPS with scalable

power options

SNR = 71.5 dBFS (to Nyquist)

SFDR = 92 dBc (to Nyquist)

DNL = 0.4 LSB (typical), INL = 0.5 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power, reduced signal option (similar to IEEE 1596.3)

Data and frame clock outputs

650 MHz full power analog bandwidth

2 V p-p differential input voltage range

1.8 V supply operation

Serial port control

Full chip and individual channel power-down modes

Flexible bit orientation

AD9637

12

D+ A

D– A

VIN+ A

VIN– A

SERIAL

LVDS

D+ B

D– B

VIN+ B

VIN– B

SERIAL

LVDS

D+ C

D– C

VIN+ C

VIN– C

SERIAL

LVDS

D+ D

D– D

VIN+ D

VIN– D

SERIAL

LVDS

D+ E

D– E

VIN+ E

VIN– E

SERIAL

LVDS

D+ F

D– F

VIN+ F

VIN– F

SERIAL

LVDS

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

D+ G

D– G

VIN+ G

VIN– G

SERIAL

LVDS

D+ H

D– H

VIN+ H

VIN– H

SERIAL

LVDS

APPLICATIONS

VREF

FCO+

FCO–

SENSE

1.0V

Medical imaging and nondestructive ultrasound

Portable ultrasound and digital beam-forming systems

Quadrature radio receivers

DATA

RATE

MULTIPLIER

VCM

REF

SELECT

SERIAL PORT

INTERFACE

DCO+

DCO–

SYNC

Diversity radio receivers

RBIAS

AGND

CSB SDIO/ SCLK/

CLK+ CLK–

Optical networking

DFS

DTP

Test equipment

Figure 1.

GENERAL DESCRIPTION

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom user-

defined test patterns entered via the serial port interface (SPI).

The AD9637 is an octal, 12-bit, 40/80 MSPS analog-to-digital

converter (ADC) with an on-chip sample-and-hold circuit

designed for low cost, low power, small size, and ease of use.

The product operates at a conversion rate of up to 80 MSPS and

is optimized for outstanding dynamic performance and low

power in applications where a small package size is critical.

The AD9637 is available in a RoHS-compliant, 64-lead LFCSP. It is

specified over the industrial temperature range of −40°C to +85°C.

This product is protected by a U.S. patent.

The ADC requires a single 1.8 V power supply and LVPECL-/

CMOS-/LVDS-compatible sample rate clock for full performance

operation. No external reference or driver components are

required for many applications.

PRODUCT HIGHLIGHTS

1. Small Footprint. Eight ADCs are contained in a small,

space-saving package.

The ADC automatically multiplies the sample rate clock for the

appropriate LVDS serial data rate. A data clock output (DCO) for

capturing data on the output and a frame clock output (FCO) for

signaling a new output byte are provided. Individual channel

power-down is supported and typically consumes less than 2 mW

when all channels are disabled.

2. Low Power of 60 mW/Channel at 80 MSPS with Scalable

Power Options.

3. Ease of Use. A data clock output (DCO) is provided that

operates at frequencies of up to 480 MHz and supports

double data rate (DDR) operation.

4. User Flexibility. The SPI control offers a wide range of

flexible features to meet specific system requirements.

5. Pin Compatible with the AD9257 (14-Bit Octal ADC).

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9637

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Clock Input Considerations...................................................... 20

Power Dissipation and Power-Down Mode ........................... 22

Digital Outputs and Timing ..................................................... 23

Built-In Output Test Modes.......................................................... 27

Output Test Modes..................................................................... 27

Serial Port Interface (SPI).............................................................. 28

Configuration Using the SPI..................................................... 28

Hardware Interface..................................................................... 29

Configuration Without the SPI ................................................ 29

SPI Accessible Features.............................................................. 29

Memory Map .................................................................................. 30

Reading the Memory Map Register Table............................... 30

Memory Map Register Table..................................................... 31

Memory Map Register Descriptions........................................ 34

Applications Information.............................................................. 36

Design Guidelines ...................................................................... 36

Power and Ground Recommendations................................... 36

Exposed Pad Thermal Heat Slug Recommendations............ 36

VCM............................................................................................. 36

Reference Decoupling................................................................ 36

SPI Port........................................................................................ 36

Outline Dimensions....................................................................... 37

Ordering Guide .......................................................................... 37

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Table of Contents.............................................................................. 2

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Specifications .................................................................. 6

Absolute Maximum Ratings............................................................ 8

Thermal Characteristics .............................................................. 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

AD9637-80 .................................................................................. 11

AD9637-40 .................................................................................. 14

Equivalent Circuits......................................................................... 17

Theory of Operation ...................................................................... 18

Analog Input Considerations.................................................... 18

Voltage Reference ....................................................................... 19

REVISION HISTORY

10/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

Data Sheet

AD9637

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 1.

AD9637-40

AD9637-80

Parameter¹

Temp

Min

Typ

Max

Min

Typ

Max Unit

RESOLUTION

14

Bits

ACCURACY

No Missing Codes

Offset Error

Offset Matching

Gain Error

Full

Guaranteed

−0.6

0.0

−8.0

−1.0

−0.8

−1.0

−0.3 +0.1

0.2 0.6

−2.1 +2.0

+1.7 +5.0

0.3 +0.8

0.4 +1.0

−0.7

0.0

−7.0

−1.0

−0.8

−1.2

−0.3 +0.1

% FSR

LSB

0.2

0.6

−3.2 +1.0

+2.3 +6.0

0.4 +0.8

0.5 +1.2

Gain Matching

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

LSB

Offset Error

Full

2

ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode)

Load Regulation at 1.0 mA (V_REF= 1 V)

Input Resistance

Full

0.98

0.99

2

7.5

1.01

0.98

0.99

2

7.5

1.01

V

mV

kΩ

INPUT REFERRED NOISE

V_REF= 1.0 V

25°C

0.36

0.49

LSB rms

ANALOG INPUTS

Differential Input Voltage (V_REF= 1 V)

Common-Mode Voltage

Differential Input Resistance

Differential Input Capacitance

POWER SUPPLY

Full

2

V p-p

V

kΩ

pF

0.9

5.2

3.5

0.9

5.2

3.5

Full

AVDD

DRVDD

I_AVDD(Eight Channels)

I_DRVDD(Eight Channels, ANSI-644 Mode)

I_DRVDD(Eight Channels, Reduced Range Mode)

TOTAL POWER CONSUMPTION

Total Power Dissipation (Eight Channels, ANSI-644 Mode)

Total Power Dissipation (Eight Channels, Reduced Range Mode)

Power-Down Dissipation

Standby Dissipation²

Full

25°C

1.7

1.8

142

51

1.9

151

79

1.7

1.8

221

58

1.9

234

85

V

mA

36

43

Full

347

320

1

414

502

475

1

574

mW

25°C

72

98

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

²Can be controlled via the SPI.

Rev. 0 | Page 3 of 40

AD9637

Data Sheet

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 2.

AD9637-40

Typ

AD9637-80

Typ

Parameter¹

Temp

Unit

Min

Max

Min

Max

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 9.7 MHz

f_IN= 19.7 MHz

f_IN= 30.5 MHz

f_IN= 63.5 MHz

25°C

Full

25°C

72.0

71.5

dBFS

70.0

71.0

f_IN= 69.5 MHz

f_IN= 123.5 MHz

71.5

70.5

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

f_IN= 9.7 MHz

f_IN= 19.7 MHz

f_IN= 30.5 MHz

f_IN= 63.5 MHz

25°C

Full

25°C

71.0

70.5

dBFS

69.0

11.2

78

70.0

11.3

78

f_IN= 69.5 MHz

f_IN= 123.5 MHz

70.5

69.5

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 9.7 MHz

f_IN= 19.7 MHz

f_IN= 30.5 MHz

f_IN= 63.5 MHz

25°C

Full

25°C

11.5

11.4

Bits

f_IN= 69.5 MHz

f_IN= 123.5 MHz

11.4

11.3

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_IN= 9.7 MHz

f_IN= 19.7 MHz

f_IN= 30.5 MHz

f_IN= 63.5 MHz

25°C

Full

25°C

96

95

96

93

92

93

dBc

f_IN= 69.5 MHz

f_IN= 123.5 MHz

89

88

WORST HARMONIC (SECOND OR THIRD)

f_IN= 9.7 MHz

f_IN= 19.7 MHz

f_IN= 30.5 MHz

f_IN= 63.5 MHz

25°C

Full

25°C

−99

−96

−98

−96

−92

−95

dBc

−78

−86

−78

−86

f_IN= 69.5 MHz

f_IN= 123.5 MHz

−89

WORST OTHER (EXCLUDING SECOND OR THIRD)

f_IN= 9.7 MHz

f_IN= 19.7 MHz

f_IN= 30.5 MHz

f_IN= 63.5 MHz

25°C

Full

25°C

−98

−97

dBFS

f_IN= 69.5 MHz

f_IN= 123.5 MHz

−97

−92

TWO-TONE INTERMODULATION DISTORTION (IMD)—

AIN1 AND AIN2 = −7.0 dBFS

f_IN1= 8 MHz, f_IN2= 10 MHz

f_IN1= 30 MHz, f_IN2= 32 MHz

25°C

93

dBc

85

Rev. 0 | Page 4 of 40

Data Sheet

AD9637

AD9637-40

−98

−89

AD9637-80

−96

−89

CROSSTALK

25°C

dB

Crosstalk (Overrange Condition)²

ANALOG INPUT BANDWIDTH, FULL POWER

650

MHz

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

²Overrange condition is specified with 3 dB of the full-scale input range.

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 3.

Parameter¹

Temp

Min

Typ

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage²

Input Voltage Range

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

Full

25°C

0.2

AGND − 0.2

3.6

AVDD + 0.2

V p-p

V

kΩ

pF

0.9

15

4

LOGIC INPUTS (PDWN, SYNC, SCLK)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

0

AVDD + 0.2

0.8

V

Input Resistance

Input Capacitance

25°C

30

2

kΩ

pF

LOGIC INPUT (CSB)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

0

AVDD + 0.2

0.8

V

Input Resistance

Input Capacitance

25°C

26

2

kΩ

pF

LOGIC INPUT (SDIO)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

0

AVDD + 0.2

0.8

V

Input Resistance

Input Capacitance

25°C

26

5

kΩ

pF

LOGIC OUTPUT (SDIO)³

Logic 1 Voltage (I_OH= 800 μA)

Logic 0 Voltage (I_OL= 50 μA)

DIGITAL OUTPUTS (D ꢀ), ANSI-644

Logic Compliance

Full

1.79

V

0.05

LVDS

Differential Output Voltage (V_OD)

Output Offset Voltage (V_OS)

Output Coding (Default)

Full

247

1.13

350

1.21

454

1.38

mV

V

Twos complement

DIGITAL OUTPUTS (D ꢀ), LOW POWER,

REDUCED SIGNAL OPTION

Logic Compliance

LVDS

Differential Output Voltage (V_OD)

Output Offset Voltage (V_OS)

Output Coding (Default)

Full

150

1.13

200

1.21

250

1.38

mV

V

Twos complement

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

²This is specified for LVDS and LVPECL only.

³This is specified for 13 SDIO/DFS pins sharing the same connection.

Rev. 0 | Page 5 of 40

AD9637

Data Sheet

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 4.

Parameter^{1, 2}

CLOCK³

Temp

Min

Typ

Max

Unit

Input Clock Rate

Conversion Rate

Full

10

640

40/80

MHz

MSPS

ns

Clock Pulse Width High (t_EH)

Clock Pulse Width Low (t_EL)

OUTPUT PARAMETERS³

Propagation Delay (t_PD)

Rise Time (t_R) (20% to 80%)

Fall Time (t_F) (20% to 80%)

FCO Propagation Delay (t_FCO

DCO Propagation Delay (t_CPD

DCO to Data Delay (t_DATA

DCO to FCO Delay (t_FRAME

Data to Data Skew

12.5/6.25

ns

Full

2.3

300

2.3

ns

ps

ns

ps

)

1.5

3.1

4

t_FCO+ (t_SAMPLE/24)

(t_SAMPLE/24)

50

4

)

(t_SAMPLE/24) − 300

(t_SAMPLE/24) + 300

200

4

)

(t_DATA-MAX− t_DATA-MIN

)

Wake-Up Time (Standby)

Wake-Up Time (Power-Down)⁵

Pipeline Latency

25°C

Full

35

375

16

μs

Clock

cycles

APERTURE

Aperture Delay (t_A)

Aperture Uncertainty (Jitter)

Out-of-Range Recovery Time

25°C

1

0.1

1

ns

ps rms

Clock

cycles

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

²Measured on standard FR-4 material.

³Can be adjusted via the SPI.

⁴t_SAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. t_SAMPLE= 1/f_S.

⁵Wake-up time is defined as the time required to return to normal operation from power-down mode.

TIMING SPECIFICATIONS

Table 5.

Parameter

Description

Limit

Unit

SYNC TIMING REQUIREMENTS

t_SSYNC

t_HSYNC

SYNC to rising edge of CLK+ setup time

SYNC to rising edge of CLK+ hold time

See Figure 61

0.24

0.40

ns typ

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_{EN_SDIO}

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

SCLK pulse width high

SCLK pulse width low

Time required for the SDIO pin to switch from an input to an output relative to

the SCLK falling edge (not shown in Figure 61)

2

40

2

10

ns min

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an input relative to

the SCLK rising edge (not shown in Figure 61)

10

ns min

Rev. 0 | Page 6 of 40

Data Sheet

AD9637

Timing Diagrams

N – 1

t_A

VIN± x

N

t_EH

t_EL

CLK–

CLK+

DCO–

DCO+

t_CPD

t_FRAME

t_FCO

FCO–

FCO+

D– x

t_PD

t_DATA

D6

MSB

D10

D9

D8

D7

D5

D4

D3

D2

D1

D0

MSB

D10

N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16

D+ x

Figure 2. Word-Wise DDR, 1× Frame, 12-Bit Output Mode (Default)

N – 1

VIN± x

t_A

N

t_EH

t_EL

CLK–

CLK+

DCO–

t_CPD

DCO+

FCO–

t_FRAME

t_FCO

FCO+

D– x

t_PD

t_DATA

D4

MSB

D8

D7

D6

D5

D3

D2

D1

D0

MSB

D8

D7

D6

D5

N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 N – 16 N – 16

D+ x

Figure 3. Word-Wise DDR, 1× Frame, 10-Bit Output Mode

CLK+

SYNC

t_SSYNC

t_HSYNC

Figure 4. SYNC Input Timing Requirements

Rev. 0 | Page 7 of 40

AD9637

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 6.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for

the LFCSP package. Soldering the exposed paddle to the printed

circuit board (PCB) increases the reliability of the solder joints

and maximizes the thermal capability of the package.

Parameter

Rating

Electrical

AVDD to AGND

DRVDD to AGND

Digital Outputs

(D ꢀx DꢁO+x DꢁO−x FꢁO+x FꢁO−) to

AGND

ꢁLK+x ꢁLK− to AGND

VIN+ ꢀx VIN− ꢀ to AGND

SꢁLK/DTPx SDIO/DFSx ꢁSB to AGND

SYNꢁx PDWN to AGND

RBIAS to AGND

VREFx SENSE to AGND

Environmental

Operating Temperature Range (Ambient) −40°ꢁ to +85°ꢁ

−0.3 V to +2.0 V

Table 7. Thermal Resistance

Airflow

Velocity

(m/sec)

Package

Type

1, 2

1, 3

1, 4

1, 2

θ_JA

θ_JC

θ_JB

_JT

0.1

0.2

Unit

°ꢁ/W

−0.3 V to +2.0 V

64-Lead

0

22.3

19.5

17.5

1.4

N/A

11.8

LFꢁSP

9 mm × 9 mm

(ꢁP-64-4)

1.0

2.5

N/A

¹Per JEDEꢁ 51-7x plus JEDEꢁ 25-5 2S2P test board.

²Per JEDEꢁ JESD51-2 (still air) or JEDEꢁ JESD51-6 (moving air).

³Per MIL-Std 883x Method 1012.1.

⁴Per JEDEꢁ JESD51-8 (still air).

Maꢀimum Junction Temperature

Lead Temperature (Solderingx 10 sec)

Storage Temperature Range (Ambient)

150°ꢁ

300°ꢁ

−65°ꢁ to +150°ꢁ

Typical θ_JAis specified for a 4-layer PCB with a solid ground

plane. As shown Table 7, airflow improves heat dissipation,

which reduces θ_JA. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and

power planes reduces θ_JA.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. 0 | Page 8 of 40

Data Sheet

AD9637

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

AVDD

VIN+ G

VIN– G

AVDD

VIN– H

VIN+ H

AVDD

CLK–

CLK+ 10

AVDD 11

AVDD 12

DNC 13

1

2

3

4

5

6

7

8

9

48 AVDD

47 VIN+ B

46 VIN– B

45 AVDD

44 VIN– A

43 VIN+ A

42 AVDD

41 PDWN

40 CSB

39 SDIO/DFS

38 SCLK/DTP

37 AVDD

36 DNC

AD9637

TOP VIEW

(Not to Scale)

DRVDD 14

D– H 15

35 DRVDD

34 D+ A

D+ H 16

33 D– A

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.

Figure 5. Pin Configuration, Top View

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

0, EP

AGND,

Eꢀposed Pad

Analog Ground, Eꢀposed Pad. The eꢀposed thermal pad on the bottom of the package provides the

analog ground for the part. This eꢀposed pad must be connected to analog ground for proper operation.

1, 4, 7, 8, 11,

12, 37, 42, 45,

48, 51, 59, 62

AVDD

1.8 V Analog Supply.

13, 36

14, 35

2, 3

DNC

DRVDD

Do Not Connect. Do not connect to this pin.

1.8 V Digital Output Driver Supply.

VIN+ G, VIN− G ADC G Analog Input True, ADC G Analog Input Complement.

VIN− H, VIN+ H ADC H Analog Input Complement, ADC H Analog Input True.

5, 6

9, 10

15, 16

17, 18

19, 20

21, 22

23, 24

25, 26

27, 28

29, 30

31, 32

33, 34

38

CLK−, CLK+

D− H, D+ H

D− G, D+ G

D− F, D+ F

D− E, D+ E

DCO−, DCO+

FCO−, FCO+

D− D, D+ D

D− C, D+ C

D− B, D+ B

D− A, D+ A

SCLK/DTP

SDIO/DFS

CSB

Input Clock Complement, Input Clock True.

ADC H Digital Output Complement, ADC H Digital Output True.

ADC G Digital Output Complement, ADC G Digital Output True.

ADC F Digital Output Complement, ADC F Digital Output True.

ADC E Digital Output Complement, ADC E Digital Output True.

Data Clock Digital Output Complement, Data Clock Digital Output True.

Frame Clock Digital Output Complement, Frame Clock Digital Output True.

ADC D Digital Output Complement, ADC D Digital Output True.

ADC C Digital Output Complement, ADC C Digital Output True.

ADC B Digital Output Complement, ADC B Digital Output True.

ADC A Digital Output Complement, ADC A Digital Output True.

Serial Clock (SCLK)/Digital Test Pattern (DTP).

39

40

Serial Data Input/Output (SDIO)/Data Format Select (DFS).

Chip Select Bar.

41

PDWN

Power-Down.

43, 44

46, 47

49, 50

VIN+ A, VIN− A ADC A Analog Input True, ADC A Analog Input Complement.

VIN− B, VIN+ B ADC B Analog Input Complement, ADC B Analog Input True.

VIN+ C, VIN− C ADC C Analog Input True, ADC C Analog Input Complement.

Rev. 0 | Page 9 of 40

AD9637

Data Sheet

Pin No.

52, 53

54

Mnemonic

Description

VIN− D, VIN+ D ADC D Analog Input Complement, ADC D Analog Input True.

RBIAS

SENSE

Sets analog current bias. Connect to 10 kΩ (1% tolerance) resistor to ground.

Reference Mode Selection.

55

56

VREF

Voltage Reference Input/Output.

57

58

60, 61

63, 64

VCM

SYNC

VIN+ E, VIN− E

VIN− F, VIN+ F

Analog Output Voltage at Midsupply. Sets common mode of the analog inputs.

Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.

ADC E Analog Input True, ADC E Analog Input Complement.

ADC F Analog Input Complement, ADC F Analog Input True.

Rev. 0 | Page 10 of 40

Data Sheet

AD9637

TYPICAL PERFORMANCE CHARACTERISTICS

AD9637-80

0

–15

80MSPS

9.7MHz AT –1dBFS

SNR = 70.8dB (71.8dBFS)

SFDR = 92.7dBc

19.7MHz AT –1dBFS

SNR = 70.7dB (71.7dBFS)

SFDR = 90.1dBc

–15

–30

–45

–60

–75

–90

–105

–120

–135

–105

–120

–135

4

8

12

16

20

24

28

32

36

4

8

12

16

20

24

28

32

36

FREQUENCY (MHz)

Figure 6. Single-Tone 16k FFT with f_IN= 9.7 MHz, f_SAMPLE= 80 MSPS

Figure 9. Single-Tone 16k FFT with f_IN= 19.7 MHz, f_SAMPLE= 80 MSPS

0

80MSPS

63.5MHz AT –1dBFS

SNR = 70.5dB (71.5dBFS)

SFDR = 93.2dBc

30.5MHz AT –1dBFS

SNR = 70.7dB (71.7dBFS)

SFDR = 90.7dBc

–15

–30

–15

–30

–45

–60

–75

–90

–105

–120

–135

–105

–120

–135

4

8

12

16

20

24

28

32

36

4

8

12

16

20

24

28

32

36

FREQUENCY (MHz)

Figure 10. Single-Tone 16k FFT with f_IN= 30.5 MHz, f_SAMPLE= 80 MSPS

Figure 7. Single-Tone 16k FFT with f_IN= 63.5 MHz, f_SAMPLE= 80 MSPS

0

–15

–30

–45

–60

–75

80MSPS

123.5MHz AT –1dBFS

SNR = 69.6dB (70.6dBFS)

SFDR = 90.3dBc

–15

–30

–45

–60

–75

–90

F1 + F2

+

F2 – F1

2F1 + F2

2F2 + F1

2F2 – F1

2F1 – F2

–105

–120

–135

–105

–120

–135

4

8

12

16

20

24

28

32

36

4

8

12

16

20

24

28

32

36

FREQUENCY (MHz)

Figure 8. Two-Tone 16k FFT with f_IN1= 30 MHz and f_IN2= 32 MHz,

f_SAMPLE= 80 MSPS

Figure 11. Single-Tone 16k FFT with f_IN= 123.5 MHz, f_SAMPLE= 80 MSPS

Rev. 0 | Page 11 of 40

AD9637

Data Sheet

0

105

100

95

SFDR (dBc)

–20

SFDR (dBc)

–40

–60

IMD3 (dBc)

90

85

–80

SFDR (dBFS)

80

–100

75

SNR (dBFS)

–15

IMD3 (dBFS)

–120

–90

70

–40

–78

–66

–54

–42

–30

–18

–6

10

35

60

85

INPUT AMPLITUDE (dBFS)

TEMPERATURE (°C)

Figure 12. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with

f_IN1= 30 MHz and f_IN2= 32 MHz, f_SAMPLE= 80 MSPS

Figure 15. SNR/SFDR vs. Temperature, f_IN= 9.7 MHz, f_SAMPLE= 80 MSPS

120

110

100

SFDR (dBc)

100

90

SFDRFS

80

SNR (dBFS)

80

70

60

50

40

30

20

10

0

SNRFS

60

SFDR

40

20

0

SNR

–70

–60

–50

–40

–30

–20

–10

0

50

100

150

200

INPUT AMPLITUDE (dBFS)

INPUT FREQUENCY (MHz)

Figure 13. SNR/SFDR vs. Analog Input Level, f_IN= 9.7 MHz, f_SAMPLE= 80 MSPS

Figure 16. SNR/SFDR vs. f_IN, f_SAMPLE= 80 MSPS

105

100

95

90

85

80

75

70

65

SFDR

100

SFDR

95

90

85

80

SNRFS

75

SNRFS

70

20

30

40

50

60

70

80

20

30

40

50

60

70

80

SAMPLE FREQUENCY (MSPS)

Figure 14. SNR/SFDR vs. Encode, f_IN= 19.7 MHz

Figure 17. SNR/SFDR vs. Encode, f_IN= 30.5 MHz

Rev. 0 | Page 12 of 40

Data Sheet

AD9637

700,000

600,000

500,000

400,000

300,000

200,000

100,000

0

1.0

0.8

0.491 LSB RMS

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

OUTPUT CODE

Figure 18. Input Referred Noise Histogram, f_SAMPLE= 80 MSPS

Figure 20. DNL, f_IN= 9.7 MHz, f_SAMPLE= 80 MSPS

2.0

1.6

1.2

0.8

0.4

0

–0.4

–0.8

–1.2

–1.6

–2.0

OUTPUT CODE

Figure 19. INL, f_IN= 9.7 MHz, f_SAMPLE= 80 MSPS

Rev. 0 | Page 13 of 40

AD9637

Data Sheet

AD9637-40

0

–15

40MSPS

19.7MHz AT –1dBFS

SNR = 70.9dB (71.9dBFS)

SFDR = 91.0dBc

–15

–30

9.7MHz AT –1dBFS

SNR = 71.0dB (72.0dBFS)

SFDR = 96.9dBc

–30

–45

–60

–75

–90

–105

–120

–135

–105

–120

–135

2

4

6

8

10

12

14

16

18

2

4

6

8

10

12

14

16

18

FREQUENCY (MHz)

Figure 21. Single-Tone 16k FFT with f_IN= 9.7 MHz, f_SAMPLE= 40 MSPS

Figure 24. Single-Tone 16k FFT with f_IN= 19.7 MHz, f_SAMPLE= 40 MSPS

0

40MSPS

69.5MHz AT –1dBFS

SNR = 70.5dB (71.5dBFS)

SFDR = 88.6dBc

30.5MHz AT –1dBFS

SNR = 70.9dB (7.19dBFS)

SFDR = 95.87dBc

–15

–30

–15

–30

–45

–60

–75

–90

–105

–120

–135

–105

–120

–135

2

4

6

8

10

12

14

16

18

2

4

6

8

10

12

14

16

18

FREQUENCY (MHz)

Figure 22. Single-Tone 16k FFT with f_IN= 30.5 MHz, f_SAMPLE= 40 MSPS

Figure 25. Single-Tone 16k FFT with f_IN= 69.5 MHz, f_SAMPLE= 40 MSPS

0

–15

–30

–45

–60

–75

–20

SFDR (dBc)

–40

IMD3 (dBc)

–60

–80

–90

2F1 + F2

SFDR (dBFS)

+

2F2 – F1

F2 – F1

F1 + F2

2F2 + F1

2F1 – F2

–105

–120

–135

–100

IMD3 (dBFS)

–120

2

4

6

8

10

12

14

16

18

–90

–78

–66

–54

–42

–30

–18

–6

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 23. Two-Tone 16k FFT with f_IN1= 8 MHz and f_IN2= 10 MHz,

_SAMPLE= 40 MSPS

Figure 26. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with

f_IN1= 30 MHz and f_IN2= 32 MHz, f_SAMPLE= 40 MSPS

f

Rev. 0 | Page 14 of 40

Data Sheet

AD9637

120

100

80

60

40

20

0

110

100

90

80

70

60

50

40

30

20

10

0

SFDR (dBc)

SNR (dBFS)

SFDRFS

SNRFS

SFDR

SNR

–70

–60

–50

–40

–30

–20

–10

0

20

40

60

80

100 120 140 160 180 200

INPUT AMPLITUDE (dBFS)

INPUT FREQUENCY (MHz)

Figure 27. SNR/SFDR vs. Analog Input Level, f_IN= 9.7 MHz, f_SAMPLE= 40 MSPS

Figure 30. SNR/SFDR vs. f_IN, f_SAMPLE= 40 MSPS

105

100

105

100

95

90

85

80

75

70

65

SFDR

95

90

85

80

75

SNRFS

70

65

20

25

30

35

40

25

30

35

40

SAMPLE FREQUENCY (MSPS)

Figure 31. SNR/SFDR vs. Encode, f_IN= 30.5 MHz

Figure 28. SNR/SFDR vs. Encode, f_IN= 19.7 MHz

1,000,000

900,000

800,000

700,000

600,000

500,000

400,000

300,000

200,000

100,000

0

105

100

95

0.356 LSB RMS

SFDR (dBc)

90

85

80

75

SNR (dBFS)

70

–40

–15

10

35

60

85

TEMPERATURE (°C)

OUTPUT CODE

Figure 32. Input-Referred Noise Histogram, f_SAMPLE= 40 MSPS

Figure 29. SNR/SFDR vs. Temperature, f_IN= 9.7 MHz, f_SAMPLE= 40 MSPS

Rev. 0 | Page 15 of 40

AD9637

Data Sheet

2.0

1.6

1.0

0.8

1.2

0.6

0.8

0.4

0.2

0

–0.4

–0.8

–1.2

–1.6

–0.2

–0.4

–0.6

–0.8

–2.0

–1.0

OUTPUT CODE

Figure 33. INL, f_IN= 9.7 MHz, f_SAMPLE= 40 MSPS

Figure 34. DNL, f_IN= 9.7 MHz, f_SAMPLE= 40 MSPS

Rev. 0 | Page 16 of 40

Data Sheet

AD9637

EQUIVALENT CIRCUITS

AVDD

350Ω

SCLK/DTP, SYNC,

AND PDWN

VIN± x

30kΩ

Figure 39. Equivalent SCLK/DTP, SYNC, and PDWN Input Circuit

Figure 35. Equivalent Analog Input Circuit

AVDD

5Ω

CLK+

AVDD

15kΩ

0.9V

AVDD

375Ω

RBIAS

AND VCM

5Ω

CLK–

Figure 36. Equivalent Clock Input Circuit

Figure 40. Equivalent RBIAS, VCM Circuit

AVDD

30kΩ

350Ω

SDIO/DFS

30kΩ

350Ω

30kΩ

CSB

Figure 37. Equivalent SDIO/DFS Input Circuit

Figure 41. Equivalent CSB Input Circuit

DRVDD

AVDD

V

D– x

D+ x

V

375Ω

VREF

7.5kΩ

DRGND

Figure 38. Equivalent Digital Output Circuit

Figure 42. Equivalent VREF Circuit

Rev. 0 | Page 17 of 40

AD9637

Data Sheet

THEORY OF OPERATION

input can help reduce the peak transient current injected from

the output stage of the driving source. In addition, low Q inductors

or ferrite beads can be placed on each leg of the input to reduce

high differential capacitance at the analog inputs and, therefore,

achieve the maximum bandwidth of the ADC. Such use of low

Q inductors or ferrite beads is required when driving the converter

front end at high IF frequencies. Either a differential capacitor or

two single-ended capacitors can be placed on the inputs to provide

a matching passive network. This ultimately creates a low-pass

filter at the input to limit unwanted broadband noise. See the

AN-742 Application Note, the AN-827 Application Note, and the

Analog Dialogue article “Transformer-Coupled Front-End for

Wideband A/D Converters” (Volume 39, April 2005) for more

information. In general, the precise values depend on the

application.

The AD9637 is a multistage, pipelined ADC. Each stage

provides sufficient overlap to correct for flash errors in the

preceding stage. The quantized outputs from each stage are

combined into a final 12-bit result in the digital correction

logic. The serializer transmits this converted data in a 12-bit

output. The pipelined architecture permits the first stage to

operate with a new input sample, while the remaining stages

operate with preceding samples. Sampling occurs on the rising

edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and an interstage residue amplifier (for example, a multiplying

digital-to-analog converter (MDAC)). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

Input Common Mode

The analog inputs of the AD9637 are not internally dc-biased.

Therefore, in ac-coupled applications, the user must provide

this bias externally. Setting the device so that V_CM= AVDD/2 is

recommended for optimum performance, but the device can

function over a wider range with reasonable performance, as

shown in Figure 44.

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. The data is then serialized

and aligned to the frame and data clocks.

ANALOG INPUT CONSIDERATIONS

100

The analog input to the AD9637 is a differential, switched

capacitor circuit designed for processing differential input

signals. This circuit can support a wide common-mode range

while maintaining excellent performance. By using an input

common-mode voltage of midsupply, users can minimize

signal-dependent errors and achieve optimum performance.

SFDR

90

80

SNRFS

70

60

50

40

30

20

H

C_PAR

H

VIN+ x

C_SAMPLE

S

0.5

0.7

0.9

(V)

1.1

1.3

C_SAMPLE

V

CM

VIN– x

H

Figure 44. SNR/SFDR vs. Common-Mode Voltage,

f_IN= 9.7 MHz, f_SAMPLE= 80 MSPS

C_PAR

H

An on-board, common-mode voltage reference is included in

the design and is available from the VCM pin. The VCM pin

must be decoupled to ground by a 0.1 μF capacitor, as described

in the Applications Information section.

Figure 43. Switched-Capacitor Input Circuit

The clock signal alternately switches the input circuit between

sample mode and hold mode (see Figure 43). When the input

circuit is switched to sample mode, the signal source must be

capable of charging the sample capacitors and settling within

one-half of a clock cycle. A small resistor in series with each

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. In the case of the

AD9637, the largest input span available is 2 V p-p.

Rev. 0 | Page 18 of 40

Data Sheet

AD9637

Differential Input Configurations

Internal Reference Connection

There are several ways to drive the AD9637 either actively or

passively. However, optimum performance is achieved by driving

the analog input differentially. Using a differential double balun

configuration to drive the AD9637 provides excellent performance

and a flexible interface to the ADC (see Figure 46) for baseband

applications.

A comparator within the AD9637 detects the potential at the

SENSE pin and configures the reference into two possible modes,

which are summarized in Table 9. If SENSE is grounded, the

reference amplifier switch is connected to the internal resistor

divider (see Figure 45), setting VREF to 1.0 V.

Table 9. Reference Configuration Summary

For applications where SNR is a key parameter, differential trans-

former coupling is the recommended input configuration (see

Figure 47), because the noise performance of most amplifiers is

not adequate to achieve the true performance of the AD9637.

Resulting

Differential

Span (V p-p)

SENSE

Resulting

V_REF(V)

Selected Mode Voltage (V)

Fiꢀed Internal

Reference

Fiꢀed Eꢀternal

Reference

AGND to 0.2

1.0 internal

2.0

Regardless of the configuration, the value of the shunt capacitor,

C, is dependent on the input frequency and may need to be

reduced or removed.

AVDD

1.0 applied

to eꢀternal

VREF pin

2.0

It is not recommended to drive the AD9637 input single-ended.

VIN+ x

VIN– x

VOLTAGE REFERENCE

A stable and accurate 1.0 V voltage reference is built into the

AD9637. VREF can be configured using either the internal 1.0 V

reference or an externally applied 1.0 V reference voltage. The

various reference modes are summarized in the sections that

follow. The VREF pin should be externally decoupled to ground

with a low ESR, 1.0 ꢀF capacitor in parallel with a low ESR,

0.1 ꢀF ceramic capacitor.

ADC

CORE

VREF

0.1µF

1.0µF

SELECT

LOGIC

SENSE

0.5V

ADC

Figure 45. Internal Reference Configuration

0.1µF

R

*C1

5pF

0.1µF

VIN+ x

33Ω

C

2V p-p

C

ADC

0.1µF

C

R

VCM

VIN– x

33Ω

ET1-1-I3

*C1

R

200Ω

*C1 IS OPTIONAL

0.1µF

C

0.1µF

Figure 46. Differential Double Balun Input Configuration for Baseband Applications

ADT1-1WT

1:1 Z RATIO

*C1

R

VIN+ x

VIN– x

33ꢀ

2Vp-p

49.9ꢀ

ADC

C

5pF

*C1

R

VCM

33ꢀ

200ꢀ

0.1µF

0.1μF

*C1 IS OPTIONAL

Figure 47. Differential Transformer-Coupled Configuration for Baseband Applications

Rev. 0 | Page 19 of 40

AD9637

Data Sheet

If the internal reference of the AD9637 is used to drive multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 48 shows

how the internal reference voltage is affected by loading.

0

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9637 sample clock inputs,

CLK+ and CLK−, with a differential signal. The signal is typically

ac-coupled into the CLK+ and CLK− pins via a transformer or

capacitors. These pins are biased internally (see Figure 36) and

require no external bias.

–0.5

–1.0

Clock Input Options

INTERNAL V

REF

= 1V

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

The AD9637 has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter is

of the utmost concern, as described in the Jitter Considerations

section.

Figure 50 and Figure 51 show two preferred methods for clocking

the AD9637 (at clock rates of up to 640 MHz prior to the internal

CLK divider). A low jitter clock source is converted from a single-

ended signal to a differential signal using either an RF transformer

or an RF balun.

0

0.5

1.0

1.5

2.0

2.5

3.0

LOAD CURRENT (mA)

Figure 48. V_REFError vs. Load Current

The RF balun configuration is recommended for clock frequencies

between 80 MHz and 640 MHz, and the RF transformer is recom-

mended for clock frequencies from 10 MHz to 200 MHz. The

back-to-back Schottky diodes across the transformer/balun

secondary winding limit clock excursions into the AD9637 to

approximately 0.8 V p-p differential.

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 49 shows the typical drift characteristics of the

internal reference in 1.0 V mode.

4

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9637 while

preserving the fast rise and fall times of the signal that are critical

to a low jitter performance. However, the diode capacitance comes

into play at frequencies above 500 MHz. Care must be taken in

choosing the appropriate signal limiting diode.

2

0

–2

–4

–6

–8

®

Mini-Circuits

ADT1-1WT, 1:1 Z

0.1µF

XFMR

CLOCK

INPUT

CLK+

100ꢀ

50ꢀ

ADC

0.1µF

CLK–

SCHOTTKY

DIODES:

HSMS2822

0.1µF

–40

–15

10

35

60

85

TEMPERATURE (°C)

Figure 50. Transformer Coupled Differential Clock (Up to 200 MHz)

Figure 49. Typical V_REFDrift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7.5 kΩ load (see Figure 42). The internal buffer generates the

positive and negative full-scale references for the ADC core.

Therefore, the external reference must be limited to a maximum

of 1.0 V. It is not recommended to leave the SENSE pin floating.

0.1µF

CLOCK

INPUT

CLK+

50ꢀ

ADC

0.1µF

CLK–

SCHOTTKY

DIODES:

HSMS2822

Figure 51. Balun Coupled Differential Clock (80 MHz to 640 MHz)

Rev. 0 | Page 20 of 40

Data Sheet

AD9637

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 52. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer

excellent jitter performance.

causes the clock divider to reset to its initial state. This

synchronization feature allows multiple parts to have their clock

dividers aligned to guarantee simultaneous input sampling.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a variety

of internal timing signals and, as a result, may be sensitive to

clock duty cycle. Commonly, a 5% tolerance is required on the

clock duty cycle to maintain dynamic performance characteristics.

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 53. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517

clock drivers offer excellent jitter performance.

The AD9637 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock signal

with a nominal 50% duty cycle. This allows the user to provide

a wide range of clock input duty cycles without affecting the

performance of the AD9637. Noise and distortion performance

are nearly flat for a wide range of duty cycles with the DCS

turned on.

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLK+ pin directly from a CMOS gate, and

bypass the CLK− pin to ground with a 0.1 ꢀF capacitor (see

Figure 54).

Input Clock Divider

The AD9637 contains an input clock divider with the ability

to divide the input clock by integer values between 1 and 8.

Jitter in the rising edge of the input is still of concern and is not

easily reduced by the internal stabilization circuit. The duty

cycle control loop does not function for clock rates less than

20 MHz, nominally. The loop has a time constant associated

with it that must be considered in applications in which the

clock rate can change dynamically. A wait time of 1.5 μs to 5 μs

is required after a dynamic clock frequency increase or decrease

before the DCS loop is relocked to the input signal.

The AD9637 clock divider can be synchronized using the external

SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the clock

divider to be resynchronized on every SYNC signal or only on

the first SYNC signal after the register is written. A valid SYNC

0.1µF

CLK+

CLOCK

INPUT

AD951x

PECL DRIVER

100ꢀ

ADC

0.1µF

CLK–

CLOCK

INPUT

240ꢀ

50kꢀ

Figure 52. Differential PECL Sample Clock (Up to 640 MHz)

0.1µF

CLOCK

INPUT

CLK+

AD951x

LVDS DRIVER

100ꢀ

ADC

0.1µF

CLOCK

INPUT

CLK–

50kꢀ

Figure 53. Differential LVDS Sample Clock (Up to 640 MHz)

V

CC

OPTIONAL

100ꢀ

0.1µF

1

0.1µF

1kꢀ

AD951x

CMOS DRIVER

CLOCK

INPUT

CLK+

50ꢀ

ADC

CLK–

0.1µF

1

50ꢀ RESISTOR IS OPTIONAL.

Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Rev. 0 | Page 21 of 40

AD9637

Data Sheet

Jitter Considerations

POWER DISSIPATION AND POWER-DOWN MODE

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(f_A) due only to aperture jitter (t_J) can be calculated by

As shown in Figure 56, the power dissipated by the AD9637 is

proportional to its sample rate. The digital power dissipation

does not vary significantly because it is determined primarily by

the DRVDD supply and bias current of the LVDS output drivers.

400

⎛

⎞

1

SNR Degradation = 20 log₁₀

⎜

⎟

2π × f_A× t_J

⎝

⎠

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 55).

350

80MSPS

300

65MSPS

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9637.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another

type of source (by gating, dividing, or other methods), it should

be retimed by the original clock at the last step.

250

200

150

50MSPS

40MSPS

20MSPS

30

10

20

40

50

60

70

80

SAMPLE RATE (MSPS)

Figure 56. Analog Core Power vs. f_SAMPLEfor f_IN= 9.7 MHz

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs.

The AD9637 is placed in power-down mode either by the SPI

port or by asserting the PDWN pin high. In this state, the ADC

typically dissipates 1 mW. During power-down, the output drivers

are placed in a high impedance state. Asserting the PDWN pin

low returns the AD9637 to its normal operating mode. Note

that PDWN is referenced to the digital output driver supply

(DRVDD) and should not exceed that supply voltage.

130

RMS CLOCK JITTER REQUIREMENT

120

110

16 BITS

100

90

80

70

60

50

40

30

14 BITS

12 BITS

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and then must be recharged when returning

to normal operation. As a result, wake-up time is related to the

time spent in power-down mode, and shorter power-down

cycles result in proportionally shorter wake-up times. When

using the SPI port interface, the user can place the ADC in

power-down mode or standby mode. Standby mode allows the

user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map section

for more details on using these features.

10 BITS

8 BITS

0.125ps

0.25ps

0.5ps

1.0ps

2.0ps

1

10

100

1000

ANALOG INPUT FREQUENCY (MHz)

Figure 55. Ideal SNR vs. Input Frequency and Jitter

Rev. 0 | Page 22 of 40

Data Sheet

AD9637

DIGITAL OUTPUTS AND TIMING

The AD9637 differential outputs conform to the ANSI-644 LVDS

standard on default power-up. This can be changed to a low power,

reduced signal option (similar to the IEEE 1596.3 standard) via the

SPI. The LVDS driver current is derived on chip and sets the

output current at each output equal to a nominal 3.5 mA. A 100 Ω

differential termination resistor placed at the LVDS receiver

inputs results in a nominal 350 mV swing (or 700 mV p-p

differential) at the receiver.

When operating in reduced range mode, the output current is

reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p

differential) across a 100 Ω termination at the receiver.

FCO 500mV/DIV

DCO 500mV/DIV

DATA 500mV/DIV

5ns/DIV

The AD9637 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs for superior switching

performance in noisy environments. Single point-to-point net

topologies are recommended with a 100 Ω termination resistor

placed as close to the receiver as possible. If there is no far-end

receiver termination or there is poor differential trace routing,

timing errors may result. To avoid such timing errors, it is

recommended that the trace length be less than 24 inches and

that the differential output traces be close together and at equal

lengths. An example of the FCO and data stream with proper

trace length and position is shown in Figure 57. An example of

LVDS output timing in reduced range mode is shown in Figure 58.

Figure 57. LVDS Output Timing Example in ANSI-644 Mode (Default)

FCO 500mV/DIV

DCO 500mV/DIV

DATA 500mV/DIV

5ns/DIV

Figure 58. LVDS Output Timing Example in Reduced Range Mode

Rev. 0 | Page 23 of 40

AD9637

Data Sheet

Figure 59 shows an example of the LVDS output using the

ANSI-644 standard (default) data eye and a time interval error

(TIE) jitter histogram with trace lengths of less than 24 inches

on standard FR-4 material.

to drive longer trace lengths, which can be achieved by program-

ming Register 0x15. Even though this option produces sharper

rise and fall times on the data edges and is less prone to bit errors,

it also increases the power dissipation of the DRVDD supply.

300

EYE: ALL BITS

ULS: 8000:448000

EYE: ALL BITS

ULS: 7000:448000

200

100

200

100

0

–100

–200

–300

–100

–200

–300

3.0k

2.5k

2.0k

1.5k

1.0k

0.5k

0

3.0k

2.5k

2.0k

1.5k

1.0k

0.5k

0

Figure 59. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

of Less Than 24 Inches on Standard FR-4, External 100 Ω Far-End

Termination Only

Figure 60. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

Greater Than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only

The default format of the output data is twos complement. Table 10

shows an example of the output coding format. To change the

output data format to offset binary, see the Memory Map section.

Figure 60 shows an example of trace lengths exceeding 24 inches

on standard FR-4 material. Note that the TIE jitter histogram

reflects the decrease of the data eye opening as the edge deviates

from the ideal position.

Data from each ADC is serialized and provided on a separate

channel in DDR mode. The data rate for each serial stream is equal

to 12 bits times the sample clock rate, quantity divided by 2,

with a maximum of 480 Mbps (12 bits × 80 MSPS)/2 = 480 Mbps.

The lowest typical conversion rate is 10 MSPS. See the Memory

Map section for details on enabling this feature.

It is the responsibility of the user to determine if the waveforms

meet the timing budget of the design when the trace lengths exceed

24 inches. Additional SPI options allow the user to further increase

the internal termination (increasing the current) of all eight outputs

Table 10. Digital Output Coding

Input (V)

Condition (V)

< −VREF − 0.5 LSB

= −VREF

Offset Binary Output Mode

Twos Complement Mode

1000 0000 0000

0000 0000 0000

0111 1111 1111

VIN+ − VIN−

0000 0000 0000

1000 0000 0000

1111 1111 1111

= 0

= +VREF − 1.0 LSB

> +VREF − 0.5 LSB

0111 1111 1111

Rev. 0 | Page 24 of 40

Data Sheet

AD9637

Two output clocks are provided to assist in capturing data from

the AD9637. The DCO is used to clock the output data and is equal

to 6× the sample clock (CLK) rate for the default mode of opera-

tion. Data is clocked out of the AD9637 and must be captured

on the rising and falling edges of the DCO that supports double

data rate (DDR) capturing. The FCO is used to signal the start of

a new output byte and is equal to the sample clock rate (see the

Timing Diagrams section).

resolution systems. When changing the resolution to a 10-bit

serial stream, the data stream is shortened. See Figure 3 for the

10-bit example.

In default mode, as shown in Figure 2, the MSB is first in the data

output serial stream. This can be inverted so that the LSB is first

in the data output serial stream by using the SPI.

There are 12 digital output test pattern options available that can

be initiated through the SPI. This is a useful feature when validating

receiver capture and timing (see Table 11 for the output bit

sequencing options that are available). Some test patterns have

two serial sequential words and can be alternated in various ways,

depending on the test pattern chosen. Note that some patterns

do not adhere to the data format select option. In addition,

custom user-defined test patterns can be assigned in the 0x19,

0x1A, 0x1B, and 0x1C register addresses.

When the SPI is used, the DCO phase can be adjusted in 60°

increments relative to the data edge. This enables the user to

refine system timing margins, if required. The default DCO+

and DCO− timing, as shown in Figure 2, is 90° relative to the

output data edge.

A 10-bit serial stream can also be initiated from the SPI. This

allows the user to implement and test compatibility to lower

Table 11. Flexible Output Test Modes

Subject

to Data

Format

Output Test

Mode Bit

Sequence

Pattern Name

Off (default)

Digital Output Word 1

N/A

Digital Output Word 2

Select

N/A

Yes

No

Notes

0000

N/A

0001

Midscale short

1000 0000 0000 (12-bit)

10 0000 0000 (10-bit)

1111 1111 1111 (12-bit)

11 1111 1111 (10-bit)

0000 0000 0000 (12-bit)

00 0000 0000 (10-bit)

1010 1010 1010 (12-bit)

10 1010 1010 (10-bit)

N/A

Offset binary code shown

0010

0011

0100

0101

+Full-scale short

−Full-scale short

Checkerboard

N/A

0101 0101 0101 (12-bit)

01 0101 0101 (10-bit)

N/A

No

PN sequence long¹

Yes

PN23

ITU 0.150

X²³+ X¹⁸+ 1

0110

0111

PN sequence short¹

N/A

Yes

PN9

ITU O.150

X⁹+ X⁵+ 1

One-/zero-word toggle 1111 1111 1111 (12-bit)

11 1111 1111 (10-bit)

0000 0000 0000 (12-bit)

00 0000 0000 (10-bit)

No

1000

1001

User input

Reg. 0ꢀ19 to Reg. 0ꢀ1A

1010 1010 1010 (12-bit)

10 1010 1010 (10-bit)

0000 0011 1111 (12-bit)

00 0001 1111 (10-bit)

1000 0000 0000 (12-bit)

Reg. 0ꢀ1B to Reg. 0ꢀ1C

1-/0-bit toggle

N/A

1010

1011

1× sync

One bit high

Pattern associated with

the eꢀternal pin

10 0000 0000 (10-bit)

N/A

No

Pattern associated with

the eꢀternal pin

1100

Miꢀed frequency

1010 0011 0011 (12-bit)

10 0110 0011 (10-bit)

N/A

No

¹All test mode options eꢀcept PN sequence short and PN sequence long can support 10-bit to 12-bit word lengths to verify data capture to the receiver.

Rev. 0 | Page 25 of 40

AD9637

Data Sheet

The PN sequence short pattern produces a pseudorandom bit

sequence that repeats itself every 2⁹− 1 or 511 bits. A description

of the PN sequence and how it is generated can be found in

Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value

is all 1s (see Table 12 for the initial values). The output is a parallel

representation of the serial PN9 sequence in MSB first format.

The first output word is the first 12 bits of the PN9 sequence in

MSB aligned format.

SCLK/DTP Pin

The SCLK/DTP pin is for use in applications that do not require

SPI mode operation. This pin can enable a single digital test

pattern if it and the CSB pin are both held high during device

power-up. When SCLK/DTP is tied to AVDD, the ADC channel

outputs shift out the following pattern: 1000 0000 0000. The

FCO and DCO function normally while all channels shift out the

repeatable test pattern. This pattern allows the user to perform

timing alignment adjustments among the FCO, DCO, and output

data. This pin has an internal 30 kΩ resistor to GND. It can be

left unconnected for normal operation.

Table 12. PN Sequence

Initial

Value

First Three Output Samples

(MSB First) Twos Complement

Sequence

PN Sequence Short

PN Sequence Long 0ꢀ1FFF 0ꢀ1FE0, 0ꢀ2001, 0ꢀ1C00

0ꢀ1FE0 0ꢀ1DF1, 0ꢀ3CC8, 0ꢀ294E

Table 14. Digital Test Pattern Pin Settings

Selected DTP

Normal Operation

DTP

DTP Voltage

No connect

AVDD

Resulting D x

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 2²³− 1 or 8,388,607 bits. A

description of the PN sequence and how it is generated can be

found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The

seed value is all 1s (see Table 12 for the initial values) and the

AD9637 inverts the bit stream with relation to the ITU standard.

The output is a parallel representation of the serial PN23 sequence

in MSB first format. The first output word is the first 12 bits of the

PN23 sequence in MSB aligned format.

Normal operation

1000 0000 0000

Additional and custom test patterns can also be observed when

commanded from the SPI port. Consult the Memory Map section

for information about the options available.

CSB Pin

The CSB pin should be tied to AVDD for applications that do

not require SPI mode operation. Tying CSB high causes all

SCLK and SDIO information to be ignored.

See the Memory Map section for information on how to change

these additional digital output timing features through the SPI.

RBIAS Pin

To set the internal core bias current of the ADC, place

SDIO/DFS Pin

a 10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin.

For applications that do not require SPI mode operation, the

CSB pin is tied to AVDD, and the SDIO/DFS pin controls the

output data format select operation according to Table 13.

Table 13. Output Data Format Select Pin Settings

DFS Pin Voltage

Output Mode

Twos complement

Offset binary

AVDD

GND (Default)

Rev. 0 | Page 26 of 40

Data Sheet

AD9637

BUILT-IN OUTPUT TEST MODES

ADC is disconnected from the digital back-end blocks and the

test pattern is run through the output formatting block. Some of

the test patterns are subject to output formatting, and some are

not. The PN generators from the PN sequence tests can be reset

by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be

performed with or without an analog signal (if present, the

analog signal is ignored), but they do require an encode clock.

For more information, see the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

The AD9637 includes a built-in test feature designed to enable

verification of the integrity of each data output channel, as well

as to facilitate board level debugging. Various output test options

are provided to place predictable values on the outputs of the

AD9637.

OUTPUT TEST MODES

The output test options are described in Table 17 at Address 0x0D.

When an output test mode is enabled, the analog section of the

Rev. 0 | Page 27 of 40

AD9637

Data Sheet

SERIAL PORT INTERFACE (SPI)

The falling edge of the CSB, in conjunction with the rising edge

of the SCLK, determines the start of the framing. An example of

the serial timing and its definitions can be found in Figure 61

and Table 5.

The AD9637 serial port interface (SPI) allows the user to configure

the converter for specific functions or operations through a

structured register space provided inside the ADC. The SPI

gives the user added flexibility and customization, depending on

the application. Addresses are accessed via the serial port and

can be written to or read from via the port. Memory is organized

into bytes that can be further divided into fields, which are docu-

mented in the Memory Map section. For detailed operational

information, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, which permanently enables the device;

this is called streaming. The CSB can stall high between bytes to

allow for additional external timing. When CSB is tied high, SPI

functions are placed in high impedance mode. This mode turns

on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and its length is determined

by the W0 and W1 bits.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK/DTP pin, the

SDIO/DFS pin, and the CSB pin (see Table 15). The SCLK

(a serial clock) is used to synchronize the read and write data

presented from and to the ADC. The SDIO (serial data input/

output) is a dual-purpose pin that allows data to be sent to and

read from the internal ADC memory map registers. The CSB

(chip select bar) is an active low control that enables or disables

the read and write cycles.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. The first bit of the first byte in

a multibyte serial data transfer frame indicates whether a read

command or a write command is issued. If the instruction is a

readback operation, performing a readback causes the serial

data input/output (SDIO) pin to change direction from an input to

an output at the appropriate point in the serial frame.

Table 15. Serial Port Interface Pins

Function

SCLK Serial clock. The serial shift clock input, which is used to

synchronize serial interface reads and writes.

SDIO Serial data input/output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

All data is composed of 8-bit words. Data can be sent in MSB

first mode or in LSB first mode. MSB first is the default on

power-up and can be changed via the SPI port configuration

register. For more information about this and other features,

see the AN-877 Application Note, Interfacing to High Speed

ADCs via SPI.

CSB

Chip select bar. An active low control that gates the read

and write cycles.

t_HIGH

t_LOW

t_CLK

t_H

t_DS

t_S

t_DH

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 61. Serial Port Interface Timing Diagram

Rev. 0 | Page 28 of 40

Data Sheet

AD9637

pins as static control lines for the output data format, output

HARDWARE INTERFACE

digital test pattern, and power-down feature control. In this

mode, CSB should be connected to AVDD, which disables the

serial port interface.

The pins described in Table 15 comprise the physical interface

between the user programming device and the serial port of the

AD9637. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

When the device is in SPI mode, the PDWN pin (if enabled)

remains active. For SPI control of power-down, the PDWN pin

should be set to its default state.

SPI ACCESSIBLE FEATURES

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in the AN-812 Application Note, Micro-

controller-Based Serial Port Interface (SPI) Boot Circuit.

Table 16 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9637 part-specific features are described in detail

in the Memory Map Register Descriptions section following

Table 17, the external memory map register table.

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used for

other devices, it may be necessary to provide buffers between

this bus and the AD9637 to prevent these signals from transi-

tioning at the converter inputs during critical sampling periods.

Table 16. Features Accessible Using the SPI

Feature Name

Description

Mode

Allows the user to set either power-down

mode or standby mode

Clock

Allows the user to access the DCS, set the

clock divider, set the clock divider phase,

and enable the sync

Some pins serve a dual function when the SPI interface is not

being used. When the pins are strapped to DRVDD or ground

during device power-on, they are associated with a specific

function. Table 16 describes the strappable functions supported

on the AD9637.

Offset

Allows the user to digitally adjust the

converter offset

Test I/O

Allows the user to set test modes to have

known data on output bits

Output Mode

Output Phase

ADC Resolution

Allows the user to set the output mode

Allows the user to set the output clock polarity

Scalable power consumption options based

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,

the SDIO/DFS pin, the SCLK/DTP pin, and the PDWN pin

serve as standalone CMOS-compatible control pins. When the

device is powered up, it is assumed that the user intends to use the

and Speed Grade on resolution and speed grade selection

Rev. 0 | Page 29 of 40

AD9637

Data Sheet

MEMORY MAP

Default Values

READING THE MEMORY MAP REGISTER TABLE

After the AD9637 is reset, critical registers are loaded with

default values. The default values for the registers are given in

Table 17, the memory map register table.

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into three sections: the chip

configuration registers (Address 0x00 to Address 0x02); the

device index and transfer registers (Address 0x05 and Address

0xFF) and the global ADC functions registers, including setup,

control, and test (Address 0x08 to Address 0x109).

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

The memory map register table (see Table 17) lists the default

hexadecimal value for each hexadecimal address shown. The

column with the heading Bit 7 (MSB) is the start of the default

hexadecimal value given. For example, Address 0x05, the device

index register, has a hexadecimal default value of 0x3F. This

means that in Address 0x05, Bits[7:6] = 0, and the remaining

Bits[5:0] = 1. This setting is the default channel index setting.

The default value results in both ADC channels receiving the

next write command. For more information on this function

and others, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI. This application note details the

functions controlled by Register 0x00 to Register 0xFF. The

remaining registers are documented in the Memory Map

Register Descriptions section.

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Channel-Specific Registers

Some channel setup functions, such as the signal monitor

thresholds, can be programmed differently for each channel. In

these cases, channel address locations are internally duplicated

for each channel. These registers and bits are designated in

Table 17 as local. These local registers and bits can be accessed

by setting the appropriate data channel bits (A, B, C, or D) and

the clock channel DCO/FCO bits (Bits[5:4]) in Register 0x05. If

all the bits are set, the subsequent write affects the registers of

all channels and the DCO/FCO clock channels. In a read cycle,

only one of the channels, A, B, C, or D, should be set to read

one of the four registers. If all the bits are set during a SPI read

cycle, the part returns the value for Channel A. Registers and

bits designated as global in Table 17 affect the entire part or the

channel features for which independent settings are not allowed

between channels. The settings in Register 0x05 do not affect

the global registers and bits.

Open Locations

All address and bit locations that are not included in Table 17

are not currently supported for this device. Unused bits of a

valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x05). If the entire address location

is open or not listed in Table 17 (for example, Address 0x13) this

address location should not be written.

Rev. 0 | Page 30 of 40

Data Sheet

AD9637

MEMORY MAP REGISTER TABLE

The AD9637 uses a 3-wire interface and 16-bit addressing and,

therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3

and Bit 4 are set to 1. When Register 0x00, Bit 5 is set high, the

SPI enters a soft reset, where all of the user registers revert to

their default values and Bit 2 is automatically cleared.

Table 17. Memory Map Register Table

Reg.

Addr.

(Hex)

Default

Value

(Hex)

Parameter

Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Comments

Chip Configuration Registers

0ꢀ00

SPI port

configuration

0 = SDO

active

LSB first

Soft reset 1 =

16-bit

address

1 =

16-bit

address

Soft reset

LSB first

0 = SDO

active

0ꢀ18

The nibbles

are mirrored

so that LSB or

MSB first

mode registers

correctly. The

default for

the ADCs is

16-bit mode.

0ꢀ01

0ꢀ02

Chip ID (global)

8-bit chip ID, Bits[7:0]

AD9637 0ꢀ93 = octal 12-bit 40 MSPS/80 MSPS serial LVDS

Read

only

0ꢀ93

Unique chip ID

that is used to

differentiate

devices; read

only.

Chip grade

(global)

Open

Speed grade ID, Bits[6:4]

Open

Read

only

Unique speed

grade ID that

is used to

differentiate

graded

001 = 40 MSPS

100 = 80 MSPS

devices; read

only.

Device Indeꢀ and Transfer Registers

Open

0ꢀ04

0ꢀ05

0ꢀFF

Device Indeꢀ 2

Device Indeꢀ 1

Transfer

Open

Data

Channel H

Data

Channel G

Data

Channel F

Data

Channel E

0ꢀF

Bits are set to

determine

which device

on chip

receives the

neꢀt write

command.

The default is

all devices on

chip.

Open

Clock

Channel

DCO

Clock

Channel

FCO

Data

Channel B

Data

Channel A

0ꢀ3F

Bits are set

to determine

which device

on chip

receives the

neꢀt write

command.

The default is

all devices on

chip.

Channel D Channel C

Open

Initiate

override

0ꢀ00

Set

resolution/

sample rate

override.

Global ADC Functions

0ꢀ08

Power modes

(global)

Eꢀternal

power-

down

Open

Internal power-down

mode

00 = chip run

01 = full power-down

10 = standby

11 = reset

Determines

various

generic

modes of chip

operation.

function

0 = full

power-

down

1 =

standby

0ꢀ09

Clock (global)

Open

Duty cycle

stabilizer

0 = off

0ꢀ01

Turns duty

cycle

stabilizer on

or off.

1 = on

Rev. 0 | Page 31 of 40

AD9637

Data Sheet

Reg.

Addr.

(Hex)

Default

Value

(Hex)

Parameter

Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Comments

0x0B

Clock divide

(global)

Open

Clock divide ratio, Bits[2:0]

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

0x00

The divide

ratio is the

value plus 1.

0x0C

0x0D

Enhancement

control

Open

Reset

Open

Chop

Open

0x00

Enables/

disables chop

mode.

mode

0 = off

1 = on

Test mode (local

except for PN

sequence resets)

User input test mode

00 = single

Reset PN

Output test mode, Bits[3:0] (local)

0000 = off (default)

When set,

the test data

is placed on

the output

pins in place

of normal

data.

long gen PN

short

gen

01 = alternate

0001 = midscale short

0010 = positive FS

0011 = negative FS

10 = single once

11 = alternate once

(affects user input test

mode only,

0100 = alternating checkerboard

0101 = PN 23 sequence

0110 = PN 9 sequence

0111 = one/zero word toggle

1000 = user input

Bits[3:0] = 1000)

1001 = 1-/0-bit toggle

1010 = 1× sync

1011 = one bit high

1100 = mixed bit frequency

0x10

0x14

Offset adjust

(local)

8-bit device offset adjustment, Bits[7:0] (local)

Offset adjust in LSBs from +127 to −128 (twos complement format)

0x00

0x01

Device offset

trim.

Output mode

Open

LVDS-ANSI/

LVDS-IEEE

option

0 = LVDS-

ANSI

Open

Output

invert

(local)

Open

Output

format

0 = offset

binary

1 = twos

comple-

ment

Configures

the outputs

and the

format of the

data.

1 = LVDS-

IEEE reduced

range link

(global)

(see Table 18)

0x15

0x16

Output adjust

Output phase

Open

Output driver

termination, Bits[1:0]

Open

Output

drive

0 = 1× drive

1 = 2× drive

0x00

0x03

Determines

LVDS or other

output

00 = none

01 = 200 Ω

10 = 100 Ω

11 = 100 Ω

properties.

Input clock phase adjust, Bits[6:4]

(value is number of input clock

cycles of phase delay)

Output clock phase adjust, Bits[3:0]

(setting = 0000 through 1011)

(see Table 20)

On devices

that use

global clock

divide,

(see Table 19)

determines

which phase

of the divider

output is

used to

supply the

output clock.

Internal

latching is

unaffected.

0x18

V_REF

Open

Internal V_REFadjustment

digital scheme, Bits[2:0]

000 = 1.0 V p-p

0x04

Selects

and/or

adjusts the

V_REF

.

001 = 1.14 V p-p

010 = 1.33 V p-p

011 = 1.6 V p-p

100 = 2.0 V p-p

Rev. 0 | Page 32 of 40

Data Sheet

AD9637

Reg.

Addr.

(Hex)

Default

Value

(Hex)

Parameter

Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Comments

0ꢀ19

USER_PATT1_LSB

(global)

B7

B6

B5

B4

B3

B2

B1

B0

0ꢀ00

User Defined

Pattern 1 LSB.

0ꢀ1A

USER_PATT1_MS

B (global)

B15

B14

B13

B12

B11

B10

B9

B8

0ꢀ00

User Defined

Pattern 1

MSB.

0ꢀ1B

0ꢀ1C

USER_PATT2_LSB

(global)

B7

B6

B5

B4

B3

B2

B1

B9

B0

B8

0ꢀ00

User Defined

Pattern 2 LSB.

USER_PATT2_MS

B (global)

B15

B14

B13

B12

B11

B10

User Defined

Pattern 2

MSB.

0ꢀ21

Serial control

(global)

LVDS

output LSB

first

Word-wise DDR 1-lane, Bits[6:4]

100 = DDR 1-lane

Open

Serial output number

of bits

0ꢀ42

Serial stream

control.

Default

causes MSB

first and the

native bit

stream.

10 = 12 bits

11 = 10 bits

0ꢀ22

Serial channel

status (local)

Open

Channel

output

reset

Channel

power-

down

0ꢀ00

Used to

power down

individual

sections of

a converter.

0ꢀ100 Resolution/

sample rate

Resolution/

sample rate

override

Resolution

10 = 12 bits

11 = 10 bits

Sample rate

000 = 20 MSPS

001 = 40 MSPS

010 = 50 MSPS

011 = 65 MSPS

100 = 80 MSPS

Resolution/

sample rate

override

(requires

transfer bit,

0ꢀFF).

override

enable

0ꢀ101 User I/O Control 2

0ꢀ102 User I/O Control 3

Open

SDIO

pull-down

0ꢀ00

Disables SDIO

pull-down.

Open

VCM

power-

down

Open

VCM control.

0ꢀ109 Sync

Open

Sync neꢀt

only

Enable

sync

0ꢀ00

Rev. 0 | Page 33 of 40

AD9637

Data Sheet

Output Mode (Register 0x14)

Bit 7—Open

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Register 0x00 to Register 0xFF, see the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

Bit 6—LVDS-ANSI/LVDS-IEEE Option

Setting this bit chooses the LVDS-IEEE (reduced range) option.

The default setting is LVDS-ANSI. As described in Table 18,

when LVDS-ANSI or LVDS-IEEE reduced range link is selected,

the user can select the driver termination. The driver current

is automatically selected to give the proper output swing.

Device Index (Register 0x04 and Register 0x05)

There are certain features in the map that can be set independently

for each channel, whereas other features apply globally to all

channels (depending on context), regardless of which are selected.

The first four bits in Register 0x04 and Register 0x05 can be

used to select which individual data channels are affected. The

output clock channels can be selected in Register 0x05, as well.

A smaller subset of the independent feature list can be applied

to those devices.

Table 18. LVDS-ANSI/LVDS-IEEE Options

Output

Mode,

Bit[6]

Output

Mode

Output Driver

Termination

Output Driver

Current

0

LVDS-ANSI

User selectable

Automatically

selected to give

proper swing

Automatically

selected to give

proper swing

Transfer (Register 0xFF)

All registers except Register 0x100 are updated the moment

they are written. Setting Bit 0 of this transfer register high

initializes the settings in the ADC sample rate override register

(Address 0x100).

1

LVDS-IEEE

reduced

User selectable

range link

Bits[5:3]—Open

Power Modes (Register 0x08)

Bit 2—Output Invert

Bits[7:6]—Open

Setting this bit inverts the output bit stream.

Bit 1—Open

Bit 5—External Power-Down Pin Function

If set, the external PDWN pin initiates standby mode. If cleared,

the external PDWN pin initiates power-down mode.

Bit 0—Output Format

By default, this bit is set to send the data output in twos

complement format. Resetting this bit changes the output mode

to offset binary.

Bits[4:2]—Open

Bits[1:0]—Internal Power-Down Mode

In normal operation (Bits[1:0] = 00), all ADC channels are active.

Output Adjust (Register 0x15)

Bits[7:6]—Open

In power-down mode (Bits[1:0] = 01), the digital data path clocks

are disabled while the digital data path is reset. Outputs are

disabled.

Bits[5:4]—Output Driver Termination

These bits allow the user to select the internal termination

resistor.

In standby mode (Bits[1:0] = 10), the digital data path clocks

and the outputs are disabled.

Bits[3:1]—Open

During a digital reset (Bits[1:0] = 11), all the digital data path

clocks and the outputs (where applicable) on the chip are reset,

except the SPI port. Note that the SPI is always left under

control of the user, that is, it is never automatically disabled or

in reset (except by power-on reset).

Bit 0—Output Drive

Bit 0 of the output adjust register controls the drive strength on

the LVDS driver of the FCO and DCO outputs only. The default

values set the drive to 1×. The drive can be increased to 2× by

setting the appropriate channel bit in Register 0x05 and then

setting Bit 0. These features cannot be used with the output driver

termination select. The termination selection takes precedence

over the 2× driver strength on FCO and DCO when both the

output driver termination and output drive are selected.

Enhancement Control (Register 0x0C)

Bits[7:3]—Open

Bit 2—Chop Mode

For applications that are sensitive to offset voltages and other

low frequency noise, such as homodyne or direct conversion

receivers, chopping in the first stage of the AD9637 is a feature

that can be enabled by setting Bit 2. In the frequency domain,

chopping translates offsets and other low frequency noise to

f

_CLK/2, where they can be filtered.

Bits[1:0]—Open

Rev. 0 | Page 34 of 40

Data Sheet

AD9637

Output Phase (Register 0x16)

Bit 7—Open

Resolution/Sample Rate Override (Register 0x100)

This register is designed to allow the user to downgrade the device.

Any attempt to upgrade the default speed grade results in a chip

power-down. Settings in this register are not initialized until Bit 0

of the transfer register (Register 0xFF) is written high.

Bits[6:4]—Input Clock Phase Adjust

Table 19. Input Clock Phase Adjust Options

Input Clock Phase

Adjust, Bits[6:4]

Number of Input Clock Cycles of

Phase Delay

User I/O Control 2 (Register 0x101)

Bits[7:1]—Open

000 (Default)

001

010

011

100

101

110

111

0

1

2

3

4

5

6

7

Bit 0—SDIO Pull-Down

Bit 0 can be set to disable the internal 30 kꢁ pull-down on the

SDIO pin, which can be used to limit loading when many

devices are connected to the SPI bus.

User I/O Control 3 (Register 0x102)

Bits[7:4]—Open

Bit 3—VCM Power-Down

Bits[3:0]—Output Clock Phase Adjust

Bit 3 can be set high to power down the internal VCM generator.

This feature is used when applying an external reference.

Table 20. Output Clock Phase Adjust Options

Output Clock (DCO), DCO Phase Adjustment

Phase Adjust, Bits[3:0] (Degrees Relative to D x Edge)

Bits[2:0]—Open

0000

0

0001

60

0010

0011 (Default)

0100

0101

0110

0111

1000

1001

1010

120

180

240

300

360

420

480

540

600

660

1011

Rev. 0 | Page 35 of 40

AD9637

Data Sheet

APPLICATIONS INFORMATION

To maximize the coverage and adhesion between the ADC and

PCB, partition the continuous copper plane by overlaying a silk-

screen on the PCB into several uniform sections. This provides

several tie points between the ADC and PCB during the reflow

process, whereas using one continuous plane with no partitions

guarantees only one tie point. For detailed information on

packaging and the PCB layout of chip scale packages, see the

AN-772 Application Note, A Design and Manufacturing Guide

for the Lead Frame Chip Scale Package (LFCSP), at

DESIGN GUIDELINES

Before starting the design and layout of the AD9637 as a system,

it is recommended that the designer become familiar with these

guidelines, which describes the special circuit connections and

layout requirements that are needed for certain pins.

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD9637, it is recommended

that two separate 1.8 V supplies be used. Use one supply for

analog (AVDD); use a separate supply for the digital outputs

(DRVDD). For both AVDD and DRVDD, several different

decoupling capacitors should be used to cover both high and

low frequencies. Place these capacitors close to the point of

entry at the PCB level and close to the pins of the part, with

minimal trace length.

www.analog.com.

VCM

The VCM pin should be decoupled to ground with a 0.1 ꢀF

capacitor.

REFERENCE DECOUPLING

The VREF pin should be externally decoupled to ground with

a low ESR, 1.0 ꢀF capacitor in parallel with a low ESR, 0.1 ꢀF

ceramic capacitor.

A single PCB ground plane should be sufficient when using the

AD9637. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

SPI PORT

EXPOSED PAD THERMAL HEAT SLUG

RECOMMENDATIONS

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9637 to keep these signals from transitioning at the con-

verter inputs during critical sampling periods.

It is required that the exposed pad on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance of the AD9637. An

exposed continuous copper plane on the PCB should mate to

the AD9637 exposed pad, Pin 0. The copper plane should have

several vias to achieve the lowest possible resistive thermal path

for heat dissipation to flow through the bottom of the PCB.

These vias should be solder-filled or plugged.

Rev. 0 | Page 36 of 40

Data Sheet

AD9637

OUTLINE DIMENSIONS

0.60 MAX

9.00

BSC SQ

0.60

MAX

PIN 1

INDICATOR

64

49

1

48

PIN 1

INDICATOR

0.50

BSC

6.35

6.20 SQ

6.05

8.75

BSC SQ

TOP VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.50

0.40

0.30

33

32

16

17

0.25 MIN

7.50

REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

0.30

0.23

0.18

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 62. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range Package Description

Package Option

CP-64-4

AD9637BCPZ-40

AD9637BCPZRL7-40

AD9637BCPZ-80

AD9637BCPZRL7-80

AD9637-80EBZ

−40°C to +85°C

64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. 0 | Page 37 of 40

AD9637

NOTES

Data Sheet

Rev. 0 | Page 38 of 40

Data Sheet

NOTES

AD9637

Rev. 0 | Page 39 of 40

AD9637

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D10215-0-10/11(0)

Rev. 0 | Page 40 of 40


型号：	AD9637BCPZ-40
厂家：	ADI
描述：	Octal, 12-Bit, 40/80 MSPS, Serial LVDS 八通道，12位， 40/80 MSPS ，串行LVDS 转换器模数转换器 PC
文件：	总40页 (文件大小：1081K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9637BCPZ-40 [ADI]

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