AD9643BCPZRL7-250_技术文档

14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V

Dual Analog-to-Digital Converter (ADC)

AD9643

FUNCTIONAL BLOCK DIAGRAM

FEATURES

AVDD

AGND

DRVDD

SNR = 70.6 dBFS at 185 MHz A_INand 250 MSPS

SFDR = 85 dBc at 185 MHz A_INand 250 MSPS

−151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS A_INand

250 MSPS

Total power consumption: 785 mW at 250 MSPS

1.8 V supply voltages

VIN+A

PIPELINE

14-BIT

ADC

D0±

14

.

VIN–A

VCM

PARALLEL

DDR LVDS

AND

AD9643

VIN+B

PIPELINE

14-BIT

ADC

D13±

14

LVDS (ANSI-644 levels) outputs

DRIVERS

VIN–B

Integer 1-to-8 input clock divider (625 MHz maximum input)

Sample rates of up to 250 MSPS

IF sampling frequencies of up to 400 MHz

Internal ADC voltage reference

Flexible analog input range

1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)

ADC clock duty cycle stabilizer

DCO±

OR±

REFERENCE

1 TO 8

CLOCK

DIVIDER

SERIAL PORT

OEB

PDWN

95 dB channel isolation/crosstalk

Serial port control

Energy saving power-down modes

User-configurable, built-in self-test (BIST) capability

SCLK

SDIO

CSB

CLK+

CLK–

SYNC

NOTES

1. THE D0± TO D13± PINS REPRESENT BOTH THE CHANNEL A

AND CHANNEL B LVDS OUTPUT DATA.

Figure 1.

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers (3G)

TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE

I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Ultrasound equipment

Broadband data applications

Programming for setup and control are accomplished using a

3-wire SPI-compatible serial interface.

GENERAL DESCRIPTION

The AD9643 is a dual, 14-bit analog-to-digital converter (ADC)

with sampling speeds of up to 250 MSPS. The AD9643 is designed

to support communications applications, where low cost, small

size, wide bandwidth, and versatility are desired.

The AD9643 is available in a 64-lead LFCSP and is specified over

the industrial temperature range of −40°C to +85°C. This

product is protected by a U.S. patent.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth inputs supporting a variety of

user-selectable input ranges. An integrated voltage reference

eases design considerations. A duty cycle stabilizer is provided

to compensate for variations in the ADC clock duty cycle,

allowing the converters to maintain excellent performance.

PRODUCT HIGHLIGHTS

1. Integrated dual, 14-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.

2. Operation from a single 1.8 V supply and a separate digital

output driver supply accommodating LVDS outputs.

3. Proprietary differential input maintains excellent SNR

performance for input frequencies of up to 400 MHz.

4. SYNC input allows synchronization of multiple devices.

5. 3-pin, 1.8 V SPI port for register programming and register

readback.

The ADC output data is routed directly to the two external

14-bit LVDS output ports and formatted as either interleaved or

channel multiplexed.

6. Pin compatibility with the AD9613, allowing a simple

migration down from 14 bits to 12 bits. This part is also pin

compatible with the AD6649 and the AD6643.

Flexible power-down options allow significant power savings,

when desired.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9643

TABLE OF CONTENTS

Features .............................................................................................. 1

Analog Input Considerations ................................................... 23

Voltage Reference ....................................................................... 25

Clock Input Considerations...................................................... 25

Power Dissipation and Standby Mode .................................... 26

Digital Outputs ........................................................................... 27

Channel/Chip Synchronization.................................................... 28

Serial Port Interface (SPI).............................................................. 29

Configuration Using the SPI..................................................... 29

Hardware Interface..................................................................... 29

SPI Accessible Features.............................................................. 30

Memory Map .................................................................................. 31

Reading the Memory Map Register Table............................... 31

Memory Map Register Table..................................................... 32

Memory Map Register Description ......................................... 34

Applications Information.............................................................. 35

Design Guidelines ...................................................................... 35

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 36

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

ADC DC Specifications............................................................... 3

ADC AC Specifications ............................................................... 4

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings.......................................................... 11

Thermal Characteristics ............................................................ 11

ESD Caution................................................................................ 11

Pin Configurations and Function Descriptions ......................... 12

Typical Performance Characteristics ........................................... 16

Equivalent Circuits......................................................................... 22

Theory of Operation ...................................................................... 23

ADC Architecture ...................................................................... 23

REVISION HISTORY

5/11—Rev. 0 to Rev. A

Changes to Table 2, Worst Other (Harmonic or Spur)

Max Values......................................................................................... 4

4/11—Revision 0: Initial Version

Rev. A | Page 2 of 36

AD9643

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range,

duty cycle stabilizer (DCS) enabled, unless otherwise noted.

Table 1.

AD9643-170

AD9643-210

AD9643-250

Typ

Parameter

Temperature

Min

Typ

Max

Min

Typ

Max

Min

Max

Unit

RESOLUTION

Full

14

Bits

ACCURACY

No Missing Codes

Offset Error

Gain Error

Full

25°C

Full

25°C

Guaranteed

1ꢀ

+2/−6

ꢀ.75

1ꢀ

+3/−5

ꢀ.75

1ꢀ

4

ꢀ.75

mV

%FSR

LSB

Differential Nonlinearity (DNL)

ꢀ.25

1.5

ꢀ.25

1.5

ꢀ.25

1.5

Integral Nonlinearity (INL)¹

1.8

2

3.5

MATCHING CHARACTERISTIC

Offset Error

Gain Error

Full

13

2.5/

+3.5

13

−2/

+3.5

13

−2.5/

+3.5

mV

%FSR

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

15

5ꢀ

15

5ꢀ

15

5ꢀ

ppm/°C

INPUT REFERRED NOISE

VREF = 1.ꢀ V

25°C

1.33

LSB rms

ANALOG INPUT

Input Span

Full

1.75

2.5

2ꢀ

1.75

2.5

2ꢀ

1.75

2.5

2ꢀ

V p-p

pF

kΩ

V

Input Capacitance²

Input Resistance³

Input Common-Mode Voltage

POWER SUPPLIES

Supply Voltage

AVDD

ꢀ.9

Full

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

V

DRVDD

Supply Current

1

I_AVDD

Full

196

145

25ꢀ

16ꢀ

217

16ꢀ

265

185

256

18ꢀ

275

21ꢀ

mA

1

I_DRVDD

POWER CONSUMPTION

Sine Wave Input (DRVDD = 1.8 V) Full

614

9ꢀ

1ꢀ

68ꢀ

9ꢀ

1ꢀ

785

9ꢀ

1ꢀ

mW

Standby Power⁴

Full

Power-Down Power

¹Measured with a low input frequency, full-scale sine wave.

²Input capacitance refers to the effective capacitance between one differential input pin and its complement.

³Input resistance refers to the effective resistance between one differential input pin and its complement.

⁴Standby power is measured with a dc input and the CLK pin inactive (that is, set to AVDD or AGND).

Rev. A | Page 3 of 36

AD9643

ADC AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless

otherwise noted.

Table 2.

AD9643-170

AD9643-210

AD9643-250

Parameter¹

Temperature

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

SIGNAL-TO-NOISE-RATIO (SNR)

f_IN= 3ꢀ MHz

25°C

Full

72.2

72.ꢀ

72.2

72.ꢀ

71.7

dBFS

f_IN= 9ꢀ MHz

7ꢀ.4

69.9

25°C

Full

71.8

71.4

71.6

71.2

71.4

7ꢀ.9

f_IN= 14ꢀ MHz

f_IN= 185 MHz

68.8

f_IN= 22ꢀ MHz

25°C

71.1

7ꢀ.9

7ꢀ.5

SIGNAL-TO-NOISE AND DISTORTION

(SINAD)

f_IN= 3ꢀ MHz

f_IN= 9ꢀ MHz

25°C

Full

71.2

71.ꢀ

71.2

71.ꢀ

7ꢀ.7

dBFS

7ꢀ.4

69.9

f_IN= 14ꢀ MHz

f_IN= 185 MHz

25°C

Full

7ꢀ.8

7ꢀ.4

7ꢀ.6

7ꢀ.2

7ꢀ.4

69.9

67.5

f_IN= 22ꢀ MHz

25°C

7ꢀ.1

69.9

69.5

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 3ꢀ MHz

25°C

11.5

11.4

11.5

11.4

11.3

11.5

11.4

11.3

Bits

f_IN= 9ꢀ MHz

f_IN= 14ꢀ MHz

f_IN= 185 MHz

f_IN= 22ꢀ MHz

WORST SECOND OR THIRD HARMONIC

f_IN= 3ꢀ MHz

25°C

Full

−95

−92

−9ꢀ

−88

dBc

f_IN= 9ꢀ MHz

−78

−8ꢀ

f_IN= 14ꢀ MHz

f_IN= 185 MHz

25°C

Full

−88

−83

−88

−87

−85

−8ꢀ

f_IN= 22ꢀ MHz

25°C

−83

−85

SPURIOUS-FREE DYNAMIC RANGE

(SFDR)

f_IN= 3ꢀ MHz

f_IN= 9ꢀ MHz

25°C

Full

95

92

9ꢀ

88

dBc

78

8ꢀ

f_IN= 14ꢀ MHz

f_IN= 185 MHz

25°C

Full

88

83

88

87

86

85

8ꢀ

f_IN= 22ꢀ MHz

25°C

83

85

WORST OTHER (HARMONIC OR SPUR)

f_IN= 3ꢀ MHz

25°C

Full

−98

−97

−95

−94

−93

dBc

f_IN= 9ꢀ MHz

−78

−8ꢀ

f_IN= 14ꢀ MHz

f_IN= 185 MHz

25°C

Full

−97

−96

−93

−92

−8ꢀ

f_IN= 22ꢀ MHz

25°C

−94

88

−9ꢀ

88

−88

88

TWO-TONE SFDR

f_IN= 184.12 MHz (−7 dBFS ), 187.12

MHz (−7 dBFS )

25°C

dBc

Rev. A | Page 4 of 36

AD9643

AD9643-170

AD9643-210

AD9643-250

Parameter¹

CROSSTALK²

Temperature

Full

Min

Typ

95

Max

Min

Typ

95

Max

Min

Typ

95

Max

Unit

dB

FULL POWER BANDWIDTH³

NOISE BANDWIDTH⁴

25°C

4ꢀꢀ

1ꢀꢀꢀ

4ꢀꢀ

1ꢀꢀꢀ

4ꢀꢀ

1ꢀꢀꢀ

MHz

25°C

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

²Crosstalk is measured at 1ꢀꢀ MHz with −1.ꢀ dBFS on one channel and no input on the alternate channel.

³Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved.

⁴Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise can enter the ADC and is not attenuated internally.

Rev. A | Page 5 of 36

AD9643

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS

enabled, unless otherwise noted.

Table 3.

Parameter

Temp

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

Input Common-Mode Range

High Level Input Current

Low Level Input Current

Input Capacitance

Full

ꢀ.9

3.6

V

V p-p

V

ꢀ.3

AGND

ꢀ.9

−1ꢀ

−22

AVDD

1.4

+22

−1ꢀ

V

μA

pF

kΩ

4

Input Resistance

8

1ꢀ

12

SYNC INPUT

Logic Compliance

Internal Bias

CMOS/LVDS

ꢀ.9

Full

V

Input Voltage Range

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

AGND

1.2

AGND

−5

AVDD

ꢀ.6

V

+5

μA

pF

kΩ

−5

1

16

Input Resistance

12

2ꢀ

LOGIC INPUT (CSB)¹

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

ꢀ

−5

2.1

ꢀ.6

+5

V

μA

kΩ

pF

−8ꢀ

−45

26

2

Input Capacitance

LOGIC INPUT (SCLK)²

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

ꢀ

45

−5

2.1

ꢀ.6

7ꢀ

V

μA

kΩ

pF

+5

26

2

Input Capacitance

LOGIC INPUTS (SDIO)¹

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

ꢀ

45

−5

2.1

ꢀ.6

7ꢀ

V

μA

kΩ

pF

+5

26

5

Input Capacitance

LOGIC INPUTS (OEB, PDWN)²

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

ꢀ

45

−5

2.1

ꢀ.6

7ꢀ

V

μA

kΩ

pF

+5

26

5

Input Capacitance

Rev. A | Page 6 of 36

AD9643

Parameter

Temp

Min

Typ

Max

Unit

DIGITAL OUTPUTS

LVDS Data and OR Outputs

Differential Output Voltage (VOD), ANSI Mode

Output Offset Voltage (VOS),

ANSI Mode

Full

25ꢀ

1.15

35ꢀ

1.25

45ꢀ

1.35

mV

V

Differential Output Voltage (VOD), Reduced Swing Mode

Output Offset Voltage (VOS),

Reduced Swing Mode

Full

15ꢀ

1.15

2ꢀꢀ

1.25

28ꢀ

1.35

mV

V

¹Pull-up.

²Pull-down.

Rev. A | Page 7 of 36

AD9643

SWITCHING SPECIFICATIONS

Table 4.

AD9643-170

AD9643-210

AD9643-250

Parameter

Temp

Min

Typ

Max

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Conversion Rate¹

CLK Period—Divide-by-1 Mode (t_CLK

CLK Pulse Width High (t_CH)

Divide-by-1 Mode, DCS Enabled Full

Full

625

17ꢀ

625

21ꢀ

625

25ꢀ

MHz

MSPS

ns

4ꢀ

5.8

4ꢀ

4.8

4ꢀ

4

)

2.61

2.76

ꢀ.8

2.9

3.19

3.ꢀ5

2.16

2.28

ꢀ.8

2.4

2.64

2.52

1.8

1.9

ꢀ.8

2.ꢀ

2.2

2.1

ns

Divide-by-1 Mode, DCS Disabled

Divide-by-2 Mode Through

Divide-by-8 Mode

Full

Aperture Delay (t_A)

Full

1.ꢀ

ꢀ.1

1.ꢀ

ꢀ.1

1.ꢀ

ꢀ.1

ns

ps rms

Aperture Uncertainty (Jitter, t_J)

DATA OUTPUT PARAMETERS

LVDS Mode

Data Propagation Delay (t_PD)

DCO Propagation Delay (t_DCO

Full

4.8

5.5

ꢀ.7

1ꢀ

1.ꢀ

ꢀ.1

1ꢀ

4.8

5.5

ꢀ.7

1ꢀ

1.ꢀ

ꢀ.1

1ꢀ

4.8

5.5

ꢀ.7

1ꢀ

1.ꢀ

ꢀ.1

1ꢀ

ns

Cycles

ns

ps rms

μs

)

DCO-to-Data Skew (t_SKEW

Pipeline Delay (Latency)

Aperture Delay (t_A)

)

ꢀ.1

1.3

ꢀ.1

1.3

ꢀ.1

1.3

Aperture Uncertainty (Jitter, t_J)

Wake-Up Time (from Standby)

Wake-UpTime (from Power-Down)

Out-of-Range Recovery Time

25ꢀ

3

25ꢀ

3

25ꢀ

3

Cycles

¹Conversion rate is the clock rate after the divider.

Rev. A | Page 8 of 36

AD9643

TIMING SPECIFICATIONS

Table 5.

Parameter

Conditions

Min Typ Max Unit

SYNC TIMING REQUIREMENTS

t_SSYNC

t_HSYNC

SYNC to the rising edge of CLK setup time

SYNC to the rising edge of CLK hold time

ꢀ.3

ꢀ.4

ns

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_{EN_SDIO}

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

Time required for the SDIO pin to switch from an input to an output

relative to the SCLK falling edge

2

4ꢀ

2

1ꢀ

ns

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an input

relative to the SCLK rising edge

1ꢀ

ns

Rev. A | Page 9 of 36

AD9643

Timing Diagrams

t_A

N – 1

N + 4

N + 5

N

N + 3

VIN

N + 1

N + 2

t_CH

t_CLK

CLK+

CLK–

t_DCO

DCO–

DCO+

t_SKEW

t_PD

PARALLEL INTERLEAVED

D0±

(LSB)

CH A

N – 10

CH B

N – 10

CH A

N – 9

CH B

N – 9

CH A

N – 8

CH B

N – 8

CH A

N – 7

CH B

N – 7

CH A

N – 6

.

CHANNEL A AND

.

CHANNEL B

D13±

(MSB)

CH A

N – 10

CH B

N – 10

CH A

N – 9

CH B

N – 9

CH A

N – 8

CH B

N – 8

CH A

N – 7

CH B

N – 7

CH A

N – 6

CHANNEL MULTIPLEXED

(EVEN/ODD) MODE

D0±/D1±

(LSB)

CH A0

N – 10

CH A1

N – 10

CH A0

N – 9

CH A1

N – 9

CH A0

N – 8

CH A1

N – 8

CH A0

N – 7

CH A1

N – 7

CH A0

N – 6

.

CHANNEL A

D12±/D13±

(MSB)

CH A12 CH A13

CH A12 CH A13 CH A12 CH A13

CH A12 CH A13 CH A12

N – 10

N – 9

N – 8

N – 7

N – 6

CHANNEL MULTIPLEXED

(EVEN/ODD) MODE

D0±/D1±

(LSB)

CH B0

N – 10

CH B1

N – 10

CH B0

N – 9

CH B1

N – 9

CH B0

N – 8

CH B1

N – 8

CH B0

N – 7

CH B1

N – 7

CH B0

N – 6

.

CHANNEL B

D12±/D13±

(MSB)

CH B12 CH B13

N – 10 N – 10

CH B12 CH B13 CH B12 CH B13

N – 9 N – 9 N – 8 N – 8

CH B12 CH B13 CH B12

N – 7 N – 7 N – 6

Figure 2. LVDS Modes for Data Output Timing

CLK+

SYNC

t_SSYNC

t_HSYNC

Figure 3. SYNC Timing Inputs

Rev. A | Page 1ꢀ of 36

AD9643

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter

THERMAL CHARACTERISTICS

Rating

The exposed paddle must be soldered to the ground plane for

the LFCSP package. This increases the reliability of the solder

joints, maximizing the thermal capability of the package.

Electrical

AVDD to AGND

DRVDD to AGND

−ꢀ.3 V to +2.ꢀ V

VIN+A/VIN+B, VIN−A/VIN−B to AGND −ꢀ.3 V to AVDD + ꢀ.2 V

Table 7. Thermal Resistance

CLK+, CLK− to AGND

SYNC to AGND

VCM to AGND

−ꢀ.3 V to AVDD + ꢀ.2 V

−ꢀ.3 V to DRVDD + ꢀ.3 V

Airflow

Velocity

(m/sec)

1, 2

1, 3

1, 4

Package Type

θ_JA

θ_JC

1.14

θ_JB

1ꢀ.4

Unit

°C/W

CSB to AGND

64-Lead LFCSP

9 mm × 9 mm

(CP-64-4)

ꢀ

26.8

21.6

2ꢀ.2

SCLK to AGND

SDIO to AGND

OEB to AGND

1.ꢀ

2.ꢀ

¹Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

PDWN to AGND

OR+/OR− to AGND

²Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

³Per MIL-Std 883, Method 1ꢀ12.1.

⁴Per JEDEC JESD51-8 (still air).

Dꢀ−/Dꢀ+ Through D13−/D13+

to AGND

DCO+/DCO− to AGND

Environmental

Operating Temperature Range

(Ambient)

Maximum Junction Temperature

Under Bias

−ꢀ.3 V to DRVDD + ꢀ.3 V

Typical θ_JAis specified for a 4-layer PCB with a solid ground

plane. As shown in Table 7, airflow increases heat dissipation,

which reduces θ_JA. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and

power planes, reduces the θ_JA.

−4ꢀ°C to +85°C

15ꢀ°C

Storage Temperature Range

(Ambient)

−65°C to +125°C

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. A | Page 11 of 36

AD9643

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

CLK+

CLK–

SYNC

DNC

1

2

3

4

5

6

7

8

9

48 PDWN

47 OEB

46 CSB

45 SCLK

44 SDIO

43 OR+

DNC

(LSB) D0–

(LSB) D0+

AD9643

PARALLEL LVDS

TOP VIEW

42 OR–

41 D13+ (MSB)

40 D13– (MSB)

39 D12+

38 D12–

37 DRVDD

36 D11+

35 D11–

34 D10+

33 D10–

(Not to Scale)

DRVDD 10

D1– 11

D1+ 12

D2– 13

D2+ 14

D3– 15

D3+ 16

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE

PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART.

THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND

FOR PROPER OPERATION.

Figure 4. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)

Table 8. Pin Function Descriptions for Interleaved Parallel LVDS Mode

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

1ꢀ, 19, 28, 37

DRVDD

AVDD

DNC

Supply

Digital Output Driver Supply (1.8 V Nominal).

Analog Power Supply (1.8 V Nominal).

49, 5ꢀ, 53, 54, 59, 6ꢀ, 63, 64

4, 5, 6, 7, 55, 56, 58

ꢀ

Do Not Connect. Do not connect to this pin.

AGND,

Exposed Paddle

Ground

Analog Ground. The exposed thermal paddle on the bottom of the

package provides the analog ground for the part. This exposed

paddle must be connected to ground for proper operation.

ADC Analog

51

52

62

61

57

VIN+A

VIN−A

VIN+B

VIN−B

VCM

Input

Output

Differential Analog Input Pin (+) for Channel A.

Differential Analog Input Pin (−) for Channel A.

Differential Analog Input Pin (+) for Channel B.

Differential Analog Input Pin (−) for Channel B.

Common-Mode Level Bias Output for Analog Inputs. This pin

should be decoupled to ground using a ꢀ.1 ꢁF capacitor.

1

2

CLK+

CLK−

Input

ADC Clock Input—True.

ADC Clock Input—Complement.

Digital Input

3

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Digital Outputs

9

8

Dꢀ+ (LSB)

Dꢀ− (LSB)

D1+

D1−

D2+

D2−

D3+

D3−

D4+

Output

Channel A/Channel B LVDS Output Data ꢀ—True.

Channel A/Channel B LVDS Output Data ꢀ—Complement.

Channel A/Channel B LVDS Output Data 1—True.

Channel A/Channel B LVDS Output Data 1—Complement.

Channel A/Channel B LVDS Output Data 2—True.

Channel A/Channel B LVDS Output Data 2—Complement.

Channel A/Channel B LVDS Output Data 3—True.

Channel A/Channel B LVDS Output Data 3—Complement.

Channel A/Channel B LVDS Output Data 4—True.

12

11

14

13

16

15

18

Rev. A | Page 12 of 36

AD9643

Pin No.

Mnemonic

D4−

D5+

D5−

D6+

D6−

D7+

D7−

D8+

Type

Description

17

21

2ꢀ

23

22

27

26

3ꢀ

29

32

31

34

33

36

35

39

38

41

4ꢀ

43

42

25

24

Output

Channel A/Channel B LVDS Output Data 4—Complement.

Channel A/Channel B LVDS Output Data 5—True.

Channel A/Channel B LVDS Output Data 5—Complement.

Channel A/Channel B LVDS Output Data 6—True.

Channel A/Channel B LVDS Output Data 6—Complement.

Channel A/Channel B LVDS Output Data 7—True.

Channel A/Channel B LVDS Output Data 7—Complement.

Channel A/Channel B LVDS Output Data 8—True.

D8−

D9+

D9−

Channel A/Channel B LVDS Output Data 8—Complement.

Channel A/Channel B LVDS Output Data 9—True.

Channel A/Channel B LVDS Output Data 9—Complement.

Channel A/Channel B LVDS Output Data 1ꢀ—True.

Channel A/Channel B LVDS Output Data 1ꢀ—Complement.

Channel A/Channel B LVDS Output Data 11—True.

Channel A/Channel B LVDS Output Data 11—Complement.

Channel A/Channel B LVDS Output Data 12—True.

Channel A/Channel B LVDS Output Data 12—Complement.

Channel A/Channel B LVDS Output Data 13—True.

Channel A/Channel B LVDS Output Data 13—Complement.

Channel A/Channel B LVDS Overrange—True.

D1ꢀ+

D1ꢀ−

D11+

D11−

D12+

D12−

D13+ (MSB)

D13− (MSB)

OR+

OR−

DCO+

DCO−

Channel A/Channel B LVDS Overrange—Complement.

Channel A/Channel B LVDS Data Clock Output—True.

Channel A/Channel B LVDS Data Clock Output—Complement.

SPI Control

45

44

46

SCLK

SDIO

CSB

Input

Input/Output

Input

SPI Serial Clock.

SPI Serial Data I/O.

SPI Chip Select (Active Low).

Output Enable and Power-Down

47

48

OEB

PDWN

Input/Output

Output Enable Input (Active Low).

Power-Down Input (Active High). The operation of this pin

depends on the SPI mode and can be configured as power-down

or standby (see Table 14).

Rev. A | Page 13 of 36

AD9643

PIN 1

INDICATOR

CLK+

CLK–

SYNC

DNC

1

2

3

4

5

6

7

8

9

48 PDWN

47 OEB

46 CSB

45 SCLK

44 SDIO

43 OR+

42 OR–

41 A D12+/D13+ (MSB)

40 A D12–/D13– (MSB)

39 A D10+/D11+

38 A D10–/D11–

37 DRVDD

36 A D8+/D9+

35 A D8–/D9–

34 A D6+/D7+

33 A D6–/D7–

AD9643

CHANNEL

MULTIPLEXED

(EVEN/ODD)

LVDS

DNC

(LSB) B D0–/D1–

(LSB) B D0+/D1+

DRVDD 10

B D2–/D3– 11

B D2+/D3+ 12

B D4–/D5– 13

B D4+/D5+ 14

B D6–/D7– 15

B D6+/D7+ 16

TOP VIEW

(Not to Scale)

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE

PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART.

THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR

PROPER OPERATION.

Figure 5. LFCSP Channel Multiplexed (Even/Odd) LVDS Pin Configuration (Top View)

Table 9. Pin Function Descriptions for Channel Multiplexed (Even/Odd) LVDS Mode

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

1ꢀ, 19, 28, 37

49, 5ꢀ, 53, 54, 59, 6ꢀ, 63, 64

4, 5, 6, 7

DRVDD

AVDD

DNC

Supply

Digital Output Driver Supply (1.8 V Nominal).

Analog Power Supply (1.8 V Nominal).

Do Not Connect. Do not connect to this pin.

ꢀ

AGND,

Exposed Paddle

Ground

Analog Ground. The exposed thermal paddle on the bottom of the

package provides the analog ground for the part. This exposed

paddle must be connected to ground for proper operation.

ADC Analog

51

52

62

61

55

56

58

57

VIN+A

VIN−A

VIN+B

VIN−B

DNC

VCM

Input

Differential Analog Input Pin (+) for Channel A.

Differential Analog Input Pin (−) for Channel A.

Differential Analog Input Pin (+) for Channel B.

Differential Analog Input Pin (−) for Channel B.

Do Not Connect. Do not connect to this pin.

Output

Common-Mode Level Bias Output for Analog Inputs. This pin

should be decoupled to ground using a ꢀ.1 ꢁF capacitor.

1

2

CLK+

CLK−

Input

ADC Clock Input—True.

ADC Clock Input—Complement.

Digital Input

3

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Digital Outputs

8

9

11

12

13

B Dꢀ−/D1− (LSB)

B Dꢀ+/D1+ (LSB)

B D2−/D3−

B D2+/D3+

B D4−/D5−

Output

Channel B LVDS Output Data ꢀ/Data 1—Complement.

Channel B LVDS Output Data ꢀ/Data 1—True.

Channel B LVDS Output Data 2/Data 3—Complement.

Channel B LVDS Output Data 2/Data 3—True.

Channel B LVDS Output Data 4/Data 5—Complement.

Rev. A | Page 14 of 36

AD9643

Pin No.

14

15

16

17

18

2ꢀ

21

22

Mnemonic

B D4+/D5+

B D6−/D7−

B D6+/D7+

B D8−/D9−

B D8+/D9+

B D1ꢀ−/D11−

B D1ꢀ+/D11+

Type

Description

Output

Channel B LVDS Output Data 4/Data 5—True.

Channel B LVDS Output Data 6/Data 7—Complement.

Channel B LVDS Output Data 6/Data 7—True.

Channel B LVDS Output Data 8/Data 9—Complement.

Channel B LVDS Output Data 8/Data 9—True.

Channel B LVDS Output Data 1ꢀ/Data 11—Complement.

Channel B LVDS Output Data 1ꢀ/Data 11—True.

Channel B LVDS Output Data 12/Data 13—Complement.

B D12−/D13−

(MSB)

23

B D12+/D13+

(MSB)

Output

Channel B LVDS Output Data 12/Data 13—True.

26

27

29

3ꢀ

31

32

33

34

35

36

38

39

4ꢀ

A Dꢀ−/D1− (LSB) Output

A Dꢀ+/D1+ (LSB) Output

Channel A LVDS Output Data ꢀ/Data 1—Complement.

Channel A LVDS Output Data ꢀ/Data 1—True.

Channel A LVDS Output Data 2/Data 3—Complement.

Channel A LVDS Output Data 2/Data 3—True.

Channel A LVDS Output Data 4/Data 5—Complement.

Channel A LVDS Output Data 4/Data 5—True.

Channel A LVDS Output Data 6/Data 7—Complement.

Channel A LVDS Output Data 6/Data 7—True.

Channel A LVDS Output Data 8/Data 9—Complement.

Channel A LVDS Output Data 8/Data 9—True.

Channel A LVDS Output Data 1ꢀ/Data 11—Complement.

Channel A LVDS Output Data 1ꢀ/Data 11—True.

Channel A LVDS Output Data 12/Data 13—Complement.

A D2−/D3−

A D2+/D3+

A D4−/D5−

A D4+/D5+

A D6−/D7−

A D6+/D7+

A D8−/D9−

A D8+/D9+

A D1ꢀ−/D11−

A D1ꢀ+/D11+

Output

A D12−/D13−

(MSB)

41

A D12+/D13+

(MSB)

Output

Channel A LVDS Output Data 12/Data 13—True.

43

42

25

24

OR+

OR−

DCO+

DCO−

Output

Channel A/Channel B LVDS Overrange Output—True.

Channel A/Channel B LVDS Overrange Output—Complement.

Channel A/Channel B LVDS Data Clock Output—True.

Channel A/Channel B LVDS Data Clock Output—Complement.

SPI Control

45

SCLK

SDIO

CSB

Input

SPI Serial Clock.

44

46

Input/Output

Input

SPI Serial Data Input/Output.

SPI Chip Select (Active Low).

Output Enable and Power-Down

47

48

OEB

PDWN

Input

Output Enable Input (Active Low).

Power-Down Input (Active High). The operation of this pin

depends on the SPI mode and can be configured as power-

down or standby (see Table 14).

Rev. A | Page 15 of 36

AD9643

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample,

T_A= 25°C, unless otherwise noted.

0

–20

–40

–60

120

170MSPS

SFDR (dBFS)

90.1MHz @ –1dBFS

SNR = 70.8dB (71.8dBFS)

SFDR = 88dBc

100

80

60

SNR (dBFS)

SFDR (dBc)

–80

–100

–120

SECOND HARMONIC

THIRD HARMONIC

40

20

0

SNR (dBc)

–140

0

10

20

30

40

50

60

70

80

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 9. AD9643-170 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN) with

f_IN= 90.1 MHz

Figure 6. AD9643-170 Single-Tone FFT with f_IN= 90.1 MHz

100

0

170MSPS

185.1MHz @ –1dBFS

SNR = 69.8dB (70.8dBFS)

SFDR = 85dBc

SFDR (dBc)

95

–20

90

–40

–60

85

80

THIRD HARMONIC

SECOND HARMONIC

–80

–100

–120

75

SNR (dBFS)

70

65

60

–140

60

90 120 150 180 210 240 270 300 330 360 390

FREQUENCY (MHz)

0

10

20

30

40

50

60

70

80

FREQUENCY (MHz)

Figure 10. AD9643-170 Single-Tone SNR/SFDR vs. Input Frequency (f_IN

)

Figure 7. AD9643-170 Single-Tone FFT with f_IN= 185.1 MHz

0

170MSPS

305.1MHz @ –1dBFS

SNR = 68.3dB (69.3dBFS)

–20

SFDR = 79dBc

SFDR (dBc)

–40

SECOND HARMONIC

IMD3 (dBc)

–60

THIRD HARMONIC

–60

–80

–100

SFDR (dBFS)

–100

–120

–140

IMD3 (dBFS)

–120

–90.0

–78.5

–67.0

–55.5

–44.0

–32.5

–21.0

–7.0

0

10

20

30

40

50

60

70

80

INPUT AMPLITUDE (dBFS)

FREQUENCY (MHz)

Figure 8. AD9643-170 Single-Tone FFT with f_IN= 305.1 MHz

Figure 11. AD9643-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with

f_IN1= 89.12, f_IN2= 92.12 MHz, f_S= 170 MSPS

Rev. A | Page 16 of 36

AD9643

100

95

0

–20

–40

–60

–80

SFDR (dBc)

90

85

IMD3 (dBc)

SFDR, CHANNEL B

SNR, CHANNEL B

SFDR, CHANNEL A

SNR, CHANNEL A

80

75

70

SFDR (dBFS)

IMD3 (dBFS)

–100

–120

–90.0

–78.5

–67.0

–55.5

–44.0

–32.5

–21.0

–7.0

40 50 60 70 80 90 100 110 120 130 140 150 160 170

INPUT AMPLITUDE (dBFS)

SAMPLE RATE (MSPS)

Figure 12. AD9643-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with

f_IN1= 184.12, f_IN2= 187.12 MHz, f_S= 170 MSPS

Figure 15. AD9643-170 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 90.1 MHz

6000

0

170MSPS

89.12MHz @ –7dBFS

92.12MHz @ –7dBFS

SFDR = 89dBc (96dBFS)

1.34LSB rms

16,379 TOTAL HITS

–20

5000

–40

4000

3000

–60

–80

–100

–120

2000

1000

0

–140

N – 5 N – 4 N – 3 N – 2 N – 1

N

N + 1 N + 2 N + 3 N + 4 N + 5

0

10

20

30

40

50

60

70

80

OUTPUT CODE

FREQUENCY (MHz)

Figure 13. AD9643-170 Two-Tone FFT with f_IN1= 89.12, f_IN2= 92.12 MHz,

f_S= 170 MSPS

Figure 16. AD9643-170 Grounded Input Histogram

0

–20

–40

–60

170MSPS

184.12MHz @ –7dBFS

187.12MHz @ –7dBFS

SFDR = 84dBc (91dBFS)

210MSPS

90.1MHz @ –1dBFS

SNR = 70.6dB (71.6dBFS)

SFDR = 88dBc

–20

–40

–60

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

–80

–100

–120

–140

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

90

100

FREQUENCY (MHz)

FREQUENCY (Hz)

Figure 14. AD9643-170 Two-Tone FFT with f_IN1= 184.12, f_IN2= 187.12 MHz,

f_S= 170 MSPS

Figure 17. AD9643-210 Single-Tone FFT with f_IN= 90.1 MHz

Rev. A | Page 17 of 36

AD9643

0

–20

–40

–60

100

95

210MSPS

185.1MHz @ –1dBFS

SNR = 70.3dB (71.3dBFS)

SFDR = 86dBc

SFDR (dBc)

90

85

80

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

75

70

65

60

SNR (dBFS)

–140

0

60

90 120 150 180 210 240 270 300 330 360 390

FREQUENCY (MHz)

10

20

30

40

50

60

70

80

90

100

FREQUENCY (MHz)

Figure 18. AD9643-210 Single-Tone FFT with f_IN= 185.1 MHz

Figure 21. AD9643-210 Single-Tone SNR/SFDR vs. Input Frequency (f_IN)

0

210MSPS

305.1MHz @ –1dBFS

SNR = 67.3dB (68.3dBFS)

–20

SFDR = 75dBc

SFDR (dBc)

–40

THIRD HARMONIC

–60

IMD3 (dBc)

–60

SECOND HARMONIC

–80

–100

–120

–80

SFDR (dBFS)

–100

IMD3 (dBFS)

–120

–90.0

–140

0

10

20

30

40

50

60

70

80

–78.5

–67.0

–55.5

–44.0

–32.5

–21.0

–7.0

90

100

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 22. AD9643-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN

)

Figure 19. AD9643-210 Single-Tone FFT with f_IN= 305.1 MHz

with f_IN1= 89.12, f_IN2= 92.12 MHz, f_S= 210 MSPS

120

0

SFDR (dBFS)

100

–20

SFDR (dBc)

–40

80

60

SNR (dBFS)

IMD3 (dBc)

–60

SFDR (dBc)

–80

40

20

0

SFDR (dBFS)

SNR (dBc)

–100

IMD3 (dBFS)

–120

–90.0

–78.5

–67.0

–55.5

–44.0

–32.5

–21.0

–7.0

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

INPUT AMPLITUDE (dBFS)

Figure 20. AD9643-210 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

Figure 23. AD9643-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN

)

with f_IN= 90.1 MHz

with f_IN1= 184.12, f_IN2= 187.12 MHz, f_S= 210 MSPS

Rev. A | Page 18 of 36

AD9643

0

–20

–40

–60

5000

4500

4000

3500

210MSPS

1.44LSB rms

16,378 TOTAL HITS

89.12MHz @ –7dBFS

92.12MHz @ –7dBFS

SFDR = 88dBc (95dBFS)

3000

2500

2000

1500

1000

–80

–100

–120

500

0

–140

0

10

20

30

40

50

60

70

80

N – 5 N – 4 N – 3 N – 2 N – 1

N

N + 1 N + 2 N + 3 N + 4 N + 5

90

100

FREQUENCY (MHz)

OUTPUT CODE

Figure 24. AD9643-210 Two-Tone FFT with f_IN1= 89.12, f_IN2= 92.12 MHz,

f_S= 210 MSPS

Figure 27. AD9643-210 Grounded Input Histogram

0

–20

–40

–60

210MSPS

184.12MHz @ –7dBFS

187.12MHz @ –7dBFS

SFDR = 88dBc (95dBFS)

250MSPS

90.1MHz @ –1dBFS

SNR = 70.6dB (71.6dBFS)

SFDR = 88dBc

–20

–40

–60

THIRD HARMONIC

SECOND HARMONIC

–80

–100

–120

–80

–100

–120

–140

0

10

20

30

40

50

60

70

80

0

10 20 30 40 50 60 70 80 90 100 110 120

FREQUENCY (MHz)

90

100

FREQUENCY (MHz)

Figure 25. AD9643-210 Two-Tone FFT with f_IN1= 184.12, f_IN2= 187.12 MHz,

f_S= 210 MSPS

Figure 28. AD9643-250 Single-Tone FFT with f_IN= 90.1 MHz

100

95

0

250MSPS

185.1MHz @ –1dBFS

SNR = 70.6dB (71.6dBFS)

SFDR = 85dBc

–20

–40

90

85

–60

THIRD HARMONIC

SECOND HARMONIC

–80

SNR, CHANNEL B

SFDR, CHANNEL B

80

SNR, CHANNEL A

SFDR, CHANNEL A

–100

75

–120

–140

70

40

60

80

100

120

140

160

180

200

0

10 20 30 40 50 60 70 80 90 100 110 120

FREQUENCY (MHz)

SAMPLE RATE (MSPS)

Figure 26. AD9643-210 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 90.1 MHz

Figure 29. AD9643-250 Single-Tone FFT with f_IN= 185.1 MHz

Rev. A | Page 19 of 36

AD9643

0

–20

–40

–60

0

–20

–40

–60

–80

250MSPS

305.1MHz @ –1dBFS

SNR = 68.6dB (71.6dBFS)

SFDR = 83dBc

SFDR (dBc)

IMD3 (dBc)

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

SFDR (dBFS)

IMD3 (dBFS)

–100

–120

–140

0

10 20 30 40 50 60 70 80 90 100 110 120

FREQUENCY (MHz)

–90.0

–78.5

–67.0

–55.5

–44.0

–32.5

–21.0

–7.0

INPUT AMPLITUDE (dBFS)

Figure 30. AD9643-250 Single-Tone FFT with f_IN= 305.1 MHz

Figure 33. AD9643-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN

)

with f_IN1= 89.12, f_IN2= 92.12 MHz, f_S= 250 MSPS

120

0

SFDR (dBFS)

100

–20

SFDR (dBc)

80

60

–40

SNR (dBFS)

IMD3 (dBc)

–60

SFDR (dBc)

–80

40

20

0

SFDR (dBFS)

SNR (dBc)

–100

IMD3 (dBFS)

–120

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

–90.0

–78.5

–67.0

–55.5

–44.0

–32.5

–21.0

–7.0

INPUT AMPLITUDE (dBFS)

Figure 31. AD9643-250 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

Figure 34. AD9643-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN

)

with f_IN= 185.1 MHz

with f_IN1= 184.12, f_IN2= 187.12 MHz, f_S= 250 MSPS

0

100

95

250MSPS

89.12MHz @ –7dBFS

92.12MHz @ –7dBFS

–20

SFDR = 87dBc (94dBFS)

SFDR (dBc)

90

–40

85

80

–60

–80

–100

–120

75

SNR (dBFS)

70

65

60

–140

60

80 100 120 140 160 180 200 220 240 260

FREQUENCY (MHz)

0

10 20 30 40 50 60 70 80 90 100 110 120

FREQUENCY (MHz)

Figure 35. AD9643-250 Two-Tone FFT with f_IN1= 89.12, f_IN2= 92.12 MHz,

f_S= 250 MSPS

Figure 32. AD9643-250 Single-Tone SNR/SFDR vs. Input Frequency (f_IN

)

Rev. A | Page 2ꢀ of 36

AD9643

0

–20

–40

–60

5000

4500

4000

3500

250MSPS

1.33LSB rms

16,378 TOTAL HITS

184.12MHz @ –7dBFS

187.12MHz @ –7dBFS

SFDR = 87dBc (94dBFS)

3000

2500

2000

1500

1000

–80

–100

–120

500

0

–140

0

10 20 30 40 50 60 70 80 90 100 110 120

FREQUENCY (MHz)

N – 5 N – 4 N – 3 N – 2 N – 1

N

N + 1 N + 2 N + 3 N + 4 N + 5

OUTPUT CODE

Figure 36. AD9643-250 Two-Tone FFT with f_IN1= 184.12, f_IN2= 187.12 MHz,

f_S= 250 MSPS

Figure 38. AD9643-250 Grounded Input Histogram

100

95

90

85

SNR, CHANNEL B

SFDR, CHANNEL B

SNR, CHANNEL A

80

SFDR, CHANNEL A

75

70

40

60

80 100 120 140 160 180 200 220 240

SAMPLE RATE (MSPS)

Figure 37. AD9643-250 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 90.1 MHz

Rev. A | Page 21 of 36

AD9643

EQUIVALENT CIRCUITS

AVDD

350Ω

26kΩ

SCLK

OR

PDWN

VIN

Figure 39. Equivalent Analog Input Circuit

Figure 43. Equivalent SCLK or PDWN Input Circuit

AVDD

26kΩ

0.9V

CSB

OR

OEB

350Ω

15kΩ

CLK+

CLK–

Figure 44. Equivalent CSB Input Circuit

Figure 40. Equivalent Clock lnput Circuit

DRVDD

AVDD

V+

DATAOUT–

V–

DATAOUT+

V+

SYNC

0.9V

16kΩ

0.9V

Figure 41. Equivalent LVDS Output Circuit

Figure 45. Equivalent SYNC Input Circuit

DRVDD

350Ω

SDIO

26kΩ

Figure 42. Equivalent SDIO Circuit

Rev. A | Page 22 of 36

AD9643

THEORY OF OPERATION

A small resistor in series with each input can help reduce the

The AD9643 has two analog input channels and two digital

output channels. The intermediate frequency (IF) signal passes

through several stages before appearing at the output port(s).

peak transient current required from the output stage of the

driving source. A shunt capacitor can be placed across the

inputs to provide dynamic charging currents. This passive

network creates a low-pass filter at the ADC input; therefore,

the precise values are dependent on the application.

The dual ADC design can be used for diversity reception of signals,

where the ADCs operate identically on the same carrier but from

two separate antennae. The ADCs can also be operated with

independent analog inputs. The user can sample frequencies

from dc to 300 MHz using appropriate low-pass or band-pass

filtering at the ADC inputs with little loss in ADC performance.

Operation to 400 MHz analog input is permitted but occurs at

the expense of increased ADC noise and distortion.

In intermediate frequency (IF) undersampling applications, the

shunt capacitors should be reduced. In combination with the

driving source impedance, the shunt capacitors limit the input

bandwidth. Refer to the AN-742 Application Note, Frequency

Domain Response of Switched-Capacitor ADCs; the AN-827

Application Note, A Resonant Approach to Interfacing Amplifiers to

Switched-Capacitor ADCs; and the Analog Dialogue article,

“Transformer-Coupled Front-End for Wideband A/D Converters,”

for more information on this subject.

Synchronization capability is provided to allow synchronized

timing between multiple devices.

Programming and control of the AD9643 are accomplished

using a 3-pin, SPI-compatible serial interface.

BIAS

S

ADC ARCHITECTURE

S

C

FB

S

The AD9643 architecture consists of a dual front-end sample-

and-hold circuit, followed by a pipelined switched-capacitor

ADC. The quantized outputs from each stage are combined into

a final 14-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate on a new input

sample and the remaining stages to operate on the preceding

samples. Sampling occurs on the rising edge of the clock.

VIN+

VIN–

C

PAR1

C

PAR2

H

S

C

S

C

FB

C

PAR1

PAR2

S

BIAS

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor digital-

to-analog converter (DAC) and an interstage residue amplifier

(MDAC). The MDAC magnifies the difference between the recon-

structed DAC output and the flash input for the next stage in

the pipeline. One bit of redundancy is used in each stage to

facilitate digital correction of flash errors. The last stage simply

consists of a flash ADC.

Figure 46. Switched-Capacitor Input

For best dynamic performance, the source impedances driving

VIN+ and VIN− should be matched, and the inputs should be

differentially balanced.

Input Common Mode

The analog inputs of the AD9643 are not internally dc biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that V_CM= 0.5 × AVDD (or

0.9 V) is recommended for optimum performance. An on-board

common-mode voltage reference is included in the design and is

available from the VCM pin. Using the VCM output to set the

input common mode is recommended. Optimum performance

is achieved when the common-mode voltage of the analog input

is set by the VCM pin voltage (typically 0.5 × AVDD). The

VCM pin must be decoupled to ground by a 0.1 μF capacitor, as

described in the Applications Information section. This

decoupling capacitor should be placed close to the pin to

minimize the series resistance and inductance between the part

and this capacitor.

The input stage of each channel contains a differential sampling

circuit that can be ac- or dc-coupled in differential or single-

ended modes. The output staging block aligns the data, corrects

errors, and passes the data to the output buffers. The output buffers

are powered from a separate supply, allowing digital output noise to

be separated from the analog core. During power-down, the

output buffers go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9643 is a differential switched-

capacitor circuit that has been designed for optimum performance

while processing a differential input signal.

The clock signal alternatively switches the input between sample

mode and hold mode (see the configuration shown in Figure 46).

When the input is switched into sample mode, the signal source

must be capable of charging the sampling capacitors and settling

within 1/2 clock cycle.

Differential Input Configurations

Optimum performance is achieved while driving the AD9643

in a differential input configuration. For baseband applications,

the AD8138, ADA4937-2, ADA4938-2, and ADA4930-2

Rev. A | Page 23 of 36

AD9643

differential drivers provide excellent performance and a flexible

interface to the ADC.

the recommended input configuration (see Figure 50). In this

configuration, the input is ac-coupled and the VCM voltage is

provided to each input through a 33 Ω resistor. These resistors

compensate for losses in the input baluns to provide a 50 Ω

impedance to the driver.

The output common-mode voltage of the ADA4930-2 is easily

set with the VCM pin of the AD9643 (see Figure 47), and the

driver can be configured in a Sallen-Key filter topology to

provide band-limiting of the input signal.

15pF

In the double balun and transformer configurations, the value of

the input capacitors and resistors is dependent on the input fre-

quency and source impedance. Based on these parameters, the

value of the input resistors and capacitors may need to be adjusted

or some components may need to be removed. Table 10 displays

recommended values to set the RC network for different input

frequency ranges. However, these values are dependent on the

input signal and bandwidth and should be used only as a

starting guide. Note that the values given in Table 10 are for each

R1, R2, C2, and R3 component shown in Figure 48 and Figure 50.

200Ω

33Ω

5pF

15Ω

90Ω

VIN–

VIN+

AVDD

ADC

VCM

76.8Ω

VIN

ADA4930-2

0.1µF

33Ω

15Ω

120Ω

15pF

200Ω

33Ω

0.1µF

Table 10. Example RC Network

Figure 47. Differential Input Configuration Using the ADA4930-2

Frequency R1

C1

R2

Series

(Ω)

C2

Shunt

(pF)

R3

Shunt

(Ω)

Range

(MHz)

Series

(Ω)

Differential

(pF)

For baseband applications where SNR is a key parameter,

differential transformer coupling is the recommended input

configuration. An example is shown in Figure 48. To bias the

analog input, the VCM voltage can be connected to the center

tap of the secondary winding of the transformer.

ꢀ to 1ꢀꢀ

33

8.2

3.9

ꢀ

15

49.9

1ꢀꢀ to 3ꢀꢀ 15

8.2

An alternative to using a transformer-coupled input at frequencies

in the second Nyquist zone is to use an amplifier with variable

gain. The AD8375 or AD8376 digital variable gain amplifier

(DVGAs) provides good performance for driving the AD9643.

Figure 49 shows an example of the AD8376 driving the AD9643

through a band-pass antialiasing filter.

C2

R3

R2

VIN+

R1

2V p-p

49.9Ω

C1

R1

ADC

VCM

R2

VIN–

1000pF 180nH 220nH

0.1µF

33Ω

0.1µF

R3

1µH

165Ω

15pF

C2

VPOS

1nF

AD9643

AD8376

5.1pF

3.9pF

VCM

1nF

2.5kΩ║2pF

Figure 48. Differential Transformer-Coupled Configuration

301Ω

1µH

68nH

The signal characteristics must be considered when selecting

a transformer. Most RF transformers saturate at frequencies

below a few megahertz. Excessive signal power can also cause

core saturation, which leads to distortion.

180nH 220nH

®

1000pF

NOTES

1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS WITH THE

EXCEPTION OF THE 1µH CHOKE INDUCTORS (COIL CRAFT 0603LS).

2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER

CENTERED AT 140MHz.

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

the true SNR performance of the AD9643. For applications where

SNR is a key parameter, differential double balun coupling is

Figure 49. Differential Input Configuration Using the AD8376

C2

R3

0.1µF

R1

R2

VIN+

2V p-p

33Ω

P

A

S

P

C1

R1

ADC

0.1µF

VCM

VIN–

R3

33Ω

0.1µF

C2

Figure 50. Differential Double Balun Input Configuration

Rev. A | Page 24 of 36

AD9643

VOLTAGE REFERENCE

25Ω

A stable and accurate voltage reference is built into the AD9643.

The full-scale input range can be adjusted by varying the

reference voltage via SPI. The input span of the ADC tracks

reference voltage changes linearly.

ADC

CLK+

390pF

1nF

390pF

CLOCK

INPUT

CLK–

SCHOTTKY

DIODES:

HSMS2822

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9643 sample clock inputs,

CLK+ and CLK−, should be clocked with a differential signal.

The signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or via capacitors. These pins are biased internally

(see Figure 51) and require no external bias. If the inputs are

floated, the CLK− pin is pulled low to prevent spurious clocking.

AVDD

Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)

If a low jitter clock source is not available, another option is to

ac-couple a differential PECL signal to the sample clock input

pins as shown in Figure 54. The AD9510, AD9511, AD9512,

AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520,

AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/

ADCLK925 clock drivers offer excellent jitter performance.

0.9V

ADC

CLK+

0.1µF

CLOCK

INPUT

CLK+

CLK–

AD95xx

PECL DRIVER

100Ω

4pF

0.1µF

CLOCK

INPUT

CLK–

240Ω

50kΩ

Figure 51. Simplified Equivalent Clock Input Circuit

Figure 54. Differential PECL Sample Clock (Up to 625 MHz)

Clock Input Options

A third option is to ac-couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 55. The AD9510,

AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517,

AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers

offer excellent jitter performance.

The AD9643 has a very flexible clock input structure. Clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter

is of the most concern, as described in the Jitter Considerations

section.

Figure 52 and Figure 53 show two preferable methods for

clocking the AD9643 (at clock rates of up to 625 MHz). A low

jitter clock source is converted from a single-ended signal to a

differential signal using an RF balun or RF transformer.

ADC

CLK+

0.1µF

CLOCK

INPUT

AD95xx

LVDS DRIVER

100Ω

0.1µF

CLOCK

INPUT

CLK–

50kΩ

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 625 MHz, and the RF transformer is recom-

mended for clock frequencies from 10 MHz to 200 MHz. The

back-to-back Schottky diodes across the transformer secondary

limit clock excursions into the AD9643 to approximately 0.8 V p-p

differential. This limit helps prevent the large voltage swings of

the clock from feeding through to other portions of the AD9643

while preserving the fast rise and fall times of the signal, which

are critical to low jitter performance.

Figure 55. Differential LVDS Sample Clock (Up to 625 MHz)

Input Clock Divider

The AD9643 contains an input clock divider with the ability to

divide the input clock by integer values between 1 and 8. The

duty cycle stabilizer (DCS) is enabled by default on power-up.

The AD9643 clock divider can be synchronized using the external

SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock

divider to be resynchronized on every SYNC signal or only on

the first SYNC signal after the register is written. A valid SYNC

causes the clock divider to reset to its initial state. This synchro-

nization feature allows multiple parts to have their clock dividers

aligned to guarantee simultaneous input sampling.

®

Mini-Circuits

ADT1-1WT, 1:1Z

ADC

390pF

XFMR

CLOCK

INPUT

CLK+

CLK–

100Ω

50Ω

SCHOTTKY

DIODES:

HSMS2822

Figure 52. Transformer-Coupled Differential Clock (Up to 200 MHz)

Rev. A | Page 25 of 36

AD9643

Clock Duty Cycle

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal controlled oscillators make

the best clock sources. If the clock is generated from another type

of source (by gating, dividing, or another method), it should be

retimed by the original clock at the last step.

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals and, as a result, may be sensitive to

clock duty cycle. Commonly, a 5% tolerance is required on the

clock duty cycle to maintain dynamic performance characteristics.

The AD9643 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows the user to

provide a wide range of clock input duty cycles without affecting

the performance of the AD9643.

Refer to the AN-501 Application Note, Aperture Uncertainty and

ADC System Performance, and the AN-756 Application Note,

Sampled Systems and the Effects of Clock Phase Noise and Jitter, for

more information about jitter performance as it relates to ADCs.

POWER DISSIPATION AND STANDBY MODE

Jitter on the rising edge of the input clock is still of paramount

concern and is not reduced by the duty cycle stabilizer. The duty

cycle control loop does not function for clock rates less than

40 MHz nominally. The loop has a time constant associated

with it that must be considered when the clock rate can change

dynamically. A wait time of 1.5 μs to 5 μs is required after a

dynamic clock frequency increase or decrease before the DCS

loop is relocked to the input signal. During the time period that

the loop is not locked, the DCS loop is bypassed, and internal

device timing is dependent on the duty cycle of the input clock

signal. In such applications, it may be appropriate to disable the

duty cycle stabilizer. In all other applications, enabling the DCS

circuit is recommended to maximize ac performance.

As shown in Figure 57, the power dissipated by the AD9643 is

proportional to its sample rate. The data in Figure 57 was taken

using the same operating conditions as those used for the Typical

Performance Characteristics section.

0.8

0.5

0.4

0.3

0.2

TOTAL POWER

0.7

0.6

0.5

0.4

0.3

I

AVDD

I

Jitter Considerations

DRVDD

0.2

0.1

0

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given input

frequency (f_IN) due to jitter (t_J) can be calculated by

0.1

0

40

60

80

100 120 140 160 180 200 220 240

ENCODE FREQUENCY (MSPS)

SNR_HF= −10 log[(2π × f_IN× t_JRMS)²+ 10 ^{(−SNR /10)}

]

LF

Figure 57. AD9643-250 Power and Current vs. Sample Rate

In the equation, the rms aperture jitter represents the root-

mean-square of all jitter sources, which include the clock input,

the analog input signal, and the ADC aperture jitter specification.

IF undersampling applications are particularly sensitive to jitter,

as shown in Figure 56.

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD9643 is placed in power-down

mode. In this state, the ADC typically dissipates 10 mW. During

power-down, the output drivers are placed in a high impedance

state. Asserting the PDWN pin low returns the AD9643 to its

normal operating mode. Note that PDWN is referenced to the

digital output driver supply (DRVDD) and should not exceed

that supply voltage.

80

75

70

65

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and then must be recharged when returning

to normal operation. As a result, wake-up time is related to the

time spent in power-down mode, and shorter power-down

cycles result in proportionally shorter wake-up times.

60

55

50

0.05ps

0.2ps

0.5ps

1ps

1.5ps

MEASURED

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map Register

Description section and the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI, for additional details.

1

10

100

1000

INPUT FREQUENCY (MHz)

Figure 56. AD9643-250 SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9643.

Rev. A | Page 26 of 36

AD9643

bar bit (Bit 4) in Register 0x14. Because the output data is

DIGITAL OUTPUTS

interleaved, if only one of the two channels is disabled, the output

data of the remaining channel is repeated in both the rising and

falling output clock cycles.

The AD9643 output drivers can be configured for either ANSI

LVDS or reduced drive LVDS using a 1.8 V DRVDD supply.

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI

control.

Timing

The AD9643 provides latched data with a pipeline delay of 10 input

sample clock cycles. Data outputs are available one propagation

delay (t_PD) after the rising edge of the clock signal.

Digital Output Enable Function (OEB)

The length of the output data lines and loads placed on them

should be minimized to reduce transients within the AD9643.

These transients can degrade converter dynamic performance.

The AD9643 has a flexible three-state ability for the digital

output pins. The three-state mode is enabled using the OEB pin

or through the SPI interface. If the OEB pin is low, the output

data drivers are enabled. If the OEB pin is high, the output data

drivers are placed in a high impedance state. This OEB function

is not intended for rapid access to the data bus. Note that OEB

is referenced to the digital output driver supply (DRVDD) and

should not exceed that supply voltage.

The lowest typical conversion rate of the AD9643 is 40 MSPS. At

clock rates below 40 MSPS, dynamic performance may degrade.

Data Clock Output (DCO)

The AD9643 also provides data clock output (DCO) intended

for capturing the data in an external register. Figure 2 shows a

graphical timing diagram of the AD9643 output modes.

When using the SPI interface, the data outputs of each channel

can be independently three-stated by using the output enable

Table 11. Output Data Format

VIN+ − VIN−,

Input Span = 1.75 V p-p (V)

Input (V)

Offset Binary Output Mode

ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

11 1111 1111 1111

Twos Complement Mode (Default)

1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

ꢀ1 1111 1111 1111

OR

1

ꢀ

VIN+ − VIN−

<–ꢀ.875

–ꢀ.875

ꢀ

+ꢀ.875

>+ꢀ.875

ꢀ1 1111 1111 1111

1

Rev. A | Page 27 of 36

AD9643

CHANNEL/CHIP SYNCHRONIZATION

The AD9643 has a SYNC input that allows the user flexible

synchronization options for synchronizing the internal blocks.

The SYNC feature is useful for guaranteeing synchronized

operation across multiple ADCs. The input clock divider can be

synchronized using the SYNC input. The divider can be enabled

to synchronize on a single occurrence of the SYNC signal or on

every occurrence by setting the appropriate bits in Register 0x3A.

The SYNC input is internally synchronized to the sample clock.

However, to ensure that there is no timing uncertainty between

multiple parts, the SYNC input signal should be synchronized

to the input clock signal. The SYNC input should be driven

using a single-ended CMOS type signal.

Using Bit 1 in Register 0x59, the SYNC input can be set to either

level or edge sensitive mode. If the SYNC input is set to edge

sensitive mode, Bit 0 of Register 0x59 can be used to determine

whether the rising or falling edge is used.

Rev. A | Page 28 of 36

AD9643

SERIAL PORT INTERFACE (SPI)

The AD9643 serial port interface (SPI) allows the user to configure

the converter for specific functions or operations through a

structured register space provided inside the ADC. The SPI

gives the user added flexibility and customization, depending on

the application. Addresses are accessed via the serial port and

can be written to or read from via the port. Memory is organized

into bytes that can be further divided into fields. These fields are

documented in the Memory Map section. For detailed operational

information, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

All data is composed of 8-bit words. The first bit of each individual

byte of serial data indicates whether a read or write command is

issued. This allows the serial data input/output (SDIO) pin to

change direction from an input to an output.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. If the instruction is a readback

operation, performing a readback causes the serial data input/

output (SDIO) pin to change direction from an input to an output

at the appropriate point in the serial frame.

CONFIGURATION USING THE SPI

Data can be sent in MSB first mode or in LSB first mode. MSB

first is the default on power-up and can be changed via the SPI

port configuration register. For more information about this

and other features, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

Three pins define the SPI of this ADC: the SCLK pin, the SDIO

pin, and the CSB pin (see Table 12). The SCLK (serial clock) pin is

used to synchronize the read and write data presented from/to the

ADC. The SDIO (serial data input/output) pin is a dual-purpose

pin that allows data to be sent and read from the internal ADC

memory map registers. The CSB (chip select bar) pin is an active

low control that enables or disables the read and write cycles.

HARDWARE INTERFACE

The pins described in Table 12 comprise the physical interface

between the user programming device and the serial port of the

AD9643. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

Table 12. Serial Port Interface Pins

Function

SCLK Serial Clock. The serial shift clock input, which is used to

synchronize serial interface reads and writes.

SDIO Serial Data Input/Output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in the AN-812 Application Note, Micro-

controller-Based Serial Port Interface (SPI) Boot Circuit.

CSB

Chip Select Bar. An active low control that gates the read

and write cycles.

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used for

other devices, it may be necessary to provide buffers between

this bus and the AD9643 to prevent these signals from transi-

tioning at the converter inputs during critical sampling periods.

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. An example of the

serial timing and its definitions can be found in Figure 58 and

Table 5.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, which permanently enables the device;

this is called streaming. The CSB can stall high between bytes

to allow for additional external timing. When CSB is tied high,

SPI functions are placed in a high impedance mode. This mode

turns on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and its length is determined

by the W0 and the W1 bits.

Rev. A | Page 29 of 36

AD9643

SPI ACCESSIBLE FEATURES

Table 13 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9643 part-specific features are described in the

Memory Map Register Description section.

Table 13. Features Accessible Using the SPI

Feature Name

Description

Mode

Clock

Offset

Test I/O

Output Mode

Output Phase

Output Delay

VREF

Allows the user to set either power-down mode or standby mode

Allows the user to access the DCS via the SPI

Allows the user to digitally adjust the converter offset

Allows the user to set test modes to have known data on output bits

Allows the user to set up outputs

Allows the user to set the output clock polarity

Allows the user to vary the DCO delay

Allows the user to set the reference voltage

t_HIGH

t_DS

t_CLK

t_H

t_S

t_DH

t_LOW

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 58. Serial Port Interface Timing Diagram

Rev. A | Page 3ꢀ of 36

AD9643

MEMORY MAP

Logic Levels

READING THE MEMORY MAP REGISTER TABLE

An explanation of logic level terminology follows:

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into three sections: the chip

configuration registers (Address 0x00 to Address 0x02); the

channel index and transfer registers (Address 0x05 and

Address 0xFF); and the ADC functions registers, including setup,

control, and test (Address 0x08 to Address 0x59).

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

The memory map register table (see Table 14) documents the

default hexadecimal value for each hexadecimal address shown.

The column with the heading Bit 7 (MSB) is the start of the

default hexadecimal value given. For example, Address 0x14,

the output mode register, has a hexadecimal default value of

0x05. This means that Bit 0 = 1 and Bit 2 = 1, and the remaining

bits are 0s. This setting is the default output format value, which

is twos complement. For more information on this function and

others, see the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI. This document details the functions

controlled by Register 0x00 to Register 0x25. The remaining

registers, Register 0x3A and Register 0x59, are documented in

the Memory Map Register Description section.

Address 0x08 to Address 0x20, Address 0x3A, and

Address 0x59 are shadowed. Writes to these addresses do

not affect part operation until a transfer command is issued by

writing 0x01 to Address 0xFF, setting the transfer bit. This allows

these registers to be updated internally and simultaneously when

the transfer bit is set. The internal update takes place when the

transfer bit is set, and then the bit autoclears.

Channel-Specific Registers

Some channel setup functions, such as the signal monitor

thresholds, can be programmed to a different value for each

channel. In these cases, channel address locations are internally

duplicated for each channel. These registers and bits are designated

in Table 14 as local. These local registers and bits can be accessed

by setting the appropriate Channel A or Channel B bits in

Register 0x05. If both bits are set, the subsequent write affects

the registers of both channels. In a read cycle, only Channel A

or Channel B should be set to read one of the two registers. If

both bits are set during an SPI read cycle, the part returns the

value for Channel A. Registers and bits designated as global in

Table 14 affect the entire part and the channel features for which

independent settings are not allowed between channels. The

settings in Register 0x05 do not affect the global registers and bits.

Open and Reserved Locations

All address and bit locations that are not included in Table 14

are not currently supported for this device. Unused bits of a

valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open (for example, Address 0x13), this address location should

not be written.

Default Values

After the AD9643 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 14.

Rev. A | Page 31 of 36

AD9643

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 14 are not currently supported for this device.

Table 14. Memory Map Registers

Default Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Chip Configuration Registers

ꢀxꢀꢀ

SPI port

ꢀ

LSB first

Soft reset

1

Soft reset

LSB first

ꢀ

ꢀx18

The nibbles

are mirrored

so that LSB

first mode

or MSB first

mode

configuration

(global)¹

registers

correctly,

regardless

of shift

mode.

ꢀxꢀ1

ꢀxꢀ2

Chip ID

(global)

8-bit chip ID[7:ꢀ]

(AD9643 = ꢀx82)

(default)

ꢀx82

Read only.

Chip grade

(global)

Open

Speed grade ID

ꢀꢀ = 25ꢀ MSPS

Open

Speed

grade ID

used to

differentiate

devices;

read only.

Channel Index and Transfer Registers

ꢀxꢀ5

Channel index Open

(global)

Open

ADC B

(default)

ADC A

(default)

ꢀxꢀ3

Bits are

set to

determine

which

device on

the chip

receives the

next write

command;

applies to

local

registers

only.

ꢀxFF

Transfer

(global)

Open

Transfer

ꢀxꢀꢀ

Synchro-

nously

transfers

data from

the master

shift register

to the slave.

ADC Functions

ꢀxꢀ8

Power modes

(local)

External

power-

down pin

function

(local)

ꢀ = power-

down

1 = standby

Open

Internal power-down mode

(local)

ꢀꢀ = normal operation

ꢀ1 = full power-down

1ꢀ = standby

Determines

various

generic

modes of

chip

operation.

11 = reserved

ꢀxꢀ9

ꢀxꢀB

Global clock

(global)

Open

Duty cycle

stabilizer

(default)

ꢀxꢀ1

ꢀxꢀꢀ

Clock divide

(global)

Input clock divider phase adjust

ꢀꢀꢀ = no delay

Clock divide ratio

ꢀꢀꢀ = divide by 1

ꢀꢀ1 = divide by 2

ꢀ1ꢀ = divide by 3

ꢀ11 = divide by 4

1ꢀꢀ = divide by 5

1ꢀ1 = divide by 6

11ꢀ = divide by 7

111 = divide by 8

Clock

divide

values

ꢀꢀ1 = 1 input clock cycle

ꢀ1ꢀ = 2 input clock cycles

ꢀ11 = 3 input clock cycles

1ꢀꢀ = 4 input clock cycles

1ꢀ1 = 5 input clock cycles

11ꢀ = 6 input clock cycles

111 = 7 input clock cycles

other than

ꢀꢀꢀ auto-

matically

cause the

duty cycle

stabilizer to

become

active.

Rev. A | Page 32 of 36

AD9643

Default Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

ꢀxꢀD

Test mode

(local)

User test

mode

control

ꢀ = con-

tinuous/

repeat

pattern

1 = single

pattern,

then ꢀs

Open

Reset PN

long gen

Reset PN

short gen

Output test mode

ꢀꢀꢀꢀ = off (default)

ꢀꢀꢀ1 = midscale short

ꢀꢀ1ꢀ = positive FS

ꢀꢀ11 = negative FS

ꢀ1ꢀꢀ = alternating checkerboard

ꢀ1ꢀ1 = PN long sequence

ꢀ11ꢀ = PN short sequence

ꢀ111 = one/zero word toggle

1ꢀꢀꢀ = user test mode

ꢀxꢀꢀ

When this

register is

set, the test

data is

placed on

the output

pins in

place of

normal data.

1ꢀꢀ1 to 111ꢀ = unused

1111 = ramp output

ꢀxꢀE

ꢀx1ꢀ

ꢀx14

BIST enable

(local)

Open

Reset BIST

sequence

Open

BIST enable

ꢀxꢀꢀ

ꢀxꢀ5

Offset adjust

(local)

Offset adjust in LSBs from +31 to −32

(twos complement format)

Output mode

Output

enable bar

(local)

Open

Output

Output format

Configures

the outputs

and the

format of

the data.

invert (local)

1 = normal

(default)

ꢀꢀ = offset binary

ꢀ1 = twos complement

(default)

1ꢀ = gray code

11 = reserved

(local)

ꢀ = inverted

ꢀx15

Output Adjust

(Global)

Open

LVDS output drive current adjust

ꢀxꢀ1

ꢀꢀꢀꢀ = 3.72 mA output drive current

ꢀꢀꢀ1 = 3.5 mA output drive current (default)

ꢀꢀ1ꢀ = 3.3ꢀ mA output drive current

ꢀꢀ11 = 2.96 mA output drive current

ꢀ1ꢀꢀ = 2.82 mA output drive current

ꢀ1ꢀ1 = 2.57 mA output drive current

ꢀ11ꢀ = 2.27 mA output drive current

ꢀ111 = 2.ꢀ mA output drive current (reduced range)

1ꢀꢀꢀ to 1111 = reserved

ꢀx16

ꢀx17

Clock phase

control

(global)

Invert

DCO clock

Open

ꢀxꢀꢀ

DCO output

delay

(global)

Enable

DCO

clock

delay

DCO clock delay

[delay = (31ꢀꢀ ps × register value/31 +1ꢀꢀ)]

ꢀꢀꢀꢀꢀ = 1ꢀꢀ ps

ꢀꢀꢀꢀ1 = 2ꢀꢀ ps

ꢀꢀꢀ1ꢀ = 3ꢀꢀ ps

…

1111ꢀ = 31ꢀꢀ ps

11111 = 32ꢀꢀ ps

ꢀx18

Input Span

select

(global)

Open

Full-scale input voltage selection

ꢀ1111 = 2.ꢀ87 V p-p

…

ꢀꢀꢀꢀ1 = 1.772 V p-p

ꢀꢀꢀꢀꢀ = 1.75 V p-p (default)

11111 = 1.727 V p-p

…

ꢀxꢀꢀ

Full-scale

input

adjustment

in ꢀ.ꢀ22 V

steps.

1ꢀꢀꢀꢀ = 1.383 V p-p

ꢀx19

ꢀx1A

ꢀx1B

ꢀx1C

ꢀx1D

ꢀx1E

User Test

Pattern 1 LSB

(global)

User Test Pattern 1[7:ꢀ]

User Test Pattern 1[15:8]

User Test Pattern 2[7:ꢀ]

User Test Pattern 2[15:8]

User Test Pattern 3[7:ꢀ]

User Test Pattern 3[15:8]

ꢀxꢀꢀ

User Test

Pattern 1 MSB

(global)

User Test

Pattern 2 LSB

(global)

User Test

Pattern 2 MSB

(global)

User Test

Pattern 3 LSB

(global)

User Test

Pattern 3 MSB

(global)

Rev. A | Page 33 of 36

AD9643

Default Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

ꢀx1F

User Test

Pattern 4 LSB

(global)

User Test Pattern 4[7:ꢀ]

ꢀxꢀꢀ

ꢀx2ꢀ

User Test

User Test Pattern 4[15:8]

ꢀxꢀꢀ

Pattern 4 MSB

(global)

ꢀx24

ꢀx25

ꢀx3A

BIST signature

LSB (local)

BIST signature[7:ꢀ]

BIST signature[15:8]

ꢀxꢀꢀ

Read only.

BIST signature

MSB (local)

Sync control

(global)

Open

Clock

divider

sync

Master sync

buffer enable

divider

next sync

only

enable

ꢀx59

SYNC pin

control

(local)

Open

SYNC pin

sensitivity

ꢀ = sync

on high

level

SYNC pin

edge

ꢀxꢀꢀ

sensitivity

ꢀ = sync on

falling edge

1 = sync on

rising edge

1 = sync

on edge

¹The channel index register at Address ꢀxꢀ5 should be set to ꢀxꢀ3 (default) when writing to Address ꢀxꢀꢀ.

Bit 0—Master Sync Buffer Enable

MEMORY MAP REGISTER DESCRIPTION

For more information on functions controlled in Register 0x00

to Register 0x25, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

Bit 0 must be set high to enable any of the sync functions. If the

sync capability is not used, this bit should remain low to

conserve power.

Sync Control (Register 0x3A)

Bits[7:3]—Reserved

SYNC Pin Control (Register 0x59)

Bits [7:2]—Reserved

Bit 2—Clock Divider Next Sync Only

Bit 1—SYNC Pin Sensitivity

If the master sync buffer enable bit (Address 0x3A, Bit 0) and

the clock divider sync enable bit (Address 0x3A, Bit 1) are high,

Bit 2 allows the clock divider to sync to the first sync pulse that

it receives and to ignore the rest. The clock divider sync enable

bit (Address 0x3A, Bit 1) resets after it syncs.

If Bit 1 is set to 0, the SYNC input responds to a level. If this bit

is set low, the SYNC input responds to the edge (rising or

falling) set in Bit 0 of Address 0x59.

Bit 0—SYNC Pin Edge Sensitivity

If Bit 1 is set high, setting Bit 0 to a 0 causes the SYNC input to

respond to a falling edge. If this bit is set, the SYNC input

respond to a rising edge.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is

enabled when Bit 1 is high and Bit 0 is high. This is continuous

sync mode.

Rev. A | Page 34 of 36

AD9643

APPLICATIONS INFORMATION

DESIGN GUIDELINES

VCM

The VCM pin should be decoupled to ground with a 0.1 ꢀF

capacitor, as shown in Figure 48. For optimal channel-to-channel

isolation, a 33 Ω resistor should be included between the AD9643

VCM pin and the Channel A analog input network connection,

as well as between the AD9643 VCM pin and the Channel B

analog input network connection.

Before starting system level design and layout of the AD9643,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9643, it is recommended

that two separate 1.8 V supplies be used: one supply should be

used for analog (AVDD), and a separate supply should be used

for the digital outputs (DRVDD). The designer can employ

several different decoupling capacitors to cover both high and

low frequencies. These capacitors should be located close to the

point of entry at the PC board level and close to the pins of the

part with minimal trace length.

SPI Port

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9643 to keep these signals from transitioning at the converter

input pins during critical sampling periods.

A single PCB ground plane should be sufficient when using the

AD9643. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance. A continuous, exposed

(no solder mask) copper plane on the PCB should mate to the

AD9643 exposed paddle, Pin 0.

The copper plane should have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow through

the bottom of the PCB. These vias should be filled or plugged with

nonconductive epoxy.

To maximize the coverage and adhesion between the ADC

and the PCB, a silkscreen should be overlaid to partition the

continuous plane on the PCB into several uniform sections.

This provides several tie points between the ADC and the PCB

during the reflow process. Using one continuous plane with no

partitions guarantees only one tie point between the ADC and

the PCB. See the evaluation board for a PCB layout example.

For detailed information about the packaging and PCB layout

of chip scale packages, refer to the AN-772 Application Note, A

Design and Manufacturing Guide for the Lead Frame Chip Scale

Package (LFCSP).

Rev. A | Page 35 of 36

AD9643

OUTLINE DIMENSIONS

0.60 MAX

9.00

BSC SQ

0.60

MAX

PIN 1

INDICATOR

64

49

1

48

PIN 1

INDICATOR

0.50

BSC

6.35

6.20 SQ

6.05

8.75

BSC SQ

TOP VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.50

0.40

0.30

33

32

16

17

0.25 MIN

7.50

REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

0.30

0.23

0.18

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-64-4

AD9643BCPZ-170

AD9643BCPZ-210

AD9643BCPZ-250

AD9643BCPZRL7-170

AD9643BCPZRL7-210

AD9643BCPZRL7-250

AD9643-170EBZ

AD9643-210EBZ

AD9643-250EBZ

−40°C to +85°C

64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board with AD9643-170

CP-64-4

Evaluation Board with AD9643-210

Evaluation Board with AD9643-250

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D09636-0-5/11(A)

Rev. A | Page 36 of 36


型号：	AD9643BCPZRL7-250
厂家：	ADI
描述：	14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) 14位， 170 MSPS / 210 MSPS / 250 MSPS ， 1.8 V双通道模拟数字转换器（ ADC ）转换器
文件：	总36页 (文件大小：1660K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9643BCPZRL7-250 [ADI]

相关型号：

AD9644

AD9644-155KITZ

AD9644-80KITZ

AD9644BCPZ-155

AD9644BCPZ-80

AD9644BCPZRL7-155

AD9644BCPZRL7-155

AD9644BCPZRL7-80

AD9644CCPZ-80

AD9644CCPZ-80

AD9644CCPZRL7-80

AD9644_17