AD9675_17 [ADI]
Octal Ultrasound AFE with JESD204B;
| 型号： | AD9675_17 |
| 厂家： | 
ADI |
| 描述： | Octal Ultrasound AFE with JESD204B |
| 文件： | 总61页 (文件大小：842K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Octal Ultrasound AFE with JESD204B
Data Sheet
AD9675
FEATURES
GENERAL DESCRIPTION
8 channels of LNA, VGA, AAF, ADC, and digital RF decimator
Low power
150 mW per channel, TGC mode, 40 MSPS
62.5 mW per channel, CW mode
10 mm × 10 mm, 144-ball CSP_BGA
TGC channel input referred noise: 0.82 nV/√Hz,
maximum gain
Flexible power-down modes
The AD9675 is designed for low cost, low power, small size, and
ease of use for medical ultrasound. It contains eight channels of
a variable gain amplifier (VGA) with a low noise preamplifier
(LNA), a continuous wave (CW) harmonic rejection I/Q
demodulator with programmable phase rotation, an antialiasing
filter (AAF), an analog-to-digital converter (ADC), and a digital
high-pass filter and RF decimation by 2 for data processing and
bandwidth reduction.
Fast recovery from low power standby mode: 2 μs
Low noise preamplifier (LNA)
Each channel features a maximum gain of up to 52 dB, a fully
differential signal path, and an active input preamplifier termina-
tion. The channel is optimized for high dynamic performance
and low power in applications where a small package size is critical.
Input referred noise: 0.78 nV/√Hz, gain = 21.6 dB
Programmable gain: 15.6 dB, 17.9 dB, or 21.6 dB
0.1 dB compression: 1000 mV p-p, 750 mV p-p, or 450 mV p-p
Flexible active input impedance matching
Variable gain amplifier (VGA)
Attenuator range: 45 dB, linear in dB gain control
Postamp gain (PGA): 21 dB, 24 dB, 27 dB, or 30 dB
Antialiasing filter (AAF)
The LNA has a single-ended to differential gain that is selectable
through the serial port interface (SPI). Assuming a 15 MHz
noise bandwidth (NBW) and a 21.6 dB LNA gain, the LNA
input SNR is 94 dB. In CW Doppler mode, each LNA output
drives an I/Q demodulator that has independently
programmable phase rotation with 16 phase settings.
Programmable second-order low-pass filter (LPF) from
8 MHz to 18 MHz or 13.5 MHz to 30 MHz and high-pass
filter (HPF)
Analog-to-digital converter (ADC)
SNR: 75 dB, 14 bits up to 125 MSPS
JESD204B Subclass 0 coded serial digital outputs
CW Doppler mode harmonic rejection I/Q demodulator
Individual programmable phase rotation
Dynamic range per channel: 160 dBFS/√Hz
Close-in SNR: 156 dBc/√Hz, 1 kHz offset, −3 dBFS input
RF digital decimation by 2 and high-pass filter
Power-down of individual channels is supported to increase
battery life for portable applications. Standby mode allows quick
power-up for power cycling. In CW Doppler operation, the
VGA, AAF, and ADC are powered down. The ADC contains
features to maximize flexibility and minimize system cost, such
as a programmable clock, data alignment, and programmable
digital test pattern generation. The digital test patterns include
built-in fixed patterns, built-in pseudorandom patterns, and
custom user-defined test patterns entered via the SPI.
APPLICATIONS
Medical imaging/ultrasound
Nondestructive testing (NDT)
Rev. A
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AD9675* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DESIGN RESOURCES
• AD9675 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Data Sheet
• AD9675: Octal Ultrasound AFE With JESD204B Data Sheet
DISCUSSIONS
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REFERENCE MATERIALS
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SAMPLE AND BUY
Visit the product page to see pricing options.
• JESD204B FPGA Debug Software Accelerates High-speed
Design
• Low Cost, Octal Ultrasound Receiver with On-Chip RF
Decimator and JESD204B Serial Interface
TECHNICAL SUPPORT
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number.
• Xilinx and Analog Devices Achieve JEDEC JESD204B
Interoperability
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AD9675
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital Outputs and Timing ..................................................... 29
Analog Test Tone Generation................................................... 38
CW Doppler Operation............................................................. 39
Digital RF Decimator..................................................................... 40
Vector Profile .............................................................................. 40
RF Decimator.............................................................................. 41
Digital Test Waveforms.............................................................. 41
Digital Block Power Saving Scheme ........................................ 42
Serial Port Interface (SPI).............................................................. 43
Hardware Interface..................................................................... 43
Memory Map .................................................................................. 45
Reading the Memory Map Table.............................................. 45
Recommended Start-Up Sequence .......................................... 45
Memory Map Register Table..................................................... 47
Memory Map Register Descriptions........................................ 59
Outline Dimensions....................................................................... 60
Ordering Guide .......................................................................... 60
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 9
Absolute Maximum Ratings.......................................................... 12
Thermal Impedance................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 16
TGC Mode................................................................................... 16
CW Doppler Mode..................................................................... 20
Theory of Operation ...................................................................... 21
TGC Operation........................................................................... 21
REVISION HISTORY
1/16—Revision A: Initial Version
Rev. A | Page 2 of 60
Data Sheet
AD9675
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2
PDWN STBY
DVDD
DRVDD
AD9675
CWQ+
CWQ–
CWI+
CWI–
LO-A TO LO-H
CWD I/Q
DEMODULATOR
LOSW-A TO LOSW-H
SERDOUT1+ TO SERDOUT4+
SERDOUT1– TO SERDOUT4–
LI-A TO LI-H
14-BIT
ADC
LNA
VGA
RF DECIMATOR
CML
AAF
LG-A TO LG-H
SERIALIZER
SYSREF+
SYSREF–
SYNCINB+
SYNCINB–
8 CHANNELS
SERIAL
DATA
LO
REFERENCE
PORT
RATE
GENERATION
INTERFACE
MULTIPLIER
Figure 1.
Rev. A | Page 3 of 60
AD9675
Data Sheet
SPECIFICATIONS
AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C),
fIN = 5 MHz, low bandwidth mode, RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.6 dB, LNA bias = mid-high, PGA gain = 27 dB, analog
gain control, VGAIN (V) = (GAIN+) − (GAIN−) = 1.6 V, AAF LPF cutoff = fSAMPLE/3 (Mode I/Mode II) = fSAMPLE/4.5 (Mode III/Mode IV),
HPF cutoff = LPF cutoff/12.00, Mode I = fSAMPLE = 40 MSPS, Mode II = fSAMPLE = 65 MSPS, Mode III = fSAMPLE = 80 MSPS, Mode IV = 125 MSPS,
RF decimator bypassed (Mode I/Mode II), RF decimator enabled (Mode III/Mode IV), digital high-pass filter bypassed, JESD204B link
parameters: M = 8 and L = 2, unless otherwise noted. All gain setting options are listed, which can be configured via SPI registers, and all
power supply currents and power dissipations are listed for the four mode settings (Mode I, Mode II, Mode III, and Mode IV).
Table 1.
Parameter1
Test Conditions/Comments
Min
Typ
Max
Unit
LNA CHARACTERISTICS
Gain
Single-ended input to differential output
Single-ended input to single-ended output
15.6/17.9/21.6
9.6/11.9/15.6
dB
dB
0.1 dB Input Compression Point
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
1000
750
450
mV p-p
mV p-p
mV p-p
1 dB Input Compression Point
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
1200
900
600
2.2
mV p-p
mV p-p
mV p-p
V
Input Common Mode (LI-x, LG-x)
Output Common Mode (LO-x)
Switch off
Switch on
High-Z
1.5
Ω
V
Output Common Mode (LOSW-x) Switch off
Switch on
High-Z
1.5
Ω
V
Input Resistance (LI-x)
RFB = 300 Ω, LNA gain = 21.6 dB
RFB = 1350 Ω, LNA gain = 21.6 dB
50
200
6
Ω
Ω
kΩ
pF
Input Capacitance (LI-x)
22
Input Referred Noise Voltage
RS = 0 Ω
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
Noise bandwidth = 15 MHz
0.83
0.82
0.78
94
nV/√Hz
nV/√Hz
nV/√Hz
dB
Input Signal-to-Noise Ratio
Input Noise Current
2.6
pA/√Hz
FULL CHANNEL CHARACTERISTICS Time gain control (TGC)
AAF Low-Pass Cutoff
−3 dB, programmable, low bandwidth mode
−3 dB, programmable, high bandwidth mode
8
13.5
18
30
MHz
MHz
%
In Range AAF Bandwidth
Tolerance
10
Group Delay Variation
Input Referred Noise Voltage
f = 1 MHz to 18 MHz, VGAIN = −1.6 V to +1.6 V
LNA gain = 15.6 dB
LNA gain = 17.9 dB
350
0.96
0.90
0.82
ps
nV/√Hz
nV/√Hz
nV/√Hz
LNA gain = 21.6 dB
Noise Figure
Active Termination Matched
LNA gain = 15.6 dB, RFB = 150 Ω
LNA gain = 17.9 dB, RFB = 200 Ω
LNA gain = 21.6 dB, RFB = 300 Ω
LNA gain = 15.6 dB, RFB = ∞
LNA gain = 17.9 dB, RFB = ∞
LNA gain = 21.6 dB, RFB = ∞
5.6
4.8
3.8
3.2
2.9
2.6
dB
dB
dB
dB
dB
dB
Unterminated
Rev. A | Page 4 of 60
Data Sheet
AD9675
Parameter1
Test Conditions/Comments
Min
Typ
Max
Unit
dB
LSB
Correlated Noise Ratio
Output Offset
No signal, correlated/uncorrelated
−30
−125
+125
Signal-to-Noise Ratio (SNR)
fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V
fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V
fIN = 3.5 MHz at −0.5 dBFS, VGAIN = 0 V,
1 kHz offset
69
59
−130
dBFS
dBFS
dBc/√Hz
Close-In SNR
Second Harmonic
fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V
fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V
fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V
fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V
fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, ARF1
−70
−62
−61
−55
−54
dBc
dBc
dBc
dBc
dBc
Third Harmonic
Two-Tone Intermodulation
Distortion (IMD3)
=
−1 dBFS, ARF2 = −21 dBFS, VGAIN = 1.6 V, IMD3
relative to ARF2
Channel-to-Channel Crosstalk
fIN1 = 5.0 MHz at −1 dBFS
Overrange condition2
TA = 25°C
−60
−55
dB
dB
GAIN ACCURACY
Gain Law Conformance Error
−1.6 < VGAIN < −1.28 V
−1.28 V < VGAIN < +1.28 V
1.28 V < VGAIN < 1.6 V
VGAIN = 0 V, normalized for ideal AAF loss
−1.28 V < VGAIN < +1.28 V, 1 σ
0.4
dB
dB
dB
dB
dB
dB
−1.3
−0.9
+1.3
+0.9
−0.5
Channel-to-Channel Matching
PGA Gain
0.1
21/24/27/30
GAIN CONTROL INTERFACE
Control Range
Control Common Mode
Input Impedance
Gain Range
Differential
GAIN+, GAIN−
GAIN+, GAIN−
−1.6
0.7
+1.6
0.9
V
V
0.8
10
45
14
3.5
750
MΩ
dB
dB/V
dB
ns
Gain Sensitivity
Analog
Digital step size
Analog 45 dB change
Response Time
CW DOPPLER MODE
LO Frequency
fLO = fMLO/M
1
10
MHz
Phase Resolution
Per channel, 4LO mode
Per channel, 8LO mode, 16LO mode
CWI+, CWI−, CWQ+, CWQ−
Per CWI+, CWI−, CWQ+, CWQ−, each channel
enabled (2 fLO and baseband signal)
45
22.5
AVDD2 ÷ 2
2.2
Degrees
Degrees
V
Output DC Bias (Single-Ended)
Output AC Current Range
2.5
mA
Transconductance (Differential)
Demodulated IOUT/VIN, per CWI+, CWI−,
CWQ+, CWQ−
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
RS = 0 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
RS = 50 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
RS = 0 Ω, RFB = ∞
3.3
4.3
6.6
mA/V
mA/V
mA/V
Input Referred Noise Voltage
Noise Figure
1.6
1.3
1.0
nV/√Hz
nV/√Hz
nV/√Hz
5.7
4.5
3.4
dB
dB
dB
Input Referred Dynamic Range
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
164
162
160
dBFS/√Hz
dBFS/√Hz
dBFS/√Hz
Rev. A | Page 5 of 60
AD9675
Data Sheet
Parameter1
Test Conditions/Comments
Min
Typ
Max
Unit
Close-In SNR
−3 dBFS input, fRF = 2.5 MHz, fLO = 40 MHz,
156
dBc/√Hz
1 kHz offset, 16LO mode, one channel enabled
−3 dBFS input, fRF = 2.5 MHz, fLO = 40 MHz,
1 kHz offset, 16LO mode, eight channels enabled
fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, fLO = 80 MHz,
ARF1 = −1 dBFS, ARF2 = −21 dBFS, IMD3 relative
to ARF2
161
−58
dBc/√Hz
dBc
Two-Tone Intermodulation
Distortion (IMD3)
LO Harmonic Rejection
−20
dBc
Quadrature Phase Error
I/Q Amplitude Imbalance
Channel to Channel Matching
I to Q, all phases, 1 σ
I to Q, all phases, 1 σ
Phase I to I, Q to Q, 1 σ
Amplitude I to I, Q to Q, 1 σ
Mode I/Mode II/Mode III/Mode IV
0.15
0.015
0.5
Degrees
dB
Degrees
dB
0.25
POWER SUPPLY
AVDD1
AVDD2
DVDD
DRVDD
IAVDD1
1.7
2.85
1.3
1.8
3.0
1.4
1.8
148/187/
223/291
1.9
3.6
1.9
1.9
V
V
V
V
1.7
TGC mode, low bandwidth mode
mA
CW Doppler mode
4
230
239
140
29/46/40/61
38/60/54/80
121/168/
122/166
mA
mA
mA
mA
mA
mA
mA
IAVDD2
TGC mode, no signal, low bandwidth mode
TGC mode, no signal, high bandwidth mode
CW Doppler mode
IDVDD
DVDD = 1.8 V
Four-lane mode, JESD204B lane rates =
1.6 Gbps/2.6 Gbps/1.6 Gbps/2.5 Gbps
IDRVDD
Two-lane mode, JESD204B lane rates =
3.2 Gbps/5.0 Gbps/3.2 Gbps/5.0 Gbps
One-lane mode, RF decimator enabled,
JESD204B lane rates = 3.2 Gbps/5.0 Gbps/
not valid/not valid
127/186/
129/184
73/105/not
mA
mA
valid/not valid
Total Power Dissipation
(Including Output Drivers)
TGC mode, no signal, two-lane mode
1200/1415/
1365/1615
1445/1680/ mW
1635/1910
TGC mode, no signal, two-lane mode,
DVDD = 1.8 V
1230/1460/
1410/1675
mW
CW Doppler mode, eight channels enabled
500
5
725
mW
mW
mW
Power-Down Dissipation
Standby Power Dissipation
ADC
30
Resolution
SNR
14
75
Bits
dB
ADC REFERENCE
Output Voltage Error
Load Regulation at 1.0 mA
Input Resistance
VREF = 1 V
VREF = 1 V
50
mV
mV
kΩ
2
7.5
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed.
2 The overrange condition is specified as 6 dB more than the full-scale input range.
Rev. A | Page 6 of 60
Data Sheet
AD9675
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C),
unless otherwise noted.
Table 2.
Parameter1
Temperature
Min
Typ
Max
Unit
INPUTS (CLK+, CLK−, TX_TRIG+, TX_TRIG−)
Logic Compliance
Differential Input Voltage2
CMOS/LVDS/LVPECL
0.2
3.6
V p-p
V
Input Voltage Range
GND – 0.2
AVDD1 + 0.2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
0.9
15
4
V
kΩ
pF
25°C
25°C
INPUTS (MLO+, MLO−, RESET+, RESET−)
Logic Compliance
Differential Input Voltage2
LVDS/LVPECL
0.250
AVDD2 × 2
AVDD2 + 0.2
V p-p
V
Input Voltage Range
GND – 0.2
Input Common-Mode Voltage
Input Resistance (Single-Ended)
Input Capacitance
AVDD2/2
20
1.5
V
kΩ
pF
25°C
25°C
LOGIC INPUTS (PDWN, STBY, SCLK, SDIO, ADDRx)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Full
Full
25°C
25°C
1.2
1.2
DRVDD + 0.3
0.3
V
V
kΩ
pF
30 (26 for SDIO)
2 (5 for SDIO)
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Full
Full
DRVDD + 0.3
0.3
V
V
Input Resistance
Input Capacitance
25°C
25°C
26
2
kΩ
pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (SERDOUTx+, SERDOUTx−)
Logic Compliance
Full
Full
1.79
V
V
0.05
CML
600
Differential Output Voltage (VOD
)
Full
Full
400
0.75
750
1.05
mV
V
Output Offset Voltage (VOS
)
LOGIC OUTPUT (GPO0, GPO1, GPO2, GPO3)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL INPUT (SYNCINB+, SYNCINB−)
Logic Compliance
Full
0.05
V
CMOS/LVDS
0.9
Internal Bias
Differential Input Voltage Range
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Full
Full
Full
Full
Full
Full
Full
Full
V
V
V
V
μA
μA
pF
kΩ
0.3
3.6
DRVDD
1.4
+5
+5
GND
0.9
−5
−5
1
16
Input Resistance
12
20
Rev. A | Page 7 of 60
AD9675
Data Sheet
Parameter1
Temperature
Min
Typ
Max
Unit
DIGITAL INPUT (SYSREF+, SYSREF−)
Logic Compliance
LVDS
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Full
Full
Full
Full
Full
Full
Full
Full
0.9
V
V p-p
V
0.3
GND
0.9
−5
3.6
DRVDD
1.4
+5
+5
V
μA
μA
pF
kΩ
−5
4
10
Input Resistance
8
12
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.
Rev. A | Page 8 of 60
Data Sheet
AD9675
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, L = 2, M = 8, fSAMPLE = 40 MHz, lane
data rate = 3.2 Gbps, full temperature range (0°C to 85°C), unless otherwise noted.
Table 3.
Parameter1
CLOCK2
Temperature Min
Typ
Max
Unit
Clock Rate (fSAMPLE
)
40 MSPS (Mode I)
65 MSPS (Mode II)
Full
Full
Full
Full
Full
Full
20.5
20.5
20.5
20.5
40
65
80
125
MHz
MHz
MHz
MHz
ns
80 MSPS (Mode III)3
125 MSPS (Mode IV)4
Clock Pulse Width High (tEH
Clock Pulse Width Low (tEL)
CLOCK INPUT PARAMETERS
)
3.75
3.75
ns
TX_TRIG to CLK Setup Time (tSETUP
)
25°C
25°C
1
1
ns
ns
TX_TRIG to CLK Hold Time (tHOLD
)
DATA OUTPUT PARAMETERS
Data Output Period or Unit Interval (UI)
Data Output Duty Cycle
Data Valid Time
Full
L/(20 × M × fSAMPLE
)
Seconds
%
UI
μs
μs
25°C
25°C
25°C
25°C
50
0.76
26
2
PLL Lock Time5
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)6
Device
JESD204B Link
SYNCINB Falling Edge to First K.28 Characters
25°C
25°C
Full
375
250
μs
μs
4
1
Multiframes
Multiframe
Code Group Synchronization (CGS) Phase K.28
Characters Duration
Full
Delay (Latency)
ADC Pipeline
RF Decimator
Full
Full
Full
Full
16
11
100
Cycles
Cycles
Cycles
Digital High-Pass Filter
TX_TRIG to Start Code (Mode I/Mode II/Mode III/
Mode IV)
Four-Lane Mode
Two-Lane Mode
Data Rate per Lane
Uncorrelated Bounded High Probability (UBHP) Jitter
Random Jitter at 2.5 Gbps Data Rate
Random Jitter at 5 Gbps Data Rate
Output Rise/Fall Time
Full
Full
31/42/30/36
31/33/30/30
Cycles
Cycles
Gbps
ps
ps rms
ps rms
ps
25°C
25°C
25°C
25°C
25°C
5.0
11
80
46
64
TERMINATION CHARACTERISTICS
Differential Termination Resistance
APERTURE
Full
100
<1
Ω
Aperture Uncertainty (Jitter)
25°C
ps rms
Rev. A | Page 9 of 60
AD9675
Data Sheet
Parameter1
Temperature Min
Typ
Max
Unit
LO GENERATION
MLO Frequency
4LO Mode
8LO Mode
16LO Mode
RESET to MLO Setup Time (tSETUP
RESET to MLO Hold Time (tHOLD
Full
Full
Full
Full
Full
4
8
16
1
1
40
80
160
MHz
MHz
MHz
ns
)
tMLO/2
tMLO/2
)
ns
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed.
2 Can be adjusted via the SPI.
3 Mode III must have the RF decimator enabled.
4 Mode IV must have the RF decimator enabled.
5 PLL lock time from 0 Hz to 40 MHz frequency change.
6 Wake-up time is defined as the time required to return to normal operation from power-down mode.
CLK± ±, T_ RIG± ,ꢀSychroyizatioy, imiyg,Diagram,
tSETUP
tHOLD
TX_TRIG+
TX_TRIG–
tEH
tEL
CLK–
CLK+
Figure 2. TX_TRIG to CLK Input Timing
CW, imiyg,Diagram,
tMLO
MLO–
MLO+
tHOLD
tSETUP
RESET–
RESET+
Figure 3. CW Doppler Mode Input MLO , Continuous Synchronous RESET Timing, Sampled on the Falling MLO Edge, 4LO Mode
tMLO
MLO–
MLO+
tHOLD
tSETUP
RESET–
RESET+
Figure 4. CW Doppler Mode Input MLO , Continuous Synchronous RESET Timing, Sampled on the Falling MLO Edge, 8LO Mode
Rev. A | Page 10 of 60
Data Sheet
AD9675
tMLO
MLO–
MLO+
tHOLD
tSETUP
RESET–
RESET+
Figure 5. CW Doppler Mode Input MLO , Pulse Synchronous RESET Timing, 4LO/8LO/16LO Mode
tMLO
MLO–
MLO+
tSETUP
tHOLD
RESET–
RESET+
Figure 6. CW Doppler Mode Input MLO , Pulse Asynchronous RESET Timing, 4LO/8LO/16LO Mode
Rev. A | Page 11 of 60
AD9675
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL IMPEDANCE
Table 4.
Parameter
Rating
Table 5.
Symbol Description
AVDD1 to GND
AVDD2 to GND
DVDD to GND
DRVDD to GND
GND to GND
AVDD2 to AVDD1
AVDD1 to DRVDD
AVDD2 to DRVDD
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +0.3 V
−2.0 V to +3.9 V
−2.0 V to +2.0 V
−2.0 V to +3.9 V
Value1 Unit
Junction-to-ambient thermal
resistance, 0.0 m/sec air flow per
JEDEC JESD51-2 (still air)
Junction-to-board thermal
characterization parameter, 0 m/sec
air flow per JEDEC JESD51-8 (still air)
Junction-to-top-of-package
characterization parameter, 0 m/sec
air flow per JEDEC JESD51-2 (still air)
22.0
°C/W
°C/W
°C/W
JA
9.2
JB
JT
0.12
SERDOUTx+, SERDOUTx−, SDIO, PDWN, −0.3 V to DRVDD + 0.3 V
STBY, SCLK, CSB, ADDRx to GND
1 Results are from simulations. Printed circuit board (PCB) is JEDEC multilayer.
Thermal performance for actual applications requires careful inspection of
the conditions in the application to determine if they are similar to those
assumed in these calculations.
LI-x, LO-x, LOSW-x, CWI−, CWI+,
CWQ−, CWQ+, GAIN+, GAIN−,
RESET+, RESET−, MLO+, MLO−,
GPO0, GPO1, GPO2, GPO3 to GND
−0.3 V to AVDD2 + 0.3 V
CLK+, CLK−, TX_TRIG+, TX_TRIG−,
VREF to GND
Operating Temperature Range
(Ambient)
−0.3 V to AVDD1 + 0.3 V
0°C to 85°C
ESD CAUTION
Storage Temperature Range
(Ambient)
−65°C to +150°C
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
150°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 12 of 60
Data Sheet
AD9675
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
LI-E
LI-F
LI-G
LI-H
VREF
RBIAS GAIN+ GAIN–
LI-A
LI-B
LI-C
LI-D
LG-E
LO-E
LG-F
LO-F
LG-G
LO-G
LG-H
LO-H
GND
GND
GND
GND
CLNA
GND
GND
GND
LG-A
LO-A
LG-B
LO-B
LG-C
LO-C
LG-D
LO-D
D
E
F
LOSW-E LOSW-F LOSW-G LOSW-H GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND LOSW-A LOSW-B LOSW-C LOSW-D
GND
AVDD1
GND
AVDD2 AVDD2 AVDD2
GND
AVDD1
GND
GND
AVDD1
GND
AVDD2 AVDD2 AVDD2
GND
AVDD1
GND
GND
AVDD1
GND
GND
DVDD
GND
GND
GND
GND
AVDD1
GND
GND
G
H
J
AVDD1
AVDD1
DVDD
CLK– TX_TRIG–
GND
GND
ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
CSB
CLK+ TX_TRIG+ CWQ+
CWI+
AVDD2 MLO+ RESET– GPO3
AVDD2 MLO– RESET+ GPO2
GPO1
PDWN
SDIO
K
L
GND
DRVDD
GND
GND
NIC
NIC
CWQ–
NIC
CWI–
GPO0
NIC
STBY
NIC
SCLK
DRVDD
GND
SYNCINB+ SERDOUT4+ SERDOUT3+ SERDOUT2+ SERDOUT1+ SYSREF+
SYNCINB– SERDOUT4– SERDOUT3– SERDOUT2– SERDOUT1– SYSREF–
M
NIC
NIC
NIC
NIC = NOT INTERNALLY CONNECTED.
Figure 7. Pin Configuration
4
6
10
12
8
2
1
3
5
7
9
11
A
B
C
D
E
F
G
H
J
K
L
M
TOP VIEW
(Not to Scale)
Figure 8. CSP_BGA Pin Location
Rev. A | Page 13 of 60
AD9675
Data Sheet
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
B5, B6, B8, C5, C6, C7, C8, D5, D6, D7, D8, GND
E1, E5, E6, E7, E8, E12, F2, F4, F6, F7, F9,
F11, G1, G3, G5, G6, G7, G8, G10, G12,
H3, H4, H5, H6, J4, K1, K2, K4, M1, M12
Ground. These pins are tied to a quiet analog ground.
F1, F3, F5, F8, F10, F12, G2, G9
AVDD1
1.8 V Analog Supply.
G4, G11
E2, E3, E4, E9, E10, E11, J6, K6
B7
L1, L12
C1
D1
A1
B1
DVDD
AVDD2
CLNA
DRVDD
LO-E
LOSW-E
LI-E
LG-E
1.4 V Digital Supply.
3.0 V Analog Supply.
LNA External Capacitor.
1.8 V Digital Output Driver Supply.
LNA Analog Inverted Output for Channel E.
LNA Analog Switched Output for Channel E.
LNA Analog Input for Channel E.
LNA Ground for Channel E.
C2
D2
A2
B2
LO-F
LOSW-F
LI-F
LNA Analog Inverted Output for Channel F.
LNA Analog Switched Output for Channel F.
LNA Analog Input for Channel F.
LNA Ground for Channel F.
LG-F
C3
D3
A3
B3
C4
D4
A4
B4
LO-G
LOSW-G
LI-G
LG-G
LO-H
LOSW-H
LI-H
LG-H
LNA Analog Inverted Output for Channel G.
LNA Analog Switched Output for Channel G.
LNA Analog Input for Channel G.
LNA Ground for Channel G.
LNA Analog Inverted Output for Channel H.
LNA Analog Switched Output for Channel H.
LNA Analog Input for Channel H.
LNA Ground for Channel H.
Clock Input Complement.
H1
CLK−
J1
CLK+
Clock Input True.
H2
J2
H11
H10
H9
H8
H7
TX_TRIG−
TX_TRIG+
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
NIC
Transmit Trigger Complement.
Transmit Trigger True.
Chip Address Bit 0.
Chip Address Bit 1.
Chip Address Bit 2.
Chip Address Bit 3.
Chip Address Bit 4.
L2, M2, L3, M3, L10, M10, L11, M11
Not Internally Connected. These pins are not connected internally. Allow the
NIC pins to float, or connect them to ground. Avoid routing high speed signals
through these pins because noise coupling may result.
L4
SYNCINB+
SYNCINB−
SERDOUT4−
SERDOUT4+
SERDOUT3−
SERDOUT3+
SERDOUT2−
SERDOUT2+
SERDOUT1−
SERDOUT1+
SYSREF−
Active Low JESD204B LVDS SYNC Input—True.
Active Low JESD204B LVDS SYNC Input—Complement.
Serial Lane 4 CML Output Data—Complement.
Serial Lane 4 CML Output Data—True.
Serial Lane 3 CML Output Data—Complement.
Serial Lane 3 CML Output Data—True.
Serial Lane 2 CML Output Data—Complement.
Serial Lane 2 CML Output Data—True.
Serial Lane 1 CML Output Data—Complement.
Serial Lane 1 CML Output Data—True.
Active Low JESD204B LVDS System Reference (SYSREF) Input—Complement.
Active Low JESD204B LVDS SYSREF Input—True.
Standby Power-Down.
M4
M5
L5
M6
L6
M7
L7
M8
L8
M9
L9
K11
J11
K12
J12
SYSREF+
STBY
PDWN
SCLK
Full Power-Down.
Serial Clock.
Serial Data Input/Output.
SDIO
Rev. A | Page 14 of 60
Data Sheet
AD9675
Pin No.
H12
B9
Mnemonic
CSB
LG-A
Description
Chip Select Bar.
LNA Ground for Channel A.
A9
LI-A
LNA Analog Input for Channel A.
D9
C9
LOSW-A
LO-A
LG-B
LI-B
LOSW-B
LO-B
LG-C
LI-C
LOSW-C
LO-C
LG-D
LNA Analog Switched Output for Channel A.
LNA Analog Inverted Output for Channel A.
LNA Ground for Channel B.
B10
A10
D10
C10
B11
A11
D11
C11
B12
A12
D12
C12
K10
J10
K9
J9
J8
K8
K7
J7
A8
A7
A6
LNA Analog Input for Channel B.
LNA Analog Switched Output for Channel B.
LNA Analog Inverted Output for Channel B.
LNA Ground for Channel C.
LNA Analog Input for Channel C.
LNA Analog Switched Output for Channel C.
LNA Analog Inverted Output for Channel C.
LNA Ground for Channel D.
LI-D
LOSW-D
LO-D
LNA Analog Input for Channel D.
LNA Analog Switched Output for Channel D.
LNA Analog Inverted Output for Channel D.
General-Purpose Open-Drain Output 0.
General-Purpose Open-Drain Output 1.
General-Purpose Open-Drain Output 2.
General-Purpose Open-Drain Output 3.
Synchronizing Input for LO Divide by M Counter Complement.
Synchronizing Input for LO Divide by M Counter True.
CW Doppler Multiple Local Oscillator Input Complement.
CW Doppler Multiple Local Oscillator Input True.
Gain Control Voltage Input Complement.
Gain Control Voltage Input True.
GPO0
GPO1
GPO2
GPO3
RESET−
RESET+
MLO−
MLO+
GAIN−
GAIN+
RBIAS
VREF
External Resistor to Set the Internal ADC Core Bias Current.
Voltage Reference Input/Output.
A5
K5
J5
K3
J3
CWI−
CWI+
CWQ−
CWQ+
CW Doppler I Output Complement.
CW Doppler I Output True.
CW Doppler Q Output Complement.
CW Doppler Q Output True.
Rev. A | Page 15 of 60
AD9675
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TGC MODE
Mode I = fSAMPLE = 40 MSPS, fIN = 5 MHz, low bandwidth mode, RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.6 dB, LNA bias =
midhigh, PGA gain = 27 dB, VGAIN (V) = (GAIN+) − (GAIN−) = 1.6 V, AAF LPF cutoff = fSAMPLE/3, HPF cutoff = LPF cutoff/12.00
(default), RF decimator bypassed, digital high-pass filter bypassed, unless otherwise noted.
2.0
25
20
15
10
5
1.5
1.0
0°C
0.5
0
25°C
85°C
–0.5
–1.0
–1.5
0
–2.0
–1.6
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
1.6
V
(V)
GAIN
GAIN ERROR (dB)
Figure 9. Gain Error vs. VGAIN
Figure 12. Gain Error Histogram, VGAIN = 1.28 V
25
20
15
10
5
20
15
10
5
0
0
GAIN ERROR (dB)
CHANNEL TO CHANNEL GAIN MATCHING (dB)
Figure 10. Gain Error Histogram, VGAIN = −1.28 V
Figure 13. Gain Matching Histogram, VGAIN = −1.2 V
35
30
25
20
15
10
5
20
15
10
5
0
0
GAIN ERROR (dB)
CHANNEL TO CHANNEL GAIN MATCHING (dB)
Figure 11. Gain Error Histogram, VGAIN = 0 V
Figure 14. Gain Matching Histogram, VGAIN = 1.2 V
Rev. A | Page 16 of 60
Data Sheet
AD9675
1.4
1.2
1.0
0.8
0.6
0.4
70
68
66
64
62
60
58
56
54
52
LNA
= 17.9dB
GAIN
LNA
= 15.6dB
GAIN
LNA
= 21.6dB
GAIN
50
10
1
2
3
4
5
6
7
8
9
10
15
20
25
30
35
40
45
50
55
FREQUENCY (MHz)
CHANNEL GAIN (dB)
Figure 15. Short-Circuit, Input Referred Noise vs. Frequency
Figure 18. SNR vs. Channel Gain and LNA Gain, AOUT = −1.0 dBFS
74
–132
PGA GAIN = 21dB
PGA
= 21dB
GAIN
72
70
68
66
64
62
60
58
56
54
–134
–136
–138
–140
–142
–144
–146
PGA
= 24dB
GAIN
PGA
= 27dB
GAIN
PGA
= 30dB
GAIN
–5
0
5
10 15 20 25 30 35 40 45 50 55
CHANNEL GAIN (dB)
–5
0
5
10
15
20
25
30
35
40
45
CHANNEL GAIN (dB)
Figure 19. SNR vs. Channel Gain and PGA Gain, AIN = −45 dBm
Figure 16. Short-Circuit, Output Referred Noise vs. Channel Gain,
LNA Gain = 21.6 dB, PGA Gain = 21 dB, VGAIN = 1.6 V
70
0
SPEED MODE = I (40MSPS)
PGA
= 21dB
GAIN
LOW BANDWIDTH MODE
68
66
64
62
60
58
56
54
52
50
–1
–2
–3
PGA
= 24dB
GAIN
–4
PGA
= 27dB
–5
GAIN
–6
PGA
= 30dB
GAIN
–7
–8
–9
–10
10
15
20
25
30
35
40
45
50
55
0
5
10
15
20
CHANNEL GAIN (dB)
INPUT FREQUENCY (MHz)
Figure 17. SNR vs. Channel Gain and PGA Gain, AOUT = −1.0 dBFS
Figure 20. Antialiasing Filter (AAF) Pass-Band Response,
LPF Cutoff = 1 × (1/3) × fSAMPLE, HPF = 1/12 × LPF Cutoff
Rev. A | Page 17 of 60
AD9675
Data Sheet
0
0
–10
MIN V
MAX V
, A
= –12.0dBFS
= –1.0dBFS
GAIN
OUT
, A
GAIN
OUT
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–20
–30
–40
–50
V
= –1.2V
GAIN
THIRD-ORDER, MIN V
GAIN
–60
THIRD-ORDER, MAX V
V
= 0V
GAIN
GAIN
–70
–80
SECOND-ORDER, MIN V
–90
GAIN
V
= +1.6V
GAIN
–100
–110
–120
SECOND-ORDER, MAX V
GAIN
2
3
4
5
6
7
8
9
10
11
–40
–35
–30
–25
–20
–15
–10
–5
0
INPUT FREQUENCY (MHz)
ADC OUTPUT LEVEL (dBFS)
Figure 21. Second-Order and Third-Order Harmonic Distortion vs. Input
Frequency
Figure 24. Second-Order Harmonic Distortion vs. ADC Output Level (AOUT)
0
–10
–20
–30
0
PGA
= 24dB
GAIN
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40
–50
V
= –1.2V
GAIN
–60
V
= 0V
GAIN
–70
LNA
= 17.9dB
–80
GAIN
LNA
= 21.6dB
–90
GAIN
V
= +1.6V
–5
–100
–110
–120
GAIN
LNA
= 15.6dB
GAIN
–40
–35
–30
–25
–20
–15
–10
0
10
15
20
25
30
35
40
45
50
ADC OUTPUT LEVEL (dBFS)
CHANNEL GAIN (dB)
Figure 25. Third-Order Harmonic Distortion vs. ADC Output Level (AOUT
)
Figure 22. Second-Order Harmonic Distortion vs. Channel Gain,
OUT = −1.0 dBFS
A
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–100
–110
–120
–130
–140
–150
–160
PGA
= 24dB
GAIN
LNA
= 17.9dB
GAIN
LNA
= 21.6dB
GAIN
LNA
= 15.6dB
GAIN
10
15
20
25
30
35
40
45
100
1k
10k
100k
CHANNEL GAIN (dB)
OFFSET FREQUENCY FROM CARRIER (Hz)
Figure 23. Third-Order Harmonic Distortion vs. Channel Gain,
OUT = −1.0 dBFS
Figure 26. TGC Path Phase Noise,
LNA Gain = 21.6 dB, PGA Gain = 27 dB, VGAIN = 0 V
A
Rev. A | Page 18 of 60
Data Sheet
AD9675
8
7
6
5
4
3
2
0
–10
fIN1 = 5.0MHz
fIN2 = 5.01MHz
FUND1 LEVEL = –1dBFS
FUND2 LEVEL = –21dBFS
–20
–30
–40
1
0
100k
–50
1M
10M
FREQUENCY (Hz)
100M
–60
V
= –1.2V
0
–10
–20
–30
–40
–50
–60
–70
–80
GAIN
–70
–80
–90
–100
–110
–120
V
= +1.6V
GAIN
V
= 0V
GAIN
–90
100k
–40
–35
–30
–25
–20
–15
–10
–5
0
1M
10M
FREQUENCY (Hz)
100M
ADC OUTPUT LEVEL (dBFS)
Figure 27. LNA Input Impedance Magnitude and Phase, Unterminated
Figure 29. IMD3 vs. ADC Output Level
0
7
6
5
4
3
2
1
fIN1 = 2.3MHz
fIN2 = 2.31MHz
–10
FUND1 LEVEL = –1dBFS
FUND2 LEVEL = –21dBFS
–20
R
= 50Ω
S
–30
–40
–50
–60
–70
–80
–90
–100
R
= 1000Ω
IN
R
R
= 50Ω
IN
= 300Ω
IN
15
20
25
30
35
40
45
50
0
2
4
6
8
10
12
14
16
18
20
CHANNEL GAIN (dB)
FREQUENCY (MHz)
Figure 28. IMD3 vs. Channel Gain
Figure 30. Noise Figure vs. Frequency
RS = RIN = 100 Ω, LNA Gain = 17.9 dB, PGA Gain = 30 dB, VGAIN = 1.6 V
Rev. A | Page 19 of 60
AD9675
Data Sheet
CW DOPPLER MODE
fIN = 5 MHz, fLO = 20 MHz, 4LO mode, RS = 50 Ω, LNA gain = 21.6 dB, LNA bias = midhigh, all CW channels enabled, phase rotation = 0°.
10
9
8
7
6
5
4
3
2
1
0
165
160
155
150
145
140
135
130
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
BASEBAND FREQUENCY (Hz)
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
BASEBAND FREQUENCY (Hz)
Figure 31. Noise Figure vs. Baseband Frequency
Figure 32. Output Referred SNR vs. Baseband Frequency
Rev. A | Page 20 of 60
Data Sheet
AD9675
THEORY OF OPERATION
MLO–
MLO+
LO
CWQ+
GENERATION
RESET+
RESET–
CWQ–
R
R
FB1
FB2
LO-x
CWI+
CWI–
LOSW-x
T/R
SWITCH
C
S
SERDOUT1+
LI-x
TO SERDOUT4+
PIPELINE
ADC
FILTER/
DEC
SERIAL
CML
ATTENUATOR
–45dB TO 0dB
POST
AMP
LNA
FILTER
LG-x
SERDOUT1–
TO SERDOUT4–
C
SH
C
LG
15.6dB,
17.9dB,
21.6dB
21dB,
SYSREF+
SYSREF–
SYNCINB+
SYNCINB–
24dB,
27dB,
30dB
GAIN
INTERPOLATOR
TRANSDUCER
gm
GAIN+ GAIN–
TX_TRIG+ TX_TRIG–
Figure 33. Simplified Block Diagram of a Single Channel
Each channel of the AD9675 contains both a TGC signal path and
a CW Doppler signal path. Common to both signal paths, the LNA
provides four user adjustable input impedance termination options
for matching different probe impedances. The CW Doppler
path includes an I/Q demodulator with programmable phase
rotation needed for analog beamforming. The TGC path includes
a differential X-AMP® VGA, an antialiasing filter, an ADC, and
a digital RF decimation by 2 and high-pass filter. Figure 33
shows a simplified block diagram with external components.
In its default condition, the LNA has a gain of 21.6 dB (12×),
and the VGA postamp gain is 24 dB. If the voltage on the
GAIN+ pin is 0 V and the voltage on the GAIN− pin is 1.6 V
(44.8 dB attenuation), the total gain of the channel is 0.8 dB if
the LNA input is unmatched. The channel gain is −5.2 dB if the
LNA is matched to 50 Ω (RFB = 300 Ω). However, if the voltage on
the GAIN+ pin is 1.6 V and the voltage on the GAIN− pin is 0 V
(0 dB attenuation), VGAATT is 0 dB. This results in a total gain of
45.6 dB through the TGC path if the LNA input is unmatched, or
in a total gain of 39.6 dB if the LNA input is matched. Similarly,
if the LNA input is unmatched and has a gain of 21.6 dB (12×),
and the VGA postamp gain is 30 dB, the channel gain is
TGC OPERATION
The system gain is distributed as listed in Table 7.
approximately 52 dB with 0 dB VGAATT
.
Table 7. Channel Analog Gain Distribution
In addition to the analog VGA attenuation described in
Equation 2, the attenuation level can be digitally controlled in
3.5 dB increments. Equation 3 is still valid, and the value of
VGAATT is equal to the attenuation level set in Address 0x011,
Bits[7:4].
Section
Nominal Gain (dB)
LNA
15.6/17.9/21.6 (LNAGAIN
−45 to 0 (VGAATT)
21/24/27/30 (PGAGAIN
0
0
)
Attenuator
VGA Amplifier
Filter
)
ADC
Low,Noise,Amplifier,(LNA),
Each LNA output is dc-coupled to a VGA input. The VGA
consists of an attenuator with a range of −45 dB to 0 dB
followed by an amplifier with a selectable gain of 21 dB, 24 dB,
27 dB, or 30 dB. The X-AMP gain interpolation technique
results in low gain error and uniform bandwidth, and
differential signal paths minimize distortion.
Good system sensitivity relies on a proprietary ultralow noise
LNA at the beginning of the signal chain, which minimizes the
noise contribution in the following VGA. Active impedance
control optimizes noise performance for applications that
benefit from input impedance matching.
The LNA input, LI-x, is capacitively coupled to the source.
An on-chip bias generator establishes dc input bias voltages of
approximately 2.2 V and centers the output common-mode
levels at 1.5 V (AVDD2 divided by 2). A capacitor, CLG, of the
same value as the input coupling capacitor, CS, is connected
from the LG-x pin to ground.
The linear in dB gain (law conformance) range of the TGC path
is 45 dB. The slope of the gain control interface is 14 dB/V, and
the gain control range is −1.6 V to +1.6 V. Equation 1 is the
expression for the differential voltage, VGAIN, at the gain control
interface. Equation 2 is the expression for the VGA attenuation,
VGAATT, as a function of VGAIN
GAIN (V) = (GAIN+) − (GAIN−)
VGAATT (dB) = −14 (dB/V) × (1.6 − VGAIN
.
The LNA supports three gains, 21.6 dB, 17.9 dB, or 15.6 dB, set
through the SPI. Overload protection ensures quick recovery
time from large input voltages.
V
(1)
(2)
)
Low value feedback resistors and the current driving capability
of the output stage allow the LNA to achieve a low input
referred noise voltage of 0.78 nV/√Hz (at a gain of 21.6 dB).
Then, calculate the total channel gain as in Equation 3.
Channel Gain (dB) = LNAGAIN + VGAATT + PGAGAIN
(3)
Rev. A | Page 21 of 60
AD9675
Data Sheet
On-chip resistor matching results in precise single-ended gains,
which are critical for accurate impedance control. The use of a
fully differential topology and negative feedback minimizes
distortion. Low second-order harmonic distortion is particularly
important in harmonic ultrasound imaging applications.
R
FB is the resulting impedance of the RFB1 and RFB2 combination
(see Figure 33). Use Register 0x02C in the SPI memory to
program the AD9675 for four impedance matching options:
three active terminations and unterminated. Table 8 shows an
example of how to select RFB1 and RFB2 for 66 Ω, 100 Ω, and
200 Ω input impedance for LNA gain = 21.6 dB (12×).
Active Impedance Matching
Table 8. Active Termination Example for LNA Gain = 21.6 dB,
The LNA consists of a single-ended voltage gain amplifier with
differential outputs and the negative output externally available
on two output pins (LO-x and LOSW-x) that are controlled via
internal switches. This configuration allows active input
impedance synthesis of 3 different impedance values (and
unterminated value) via connecting up to two external
resistances in parallel and controlling the internal switch states
via SPI. This well known technique is used for interfacing
multiple probe impedances to a single system. For example,
with a fixed gain of 8× (17.9 dB), an active input termination is
synthesized by connecting a feedback resistor between the
negative output pin, LO-x, and the positive input pin, LI-x.
The input resistance calculation is shown in Equation 4.
RFB1 = 650 Ω, RFB2 = 1350 Ω
Addr 0x02C
Value
LO-x
LOSW-x
RIN (Ω)
RS (Ω) Switch Switch
RFB (Ω)
RFB1
RFB1||RFB2
RFB2
(Eq. 4)
100
69
200
∞
00 (default)
100
50
200
N/A1
On
On
Off
Off
Off
On
On
Off
01
10
11
∞
1 N/A means not applicable.
The bandwidth (BW) of the LNA is greater than 80 MHz.
Ultimately, the BW of the LNA limits the accuracy of the
synthesized RIN. For RIN = RS up to about 200 Ω, the best match
is between 100 kHz and 10 MHz, where the lower frequency
limit is determined by the size of the ac coupling capacitors, and
the upper limit is determined by the LNA BW. Furthermore, the
input capacitance and RS limit the BW at higher frequencies.
Figure 34 shows RIN vs. frequency for various values of RFB.
1k
(RFB1 20 )||(RFB2 20 ) 30
RIN
(4)
A
(1
)
2
where:
FB1 and RFB2 are the external feedback resistors.
20 Ω is the internal switch on resistance.
R
R
= 500Ω, R = 2kΩ
S
FB
30 Ω is an internal series resistance common to the two internal
switches.
R
R
= 200Ω, R = 800Ω
A/2 is the single-ended gain or the gain from the LI-x inputs to
the LO-x outputs.
S
FB
= 100Ω, R = 400Ω, C = 20pF
FB SH
S
100
RFB can be equal to RFB1, RFB2, or (RFB1 + 20)||(RFB2 + 20)
depending on the connection status of the internal switches.
R
= 50Ω, R = 200Ω, C = 70pF
FB SH
S
Because the amplifier has a gain of 8× from its input to its
differential output, it is important to note that the gain, A/2, is
the gain from Pin LI-x to Pin LO-x and that it is 6 dB less than
the gain of the amplifier, or 12.1 dB (4×). The input resistance is
reduced by an internal bias resistor of 6 kΩ in parallel with the
source resistance connected to pin LI-x, with Pin LG-x ac
grounded. Use, the more accurate, Equation 5 to calculate the
required RFB for a desired RIN, even for higher values of RIN.
10
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 34. RIN vs. Frequency for Various Values of RFB
(Effects of RSH and CSH Are Also Shown)
However, for larger RIN values, parasitic capacitance starts
rolling off the signal BW before the LNA can produce peaking.
SH further degrades the match; therefore, do not use CSH for
(RFB1 20 )||(RFB2 20 ) 30
RIN
||6 k
(5)
C
(1 A/2)
values of RIN that are greater than 100 Ω. Table 9 lists the
recommended values for RFB and CSH in terms of RIN. CFB is
needed in series with RFB because the dc levels at Pin LO-x and
Pin LI-x are unequal.
For example, to set RIN to 200 Ω with a single-ended LNA gain of
12.1 dB (4×), the value of RFB1 from Equation 4 must be 950 Ω,
while the switch for RFB2 is open. If the more accurate equation
(Equation 5) is used to calculate RIN, the value is then 194 Ω
instead of 200 Ω, resulting in a gain error of less than 0.27 dB.
Some factors, such as the presence of a dynamic source resistance,
may influence the absolute gain accuracy more significantly. At
higher frequencies, the input capacitance of the LNA must be
considered. The user must determine the level of matching
accuracy and adjust RFB1 and RFB2 accordingly.
Rev. A | Page 22 of 60
Data Sheet
AD9675
8
7
6
5
4
3
2
1
0
Table 9. Active Termination External Component Values
R
R
R
R
= 50Ω
= 75Ω
= 100Ω
= 200Ω
IN
IN
IN
IN
LNA Gain (dB)
RIN (Ω)
RFB (Ω)
Minimum CSH (pF)
15.6
50
150
90
17.9
50
200
70
UNTERMINATED
21.6
50
300
50
15.6
17.9
21.6
15.6
17.9
21.6
100
100
100
200
200
200
350
450
650
750
950
1350
30
20
10
Not applicable
Not applicable
Not applicable
10
100
(Ω)
1k
R
S
LNA Noise
Figure 36. Noise Figure vs. RS for Various Fixed Values of RIN,
Active Termination Matched Inputs, VGAIN = 1.6 V
The short-circuit noise voltage (input referred noise) is an impor-
tant limit on system performance. The short-circuit noise voltage
for the LNA is 0.78 nV/√Hz at a gain of 21.6 dB, including the
VGA noise at a VGA postamp gain of 27 dB. These measurements,
which were taken without a feedback resistor, provide the basis
for calculating the input noise and noise figure (NF) performance.
CLNA Connection
CLNA (Pin B7) must have a 1 nF capacitor attached to AVDD2.
DC Offset Correction/High-Pass Filter
The AD9675 LNA architecture corrects for dc offset voltages
that can develop on the external CS capacitor due to leakage of
the transmit (Tx)/receive (Rx) switch during ultrasound
transmit cycles. The dc offset correction, as shown in Figure 37,
provides a feedback mechanism to the LG-x input of the LNA
to correct for this dc voltage.
Figure 35 and Figure 36 are simulations of noise figure vs. RS
results with different input configurations and an input referred
noise voltage of 2.5 nV/√Hz for the VGA. Unterminated (RFB = ∞)
operation exhibits the lowest equivalent input noise and noise
figure. Figure 36 shows the noise figure vs. source resistance rising
at low RS, where the LNA voltage noise is large compared with
the source noise, and at high RS due to the noise contribution
from RFB. The lowest NF is achieved when RS matches RIN.
AD9675
R
FB1
FB2
LO-x
R
LOSW-x
Figure 35 shows the relative noise figure performance. With an
LNA gain of 21.6 dB, the input impedance is swept with RS to
preserve the match at each point. The noise figures for a source
impedance of 50 Ω are 7 dB, 4 dB, and 2.5 dB for the shunt
termination, active termination, and unterminated configura-
tions, respectively. The noise figures for 200 Ω are 4.5 dB, 1.7 dB,
and 1 dB, respectively.
Tx/Rx
SWITCH
C
S
LI-x
LG-x
LNA
C
SH
15.6dB,
17.9dB,
21.6dB
C
LG
TRANSDUCER
gm
12.0
DC OFFSET
CORRECTION
10.5
9.0
Figure 37. Simplified LNA Input Configuration
The feedback acts as high-pass filter providing dynamic
correction of the dc offset. The cutoff frequency of the high-
pass filter response is dependent on the value of the CLG
capacitor, the gain of the LNA (LNAGAIN) and the gm of the
feedback transconductance amplifier. The gm value is
programmed in Register 0x120, Bits[4:3]. Ensure that CS is
equal to CLG for proper operation.
7.5
SHUNT TERMINATION
6.0
4.5
3.0
ACTIVE TERMINATION
UNTERMINATED
1.5
0
Table 10. High-Pass Filter Cutoff Frequency, fHP, for CLG = 10 nF
10
100
(Ω)
1k
R
Address
0x120[4:3]
LNAGAIN
15.6 dB
=
LNAGAIN
17.9 dB
=
LNAGAIN
21.6 dB
=
S
gm
Figure 35. Noise Figure vs. RS for Shunt Termination, Active
Termination Matched and Unterminated Inputs, VGAIN = 1.6 V
00 (default)
0.5 mS 41 kHz
1.0 mS 83 kHz
1.5 mS 133 kHz
2.0 mS 167 kHz
55 kHz
83 kHz
01
10
11
110 kHz
178 kHz
220 kHz
167 kHz
267 kHz
330 kHz
Figure 36 shows the noise figure as it relates to RS for various
values of RIN, which is helpful for design purposes.
Rev. A | Page 23 of 60
AD9675
Data Sheet
For other values of CLG, determine the high-pass filter cutoff
frequency by scaling the values from Table 10 or calculating
based on CLG, LNAGAIN, and gm, as shown in Equation 6.
VGA Noise
In a typical application, a VGA compresses a wide dynamic
range input signal to within the input span of an ADC. The
input referred noise of the LNA limits the minimum resolvable
input signal, whereas the output referred noise, which depends
primarily on the VGA, limits the maximum instantaneous dynamic
range that can be processed at any one particular gain control
voltage. This latter limit is set in accordance with the total noise
floor of the ADC.
10 nF
CLG
1
2
gm
CLG
(6)
f
HP (CLG )
LNAGAIN
fHP
where fHP is the high-pass filter cutoff frequency (see Table 10).
Variable,Gaiy,Amplifier,(VGA),
The differential X-AMP VGA provides precise input attenu-
ation and interpolation. It has a low input referred noise of
2.5 nV/√Hz and excellent gain linearity. The VGA is driven by a
fully differential input signal from the LNA. The X-AMP archi-
tecture produces a linear-in-dB gain law conformance and low
distortion levels—deviating only 0.5 dB or less from the ideal.
The gain slope is monotonic with respect to the control voltage
and is stable with variations in process, temperature, and supply.
The resulting total gain range is 45 dB, which allows range loss
at the endpoints.
The output referred noise is a flat 40 nV/√Hz (postamp gain =
24 dB) over most of the gain range because it is dominated by
the fixed output referred noise of the VGA. At the high end of the
gain control range, the noise of the LNA and the source prevail.
The input referred noise reaches its minimum value near the
maximum gain control voltage, where the input referred
contribution of the VGA is miniscule.
At lower gains, the input referred noise and, therefore, the noise
figure increase as the gain decreases. The instantaneous dynamic
range of the system is not lost, however, because the input capacity
increases as the input referred noise increases. The contribution of
the ADC noise floor has the same dependence. The important
relationship is the magnitude of the VGA output noise floor
relative to that of the ADC.
The X-AMP inputs are part of a PGA that completes the VGA.
The PGA in the VGA can be programmed to a gain of 21 dB,
24 dB, 27 dB, or 30 dB, allowing for optimization of channel
gain for different imaging modes in the ultrasound system.
The VGA bandwidth is greater than 100 MHz. The input stage
ensures excellent frequency response uniformity across the gain
setting. For TGC mode, this minimizes time delay variation
across the gain range.
Gain control noise is a concern in very low noise applications.
Thermal noise in the gain control interface can modulate the
channel gain. The resulting noise is proportional to the output
signal level and is usually evident only when a large signal is
present. Take care to minimize noise impinging at the GAIN
inputs. Use an external RC filter to remove VGAIN source noise.
Ensure that the filter bandwidth is sufficient to accommodate the
desired control bandwidth and attenuate unwanted switching noise
from the external DACs used to drive the gain control.
Gain Control
The analog gain control interface, GAIN , is a differential
input. VGAIN varies the gain of all VGAs through the interpolator
by selecting the appropriate input stages connected to the input
attenuator. The nominal VGAIN range is 14 dB/V from −1.6 V to
+1.6 V, with the best gain linearity from approximately −1.44 V
to +1.44 V, where the error is typically less than 0.5 dB. For
The AD9675 can bypass the GAIN inputs and control the gain
of the attenuator digitally (see the Gain Control section). This
mode removes any external noise contributions when active gain
control is not needed.
VGAIN voltages of greater than 1.44 V and less than −1.44 V, the
error increases. The value of GAIN can exceed the supply
voltage by 1 V without gain foldover.
Gain control response time is less than 750 ns to settle within 10%
of the final value for a change from minimum to maximum gain.
Aytialiasiyg,Filter,(AAF),
The filter that the signal reaches prior to the ADC is used to
reject dc signals and to band limit the signal for antialiasing.
The antialiasing filter is a combination of a single-pole, high-pass
filter and a second-order, low-pass filter. Configure the high-
pass filter as a ratio of the low-pass filter cutoff frequency using
Address 0x02B, Bits[1:0].
The differential input pins, GAIN+ and GAIN−, can interface
to an amplifier, as shown in Figure 38. Decouple and drive the
GAIN+ and GAIN− pins to accommodate a 3.2 V full-scale input.
249Ω
31.3kΩ
±1.6V
±0.8V DC
AD9675
249Ω
100Ω
AT 0.8V CM
GAIN+
The filter uses on-chip tuning to trim the capacitors and, in
turn, to set the desired low-pass cutoff frequency and reduce
variations. The default −3 dB low-pass filter cutoff is 1/3, 1/4.5,
or 1/6 of the ADC sample clock rate. The cutoff can be scaled to
0.75, 0.8, 0.9, 1.0, 1.13, 1.25, or 1.45 times this frequency using
Address 0x00F. The cutoff tolerance ( 10%) is maintained from
8 MHz to 18 MHz for low bandwidth mode or 13.5 MHz to
30 MHz for high bandwidth mode.
ADA4938-1
ADA4938-2
0.8V CM
0.01µF
100Ω
249Ω
10kΩ
GAIN–
±0.8V DC
AT 0.8V CM
0.01µF
249Ω
Figure 38. Differential GAIN Pin Configuration
Use Address 0x011, Bits[7:4], to disable the analog gain control
and to control the attenuator digitally. The control range is
45 dB and the step size is 3.5 dB.
Rev. A | Page 24 of 60
Data Sheet
AD9675
Table 11 and Table 12 calculate the valid SPI-selectable low-pass
filter settings and expected cutoff frequencies for the low
bandwidth and high bandwidth modes at the minimum sample
frequency and the maximum sample frequency in each speed
mode.
after reprogramming of the filter cutoff scaling or the ADC
sample rate. The tuning is initiated using Address 0x02B, Bit 6.
Four SPI-programmable settings allow users to vary the high-
pass filter cutoff frequency as a function of the low-pass cutoff
frequency. Two examples are shown in Table 13: an 8 MHz low-
pass cutoff frequency and an 18 MHz low-pass cutoff frequency. In
both cases, as the ratio decreases, the amount of rejection on the
low end frequencies increases. Therefore, making the entire AAF
frequency pass band narrow can reduce low frequency noise or
maximize dynamic range for harmonic processing.
Tuning is normally off to avoid changing the capacitor settings
during critical times. The tuning circuit is enabled through the
SPI. It is disabled automatically after 512 cycles of the ADC sample
clock. Initialize the tuning of the filter after initial power-up and
Table 11. SPI-Selectable Low-Pass Filter Cutoff Options for Low Bandwidth Mode at Example Sampling Frequencies
Sampling Frequency (MHz)
Address LPF Cutoff
0x00F[7:3] Frequency (MHz)
20.5
40
65
80
125
0 0000
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1.45 × (1/3) × fSAMPLE
1.25 × (1/3) × fSAMPLE
1.13 × (1/3) × fSAMPLE
1.0 × (1/3) × fSAMPLE
0.9 × (1/3) × fSAMPLE
0.8 × (1/3) × fSAMPLE
0.75 × (1/3) × fSAMPLE
9.91
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
8.54
16.67
15.00
13.33
12.00
10.67
10.00
12.89
11.11
10.00
8.89
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
17.33
16.25
20.94
18.06
16.25
14.44
13.00
11.56
10.83
15.71
13.54
12.19
10.83
9.75
Out of tunable
filter range
16.82
1.45 × (1/4.5) × fSAMPLE Out of tunable
filter range
1.25 × (1/4.5) × fSAMPLE Out of tunable
filter range
1.13 × (1/4.5) × fSAMPLE Out of tunable
filter range
1.0 × (1/4.5) × fSAMPLE
0.9 × (1/4.5) × fSAMPLE
0.8 × (1/4.5) × fSAMPLE
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
17.78
16.00
14.22
13.33
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
8.00
Out of tunable
filter range
Out of tunable
filter range
0.75 × (1/4.5) × fSAMPLE Out of tunable
filter range
17.50
1.45 × (1/6) × fSAMPLE
1.25 × (1/6) × fSAMPLE
1.13 × (1/6) × fSAMPLE
1.0 × (1/6) × fSAMPLE
0.9 × (1/6) × fSAMPLE
0.8 × (1/6) × fSAMPLE
0.75 × (1/6) × fSAMPLE
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
9.67
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
8.33
16.67
15.00
13.33
12.00
10.67
10.00
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
16.67
8.67
Out of tunable
filter range
8.13
15.63
Rev. A | Page 25 of 60
AD9675
Data Sheet
Table 12. SPI-Selectable Low-Pass Filter Cutoff Options for High Bandwidth Mode at Example Sampling Frequencies
Sampling Frequency (MHz)
Address LPF Cutoff
0x00F[7:3] Frequency (MHz)
20.5
40
65
80
125
0 0000
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1.45 × (1/3) × fSAMPLE
1.25 × (1/3) × fSAMPLE
1.13 × (1/3) × fSAMPLE
1.0 × (1/3) × fSAMPLE
0.9 × (1/3) × fSAMPLE
0.8 × (1/3) × fSAMPLE
0.75 × (1/3) × fSAMPLE
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
19.33
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
16.67
15.00
27.08
24.38
21.67
19.50
17.33
16.25
20.94
18.06
16.25
14.44
30.00
26.67
24.00
21.33
20.00
25.78
22.22
20.00
17.78
16.00
14.22
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
1.45 × (1/4.5) × fSAMPLE Out of tunable
filter range
1.25 × (1/4.5) × fSAMPLE Out of tunable
filter range
1.13 × (1/4.5) × fSAMPLE Out of tunable
filter range
1.0 × (1/4.5) × fSAMPLE
0.9 × (1/4.5) × fSAMPLE
0.8 × (1/4.5) × fSAMPLE
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
27.78
25.00
22.22
20.83
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
0.75 × (1/4.5) × fSAMPLE Out of tunable
filter range
Out of tunable
filter range
1.45 × (1/6) × fSAMPLE
1.25 × (1/6) × fSAMPLE
1.13 × (1/6) × fSAMPLE
1.0 × (1/6) × fSAMPLE
0.9 × (1/6) × fSAMPLE
0.8 × (1/6) × fSAMPLE
0.75 × (1/6) × fSAMPLE
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
15.71
19.33
16.67
15.00
Out of tunable
filter range
13.54
26.04
23.44
20.83
18.75
16.67
15.63
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Out of tunable
filter range
Table 13. High-Pass Filter Cutoff Options
High-Pass Cutoff Frequency
Low-Pass Cutoff = 18 MHz
Address 0x02B[1:0] High-Pass
Filter Cutoff
Ratio1
12.00
9.00
6.00
3.00
Low-Pass Cutoff = 8 MHz
670 kHz
890 kHz
1.33 MHz
2.67 MHz
00 (default)
1.5 MHz
2.0 MHz
3.0 MHz
6.0 MHz
01
10
11
1 Ratio is the low-pass filter cutoff frequency/high-pass filter cutoff frequency.
Rev. A | Page 26 of 60
Data Sheet
AD9675
3.3V
AAF/VGA Test Mode
AD9524/AD9516-0
VFAC3
OUT
0.1µF
0.1µF
For debug and testing, there is a bypass switch to view the AAF
output on the GPO2 and GPO3 pins. Enable this mode via SPI
Address 0x109, Bit 4. The differential AAF output of only one
channel can be accessed at a time. The dc output voltage is 1.5 V
(or AVDD2/2) and the maximum ac output voltage is 2 V p-p.
CLK+
CLK
PECL DRIVER
CLK
50Ω*
0.1µF
100Ω
ADC
0.1µF
CLK–
240Ω
240Ω
ADC,
*50Ω RESISTOR IS OPTIONAL.
The AD9675 uses a pipelined ADC architecture. The quantized
output from each stage is combined into a 14-bit result in the
digital correction logic. The pipelined architecture permits the
first stage to operate on a new input sample and the remaining
stages to operate on preceding samples. Sampling occurs on the
rising edge of the clock.
Figure 40. Differential PECL Sample Clock
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 41.
3.3V
AD9524/AD9516-0
0.1µF
VFAC3
OUT
0.1µF
CLK+
CLK
LVDS DRIVER
CLK
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and output clocks.
50Ω*
0.1µF
100Ω
0.1µF
ADC
CLK–
Clock Input Considerations
*50Ω RESISTOR IS OPTIONAL.
For optimum performance, clock the AD9675 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally and
require no additional bias.
Figure 41. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
drive CLK+ directly from a CMOS gate, and bypass the CLK−
pin to ground with a 0.1 μF capacitor (see Figure 42).
3.3V
Figure 39 shows the preferred method for clocking the AD9675.
A low jitter clock source, such as the Valpey Fisher oscillator,
VFAC3AHL-1 80.000, is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9675 to approximately 0.8 V p-p differential. This
prevents the large voltage swings of the clock from feeding
through to other portions of the AD9675, and it preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
AD9524/AD9516-0
0.1µF
VFAC3
CLK
CMOS DRIVER
CLK
OUT
OPTIONAL
100Ω
0.1µF
50Ω*
CLK+
ADC
0.1µF
CLK–
0.1µF
*50Ω RESISTOR IS OPTIONAL.
Figure 42. Single-Ended 1.8 V CMOS Sample Clock
3.3V
®
MINI-CIRCUITS
Clock Duty Cycle Considerations
ADT1-1WT, 1:1Z
0.1µF
0.1µF
XFMR
CLK+
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs can
be sensitive to the clock duty cycle. Commonly, a 5% tolerance
is required on the clock duty cycle to maintain dynamic
performance characteristics. The AD9675 contains a duty cycle
stabilizer (DCS) that retimes the nonsampling edge, providing
an internal clock signal with a nominal 50% duty cycle. This
allows a wide range of clock input duty cycles without affecting
the performance of the AD9675. When the DCS is on, noise
and distortion performance are nearly flat for a wide range of
duty cycles. However, some applications may require the DCS
function to be off. When the DCS function is off, the dynamic
range performance can be affected.
OUT
100Ω
50Ω
ADC
VFAC3
0.1µF
CLK–
SCHOTTKY
DIODES:
HSM2812
0.1µF
Figure 39. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac couple a
differential positive emitter-coupled logic (PECL) signal to the
sample clock input pins, as shown in Figure 40. Analog Devices
offers clock drivers with excellent jitter performance, such as
the AD9516-0 or the AD9524.
The duty cycle stabilizer uses a delay-locked loop (DLL) to create
the nonsampling edge. As a result, any changes to the sampling
frequency require approximately eight clock cycles to allow the
DLL to acquire and lock to the new rate.
Rev. A | Page 27 of 60
AD9675
Data Sheet
By asserting the STBY pin high, the AD9675 is placed in standby
mode. In this state, the device typically dissipates 725 mW.
During standby, the entire device is powered down except the
internal references. The LVDS output drivers are placed into a
high impedance state. This mode is well suited for applications
that require power savings because it allows the device to be
powered down when not in use and then quickly powers up.
The time to power up the device is also greatly reduced. The
AD9675 returns to normal operating mode when the STBY pin
is pulled low. This pin is only 1.8 V tolerant. To drive the STBY
pin from a 3.3 V logic level, insert a 1 kΩ resistor in series with
this pin to limit the current.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. Calculate the degradation in SNR at a given input
frequency (fA) due only to aperture jitter (tJ) as follows:
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
(7)
In this equation, the rms aperture jitter represents the root
mean square of all jitter sources, including the clock input,
analog input signal, and ADC aperture jitter (see Figure 43).
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9675. Separate
power supplies for clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter, crystal controlled oscillators make the best clock
sources, such as the Valpey Fisher VFAC3 series. If the clock is
generated from another type of source (by gating, dividing, or
other methods), it is retimed by the original clock during the
last step.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on VREF are discharged
when entering power-down mode and must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in power-down mode: shorter cycles
result in proportionally shorter wake-up times. To restore the
device to full operation, approximately 375 μs is required when
using the recommended 1 μF and 0.1 μF decoupling capacitors
on the VREF pin and the 0.01 μF decoupling capacitors on the
GAIN pins. Most of this time is dependent on gain decoupling;
higher value decoupling capacitors on the GAIN pins result in
longer wake-up times.
For more information on how jitter performance relates to
ADCs, refer to the AN-501 Application Note and the AN-756
Application Note.
130
RMS CLOCK JITTER REQUIREMENT
120
110
16 BITS
100
90
80
70
60
50
40
30
A number of other power-down options are available when using
the SPI port interface. The user can individually power down
each channel or place the entire device into standby mode. When
fast wake-up times are required, standby mode allows the user
to keep the internal PLL powered up. The wake-up time is slightly
dependent on gain. To achieve a 2 μs wake-up time when the
device is in standby mode, apply 0.8 V to the GAIN pins.
14 BITS
12 BITS
10 BITS
8 BITS
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
Power,ayd,Grouyd,Coyyectioy,Recommeydatioys,
1
10
100
1000
When connecting power to the AD9675, use two separate 1.8 V
supplies: one for analog (AVDD1) and one for digital (DRVDD).
If only one 1.8 V supply is available, route it to the AVDD1 pin
first and then tap it off and isolate it with a ferrite bead or a filter
choke preceded by decoupling capacitors for the DRVDD pin.
ANALOG INPUT FREQUENCY (MHz)
Figure 43. Ideal SNR vs. Input Frequency and Jitter
Power,Dissipatioy,ayd,Power-Dowy,Mode,
The power dissipated by the AD9675 is proportional to its
sample rate. The digital power dissipation does not vary
significantly because it is determined primarily by the DRVDD
supply and the bias current of the LVDS output drivers. The
AD9675 features scalable LNA bias currents (see Table 31,
Address 0x012). The default LNA bias current settings are
midhigh.
The DVDD pin can be tied to the 1.8 V DRVDD supply. When
this is done, route the DVDD supply first, tap it off, and isolate
it with a ferrite bead or filter choke preceded by decoupling
capacitors for the DRVDD pin. It is not recommended to use
the same supply for AVDD1, DVDD, and DRVDD. For
compatibility with the AD9671 or for lower power operation,
the DVDD pin can be tied to 1.4 V.
By asserting the PDWN pin high, the AD9675 is placed into
power-down mode. In this state, the device typically dissipates
5 mW. During power-down, the LVDS output drivers are placed
into a high impedance state. The AD9675 returns to normal
operating mode when the PDWN pin is pulled low. This pin is
only 1.8 V tolerant. To drive the PDWN pin from a 3.3 V logic
level, insert a 1 kΩ resistor in series with this pin to limit the
current.
For both high and low frequencies, use several decoupling
capacitors on all supplies. Place these capacitors near the point
of entry at the PCB level and near the device, with minimal
trace lengths.
When using the AD9675, a single PCB ground plane is sufficient.
With proper decoupling and smart partitioning of the analog,
Rev. A | Page 28 of 60
Data Sheet
AD9675
digital, and clock sections of the PCB, optimum performance
can be easily achieved.
a serial interface up to 5 Gbps link speeds. The benefits of the
JESD204B interface include a reduction in required board area
for data interface routing, and enables smaller packages for
converter and logic devices. The AD9675 supports single, dual,
or quad lane interfaces.
Advayced,Power,Coytrol,
For an ultrasound system, not all channels are needed during all
scanning periods. The POWER_START and POWER_STOP
values in the vector profile can be used to delay the channel
startup and turn the channel off after a certain number of samples.
These counters are relative to TX_TRIG . The analog circuitry
needs to power up before the digital one and the advance time
(POWER_SETUP) for powering up the analog circuitry, before
POWER_START, is set up in Address 0x112 (see Table 31).
JEꢀD204B,Overview,
The JESD204B data transmit block, as shown in Figure 45,
assembles the parallel channel data from the ADC or digital
processing block into frames and uses 8-bit/10-bit encoding as
well as optional scrambling to form serial output data. Lane
synchronization is supported through the use of special
characters during the initial establishment of the link, and
additional synchronization is embedded in the data stream
thereafter. A matching external receiver is required to lock onto
the serial data stream and recover the data and clock. For
additional details on the JESD204B interface, users are
encouraged to refer to the JESD204B standard.
POWER_STOP
(PROFILE SPECIFIC)
TX_TRIG±
POWER_START
(PROFILE SPECIFIC)
DIGITAL
POWER
The AD9675 JESD204B transmit block maps the eight channel
outputs over a link. A link can be configured to use either single,
dual, or quad serial differential outputs, which are called lanes.
The JESD204B specification refers to a number of parameters to
define the link, and these parameters must match between the
JESD204B transmitter (AD9675 output) and receiver.
ANALOG
POWER
POWER_SETUP
(SPI SET)
Figure 44. Power Sequencing
DIGITAL OUTPUTS AND TIMING
JEꢀD204B, raysmit, op,Level,Descriptioy,
The JESD204B link is described according to the parameters
listed in Table 14.
The AD9675 digital output complies with the JEDEC Standard
JESD204B, Serial Interface for Data Converters. JESD204B is a
protocol to link the AD9675 to a digital processing device over
Table 14. JESD204B Parameters
Parameter Description
AD9675 Value
S
M
L
N
N'
CF
Samples transmitted per single converter per frame cycle
Number of converters per converter device
Number of lanes per converter device
Converter resolution
Total number of bits per sample
Number of control words per frame clock cycle per
converter device
1
8
1, 2, or 4
12, 14, or 16
16
0
CS
K
HD
F
Number of control bits per conversion sample
Number of frames per multiframe
High density mode
Octets per frame
Control bit
0
Configurable on the AD9675
0
4, 8, 16, or 32 (dependent on L = 4, 2, or 1, respectively)
0
C
T
Tail bit
Available on the AD9675
SCR
FCHK
Scrambler enable/disable
Checksum for the JESD204B parameters
Configurable on the AD9675
Automatically calculated and stored in the register map
Rev. A | Page 29 of 60
AD9675
Data Sheet
TRANSPORT
LAYER
DATA LINK
LAYER
PHYSICAL
LAYER
LANE
SAMPLES
FROM CHANNEL
SAMPLE
CONSTRUCTION
FRAME
CONSTRUCTION
8-BIT/10-BIT
ENCODER
ALIGNMENT
CHARACTER
GENERATION
SERIALIZER
OUTPUT
SCRAMBLER
Figure 45. AD9675 Transmit Link Simplified Block Diagram
Figure 45 shows a simplified block diagram of the AD9675
JESD204B link. By default, the AD9675 is configured to use
eight channels and four lanes. Channel A and Channel B data is
output to SERDOUT1 , Channel C and Channel D data is
output to SERDOUT2 , Channel E and Channel F data is
output to SERDOUT3 , and Channel G and Channel H data is
output to SERDOUT4 . The AD9675 allows other configura-
tions such as combining the outputs of the eight channels onto a
single lane.
Refer to JEDEC Standard JESD204B (July 2011) for additional
information about the JESD204B interface. Section 5.1
describes the transport layer and data format details, and
Section 5.2 describes scrambling and descrambling.
JEꢀD204B,ꢀSychroyizatioy,Details,
The AD9675 is a JESD204B Subclass 0 device and establishes
synchronization of the link through three control signals,
SYNCINB, TX_TRIG, optionally SYSREF, and typically a
common device clock. SYNCINB, TX_TRIG, and SYSREF are
assumed to be common to all converter devices for alignment
purposes at the system level.
By default in the AD9675, the 14-bit converter word from each
converter is broken into two octets (eight bits of data). Bit 0
(MSB) through Bit 7 are in the first octet. The second octet
contains Bit 8 through Bit 13 (LSB) and two tail bits. The tail
bits can be configured as zeros or a pseudorandom number
sequence.
The synchronization process is accomplished over three phases:
code group synchronization (CGS) phase, initial lane alignment
sequence (ILAS) phase, and data transmission phase. Note that
if scrambling is enabled, the bits are not actually scrambled
until the data transmission phase. The CGS and ILAS phases do
not use scrambling.
The two resulting octets can be scrambled. Scrambling is optional
but is available to avoid spectral peaks when transmitting similar
digital data patterns. The scrambler uses a self synchronizing
polynomial-based algorithm defined by the equation: 1 + x14 + x15.
The descrambler in the receiver must be a self synchronizing
version of the scrambler polynomial.
CGS Phase
In this phase, the JESD204B transmit block transmits /K28.5/
characters in response to a synchronization request from the
receiver (SYNCINB signal asserted). The receiver (external
logic device) must locate K28.5 characters in its input data
stream using clock and data recovery (CDR) techniques.
The two octets are then encoded with an 8-bit/10-bit encoder. The
8-bit/10-bit encoder works by taking eight bits of data (an octet)
and encoding them into a 10-bit symbol. Figure 46 shows how
the 14-bit data is taken from the ADC, the tail bits are added, the
two octets are scrambled, and how the octets are encoded into
two 10-bit symbols. Figure 46 illustrates the default data format.
After a certain number of consecutive K28.5 characters are
detected on all link lanes, the receiver can optionally initiate a
SYS_REF edge so that the AD9675 transmit data establishes a
local multiframe clock (LMFC) internally. The AD9675 is a
subclass 0 device that does not mandate SYS_REF for multi-
device synchronization. The use of SYS_REF reduces the
latency variation between devices and reduce the absolute
latency of each device to some extent. However, SYS_REF does
not meet the full requirements of a JESD204B subclass 1 device,
and the primary synchronization tool on the AD9675 is to use
the global TX_TRIG signal that embed a START_CODE into
the data stream simultaneously for all devices.
At the data link layer, in addition to the 8-bit/10-bit encoding,
the character replacement allows the receiver to monitor frame
alignment. The character replacement process occurs on the
frame and multiframe boundaries, and implementation depends
on which boundary is occurring and if scrambling is enabled.
If scrambling is disabled, the following applies. If the last
scrambled octet of the last frame of the multiframe equals the
last octet of the previous frame, the transmitter replaces the last
octet with the control character /A/ = /K28.3/. On other frames
within the multiframe, if the last octet in the frame equals the
last octet of the previous frame, the transmitter replaces the last
octet with the control character /F/ = /K28.7/.
After synchronizing all lanes, the receiver or logic device
deasserts the SYNCINB signal (SYNCINB goes high), and the
transmitter block begins the ILAS phase, if enabled, on the next
internal LMFC boundary.
If scrambling is enabled, the following applies. If the last octet of
the last frame of the multiframe equals 0x7C, the transmitter
replaces the last octet with the control character /A/ = /K28.3/.
On other frames within the multiframe, if the last octet equals
0xFC, the transmitter replaces the last octet with the control
character /F/ = /K28.7/.
ILAS Phase
In the ILAS phase, the transmitter sends out a known pattern
and the receiver aligns all lanes of the link and verifies the
parameters of the link.
Rev. A | Page 30 of 60
Data Sheet
AD9675
The ILAS phase begins after SYNCINB is deasserted (goes
high). The transmit block begins to transmit four multiframes.
Dummy samples are inserted between the required characters
so that full multiframes are transmitted.
Liyk,ꢀetup,Parameters,
The following steps demonstrate how to configure the AD9675
JESD204B interface and the outputs.
1. Disable lanes before changing the configuration
2. Select the converter and lane configuration
3. Configure the tail bits and control bits
4. Set the lane identification values
5. Set the number of frame per multiframe, K
6. Enable scramble, SCR
The four multiframes have the following properties:
Multiframe 1 begins with an /R/ character (K28.0) and
ends with an /A/ character (K28.3).
Multiframe 2 begins with an /R/ character, followed by a /Q/
(K28.4) character and link configuration parameters over
14 configuration octets (see Table 15), and ends with an
/A/ character. Many of the parameter values are of the
notation of the value − 1.
7. Set the lane synchronization options
8. Check FCHK, checksum of JESD204B interface parameters
9. Set additional digital output configuration options
10. Reenable lane(s) after configuration
Multiframe 3 is the same as Multiframe 1.
Multiframe 4 is the same as Multiframe 1.
Disable Lanes
Data Transmission Phase
Before modifying the JESD204B link parameters, disable the
link and hold it in reset. This is accomplished by writing a
Logic 1 to Address 0x142, Bit 0.
By the end of the ILAS phase, data transmission starts.
Initiating a global TX_TRIG signal resets any sampling edges
within the ADC and replaces a sample with the START_CODE
(see Address 0x18B and Address 0x18C in Table 31). Aligning
the data on all lanes based on the START_CODE guarantees the
synchronization across multiple lanes and across multiple
devices.
Converter and Lane Configuration
The JESD204B M parameter (number of converters) is set to 8
(Address 0x153 = 0x07).
The lane configuration is set in Address 0x150, Bits[1:0] such
that 00 = one lane per link, 01 = two lanes per link, or 11 = four
lanes per link. The channel data (A to H) is placed on the
JESD204B lanes according Table 16.
In the data transmission phase, frame alignment is monitored
with control characters. Character replacement is used at the
end of frames. Character replacement in the transmitter occurs
in the following instances:
Table 16. Channel to JESD204B Lane Mapping
L
SERDOUT1
SERDOUT2
SERDOUT3
SERDOUT4
If scrambling is disabled and the last octet of the frame or
multiframe equals the octet value of the previous frame.
If scrambling is enabled and the last octet of the multiframe is
equal to 0x7C, or the last octet of a frame is equal to 0xFC.
1
A, B, C, D, E, F,
G, H
A, B, C, D
A, B
Power-down Power-down Power-down
2
4
Power-down E, F, G, H
C, D E, F
Power-down
G, H
Table 15. 14 Configuration Octets of the ILAS Phase
Configure the Tail Bits and Control Bits
Bit 7
No. (MSB)
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit 0
(LSB)
With N' = 16 and N = 14, two tail bits are available per sample
for transmitting additional information over the JESD204B link.
Tail bits are dummy bits sent over the link to complete the two
octets and do not convey any information about the input signal.
Tail bits can be fixed zeros (default) or pseudorandom numbers
(Address 0x142, Bit 6).
0
DID[7:0]
1
0
0
0
0
0
0
0
0
0
BID[3:0]
LID[4:0]
L[4:0]
2
3
SCR
4
F[7:0]
M[7:0]
5
0
0
0
K[4:0]
Set Lane Identification Values
6
JESD204B allows parameters to identify the device and lane.
These parameters are transmitted during the ILAS phase, and they
are accessible in the internal registers.
7
CS[1:0]
0
0
0
0
N[4:0]
N'[4:0]
S[4:0]
8
0
0
0
0
0
9
There are three identification values: device identification
(DID), bank identification (BID), and lane identification (LID).
DID and BID are device specific; therefore, they can be used for
link identification.
10
11
12
13
HD
CF[4:0]
Reserved, don’t care
Reserved, don’t care
FCHK[7:0]
Rev. A | Page 31 of 60
AD9675
Data Sheet
Table 17. JESD204B Configurable Identification Values
The AD9675 has fixed values of some of the JESD204B interface
parameters, and they are as follows:
DID Value
Register, Bits
0x148, [4:0]
0x149, [4:0]
0x14A, [4:0]
0x14B, [4:0]
0x146, [7:0]
0x147, [3:0]
Value Range
LID (SERDOUT1 )
LID (SERDOUT2 )
LID (SERDOUT3 )
LID (SERDOUT4 )
DID
0 to 31
0 to 31
0 to 31
0 to 31
0 to 255
0 to 15
N' = 16: number of bits per sample is 16. Read only value
from Address 0x155, Bits[3:0] = 15 (N' − 1).
CF = 0: number of control words per frame clock cycle per
converter is 0, in Address 0x157, Bits[4:0].
The AD9675 calculates values for some JESD204B parameters
based on other settings, particularly the quick configuration
register selection. The following read only values are available in
the register map for verification:
BID
Set Number of Frames per Multiframe, K
Per the JESD204B specification, a multiframe is defined as a group
of K successive frames, where K is between 1 and 32, and it
requires that the number of octets be between 17 and 1024. The
K value is set to 32 by default in Register 0x152, Bits[4:0]. Note
that Register 0x152 represents a value of K − 1.
F: octets per frame can be 32, 16, 8, or 4; read the value
(F − 1) from Address 0x151, Bits[4:0]
M: number of converters per link can be 8 or 16; read the
value (M − 1) from Address 0x153, Bits[3:0]
S: samples per converter per frame is 1; read the value
(S − 1) from Address 0x156, Bit 0.
The K value can be changed; however, it must comply with a
few conditions. The AD9675 uses a fixed value for octets per
frame, F. K must also be a multiple of 4 and conform to the
following equation:
Check FCHK, Checksum of JESD204B Interface
Parameters
32 ≥ K ≥ Ceil(17/F)
The JESD204B parameters can be verified through a checksum
value (FCHK) of the JESD204B interface parameters. Each lane
has a FCHK value associated with it. The FCHK value is
transmitted during the ILAS second multiframe and can be
read from the internal registers.
The JESD204B specification also requires that the number of
octets per multiframe (K × F) be between 17 and 1024. The F
value is fixed based on the value of M and L. F can be read from
Address 0x151.
Checksum value is the modulo 256 sum of the parameters listed
as Octet 0 to Octet 10 in Table 18. Checksum is calculated by
adding the parameter fields before they are packed into the octets.
M 2
F
L
Enable Scramble, SCR
The FCHK for the lane configuration for data coming out of
SERDOUT1 can be read from Address 0x15A. Similarly,
FCHK for the lane defined for SERDOUT2 can be read from
Address 0x15B.
Scrambling can be enabled or disabled by setting Address 0x150,
Bit 7. By default, scrambling is enabled. Per the JESD204B
protocol, scrambling is only functional after the lane
synchronization is complete.
Table 18. JESD204B Configuration Table Used in ILAS and
Checksum Calculation
Set Lane Synchronization Options
Most of the synchronization features of the JESD204B interface
are enabled by default for typical applications. In some cases,
these features can be disabled or modified as follows.
Bit 7
No. (MSB)
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit 0
(LSB)
0
DID[7:0]
ILAS enabling is controlled in Address 0x142, Bits[3:2] and is
enabled by default. Optionally, to support some unique
instances of the interfaces (such as NMCDA-SL), the JESD204B
interface can be programmed to either disable the ILAS
sequence or continually repeat the ILAS sequence. Additionally,
the ILAS can be repeated for a fixed count, as programmed in
Address 0x145, Bits[7:0].
1
2
3
4
5
6
7
8
9
10
0
0
0
0
0
0
0
0
0
BID[3:0]
LID[4:0]
SCR
L[4:0]
F[7:0]
M[7:0]
0
0
0
0
0
K[4:0]
CS[1:0]
N[4:0]
N'[4:0]
S[4:0]
0
0
0
0
CF[4:0]
Rev. A | Page 32 of 60
Data Sheet
AD9675
Reenable Lanes After Configuration
Set Additional Digital Output Configuration Options
After modifying the JESD204B link parameters, enable the link,
and then the synchronization process can begin. Enable the link
by writing a Logic 0 to Address 0x142, Bit 0.
The JESD204B outputs are configured by default to produce a
peak differential voltage of 262 mV, which satisfies the JESD204B
specification for a transmit eye mask for an LV-OIF-11G-SR-
based operation target of between 180 mV and 385 mV peak
differential voltage, but other peak differential voltages can be
accommodated. Address 0x015, Bits[6:4] settings allow output
peak voltages. Additional options include the following:
Invert polarity of the serial output data: Address 0x014, Bit 2
Flip (mirror) 10-bit word before output: Address 0x143, Bit 0
Channel data format (offset binary, twos complement,
Gray code): Address 0x014, Bits[1:0]
Options for interpreting the signal on the SYNCINB pin:
Address 0x156, Bit 5
ADC
TEST PATTERN
16-BIT
JESD204B
TEST PATTERN
8-BIT
JESD204B
TEST PATTERN
10-BIT
A0
A1
A2
A3
A4
A5
A6
8-BIT/10-BIT
ENCODER/
OPTIONAL
SCRAMBLER
SERIALIZER
SERDOUTx±
CHARACTER
14
15
1 + x + x
REPLACMENT
CHANNEL
TX_TRIG
A7
A8
A9
A10
A11
A12
A13
E19
. . .
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9
E10 E0
E11 E1
E12 E2
E13 E3
E14 E4
E15 E5
E16 E6
E17 E7
E18 E8
E19 E9
SYNCINB
t
S8 S0
S9 S1
S10 S2
S11 S3
S12 S4
S13 S5
S14 S6
S15 S7
A8 A0
SYSREF
A9 A1
A10 A2
A11 A3
A12 A4
A13 A5
A PATH
A6
T0
T1 A7
Figure 46. AD9675 Digital Processing of JESD204B Lanes
Table 19. AD9675 JESD204B Frame Alignment Monitoring and Correction Replacement Characters
Last Octet in
Multiframe
Scrambling Lane Synchronization
Character to be Replaced
Replacement Character
Off
Off
Off
On
On
On
On
On
Off
On
On
Off
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame equals D28.7
Last octet in frame equals D28.3
Last octet in frame equals D28.7
No
Yes
K28.7
K28.3
Not applicable K28.7
No
Yes
K28.7
K28.3
Not applicable K28.7
Rev. A | Page 33 of 60
AD9675
Data Sheet
Frame,ayd,Laye,Aligymeyt,Moyitoriyg,ayd,Correctioy,
For receivers whose input common mode voltage requirements
match the output common-mode voltage (DRVDD/2) of the
AD9675, a dc-coupled connection can be used. The common
mode of the digital output automatically biases itself to half of
DRVDD (0.9 V for DRVDD = 1.8 V) (see Figure 48).
Frame alignment monitoring and correction is part of the
JESD204B specification. The 14-bit word requires two octets to
transmit all the data. The two octets (MSB and LSB), where
F = 2, make up a frame. During normal operating conditions,
frame alignment is monitored via alignment characters that are
inserted under certain conditions at the end of a frame. Table 19
summarizes the conditions for character insertion along with
the expected characters under the various operation modes. If
lane synchronization is enabled, the replacement character
value depends on whether the octet is at the end of a frame or at
the end of a multiframe.
If there is no far end receiver termination or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches and that the differential output traces be
adjacent and at equal lengths.
Figure 49 to Figure 54 show examples of the digital output
(default) data eye and a time interval error (TIE) jitter histogram.
Based on the operating mode, the receiver can ensure that it is
still synchronized to the frame boundary by correctly receiving
the replacement characters.
SINGLE-ENDED
TERMINATION
V
RXCM
100Ω
DIFFERENTIAL
TRACE PAIR
50Ω
50Ω
Digital,Outputs,ayd, imiyg,
DRVDD
0.1µF
0.1µF
The AD9675 has differential digital outputs that power up by
default. The driver current is derived on chip and sets the
output current at each output equal to a nominal 4 mA. Each
output presents a 100 Ω dynamic internal termination to reduce
unwanted reflections.
SERDOUTx+
RECEIVER
100Ω
SERDOUTx–
V
= Rx V
CM
OUTPUT SWING = 600mV p-p
CM
The AD9675 digital outputs can interface with custom ASICs and
FPGA receivers, providing superior switching performance in
noisy environments. Single point-to-point network topologies are
recommended with a single differential 100 Ω termination resistor
placed as close to the receiver logic as possible.
Figure 47. AC-Coupled Digital Output Termination Example
100Ω
DIFFERENTIAL
TRACE PAIR
DRVDD
SERDOUTx+
For receiver inputs that provide their own common-mode bias,
or whose input common-mode requirements are not within the
bounds of the AD9675 DRVDD supply, use an ac-coupled
connection as shown in Figure 47. Place a 0.1 μF series
capacitor on each output pin and use a 100 Ω differential
termination close to the receiver side. The 100 Ω differential
termination results in a nominal 600 mV p-p differential swing
at the receiver. In the case where the receiver inputs do not
provide their own common mode bias, single-ended 50 Ω
terminations can be used. When single-ended terminations are
used, the termination voltage (VRXCM) must be chosen to match
the input requirements of the receiver.
RECEIVER
100Ω
SERDOUTx–
V
= DRVDD/2
OUTPUT SWING = 600mV p-p
CM
Figure 48. DC-Coupled Digital Output Termination Example
Rev. A | Page 34 of 60
Data Sheet
AD9675
MASK HITS1: EYE DIAGRAM
MASK HITS1: EYE DIAGRAM
400
300
200
100
0
400
300
1
1
–
–
200
100
0
–100
–200
–300
–100
–200
–300
–400
EYE: ALL BITS
OFFSET: 0.0018
ULS: 8000; 993330, TOTAL: 8000; 993330
EYE: ALL BITS
MASK: TEMP_MSK
OFFSET: –0.0018
MASK: TEMP_MSK
ULS: 6000; 493327, TOTAL: 6000; 493327
–400
–400
–200
0
200
400
–200
–100
0
100
200
TIME (ps)
TIME (ps)
Figure 49. Digital Outputs Data Eye, External 100 Ω Terminations at 2.5 Gbps
Figure 52. Digital Outputs Data Eye, External 100 Ω Terminations at 5.0 Gbps
PERIOD1: HISTOGRAM
PERIOD1: HISTOGRAM
4
3500
4
6000
–
–
3000
5000
4000
3000
2000
1000
0
2500
2000
1500
1000
500
0
–15
–10
–5
0
5
10
15
–22.5
–15.0
–7.5
0
7.5
15.0
22.5
TIME (ps)
TIME (ps)
Figure 53. Digital Outputs Histogram, External 100 Ω Terminations
at 5.0 Gbps
Figure 50. Digital Outputs Histogram External 100 Ω Terminations
at 2.5 Gbps
TJ AT BER1: BATHTUB
TJ AT BER1: BATHTUB
1
1
3
3
–
–
–2
–4
–6
–8
–2
–4
–6
–8
1
1
1
1
1
1
1
1
–10
–12
–14
–16
–10
–12
–14
–16
1
1
1
1
1
1
1
1
0.75
0.81
–0.5
0
0.5
–0.5
0
0.5
UIs
UIs
Figure 54. Digital Outputs Bathtub Curve, External 100 Ω Terminations
at 5.0 Gbps
Figure 51. Digital Outputs Bathtub Curve, External 100 Ω Terminations
at 2.5 Gbps
Rev. A | Page 35 of 60
AD9675
Data Sheet
Additional SPI options allow the user to further increase the
output driver voltage swing of all four outputs to drive longer
trace lengths (see Address 0x015 in Table 31). Even though this
produces sharper rise and fall times on the data edges and is less
prone to bit errors, the power dissipation of the DRVDD supply
increases when this option is used. See the Memory Map section
for more details.
patterns are assigned in the user pattern registers (Address 0x019
through Address 0x020). All test mode options except PN
sequence short and PN sequence long can support 8-bit to 14-bit
word lengths to verify data capture to the receiver.
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 − 1 bits, or 511 bits. For a
description of the PN sequence short pattern and how it is
generated, see Section 5.1 of the ITU-T O.150 (05/96) standard.
The only difference from the standard is that the starting value
is a specific value instead of all 1s (see Table 20 for the initial
values).
Preemphasis,
Preemphasis enables the receiver eye diagram mask to be met
in conditions where the interconnect insertion loss is not in
accordance with the JESD204B specification. In conditions
where pre-emphasis is not needed to achieve sufficient signal
integrity for the link, it is best to disable the pre-emphasis to
conserve power. Enabling pre-emphasis on a short link and
increasing the de-emphasis value too high may cause the
receiver eye diagram to fail in cases where it passes with no de-
emphasis. The transmitter eye diagram does not necessarily
pass when pre-emphasis is enabled. Furthermore, using more
pre-emphasis than necessary may increase EMI; therefore,
consider EMI when choosing an insertion loss compensation
strategy. To enable pre-emphasis, write a Logic 1 to
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 − 1 bits, or 8,388,607 bits.
For a description of the PN sequence long pattern and how it is
generated, see Section 5.6 of the ITU-T O.150 (05/96) standard.
The only differences from the standard are that the starting
value is a specific value instead of all 1s and that the AD9675
inverts the bit stream with relation to the ITU-T standard (see
Table 20 for the initial values). The output sample size depends on
the selected bit length.
Table 20. PN Sequence Initial Values
Address 0x015, Bit 1.
Initial
Value
First Three Output Samples
(MSB First, 16-Bit)
There are several methods to select test data patterns on the
JESD204B link, as shown in Figure 55. These methods serve
different purposes in the testing process of establishing the link.
Sequence
PN Sequence Short
PN Sequence Long
0x092
0x003
0x496F, 0xC9A9, 0x980C
0xFF5C, 0x0029, 0xB80A
The processed samples from the ADC can be replaced by nine
digital output test pattern options. The replacement is initiated
through the SPI using Address 0x00D, Bits[3:0]. These options
are useful when validating receiver capture and timing. See
Table 21 for the output test mode bit sequencing options. Some
test patterns have two serial sequential words, which the user
can alternate in various ways, depending on the test pattern
chosen. Note that some patterns may not adhere to the data
format select option. In addition, custom user defined test
See the Memory Map section for information on how to change
these additional digital output timing features through the SPI.
Test patterns are initiated at the input of the scrambler block by
setting Address 0x144, Bits[5:4] = 10 or at the output of the 8-bit/
10-bit encoder by setting Address 0x144, Bits[5:4] = 01. The test
pattern generated is selected in Address 0x144, Bits[3:0], and is
specified in Table 22.
Rev. A | Page 36 of 60
Data Sheet
AD9675
Digital,Output, est,Patterys,
TEST
PATTERNS
TEST
PATTERNS
OUTPUT
SERIALIZER
FRAME
CONSTRUCTION
FRAME/LANE
ALIGNMENT
CHARACTER
GENERATION
8-BIT/10-BIT
ENCODER
SCRAMBLER
PROCESSED
SAMPLE FROM
ADC
SAMPLE
CONSTRUCTION
TEST
PATTERNS
Figure 55. Example of Data Flow Block Diagram
Table 21. Flexible Output Test Modes—Address 0x00D
Output Test
Mode Bit
Sequence
Subject to
Resolution
Select
Digital Output
Word 1
Digital Output
Word 2
Digital Output
Word 3
Digital Output
Word 4
Pattern Name
Off (default)
Midscale short
+Full-scale short
−Full-scale short
0000
0001
0010
0011
0100
Not applicable
Not applicable
Same
Same
Same
01 0101 0101 0101
Not applicable
Same
Same
Same
10 1010 1010 1010
Not applicable
Same
Same
Same
01 0101 0101 0101
Not applicable
10 0000 0000 0000
11 1111 1111 1111
00 0000 0000 0000
10 1010 1010 1010
Yes
Yes
Yes
No
Checkerboard
output
0101
0110
0111
1000
PN sequence
long
PN sequence
short
One-/zero-word
toggle
User input
Not applicable
Not applicable
11 1111 1111 1111
Not applicable
Not applicable
00 0000 0000 0000
Not applicable
Not applicable
11 1111 1111 1111
Not applicable
Not applicable
00 0000 0000 0000
Yes
Yes
No
Address 0x019 and
Address 0x01A
Not applicable
Address 0x01B and Address 0x01D and Address 0x01F and No
Address 0x01C
Not applicable
00 0000 0000 0001
Address 0x01E
Not applicable
00 0000 0000 0000
Address 0x020
Not applicable
00 0000 0000 0001
1001 to 1110 Reserved
1111 Ramp output
No
Yes
00 0000 0000 0000
Table 22. Flexible Output Test Modes—Address 0x144
Output Test
Mode Bit
Sequence
Subject to
Resolution
Select
Digital Output
Word 1
Digital Output
Word 2
Digital Output
Word 3
Digital Output
Word 4
Pattern Name
0000
0001
Off (default)
Alternating
Not applicable
Not applicable
Not applicable
Not applicable
01 0101 0101 0101 No
Not applicable
10 1010 1010 1010 01 0101 0101 0101 10 1010 1010 1010
checkerboard
0010
One-/zero-word
toggle
11 1111 1111 1111 00 0000 0000 0000 11 1111 1111 1111
00 0000 0000 0000 No
0011
0100
PN sequence long Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Yes
Yes
PN sequence
short
Not applicable
0101
0110
Continuous/
repeat user test
pattern
Single user test
pattern
Address 0x019 and Address 0x01B and Address 0x01D and Address 0x01F and No
Address 0x01A Address 0x01C Address 0x01E Address 0x020
Address 0x019 and Address 0x01B and Address 0x01D and Address 0x01F and No
Address 0x01A
Address 0x01C
Address 0x01E
Address 0x020
0111
1000
Ramp output
Modified RPAT
sequence
00 0000 0000 0000 00 0000 0000 0001 00 0000 0000 0000
00 0000 0000 0001 Yes
See JESD204B
specification
See JESD204B
specification
See JESD204B
specification
See JESD204B
specification
Not applicable
1001 to 1111 Reserved
Not applicable
Not applicable
No
Rev. A | Page 37 of 60
AD9675
Data Sheet
ꢀDIO,Piy,
T_ RIG± ,Piys,
The SDIO pin is required to operate the SPI. The SDIO pin has an
internal 30 kΩ pull-down resistor that pulls this pin low and is only
1.8 V tolerant. To drive the SDIO pin from a 3.3 V logic level,
insert a 1 kΩ resistor in series with this pin to limit the current.
The TX_TRIG function has several uses within the AD9675
and is initiated with an external hardware trigger either on
the TX_TRIG pins or by a software trigger by setting
Address 0x10C, Bit 5 to 1. The hardware trigger has the
advantage of guaranteed synchronous triggering of multiple
AD9675 devices in a system. The setup and hold time for each
TX_TRIG hardware input is given in Table 3 as 1 ns. Due to
the asynchronous SPI function, the software trigger cannot
guarantee synchronization of multiple AD9675 devices. If the
TX_TRIG hardware trigger is not used, tie the TX_TRIG pins
in a low logic state.
ꢀCLK,Piy,
The SCLK pin is required to operate the SPI. It has an internal
30 kΩ pull-down resistor that pulls this pin low and is only 1.8 V
tolerant. To drive the SCLK pin from a 3.3 V logic level, insert a
1 kΩ resistor in series with this pin to limit the current.
CꢀB,Piy,
The CSB pin is required to operate the SPI. It has an internal
70 kΩ pull-up resistor that pulls this pin high and is only 1.8 V
tolerant. To drive the CSB pin from a 3.3 V logic level, insert a
1 kΩ resistor in series with this pin to limit the current.
The TX_TRIG function is used to initiate the advanced power
mode (see the Advanced Power Control section), and
synchronize the data serialization in the JESD204B block (see
the JESD204B Overview section).
RBIAꢀ,Piy,
ANALOG TEST TONE GENERATION
To set the internal core bias current of the ADC, place a resistor
nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using a
resistor other than the recommended 10.0 kΩ resistor for RBIAS
degrades the performance of the device. Therefore, use at least a
1% tolerance on this resistor to achieve consistent performance.
The AD9675 can generate analog test tones that the user can
then switch to the input of the LNA of each channel for channel
gain calibration. The test tone amplitude at the LNA output is
dependent on LNA gain, as shown in Table 23.
Table 23. Test Signal Fundamental Amplitude at LNA Output
VREF,Piy,
Address 0x116[3:2], LNA Gain
LNA Gain
17.9 dB
LNA Gain
21.6 dB
A stable and accurate 0.5 V voltage reference is built into the
AD9675. This voltage reference is amplified internally by a factor
of 2, setting VREF to 1.0 V, which results in a full-scale differential
input span of 2.0 V p-p for the ADC. VREF is set internally by
default, but the user can drive the VREF pin externally with a
1.0 V reference to achieve more accuracy. However, the AD9675
does not support ADC full-scale ranges less than 2.0 V p-p.
Analog Test Tones
15.6 dB
00 (default)
80 mV p-p
98 mV p-p
119 mV p-p
01
10
11
160 mV p-p 196 mV p-p 238 mV p-p
320 mV p-p 391 mV p-p 476 mV p-p
Reserved
Reserved
Reserved
Calculate the test signal amplitude at the input to the ADC
given the LNA gain, attenuator control voltage, and the PGA
gain. Table 24 and Table 25 list example calculations.
When applying the decoupling capacitors to the VREF pin, use
ceramic, low equivalent series resistance (ESR) capacitors. Ensure
that these capacitors are near the reference pin and on the same
layer of the PCB as the AD9675. The VREF pin must have both
a 0.1 μF capacitor and a 1 μF capacitor that are connected in
parallel to analog ground. These capacitor values are recommended
for the ADC to properly settle and acquire the next valid sample.
Table 24. Test Signal Fundamental Amplitude at ADC Input,
VGAIN = 0 V, PGA Gain = 21 dB
Address 0x116[3:2],
Analog Test Tones
LNA Gain LNA Gain LNA Gain
15.6 dB
17.9 dB
21.6 dB
00 (default)
−29 dBFS
−23 dBFS
−17 dBFS
Reserved
−28 dBFS
−22 dBFS
−16 dBFS
Reserved
−26 dBFS
−20 dBFS
−14 dBFS
Reserved
01
10
11
GPOx,Piys,
Use the general-purpose output pins, GPO0, GPO1, GPO2, and
GPO3, in a system to provide programmable inputs to other chips
in the system. The value of each pin is set via Address 0x00E to
either Logic 0 or Logic 1 (see Table 31).
Table 25. Test Signal Fundamental Amplitude at ADC Input,
VGAIN = 0 V, PGA Gain = 30 dB
ADDRx,Piys,
Address 0x116[3:2],
Analog Test Tones
LNA Gain LNA Gain LNA Gain
Use the chip address pins to address individual AD9675 devices in
a system. Chip address mode is enabled using Address 0x115,
Bit 5 (see Table 31). If the value written to Bits[4:0] matches the
value on the chip address bit pins (ADDR[4:0]), the device is
selected and any subsequent SPI writes or reads to addresses
indicated as chip registers are written only to that device. If chip
address mode is disabled, write all addresses regardless of the value
on the address pins.
15.6 dB
17.9 dB
21.6 dB
00 (default)
−20 dBFS
−14 dBFS
−8 dBFS
Reserved
−19 dBFS
−13 dBFS
−7 dBFS
Reserved
−17 dBFS
−11 dBFS
−5 dBFS
Reserved
01
10
11
Rev. A | Page 38 of 60
Data Sheet
AD9675
can be asynchronous. If a continuous signal is used for the
CW DOPPLER OPERATION
RESET , it must be at the LO rate. For synchronous RESET ,
the device can be configured to sample the RESET signal with
either the falling or rising edge of the MLO clock, which
makes it easier to align the RESET signal with the opposite
MLO clock edge. Register 0x02E is used to configure the
RESET signal behavior. Synchronize the RESET input to the
MLO signal input. Achieve accurate channel-to-channel phase
matching via a common clock on the RESET input when using
more than one AD9675.
Each channel of the AD9675 includes an I/Q demodulator.
Each demodulator has an individual programmable phase shifter.
The I/Q demodulator is ideal for phased array beamforming
applications in medical ultrasound. Each channel can be
programmed for 16 phase settings/360° (or 22.5°/step), selectable
via the SPI port. The device has a RESET input that is used to
synchronize the LO dividers of each channel. If multiple AD9675
devices are used, a common reset across the array ensures a
synchronized phase for all channels. If the RESET input is not
used, tie each input pin to ground. Internal to the AD9675, the
individual Channel I and Channel Q outputs are current summed.
If multiple AD9675 devices are used, current sum and convert the
I and Q outputs from each AD9675 to a voltage using an external
transimpedance amplifier.
I/Q,Demodulator,ayd,Phase,ꢀhifter,
The I/Q demodulators consist of double-balanced, harmonic
rejection, passive mixers. The RF input signals are converted
into currents by transconductance stages that have a maximum
differential input signal capability of matching the LNA output
full scale. These currents are then presented to the mixers that
convert them to baseband (RF − LO) and 2× RF (RF + LO).
The signals are phase shifted according to the codes that are
programmed into the SPI latch (see Table 26). The phase shift
function is an integral part of the overall circuit. The phase shift
listed in Table 26 is defined as being between the baseband I or
Q channel outputs. As an example, for a common signal applied
to a pair of RF inputs to an AD9675, the baseband outputs are
in phase for matching phase codes. However, if the phase code
for Channel 1 is 0000 and the phase code for Channel 2 is 0001,
Channel 2 leads Channel 1 by 22.5°.
Quadrature,Geyeratioy,
The internal 0° and 90° LO phases are digitally generated by a
divide-by-M logic circuit, where M is 4, 8, or 16. The internal
divider is selected via Address 0x02E, Bits[2:0] (see Table 31). The
divider is dc-coupled and inherently broadband; the maximum
LO frequency is limited only by its switching speed. Ensure that
the duty cycle of the quadrature LO signals is as near 50% as
possible for the 4LO and 8LO modes. The 16LO mode does not
require a 50% duty cycle. Furthermore, the divider is implemented
such that the multiple local oscillator (MLO) signal reclocks the
final flip-flops that generate the internal LO signals and thereby
minimizes noise introduced by the divide circuitry.
Table 26. Phase Select Code for Channel-to-Channel Phase Shift
For optimum performance, the MLO signal input is driven
differentially, as on the AD9675 evaluation board. The common-
mode voltage on each pin is approximately 1.2 V with the
nominal 3 V supply. It is important to ensure that the MLO source
have very low phase noise (jitter), a fast slew rate, and an
adequate input level to obtain optimum performance of the CW
signal chain.
Phase Shift
I/Q Demodulator Phase (Address 0x02D[3:0])
0°
22.5°
45°
67.5°
90°
112.5°
135°
157.5°
180°
202.5°
225°
247.5°
270°
292.5°
315°
0000
0001 (not valid in 4LO mode)
0010
0011 (not valid in 4LO mode)
0100
0101 (not valid in 4LO mode)
0110
0111 (not valid in 4LO mode)
1000
1001 (not valid in 4LO mode)
1010
1011 (not valid in 4LO mode)
1100
1101 (not valid in 4LO mode)
1110
1111 (not valid in 4LO mode)
Beamforming applications require a precise channel-to-channel
phase relationship for coherence among multiple channels. The
RESET input is provided to synchronize the LO divider
circuits in different AD9675 devices when they are used in
arrays. The RESET input is a synchronous edge-triggered
input that resets the dividers to a known state after power is
applied to multiple AD9675 devices. The RESET signal can be
either a continuous signal or a single pulse, and it can be either
synchronized with the MLO clock edge (recommended) or it
337.5°
Rev. A | Page 39 of 60
AD9675
Data Sheet
DIGITAL RF DECIMATOR
The AD9675 contains digital processing capability. Each channel
has two stages of processing that are available: RF decimator and
high-pass filter. For test purposes, the input to the decimator can
serve as a test waveform. Normally, the input is the output of the
ADC. The output of the decimator/filter is sent to the framer/
serializer for output formatting.
write/read address needs to refer to the last register address, not
the first one. For example, writing or reading the first profile
that spans the address space between 0xF00 and 0xF07, and the
SPI port is configured as MSB first, then the referenced address
must be 0xF07 to allow reading or writing the profile 64 bits in
MSB mode. For more information about stream mode, see the
AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
The maximum data rate of the framer/serializer is 65 MSPS.
Therefore, if the sample of the ADC is greater than 65 MSPS,
enable the RF decimator (fixed rate of 2). The ADC resolution
is 14 bits. Saturation of the ADC is determined after the dc offset
calibration to ensure maximum dynamic range.
There is a buffer used to store the current profile data. When
the profile index is written in Register 0x10C, the selected
profile is read from memory and stored in the current profile
buffer. The profile memory is read/written in the SPI clock
domain. Once the SPI writes the profile index value, it takes
four SPI clock cycles to read the profile from RAM and store it
in the current profile buffer. If the SPI is in LSB mode, these
additional SPI clock cycles are provided when the profile index
register is written. If the SPI is in MSB mode, an additional byte
needs to be read or written to update the profile buffer.
VECTOR PROFILE
To minimize the time needed to reconfigure device settings
during operation, the device supports configuration profiles.
The user can store up to 32 profiles in the device. A profile is
selected by a 5-bit index. A profile consists of a 64-bit vector,
as described in Table 27. Each parameter is concatenated to
form the 64-bit profile vector. The profile memory starts at
Register 0xF00 and ends at Register 0xFFF. Write the memory
in either stream or address selected data mode. However, the
user must read the memory using stream mode. When writing
or reading in stream mode while the SPI configuration is set to
MSB first mode (default setting for register 0x000) then the
Updating profile memory does not affect the data in the profile
buffer. The profile index register must be written to cause a
refresh of the current profile data, even if the profile index
register is written with the same value.
RF DECIMATOR
MULTIBAND AAF
DECIMATE BY 2
ADC OUTPUT OR
TEST WAVEFORM
HIGH-PASS
FILTER
FRAMER
SERIALIZER
DC OFFSET
CALIBRATION
Figure 56. Simplified Block Diagram of a Single Channel of RF Decimator
Table 27. Profile Definition
Field
No. of Bits
Description
Reserved
HPF Bypass
32
1
Reserved
Digital high-pass filter bypass
0 = disable (filter enabled)
1 = enable (filter bypassed)
POWER_START
15
ADC clock cycles counted from the TX_TRIG signal assertion when the active channels are powered up
0x0000 = 0 clock cycles
0x0001 = 1 clock cycle
…
0x7FFF = 32,767 clock cycles
Reserved
1
Reserved
POWER_STOP
15
ADC clock cycles counted from the TX_TRIG signal assertion when the active channels are powered down
0x0000 = 0 clock cycles
0x0001 = 1 clock cycle
…
0x7FFF = continuous run mode
Rev. A | Page 40 of 60
Data Sheet
AD9675
2
1
RF DECIMATOR
The input to the RF decimator is either the ADC output data or
a test waveform, as described in the Digital Test Waveforms
section. The test waveforms are enabled per channel using
Address 0x11A (see Table 31).
0
–1
–2
–3
–4
–5
–6
–7
–8
LOW BAND FILTER
HIGH BAND FILTER
DC,Offset,Calibratioy,
The user can reduce dc offset through a manual system
calibration process. Measure the dc offset of every channel in
the system and then set a calibration value using Address 0x110
and Address 0x111. Note that these registers are both chip and
local addresses, meaning that they are accessed using the chip
address and device index. Bypass the dc offset calibration using
Address 0x10F, Bits[2:0].
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
Figure 58. AAF Frequency Response, Zoomed In (Frequency Scale Assumes
fADC = 2 × fDEC = 40 MHz)
Multibayd,AAF,ayd,Decimate,bS,2,
The multiband filter is an FIR filter. It is programmable with low or
high bandwidth filtering. The filter requires 11 input samples to
populate the filter. The decimation rate is fixed at 2×. Therefore,
the decimation frequency is fDEC = fSAMPLE/2. Figure 57 and
Figure 58 show the frequency response of the filter, depending
on the mode. Figure 57 shows the attenuation amplitude over
the Nyquist frequency range. Figure 58 shows the pass band
response as nearly flat.
High-Pass,Filter,
The user can apply a second-order Butterworth high-pass IIR
filter after the RF decimator. The filter has a cutoff of 700 kHz
for an encode clock of 50 MHz. The filter has a settling time of
2.5 μs. Therefore, if the ADC clock is 50 MHz, ignore the first
125 samples (2.5 μs/0.02 μs). Bypass or enable the filter in the
vector profile if the filter is enabled in Register 0x113, Bit 5. If
the filter is bypassed by setting Register 0x113, Bit 5 to 1, the
filter cannot be enabled from the vector profile.
10
0
DIGITAL TEST WAVEFORMS
LOW BAND FILTER
HIGH BAND FILTER
–10
–20
–30
–40
–50
–60
Digital test waveforms can be used in the digital processing block
instead of the ADC output. To enable digital test waveforms,
use Address 0x11B. Enable each channel individually in
Address 0x11A.
Waveform,Geyerator,
For testing and debugging, use a programmable waveform
generator in place of ADC data. The waveform generator can
vary offset, amplitude, and frequency. The generator uses the
ADC sample frequency, fSAMPLE, and ADC full-scale amplitude,
AFULL-SCALE, as references. The values are set in Address 0x117,
Address 0x118, and Address 0x119 (see Table 31).
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
Figure 57. AAF Frequency Response (Frequency Scale Assumes
fADC = 2 × fDEC = 40 MHz)
x = C + A × sin(2 × π × N)
(8)
f
SAMPLE n
N
, see Address 0x117
(9)
64
AFULLSCALE
A
, see Address 0x118
(10)
(11)
2x
C = AFULL-SCALE × a × 2−(13 − b), see Address 0x119
Chayyel,ID,ayd,Ramp,Geyerator,
In Channel ID test mode, the output is a concatenated value.
Bits[6:0] are a ramp. Bit 7 is reserved as 0. Bits[10:8] are the
channel ID such that Channel A is coded as 000 and Channel B
is 001. Bits[15:11] are the chip address.
Rev. A | Page 41 of 60
AD9675
Data Sheet
CHIP IN POWER-DOWN,
DIGITAL BLOCK POWER SAVING SCHEME
STANDBY,
OR CW MODE
To reduce power consumption in the digital block after the
ADC, the RF decimator and filter start in an idle state after
running the chip (Register 0x008, Bits[2:0] = 000). The digital
block only switches to a running state when the negative edge of
the TX_TRIG pulse is detected, or with a software TX_TRIG
write (Register 0x10C, Bit 5 = 1).
RUN CHIP
DIGITAL
DECIMATOR/FILTER
IDLE
TX_TRIG IS HIGH, PROFILE
INDEX WRITE, OR POWER
STOP EXPIRES
NEGATIVE EDGE TX_TRIG
OR S/W TX_TRIG
To put the digital block back into the idle state (while the rest of
the chip is still running) and to save power, enact one of the
following three events: raise the TX_TRIG signal high, write to
the profile index (Register 0x10C, Bits[0:4]), or the power stop
expires if the advanced power control feature is used. Figure 59
illustrates the digital block power saving scheme.
DIGITAL
DECIMATOR/FILTER
RUNNING
Figure 59. Digital Block Power Saving Scheme
Rev. A | Page 42 of 60
Data Sheet
AD9675
SERIAL PORT INTERFACE (SPI)
The AD9675 SPI allows the user to configure the signal chain for
specific functions or operations through the structured register
space provided inside the chip. The SPI offers the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
can be further divided into fields, as documented in the Memory
Map section. For detailed operational information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
communication. Although the device is synchronized during
power-up, exercise caution when using 2-wire mode to ensure
that the serial port remains synchronized with the CSB line.
When operating in 2-wire mode, use a 1-, 2-, or 3-byte transfer
exclusively. Without an active CSB line, streaming mode can be
entered but not exited.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a read-
back operation, performing a readback causes the serial data
input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.
Three pins define the serial port interface: SCLK, SDIO, and CSB
(see Table 28). The SCLK (serial clock) pin is used to synchronize
the read and write data presented to the device. The SDIO (serial
data input/output) pin is a dual-purpose pin that allows data to
be sent to and read from the internal memory map registers of
the device. The CSB (chip select bar) pin is an active low control
that enables or disables the read and write cycles.
The user can send data in MSB first mode or LSB first mode.
MSB first mode is the default at power-up and is changed by
adjusting the configuration register (Address 0x000). For more
information about this and other features, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Table 28. Serial Port Pins
Pin
Function
SCLK
Serial clock. Serial shift clock input. SCLK
synchronizes serial interface reads and writes.
HARDWARE INTERFACE
The pins described in Table 28 constitute the physical interface
between the programming device and the serial port of the
AD9675. The SCLK and CSB pins function as inputs when
using the SPI. The SDIO pin is bidirectional, functioning as an
input during write phases and as an output during readback.
SDIO
Serial data input/output. Dual-purpose pin that
typically serves as an input or an output, depending
on the instruction sent and the relative position in
the timing frame.
Chip select bar (active low). This control gates the
read and write cycles.
CSB
If multiple SDIO pins share a common connection, ensure that
proper VOH levels are met. Figure 60 shows the number of SDIO
pins that can be connected together and the resulting VOH level,
assuming the same load for each AD9675.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing sequence. During the
instruction phase, a 16-bit instruction is transmitted, followed
by one or more data bytes, which is determined by Bit Field W0
and Bit Field W1. An example of the serial timing and its
definitions are shown in Figure 61 and Table 29.
1.800
1.795
1.790
1.785
1.780
1.775
1.770
1.765
1.760
1.755
1.750
1.745
1.740
1.735
1.730
1.725
1.720
1.715
During normal operation, CSB signals to the device that SPI
commands are to be received and processed. When CSB is
brought low, the device processes SCLK and SDIO to execute
instructions. Normally, CSB remains low until the communication
cycle is complete. However, if connected to a slow device, CSB
can be brought high between bytes, allowing older microcontrollers
enough time to transfer data into shift registers. CSB can be
stalled when transferring one, two, or three bytes of data. When
W0 and W1 are set to 11, the device enters streaming mode and
continues to process data, either reading or writing, until CSB is
taken high to end the communication cycle. This mode allows
complete memory transfers without the need for additional
instructions. Regardless of the mode, if CSB is taken high in the
middle of a byte transfer, the SPI state machine is reset, and the
device waits for a new instruction.
0
10
20
30
40
50
60
70
80
90
100
NUMBER OF SDIO PINS CONNECTED TOGETHER
Figure 60. SDIO Pin Loading
This interface is flexible enough to be controlled either by serial
programmable read-only memories (PROMs) or by PIC
microcontrollers, which provide the user with an alternative to a
full SPI controller for programming the device (see the AN-812
Application Note, Microcontroller-Based Serial Port Interface
(SPI®) Boot Circuit).
The SPI port can be configured to operate in different manners.
CSB can also be tied low to enable 2-wire mode. When CSB is
tied low, SCLK and SDIO are the only pins required for
Rev. A | Page 43 of 60
AD9675
Data Sheet
tDS
tHIGH
tCLK
tH
tS
tDH
tLOW
CSB
DON’T
SCLK
DON’T
CARE
CARE
DON’T
CARE
DON’T
CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
SDIO
D5
D4
D3
D2
D1
D0
Figure 61. Serial Timing Details
Table 29. Serial Timing Definitions
Parameter
Timing (ns min)
Description
tDS
tDH
tCLK
tS
12.5
5
40
5
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
tH
2
Hold time between CSB and SCLK
tHIGH
tLOW
tEN_SDIO
16
16
15
Minimum period that SCLK must be in a logic high state
Minimum period that SCLK must be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling
edge (not shown in Figure 61)
tDIS_SDIO
15
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 61)
Rev. A | Page 44 of 60
Data Sheet
AD9675
MEMORY MAP
Reserved,Locatioys,
READING THE MEMORY MAP TABLE
Do not write to undefined memory locations except when
writing the default values suggested in this data sheet. Addresses
that have values marked as 0 must be considered reserved and
have a 0 written into their registers during power-up.
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into two sections: the chip
configuration register map (Address 0x000 to Address 0x19E)
and the profile register map (Address 0xF00 to Address 0xFFF).
Registers that are designated as local registers use the device
index in Address 0x004 and Address 0x005 to determine to
which channels of a device the command is applied. Registers
that are designated as chip registers use the chip address mode
in Address 0x115 to determine whether the device is to be
updated by writing to the chip register.
Default,Values,
After a reset, critical registers are automatically loaded with default
values. These values are indicated in Table 31, where an X refers
to an undefined feature (don’t care).
Logic,Levels,
An explanation of various registers follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “bit is cleared” is synonymous with “bit is set
to Logic 0” or “writing Logic 0 for the bit.”
The first column of the memory map indicates the register
address, and the default value is shown in the second rightmost
column. The Bit 7 (MSB) column is the start of the default
hexadecimal value given. For example, Address 0x011, the LNA
and VGA gain adjustment register, has a default value of 0x06,
meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,
Bit 2 = 1, Bit 1 = 1, and Bit 0 = 0, or 0000 0110 in binary. This
setting is the default for GAIN pins enabled, PGA gain = 24 dB,
and LNA gain = 21.6 dB.
RECOMMENDED START-UP SEQUENCE
To save system power during programming, the AD9675 powers
up in power-down mode. To start the device up and initialize
the data interface, the SPI commands listed in Table 30 are
recommended. At a minimum, write the profile memory for an
index of 0 (Address 0xF00 to Address 0xF07; see Table 27). If
additional profiles and coefficient memory are required, write
these profiles and coefficient memory blocks after Profile File
Memory 0.
For more information about the SPI memory map and other
functions, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
Rev. A | Page 45 of 60
AD9675
Data Sheet
Table 30. AD9675 SPI Write Start-Up Sequence Example
Address
0x000
0x002
0x0FF
0x004
0x005
0x113
0x011
0xF00
0xF01
0xF02
0xF03
0x10C1
0x014
0x008
0x021
0x199
0x142
0x188
0x18B
0x18C
0x150
0x182
0x181
0x186
Value
Description
0x3C
0x0X (default)
0x01
0x0F
0x3F
0x00
0x06 (default)
0xFF
0x7F
0x00
0x80
0x00 (default)
0x00
0x00
0x12
0x80
0x04
0x01
0x27
Initiate SPI reset
Set speed mode to 40 MSPS
Enable speed mode change
Set local registers to all channels
Set local registers to all channels
Bypass RF decimator, enable high-pass filter
Set LNA gain= 21.6 dB, GAIN pins enabled, and PGA gain = 24 dB
Continuous run mode enable; do not power down channels (POWER_STOP LSB)
Continuous run mode enable; do not power down channels (POWER_STOP MSB)
Power up all channels 0 clock cycles after TX_TRIG signal assertion (POWER_START LSB)
Digital high-pass bypassed (POWER_START MSB)
Set index profile (required after profile memory writes)
Set output data format
Chip run (TGC mode)2
16-bit, four-lane mode
Enables automatic serializer/deserializer (SERDES) sample clock counter
ILAS enabled
Enable start code identifier
Set start code MSB
Set start code LSB
JESD204B scrambler disabled and four-lane configuration (L = 4)
Automatically configures PLL
PLL N-divider = ÷20
0x72
0x03
0x82
0x02
0xAA
Disable continuous data resync (continuous data resync is not recommended during real-time
scanning; one time data resync is sufficient)
0x10C3
0x00F
0x02B
0x20
0x18
0x40
Set SPI TX_TRIG and index profile
Set low-pass filter cutoff frequency, bandwidth mode
Set analog LPF and HPF to defaults, tune filters4
1 Setting the profile index requires an additional SPI write in SPI MSB mode before the chip is run to complete the current profile buffer update.
2 Running the chip from full power-down mode requires 375 μs wake up time as listed in Table 3.
3 Soft TX_TRIG switches the RF decimator and filter to a running state. The soft TX_TRIG may not be needed if a hardware TX_TRIG signal is used to run the digital block.
4 Tuning the filters requires 512 ADC clock cycles.
Rev. A | Page 46 of 60
Data Sheet
AD9675
MEMORY MAP REGISTER TABLE
Table 31. AD9675 Memory Map Registers
Addr.
(Hex)
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
Chip Configuration Registers
0x000 CHIP_
PORT_
0
LSB first
0 = off
(default)
SPI reset
0 = off
(default)
1
1
SPI reset
0 = off
(default)
LSB first
0 = off
(default)
0
0x18
Nibbles
mirrored so
that LSB or
MSB first
mode is set
correctly
CONFIG
1 = on
1 = on
1 = on
1 = on
regardless of
shift mode.
SPI reset
reverts all
registers
(including
the JESD
ones), except
Reg. 0x000 to
their default
values and
0x000[2, 5]
bits are
automatically
cleared.
0x001 CHIP_
ID
Chip ID Bits[7:0]
AD9675 = 0xA9 (default)
0xA9
0x0X
Default is
unique chip
ID, different
for each
device; read
only register
0x002 CHIP_
GRADE
X
X
Speed mode
(identify device
X
X
X
X
Speed mode
used to diff-
erentiate
ADC speed
power modes
(must update
Reg. 0x0FF to
initiate mode
setting)
variants of chip ID)
00: Mode I
(40 MSPS) (default)
01: Mode II (65 MSPS)
10: Mode III (80 MSPS)
11: Mode III (125 MSPS)
Device Index and Update Registers
0x004 DEVICE_
INDEX_2
X
X
X
X
X
Data
Channel H
0 = off
1 = on
(default)
Data
Channel
G
0 = off
1 = on
(default)
Data
Data
0x0F
0x3F
Bits are set to
determine
which on-
chip device
receives the
next write
Channel F Channel E
0 = off
1 = on
(default)
0 = off
1 = on
(default)
command.
0x005 DEVICE_
INDEX_1
X
1
1
Data
Channel D
0 = off
1 = on
(default)
Data
Data
Data
Bits are set to
determine
which on-
chip device
receives the
next write
Channel C Channel B Channel A
0 = off
1 = on
(default)
0 = off
1 = on
(default)
0 = off
1 = on
(default)
command.
Rev. A | Page 47 of 60
AD9675
Data Sheet
Addr.
(Hex)
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x0FF
DEVICE_
UPDATE
X
X
X
X
X
X
X
Update
speed
0x00
A write to
Reg 0xFF
mode
(value does
not matter)
resets all
default reg-
ister values
(analog and
ADC registers
only, not JESD
registers,
0 = off
(default)
1 = on
Reg 0x00 or
Reg 0x02[4:5])
if Reg 0x02
was prev-
iously written
since the last
reset/load of
defaults.
Program Function Registers
0x008 GLOBAL_
MODES
X
LNA input
impe-
dance
0 = 6 kΩ
(default)
1= 3 kΩ
X
X
X
0
X
X
0
X
X
Internal power-down mode
000 = chip run (TGC mode)
001 = full power-down (default)
010 = standby
011 = reset all JESD registers
100 = CW mode (TGC power-down)
0x01
0x01
0x00
Determines
generic
modes of
chip
operation
(global)
0x009 GLOBAL_
CLOCK
X
X
X
X
X
DCS
Turns the
internal duty
cycle
stabilizer
(DCS) on and
off (global)
0 = off
1 = on
(default)
0x00A PLL_
STATUS
PLL lock
status
0 = not
locked
1 =
X
X
JESD204B
link ready
status
Monitor PLL
lock and link
ready status
(read only,
global)
0 = link not
ready
(default)
locked
1 = link
ready, PLL
locked
0x00D TEST_IO
User test
mode
0 = con-
tinuous,
repeat
X
Reset PN
long gen
0 = on, PN
long
running
(default)
1 = off, PN
long held
in reset
Reset PN
short
gen
Output test mode
0000 = off (default)
0001 = midscale short
0010 = +FS short
0x00
When this
register is
set, the test
data is
placed on
the output
pins in place
of normal
data (local)
0 = on,
PN short
running
(default)
1 = off,
PN short
held in
reset
0011 = −FS short
user
0100 = checkerboard output
0101 = PN sequence long
0110 = PN sequence short
0111 = one-/zero-word toggle
1000 = user input
patterns
(1, 2, 3, 4, 1,
2, 3, 4, …)
(default)
1 = single
clock
1001 to 1110 = reserved
1111 = ramp output
cycle user
patterns,
then zeros
(1, 2, 3, 4,
0, 0, …)
0x00E GPO
X
X
X
X
General-purpose digital outputs
0x00
Values
placed on
GPO0 to
GPO3 pins
(global)
Rev. A | Page 48 of 60
Data Sheet
AD9675
Addr.
(Hex)
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x00F FLEX_
CHANNEL_
Filter cutoff frequency control
0 0000 = 1.45 × (1/3) × fSAMPLE
0 0001 = 1.25 × (1/3) × fSAMPLE
0 0010 = 1.13 × (1/3) × fSAMPLE
0 0011 = 1.0 × (1/3) × fSAMPLE (default)
0 0100 = 0.9 × (1/3) × fSAMPLE
0 0101 = 0.8 × (1/3) × fSAMPLE
0 0110 = 0.75 × (1/3) × fSAMPLE
0 0111 = N/A
BW mode
0 = low
X
X
0x18
Antialiasing
filter cutoff
(global)
INPUT
(default,
8 MHz to
18 MHz)
1 = high
(13.5 MHz
to 30 MHz)
0 1000 = 1.45 × (1/4.5) × fSAMPLE
0 1001 = 1.25 × (1/4.5) × fSAMPLE
0 1010 = 1.13 × (1/4.5) × fSAMPLE
0 1011 = 1.0 × (1/4.5) × fSAMPLE
0 1100 = 0.9 × (1/4.5) × fSAMPLE
0 1101 = 0.8 × (1/4.5) × fSAMPLE
0 1110 = 0.75 × (1/4.5) × fSAMPLE
0 1111 = N/A
1 0000 = 1.45 × (1/6) × fSAMPLE
1 0001 = 1.25 × (1/6) × fSAMPLE
1 0010 = 1.13 × (1/6) × fSAMPLE
1 0011 = 1.0 × (1/6) × fSAMPLE
1 0100 = 0.9 × (1/6) × fSAMPLE
1 0101 = 0.8 × (1/6) × fSAMPLE
1 0110 = 0.75 × (1/6) × fSAMPLE
1 0111 = N/A
0x010 FLEX_
OFFSET
X
X
1
0
0
0
0
0
LNA gain
00 = 15.6 dB
01 = 17.9 dB
10 = 21.6 dB
(default)
0x20
0x06
Reserved
0x011 FLEX_
GAIN
Digital VGA gain control
0000 = GAIN pins enabled (default)
0001 = 0.0 dB (max gain, GAIN pins disabled)
PGA gain
00 = 21 dB
01 = 24 dB (default)
10 = 27 dB
LNA and
PGA gain
adjustment
(global)
0010 = −3.5 dB
0011 = −7.0 dB
…
11 = 30 dB
11 = reserved
1110 = −45 dB
1111 = reserved (do not use)
0x012 BIAS_
CURRENT
X
X
X
X
0
1
PGA bias
0 =100%
(default)
1 = 60%
LNA bias
00 = high
01 = midhigh (default)
10 = midlow
0x09
LNA bias
current
adjustment
(global)
11 = low
0x013 RESERVED_
13
0
0
0
0
0
0
0
0x00
0x01
Reserved
0x014 OUTPUT_
MODE
X
X
X
Output
data
enable
X
Output
data
invert
Output data format
00 = offset binary
01 = twos complement
(default)
Data output
modes
(local)
0 =
0 =
enable
(default)
1 =
disable
(default)
1 =
10 = gray code
11 = reserved
disable
enable
0x015 OUTPUT_
ADJUST
X
CML output drive level adjustment
000 = reserved
X
X
Output
pre-
emphasis
0 = off
(default)
1 = on
1
0x61
Data output
levels
(global)
001 = reserved
010 = 368 mV
011 = reserved
100 = 293 mV
101 = 286 mV
110 = 262 mV (default)
111 = 238 mV
Rev. A | Page 49 of 60
AD9675
Data Sheet
Addr.
(Hex)
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x016 RESERVED_
16
X
X
X
X
X
X
X
X
0x00
0x017 RESERVED_
17
X
X
X
X
X
X
X
X
0x00
0x04
0x00
0x018 FLEX_
VREF
X
X
X
X
X
1
0
0
Reserved
(global)
0x019 USER_
PATT1_
B7
B6
B5
B4
B3
B2
B1
B0
User-Defined
Pattern 1,
LSB
LSB (global)
0x01A USER_
PATT1_
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B9
B1
B9
B1
B9
B1
B9
B8
B0
B8
B0
B8
B0
B8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
User-Defined
Pattern 1,
MSB (global)
MSB
0x01B USER_
PATT2_
User-Defined
Pattern 2,
LSB (global)
LSB
0x01C USER_
PATT2_
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
User-Defined
Pattern 2,
MSB (global)
MSB
0x01D USER_
PATT3_
User-Defined
Pattern 3,
LSB (global)
LSB
0x01E USER_
PATT3_
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
User-Defined
Pattern 3,
MSB (global)
MSB
0x01F
USER_
PATT4_
LSB
User-Defined
Pattern 4,
LSB (global)
0x020 USER_
PATT4_
B15
0
B14
X
B13
B12
B11
B10
X
User-Defined
Pattern 4,
MSB (global)
MSB
0x021 FLEX_
SERIAL_
Lane mode
Lane low
rate:
0 = normal
(default)
1 = low
Output word length
00 = 12 bits (default)
01 = 14 bits
Lane setting
control
(global)
00 = reserved (default)
01 = 2 channels/lane
(4 lanes)
10 = 4 channels/lane
(2 lanes)
CTRL
10 = 16 bits
11 = reserved
output rate
(<1 Gbps)
11 = 8 channels/lane
(1 lane)
0x022 SERIAL_
CH_STAT
X
X
X
X
X
X
X
X
X
Channel
power-
down
1 = on
0 = off
0x00
0x00
Used to
power down
individual
channels
(local)
(default)
0x02B FLEX_
FILTER
Enable
automatic
low-pass
tuning
1 = on
(self
X
X
X
Bypass
analog HPF
0 = off
(default)
1 = on
Analog high-pass filter
cutoff
Filter cutoff
(global)
(fLP = low-
pass filter
cutoff
00 = fLP/12.00 (default)
01 = fLP/9.00
10 = fLP/6.00
11 = fLP/3.00
frequency)
clearing)
0x02C LNA_
TERM
X
X
X
X
X
LO-x, LOSW-x
connection
0x00
LNA active
termination/
input
impedance
(global)
00 = RFB1 + 50 Ω (default)
01 = (RFB1||RFB2) + 50 Ω
10 = RFB2 + 50 Ω
11 = ∞
Rev. A | Page 50 of 60
Data Sheet
AD9675
Addr.
(Hex)
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x02D CW_
ENABLE_
X
X
X
CW
I/Q demodulator phase
0000 = 0° (default)
0001 = 22.5° (not valid for 4LO mode)
0010 = 45°
0011 = 67.5° (not valid for 4LO mode)
0100 = 90°
0x00
Phase of
demodu-
lators (local)
Doppler
channel
enable
1 = on
0 = off
PHASE
0101 = 112.5° (not valid for 4LO mode)
0110 = 135°
0111 = 157.5° (not valid for 4LO mode)
1000 = 180°
1001 = 202.5° (not valid for 4LO mode)
1010 = 225°
1011 = 247.5° (not valid for 4LO mode)
1100 = 270°
1101 = 292.5° (not valid for 4LO mode)
1110 = 315°
1111 = 337.5° (not valid for 4LO mode)
0x02E CW_LO_
MODE
Enable
JESD
during CW MLO
0: JESD
link
disabled
during CW nous
(default)
1: JESD
link
RESET
with
Synchro-
nous
RESET
RESET
polarity
0 =
active
high
(default)
1 =
active
low
MLO and
RESET
buffer
enable (in
all modes
except CW
mode)
0 = power-
down
LO mode
00X = 4LO, 3rd to 5th odd harmonic
rejection (default)
0x00
CW mode
functions
(global)
010 = 8LO, 3rd to 5th odd harmonic
rejection
clock edge sampling
MLO
0 =
synchro-
clock edge
0 = falling
(default)
1 = rising
011 = 8LO, 3rd to 13th odd harmonic
rejection
(default)
1 =
asynchro-
nous
100 = 16LO, 3rd to 5th odd harmonic
rejection
(default)
1 = enable
101 = 16LO, 3rd to 13th odd harmonic
rejection
enabled
during CW
(switching
activity
11X = reserved
can de-
grade CW
perfor-
mance)
0x02F
CW_
CW
0
0
0
0
0
0
0
0x80
Global
OUTPUT
output dc
bias
voltage
0 =
bypass
1 =
enable
(default)
0x102 RESERVED_
102
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
X
0
0
0
1
0
0
X
0
0X00
0X00
0x3F
0x00
0x00
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x103 RESERVED_
103
0x104 RESERVED_
104
0x105 RESERVED_
105
0x106 RESERVED_
106
0x107 RESERVED_
107
Read
only
0x108 RESERVED_
108
0x00
Rev. A | Page 51 of 60
AD9675
Data Sheet
Addr.
(Hex)
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x109 VGA_TEST
X
X
X
VGA/
X
VGA/AAF output test mode
000 = Channel A (default)
001 = Channel B
0x00
VGA/AAF
test mode
enables AAF
output to
GPO2/
GPO3 pins
(global)
AAF test
enable
0 = off
(default)
1 = on
010 = Channel C
011 = Channel D
100 = Channel E
101 = Channel F
110 = Channel G
111 = Channel H
0x10C PROFILE_
INDEX
X
X
Manual
TX_TRIG
signal
Profile index[4:0]
0x00
Index for
profile
memory
selects
active
0 = off,
use pin
(default)
1 = on,
profile
(global)
auto-
generate
TX_TRIG
(self-clears)
0x10D RESERVED_
10D
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
1
1
1
0xFF
0xFF
0x00
Reserved
Reserved
0x10E RESERVED_
10E
1
0x10F
DIG_
Digital offset
calibration
status
Digital offset calibration
Control
OFFSET_
CAL
digital offset
calibration
enable and
number of
samples used
(global)
000 = disable correction, reset correction
value (default)
001 = average 210 samples
010 = average 211 samples
…
0 = not
complete
(default)
1 =
111 = average 216 samples
complete
0x110 DIG_
OFFSET_
CORR1
0x111 DIG_
D7
D6
D5
D4
D3
D2
D1
D0
D8
0x00
0x00
Offset
correction
LSB (local)
D15
D14
D13
D12
D11
D10
D9
Offset
correction
MSB (local)
OFFSET_
CORR2
Digital offset calibration (read back if autocalibration enabled with Register 0x10F.
Otherwise, force correction value.)
Offset correction = [D15:D0] × full scale/216
0111 1111 1111 1111 (215 − 1) = +1/2 full scale − 1/216 full scale
0111 1111 1111 1110 (215 – 2) = +1/2 full scale − 2/216 full scale
…
0000 0000 0000 0001 (+1) = +1/216 full scale
0000 0000 0000 0000 = no correction (default)
1111 1111 1111 1111 (−1) = −1/216 full scale
…
1000 0000 0000 0000 (−215) = −1/2 full scale
0x112 POWER_
MASK_
X
X
X
X
X
Power-up setup time (POWER_SETUP)
0 0000 = 0
0x02
0x00
POWER_
SETUP time
is used to
set the
power-up
time (global)
CONFIG
0 0001 = 1 × 40/fSAMPLE
0 0010 = 2 × 40/fSAMPLE (default)
0 0011 = 3 × 40/fSAMPLE
…
1 1111 = 31 × 40/fSAMPLE
0x113 DIG_
CONFIG
Digital
high-pass
filter
0 = enable
(default)
1 = bypass
X
Decimator and filter
enable
X
X
Enable
stages of the
digital
processing
(global)
00 = RF 2× decimator
bypassed (default)
01 = RF 2× decimator
enabled and low
bandwidth filter
1X = RF 2× decimator
enabled and high
bandwidth filter
Rev. A | Page 52 of 60
Data Sheet
AD9675
Addr.
(Hex)
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x115 CHIP_
ADDR_EN
X
X
Chip
address
mode
0 = disable
(default)
1 = enable
Chip address qualifier
0 0000 (default)
(If read, returns the state of ADDR0 to ADRR4 pins)
0x00
Chip address
mode en-
ables the
addressing of
devices if the
value of chip
address
qualifier
equals the
state on the
address pins,
ADDRx
(global)
0x116 ANALOG_
TEST_
X
X
X
X
Analog test tone
amplitude
Analog test tone
frequency
0x00
Analog test
tone
TONE
amplitude
and
frequency
(global)
See Table 23 to
Table 25
00 = fSAMPLE/4 (default)
01 = fSAMPLE/8
10 = fSAMPLE/16
11 = fSAMPLE/32
0x117 DIG_
SINE_
X
X
X
X
X
X
Digital test tone frequency
0 0000 = 1 × fSAMPLE/64
0 0001 = 2 × fSAMPLE/64
…
0x00
0x00
Digital sine
test tone
frequency
(global)
TEST_
FREQ
1 1111 = 32 × fSAMPLE/64
0x118 DIG_
SINE_
X
Digital test tone amplitude
0000 = AFULL-SCALE (default)
0001 = AFULL-SCALE/2
0010 = AFULL-SCALE/22
…
Digital sine
test tone
amplitude
(global)
TEST_
AMP
1111 = AFULL-SCALE/215
0x119 DIG_
SINE_
Offset multiplier (a)
0 1111 = 15
0 1110 = 14
…
Offset exponent (b)
000 = 0 (default)
001 = 1
0x00
Digital sine
test tone
offset
TEST_
OFFSET
(global)
…
0 0000 = 0 (default)
1 1111 = −1
…
111 = 7
1 0000 = −16
Offset = AFULL-SCALE × a × 2−(13 − b)
Offset range is ~0.5 dB
Maximum positive offset = 15 × 2−(13 − 7) = 0.25 × AFULL-SCALE
Maximum negative offset = −16 × 2−(13 − 7) ≈ −0.25 × AFULL-SCALE
0x11A TEST_
MODE_
Ch H
Ch G
Ch F
Ch E
Ch D
Ch C
Ch B
Ch A
0x00
0x00
Enable
enable
0 = off
(default)
1 = on
enable
0 = off
(default)
1 = on
enable
0 = off
(default)
1 = on
enable
0 = off
(default)
1 = on
enable
0 = off
(default)
1 = on
enable
0 = off
(default)
1 = on
enable
0 = off
(default)
1 = on
enable
0 = off
(default)
1 = on
channels for
test mode
(global)
CHENABLE
0x11B TEST_
MODE_
X
X
X
X
X
Data path test mode selection
000 = disable test modes (default)
001 = enable digital sine test mode
010 = reserved
Enable
digital test
modes
CONFIG
(local)
011 = enable channel ID test mode
(16-bit data = digital ramp (7 bits) +
reserved bit (0) + Channel ID (3 bits) +
Chip Address (5 bits)
100 = enable analog test tone
101 = reserved
…
111 = reserved
0x11C RESERVED_
11C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00
0x00
Reserved
Reserved
0x11D RESERVED_
11D
0
Rev. A | Page 53 of 60
AD9675
Data Sheet
Addr.
(Hex)
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x11E RESERVED_
11E
0
0
0
0
0
0
0
0
0
0
0
0
0x00
Reserved
0x11F
RESERVED_
11F
0
0
0
0
0
0
0x00
0x00
Reserved
0x120 CW_
TEST_
CW I/Q
output
swap
LNA offset
cancella-
tion
0 = enable
(default)
1 = disable
LNA offset cancellation
transconductance
00 = 0.5 mS (default)
01 = 1.0 mS
CW analog test tone
override for
Sets the
frequency of
the analog
test tone to
TONE
Address 0x116, Bits [1:0]
00 = disable override
(default)
0 =
fLO in CW
disable
(default)
1 =
10 = 1.5 mS
11 = 2.0 mS
Doppler
mode;
01 = set analog test
tone frequency to fLO
1X = set analog test
tone frequency to dc
enables I/Q
output swap;
LNA offset
cancellation
control
enable
(global)
JESD204B
test mode
enable
0 = disable
(default)
JESD204
B lane
sync
enable
0 =
disable
(default)
1 =
JESD204B
serial
frame
alignment
character
insertion
(FACI)
disable
0: FACI
enabled
1: FACI
Power
down
JESD204B
link
0 = link
enabled
(default)
1 = link
powered
down
0x142 JTX_
LINK_
JESD204B
power
during
standby
0 = remain (default)
powered
up
(default)
1 = power
down
JESD204B
tail bit
value
JESD204B ILAS enable
00 = disable (default)
01 = enable
10 = always on, test
mode
0x00
JESD204B
configuration
(global)
CTRL1
0 = zeros
1 = enable
1 = PN
sequence
11 = reserved
enable
disabled
0x143 JTX_
LINK_
SYNCINB
signal
0
0
8-bit/
10-bit
encoder
0 = enable 0 = not
(default)
1 = bypass
(test mode 1 =
10-bit
transmit
bit invert
10-bit
0x00
JESD204B
configuration
(global)
transmit
bit mirror
0 = not
mirrored
(default)
1 =
CTRL2
polarity
0 = not
inverted
(default)
1 =
inverted
(default)
inverted
only)
inverted
SERD-
OUTx
mirrored
0x144 JTX_
LINK_
Checksum Checksum
JESD204B test pattern
input selection
JESD204B test mode selection
0000 = off (default)
0x00
JESD204B
test mode
and
checksum
controls
(global)
enable
0 =
enable
(default)
1 =
algorithm
0 = add
parameter
(default)
1 = add
packed
CTRL3
0001 = alternating checkerboard
0010 = 1-/0-word toggle
0011 = PN sequence long
0100 = PN sequence short
0101 = continuous/repeat user test pattern
0110 = single user test pattern
0111 = ramp output
00 = reserved (default)
01 = 10-bit test data
injected at output of
8-bit/10-bitencoder
10 = 8-bit test data
injected at input of
scrambler
disable
octets
1000 = RPAT sequence
11 = reserved
1001 = reserved
…
1111 = reserved
0x145 JTX_
LINK_
Initial lane alignment sequence repeat count
0000 0000 = 4 × K + 1 (default)
0000 0001 = 4 × K + 2
0x00
JESD204B
ILAS repeat
count
CTRL4
(global)
…
1111 1111 = 4 × K + 128
0x146 JTX_DID_
CFG
JESD204B serial device identification (DID) number
0x00
0x00
0x00
0x01
Global
Global
Global
Global
0x147 JTX_BID_
CFG
X
X
X
X
X
X
X
X
X
X
JESD204B serial bank identification (BID) number
(extension to DID)
0x148 JTX_LID0_
CFG
Serial lane identification (LID) number for Lane 1
0x149 JTX_LID1_
CFG
Serial lane identification (LID) number for Lane 2
Rev. A | Page 54 of 60
Data Sheet
AD9675
Addr.
(Hex)
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x14A JTX_LID2_
CFG
X
X
0
0
0
0
X
X
Serial lane identification (LID) number for Lane 3
0x02
0x03
0x00
0x00
0x00
0x00
0x83
Global
0x14B JTX_LID3_
CFG
X
0
0
0
0
X
X
0
0
0
0
X
Serial lane identification (LID) number for Lane 4
Global
0x14C RESERVED_
14C
0
0
0
0
X
0
0
0
0
X
0
0
0
0
X
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
0x14D RESERVED_
14D
0x14E RESERVED_
14E
0x14F
RESERVED_
14F
0x150 JTX_SCR_ JESD204B
Lanes per link
00 = one lane (L = 1)
01 = two lanes (L = 2)
10 = reserved
JESD204B
scrambler
and lane
configuration
(global)
L_CFG
serial
scrambler
mode
0 =
disabled
1 =
11 = four lanes (L = 4)
(default)
enabled
(default)
0x151 JTX_F_
CFG
X
X
X
Number of octets per frame (F)
F = (M × 2)/(L)
0 0000 = reserved
…
0 0011 = 4 octets ( M = 8, L = 4, default)
0x03
JESD204B
number of
octets per
frame (read
only, global)
0 0100 = reserved
…
0 0111 = 8 octets (M = 8, L = 2) or (M = 16, L = 4)
0 1000 = reserved
…
0 1111 = 16 octets (M = 8, L = 1) or (M = 16, L = 2)
1 0000 = reserved
…
1 1111 = 32 octets (M = 16, L = 1)
0x152 JTX_K_
CFG
X
X
X
X
X
X
Number of frames per multiframe (K)
0x0F
0x07
JESD204B
frames per
multiframe
(global)
0 0000 = 1
0 0001 = 2
…
1 1111 = 32
0x153 JTX_M_
CFG
X
0
Number of converters per link
JESD204B
number of
converter
per link
(read only,
global)
0000 = reserved
…
0111 = 8 channels, real data (M = 8)
1000 = reserved
…
1111 = 8 channels, quadrature data (M = 16)
0x154 JTX_CS_
N_CFG
X
Control
bits per
sample
0 = none
(CS = 0,
default,
read only)
X
Output resolution (N)
0000 = reserved
…
1011 = 12 bits
1100 = reserved
1101 = 14 bits
0x0F
JESD204B
serializer
number of
bits per
channel
(global)
1110 = reserved
1111 = 16 bits (default)
0x155 JTX_SCV_
NP_CFG
0
0
0
0
Bits per output sample (N')
0000 = reserved
…
0x0F
JESD204B
number of
bits per
samples
(global, read
only)
1110 = reserved
1111 = 16 (default)
Rev. A | Page 55 of 60
AD9675
Data Sheet
Addr.
(Hex)
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x156 JTX_JV_
S_CFG
X
X
Number of
clocks
0
0
0
0
Samples
per
channel
per frame
(S)
0x20
Number of
clocks
SYNCINB
signal must
be low for
synchro-
nization to
begin
SYNCINB
signal must
be low for
synchro-
nization to
begin
0 = 1
sample
(default,
read only)
1 = 2
(global)
0 = 2 frame
clock
cycles
samples
1 = 4 frame
clock
cycles
(default)
0x157 JTX_HD_
CF_CFG
0
0
0
Control words per frame clock per link
0 0000 = 0 (default)
0 0001 = reserved
…
0x00
JESD204B
control
words per
frame
(global,
read only)
1 1111 = reserved
0x158 JTX_RES1_
CFG
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00
0x00
0x3C
Reserved
0x159 JTX_RES2_
CFG
Reserved
0x15A JTX_
CHKSUM0_
CFG
Checksum value for Lane 1 (FCHK)
Checksum value for Lane 2 (FCHK)
Checksum value for Lane 3 (FCHK)
Checksum value for Lane 4 (FCHK)
JESD204B
checksum
value Lane 1
(global,
read only)
0x15B JTX_
CHKSUM1_
CFG
0x3D
0x3E
0x3F
JESD204B
checksum
value Lane 2
(global,
read only)
0x15C JTX_
CHKSUM2_
CFG
JESD204B
checksum
value Lane 3
(global,
read only)
0x15D JTX_
CHKSUM3_
CFG
JESD204B
checksum
value Lane 4
(global,
read only)
0x15E RESERVED_
15E
0
0
0
0
0
1
1
0
0
1
1
1
1
1
0
1
1
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
1
1
0
1
0
1
1
1
1
0
1
1
0
1
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
0
1
1
0x3C
0x3C
0x3C
0x3C
0x00
0xFF
0xFF
0x00
0x0F
0x87
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x15F
RESERVED_
15F
0x160 RESERVED_
160
0x161 RESERVED_
161
0x170 RESERVED_
170
0x171 RESERVED_
171
0x172 RESERVED_
172
0x173 RESERVED_
173
0x174 RESERVED_
174
0x180 JTX_CLK_
CNTL_1
Rev. A | Page 56 of 60
Data Sheet
AD9675
Addr.
(Hex)
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x181 JTX_CLK_
CNTL_2
0
0
0
0
0
PLL N-divider setting (in powers of 2)
000 = divide by 1 (Z = ÷5, default)
001 = divide by 2 (Z = ÷10)
010 = divide by 4 (Z = ÷20)
011 = divide by 8 (Z = ÷40)
100 = divide by 16 (Z = ÷80)
101 = reserved
0x00
PLL
N-divider
setting
(global)
110 = reserved
111 = reserved
0x182 PLL_
STARTUP
PLL auto-
configure
0 =
0
0
0
0
0
1
0
0x02
PLL control
(global)
disable
(default)
1 =
enable
0x183 RESERVED_
183
0
0
1
0
0
0
0
0
1
0
0
0
0
1
1
0
1
0
0x07
0x00
0xAE
Reserved
Reserved
0x184 RESERVED_
184
0
0
0x186 DATA_
VALID_
One time
data resync ous data
Continu-
One time
SYSREF
resync
with JESD
clock after
TX_TRIG
0 = disable (default)
resync
1 = enable
Continuous
SYSREF
resync with
JESD clock
0 = disable
resync
Data and
SYSREF
resync
RESYNC
with JESD
clock after
TX_TRIG
0 = disable
resync
1 = enable
resync
(default)
resync
with JESD
clock
0 = disable
resync
1 = enable
resync
1 = enable resync
resync
(default)
(default)
0x188 START_
CODE_EN
0
0
0
0
0
0
0
Start code
0x01
Enable start
code
identifier
(global)
identifier
0 = disable
1 = enable
(default)
0x189 RESERVED
0x18A RESERVED
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0x00
0x00
0x27
Reserved
Reserved
0x18B START_
CODE_
Start code
MSB (global)
MSB
0x18C START_
CODE_
0
1
1
1
0
0
1
0
0x72
0x10
Start code
LSB (global)
LSB
0x190 FRAME_
X
X
X
Automa-
tically set
frame
size
X
X
X
X
Automati-
cally set
frame size
(global)
SIZE_
MSB
0 =
disable
1 =
enable
(default)
0x191 RESERVED_
191
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00
0x18
0x00
0x1C
0x00
0x18
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x192 RESERVED_
192
0x193 RESERVED_
193
0x194 RESERVED_
194
0x195 RESERVED_
195
0x196 RESERVED_
196
Rev. A | Page 57 of 60
AD9675
Data Sheet
Addr.
(Hex)
Register
Name
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x197 RESERVED_
197
0
0
0
0
0
0
0
0
0
0
0x00
Reserved
0x198 RESERVED_
198
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00
0x00
Reserved
0x199 SAMPLE_
CLOCK_
SERDES
clock
Enables
automatic
SERDES
sample
clock
COUNTER counter
0 = disable
(default)
1 = enable
counter
0x19A RESERVED_
0
0
X
0
1
X
0
1
X
0
1
0
0
X
0
0
X
0
0
0
0
0
0
0x00
0x70
0x10
Reserved
19A
0x19B RESERVED_
19B
Reserved
0x19C JTX_
FRAME_
SIZE
Set
frame
size
automa-
tically
0 =
Automatic-
ally set
JESD204B
frame size
(global)
disable
1 =
enable
(default)
0x19D RESERVED_
19D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00
0x10
Reserved
Reserved
0x19E RESERVED_
19E
1
Profile Memory Registers
0xF00 Profile
32 × 64 bits
0x00
Global
to
Memory
0xFFF
Rev. A | Page 58 of 60
Data Sheet
AD9675
Profile,Iydex,ayd,ꢀoftware, T_ RIG,(Register,0x10C),
MEMORY MAP REGISTER DESCRIPTIONS
The vector profile is selected using the profile index in
Register 0x10C, Bits[4:0]. The software TX_TRIG control in Bit 5
generates a TX_TRIG signal internal to the device. This signal
is asynchronous to the ADC sample clock. Therefore, do not
used this signal to align the data output or to initiate advanced
power mode across multiple devices in the system. The external
pin-driven TX_TRIG control is recommended for systems
that require synchronization of these features across multiple
AD9675 devices.
For more information about the SPI memory map and other
functions, see the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI.
raysfer,(Register,0x0FF),
All registers except Register 0x002 are updated as soon as they
are written. Writing to Register 0x0FF (the value written is don’t
care) initializes and updates the speed mode (Address 0x002)
and resets all other registers to their default values (analog and
ADC registers only, and not JESD204B registers, Register 0x000,
or Register 0x002). Set the speed mode in Register 0x002 and
write to Register 0x0FF at the beginning of the setup of the SPI
writes after the device is powered up to avoid rewriting other
registers after Register 0x0FF is written.
Rev. A | Page 59 of 60
AD9675
Data Sheet
OUTLINE DIMENSIONS
10.10
10.00 SQ
9.90
A1 BALL
CORNER
A1 BALL
CORNER
12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
8.80
BSC SQ
G
H
J
0.80
K
L
M
0.60
REF
TOP VIEW
DETAIL A
BOTTOM VIEW
*
1.40 MAX
0.65 MIN
DETAIL A
0.25 MIN
0.50
0.45
0.40
COPLANARITY
0.20
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT WITH JEDEC STANDARDS MO-275-EEAB-1
WITH EXCEPTION TO PACKAGE HEIGHT.
Figure 62. 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]
(BC-144-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9675KBCZ
AD9671EBZ
Temperature Range
0°C to 85°C
Package Description
Package Option
144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]
Evaluation Board
BC-144-1
1 Z = RoHS Compliant Part.
©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11381-0-1/16(A)
Rev. A | Page 60 of 60
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