AD9707ACPZ [ADI]
IC,D/A CONVERTER,SINGLE,14-BIT,CMOS,LLCC,32PIN;
| 型号： | AD9707ACPZ |
| 厂家： | 
ADI |
| 描述： | IC,D/A CONVERTER,SINGLE,14-BIT,CMOS,LLCC,32PIN 转换器 |
| 文件： | 总27页 (文件大小：803K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Bit, 175 MSPS
TxDAC® D/A Converter
Preliminary Technical Data
AD9707
FEATURES1
FUNCTIONAL BLOCK DIAGRAMS
Low Power Member of Pin Compatible
TxDAC Product Family
Power Dissipation @ 3.3 V:
21 mW @ 10 MSPS
24 mW @ 25 MSPS
30 mW @ 50 MSPS
Sleep Mode: 5 mW @ 3.3 V
Supply Voltage: 1.7 V to 3.6 V
SFDR to Nyquist:
85 dBc @ 5 MHz Output
80 dBc @ 10 MHz Output
75 dBc @ 20 MHz Output
Figure 1. Functional Block Diagram (LFCSP Package)
SNR @ 10 MHz Output, 125 MSPS: TBD dB
Differential Current Outputs: 1 mA to 5 mA
Data Format: Twos Complement or Straight Binary
On-Chip 1.0 V Reference
CMOS Compatible Digital Interface
Edge-Triggered Latches
32-LEAD LFCSP PACKAGE FEATURES
Clock Input: Single-Ended and Differential
Output Common Mode: Adjustable 0 V to 1.2 V
Power-Down Mode: < 400 µW @ 3.3 V (SPI Controllable)
Serial Peripheral Interface (SPI)
Self-calibration
Figure 2. Functional Block Diagram (TSSOP Package)
32-Lead LFCSP Pb-Free Package
28-LEAD TSSOP PACKAGE FEATURES
Internal 500Ω Load Resistor
Internal 16kΩ Resistor to Set Full Scale Current Output
Clock Input: Single-Ended
28-Lead TSSOP Pb-Free Package
1 Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
2005Analog Devices, Inc. All rights reserved.
AD9707
Preliminary Technical Data
provide a complete monolithic DAC solution. The digital inputs
support 1.8 V and 3.3 V CMOS logic families.
GENERAL DESCRIPTION
The AD9707 is a14-bit resolution, low power, fourth generation
member of the TxDAC series of high performance, CMOS
digital-to-analog converters (DACs). The AD970x family,
consisting of 8-, 10-, 12-, and 14-bit DACs, is pin compatible
with the AD974x family of TxDACs and is specifically
optimized for the transmit signal path of communication
systems. All of the devices share the same interface, small
outline package, and pinout, providing an upward or downward
component selection path based on performance, resolution,
and cost. The AD9707 offers exceptional ac and dc performance
while supporting update rates up to 175 MSPS.
PRODUCT HIGHLIGHTS
1. Pin Compatible: The AD970x line of TxDACs is pin
compatible with the AD974x TxDAC line.
2. Low power: Complete CMOS DAC operates on a single
supply of 3.6 V down to 1.7 V, consuming 25mW (3.3V)
and 10mW (1.8 V). The DAC full-scale current can be
reduced for lower power operation, and sleep and
power-down modes are provided for low power idle
periods.
3. Self-Calibration (foreground) enables true 14-bit INL
and DNL performance. (LFCSP only)
The AD9707’s flexible power supply operating range of 1.7 V to
3.6 V and low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to 15 mW with a slight degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 5 mW.
4. Data input supports twos complement or straight binary
data coding.
5. High speed, single-ended and differential (LFCSP only)
CMOS clock input supports 175 MSPS conversion rate.
6. SPI control offers higher level of programmability.
(LFCSP package only)
7. Adjustable output common mode from 0 V to 1.2 V
allows for easy interfacing to other components that
accept common mode levels greater than 0 V (LFCSP
only).
8. On-chip voltage reference: The AD9707 includes a 1.0 V
temperature compensated band gap voltage reference.
9. Industry-standard 28-lead TSSOP and 32-lead LFCSP
packages.
The AD9707-LFCSP has an optional serial peripheral interface
(SPI) which provides a higher level of programmability to
enhance performance of the DAC. An adjustable output
common mode feature has also been added to the AD9707-
LFCSP that allows for easy interfacing to other components that
require common modes greater than 0 V.
Edge-triggered input latches and a 1.0 V temperature
compensated band gap reference have been integrated to
Rev. PrB | Page 2 of 27
Preliminary Technical Data
AD9707
TABLE OF CONTENTS
FEATURES.....................................................................................1
32-LEAD LFCSP PACKAGE FEATURES.................................1
28-LEAD TSSOP PACKAGE FEATURES.................................1
FUNCTIONAL BLOCK DIAGRAMS .......................................1
GENERAL DESCRIPTION.........................................................2
PRODUCT HIGHLIGHTS .........................................................2
AD9707–Specifications ....................................................................4
DC Specifications (3.3 V).............................................................4
Dynamic Specifications (3.3V) ...................................................5
Digital Specifications (3.3V)........................................................6
DC Specifications (1.8V)..............................................................7
Dynamic Specifications (1.8V) ...................................................8
Digital Specifications (1.8V)........................................................9
Absolute Maximum Ratings ..........................................................10
Thermal Characteristics.............................................................10
ESD Caution ................................................................................10
Pin Configuration and Function Descriptions ...........................11
Definitions of Specifications..........................................................12
AD9707–Typical Performance Characteristics...........................13
Functional Description...................................................................16
Serial Peripheral Interface (LFCSP only).................................16
SPI Register Map.........................................................................18
SPI Register Descriptions...........................................................18
Reference Operation...................................................................19
Reference Control Amplifier .....................................................19
DAC Transfer Function..............................................................19
Analog Outputs...........................................................................20
Adjustable Output Common Mode (LFCSP only).................21
Digital Inputs...............................................................................21
Clock Input ..................................................................................21
DAC Timing ................................................................................21
Power Dissipation .......................................................................22
Evaluation Board.............................................................................24
General Description ...................................................................24
Outline Dimensions........................................................................25
Ordering Guide ...............................................................................26
Revision History..............................................................................27
Rev. PrB | Page 3 of 27
AD9707
Preliminary Technical Data
AD9707–SPECIFICATIONS
DC SPECIFICATIONS (3.3 V)
(TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 2 mA, unless otherwise noted.)
Table 1.
Parameter
Min
Typ
Max
Unit
RESOLUTION
14
Bits
DC ACCURACY1
Integral Nonlinearity (INL) Pre-calibration
Integral Nonlinearity (INL) Post-calibration2
Differential Nonlinearity (DNL) Pre-calibration
Differential Nonlinearity (DNL) Post-calibration2
ANALOG OUTPUT
3
0.8
1.5
0.7
LSB
LSB
LSB
LSB
Offset Error
-0.02
+0.02
% of FSR
% of FSR
% of FSR
mA
V
MΩ
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current3
Output Compliance Range
Output Resistance
-0.8
1
-1
-0.2
2
+0.2
5
+1.25
200
5
Output Capacitance
pF
REFERENCE OUTPUT
Reference Voltage
Reference Output Current4
1.0
100
V
nA
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (Ext. Reference)
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
0.1
1.25
V
MΩ
MHz
1
0.5
0
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
TBD
70
80
Supply Voltages
AVDD
DVDD
2.5
2.5
2.5
3.3
3.3
3.3
4.5
1.1
1.7
0.4
20
3.6
3.6
3.6
V
V
V
mA
mA
mA
mA
CLKVDD
Analog Supply Current (IAVDD
Digital Supply Current (IDVDD
Clock Supply Current (ICLKVDD
Supply Current Sleep Mode (IAVDD
Supply Current Power-Down Mode
Power Dissipation5
Power Supply Rejection Ratio—AVDD6
Power Supply Rejection Ratio—DVDD
OPERATING RANGE
)
)
)
5
)
1.0
µA
mW
% of FSR/V
% of FSR/V
°C
24
-1
-0.04
-40
+1
+0.04
+85
6
1 Measured at IOUTA, driving a virtual ground.
2 Calibration offered in LFCSP package only.
3 Nominal full-scale current, IOUTFS, is 32 times the IREF current.
4 An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
5 Measured at fCLOCK = 25 MSPS and fOUT = 2.5 MHz.
6
5% power supply variation.
Rev. PrB | Page 4 of 27
Preliminary Technical Data
AD9707
DYNAMIC SPECIFICATIONS (3.3V)
(TMIN to TMAX , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 2 mA, differential transformer coupled output, 500 Ω terminated,
unless otherwise noted.)
Table 2
Parameter
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK
Output Settling Time (tST) (to 0.1%)1
)
175
MSPS
ns
ns
pV-s
ns
ns
TBD
TBD
TBD
TBD
TBD
45
Output Propagation Delay (tPD
)
Glitch Impulse
Output Rise Time (10% to 90%)
1
Output Fall Time (10% to 90%)
1
Output Noise (IOUTFS = 2 mA)2
Noise Spectral Density2
AC LINEARITY
pA/√Hz
dBc/Hz
-150
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 10 MSPS; fOUT = 1.00 MHz
fCLOCK = 25 MSPS; fOUT = 1.00 MHz
fCLOCK = 65 MSPS; fOUT = 5.00 MHz
fCLOCK = 65 MSPS; fOUT = 10 MHz
fCLOCK = 125 MSPS; fOUT = 15 MHz
fCLOCK = 125 MSPS; fOUT = 25 MHz
fCLOCK = 175 MSPS; fOUT = 20 MHz
fCLOCK = 175 MSPS; fOUT = 40 MHz
Total Harmonic Distortion
82
80
80
80
80
79
78
75
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fCLOCK = 25 MSPS; fOUT = 1.00 MHz
fCLOCK = 50 MSPS; fOUT = 2.00 MHz
fCLOCK = 65 MSPS; fOUT = 2.00 MHz
fCLOCK = 125 MSPS; fOUT = 2.00 MHz
Signal-to-Noise Ratio
-78
-78
-78
-78
dBc
dBc
dBc
dBc
fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 2 mA
fCLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 2 mA
fCLOCK = 175 MSPS; fOUT = 5 MHz; IOUTFS = 2 mA
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
fCLOCK = 78 MSPS; fOUT = 15.0 MHz to 18.2 MHz
0 dBFS Output
82
77
70
dB
dB
dB
TBD
TBD
TBD
TBD
dBc
dBc
dBc
dBc
- 6 Dbfs Output
-12 dBFS Output
-18 dBFS Output
1 Measured single-ended into 500 Ω•load.
2 Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone. Measured single-ended
into a 500 Ω load.
Rev. PrB | Page 5 of 27
AD9707
Preliminary Technical Data
DIGITAL SPECIFICATIONS (3.3V)
(TMIN to TMAX , AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 2 mA, unless otherwise noted.)
Table 3
Parameter
Min
2.1
Typ
Max
Unit
DIGITAL INPUTS1
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
3
0
V
V
0.9
+10
+10
-10
µA
µA
pF
ns
ns
ns
Logic 0 Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW
CLK INPUTS2
5
TBD
TBD
TBD
)
Input Voltage Range
Common-Mode Voltage
Differential Voltage
0
0.75
0.5
3
2.25
V
V
V
1.5
1.5
1 Includes CLOCK pin on TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.
2 Applicable to CLK+ and CLK– inputs when configured for differential clock input mode.
Rev. PrB | Page 6 of 27
Preliminary Technical Data
AD9707
DC SPECIFICATIONS (1.8V)
(TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, IOUTFS = 1 mA, unless otherwise noted.)
Table 4.
Parameter
Min
Typ
Max
Unit
RESOLUTION
14
Bits
DC ACCURACY1
Integral Nonlinearity (INL) Pre-calibration
Integral Nonlinearity (INL) Post-calibration2
Differential Nonlinearity (DNL) Pre-calibration
Differential Nonlinearity (DNL) Post-calibration2
ANALOG OUTPUT
3
0.8
1.5
0.5
LSB
LSB
LSB
LSB
Offset Error
-0.02
-0.5
+0.02
+0.5
+0.6
% of FSR
% of FSR
% of FSR
mA
V
MΩ
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current3
Output Compliance Range
Output Resistance
0.1
1
-0.5
200
5
Output Capacitance
pF
REFERENCE OUTPUT
Reference Voltage
Reference Output Current4
1.0
100
V
nA
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (Ext. Reference)
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
0.1
1.25
V
MΩ
MHz
1
0.5
0
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
70
80
Supply Voltages
AVDD
DVDD
1.7
1.7
1.7
1.8
V
V
V
mA
mA
mA
mA
1.8
1.8
3.1
0.5
0.7
0.3
18
8
CLKVDD
Analog Supply Current (IAVDD
Digital Supply Current (IDVDD
Clock Supply Current (ICLKVDD
Supply Current Sleep Mode (IAVDD
Supply Current Power-Down Mode
Power Dissipation5
Power Supply Rejection Ratio—AVDD6
Power Supply Rejection Ratio—DVDD
OPERATING RANGE
)
)
)
5
)
µA
mW
% of FSR/V
% of FSR/V
°C
-1
-0.04
-40
+1
+0.04
+85
6
1 Measured at IOUTA, driving a virtual ground.
2 Calibration offered in LFCSP package only.
3 Nominal full-scale current, IOUTFS, is 32 times the IREF current.
4 An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
5 Measured at fCLOCK = 25 MSPS and fOUT = 1 MHz.
6
5% power supply variation.
Rev. PrB | Page 7 of 27
AD9707
Preliminary Technical Data
DYNAMIC SPECIFICATIONS (1.8V)
(TMIN to TMAX , AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, IOUTFS = 1 mA, differential transformer coupled output, 500 Ω doubly
terminated, unless otherwise noted.)
Table 5
Parameter
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK
Output Settling Time (tST) (to 0.1%)1
)
80
MSPS
ns
ns
pV-s
ns
ns
TBD
TBD
TBD
TBD
TBD
45
Output Propagation Delay (tPD
)
Glitch Impulse
Output Rise Time (10% to 90%)
1
Output Fall Time (10% to 90%)
1
Output Noise (IOUTFS = 2 mA)2
Noise Spectral Density2
AC LINEARITY
pA/√Hz
dBc/Hz
-150
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 10 MSPS; fOUT = 1.00 MHz
fCLOCK = 25 MSPS; fOUT = 1.00 MHz
fCLOCK = 25 MSPS; fOUT = 5 MHz
fCLOCK = 65 MSPS; fOUT = 10 MHz
fCLOCK = 65 MSPS; fOUT = 15 MHz
fCLOCK = 80 MSPS; fOUT = 15 MHz
fCLOCK = 80 MSPS; fOUT = 30 MHz
Total Harmonic Distortion
79
78
77
76
73
71
63
dBc
dBc
dBc
dBc
dBc
dBc
fCLOCK = 10 MSPS; fOUT = 1.00 MHz
fCLOCK = 25 MSPS; fOUT = 2.00 MHz
fCLOCK = 45 MSPS; fOUT = 2.00 MHz
fCLOCK = 65 MSPS; fOUT = 2.00 MHz
Signal-to-Noise Ratio
-79
-75
-75
-75
dBc
dBc
dBc
dBc
fCLOCK = 25 MSPS; fOUT = 5 MHz; IOUTFS = 1 mA
fCLOCK = 45 MSPS; fOUT = 5 MHz; IOUTFS = 1 mA
fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 1 mA
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
fCLOCK = 40 MSPS; fOUT = 10 MHz to 13.2 MHz
0 dBFS Output
76
74
70
dB
dB
dB
TBD
TBD
TBD
TBD
dBc
dBc
dBc
dBc
- 6 dBFS Output
-12 dBFS Output
-18 dBFS Output
1 Measured single-ended into 500 Ω•load.
2 Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone. Measured single-ended
into 500 Ω load.
Rev. PrB | Page 8 of 27
Preliminary Technical Data
AD9707
DIGITAL SPECIFICATIONS (1.8V)
(TMIN to TMAX , AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, IOUTFS = 1 mA, unless otherwise noted.)
Table 6
Parameter
Min
1.2
Typ
Max
Unit
DIGITAL INPUTS1
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
1.8
0
V
V
0.5
+10
+10
-10
µA
µA
pF
ns
ns
ns
Logic 0 Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW
CLK INPUTS2
5
TBD
TBD
TBD
)
Input Voltage Range
Common-Mode Voltage
Differential Voltage
0
0.4
0.5
1.8
1.3
V
V
V
0.9
1.5
1 Includes CLOCK pin on TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.
2 Applicable to CLK+ and CLK– inputs when configured for differential clock input mode.
Figure 3. Timing Diagram
Rev. PrB | Page 9 of 27
AD9707
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS1
Table 7.
Thermal Resistance
28-Lead TSSOP
θJA = 67.7°C/W
32-Lead LFCSP
θJA = 32.5°C/W
With
Respect to Min
Parameter
Max
Unit
AVDD
ACOM
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-3.9
-3.9
-3.9
-0.3
-0.3
-1.0
-0.3
-0.3
+3.9
V
V
DVDD
DCOM
+3.9
CLKVDD
CLKCOM
DCOM
+3.9
V
ACOM
+0.3
V
1 Thermal impedance measurements were taken on a 4-layer board in still air,
in accordance with EIA/JESD51-7.
ACOM
CLKCOM
CLKCOM
DVDD
+0.3
V
DCOM
+0.3
V
AVDD
+3.9
V
AVDD
CLKVDD
CLKVDD
DCOM
+3.9
V
DVDD
+3.9
V
CLOCK, SLEEP
Digital Inputs, MODE
IOUTA, IOUTB
REFIO, REFLO, FS ADJ
CLK+, CLK–, CMODE
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
DVDD+0.3
DVDD+0.3
AVDD+0.3
AVDD+0.3
CLKVDD+0.3
150
V
DCOM
V
ACOM
V
ACOM
V
CLKCOM
V
°C
°C
°C
-65
+150
300
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 10 of 27
Preliminary Technical Data
AD9707
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
28-Lead TSSOP
32-Lead LFCSP
Figure 4. Pin Configurations (TSSOP and LFCSP packages)
Table 8. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic
Description
1
27
DB13
Most Significant Data Bit (MSB).
Data Bits 12–1.
2–13
28–32, 1, 2, DB12–DB1
4–8
14
15
9
DB0
Least Significant Data Bit (LSB).
25
SLEEP / CSB
Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated if not
used. Must be driven low during SPI operation.
16
17
N/A
23
REFLO
REFIO
Reference Ground when Internal 1.0 V Reference Used. Connect to AVDD to disable internal reference.
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference
output when internal reference activated. Requires 0.1 μF capacitor to ACOM when internal reference
activated.
18
19
24
FS ADJ
RSET
Full-Scale Current Output Adjust.
N/A
Internal 16K Resistor. Connect to pin 18 (FSADJ) to set 2 mA Full-Scale Output Current; it may be left floating
if not used. Refer to page 21 for details.
20
22
20
21
N/A
18
19
17
ACOM
IOUTB
IOUTA
RLOAD
AVDD
OTCM
Analog Common.
21
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Internal 500Ω Termination Resistor. Refer to page 21 for details.
Analog Supply Voltage (1.7 V – 3.6 V).
22
23
24
N/A
N/A
Adjustable Output Common Mode. Refer to page 21 for details.
PIN / SPI/RESET Selects SPI mode or Pin mode operation. Active low for SPI operation. Active high for non-SPI operation.
Pulse high to reset SPI registers to default values.
25
16
15
MODE / SDIO
Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. When SPI is
enabled (LFCSP package only), this pin acts as SPI data input / output.
N/A
CMODE / SCLK
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK–).
Connect to CLKVDD for differential receiver. When SPI is enabled, SPI data clock input.
26
10, 26
3
DCOM
DVDD
CLOCK
CLK+
Digital Common.
27
Digital Supply Voltage (1.7 V – 3.6 V)
Clock Input. Data latched on positive edge of clock.
Differential Clock Input.
28
N/A
12
N/A
N/A
N/A
N/A
13
CLK–
Differential Clock Input.
11
CLKVDD
CLKCOM
Clock Supply Voltage (1.7 V – 3.6 V).
Clock Common.
14
Rev. PrB | Page 11 of 27
AD9707
Preliminary Technical Data
DEFINITIONS OF SPECIFICATIONS
range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C.
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified
bandwidth.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak
spurious signal in the region of a removed tone.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
Figure 5. Basic AC Characterization Test Set-Up (LFCSP Package)
Rev. PrB | Page 12 of 27
Preliminary Technical Data
AD9707
AD9707–TYPICAL PERFORMANCE CHARACTERISTICS
TBD
TBD
Figure 6. SFDR vs. fOUT
Figure 10. SFDR vs. fOUT and IOUTFS @ 65 MSPS
TBD
TBD
Figure 7. SFDR vs. fOUT @ 25 MSPS
Figure 11. Single-Tone SFDR vs. AOUT @ fOUT=fCLOCK/11
TBD
TBD
Figure 8. SFDR vs. fOUT @ 125 MSPS
Figure 12. Single-Tone SFDR vs. AOUT @ fOUT=fCLOCK/5
TBD
TBD
Figure 9. SFDR vs. fOUT @ 175 MSPS
Figure 13. SNR vs. fCLOCK and IOUTFS @ fOUT=5 MHz and 0 dBFS
Rev. PrB | Page 13 of 27
AD9707
Preliminary Technical Data
TBD
TBD
Figure 14. Dual-Tone IMD vs. AOUT @ fOUT=fCLOCK/7
Figure 18. Single-Tone SFDR
TBD
TBD
Figure 15. Typical INL
Figure 19. Dual-Tone SFDR
TBD
Figure 16. Typical DNL
TBD
TBD
Figure 20. Four-Tone SFDR
Figure 17. SFDR vs. Temperature @ 125 MSPS
Rev. PrB | Page 14 of 27
Preliminary Technical Data
AD9707
Figure 21. Simplified Block Diagram (LFCSP Package)
Rev. PrB | Page 15 of 27
AD9707
Preliminary Technical Data
FUNCTIONAL DESCRIPTION
including both the Motorola SPI® and Intel® SSR protocols. The
interface allows read/write access to all registers that configure
the AD9707. Single or multiple byte transfers are supported, as
well as MSB first or LSB first transfer formats. The AD9707’s
serial interface port is configured as a single pin I/O.
Figure 21 shows a simplified block diagram of the AD9707. The
AD9707 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing a nominal full-scale current
(IOUTFS) of 2 mA and a maximum of 5 mA. The array is divided
into 31 equal currents that make up the five most significant
bits (MSBs). The next four bits, or middle bits, consist of 15
equal current sources whose value is 1/16th of an MSB current
source. The remaining LSBs are binary weighted fractions of the
middle bits current sources. Implementing the middle and
lower bits with current sources, instead of an R-2R ladder,
enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >200MΩ).
General Operation of the Serial Interface
There are two phases to a communication cycle with the
AD9707. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9707, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9707 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write, the number of bytes in
the data transfer, and the starting register address for the first
byte of the data transfer. The first eight SCLK rising edges of
each communication cycle are used to write the instruction byte
into the AD9707.
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces
various timing errors and provides matching complementary
drive signals to the inputs of the differential current switches.
A logic high on pin 17 (SPI RES/PIN), followed by a logic low,
will reset the SPI port timing to the initial state of the
instruction cycle. This is true regardless of the present state of
the internal registers or the other signal levels present at the
inputs to the SPI port. If the SPI port is in the midst of an
instruction cycle or a data transfer cycle, none of the present
data will be written.
The analog and digital sections of the AD9707 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 1.7 V to 3.6 V range. The digital section,
which is capable of operating at a rate of up to 175 MSPS,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.0 V band gap
voltage reference, and a reference control amplifier.
The remaining SCLK edges are for Phase 2 of the
communication cycle. Phase 2 is the actual data transfer
between the AD9707 and the system controller. Phase 2 of the
communication cycle is a transfer of 1, 2, 3, or 4 data bytes as
determined by the instruction byte. Using one multibyte
transfer is the preferred method. Single byte data transfers are
useful to reduce CPU overhead when register access requires
one byte only. Registers change immediately upon writing to the
last bit of each transfer byte.
The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 1 mA to 5 mA via an
external resistor, RSET, connected to the full-scale adjust (FS
ADJ) pin. The external resistor, in combination with both the
reference control amplifier and voltage reference VREFIO, sets the
reference current IREF, which is replicated to the segmented
current sources with the proper scaling factor. The full-scale
Instruction Byte
The instruction byte contains the information shown in Table 9.
current, IOUTFS, is 32 times IREF
.
MSB
I7
LSB
I0
The AD9707-LFCSP provides the option of setting the output
common mode to a value other than ACOM via the output
common mode (OTCM) pin. This option allows the user to
directly interface the output of the AD9707 to components that
require common mode levels greater than 0 V.
I6
I5
I4
I3
I2
I1
R/W
N1
N0
A4
A3
A2
A1
A0
Table 9. SPI Instruction Byte
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer will occur after the instruction byte write.
Logic high indicates read operation. Logic 0 indicates a write
operation. N1, N0, Bits 6 and 5 of the instruction byte,
determine the number of bytes to be transferred during the data
transfer cycle. The bit decodes are shown in Table 10.
SERIAL PERIPHERAL INTERFACE (LFCSP ONLY)
The AD9707 serial port is a flexible, synchronous serial
communications port allowing easy interface to many industry
standard microcontrollers and microprocessors. The serial I/O
is compatible with most synchronous transfer formats,
Rev. PrB | Page 16 of 27
Preliminary Technical Data
AD9707
A4, A3, A2, A1, A0, Bits 4, 3, 2, 1, 0 of the instruction byte,
determine which register is accessed during the data transfer
portion of the communications cycle. For multibyte transfers,
this address is the starting byte address. The remaining register
addresses are generated by the AD9707 based on the DATADIR
bit (REG00, bit 6).
the multibyte communication cycle.
The AD9707 serial port controller data address will decrement
from the data address written toward 0x00 for multibyte I/O
operations if the MSB first mode is active. The serial port
controller address will increment from the data address written
toward 0x1F for multibyte I/O operations if the LSB first mode
is active.
N1
N1
Description
0
0
1
1
0
1
0
1
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
Notes on Serial Port Operation
The AD9707 serial port configuration is controlled by REG00,
bit 7. It is important to note that the configuration changes
immediately upon writing to the last bit of the register. For
multibyte transfers, writing to this register may occur during
the middle of communication cycle. Care must be taken to
compensate for this new configuration for the remaining bytes
of the current communication cycle.
Table 10. Byte Transfer Count
Serial Interface Port Pin Descriptions
SCLK—Serial Clock. The serial clock pin is used to
synchronize data to and from the AD9707 and to run the
internal state machines. SCLK’s maximum frequency is 20 MHz.
All data input to the AD9707 is registered on the rising edge of
SCLK. All data is driven out of the AD9707 on the falling edge
of SCLK.
The same considerations apply to setting the software reset,
RESET (REG00, bit 5). All registers are set to their default values
EXCEPT REG00 which remains unchanged.
Use of only single byte transfers when changing serial port
configurations or initiating a software reset is recommended to
prevent unexpected device behavior.
CSB—Chip Select. Active low input starts and gates a
communication cycle. It allows more than one device to be used
on the same serial communications lines. The SDIO pin will go
to a high impedance state when this input is high. Chip select
should stay low during the entire communication cycle.
TBD
SDIO—Serial Data I/O. This pin is used as a bidirectional data
line to transmit and receive data.
Figure 22. Serial Register Interface Timing MSB First
MSB/LSB Transfers
The AD9707 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by register bit DATADIR (REG00, bit
6). The default is MSB first (DATADIR = 0).
TBD
Figure 23. Serial Register Interface Timing LSB First
When DATADIR = 0 (MSB first) the instruction and data bytes
must be written from most significant bit to least significant bit.
Multibyte data transfers in MSB first format start with an
instruction byte that includes the register address of the most
significant data byte. Subsequent data bytes should follow in
order from high address to low address. In MSB first mode, the
serial port internal byte address generator decrements for each
data byte of the multibyte communication cycle.
TBD
Figure 24. Timing Diagram for SPI Register Write
TBD
When DATADIR = 1 (LSB first) the instruction and data bytes
must be written from least significant bit to most significant bit.
Multibyte data transfers in LSB first format start with an
instruction byte that includes the register address of the least
significant data byte followed by multiple data bytes. The serial
port internal byte address generator increments for each byte of
Figure 25. Timing Diagram for SPI Register Read
Rev. PrB | Page 17 of 27
AD9707
Preliminary Technical Data
SPI REGISTER MAP
Table 11
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI CTL
DATA
00
02
0E
0F
10
11
17
SDIODIR
DATAFMT
DATADIR
SWRST
LNGINS
DCLKPOL
CALMEM[0]
PDN
SLEEP
CLKOFF
EXREF
LOWSKEW
DIVSEL[3]
SMEMWR
CLKDIFF
DIVSEL[2]
SMEMRD
CALCLK
DIVSEL[0]
UNCAL
CALMEM
MEMRDWR
MEMADDR
MEMDATA
ANAETST
CALMEM[1]
DIVSEL[1]
CALSTAT
CALEN
MEMADDR[5] MEMADDR[4] MEMADDR[3] MEMADDR[2] MEMADDR[1] MEMADDR[0]
MEMDATA[5] MEMDATA[4] MEMDATA[3] MEMDATA[2] MEMDATA[1] MEMDATA[0]
PRELDS1
CDAOFF
ONE OF
SPI REGISTER DESCRIPTIONS
Table 12
SPI CNTL (00)
SDIODIR
Bit
7
Direction (I/O)
Default
1
Description
1: SDIO pin hardwired for input or output during data transfer (3-wire interface)
0: Serial data uses MSB first format
1: Serial data uses LSB first format
0: Software reset not enabled (running)
1: Default all serial register bits, except address 00h
0: Use 1 byte premable (5 address bits)
1: Use 2 byte preamble (13 adress bits)
1: All analog and digital circuitry off, except serial interface
1: DAC output current off
I
DATADIR
SWRST
LNGINS
6
5
4
I
0
I
I
0
0
PDN
SLEEP
CLKOFF
3
2
1
I
I
I
0
0
0
1: Clock off
0: Internal bandgap reference
1: External reference
EXREF
0
I
0
DATA (02)
DATAFMT
Bit
7
Direction (I/O)
I
Default
0
Description
0: Unsigned binary input data format
1: 2's complement input data format
0: Data latched on DATACLK rising edge
1: Data latched on DATACLK falling edge
0: Low skew mode disabled
1: Low skew mode enabled
0: Single-ended clock input
1: Differential clock input
0: Calibration clock disabled
DCLKPOL
LOWSKEW
CLKDIFF
4
3
2
0
I
I
I
I
0
0
0
0
CALCLK
1: Calibration clock enabled
CALMEM (0E)
Bit
Direction (I/O)
O
Default
00
Description
Calibration Memory
00: Uncalibrated
01: Self calibration
CALMEM[5:4]
[5:4]
11: User input
Calibration clock divide ratio from channel data rate
0000: / 256
0001: / 128
:
DIVSEL[2:0]
[3:0]
I
0000
1110: / 2
1111: / 1
MEMRDWR (0F)
Bit
7
Direction (I/O)
O
Default
0
Description
0: Calibration cycle not complete
1: Calibration cycle complete
CALSTAT
CALEN
SMEMWR
SMEMRD
UNCAL
6
3
2
0
I
I
I
I
0
0
0
0
1: Calibration in progress
1: Write static memory data from external port
1: Read static memory to external port
1: Use uncalibrated
MEMADDR (10)
MEMADDR[5:0]
Bit
[5:0]
Direction (I/O)
I/O
Default
00000
Description
Address of static memory to be accessed
MEMDATA (11)
MEMDATA[5:0]
Bit
[5:0]
Direction (I/O)
I/O
Default
11111
Description
Data for static memory access
ANAETST (17)
Bit
3
Direction (I/O)
I
Default
0
Description
0: Pre-load calibration reference specified by user
1: Pre-load calibration reference of 32
PRELDS1
Rev. PrB | Page 18 of 27
Preliminary Technical Data
AD9707
REFERENCE OPERATION
The AD9707 contains an internal 1.0 V band gap reference. The
internal reference can be disabled in both packages. To disable
the reference in the 32-lead LFCSP package, a logic 1 must be
written to REG00, Bit 0 (EXREF) in the SPI. In the 28-lead
TSSOP package, the reference can be disabled by raising REFLO
to AVDD. In both packages, the reference can also be
overridden by an external reference with no effect on
performance. REFIO serves as either an input or an output
depending on whether the internal or an external reference is
used. Table 13 summarizes the reference operation for the
LFCSP and TSSOP package options.
TBD
Figure 27. External Reference Configuration
REFERENCE CONTROL AMPLIFIER
The AD9707 contains a control amplifier that is used to regulate
the full-scale output current, IOUTFS. The control amplifier is
configured as a V-I converter, as shown in Figure 26, so that its
current output, IREF, is determined by the ratio of the VREFIO and
an external resistor, RSET, as stated in Equation
(4). IREF is copied to the segmented current sources with the
proper scale factor to set IOUTFS, as stated in Equation
Reference REFIO pin
Mode
LFCSP
TSSOP
Internal
Connect 0.1 μF
Capacitor
REG00, Bit 0 = 0
(default)
REFLO = ACOM
REFLO = AVDD
(3).
External
Apply External
Reference
REG00, Bit 0 = 1
The control amplifier allows a 5:1 adjustment span of IOUTFS
from 1 mA to 5 mA by setting IREF between 31.25 µA and 156.25
µA (RSET between 6.4 kΩ and 32 kΩ). The wide adjustment span
of IOUTFS provides several benefits. The first relates directly to the
power dissipation of the AD9707, which is proportional to IOUTFS
(refer to the Power Dissipation section). The second benefit
relates to the ability to adjust the output over a 14 dB range,
which is useful for system gain control purposes.
Table 13. Reference Operation (TSSOP and LFCSP packages)
To use the internal reference, simply decouple the REFIO pin to
ACOM with a 0.1 µF capacitor and enable the internal
reference. To enable the internal reference in the 28-lead TSSOP
package, connect REFLO to ACOM via a resistance less than
5Ω. In the LFCSP package, a logic 0 must be written to REG00,
Bit 0 in the SPI. (Note that this is the default configuration for
the LFCSP package.) The internal reference voltage will be
present at REFIO. If the voltage at REFIO is to be used
anywhere else in the circuit, an external buffer amplifier with an
input bias current of less than 100 nA should be used. An
example of the use of the internal reference is shown in Figure
26.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency small
signal multiplying applications.
DAC TRANSFER FUNCTION
The AD9707 provides complementary current outputs, IOUTA
and IOUTB. IOUTA provides a near fullscale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 16383), while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of
both the input code and IOUTFS and can be expressed as
TBD
IOUTA =
IOUTB =
DAC CODE/16384
×IOUTFS
(1)
(2)
Figure 26. Internal Reference Configuration
An external reference can be applied to REFIO, as shown in
16383− DAC CODE
/16384×IOUTFS
where DAC CODE = 0 to 16383 (i.e., decimal representation).
TBD
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage, VREFIO
and external resistor, RSET. It can be expressed as
,
IOUTFS = 32× IREF
(3)
Figure 27. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 µF
compensation capacitor is not required since the internal
reference is overridden, and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
where
IREF = VREFIO /RSET
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
Rev. PrB | Page 19 of 27
AD9707
Preliminary Technical Data
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. The
single-ended voltage output appearing at the IOUTA and
IOUTB nodes is simply
IOUTB may be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into
complementary single-ended voltage outputs, VOUTA and VOUTB
via a load resistor, RLOAD, as described in the DAC Transfer
Function section by Equations
,
VOUTA = IOUTA× RLOAD
VOUTB = IOUTB ×RLOAD
(5)
(6)
(5) through
(8). The differential voltage, VDIFF, existing between VOUTA and
Note: To achieve the maximum output compliance of 1 V at the
nominal 2 mA output current, RLOAD must be set to 500Ω.
VOUTB, can also be converted to a single-ended voltage via a
transformer or differential amplifier configuration. The ac
performance of the AD9707 is optimum and specified using a
differential transformer-coupled output in which the voltage
swing at IOUTA and IOUTB is limited to 0.5 V.
Also note that the full-scale value of VOUTA and VOUTB should not
exceed the specified output compliance range to maintain
specified distortion and linearity performance
The 28-lead TSSOP package option contains two internal
resistors (RSET = 16 kΩ and RLOAD = 500 Ω) that can be used to
configure the AD9707 with a reduced number of external
resistors. Connecting the RSET pin to the FSADJ pin sets the
full scale output current to 2 mA without the need for an
external RSET resistor. Connecting the RLOAD pin to IOUTA
allows the user to generate a single-ended output driving into a
500 Ω load without the need for an external RLOAD resistor.
The distortion and noise performance of the AD9707 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed
waveform increases and/or its amplitude increases. This is due
to the first order cancellation of various dynamic common-
mode distortion mechanisms, digital feedthrough, and noise.
VDIFF
=
(
IOUTA − IOUTB
)
× RLOAD
(7)
Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be
expressed as
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (assuming no source
termination). Since the output currents of IOUTA and IOUTB
are complementary, they become additive when processed
differentially.
V DIFF
=
{(2× DAC CODE −16383
)
/16384
}
(8)
(32×VREFIO / RSET
)
× RLOAD
Equations
(7) and
As mentioned above, if the AD9707 is being used at its nominal
operating point of 2 mA output current, and 1 V output swing is
desired, RLOAD must be set to 500Ω. A properly selected
transformer will allow the AD9707 to provide the required
power and voltage levels to different loads.
(8) highlight some of the advantages of operating the AD9707
differentially. First, the differential operation helps cancel
common-mode error sources associated with IOUTA and
IOUTB, such as noise, distortion, and dc offsets. Second, the
differential code dependent current and subsequent voltage,
VDIFF, is twice the value of the single-ended voltage output (i.e.,
VOUTA or VOUTB), thus providing twice the signal power to the
load.
The output impedance of IOUTA and IOUTB is determined by
the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 200 MΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (i.e., VOUTA and VOUTB) due to the nature of a PMOS
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration will result in
the optimum dc linearity. Note that the INL/DNL specifications
for the AD9707 are measured with IOUTA maintained at a
virtual ground via an op amp.
Note that the gain drift temperature performance for a single-
ended (VOUTA and VOUTB) or differential output (VDIFF) of the
AD9707 can be enhanced by selecting temperature tracking
resistors for RLOAD and RSET due to their ratiometric relationship,
as shown in Equation
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of –1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a
(8).
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA, and
Rev. PrB | Page 20 of 27
Preliminary Technical Data
AD9707
breakdown of the output stage and affect the reliability of the
AD9707.
minimum times are met, although the location of these
transition edges may affect digital feedthrough and distortion
performance. Best performance is typically achieved when the
input data transitions on the falling edge of a 50% duty cycle
clock.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.2 V for an IOUTFS = 2 mA to 1 V for an IOUTFS = 1 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
CLOCK INPUT
TSSOP Package
The 28-lead TSSOP package option has a single-ended clock
input (CLOCK) that must be driven to rail-to-rail CMOS levels.
The quality of the DAC output is directly related to the clock
quality and jitter is a key concern. Any noise or jitter in the
clock will translate directly into the DAC output. Optimal
performance will be achieved if the CLOCK input has a sharp
rising edge, since the DAC latches are positive edge triggered.
ADJUSTABLE OUTPUT COMMON MODE (LFCSP
ONLY)
The 32-lead LFCSP package option provides the ability to set
the output common mode to a value other than ACOM via pin
19 (OTCM). This option allows the user to directly interface the
output of the AD9707 to components that require common
mode levels other than 0 V. The OTCM pin contains some
amount of data switching current and thus should be actively
driven to the desired voltage level when not tied directly to
ACOM. Optium performance is achieved when the voltage on
OTCM is equal to the center of the output swing on IOUTA
and IOUTB.
LFCSP Package
A configurable clock input is available in the 32-lead LFCSP
package, which allows for a single-ended and a differential clock
mode. The mode selection can be controlled either by the
CMODE pin if the SPI is disabled or through SPI REG02, Bit 2
(CLKDIFF) if the SPI is enabled. Connecting CMODE to
CLKCOM selects the single-ended clock input. In this mode,
the CLK+ input is driven with rail-to-rail swings and the CLK–
input is left floating. If CMODE is connected to CLKVDD, the
differential receiver mode is selected. In this mode, both inputs
are high impedance. Table 14 summarizes the clock mode
control for the LFCSP version of the AD9707. There is no
significant performance difference between the clock input
modes.
Note that setting OTCM to a voltage greater than ACOM allows
the peak of the output signal to be closer to the positive supply
rail. To prevent distortion in the output signal due to limited
available headroom, the supply voltage, common mode level
must be chosen such that the following expression is satisfied:
(10)
A
−VOTCM > 2.0V
VDD
DIGITAL INPUTS
SPI Disabled
CMODE Pin
CLKCOM
SPI Enabled
REG02, Bit 2
The AD9707 digital section consists of 14 input bit channels
and a clock input. The 14-bit parallel data inputs can follow
standard positive binary or twos complement coding, where
DB13 is the most significant bit (MSB) and DB0 is the least
significant bit (LSB). IOUTA produces a full-scale output
current when all data bits are at Logic 1. IOUTB produces a
Clock Input Mode
Single-Ended
Differential
0
1
CLKVDD
Table 14. Clock Mode Selection (LFCSP package)
The single-ended clock in the LFCSP package has the same
operating requirements as the TSSOP single-ended clock. Please
refer to the section describing the TSSOP single-ended clock
input for details on operating requirements.
complementary output with the full-scale current split between
the two outputs as a function of the input code.
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK– inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave since
the high gain bandwidth of the differential inputs will convert
the sine wave into a single-ended square wave internally.
Figure 28. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
175 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulsewidth. The setup and hold times
can also be varied within the clock cycle as long as the specified
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the
relationship between the position of the clock edges and the
time at which the input data changes. The AD9707 is rising-
Rev. PrB | Page 21 of 27
AD9707
Preliminary Technical Data
10
9
8
7
6
5
4
3
2
1
0
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the goal
when applying the AD9707 is to make the data transition close
to the falling clock edge. This becomes more important as the
sample rate increases. Figure 29 shows the relationship of SFDR
to clock placement with different sample rates. Note that at the
lower sample rates, more tolerance is allowed in clock
175 MSPS
125 MSPS
75 MSPS
placement, while at higher rates, more care must be taken.
25 MSPS
10 MSPS
0.01
TBD
0.1
1
fOUT/fCLOCK
Figure 31. IDVDD vs fOUT/fCLKRatio @ DVDD=3.3 V
Figure 29. SFDR vs. Clock Placement @ fOUT=20 MHz and 50 MHz
5
4
3
2
1
0
POWER DISSIPATION
DIFF
The power dissipation, PD, of the AD9707 is dependent on
several factors that include:
•
•
•
•
The power supply voltages (AVDD, CVDD, and DVDD)
The full-scale current output IOUTFS
The update rate fCLOCK
SE
The reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current, IAVDD, and the digital supply current, IDVDD. IAVDD
is directly proportional to IOUTFS, as shown in Figure 30, and is
insensitive to fCLOCK. Conversely, IDVDD is dependent on both the
digital input waveform, fCLOCK, and digital supply DVDD. Figure
31 shows IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 3.3 V. ICLKVDD
is directly proportional to fCLOCK, and is higher for differential
clock operation than single-ended operation. This difference in
clock current is due primarily to the differential clock receiver
which is disabled in single-ended clock mode.
0
50
100
150
200
fCLK (MSPS)
Figure 32. ICLKVDD vs. fCLOCK (Differential Clock Mode)
Sleep and Power-Down Mode Operation
The AD9707 has a sleep mode that turns off the output current
and reduces the total supply current to less than 3.5 mA over
the specified supply range of 1.7 V to 3.6 V and temperature
range. This mode can be activated by applying a logic level 1 to
the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5Ω x
AVDD. This digital input also contains an active pulldown
circuit that ensures that the AD9707 remains enabled if this
input is left disconnected.
8
7
6
5
4
3
2
1
0
The AD9707 takes less than 50 ns to power down and
approximately 5 µs to power back up.
LFCSP Package
The 32-lead LFCSP package option offers three power-down
functions that can be controlled through the SPI, if enabled.
These power-down modes reduce the power dissipation to as
little as 120 µA. The power-down functions are controlled
through SPI REG00, Bits 1–3. Table 15 below summarizes the
power-down functions of the AD9707 that can be controlled
through the SPI. The power-down mode can be enabled by
writing a logic level 1 to the corresponding bit in Register 00.
1
2
3
4
5
IOUTFS (mA)
Figure 30. IAVDD vs IOUTFS
Power Down
Mode
Clock Off
Sleep
Bit
(REG00)
Functional Description
1
2
Turn off clock
Turn off output current
Rev. PrB | Page 22 of 27
Preliminary Technical Data
AD9707
Power Down
3
Turn off clock, output current
and internal voltage reference
Table 15. Power-Down Mode Selection (LFCSP package)
Rev. PrB | Page 23 of 27
AD9707
Preliminary Technical Data
This board allows the user the flexibility to operate the AD9707
in various configurations. Possible output configurations
include transformer coupled, resistor terminated, and single and
differential outputs. The digital inputs are designed to be driven
from various word generators, with the on-board option to add
a resistor network for proper load termination. Provisions are
also made to operate the AD9707 with either the internal or
external reference or to exercise the power-down feature.
EVALUATION BOARD
GENERAL DESCRIPTION
The TxDAC family evaluation boards allow for easy setup and
testing of any TxDAC product in the TSSOP and LFCSP
packages. Careful attention to layout and circuit design,
combined with a prototyping area, allows the user to evaluate
the AD9707 easily and effectively in any application where low
power, high resolution, high speed conversion is required.
Rev. PrB | Page 24 of 27
Preliminary Technical Data
OUTLINE DIMENSIONS
AD9707
Figure 33. 32-Lead Lead Frame Chip Scale Package [LFCSP] (CP-32)
Dimensions shown in millimeters
Figure 34. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28)
Dimensions shown in millimeters
Rev. PrB | Page 25 of 27
AD9707
Preliminary Technical Data
ORDERING GUIDE
Model
Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Package Description
28-Lead TSSOP
28-Lead TSSOP
32-Lead LFCSP
32-Lead LFCSP
Package Options 1
RUZ-28
RUZ-28
CPZ-32
AD9707ARUZ
AD9707ARUZRL7
AD9707ACPZ
AD9707ACPZRL7
AD9707ACP-PCB
AD9707ARU-PCB
CPZ-32
Evaluation Board (LFCSP)
Evaluation Board (TSSOP)
1 RUZ = Pb-Free Thin Shrink Small Outline Package (TSSOP); CPZ = Pb-Free Lead Frame Chip Scale Package (LFCSP)
Rev. PrB | Page 26 of 27
Preliminary Technical Data
AD9707
REVISION HISTORY
Location
Page
7/05—Data Sheet changed from REV. A to REV. PrB.
UNIVERSAL
UNIVERSAL
4/05—Data Sheet changed from REV. 0 to REV. A.
Added 28-Lead TSSOP Package
2005
Analog Devices, Inc. All rights reserved. Trademarks and registered
trademarks are the property of their respective companies.
Printed in the U.S.A.
PR05674-0-7/05(PrB)
Rev. PrB | Page 27 of 27
相关型号：
AD9707BRUZ
IC PARALLEL INPUT LOADING, 14-BIT DAC, PDSO28, MO-153AE, TSSOP-28, Digital to Analog Converter
ADI
AD9707BRUZRL7
IC PARALLEL INPUT LOADING, 14-BIT DAC, PDSO28, MO-153AE, TSSOP-28, Digital to Analog Converter
ADI
AD9708AR
PARALLEL, 8 BITS INPUT LOADING, 0.035us SETTLING TIME, 8-BIT DAC, PDSO28, 0.300 INCH, SOIC-28
ROCHESTER
©2020 ICPDF网 联系我们和版权申明