AD9707BRUZ_技术文档

8-, 10-, 12-, 14-Bit, 175 MSPS

TxDAC^®D/A Converters

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

FEATURES¹

0

FUNCTIONAL BLOCK DIAGRAMS

Pin-compatible Family

Low Power Member of Pin Compatible

TxDAC Product Family

Power Dissipation @ 3.3 V:

21 mW @ 10 MSPS

24 mW @ 25 MSPS

30 mW @ 50 MSPS

Sleep Mode: 5 mW @ 3.3 V

Supply Voltage: 1.7 V to 3.6 V

SFDR to Nyquist:

AD9707: 85 dBc @ 5 MHz Output

AD9707: 80 dBc @ 10 MHz Output

AD9707: 75 dBc @ 20 MHz Output

AD9707 SNR @ 10 MHz Output, 125 MSPS: TBD dB

Differential Current Outputs: 1 mA to 5 mA

Data Format: Twos Complement or Straight Binary

On-Chip 1.0 V Reference

Figure 1. AD9707 Functional Block Diagram (LFCSP Package)

CMOS Compatible Digital Interface

Edge-Triggered Latches

32-LEAD LFCSP PACKAGE FEATURES

Clock Input: Single-Ended and Differential

Output Common Mode: Adjustable 0 V to 1.2 V

Power-Down Mode: < 400 μW @ 3.3 V (SPI Controllable)

Serial Peripheral Interface (SPI)

Figure 2. AD9707 Functional Block Diagram (TSSOP Package)

Self-calibration

32-Lead LFCSP Pb-Free Package

28-LEAD TSSOP PACKAGE FEATURES

Internal 500Ω Load Resistor

Internal 16kΩ Resistor to Set Full Scale Current Output

Clock Input: Single-Ended

28-Lead TSSOP Pb-Free Package

¹Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519

Rev. PrC

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infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

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registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

compensated band gap reference have been integrated to

provide a complete monolithic DAC solution. The digital inputs

support 1.8 V and 3.3 V CMOS logic families.

GENERAL DESCRIPTION

The AD9704/05/06/07 are the fourth generation family in the

TxDAC series of high performance, CMOS digital-to-analog

converters (DACs). This pin compatible 8–/10–/12–/14–bit

resolution family has been optimized for low power operation

while maintaining excellent dynamic performance. The AD970x

family is pin compatible with the AD9748/40/42/44 family of

TxDAC converters and is specifically optimized for the transmit

signal path of communication systems. All of the devices share

the same interface, small outline package, and pinout, providing

an upward or downward component selection path based on

performance, resolution, and cost. The AD970X offers

exceptional ac and dc performance while supporting update

rates up to 175 MSPS.

PRODUCT HIGHLIGHTS

1. Pin Compatible: The AD970x line of TxDACs is pin

compatible with the AD974x TxDAC line.

2. Low power: Complete CMOS DAC operates on a single

supply of 3.6 V down to 1.7 V, consuming 25mW (3.3V)

and 10mW (1.8 V). The DAC full-scale current can be

reduced for lower power operation, and sleep and

power-down modes are provided for low power idle

periods.

3. Self-Calibration (foreground) enables true 14-bit INL

and DNL performance. (LFCSP only)

4. Data input supports twos complement or straight binary

data coding.

5. High speed, single-ended and differential (LFCSP only)

CMOS clock input supports 175 MSPS conversion rate.

6. SPI control offers higher level of programmability.

(LFCSP package only)

7. Adjustable output common mode from 0 V to 1.2 V

allows for easy interfacing to other components that

accept common mode levels greater than 0 V (LFCSP

only).

8. On-chip voltage reference: The AD970X includes a 1.0 V

temperature compensated band gap voltage reference.

9. Industry-standard 28-lead TSSOP and 32-lead LFCSP

packages.

The AD970X’s flexible power supply operating range of 1.7 V to

3.6 V and low power dissipation makes it well suited for

portable and low power applications. Its power dissipation can

be further reduced to 15 mW with a slight degradation in

performance by lowering the full-scale current output. Also, a

power-down mode reduces the standby power dissipation to

approximately 5 mW.

The AD970X-LFCSP has an optional serial peripheral interface

(SPI) which provides a higher level of programmability to

enhance performance of the DAC. An adjustable output

common mode feature has also been added to the AD970X-

LFCSP that allows for easy interfacing to other components that

require common modes greater than 0 V.

Edge-triggered input latches and a 1.0 V temperature

Rev. PrC | Page 2 of 32

Preliminary Technical Data

TABLE OF CONTENTS

AD9704/AD9705/AD9706/AD9707

0

1

2

3

4

5

FEATURES ...................................................................................

32-LEAD LFCSP PACKAGE FEATURES................................

28-LEAD TSSOP PACKAGE FEATURES ...............................

FUNCTIONAL BLOCK DIAGRAMS......................................

GENERAL DESCRIPTION .......................................................

PRODUCT HIGHLIGHTS ........................................................

3

4

7

8

9

0

1

2

3

4

5

6

7

1

2

4

6

7

8

1

9

Functional Description.................................................................

5

6

7

6

7

8

9

0

1

2

3

4

5

6

7

8

9

0

1

2

3

21

23

24

25

26

27

29

30

31

32

2

3

0

1

2

3

4

5

6

7

8

9

0

1

Serial Peripheral Interface (LFCSP only) ...............................

SPI Register Map .......................................................................

SPI Register Descriptions .........................................................

Reference Operation .................................................................

Reference Control Amplifier....................................................

DAC Transfer Function ............................................................

Analog Outputs..........................................................................

Adjustable Output Common Mode (LFCSP only) ...............

Digital Inputs .............................................................................

Clock Input.................................................................................

DAC Timing...............................................................................

Power Dissipation......................................................................

6

AD9704/05/06/07–Specifications..................................................

7

8

9

1

DC Specifications (3.3 V) ...........................................................

Dynamic Specifications (3.3V) ..................................................

Digital Specifications (3.3V) ......................................................

0

1

2

DC Specifications (1.8V)............................................................

Dynamic Specifications (1.8V)................................................

Digital Specifications (1.8V) ....................................................

4

5

8

9

0

1

2

3

4

5

10

11

12

13

17

18

1

3

Absolute Maximum Ratings.........................................................

3

2

Evaluation Board ...........................................................................

1

4

Thermal Characteristics ...........................................................

ESD Caution...............................................................................

3

General Description..................................................................

1

5

3

4

5

6

Outline Dimensions ......................................................................

Ordering Guide..............................................................................

Revision History ............................................................................

1

6

7

8

Pin Configuration and Function Descriptions..........................

Definitions of Specifications ........................................................

AD9707–Typical Performance Characteristics .........................

Rev. PrC | Page 3 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

AD9704/05/06/07–SPECIFICATIONS

DC SPECIFICATIONS (3.3 V)

(T_MINto T_MAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I_OUTFS= 2 mA, unless otherwise noted.)

Table 1.

AD9707

AD9706

AD9705

Min Typ Max

AD9704

Min Typ Max

14

Parameter

Min Typ Max Min Typ Max

Unit

RESOLUTION

Bits

DC ACCURACY¹

0

F

Integral Nonlinearity (INL) Pre-

calibration

3

0.5

0.12

0.04

0.07

0.03

TBD

LSB

Integral Nonlinearity (INL) Post-

1

F

0.8

1.5

0.7

0.25

0.13

calibration²

Differential Nonlinearity (DNL) Pre-

calibration

Differential Nonlinearity (DNL)

Post-calibration²

ANALOG OUTPUT

Offset Error

Gain Error (Without Internal

Reference)

-0.02

+0.02 -0.02

+0.02 % of FSR

% of FSR

Gain Error (With Internal

Reference)

-0.8 -0.2 +0.2 -0.8 -0.2 +0.2

-0.8 -0.2 +0.2

% of FSR

Full-Scale Output Current³

2

F

1

2

5

1

2

5

1

2

5

1

2

5

mA

V

MΩ

pF

Output Compliance Range

Output Resistance

-1

+1.25 -1

+1.25

200

5

200

5

200

5

200

5

Output Capacitance

REFERENCE OUTPUT

Reference Voltage

1.0

100

1.0

100

V

nA

Reference Output Current⁴

3

F

100

REFERENCE INPUT

Input Compliance Range

0.1

1.25 0.1

1.25

0.1

1.25

0.1

1.25

V

Reference Input Resistance (Ext.

Reference)

1

MΩ

Small Signal Bandwidth

TEMPERATURE COEFFICIENTS

Offset Drift

0.5

MHz

0

ppm of

FSR/°C

Gain Drift (Without Internal

Reference)

Gain Drift (With Internal

Reference)

Reference Voltage Drift

POWER SUPPLY

Supply Voltages

AVDD

DVDD

CLKVDD

Analog Supply Current (I_AVDD

Digital Supply Current (I_DVDD

TBD

70

80

TBD

70

80

TBD

70

80

TBD

70

80

ppm of

FSR/°C

ppm of

FSR/°C

ppm/°C

2.5

3.3

4.5

1.1

1.7

0.4

20

3.6

2.5

3.3

4.5

1.1

1.7

0.4

20

3.6

2.5

3.3

4.5

1.1

1.7

0.4

20

3.6

2.5

3.3

4.5

1.1

1.7

0.4

20

3.6

V

mA

μA

)

5

)

4

F

Clock Supply Current (I_CLKVDD

Supply Current Sleep Mode (I_AVDD

Supply Current Power-Down

Mode

)

1.0

Rev. PrC | Page 4 of 32

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

Power Dissipation⁵

Power Dissipation⁶

Power Supply Rejection Ratio—

AVDD⁷

Power Supply Rejection Ratio—

DVDD⁷

7

4

24

46

24

46

24

46

24

46

mW

% of

5

F

-1

+1

-1

+1

+0.04 -0.04

+85 -40

-1

+1

+0.04 -0.04

+85 -40

-1

+1

6

F

FSR/V

-0.04

-40

+0.04 -0.04

+85 -40

+0.04 % of

FSR/V

7

5

OPERATING RANGE

+85

°C

¹Measured at IOUTA, driving a virtual ground.

²Calibration offered in LFCSP package only.

³Nominal full-scale current, I_OUTFS, is 32 times the I_REFcurrent.

⁴An external buffer amplifier with input bias current <100 nA should be used to drive any external load.

⁵Measured at f_CLOCK= 25 MSPS and f_OUT= 2.5 MHz.

⁶Measured at f_CLOCK= 175 MSPS and f_OUT= 20 MHz.

7

5% power supply variation.

Rev. PrC | Page 5 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

DYNAMIC SPECIFICATIONS (3.3V)

(T_MINto T_MAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I_OUTFS= 2 mA, differential transformer coupled output, 500 Ω terminated,

unless otherwise noted.)

Table 2

AD9707

AD9706

AD9705

AD9704

Parameter

Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f_CLOCK

)

175

MSPS

ns

pV-s

ns

Output Settling Time (t_ST) (to 0.1%)¹

7

F

TBD

45

TBD

Output Propagation Delay (t_PD

)

Glitch Impulse

Output Rise Time (10% to 90%)¹

Output Fall Time (10% to 90%)¹

7

6

7

Output Noise (I_OUTFS= 2 mA)

AC LINEARITY

pA/√Hz

Spurious-Free Dynamic Range to

Nyquist

f_CLOCK= 10 MSPS; f_OUT= 1.00 MHz

f_CLOCK= 25 MSPS; f_OUT= 1.00 MHz

f_CLOCK= 65 MSPS; f_OUT= 5.00 MHz

f_CLOCK= 65 MSPS; f_OUT= 10 MHz

f_CLOCK= 125 MSPS; f_OUT= 15 MHz

f_CLOCK= 125 MSPS; f_OUT= 25 MHz

f_CLOCK= 175 MSPS; f_OUT= 20 MHz

f_CLOCK= 175 MSPS; f_OUT= 40 MHz

Total Harmonic Distortion

82

80

79

78

75

79

91

82

77

75

80

88

79

77

76

TBD

dBc

f_CLOCK= 25 MSPS; f_OUT= 1.00 MHz

f_CLOCK= 50 MSPS; f_OUT= 2.00 MHz

f_CLOCK= 65 MSPS; f_OUT= 2.00 MHz

TBD

-89

-85

-87

-78

-79

-78

TBD

dBc

f_CLOCK= 125 MSPS; f_OUT= 2.00 MHz

Noise Spectral Density

f_CLOCK= 175 MSPS; f_OUT= 41.7 MHz;

I_OUTFS= 5 mA

f_CLOCK= 175 MSPS; f_OUT= 41.7 MHz;

I_OUTFS= 2 mA

f_CLOCK= 175 MSPS; f_OUT= 41.7 MHz;

I_OUTFS= 1 mA

-164.1

-168.3

-169.8

-163.7

-167.7

-169.8

-157.4

-167.5

-169.7

TBD

dBm/Hz

Multitone Power Ratio (8 Tones at 400 kHz

Spacing)

f_CLOCK= 78 MSPS; f_OUT= 15.0 MHz to

18.2 MHz

0 dBFS Output

- 6 Dbfs Output

-12 dBFS Output

-18 dBFS Output

TBD

dBc

¹Measured single-ended into 500 Ω•load.

Rev. PrC | Page 6 of 32

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

DIGITAL SPECIFICATIONS (3.3V)

(T_MINto T_MAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I_OUTFS= 2 mA, unless otherwise noted.)

Table 3

AD9707

Typ

AD9706

Typ

AD9705

Typ

AD9704

Typ

Parameter

Min

2.1

Max

Min

2.1

Max

Min

2.1

Max

Min

2.1

Max

Unit

DIGITAL INPUTS¹

8

F

Logic 1 Voltage

Logic 0 Voltage

3

0

3

0

3

0

3

0

V

0.9

Logic 1 Current

Logic 0 Current

Input Capacitance

Input Setup Time (t_S)

Input Hold Time (t_H)

Latch Pulsewidth (t_LPW

-10

+10

-10

+10

-10

+10

-10

+10

μA

pF

ns

5

TBD

)

CLK INPUTS²

9

F

Input Voltage Range

Common-Mode Voltage

Differential Voltage

0

0.75

0.5

3

2.25

0

0.75

0.5

3

2.25

0

0.75

0.5

3

2.25

0

0.75

0.5

3

2.25

V

1.5

¹Includes CLOCK pin on TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.

²Applicable to CLK+ and CLK– inputs when configured for differential clock input mode.

Rev. PrC | Page 7 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

DC SPECIFICATIONS (1.8V)

(T_MINto T_MAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, I_OUTFS= 1 mA, unless otherwise noted.)

Table 4.

AD9707

AD9706

AD9705

Min Typ Max

AD9704

Min Typ Max

14

Parameter

Min Typ Max Min Typ Max

Unit

RESOLUTION

Bits

DC ACCURACY¹

1

F

Integral Nonlinearity (INL) Pre-

calibration

3

0.5

0.1

TBD

LSB

Integral Nonlinearity (INL) Post-

2

F

0.8

1.5

0.7

0.3

0.05

0.07

0.03

calibration²

Differential Nonlinearity (DNL) Pre-

calibration

0.3

Differential Nonlinearity (DNL)

0.13

Post-calibration²

7

8

ANALOG OUTPUT

Offset Error

Gain Error (Without Internal

Reference)

-0.02

+0.02 -0.02

+0.02 % of FSR

% of FSR

Gain Error (With Internal

Reference)

-0.8 -0.2 +0.2 -0.8 -0.2 +0.2

-0.8 -0.2 +0.2

% of FSR

Full-Scale Output Current³

3

F

1

2

5

1

2

5

1

2

5

1

2

5

mA

V

MΩ

pF

Output Compliance Range

Output Resistance

-1

+1.25 -1

+1.25

200

5

200

5

200

5

200

5

Output Capacitance

REFERENCE OUTPUT

Reference Voltage

1.0

100

1.0

100

V

nA

Reference Output Current⁴

4

F

100

REFERENCE INPUT

Input Compliance Range

0.1

1.25 0.1

1.25

0.1

1.25

0.1

1.25

V

Reference Input Resistance (Ext.

Reference)

1

MΩ

Small Signal Bandwidth

TEMPERATURE COEFFICIENTS

Offset Drift

0.5

MHz

0

ppm of

FSR/°C

Gain Drift (Without Internal

Reference)

Gain Drift (With Internal

Reference)

Reference Voltage Drift

POWER SUPPLY

Supply Voltages

AVDD

DVDD

CLKVDD

Analog Supply Current (I_AVDD

Digital Supply Current (I_DVDD

TBD

70

80

TBD

70

80

TBD

70

80

TBD

70

80

ppm of

FSR/°C

ppm of

FSR/°C

ppm/°C

1.7

1.8

3.1

0.5

0.7

TBD 1.7

1.8

3.1

0.5

0.7

TBD

1.7

1.8

3.1

0.5

0.7

TBD

1.7

1.8

3.1

0.5

0.7

TBD

V

mA

)

5

)

5

F

Clock Supply Current (I_CLKVDD

)

¹Measured at IOUTA, driving a virtual ground.

²Calibration offered in LFCSP package only.

³Nominal full-scale current, I_OUTFS, is 32 times the I_REFcurrent.

⁴An external buffer amplifier with input bias current <100 nA should be used to drive any external load.

⁵Measured at f_CLOCK= 25 MSPS and f_OUT= 2.5 MHz.

Rev. PrC | Page 8 of 32

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

Supply Current Sleep Mode (I_AVDD

)

0.3

18

0.3

18

0.3

18

0.3

18

mA

Supply Current Power-Down

Mode

μA

Power Dissipation⁵

7

9

8

mW

Power Supply Rejection Ratio—

AVDD⁶

Power Supply Rejection Ratio—

DVDD⁶

-1

+1

-1

+1

+0.04 -0.04

+85 -40

-1

+1

+0.04 -0.04

+85 -40

-1

+1

% of

FSR/V

6

F

-0.04

-40

+0.04 -0.04

+85 -40

+0.04 % of

FSR/V

8

0

OPERATING RANGE

+85

°C

6

5% power supply variation.

Rev. PrC | Page 9 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

DYNAMIC SPECIFICATIONS (1.8V)

(T_MINto T_MAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, I_OUTFS= 1 mA, differential transformer coupled output, 500 Ω doubly

terminated, unless otherwise noted.)

Table 5

AD9707

AD9706

AD9705

AD9704

Parameter

Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f_CLOCK

)

80

MSPS

ns

pV-s

ns

Output Settling Time (t_ST) (to 0.1%) ¹

1

0

F

TBD

45

TBD

Output Propagation Delay (t_PD

)

Glitch Impulse

Output Rise Time (10% to 90%)¹

Output Fall Time (10% to 90%)¹

8

1

8

2

Output Noise (I_OUTFS= 2 mA)²

pA/√Hz

AC LINEARITY

Spurious-Free Dynamic Range to

Nyquist

f_CLOCK= 10 MSPS; f_OUT= 1.00 MHz

f_CLOCK= 25 MSPS; f_OUT= 1.00 MHz

f_CLOCK= 25 MSPS; f_OUT= 5 MHz

f_CLOCK= 65 MSPS; f_OUT= 10 MHz

f_CLOCK= 65 MSPS; f_OUT= 15 MHz

f_CLOCK= 80 MSPS; f_OUT= 15 MHz

f_CLOCK= 80 MSPS; f_OUT= 30 MHz

Total Harmonic Distortion

79

78

77

76

73

71

63

84

83

89

83

79

76

63

81

78

81

79

72

76

64

TBD

dBc

f_CLOCK= 10 MSPS; f_OUT= 1.00 MHz

f_CLOCK= 25 MSPS; f_OUT= 2.00 MHz

f_CLOCK= 45 MSPS; f_OUT= 2.00 MHz

f_CLOCK= 65 MSPS; f_OUT= 2.00 MHz

Noise Spectral Density

TBD

-83

-87

-86

-78

-82

-80

-81

TBD

dBc

f_CLOCK= 80 MSPS; f_OUT= 30 MHz; I_OUTFS

2 mA

f_CLOCK= 80 MSPS; f_OUT= 30 MHz; I_OUTFS

1 mA

=

-167.4

-170.1

-166.0

-169.6

-161.2

-166.2

TBD

dBm/Hz

Multitone Power Ratio (8 Tones at 400 kHz

Spacing)

f_CLOCK= 40 MSPS; f_OUT= 10 MHz to 13.2

MHz

0 dBFS Output

- 6 Dbfs Output

-12 dBFS Output

-18 dBFS Output

TBD

dBc

¹Measured single-ended into 500 Ω•load.

Rev. PrC | Page 10 of 32

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

DIGITAL SPECIFICATIONS (1.8V)

(T_MINto T_MAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, I_OUTFS= 1 mA, unless otherwise noted.)

Table 6

AD9707

Typ

AD9706

Typ

AD9705

Typ

AD9704

Typ

Parameter

Min

1.2

Max

Min

1.2

Max

Min

1.2

Max

Min

1.2

Max

Unit

DIGITAL INPUTS ¹

11

F

Logic 1 Voltage

Logic 0 Voltage

1.8

0

1.8

0

1.8

0

1.8

0

V

0.5

Logic 1 Current

Logic 0 Current

Input Capacitance

Input Setup Time (t_S)

Input Hold Time (t_H)

Latch Pulsewidth (t_LPW

-10

+10

-10

+10

-10

+10

-10

+10

μA

pF

ns

5

TBD

)

CLK INPUTS ²

12

F

Input Voltage Range

Common-Mode Voltage

Differential Voltage

0

0.4

0.5

1.8

1.3

0

0.4

0.5

1.8

1.3

0

0.4

0.5

1.8

1.3

0

0.4

0.5

1.8

1.3

V

0.9

1.5

0.9

1.5

0.9

1.5

0.9

1.5

¹Includes CLOCK pin on TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.

²Applicable to CLK+ and CLK– inputs when configured for differential clock input mode.

Figure 3. Timing Diagram

Rev. PrC | Page 11 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS¹

7

F

Table 7.

Thermal Resistance

28-Lead TSSOP

With

Parameter

Respect to Min

Max

Unit

θ

_JA= 67.7°C/W

32-Lead LFCSP

_JA= 32.5°C/W

AVDD

ACOM

-0.3

-3.9

-0.3

-1.0

-0.3

+3.9

V

DVDD

DCOM

+3.9

θ

CLKVDD

CLKCOM

DCOM

+3.9

V

ACOM

+0.3

V

¹Thermal impedance measurements were taken on a 4-layer board in still air,

in accordance with EIA/JESD51-7.

ACOM

CLKCOM

DVDD

+0.3

V

DCOM

+0.3

V

AVDD

+3.9

V

AVDD

CLKVDD

DCOM

+3.9

V

DVDD

+3.9

V

CLOCK, SLEEP

Digital Inputs, MODE

IOUTA, IOUTB

REFIO, REFLO, FS ADJ

CLK+, CLK–, CMODE

Junction Temperature

Storage Temperature

Lead Temperature (10 sec)

DVDD+0.3

AVDD+0.3

CLKVDD+0.3

150

V

DCOM

V

ACOM

V

ACOM

V

CLKCOM

V

°C

-65

+150

300

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to

absolute maximum ratings for extended periods may affect

device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. PrC | Page 12 of 32

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

28-Lead TSSOP

32-Lead LFCSP

Figure 4. AD9707 Pin Configurations (TSSOP and LFCSP packages)

Table 8. AD9707 Pin Function Descriptions

TSSOP

Pin No.

LFCSP

Pin No.

Mnemonic

Description

1

27

DB13

Most Significant Data Bit (MSB).

Data Bits 12–1.

2–13

28–32, 1, 2, DB12–DB1

4–8

14

15

9

DB0

Least Significant Data Bit (LSB).

25

SLEEP / CSB

Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated if not

used. Must be driven low during SPI operation.

16

17

N/A

23

REFLO

REFIO

Reference Ground when Internal 1.0 V Reference Used. Connect to AVDD to disable internal reference.

Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference

output when internal reference activated. Requires 0.1 ꢀF capacitor to ACOM when internal reference

activated.

18

19

24

FS ADJ

RSET

Full-Scale Current Output Adjust.

N/A

Internal 16K Resistor. Connect to pin 18 (FSADJ) to set 2 mA Full-Scale Output Current; it may be left floating

if not used. Refer to page 21 for details.

20

22

20

21

N/A

18

19

17

ACOM

IOUTB

IOUTA

RLOAD

AVDD

OTCM

Analog Common.

21

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

DAC Current Output. Full-scale current when all data bits are 1s.

Internal 500Ω Termination Resistor. Refer to page 21 for details.

Analog Supply Voltage (1.7 V – 3.6 V).

22

23

24

N/A

Adjustable Output Common Mode. Refer to page 21 for details.

PIN / SPI/RESET Selects SPI mode or Pin mode operation. Active low for SPI operation. Active high for non-SPI operation.

Pulse high to reset SPI registers to default values.

25

16

15

MODE / SDIO

Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. When SPI is

enabled (LFCSP package only), this pin acts as SPI data input / output.

N/A

CMODE / SCLK

Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK–).

Connect to CLKVDD for differential receiver. When SPI is enabled, SPI data clock input.

26

10, 26

3

DCOM

DVDD

CLOCK

CLK+

Digital Common.

27

Digital Supply Voltage (1.7 V – 3.6 V)

Clock Input. Data latched on positive edge of clock.

Differential Clock Input.

28

N/A

12

N/A

13

CLK–

Differential Clock Input.

11

CLKVDD

CLKCOM

Clock Supply Voltage (1.7 V – 3.6 V).

Clock Common.

14

Rev. PrC | Page 13 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

28-Lead TSSOP

32-Lead LFCSP

1

28

(MSB) DB11

DB10

DB9

CLOCK

DVDD

2

3

27

26

DCOM

MODE

AVDD

4

5

25

24

23

22

21

20

19

18

17

16

15

DB8

DB7

AD9706

DB5 1

DB4 2

24 FS ADJ

23 REFIO

PIN 1

INDICATOR

6

DB6

RLOAD

IOUTA

IOUTB

ACOM

RSET

TOP VIEW

7

DB5

DVDD 3

DB3 4

DB2 5

22 ACOM

21 IOUTA

20 IOUTB

(Not to Scale)

AD9706

TOP VIEW

8

DB4

9

19 OTCM

DB3

DB1 6

(Not to Scale)

(LSB) DB0 7

NC 8

18 AVDD

17 PIN (SPI/RESET)

10

11

12

13

14

DB2

DB1

FS ADJ

REFIO

REFLO

SLEEP

(LSB) DB0

NC

Figure 5. AD9706 Pin Configurations (TSSOP and LFCSP packages)

Table 9. AD9706 Pin Function Descriptions

TSSOP

Pin No.

LFCSP

Pin No.

Mnemonic

Description

1

27

DB11

Most Significant Data Bit (MSB).

Data Bits 10–1.

2–11

28–32, 1, 2, DB10–DB1

4–6

12

7

DB0

Least Significant Data Bit (LSB).

No Connection

13, 14

15

8, 9

25

NC

SLEEP / CSB

Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated if not

used. Must be driven low during SPI operation.

16

17

N/A

23

REFLO

REFIO

Reference Ground when Internal 1.0 V Reference Used. Connect to AVDD to disable internal reference.

Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference

output when internal reference activated. Requires 0.1 ꢀF capacitor to ACOM when internal reference

activated.

18

19

24

FS ADJ

RSET

Full-Scale Current Output Adjust.

N/A

Internal 16K Resistor. Connect to pin 18 (FSADJ) to set 2 mA Full-Scale Output Current; it may be left floating

if not used. Refer to page 21 for details.

20

22

20

21

N/A

18

19

17

ACOM

IOUTB

IOUTA

RLOAD

AVDD

OTCM

Analog Common.

21

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

DAC Current Output. Full-scale current when all data bits are 1s.

Internal 500Ω Termination Resistor. Refer to page 21 for details.

Analog Supply Voltage (1.7 V – 3.6 V).

22

23

24

N/A

Adjustable Output Common Mode. Refer to page 21 for details.

PIN / SPI/RESET Selects SPI mode or Pin mode operation. Active low for SPI operation. Active high for non-SPI operation.

Pulse high to reset SPI registers to default values.

25

16

15

MODE / SDIO

Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. When SPI is

enabled (LFCSP package only), this pin acts as SPI data input / output.

N/A

CMODE / SCLK

Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK–).

Connect to CLKVDD for differential receiver. When SPI is enabled, SPI data clock input.

26

10, 26

3

DCOM

DVDD

CLOCK

CLK+

Digital Common.

27

Digital Supply Voltage (1.7 V – 3.6 V)

Clock Input. Data latched on positive edge of clock.

Differential Clock Input.

28

N/A

12

N/A

13

CLK–

Differential Clock Input.

11

CLKVDD

CLKCOM

Clock Supply Voltage (1.7 V – 3.6 V).

Clock Common.

14

Rev. PrC | Page 14 of 32

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

28-Lead TSSOP

32-Lead LFCSP

1

28

(MSB) DB9

DB8

CLOCK

DVDD

2

3

27

26

DB7

DCOM

MODE

AVDD

4

5

25

24

23

22

21

20

19

18

17

16

15

DB6

DB5

AD9705

DB3 1

DB2 2

24 FS ADJ

23 REFIO

PIN 1

INDICATOR

6

DB4

RLOAD

IOUTA

IOUTB

ACOM

RSET

TOP VIEW

7

DB3

DVDD 3

DB1 4

(LSB) DB0 5

NC 6

22 ACOM

21 IOUTA

20 IOUTB

19 OTCM

(Not to Scale)

AD9705

8

DB2

TOP VIEW

9

DB1

(Not to Scale)

NC 7

18 AVDD

10

11

12

13

14

(LSB) DB0

NC

17 PIN (SPI/RESET)

NC 8

FS ADJ

REFIO

REFLO

SLEEP

NC

Figure 6. AD9705 Pin Configurations (TSSOP and LFCSP packages)

Table 10. AD9705 Pin Function Descriptions

TSSOP

Pin No.

1

2–9

10

LFCSP

Pin No.

27

Mnemonic

DB9

Description

Most Significant Data Bit (MSB).

Data Bits 8–1.

Least Significant Data Bit (LSB).

No Connection

28–32, 1–4

DB8–DB1

DB0

5

11–14

15

6–9

25

NC

SLEEP / CSB

Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated if not

used. Must be driven low during SPI operation.

16

17

N/A

23

REFLO

REFIO

Reference Ground when Internal 1.0 V Reference Used. Connect to AVDD to disable internal reference.

Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference

output when internal reference activated. Requires 0.1 ꢀF capacitor to ACOM when internal reference

activated.

18

19

24

FS ADJ

RSET

Full-Scale Current Output Adjust.

N/A

Internal 16K Resistor. Connect to pin 18 (FSADJ) to set 2 mA Full-Scale Output Current; it may be left floating

if not used. Refer to page 21 for details.

20

22

20

21

N/A

18

19

17

ACOM

IOUTB

IOUTA

RLOAD

AVDD

OTCM

Analog Common.

21

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

DAC Current Output. Full-scale current when all data bits are 1s.

Internal 500Ω Termination Resistor. Refer to page 21 for details.

Analog Supply Voltage (1.7 V – 3.6 V).

22

23

24

N/A

Adjustable Output Common Mode. Refer to page 21 for details.

PIN / SPI/RESET Selects SPI mode or Pin mode operation. Active low for SPI operation. Active high for non-SPI operation.

Pulse high to reset SPI registers to default values.

25

16

15

MODE / SDIO

Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. When SPI is

enabled (LFCSP package only), this pin acts as SPI data input / output.

N/A

CMODE / SCLK

Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK–).

Connect to CLKVDD for differential receiver. When SPI is enabled, SPI data clock input.

26

10, 26

3

DCOM

DVDD

CLOCK

CLK+

Digital Common.

27

Digital Supply Voltage (1.7 V – 3.6 V)

Clock Input. Data latched on positive edge of clock.

Differential Clock Input.

28

N/A

12

N/A

13

CLK–

Differential Clock Input.

11

CLKVDD

CLKCOM

Clock Supply Voltage (1.7 V – 3.6 V).

Clock Common.

14

Rev. PrC | Page 15 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

28-Lead TSSOP

32-Lead LFCSP

1

28

(MSB) DB7

DB6

DB5

DB4

DB3

DB2

DB1

(LSB) DB0

NC

CLOCK

DVDD

2

3

27

26

DCOM

MODE

AVDD

4

5

25

24

23

22

21

20

19

18

17

16

15

AD9704

DB1 1

(LSB) DB0 2

DVDD 3

NC 4

24 FS ADJ

23 REFIO

22 ACOM

21 IOUTA

20 IOUTB

PIN 1

6

RLOAD

IOUTA

IOUTB

ACOM

RSET

INDICATOR

TOP VIEW

7

(Not to Scale)

AD9704

TOP VIEW

8

NC 5

9

19 OTCM

NC 6

(Not to Scale)

NC 7

18 AVDD

10

11

12

13

14

NC

17 PIN (SPI/RESET)

NC 8

NC

FS ADJ

REFIO

REFLO

SLEEP

NC

Figure 7. AD9704 Pin Configurations (TSSOP and LFCSP packages)

Table 11. AD9704 Pin Function Descriptions

TSSOP

Pin No.

1

2–7

8

LFCSP

Pin No.

27

Mnemonic

DB7

DB6–DB1

DB0

Description

Most Significant Data Bit (MSB).

Data Bits 6–1.

28–32, 1

2

Least Significant Data Bit (LSB).

No Connection

9–14

15

4–9

25

NC

SLEEP / CSB

Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated if not

used. Must be driven low during SPI operation.

16

17

N/A

23

REFLO

REFIO

Reference Ground when Internal 1.0 V Reference Used. Connect to AVDD to disable internal reference.

Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference

output when internal reference activated. Requires 0.1 ꢀF capacitor to ACOM when internal reference

activated.

18

19

24

FS ADJ

RSET

Full-Scale Current Output Adjust.

N/A

Internal 16K Resistor. Connect to pin 18 (FSADJ) to set 2 mA Full-Scale Output Current; it may be left floating

if not used. Refer to page 21 for details.

20

22

20

21

N/A

18

19

17

ACOM

IOUTB

IOUTA

RLOAD

AVDD

OTCM

Analog Common.

21

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

DAC Current Output. Full-scale current when all data bits are 1s.

Internal 500Ω Termination Resistor. Refer to page 21 for details.

Analog Supply Voltage (1.7 V – 3.6 V).

22

23

24

N/A

Adjustable Output Common Mode. Refer to page 21 for details.

PIN / SPI/RESET Selects SPI mode or Pin mode operation. Active low for SPI operation. Active high for non-SPI operation.

Pulse high to reset SPI registers to default values.

25

16

15

MODE / SDIO

Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement. When SPI is

enabled (LFCSP package only), this pin acts as SPI data input / output.

N/A

CMODE / SCLK

Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK–).

Connect to CLKVDD for differential receiver. When SPI is enabled, SPI data clock input.

26

10, 26

3

DCOM

DVDD

CLOCK

CLK+

Digital Common.

27

Digital Supply Voltage (1.7 V – 3.6 V)

Clock Input. Data latched on positive edge of clock.

Differential Clock Input.

28

N/A

12

N/A

13

CLK–

Differential Clock Input.

11

CLKVDD

CLKCOM

Clock Supply Voltage (1.7 V – 3.6 V).

Clock Common.

14

Rev. PrC | Page 16 of 32

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

DEFINITIONS OF SPECIFICATIONS

range (FSR) per °C. For reference drift, the drift is reported in

ppm per °C.

Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the

actual analog output from the ideal output, determined by a

straight line drawn from zero to full scale.

Power Supply Rejection

The maximum change in the full-scale output as the supplies

are varied from nominal to minimum and maximum specified

voltages.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input

code.

Settling Time

The time required for the output to reach and remain within a

specified error band about its final value, measured from the

start of the output transition.

Monotonicity

A D/A converter is monotonic if the output either increases or

remains constant as the digital input increases.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired

output transients that are quantified by a glitch impulse. It is

specified as the net area of the glitch in pV-s.

Offset Error

The deviation of the output current from the ideal of zero is

called the offset error. For IOUTA, 0 mA output is expected

when the inputs are all 0s. For IOUTB, 0 mA output is expected

when all inputs are set to 1s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output

signal and the peak spurious signal over the specified

bandwidth.

Gain Error

The difference between the actual and ideal output span. The

actual span is determined by the output when all inputs are set

to 1s minus the output when all inputs are set to 0s.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured input signal. It is

expressed as a percentage or in decibels (dB).

Output Compliance Range

The range of allowable voltage at the output of a current output

DAC. Operation beyond the maximum compliance limits may

cause either output stage saturation or breakdown, resulting in

nonlinear performance.

Multitone Power Ratio

The spurious-free dynamic range containing multiple carrier

tones of equal amplitude. It is measured as the difference

between the rms amplitude of a carrier tone to the peak

spurious signal in the region of a removed tone.

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (25°C) value to the value at either T_MINor T_MAX. For

offset and gain drift, the drift is reported in ppm of full-scale

Figure 8. Basic AC Characterization Test Set-Up (LFCSP Package)

Rev. PrC | Page 17 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

AD9707–TYPICAL PERFORMANCE CHARACTERISTICS

TBD

Figure 9. SFDR vs. f_OUT

TBD

Figure 13. SFDR vs. f_OUTand I_OUTFS@ 65 MSPS

TBD

Figure 10. SFDR vs. f_OUT@ 25 MSPS

Figure 14. Single-Tone SFDR vs. A_OUT@ f_OUT=f_CLOCK/11

95

90

85

80

75

70

65

60

55

50

45

0dBFS

TBD

0

5

10

15

20

25

f_OUT- MHz

Figure 15. Single-Tone SFDR vs. A_OUT@ f_OUT=f_CLOCK/5

Figure 11. SFDR vs. f_OUT@ 65 MSPS

95

90

85

80

75

70

65

60

55

50

45

0dBFS

-6dBFS

TBD

0

10

20

30

40

50

60

f_OUT- MHz

Figure 16. SNR vs. f_CLOCKand I_OUTFS@ f_OUT=5 MHz and 0 dBFS

Figure 12. SFDR vs. f_OUT@ 175 MSPS

Rev. PrC | Page 18 of 32

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

TBD

Figure 21. Single-Tone SFDR

TBD

Figure 17. Dual-Tone IMD vs. A_OUT@ f_OUT=f_CLOCK/7

TBD

Figure 18. Typical INL

Figure 22. Dual-Tone SFDR

TBD

Figure 19. Typical DNL

TBD

Figure 23. Four-Tone SFDR

Figure 20. SFDR vs. Temperature @ 125 MSPS

Rev. PrC | Page 19 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

Figure 24. Simplified Block Diagram (LFCSP Package)

Rev. PrC | Page 20 of 32

Preliminary Technical Data

FUNCTIONAL DESCRIPTION

AD9704/AD9705/AD9706/AD9707

including both the Motorola SPI® and Intel® SSR protocols. The

interface allows read/write access to all registers that configure

the AD970X. Single or multiple byte transfers are supported, as

well as MSB first or LSB first transfer formats. The AD970X’s

serial interface port is configured as a single pin I/O.

8

3

Figure 24 shows a simplified block diagram of the AD970X.

The AD970X consists of a DAC, digital control logic, and full-

scale output current control. The DAC contains a PMOS

current source array capable of providing a nominal full-scale

current (I_OUTFS) of 2 mA and a maximum of 5 mA. The array is

divided into 31 equal currents that make up the five most

significant bits (MSBs). The next four bits, or middle bits,

consist of 15 equal current sources whose value is 1/16th of an

MSB current source. The remaining LSBs are binary weighted

fractions of the middle bits current sources. Implementing the

middle and lower bits with current sources, instead of an R-2R

ladder, enhances its dynamic performance for multitone or low

amplitude signals and helps maintain the DAC’s high output

impedance (i.e., >200MΩ).

General Operation of the Serial Interface

There are two phases to a communication cycle with the

AD970X. Phase 1 is the instruction cycle, which is the writing of

an instruction byte into the AD970X, coincident with the first

eight SCLK rising edges. The instruction byte provides the

AD970X serial port controller with information regarding the

data transfer cycle, which is Phase 2 of the communication

cycle. The Phase 1 instruction byte defines whether the

upcoming data transfer is read or write, the number of bytes in

the data transfer, and the starting register address for the first

byte of the data transfer. The first eight SCLK rising edges of

each communication cycle are used to write the instruction byte

into the AD970X.

All of these current sources are switched to one or the other of

the two output nodes (i.e., IOUTA or IOUTB) via PMOS

differential current switches. The switches are based on the

architecture that was pioneered in the AD9764 family, with

further refinements to reduce distortion contributed by the

switching transient. This switch architecture also reduces

various timing errors and provides matching complementary

drive signals to the inputs of the differential current switches.

A logic high on pin 17 (SPI RES/PIN), followed by a logic low,

will reset the SPI port timing to the initial state of the

instruction cycle. This is true regardless of the present state of

the internal registers or the other signal levels present at the

inputs to the SPI port. If the SPI port is in the midst of an

instruction cycle or a data transfer cycle, none of the present

data will be written.

The analog and digital sections of the AD970X have separate

power supply inputs (i.e., AVDD and DVDD) that can operate

independently over a 1.7 V to 3.6 V range. The digital section,

which is capable of operating at a rate of up to 175 MSPS,

consists of edge-triggered latches and segment decoding logic

circuitry. The analog section includes the PMOS current

sources, the associated differential switches, a 1.0 V band gap

voltage reference, and a reference control amplifier.

The remaining SCLK edges are for Phase 2 of the

communication cycle. Phase 2 is the actual data transfer

between the AD970X and the system controller. Phase 2 of the

communication cycle is a transfer of 1, 2, 3, or 4 data bytes as

determined by the instruction byte. Using one multibyte

transfer is the preferred method. Single byte data transfers are

useful to reduce CPU overhead when register access requires

one byte only. Registers change immediately upon writing to the

last bit of each transfer byte.

The DAC full-scale output current is regulated by the reference

control amplifier and can be set from 1 mA to 5 mA via an

external resistor, R_SET, connected to the full-scale adjust (FS

ADJ) pin. The external resistor, in combination with both the

reference control amplifier and voltage reference V_REFIO, sets the

reference current I_REF, which is replicated to the segmented

current sources with the proper scaling factor. The full-scale

Instruction Byte

The instruction byte contains the information shown in Table 9.

current, I_OUTFS, is 32 times I_REF

.

MSB

I7

LSB

I0

The AD970X-LFCSP provides the option of setting the output

common mode to a value other than ACOM via the output

common mode (OTCM) pin. This option allows the user to

directly interface the output of the AD970X to components that

require common mode levels greater than 0 V.

I6

I5

I4

I3

I2

I1

R/W

N1

N0

A4

A3

A2

A1

A0

Table 12. SPI Instruction Byte

R/W, Bit 7 of the instruction byte, determines whether a read or

a write data transfer will occur after the instruction byte write.

Logic high indicates read operation. Logic 0 indicates a write

operation. N1, N0, Bits 6 and 5 of the instruction byte,

determine the number of bytes to be transferred during the data

transfer cycle. The bit decodes are shown in Table 10.

SERIAL PERIPHERAL INTERFACE (LFCSP ONLY)

The AD970X serial port is a flexible, synchronous serial

communications port allowing easy interface to many industry

standard microcontrollers and microprocessors. The serial I/O

is compatible with most synchronous transfer formats,

Rev. PrC | Page 21 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

A4, A3, A2, A1, A0, Bits 4, 3, 2, 1, 0 of the instruction byte,

determine which register is accessed during the data transfer

portion of the communications cycle. For multibyte transfers,

this address is the starting byte address. The remaining register

addresses are generated by the AD970X based on the DATADIR

bit (REG00, bit 6).

the multibyte communication cycle.

The AD970X serial port controller data address will decrement

from the data address written toward 0x00 for multibyte I/O

operations if the MSB first mode is active. The serial port

controller address will increment from the data address written

toward 0x1F for multibyte I/O operations if the LSB first mode

is active.

N1

Description

0

1

0

1

0

1

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

Notes on Serial Port Operation

The AD970X serial port configuration is controlled by REG00,

bit 7. It is important to note that the configuration changes

immediately upon writing to the last bit of the register. For

multibyte transfers, writing to this register may occur during

the middle of communication cycle. Care must be taken to

compensate for this new configuration for the remaining bytes

of the current communication cycle.

Table 13. Byte Transfer Count

Serial Interface Port Pin Descriptions

SCLK—Serial Clock. The serial clock pin is used to

synchronize data to and from the AD970X and to run the

internal state machines. SCLK’s maximum frequency is 20 MHz.

All data input to the AD970X is registered on the rising edge of

SCLK. All data is driven out of the AD970X on the falling edge

of SCLK.

The same considerations apply to setting the software reset,

RESET (REG00, bit 5). All registers are set to their default values

EXCEPT REG00 which remains unchanged.

Use of only single byte transfers when changing serial port

configurations or initiating a software reset is recommended to

prevent unexpected device behavior.

CSB—Chip Select. Active low input starts and gates a

communication cycle. It allows more than one device to be used

on the same serial communications lines. The SDIO pin will go

to a high impedance state when this input is high. Chip select

should stay low during the entire communication cycle.

TBD

SDIO—Serial Data I/O. This pin is used as a bidirectional data

line to transmit and receive data.

Figure 25. Serial Register Interface Timing MSB First

MSB/LSB Transfers

The AD970X serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by register bit DATADIR (REG00, bit

6). The default is MSB first (DATADIR = 0).

TBD

Figure 26. Serial Register Interface Timing LSB First

When DATADIR = 0 (MSB first) the instruction and data bytes

must be written from most significant bit to least significant bit.

Multibyte data transfers in MSB first format start with an

instruction byte that includes the register address of the most

significant data byte. Subsequent data bytes should follow in

order from high address to low address. In MSB first mode, the

serial port internal byte address generator decrements for each

data byte of the multibyte communication cycle.

TBD

Figure 27. Timing Diagram for SPI Register Write

TBD

When DATADIR = 1 (LSB first) the instruction and data bytes

must be written from least significant bit to most significant bit.

Multibyte data transfers in LSB first format start with an

instruction byte that includes the register address of the least

significant data byte followed by multiple data bytes. The serial

port internal byte address generator increments for each byte of

Figure 28. Timing Diagram for SPI Register Read

Rev. PrC | Page 22 of 32

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

SPI REGISTER MAP

Table 14

Address

SPI CTL

DATA

CALMEM

MEMRDWR

MEMADDR

MEMDATA

ANAETST

Bit 7

SDIODIR

DATAFMT

Bit 6

DATADIR

Bit 5

SWRST

Bit 4

LNGINS

DCLKPOL

CALMEM[0]

Bit 3

PDN

LOWSKEW

DIVSEL[3]

SMEMWR

Bit 2

SLEEP

CLKDIFF

DIVSEL[2]

SMEMRD

Bit 1

CLKOFF

Bit 0

EXREF

CALCLK

DIVSEL[0]

UNCAL

00

02

0E

0F

10

11

17

CALMEM[1]

DIVSEL[1]

CALSTAT

CALEN

MEMADDR[5] MEMADDR[4] MEMADDR[3] MEMADDR[2] MEMADDR[1] MEMADDR[0]

MEMDATA[5] MEMDATA[4] MEMDATA[3] MEMDATA[2] MEMDATA[1] MEMDATA[0]

PRELDS1

CDAOFF

ONE OF

SPI REGISTER DESCRIPTIONS

Table 15

SPI CNTL (00)

SDIODIR

Bit

7

Direction (I/O)

Default

1

Description

1: SDIO pin hardwired for input or output during data transfer (3-wire interface)

0: Serial data uses MSB first format

1: Serial data uses LSB first format

0: Software reset not enabled (running)

1: Default all serial register bits, except address 00h

0: Use 1 byte premable (5 address bits)

1: Use 2 byte preamble (13 adress bits)

1: All analog and digital circuitry off, except serial interface

1: DAC output current off

I

DATADIR

SWRST

LNGINS

6

5

4

I

0

I

0

PDN

SLEEP

CLKOFF

3

2

1

I

0

1: Clock off

0: Internal bandgap reference

1: External reference

EXREF

0

I

0

DATA (02)

DATAFMT

Bit

7

Direction (I/O)

I

Default

0

Description

0: Unsigned binary input data format

1: 2's complement input data format

0: Data latched on DATACLK rising edge

1: Data latched on DATACLK falling edge

0: Low skew mode disabled

1: Low skew mode enabled

0: Single-ended clock input

1: Differential clock input

0: Calibration clock disabled

DCLKPOL

LOWSKEW

CLKDIFF

4

3

2

0

I

0

CALCLK

1: Calibration clock enabled

CALMEM (0E)

Bit

Direction (I/O)

O

Default

00

Description

Calibration Memory

00: Uncalibrated

01: Self calibration

CALMEM[5:4]

[5:4]

11: User input

Calibration clock divide ratio from channel data rate

0000: / 256

0001: / 128

:

DIVSEL[2:0]

[3:0]

I

0000

1110: / 2

1111: / 1

MEMRDWR (0F)

Bit

7

Direction (I/O)

O

Default

0

Description

0: Calibration cycle not complete

1: Calibration cycle complete

CALSTAT

CALEN

SMEMWR

SMEMRD

UNCAL

6

3

2

0

I

0

1: Calibration in progress

1: Write static memory data from external port

1: Read static memory to external port

1: Use uncalibrated

MEMADDR (10)

MEMADDR[5:0]

Bit

[5:0]

Direction (I/O)

I/O

Default

00000

Description

Address of static memory to be accessed

MEMDATA (11)

MEMDATA[5:0]

Bit

[5:0]

Direction (I/O)

I/O

Default

11111

Description

Data for static memory access

ANAETST (17)

Bit

3

Direction (I/O)

I

Default

0

Description

0: Pre-load calibration reference specified by user

1: Pre-load calibration reference of 32

PRELDS1

Rev. PrC | Page 23 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

REFERENCE OPERATION

The AD970X contains an internal 1.0 V band gap reference. The

internal reference can be disabled in both packages. To disable

the reference in the 32-lead LFCSP package, a logic 1 must be

written to REG00, Bit 0 (EXREF) in the SPI. In the 28-lead

TSSOP package, the reference can be disabled by raising REFLO

to AVDD. In both packages, the reference can also be

overridden by an external reference with no effect on

performance. REFIO serves as either an input or an output

depending on whether the internal or an external reference is

used. Table 13 summarizes the reference operation for the

LFCSP and TSSOP package options.

TBD

Figure 30. External Reference Configuration

REFERENCE CONTROL AMPLIFIER

The AD970X contains a control amplifier that is used to

regulate the full-scale output current, I_OUTFS. The control

amplifier is configured as a V-I converter, as shown in

8

6

Figure

29, so that its current output, I_REF, is determined by the ratio of

the V_REFIOand an external resistor, R_SET, as stated in Equation

(4). I_REFis copied to the segmented current sources with the

8

7

Reference REFIO pin

Mode

LFCSP

TSSOP

proper scale factor to set IOUTFS, as stated in Equation

8

Internal

Connect 0.1 ꢀF

Capacitor

REG00, Bit 0 = 0

(default)

REFLO = ACOM

REFLO = AVDD

(3).

External

Apply External

Reference

REG00, Bit 0 = 1

The control amplifier allows a 5:1 adjustment span of I_OUTFS

from 1 mA to 5 mA by setting I_REFbetween 31.25 μA and 156.25

μA (R_SETbetween 6.4 kΩ and 32 kΩ). The wide adjustment span

of I_OUTFSprovides several benefits. The first relates directly to the

power dissipation of the AD970X, which is proportional to

Table 16. Reference Operation (TSSOP and LFCSP packages)

To use the internal reference, simply decouple the REFIO pin to

ACOM with a 0.1 μF capacitor and enable the internal

I

_OUTFS(refer to the Power Dissipation section). The second

reference. To enable the internal reference in the 28-lead TSSOP

package, connect REFLO to ACOM via a resistance less than

5Ω. In the LFCSP package, a logic 0 must be written to REG00,

Bit 0 in the SPI. (Note that this is the default configuration for

the LFCSP package.) The internal reference voltage will be

present at REFIO. If the voltage at REFIO is to be used

benefit relates to the ability to adjust the output over a 14 dB

range, which is useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is

approximately 500 kHz and can be used for low frequency small

signal multiplying applications.

anywhere else in the circuit, an external buffer amplifier with an

input bias current of less than 100 nA should be used. An

DAC TRANSFER FUNCTION

The AD970X provides complementary current outputs, IOUTA

and IOUTB. IOUTA provides a near fullscale current output,

example of the use of the internal reference is shown in

8

4

Figure

29.

I

_OUTFS, when all bits are high (i.e., DAC CODE = 16383), while

IOUTB, the complementary output, provides no current. The

current output appearing at IOUTA and IOUTB is a function of

both the input code and I_OUTFSand can be expressed as

TBD

IOUTA =

IOUTB =

(

DAC CODE/16384

)

×I_OUTFS

(1)

(2)

Figure 29. Internal Reference Configuration

An external reference can be applied to REFIO, as shown in

8

5

(

16383 − DAC CODE

)

/16384×I_OUTFS

where DAC CODE = 0 to 16383 (i.e., decimal representation).

TBD

As mentioned previously, I_OUTFSis a function of the reference

current I_REF, which is nominally set by a reference voltage, V_REFIO

and external resistor, R_SET. It can be expressed as

,

I_OUTFS= 32×I_REF

(3)

Figure 30. The external reference may provide either a fixed

reference voltage to enhance accuracy and drift performance or

a varying reference voltage for gain control. Note that the 0.1 μF

compensation capacitor is not required since the internal

reference is overridden, and the relatively high input impedance

of REFIO minimizes any loading of the external reference.

where

I_REF=V_REFIO/R_SET

(4)

The two current outputs will typically drive a resistive load

directly or via a transformer. If dc coupling is required, IOUTA

Rev. PrC | Page 24 of 32

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

and IOUTB should be directly connected to matching resistive

loads, R_LOAD, that are tied to analog common, ACOM. The

single-ended voltage output appearing at the IOUTA and

IOUTB nodes is simply

IOUTB may be configured for single-ended or differential

operation. IOUTA and IOUTB can be converted into

complementary single-ended voltage outputs, V_OUTAand V_OUTB

,

via a load resistor, R_LOAD, as described in the DAC Transfer

Function section by Equations

9

2

V_OUTA= IOUTA×R_LOAD

V_OUTB= IOUTB×R_LOAD

(5)

(6)

(5) through

93

(8). The differential voltage, V_DIFF, existing between V_OUTAand

V_OUTB, can also be converted to a single-ended voltage via a

transformer or differential amplifier configuration. The ac

performance of the AD970X is optimum and specified using a

differential transformer-coupled output in which the voltage

swing at IOUTA and IOUTB is limited to 0.5 V.

Note: To achieve the maximum output compliance of 1 V at the

nominal 2 mA output current, R_LOADmust be set to 500Ω.

Also note that the full-scale value of V_OUTAand V_OUTBshould not

exceed the specified output compliance range to maintain

specified distortion and linearity performance

The 28-lead TSSOP package option contains two internal

resistors (R_SET= 16 kΩ and R_LOAD= 500 Ω) that can be used to

configure the AD970X with a reduced number of external

resistors. Connecting the RSET pin to the FSADJ pin sets the

full scale output current to 2 mA without the need for an

external R_SETresistor. Connecting the RLOAD pin to IOUTA

allows the user to generate a single-ended output driving into a

500 Ω load without the need for an external R_LOADresistor.

The distortion and noise performance of the AD970X can be

enhanced when it is configured for differential operation. The

common-mode error sources of both IOUTA and IOUTB can

be significantly reduced by the common-mode rejection of a

transformer or differential amplifier. These common-mode

error sources include even-order distortion products and noise.

The enhancement in distortion performance becomes more

significant as the frequency content of the reconstructed

waveform increases and/or its amplitude increases. This is due

to the first order cancellation of various dynamic common-

mode distortion mechanisms, digital feedthrough, and noise.

V_DIFF

=

(

IOUTA − IOUTB

)

×R_LOAD

(7)

Substituting the values of IOUTA, IOUTB, I_REF, and V_DIFFcan be

expressed as

Performing a differential-to-single-ended conversion via a

transformer also provides the ability to deliver twice the

reconstructed signal power to the load (assuming no source

termination). Since the output currents of IOUTA and IOUTB

are complementary, they become additive when processed

differentially.

V _DIFF

=

{(2× DAC CODE −16383

)

/16384

}

(8)

(

32×V_REFIO/ R_SET

)

× R_LOAD

Equations

8

9

(7) and

9

0

As mentioned above, if the AD970X is being used at its nominal

operating point of 2 mA output current, and 1 V output swing is

desired, R_LOADmust be set to 500Ω. A properly selected

transformer will allow the AD970X to provide the required

power and voltage levels to different loads.

(8) highlight some of the advantages of operating the AD970X

differentially. First, the differential operation helps cancel

common-mode error sources associated with IOUTA and

IOUTB, such as noise, distortion, and dc offsets. Second, the

differential code dependent current and subsequent voltage,

V_DIFF, is twice the value of the single-ended voltage output (i.e.,

V_OUTAor V_OUTB), thus providing twice the signal power to the

load.

The output impedance of IOUTA and IOUTB is determined by

the equivalent parallel combination of the PMOS switches

associated with the current sources and is typically 200 MΩ in

parallel with 5 pF. It is also slightly dependent on the output

voltage (i.e., V_OUTAand V_OUTB) due to the nature of a PMOS

device. As a result, maintaining IOUTA and/or IOUTB at a

virtual ground via an I-V op amp configuration will result in

the optimum dc linearity. Note that the INL/DNL specifications

for the AD970X are measured with IOUTA maintained at a

virtual ground via an op amp.

Note that the gain drift temperature performance for a single-

ended (V_OUTAand V_OUTB) or differential output (V_DIFF) of the

AD970X can be enhanced by selecting temperature tracking

resistors for R_LOADand R_SETdue to their ratiometric relationship,

as shown in Equation

9

1

IOUTA and IOUTB also have a negative and positive voltage

compliance range that must be adhered to in order to achieve

optimum performance. The negative output compliance range

of –1 V is set by the breakdown limits of the CMOS process.

Operation beyond this maximum limit may result in a

(8).

ANALOG OUTPUTS

The complementary current outputs in each DAC, IOUTA, and

Rev. PrC | Page 25 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

breakdown of the output stage and affect the reliability of the

AD970X.

minimum times are met, although the location of these

transition edges may affect digital feedthrough and distortion

performance. Best performance is typically achieved when the

input data transitions on the falling edge of a 50% duty cycle

clock.

The positive output compliance range is slightly dependent on

the full-scale output current, I_OUTFS. It degrades slightly from its

nominal 1.2 V for an I_OUTFS= 2 mA to 1 V for an I_OUTFS= 1 mA.

The optimum distortion performance for a single-ended or

differential output is achieved when the maximum full-scale

signal at IOUTA and IOUTB does not exceed 0.5 V.

CLOCK INPUT

TSSOP Package

The 28-lead TSSOP package option has a single-ended clock

input (CLOCK) that must be driven to rail-to-rail CMOS levels.

The quality of the DAC output is directly related to the clock

quality and jitter is a key concern. Any noise or jitter in the

clock will translate directly into the DAC output. Optimal

performance will be achieved if the CLOCK input has a sharp

rising edge, since the DAC latches are positive edge triggered.

ADJUSTABLE OUTPUT COMMON MODE (LFCSP

ONLY)

The 32-lead LFCSP package option provides the ability to set

the output common mode to a value other than ACOM via pin

19 (OTCM). This option allows the user to directly interface the

output of the AD970X to components that require common

mode levels other than 0 V. The OTCM pin contains some

amount of data switching current and thus should be actively

driven to the desired voltage level when not tied directly to

ACOM. Optium performance is achieved when the voltage on

OTCM is equal to the center of the output swing on IOUTA

and IOUTB.

LFCSP Package

A configurable clock input is available in the 32-lead LFCSP

package, which allows for a single-ended and a differential clock

mode. The mode selection can be controlled either by the

CMODE pin if the SPI is disabled or through SPI REG02, Bit 2

(CLKDIFF) if the SPI is enabled. Connecting CMODE to

CLKCOM selects the single-ended clock input. In this mode,

the CLK+ input is driven with rail-to-rail swings and the CLK–

input is left floating. If CMODE is connected to CLKVDD, the

differential receiver mode is selected. In this mode, both inputs

Note that setting OTCM to a voltage greater than ACOM allows

the peak of the output signal to be closer to the positive supply

rail. To prevent distortion in the output signal due to limited

available headroom, the supply voltage, common mode level

must be chosen such that the following expression is satisfied:

are high impedance.

Table 17 summarizes the clock mode

9

4

control for the LFCSP version of the AD970X. There is no

significant performance difference between the clock input

modes.

(10)

A

_VDD−V_OTCM> 2.0V

DIGITAL INPUTS

SPI Disabled

CMODE Pin

CLKCOM

SPI Enabled

REG02, Bit 2

The AD970X digital section consists of 14 input bit channels

and a clock input. The 14-bit parallel data inputs can follow

standard positive binary or twos complement coding, where

DB13 is the most significant bit (MSB) and DB0 is the least

significant bit (LSB). IOUTA produces a full-scale output

current when all data bits are at Logic 1. IOUTB produces a

complementary output with the full-scale current split between

the two outputs as a function of the input code.

Clock Input Mode

Single-Ended

Differential

0

1

CLKVDD

Table 17. Clock Mode Selection (LFCSP package)

The single-ended clock in the LFCSP package has the same

operating requirements as the TSSOP single-ended clock. Please

refer to the section describing the TSSOP single-ended clock

input for details on operating requirements.

In the differential input mode, the clock input functions as a

high impedance differential pair. The common-mode level of

the CLK+ and CLK– inputs can vary from 0.75 V to 2.25 V, and

the differential voltage can be as low as 0.5 V p-p. This mode

can be used to drive the clock with a differential sine wave since

the high gain bandwidth of the differential inputs will convert

the sine wave into a single-ended square wave internally.

Figure 31. Equivalent Digital Input

The digital interface is implemented using an edge-triggered

master/slave latch. The DAC output updates on the rising edge

of the clock and is designed to support a clock rate as high as

175 MSPS. The clock can be operated at any duty cycle that

meets the specified latch pulsewidth. The setup and hold times

can also be varied within the clock cycle as long as the specified

DAC TIMING

Input Clock and Data Timing Relationship

Dynamic performance in a DAC is dependent on the

relationship between the position of the clock edges and the

time at which the input data changes. The AD970X is rising-

Rev. PrC | Page 26 of 32

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

10

9

8

7

6

5

4

3

2

1

0

edge triggered, and so exhibits dynamic performance sensitivity

when the data transition is close to this edge. In general, the goal

when applying the AD970X is to make the data transition close

to the falling clock edge. This becomes more important as the

175 MSPS

sample rate increases. Figure 32 shows the relationship of SFDR

9

5

125 MSPS

75 MSPS

to clock placement with different sample rates. Note that at the

lower sample rates, more tolerance is allowed in clock

placement, while at higher rates, more care must be taken.

25 MSPS

10 MSPS

0.01

TBD

0.1

1

f_OUT/f_CLOCK

Figure 34. I_DVDDvs f_OUT/f_CLKRatio @ DVDD=3.3 V

Figure 32. SFDR vs. Clock Placement @ f_OUT=20 MHz and 50 MHz

5

4

3

2

1

0

POWER DISSIPATION

DIFF

The power dissipation, P_D, of the AD970X is dependent on

several factors that include:

•

The power supply voltages (AVDD, CVDD, and DVDD)

The full-scale current output I_OUTFS

The update rate f_CLOCK

SE

The reconstructed digital input waveform

The power dissipation is directly proportional to the analog

supply current, I_AVDD, and the digital supply current, I_DVDD. I_AVDD

is directly proportional to I_OUTFS, as shown in

insensitive to f_CLOCK. Conversely, I_DVDDis dependent on both the

digital input waveform, f_CLOCK, and digital supply DVDD. Figure

34 shows I_DVDDas a function of full-scale sine wave output ratios

(f_OUT/f_CLOCK) for various update rates with DVDD = 3.3 V. I_CLKVDD

is directly proportional to f_CLOCK, and is higher for differential

clock operation than single-ended operation. This difference in

clock current is due primarily to the differential clock receiver

which is disabled in single-ended clock mode.

0

50

100

150

200

f

_CLK(MSPS)

9

6

Figure 33, and is

Figure 35. I_CLKVDDvs. f_CLOCK(Differential Clock Mode)

9

7

Sleep and Power-Down Mode Operation

The AD970X has a sleep mode that turns off the output current

and reduces the total supply current to less than 3.5 mA over

the specified supply range of 1.7 V to 3.6 V and temperature

range. This mode can be activated by applying a logic level 1 to

the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5Ω x

AVDD. This digital input also contains an active pulldown

circuit that ensures that the AD970X remains enabled if this

input is left disconnected.

8

7

6

5

4

3

2

1

0

The AD970X takes less than 50 ns to power down and

approximately 5 μs to power back up.

LFCSP Package

The 32-lead LFCSP package option offers three power-down

functions that can be controlled through the SPI, if enabled.

These power-down modes reduce the power dissipation to as

little as 120 μA. The power-down functions are controlled

through SPI REG00, Bits 1–3. Table 15 below summarizes the

power-down functions of the AD970X that can be controlled

through the SPI. The power-down mode can be enabled by

writing a logic level 1 to the corresponding bit in Register 00.

1

2

3

4

5

I_OUTFS(mA)

Figure 33. I_AVDDvs I_OUTFS

Power Down

Mode

Clock Off

Sleep

Bit

(REG00)

Functional Description

1

2

Turn off clock

Turn off output current

Rev. PrC | Page 27 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

Power Down

3

Turn off clock, output current

and internal voltage reference

Table 18. Power-Down Mode Selection (LFCSP package)

Rev. PrC | Page 28 of 32

Preliminary Technical Data

AD9704/AD9705/AD9706/AD9707

This board allows the user the flexibility to operate the AD970X

in various configurations. Possible output configurations

include transformer coupled, resistor terminated, and single and

differential outputs. The digital inputs are designed to be driven

from various word generators, with the on-board option to add

a resistor network for proper load termination. Provisions are

also made to operate the AD970X with either the internal or

external reference or to exercise the power-down feature.

EVALUATION BOARD

GENERAL DESCRIPTION

The TxDAC family evaluation boards allow for easy setup and

testing of any TxDAC product in the TSSOP and LFCSP

packages. Careful attention to layout and circuit design,

combined with a prototyping area, allows the user to evaluate

the AD970X easily and effectively in any application where low

power, high resolution, high speed conversion is required.

Rev. PrC | Page 29 of 32

AD9704/AD9705/AD9706/AD9707

OUTLINE DIMENSIONS

Preliminary Technical Data

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

3.25

EXPOSED

4.75

BSC SQ

PAD

(BOTTOM VIEW)

3.10 SQ

2.95

0.50

0.40

0.30

17

16

8

9

0.25 MIN

3.50 REF

0.80 MAX

0.65 TYP

12° MAX

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 36. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5mm × 5mm, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

9.80

9.70

9.60

28

15

4.50

4.40

4.30

6.40 BSC

1

14

PIN 1

0.65

BSC

1.20 MAX

0.15

0.05

8°

0°

0.75

0.60

0.45

0.30

0.19

0.20

0.09

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AE

Figure 37. 28-Lead Thin Shrink Small Outline Package [TSSOP

(RU-28)

Dimensions shown in millimeters

Rev. PrC | Page 30 of 32

Preliminary Technical Data

ORDERING GUIDE

AD9704/AD9705/AD9706/AD9707

Model

Temperature Range

Package Description

28-Lead TSSOP

Package Options

RU-28

AD9704BRUZ

AD9704BRUZRL7

AD9704BCPZ

AD9704BCPZRL7

AD9704BCP-PCB

AD9704BRU-PCB

AD9705BRUZ

AD9705BRUZRL7

AD9705BCPZ

AD9705BCPZRL7

AD9705BCP-PCB

AD9705BRU-PCB

AD9706BRUZ

AD9706BRUZRL7

AD9706BCPZ

AD9706BCPZRL7

AD9706BCP-PCB

AD9706BRU-PCB

AD9707BRUZ

-40°C to +85°C

32-Lead LFCSP_VQ

Evaluation Board (LFCSP)

Evaluation Board (TSSOP)

28-Lead TSSOP

CP-32-2

-40°C to +85°C

RU-28

28-Lead TSSOP

RU-28

32-Lead LFCSP_VQ

Evaluation Board (LFCSP)

Evaluation Board (TSSOP)

28-Lead TSSOP

CP-32-2

-40°C to +85°C

RU-28

28-Lead TSSOP

RU-28

32-Lead LFCSP_VQ

Evaluation Board (LFCSP)

Evaluation Board (TSSOP)

28-Lead TSSOP

CP-32-2

-40°C to +85°C

RU-28

AD9707BRUZRL7

AD9707BCPZ

28-Lead TSSOP

RU-28

32-Lead LFCSP_VQ

Evaluation Board (LFCSP)

Evaluation Board (TSSOP)

CP-32-2

AD9707BCPZRL7

AD9707BCP-PCB

AD9707BRU-PCB

Rev. PrC | Page 31 of 32

AD9704/AD9705/AD9706/AD9707

Preliminary Technical Data

REVISION HISTORY

Location

Page

1/06—Data Sheet changed from REV. PrB to REV. PrC.

Added AD9704/05/06 generics and related data

7/05—Data Sheet changed from REV. A to REV. PrB.

UNIVERSAL

4/05—Data Sheet changed from REV. 0 to REV. A.

Added 28-Lead TSSOP Package

trademarks are the property of their respective companies.

PR05926-0-1/06(PrC)

Printed in the U.S.A.

Rev. PrC | Page 32 of 32


型号：	AD9707BRUZ
厂家：	ADI
描述：	IC PARALLEL INPUT LOADING, 14-BIT DAC, PDSO28, MO-153AE, TSSOP-28, Digital to Analog Converter 输入元件光电二极管
文件：	总32页 (文件大小：573K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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