AD9739ABBCZ [ADI]
11-/14-Bit, 2.5 GSPS; 11-位/ 14位， 2.5 GSPS
| 型号： | AD9739ABBCZ |
| 厂家： | 
ADI |
| 描述： | 11-/14-Bit, 2.5 GSPS |
| 文件： | 总64页 (文件大小：2705K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
11-/14-Bit, 2.5 GSPS,
RF Digital-to-Analog Converters
AD9737A/AD9739A
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Direct RF synthesis at 2.5 GSPS update rate
DC to 1.25 GHz in baseband mode
1.25 GHz to 3.0 GHz in mix-mode
Industry leading single/multicarrier IF or RF synthesis
Dual-port LVDS data interface
Up to 1.25 GSPS operation
Source synchronous DDR clocking
Pin compatible with the AD9739
RESET
IRQ
AD9737A/AD9739A
SDIO
SDO
CS
1.2V
SPI
DAC BIAS
SCLK
VREF
I120
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.1 W at 2.5 GSPS
IOUTN
IOUTP
TxDAC
CORE
APPLICATIONS
DCI
Broadband communications systems
DOCSIS CMTS systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics
CLK DISTRIBUTIONꢀ
DLL
(DIV-BY-4)
(MU CONTROLLER)
DCO
DACCLK
Figure 1.
GENERAL DESCRIPTION
The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high
performance RF DACs that are capable of synthesizing wideband
signals from dc up to 3 GHz. The AD9737A/AD9739A are pin
and functionally compatible with the AD9739 with the
exception that the AD9737A/AD9739A do not support
synchronization or RZ mode, and are specified to operate
between 1.6 GSPS and 2.5 GSPS.
The AD9737A/AD9739A are manufactured on a 0.18 µm
CMOS process and operate from 1.8 V and 3.3 V supplies.
They are supplied in a 160-ball chip scale ball grid array for
reduced package parasitics.
PRODUCT HIGHLIGHTS
1. Ability to synthesize high quality wideband signals with
bandwidths of up to 1.25 GHz in the first or second
Nyquist zone.
2. A proprietary quad-switch DAC architecture provides
exceptional ac linearity performance while enabling mix-
mode operation.
3. A dual-port, double data rate, LVDS interface supports the
maximum conversion rate of 2500 MSPS.
4. On-chip controllers manage external and internal clock
domain skews.
By elimination of the synchronization circuitry, some nonideal
artifacts such as images and discrete clock spurs remain stationary
on the AD9737A/AD9739A between power-up cycles, thus
allowing for possible system calibration. AC linearity and noise
performance remain the same between the AD9739 and the
AD9737A/AD9739A.
The inclusion of on-chip controllers simplifies system integration.
A dual-port, source synchronous, LVDS interface simplifies the
digital interface with existing FGPA/ASIC technology. On-chip
controllers are used to manage external and internal clock domain
variations over temperature to ensure reliable data transfer from
the host to the DAC core. A serial peripheral interface (SPI) is
used for device configuration as well as readback of status
registers.
5. Programmable differential current output with an 8.66 mA
to 31.66 mA range.
Rev.C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved.
AD9737A/AD9739A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
SPI Register Map Description .................................................. 40
SPI Operation ............................................................................. 40
SPI Register Map ............................................................................ 42
SPI Port Configuration and Software Reset ........................... 43
Power-Down LVDS Interface and TxDAC® ........................... 43
Controller Clock Disable........................................................... 43
Interrupt Request (IRQ) Enable/Status................................... 44
TxDAC Full-Scale Current Setting (IOUTFS) and Sleep........... 44
TxDAC Quad-Switch Mode of Operation.............................. 44
DCI Phase Alignment Status .................................................... 44
Data Receiver Controller Configuration................................. 44
Data Receiver Controller_Data Sample Delay Value ............ 45
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
LVDS Digital Specifications........................................................ 5
Serial Port Specifications............................................................. 6
AC Specifications.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics—AD9737A ..................... 14
Static Linearity ............................................................................ 14
AC (Normal Mode).................................................................... 15
AC (Mix-Mode).......................................................................... 17
One-Carrier DOCSIS Performance (Normal Mode)............ 20
Four-Carrier DOCSIS Performance (Normal Mode) ........... 21
Eight-Carrier DOCSIS Performance (Normal Mode) .......... 22
16-Carrier DOCSIS Performance (Normal Mode) ............... 23
32-Carrier DOCSIS Performance (Normal Mode) ............... 24
64- and 128-Carrier DOCSIS Performance (Normal Mode)25
Typical Performance Characteristics—AD9739A ..................... 26
Static Linearity ............................................................................ 26
AC (Normal Mode).................................................................... 28
AC (Mix-Mode).......................................................................... 31
One-Carrier DOCSIS Performance (Normal Mode)............ 33
Four-Carrier DOCSIS Performance (Normal Mode) ........... 34
Eight-Carrier DOCSIS Performance (Normal Mode) .......... 35
16-Carrier DOCSIS Performance (Normal Mode) ............... 36
32-Carrier DOCSIS Performance (Normal Mode) ............... 37
64- and 128-Carrier DOCSIS Performance (Normal Mode)38
Terminology .................................................................................... 39
Serial Port Interface (SPI) Register............................................... 40
Data Receiver Controller_DCI Delay Value/Window and
Phase Rotation............................................................................ 45
Data Receiver Controller_Delay Line Status .......................... 45
Data Receiver Controller Lock/Tracking Status..................... 45
CLK Input Common Mode ...................................................... 46
Mu Controller Configuration and Status................................ 46
Part ID ......................................................................................... 47
Theory of Operation ...................................................................... 48
LVDS Data Port Interface.......................................................... 49
Mu Controller............................................................................. 52
Interrupt Requests...................................................................... 54
Analog Interface Considerations.................................................. 55
Analog Modes of Operation ..................................................... 55
Clock Input Considerations...................................................... 56
Voltage Reference ....................................................................... 57
Analog Outputs .......................................................................... 57
Output Stage Configuration ..................................................... 59
Nonideal Spectral Artifacts....................................................... 60
Lab Evaluation of the AD9737A/AD9739A ........................... 61
Recommended Start-Up Sequence .......................................... 61
Outline Dimensions....................................................................... 63
Ordering Guide .......................................................................... 63
Rev.C | Page 2 of 64
Data Sheet
AD9737A/AD9739A
REVISION HISTORY
Added SPI Port Configuration and Software Reset Section,
Power-Down LVDS Interface and TxDAC Section, Controller
Clock Disable Section, and Table 11 to Table 13 ........................43
Added Interrupt Request (IRQ) Enable/Status Section, TxDAC
Full-Scale Current Setting (IOUTFS) and Sleep Section, TxDAC
Quad-Switch Mode of Operation Section, DCI Phase
2/12—Rev. B to Rev. C
Changes to Figure 5...........................................................................9
Changes to Table 7 ..........................................................................11
Changes to Ordering Guide...........................................................63
2/12—Rev. A to Rev. B
Alignment Status Section, Data Receiver Controller
Added AD9737A................................................................ Universal
Reorganized Layout ........................................................... Universal
Moved Revision History Section.....................................................3
Deleted 6% from Table Summary Statement; Changes
to Table 1 ............................................................................................4
Deleted 6% from Table Summary Statement, Table 2................5
Deleted 6% from Table Summary Statement, Table 3................6
Changes to AC Specifications Section and Table 4.......................7
Added Figure 5, Renumbered Sequentially ...................................9
Added Figure 7 and Table 7, Renumbered Sequentially............10
Deleted Figure 24 ............................................................................13
Added Typical Performance Characteristics—AD9737A
Configuration Section, and Table 14 to Table 18........................44
Added Data Receiver Controller_Data Sample Delay Value
Section, Data Receiver Controller_DCI Delay Value/Window
and Phase Rotation Section, Data Receiver Controller_Delay
Line Status Section, Data Receiver Controller Lock/Tracking
Status Section, and Table 19 to Table 22 ......................................45
Added CLK Input Common Mode Section, and Mu
Controller Configuration and Status Section, and Table 23
and Table 24 .....................................................................................46
Added Part ID Section, and Table 25 ...........................................47
Changes to LVDS Data Port Interface Section............................49
Changes to Data Receiver Controller Initialization
Section and Figure 9 to Figure 77 .................................................14
Deleted Table 9 ................................................................................25
Added Static Linearity Section and Figure 78 to Figure 88 ............26
Added Figure 106 ............................................................................30
Changes to Figure 116, Figure 117, Figure 118, Figure 119,
Figure 120, and Figure 121.............................................................33
Changes to Figure 122, Figure 123, Figure 124, Figure 125,
Figure 126, and Figure 127.............................................................34
Changes to Figure 128, Figure 129, Figure 130, Figure 131,
Figure 132, and Figure 133.............................................................35
Changes to Figure 134, Figure 135, Figure 136, Figure 137,
Figure 138, and Figure 139.............................................................36
Changes to Figure 140, Figure 141, Figure 142, Figure 143,
Figure 144, and Figure 145.............................................................37
Changes to Figure 146, Figure 147, Figure 148, Figure 149,
and Figure 150; Added Figure 151................................................38
Added Table 10 ................................................................................42
Description Section ........................................................................51
Changes to Mu Controller Section ...............................................52
Added Figure 167 and Table 27, Changes to Mu Controller
Initialization Description Section.................................................53
Changes to Analog Modes of Operation Section, Figure 171,
and Figure 172 .................................................................................55
Updated Outline Dimensions........................................................63
Changes to Ordering Guide...........................................................63
7/11—Rev. 0 to Rev. A
Changed Maximum Update Rate (DACCLK Input) Parameter
to DAC Clock Rate Parameter in Table 4.......................................6
Added Adjusted DAC Update Rate Parameter and Endnote 1 in
Table 4.................................................................................................6
Updated Outline Dimensions........................................................43
1/11—Revision 0: Initial Version
Rev. C | Page 3 of 64
AD9737A/AD9739A
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA.
Table 1.
AD9737A
Typ
AD9739A
Typ
Parameter
Min
Max
Min
Max
Unit
RESOLUTION
11
14
Bits
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Gain Error (with Internal Reference)
Full-Scale Output Current
Output Compliance Range
Common-Mode Output Resistance
Differential Output Resistance
Output Capacitance
DAC CLOCK INPUT (DACCLK_P, DACCLK_N)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Clock Rate
0.5
0.5
2.5
2.0
LSB
LSB
5.5
20.2
5.5
20.2
%
8.66
−1.0
31.66 8.66
31.66 mA
+1.0
−1.0
+1.0
V
MΩ
Ω
10
70
1
10
70
1
pF
1.2
1.6
1.6
900
2.0
2.5
1.2
1.6
1.6
900
2.0
2.5
V
mV
GHz
TEMPERATURE DRIFT
Gain
Reference Voltage
REFERENCE
60
20
60
20
ppm/°C
ppm/°C
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
VDDA
1.15
1.2
5
1.25
1.15
1.2
5
1.25
V
kΩ
3.1
1.70
3.3
1.8
3.5
1.90
3.1
1.70
3.3
1.8
3.5
1.90
V
V
VDDC
DIGITAL SUPPLY VOLTAGES
VDD33
VDD
3.10
1.70
3.3
1.8
3.5
1.90
3.10
1.70
3.3
1.8
3.5
1.90
V
V
SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS
IVDDA
IVDDC
IVDD33
IVDD
37
38
167
16
37
38
167
16
mA
mA
mA
mA
W
158
14.5
173
0.770
2.5
158
14.5
173
0.770
2.5
183
183
Power Dissipation
Sleep Mode, IVDDA
2.75
2.75
mA
Power-Down Mode (All Power-Down Bits Set in Register 0x01 and
Register 0x02)
IVDDA
IVDDC
IVDD33
IVDD
0.02
6
0.6
0.1
0.02
6
0.6
0.1
mA
mA
mA
mA
SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS
IVDDC
IVDD33
IVDD
223
14.5
215
223
14.5
215
mA
mA
mA
mW
Power Dissipation
0.960
0.960
Rev.C | Page 4 of 64
Data Sheet
AD9737A/AD9739A
LVDS DIGITAL SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-
1996 reduced range link, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
LVDS DATA INPUTS (DB0[13:0], DB1[13:0])1
Input Common-Mode Voltage Range, VCOM
Logic High Differential Input Threshold, VIH_DTH
Logic Low Differential Input Threshold, VIL_DTH
Receiver Differential Input Impedance, RIN
Input Capacitance
825
175
−175
80
1575
mV
mV
mV
Ω
400
−400
120
1.2
pF
LVDS Input Rate
LVDS Minimum Data Valid Period (tMDE) (See Figure 159)
LVDS CLOCK INPUT (DCI)2
1250
MSPS
ps
344
Input Common-Mode Voltage Range, VCOM
Logic High Differential Input Threshold, VIH_DTH
Logic Low Differential Input Threshold, VIL_DTH
Receiver Differential Input Impedance, RIN
Input Capacitance
825
175
−175
80
1575
mV
mV
mV
Ω
400
−400
120
1.2
pF
Maximum Clock Rate
625
MHz
LVDS CLOCK OUTPUT (DCO)3
Output Voltage High (DCO_P or DCO_N)
Output Voltage Low (DCO_P or DCO_N)
1375
mV
mV
mV
mV
Ω
1025
150
1150
80
Output Differential Voltage, |VOD
|
200
100
250
1250
120
10
Output Offset Voltage, VOS
Output Impedance, Single-Ended, RO
RO Single-Ended Mismatch
Maximum Clock Rate
%
MHz
625
1 DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.
2 DCI_P and DCI_N pins.
3 DCO_P and DCO_N pins with 100 Ω differential termination.
Rev.C | Page 5 of 64
AD9737A/AD9739A
Data Sheet
SERIAL PORT SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V.
Table 3.
Parameter
Min
Typ
Max
Unit
WRITE OPERATION (See Figure 154)
SCLK Clock Rate, fSCLK, 1/tSCLK
SCLK Clock High, tHIGH
20
MHz
ns
ns
ns
ns
18
18
2
1
3
SCLK Clock Low, tLOW
SDIO to SCLK Setup Time, tDS
SCLK to SDIO Hold Time, tDH
CS to SCLK Setup Time, tS
SCLK to CS Hold Time, tH
ns
2
ns
READ OPERATION (See Figure 155 and Figure 156)
SCLK Clock Rate, fSCLK, 1/tSCLK
SCLK Clock High, tHIGH
SCLK Clock Low, tLOW
SDIO to SCLK Setup Time, tDS
20
15
MHz
ns
ns
ns
ns
18
18
2
1
3
SCLK to SDIO Hold Time, tDH
CS to SCLK Setup Time, tS
ns
SCLK to SDIO (or SDO) Data Valid Time, tDV
CS to SDIO (or SDO) Output Valid to High-Z, tEZ
ns
ns
2
INPUTS (SDI, SDIO, SCLK, CS)
Voltage in High, VIH
Voltage in Low, VIL
2.0
3.3
0
V
V
0.8
Current in High, IIH
Current in Low, IIL
−10
−10
+10
+10
µA
µA
OUTPUT (SDIO)
Voltage Out High, VOH
Voltage Out Low, VOL
Current Out High, IOH
Current Out Low, IOL
2.4
0
3.5
0.4
V
V
mA
mA
4
4
Rev.C | Page 6 of 64
Data Sheet
AD9737A/AD9739A
AC SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA, fDAC = 2400 MSPS, unless otherwise noted.
Table 4.
AD9737A
Typ
AD9739A
Typ
Parameter
Min
Max
Min
Max
Unit
DYNAMIC PERFORMANCE
DAC Clock Rate
Adjusted DAC Update Rate1
Output Settling Time to 0.1%
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fOUT = 100 MHz
fOUT = 350 MHz
fOUT = 550 MHz
fOUT = 950 MHz
1600
1600
2500
2500
1600
1600
2500
2500
MSPS
MSPS
ns
13
13
70
65
58
55
70
65
58
55
dBc
dBc
dBc
dBc
TWO-TONE INTERMODULATION DISTORTION (IMD),
f
OUT2 = fOUT1 + 1.25 MHz
fOUT = 100 MHz
fOUT = 350 MHz
fOUT = 550 MHz
fOUT = 950 MHz
94
78
72
68
94
78
72
68
dBc
dBc
dBc
dBc
NOISE SPECTRAL DENSITY (NSD), 0 dBFS SINGLE TONE
fOUT = 100 MHz
fOUT = 350 MHz
fOUT = 550 MHz
fOUT = 850 MHz
−162
−162
−161
−161
−167
−166
−164
−163
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
WCDMA ACLR (SINGLE CARRIER), ADJACENT/ALTERNATE
ADJACENT CHANNEL
fDAC = 2457.6 MSPS, fOUT = 350 MHz
fDAC = 2457.6 MSPS, fOUT = 950 MHz
fDAC = 2457.6 MSPS, fOUT = 1700 MHz (Mix-Mode)
fDAC = 2457.6 MSPS, fOUT = 2100 MHz (Mix-Mode)
80/81
75/75
69/71
66/67
80/80
78/79
74/74
69/72
dBc
dBc
dBc
dBc
1 Adjusted DAC updated rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9737A/AD9739A, the minimum interpolation factor
is 1. Thus, with fDAC = 2500 MSPS, fDAC, adjusted, = 2500 MSPS.
Rev.C | Page 7 of 64
AD9737A/AD9739A
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
VDDA to VSSA
−0.3 V to +3.6 V
VDD33 to VSS
VDD to VSS
VDDC to VSSC
VSSA to VSS
−0.3 V to +3.6 V
Table 6. Thermal Resistance
Package Type
−0.3 V to +1.98 V
−0.3 V to +1.98 V
−0.3 V to +0.3 V
θJA
θJC
Unit
°C/W1
160-Ball CSP_BGA
31.2
7.0
1 With no airflow movement.
VSSA to VSSC
−0.3 V to +0.3 V
VSS to VSSC
DACCLK_P, DACCLK_N to VSSC
DCI, DCO to VSS
LVDS Data Inputs to VSS
IOUTP, IOUTN to VSSA
I120, VREF to VSSA
IRQ, CS, SCLK, SDO, SDIO, RESET to VSS
Junction Temperature
Storage Temperature Range
−0.3 V to +0.3 V
ESD CAUTION
−0.3 V to VDDC + 0.18 V
−0.3 V to VDD33 + 0.3 V
−0.3 V to VDD33 + 0.3 V
−1.0 V to VDDA + 0.3 V
−0.3 V to VDDA + 0.3 V
−0.3 V to VDD33 + 0.3 V
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev.C | Page 8 of 64
Data Sheet
AD9737A/AD9739A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10 11 12 13 14
1
2
3
4
5
6
7
8
9
10 11 12 13 14
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
AD9737A/AD9739A
AD9737A/AD9739A
K
L
K
L
M
N
P
M
N
P
VDDC, 1.8V, CLOCK SUPPLY
VDDA, 3.3V, ANALOG SUPPLY
VSSC, CLOCK SUPPLY GROUND
VSSA, ANALOG SUPPLY GROUND
VSSA SHIELD, ANALOG SUPPLY GROUND SHIELD
Figure 4. Digital LVDS Clock Supply Pins (Top View)
Figure 2. Analog Supply Pins (Top View)
1
2
3
4
5
6
7
8
9 10 11 12 13 14
1
2
3
4
5
6
7
8
9
10 11 12 13 14
A
B
C
D
E
F
A
B
C
D
E
F
DACCLK_N
DACCLK_P
G
H
J
AD9737A
DCO_P/_N
DCI_P/_N
G
H
J
AD9737A/AD9739A
K
L
DB1[0:10]P
DB1[0:10]N
DB0[0:10]P
DB0[0:10]N
M
N
P
K
L
M
N
P
DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)
Figure 5. AD9737A Digital LVDS Input, Clock I/O (Top View)
VDD, 1.8V, DIGITAL SUPPLY
VSS DIGITAL SUPPLY GROUND
VDD33, 3.3V DIGITAL SUPPLY
1
2
3
4
5
6
7
8
9 10 11 12 13 14
A
B
C
D
E
F
Figure 3. Digital Supply Pins (Top View)
DACCLK_N
DACCLK_P
G
H
J
AD9739A
DCO_P/_N
DCI_P/_N
K
L
DB1[0:13]P
DB1[0:13]N
DB0[0:13]P
DB0[0:13]N
M
N
P
DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)
Figure 6. AD9739A Digital LVDS Input, Clock I/O (Top View)
Rev. C | Page 9 of 64
AD9737A/AD9739A
Data Sheet
1
2
3
4
5
6
7
8
9
10 11 12 13 14
A
B
C
D
E
F
I120
VREF
IRQ
CS
RESET
SDIO
SDO
G
H
J
AD9737A
SCLK
K
L
M
N
P
Figure 7. AD9737A Analog I/O and SPI Control Pins (Top View)
Table 7. AD9737A Pin Function Descriptions
Pin No.
Mnemonic
Description
C1, C2, D1, D2, E1, E2, E3, E4
A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4,
C5, D4, D5
VDDC
VSSC
1.8 V Clock Supply Input.
Clock Supply Ground.
A10, A11, B10, B11, C10, C11, D10, D11
A12, A13, B12, B13, C12, C13, D12, D13,
VDDA
VSSA
3.3 V Analog Supply Input.
Analog Supply Ground.
A6, A9, B6, B9, C6, C9, D6, D9, E11, E12,
E13, E14, F1, F2, F3, F4, F11, F12
VSSA Shield
Analog Supply Ground Shield. Tie to VSSA at the DAC.
A14
NC
Do not connect to this pin.
A7, B7, C7, D7
A8, B8, C8, D8
B14
IOUTN
IOUTP
I120
DAC Negative Current Output Source.
DAC Positive Current Output Source.
Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ
resistor to generate a 120 µA reference current.
C14
VREF
Voltage Reference Input/Output. Decouple to VSSA with a 1 nF
capacitor.
D14
C3, D3
F13
NC
Factory Test Pin. Do not connect to this pin.
Negative/Positive DAC Clock Input (DACCLK).
Interrupt Request Open Drain Output. Active high. Pull up to
VDD33 with a 10 kΩ resistor.
DACCLK_N/DACCLK_P
IRQ
F14
G13
RESET
CS
Reset Input. Active high. Tie to VSS if unused.
Serial Port Enable Input.
G14
H13
H14
SDIO
SCLK
SDO
Serial Port Data Input/Output.
Serial Port Clock Input.
Serial Port Data Output.
J3, J4, J11, J12
G1, G2, G3, G4, G11, G12
H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS
VDD33
VDD
3.3 V Digital Supply Input.
1.8 V Digital Supply Input.
Digital Supply Ground.
J1, J2
NC
Differential resistor of 200 Ω exists between J1 and J2. Do not
connect to this pin.
K1, K2
NC
Differential resistor of 100 Ω exists between K1 and K2. Do not
connect to this pin.
J13, J14
K13, K14
DCO_P/DCO_N
DCI_P/DCI_N
Positive/Negative Data Clock Output (DCO).
Positive/Negative Data Clock Input (DCI).
Rev.C | Page 10 of 64
Data Sheet
AD9737A/AD9739A
Pin No.
L1, M1
L2, M2
Mnemonic
Description
NC, NC
NC, NC
NC, NC
Do not connect to this pin.
Do not connect to this pin.
Do not connect to this pin.
L3, M3
L4, M4
L5, M5
L6, M6
L7, M7
L8, M8
L9, M9
L10, M10
L11, M11
L12, M12
L13, M13
L14, M14
N1, P1
DB1[0]P/DB1[0]N
DB1[1]P/DB1[1]N
DB1[2]P/DB1[2]N
DB1[3]P/DB1[3]N
DB1[4]P/DB1[4]N
DB1[5]P/DB1[5]N
DB1[6]P/DB1[6]N
DB1[7]P/DB1[7]N
DB1[8]P/DB1[8]N
DB1[9]P/DB1[9]N
DB1[10]P/DB1[10]N
NC, NC
Port 1 Positive/Negative Data Input Bit 0.
Port 1 Positive/Negative Data Input Bit 1.
Port 1 Positive/Negative Data Input Bit 2.
Port 1 Positive/Negative Data Input Bit 3.
Port 1 Positive/Negative Data Input Bit 4.
Port 1 Positive/Negative Data Input Bit 5.
Port 1 Positive/Negative Data Input Bit 6.
Port 1 Positive/Negative Data Input Bit 7.
Port 1 Positive/Negative Data Input Bit 8.
Port 1 Positive/Negative Data Input Bit 9.
Port 1 Positive/Negative Data Input Bit 10.
Do not connect to this pin.
N2, P2
NC, NC
Do not connect to this pin.
N3, P3
NC, NC
Do not connect to this pin.
N4, P4
N5, P5
N6, P6
N7, P7
N8, P8
N9, P9
N10, P10
N11, P11
N12, P12
N13, P13
N14, P14
DB0[0]P/DB0[0]N
DB0[1]P/DB0[1]N
DB0[2]P/DB0[2]N
DB0[3]P/DB0[3]N
DB0[4]P/DB0[4]N
DB0[5]P/DB0[5]N
DB0[6]P/DB0[6]N
DB0[7]P/DB0[7]N
DB0[8]P/DB0[8]N
DB0[9]P/DB0[9]N
DB0[10]P/DB0[10]N
Port 0 Positive/Negative Data Input Bit 0.
Port 0 Positive/Negative Data Input Bit 1.
Port 0 Positive/Negative Data Input Bit 2.
Port 0 Positive/Negative Data Input Bit 3.
Port 0 Positive/Negative Data Input Bit 4.
Port 0 Positive/Negative Data Input Bit 5.
Port 0 Positive/Negative Data Input Bit 6.
Port 0 Positive/Negative Data Input Bit 7.
Port 0 Positive/Negative Data Input Bit 8.
Port 0 Positive/Negative Data Input Bit 9.
Port 0 Positive/Negative Data Input Bit 10.
Rev. C | Page 11 of 64
AD9737A/AD9739A
Data Sheet
1
2
3
4
5
6
7
8
9
10 11 12 13 14
A
B
C
D
E
F
I120
VREF
IRQ
CS
RESET
SDIO
SDO
G
H
J
AD9739A
SCLK
K
L
M
N
P
Figure 8. AD9739A Analog I/O and SPI Control Pins (Top View)
Table 8. AD9739A Pin Function Descriptions
Pin No.
Mnemonic
Description
C1, C2, D1, D2, E1, E2, E3, E4
A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4,
C5, D4, D5
VDDC
VSSC
1.8 V Clock Supply Input.
Clock Supply Ground.
A10, A11, B10, B11, C10, C11, D10, D11
A12, A13, B12, B13, C12, C13, D12, D13,
VDDA
VSSA
3.3 V Analog Supply Input.
Analog Supply Ground.
A6, A9, B6, B9, C6, C9, D6, D9, E11, E12,
E13, E14, F1, F2, F3, F4, F11, F12
VSSA Shield
Analog Supply Ground Shield. Tie to VSSA at the DAC.
A14
NC
Do not connect to this pin.
A7, B7, C7, D7
A8, B8, C8, D8
B14
IOUTN
IOUTP
I120
DAC Negative Current Output Source.
DAC Positive Current Output Source.
Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ
resistor to generate a 120 μA reference current.
C14
VREF
Voltage Reference Input/Output. Decouple to VSSA with a 1 nF
capacitor.
D14
C3, D3
F13
NC
Factory Test Pin. Do not connect to this pin.
Negative/Positive DAC Clock Input (DACCLK).
Interrupt Request Open Drain Output. Active high. Pull up to
VDD33 with a 10 kΩ resistor.
DACCLK_N/DACCLK_P
IRQ
F14
G13
RESET
CS
Reset Input. Active high. Tie to VSS if unused.
Serial Port Enable Input.
G14
H13
H14
SDIO
SCLK
SDO
Serial Port Data Input/Output.
Serial Port Clock Input.
Serial Port Data Output.
J3, J4, J11, J12
G1, G2, G3, G4, G11, G12
H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS
VDD33
VDD
3.3 V Digital Supply Input.
1.8 V Digital Supply Input.
Digital Supply Ground.
J1, J2
NC
Differential resistor of 200 Ω exists between J1 and J2. Do not
connect to this pin.
K1, K2
NC
Differential resistor of 100 Ω exists between K1 and K2. Do not
connect to this pin.
J13, J14
K13, K14
DCO_P/DCO_N
DCI_P/DCI_N
Positive/Negative Data Clock Output (DCO).
Positive/Negative Data Clock Input (DCI).
Rev. C | Page 12 of 64
Data Sheet
AD9737A/AD9739A
Pin No.
L1, M1
L2, M2
L3, M3
L4, M4
L5, M5
L6, M6
L7, M7
L8, M8
Mnemonic
Description
DB1[0]P/DB1[0]N
DB1[1]P/DB1[1]N
DB1[2]P/DB1[2]N
DB1[3]P/DB1[3]N
DB1[4]P/DB1[4]N
DB1[5]P/DB1[5]N
DB1[6]P/DB1[6]N
DB1[7]P/DB1[7]N
DB1[8]P/DB1[8]N
DB1[9]P/DB1[9]N
DB1[10]P/DB1[10]N
DB1[11]P/DB1[11]N
DB1[12]P/DB1[12]N
DB1[13]P/DB1[13]N
DB0[0]P/DB0[0]N
DB0[1]P/DB0[1]N
DB0[2]P/DB0[2]N
DB0[3]P/DB0[3]N
DB0[4]P/DB0[4]N
DB0[5]P/DB0[5]N
DB0[6]P/DB0[6]N
DB0[7]P/DB0[7]N
DB0[8]P/DB0[8]N
DB0[9]P/DB0[9]N
DB0[10]P/DB0[10]N
DB0[11]P/DB0[11]N
DB0[12]P/DB0[12]N
DB0[13]P/DB0[13]N
Port 1 Positive/Negative Data Input Bit 0.
Port 1 Positive/Negative Data Input Bit 1.
Port 1 Positive/Negative Data Input Bit 2.
Port 1 Positive/Negative Data Input Bit 3.
Port 1 Positive/Negative Data Input Bit 4.
Port 1 Positive/Negative Data Input Bit 5.
Port 1 Positive/Negative Data Input Bit 6.
Port 1 Positive/Negative Data Input Bit 7.
Port 1 Positive/Negative Data Input Bit 8.
Port 1 Positive/Negative Data Input Bit 9.
Port 1 Positive/Negative Data Input Bit 10.
Port 1 Positive/Negative Data Input Bit 11.
Port 1 Positive/Negative Data Input Bit 12.
Port 1 Positive/Negative Data Input Bit 13.
Port 0 Positive/Negative Data Input Bit 0.
Port 0 Positive/Negative Data Input Bit 1.
Port 0 Positive/Negative Data Input Bit 2.
Port 0 Positive/Negative Data Input Bit 3.
Port 0 Positive/Negative Data Input Bit 4.
Port 0 Positive/Negative Data Input Bit 5.
Port 0 Positive/Negative Data Input Bit 6.
Port 0 Positive/Negative Data Input Bit 7.
Port 0 Positive/Negative Data Input Bit 8.
Port 0 Positive/Negative Data Input Bit 9.
Port 0 Positive/Negative Data Input Bit 10.
Port 0 Positive/Negative Data Input Bit 11.
Port 0 Positive/Negative Data Input Bit 12.
Port 0 Positive/Negative Data Input Bit 13.
L9, M9
L10, M10
L11, M11
L12, M12
L13, M13
L14, M14
N1, P1
N2, P2
N3, P3
N4, P4
N5, P5
N6, P6
N7, P7
N8, P8
N9, P9
N10, P10
N11, P11
N12, P12
N13, P13
N14, P14
Rev. C | Page 13 of 64
AD9737A/AD9739A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS—AD9737A
STATIC LINEARITY
IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
0.3
0.2
0.25
0.20
0.15
0.10
0.1
0.05
0
0
–0.1
–0.2
–0.3
–0.05
–0.10
–0.15
–0.20
–0.25
–0.4
0
0
0
256
512
768
1024
1280
1536
1792
1792
1792
2048
2048
2048
0
256
512
768
1024
1280
1536
1792
2048
CODE
CODE
Figure 9. Typical INL, 20 mA at 25°C
Figure 12. Typical DNL, 10 mA at 25°C
0.4
0.3
0.6
0.5
0.4
0.3
0.2
0.1
0.2
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.1
–0.2
–0.3
0
256
512
768
1024
1280
1536
1792
2048
256
512
768
1024
1280
1536
CODE
CODE
Figure 10. Typical DNL, 20 mA at 25°C
Figure 13. Typical INL, 30 mA at 25°C
0.25
0.2
0.1
0.20
0.15
0.10
0.05
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.05
–0.10
–0.15
–0.20
–0.25
0
256
512
768
1024
1280
1536
1792
2048
256
512
768
1024
1280
1536
CODE
CODE
Figure 14. Typical DNL, 30 mA at 25°C
Figure 11. Typical INL, 10 mA at 25°C
Rev.C | Page 14 of 64
Data Sheet
AD9737A/AD9739A
AC (NORMAL MODE)
IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
120
100
80
1.2GSPS
1.6GSPS
2.0GSPS
2.4GSPS
60
40
20
0
0
200
400
600
800
1000
1200
1400
START 20MHz
STOP 2.4GHz
fOUT (MHz)
VBW 20kHz
Figure 15. Single Tone Spectrum at fOUT = 91 MHz, fDAC = 2.4 GSPS
Figure 18. IMD vs. fOUT over fDAC
–150
–152
–154
–156
–158
–160
–162
–164
–166
–168
–170
1.2GSPS
2.4GSPS
START 20MHz
STOP 2.4GHz
0
200
400
600
800
1000
1200
fOUT (MHz)
VBW 20kHz
Figure 19. Single-Tone NSD over fOUT
Figure 16. Single-Tone Spectrum at fOUT = 1091 MHz, fDAC = 2.4 GSPS
–150
–152
90
80
–154
–156
–158
–160
–162
–164
–166
–168
–170
1.2GSPS
70
60
50
40
30
20
10
0
2.4GSPS
1.2GSPS
1.6GSPS
2.0GSPS
2.4GSPS
0
200
400
600
800
1000
1200
0
200
400
600
fOUT (MHz)
800
1000
1200
fOUT (MHz)
Figure 20. Eight-Tone NSD over fOUT
Figure 17. SFDR vs. fOUT over fDAC
Rev.C | Page 15 of 64
AD9737A/AD9739A
Data Sheet
fDAC = 2 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
90
85
100
95
90
85
80
75
70
65
60
55
50
45
40
–6dBFS
0dBFS
80
75
70
65
60
55
50
45
40
35
30
–6dBFS
–3dBFS
–3dBFS
0dBFS
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
0
0
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
Figure 21. SFDR vs. fOUT over Digital Full Scale
Figure 24. IMD vs. fOUT over Digital Full Scale
90
80
90
85
80
75
70
65
60
55
50
45
40
35
30
–6dBFS
–3dBFS
30mA FS
70
60
50
40
30
20mA FS
10mA FS
0dBFS
0
200
400
600
800
1000
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
fOUT (MHz)
Figure 22. SFDR for Second Harmonic vs. fOUT over Digital Full Scale
Figure 25. SFDR vs. fOUT over DAC IOUTFS
90
100
95
90
85
80
75
70
65
60
55
50
45
–6dBFS
80
20mA FS
30mA FS
70
–3dBFS
60
0dBFS
10mA FS
50
40
30
40
0
200
400
600
800
1000
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
fOUT (MHz)
Figure 23. SFDR for Third Harmonic vs. fOUT over Digital Full Scale
Figure 26. IMD vs. fOUT over DAC IOUTFS
Rev.C | Page 16 of 64
Data Sheet
AD9737A/AD9739A
AC (MIX-MODE)
fDAC = 2.1 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
90
85
80
75
70
65
60
55
50
45
40
35
30
–150
–152
–154
–156
–158
–160
–162
–164
–166
–168
–170
+85°C
+25°C
+85°C
–40°C
+25°C
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
Figure 30. Eight-Tone NSD vs. fOUT over Temperature
Figure 27. SFDR vs. fOUT over Temperature
100
95
90
85
80
75
70
65
60
55
50
45
–82.2dBc –81.6dBc –81.7dBc –81.1dBc –80.5dBc –13.2dBm –79.7dBc –80.2dBc –80.8dBc –81.4dBc –81.5dBc
–35
+85°C
+25°C
–45
–55
–65
–40°C
–75
–85
–95
–105
–115
40
CENTER 350MHz
#RES BW 30kHz
VBW 3kHz
SPAN 54.68MHz
SWEEP 1.509s
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
CARRIER POWER –13.167dBm/3.84MHz
ACP-IBW
UPPER
LOWER
OFFSET FREQ INTEG BW
dBc
dBm
dBc dBm FILTER
5.000MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
3.840MHz –80.51 –93.67 –79.73 –92.90 ON
3.840MHz –81.11 –94.27 –80.21 –93.38 ON
3.840MHz –81.67 –94.84 –80.85 –94.01 ON
3.840MHz –81.61 –94.77 –81.41 –94.58 ON
3.840MHz –82.19 –95.35 –81.46 –94.63 ON
Figure 31. Single-Carrier WCDMA at 350 MHz, fDAC = 2457.6 MSPS
Figure 28. IMD vs. fOUT over Temperature
–150
–152
–154
–156
–158
–160
–162
–164
–166
–168
–170
–50
–55
–60
–65
–70
+85°C
FIRST ADJ CH
–75
+25°C
–80
–85
–90
SECOND ADJ CH
FIFTH ADJ CH
0
200
400
600
800
1000
1200
1400
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
fOUT (MHz)
Figure 32. Single-Carrier WCDMA ACLR vs. fOUT at 2457.6 MSPS
Figure 29. Single-Tone NSD vs. fOUT over Temperature
Rev.C | Page 17 of 64
AD9737A/AD9739A
Data Sheet
fDAC = 2.1 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
100
90
80
70
60
50
40
30
1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
START 20MHz
#RES BW 20kHz
STOP 2.4GHz
SWEEP 7.174s (601pts)
fOUT (MHz)
VBW 20kHz
Figure 33. Single-Tone Spectrum at fOUT = 2.31 GHz, fDAC = 2.4 GSPS
Figure 36. IMD in Mix-Mode vs. fOUT at 2.4 GSPS
–71.9dBc –72.3dBc –71.8dBc –69.9dBc –68.8dBc –19.5dBm –69.8dBc –71.1dBc –71.8dBc –72.2dBc –72.7dBc
–35
–45
–55
–65
–75
–85
–95
–105
–115
CENTER 2.108MHz
#RES BW 30kHz
VBW 3kHz
SPAN 54.68MHz
SWEEP 1.509s
START 20MHz
#RES BW 20kHz
STOP 2.4GHz
SWEEP 7.174s (601pts)
CARRIER POWER –19.526dBm/3.84MHz
ACP-IBW
UPPER
VBW 20kHz
LOWER
OFFSET FREQ INTEG BW
dBc
dBm
dBc dBm FILTER
5.000MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
3.840MHz –69.82 –88.34 –69.84 –89.36 ON
3.840MHz –69.93 –89.46 –71.15 –90.67 ON
3.840MHz –71.77 –91.29 –71.75 –91.28 ON
3.840MHz –72.26 –91.79 –72.19 –91.71 ON
3.840MHz –71.90 –91.42 –72.70 –92.22 ON
Figure 37. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz,
Figure 34. Single-Tone Spectrum at fOUT = 1.31 GHz, fDAC = 2.4 GSPS
fDAC = 2457.6 MSPS (Second Nyquist Zone)
80
75
70
65
60
55
50
45
40
35
30
25
20
15
–50
SECOND NYQUIST ZONE
FIRST ADJ CH
THIRD NYQUIST ZONE
–55
–60
–65
–70
–75
–80
–85
–90
SECOND ADJ CH
THIRD ADJ CH
10
1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400
fOUT (MHz)
fOUT (MHz)
Figure 38. Single-Carrier WCDMA ACLR vs. fOUT, fDAC = 2457.6 MSPS
Figure 35. SFDR in Mix-mode vs. fOUT at 2.4 GSPS
Rev.C | Page 18 of 64
Data Sheet
AD9737A/AD9739A
fDAC = 2.1 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
–58.0dBc
–58.0dBc
–37.4dBm
–37.1dBm
–58.2dBc
–58.3dBc
–58.2dBc
–65.8dBc –65.8dBc –65.8dBc –65.7dBc –65.6dBc –29.2dBm –65.6dBc –65.8dBc –66.0dBc –66.1dBc –66.1dBc
–58.0dBc –57.9dBc
–58.0dBc
–37.1dBm
–36.9dBm
–58.1dBc
–58.3dBc
–45
–55
–60
–70
–65
–80
–75
–90
–85
–100
–110
–120
–130
–140
–95
–105
–115
–125
CENTER 2.808MHz
#RES BW 30kHz
VBW 3kHz
SPAN 54.68MHz
SWEEP 1.509s
CENTER 2.808MHz
#RES BW 30kHz
VBW 3kHz
SPAN 69.68MHz
SWEEP 1.922s
CARRIER POWER –26.161dBm/3.84MHz
ACP-IBW
UPPER
LOWER
CARRIER POWER –31.097dBm/15.36MHz ACP-IBW
OFFSET FREQ INTEG BW
dBc
dBm
dBc dBm FILTER
5.000MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
3.840MHz –65.65 –94.81 –65.56 –94.72 ON
3.840MHz –65.70 –94.86 –65.82 –94.98 ON
3.840MHz –65.81 –94.97 –65.98 –95.14 ON
3.840MHz –65.84 –95.00 –66.06 –95.22 ON
3.840MHz –65.84 –95.00 –66.14 –95.31 ON
LOWER UPPER
OFFSET FREQ INTEG BW
dBc dBm dBc dBm FILTER
5.000MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
3.840MHz –58.05 –95.11 –58.20 –95.26 ON
3.840MHz –57.95 –95.02 –58.15 –95.21 ON
3.840MHz –57.95 –95.01 –58.26 –95.32 ON
3.840MHz –57.97 –95.04 –58.33 –95.39 ON
3.840MHz –58.05 –95.11 –58.21 –95.27 ON
Figure 41. Typical Four-Carrier WCDMA ACLR Performance at 2.8 GHz,
fDAC = 2457.6 MSPS (Third Nyquist Zone)
Figure 39. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz,
DAC = 2457.6 MSPS (Third Nyquist Zone)
f
–65.2dBc
–64.9dBc
–27.6dBm
–27.3dBm
–64.9dBc
–65.2dBc
–66.1dBc
–65.6dBc
–65.1dBc
–65.4dBc
–27.6dBm
–27.4dBm
–64.3dBc
–65.7dBc
–50
–60
–70
–80
–90
–100
–110
–120
–130
CENTER 2.108MHz
#RES BW 30kHz
VBW 3kHz
SPAN 69.68MHz
SWEEP 1.922s
CARRIER POWER –21.446dBm/15.36MHz ACP-IBW
LOWER UPPER
dBc dBm dBc dBm FILTER
OFFSET FREQ INTEG BW
5.000MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
3.840MHz –65.42 –92.72 –64.93 –92.23 ON
3.840MHz –64.93 –92.23 –64.26 –91.56 ON
3.840MHz –65.12 –92.42 –65.21 –92.50 ON
3.840MHz –65.24 –92.53 –65.74 –93.04 ON
3.840MHz –65.61 –92.91 –66.13 –93.42 ON
Figure 40. Typical Four-Carrier WCDMA ACLR Performance at 2.1 GHz,
DAC = 2457.6 MSPS (Second Nyquist Zone)
f
Rev.C | Page 19 of 64
AD9737A/AD9739A
Data Sheet
ONE-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–78.4dBc
–78.6dBc
–78.4dBc
–79.3dBc
–10.2dBm
–79.9dBc
–79.0dBc
–78.7dBc
–78.7dBc
–30
–40
–30
–40
1
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
5Δ1
–100
–110
–100
–110
2Δ1
3Δ1
4Δ1
CENTER 200MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 3kHz
VBW 2kHz
CARRIER POWER –10.226dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
OFFSET FREQ INTEG BW
dBc dBm
–58.34 –68.57 –57.47 –67.70 OFF
1
2
3
4
5
N
1
1
1
1
1
f
f
f
f
f
200.10MHz
–10.238dBm BAND POWER 6MHz
–10.238dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
Δ1
(Δ) 199.50MHz (Δ) –74.467dB
(Δ) 399.95MHz (Δ) –77.224dB
(Δ) 599.45MHz (Δ) –78.437dB
(Δ) 413.25MHz (Δ) –67.413dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –74.467dB
(Δ) –77.224dB
(Δ) –78.437dB
(Δ) –67.413dB
5.250MHz –79.27 –89.50 –79.87 –90.10 OFF
6.000MHz –78.44 –88.66 –78.96 –89.19 OFF
6.000MHz –78.59 –88.82 –78.69 –88.92 OFF
6.000MHz –78.41 –88.63 –78.68 –88.90 OFF
Figure 42. Low Band Wideband ACLR
Figure 45. Low Band Narrow-Band ACLR
–76.0dBc
–75.0dBc
–74.5dBc
–74.0dBc
–12.1dBm
–74.1dBc
–74.7dBc
–78.9dBc
–75.3dBc
–30
–40
–30
–40
1
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
5Δ1
–100
–110
4Δ1
3Δ1
2Δ1
CENTER 550MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 3kHz
VBW 2kHz
CARRIER POWER –12.104dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
OFFSET FREQ INTEG BW
dBc dBm
–59.37 –71.48 –60.92 –73.03 OFF
1
2
3
4
5
N
1
1
1
1
1
f
f
f
f
f
550.65MHz
–11.538dBm BAND POWER 6MHz
–11.538dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
Δ1
(Δ) –487.35MHz (Δ) –74.421dB
(Δ) 125.40MHz (Δ) –76.294dB
(Δ) 253.65MHz (Δ) –68.472dB
(Δ) 62.70MHz (Δ) –66.156dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –74.399dB
(Δ) –74.344dB
(Δ) –68.472dB
(Δ) –66.197dB
5.250MHz –74.02 –86.12 –74.14 –86.25 OFF
6.000MHz –74.53 –86.63 –74.68 –86.79 OFF
6.000MHz –75.00 –87.11 –74.91 –87.01 OFF
6.000MHz –75.97 –88.08 –75.34 –87.44 OFF
Figure 46. Mid Band Narrow-Band ACLR
Figure 43. Mid Band Wideband ACLR
–71.9dBc
–70.9dBc
–70.0dBc
–69.0dBc
–13.6dBm
–69.4dBc
–70.5dBc
–71.0dBc
–71.7dBc
–30
–40
–30
–40
1
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
2Δ1
–100
–110
5Δ1
3Δ1
–100
–110
6Δ1
4Δ1
CENTER 950MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
STOP 1GHz
VBW 2kHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
CARRIER POWER –13.589dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
WIDTH VALUE
LOWER
UPPER
dBc dBm FILTER
MKR MODE TRC SCL
X
Y
FUNCTION
OFFSET FREQ INTEG BW
dBc dBm
–57.84 –71.43 –61.30 –74.89 OFF
1
2
3
4
5
6
N
1
1
1
1
1
1
f
f
f
f
f
f
948.70MHz
–14.418dBm BAND POWER 6MHz
–14.446dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
Δ1
Δ1
(Δ) –393.30MHz
(Δ) –553.85MHz
(Δ) –612.75MHz
(Δ) –335.35MHz
(Δ) –57.95MHz
(Δ) –60.856dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –60.856dB
(Δ) –66.013dB
(Δ) –68.697dB
(Δ) –63.533dB
(Δ) –68.162dB
5.250MHz –69.02 –82.61 –69.39 –82.98 OFF
6.000MHz –70.01 –83.60 –70.50 –84.09 OFF
6.000MHz –70.89 –84.48 –71.02 –84.61 OFF
6.000MHz –71.94 –85.53 –71.75 –85.34 OFF
(Δ) –66.000dB
(Δ) –68.751dB
(Δ) –63.533dB
(Δ) –66.162dB
Figure 47. High Band Narrow-Band ACLR
Figure 44. High Band Wideband ACLR
Rev.C | Page 20 of 64
Data Sheet
AD9737A/AD9739A
FOUR-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–30
–40
–40
–50
–17.9dBc
1
–73.7dBc
–53.2dBc
0dBc
0.1dBc
–0.6dBc
–73.3dBc
–72.9dBc
–73.5dBc
–60
–50
–70
–60
–80
–70
–90
–80
–100
–110
–120
–90
5Δ1
–100
–110
2Δ1
3Δ1
4Δ1
CENTER 218MHz
#RES BW 30kHz
VBW 3kHz
SPAN 54MHz
SWEEP 1.49s
START 50MHz
#RES BW 20kHz
VBW 2kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
CARRIER POWER –17.892dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
dBc dBm
UPPER
dBc dBm FILTER
1
2
3
4
5
N
1
1
1
1
1
f
f
f
f
f
200.10MHz
–18.419dBm BAND POWER 6MHz
–18.419dBm
OFFSET FREQ INTEG BW
Δ1
Δ1
Δ1
Δ1
(Δ) 221.35MHz (Δ) –69.252dB
(Δ) 431.30MHz (Δ) –71.282dB
(Δ) 651.70MHz (Δ) –72.100dB
(Δ) 413.25MHz (Δ) –59.520dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –69.277dB
(Δ) –71.485dB
(Δ) –72.343dB
(Δ) –59.518dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750kHz
5.25kHz
6MHz
–10.82 –28.71 –58.82 –76.71 OFF
–0.566 –18.46 –73.28 –91.17 OFF
–0.123 –17.77 –72.92 –90.81 OFF
–0.028 –17.86 –73.50 –91.39 OFF
–53.18 –71.07 –73.74 –91.63 OFF
6MHz
6MHz
Figure 48. Low Band Wideband ACLR
Figure 51. Low Band Narrow-Band ACLR (Worse Side)
–40
–50
–30
–40
–19.5dBc
1
–70.6dBc
–69.7dBc
–68.5dBc –68.3dBc
–0.5dBc
–0.2dBc
0dBc
–54.2dBc
–60
–50
–70
–60
–80
–70
–90
–80
–100
–110
–120
–90
5Δ1
–100
–110
4Δ1
3Δ1
2Δ1
CENTER 550MHz
#RES BW 30kHz
VBW 3kHz
SPAN 54MHz
SWEEP 1.49s
START 50MHz
VBW 2kHz
STOP 1GHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
CARRIER POWER –17.892dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
dBc dBm
UPPER
dBc dBm FILTER
OFFSET FREQ INTEG BW
1
2
3
4
5
N
1
1
1
1
1
f
f
f
f
f
549.70MHz
–19.885dBm BAND POWER 6MHz
–19.885dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750kHz
5.25kHz
6MHz
–58.29 –77.82 –10.49 –30.02 OFF
–68.28 –87.81 –0.526 –20.06 OFF
–68.47 –88.00 –0.160 –19.69 OFF
–69.72 –89.25 –0.024 –19.56 OFF
–70.64 –90.17 –54.18 –73.72 OFF
Δ1
Δ1
Δ1
Δ1
(Δ) –486.40MHz (Δ) –70.252dB
(Δ) 126.35MHz (Δ) –69.535dB
(Δ) 228.00MHz (Δ) –67.793dB
(Δ) 63.65MHz (Δ) –58.085dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –70.252dB
(Δ) –69.581dB
(Δ) –67.793dB
(Δ) –58.085dB
6MHz
6MHz
Figure 49. Mid Band Wideband ACLR
Figure 52. Mid Band Narrow-Band ACLR (Worse Side)
–40
–50
–21.5dBm
–40
–50
1
–66.6dBc
–65.4dBc
–64.3dBc
–63.9dBc
–0.4dBc
–0.2dBc
0.1dBc
–53.1dBc
–60
–60
–70
–70
–80
–80
–90
–90
5Δ1
–100
–110
–120
–100
–110
–120
2Δ1
6Δ1
3Δ1
4Δ1
CENTER 950MHz
#RES BW 30kHz
VBW 3kHz
SPAN 54MHz
SWEEP 1.49s
START 50MHz
VBW 2kHz
STOP 1GHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
CARRIER POWER –21.510dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
dBc dBm
UPPER
dBc dBm FILTER
OFFSET FREQ INTEG BW
1
2
3
4
5
6
N
1
1
1
1
1
1
f
f
f
f
f
f
950.60MHz
–21.631dBm BAND POWER 6MHz
–21.676dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750kHz
5.25kHz
6MHz
–59.52 –81.03 –11.04 –32.55 OFF
–63.90 –85.41 –0.437 –21.95 OFF
–64.29 –85.80 –0.172 –21.68 OFF
–65.41 –86.92 –0.098 –21.41 OFF
–66.57 –88.08 –53.11 –74.62 OFF
Δ1
Δ1
Δ1
Δ1
Δ1
(Δ) –415.15MHz (Δ) –62.206dB
(Δ) –529.15MHz (Δ) –65.730dB
(Δ) –610.85MHz (Δ) –67.064dB
(Δ) –337.25MHz (Δ) –56.405dB
(Δ) –59.85MHz (Δ) –65.729dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –62.206dB
(Δ) –65.730dB
(Δ) –67.064dB
(Δ) –56.405dB
(Δ) –65.729dB
6MHz
6MHz
Figure 53. High Band Narrow-Band ACLR (Worse Side)
Figure 50. High Band Wideband ACLR
Rev.C | Page 21 of 64
AD9737A/AD9739A
Data Sheet
EIGHT-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–69.1dBc
–69.2dBc
–70.3dBc
–23.3dBc
–0.6dBc
–0.3dBc
–0.2dBc
–40
–50
–40
–50
1
–60
–60
–70
–70
–80
–80
–90
–90
3Δ1
–100
–110
–120
–100
–110
–120
2Δ1
CENTER 200MHz
#RES BW 30kHz
VBW 3kHz
SPAN 42MHz
SWEEP 1.159s
START 50MHz
#RES BW 20kHz
VBW 2kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
FUNCTION FUNCTION
CARRIER POWER –23.288dBm/6MHz
ACP-IBW
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
dBc dBm
UPPER
dBc dBm FILTER
1
2
3
N
Δ1
Δ1
1
1
1
f
f
f
200.10MHz
–22.253dBm BAND POWER 6MHz
–22.253dBm
(Δ) –66.457dB
(Δ) –55.791dB
OFFSET FREQ INTEG BW
(Δ) 235.60MHz (Δ) –66.457dB
(Δ) 431.25MHz (Δ) –55.791dB
BAND POWER 6MHz
BAND POWER 6MHz
3.375MHz
6.375MHz
12.00MHz
18.00MHz
750kHz
5.25MHz
6MHz
–55.24 –78.53 –10.96 –34.25 OFF
–70.28 –93.56 –0.572 –23.86 OFF
–69.23 –92.52 –0.250 –23.54 OFF
–69.11 –92.40 –0.186 –23.47 OFF
6MHz
Figure 54. Low Band Wideband ACLR
Figure 57. Low Band Narrow-Band ACLR (Worse Side)
–40
–50
–40
–50
–23.7dBc
1
–66.8dBc
–66.4dBc
–66.8dBc
0.1dBc
0.3dBc
–0.1dBc
–60
–60
–70
–70
–80
–80
–90
–90
2Δ1
–100
–110
–120
–100
–110
–120
3Δ1
START 50MHz
VBW 2kHz
STOP 1GHz
CENTER 592MHz
#RES BW 30kHz
VBW 3kHz
SPAN 42MHz
SWEEP 1.159s
#RES BW 20kHz
SWEEP 24.1s (1001pts)
FUNCTION FUNCTION
CARRIER POWER –23.676dBm/6MHz
ACP-IBW
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
1
2
3
N
Δ1
Δ1
1
1
1
f
f
f
550.65MHz
–23.586dBm BAND POWER 6MHz
–23.585dBm
(Δ) –54.206dB
(Δ) –66.628dB
OFFSET FREQ INTEG BW
dBc dBm
(Δ) 62.70MHz (Δ) –54.209dB
(Δ) 167.20MHz (Δ) –66.696dB
BAND POWER 6MHz
BAND POWER 6MHz
3.375MHz
6.375MHz
12.00MHz
18.00MHz
750kHz
5.25kHz
6MHz
–10.79 –34.47 –56.23 –79.91 OFF
–0.089 –23.76 –66.75 –90.43 OFF
–0.289 –23.39 –66.45 –90.12 OFF
–0.145 –23.53 –66.78 –90.46 OFF
6MHz
Figure 58. Mid Band Narrow-Band ACLR (Worse Side)
Figure 55. Mid Band Wideband ACLR
–40
–50
–40
–50
–26.4dBm
1
–63.5dBc
–62.7dBc
–62.2dBc
–62.7dBc
–0.4dBc
0.1dBc
0.1dBc
0.2dBc
–60
–60
–70
–70
–80
–80
–90
–90
5Δ1
–100
–110
–120
–100
–110
–120
2Δ1
3Δ1
4Δ1
CENTER 950MHz
#RES BW 30kHz
VBW 3kHz
SPAN 54MHz
SWEEP 1.49s
START 50MHz
#RES BW 20kHz
VBW 2kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
FUNCTION FUNCTION
CARRIER POWER –26.388dBm/6MHz
ACP-IBW
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
dBc dBm
UPPER
dBc dBm FILTER
1
2
3
4
5
N
1
1
1
1
1
f
f
f
f
f
950.60MHz
–26.330dBm BAND POWER 6MHz
–26.330dBm
OFFSET FREQ INTEG BW
Δ1
Δ1
Δ1
Δ1
(Δ) –448.40MHz (Δ) –61.549dB
(Δ) –582.35MHz (Δ) –63.183dB
(Δ) –80.75MHz (Δ) –62.616dB
(Δ) –338.20MHz (Δ) –51.728dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –61.574dB
(Δ) –63.268dB
(Δ) –62.616dB
(Δ) –51.728dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750kHz
5.25kHz
6MHz
–60.71 –87.10 –10.99 –37.38 OFF
–62.67 –89.06 –0.366 –26.75 OFF
–62.21 –88.60 –0.073 –26.31 OFF
–62.68 –89.07 –0.053 –26.33 OFF
–63.49 –89.88 –0.225 –26.16 OFF
6MHz
6MHz
Figure 56. High Band Wideband ACLR
Figure 59. High Band Narrow-Band ACLR
Rev.C | Page 22 of 64
Data Sheet
AD9737A/AD9739A
16-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
0.0dBc
–0.1dBc
–0.2dBc
–0.3dBc
–26.3dBm
–65.2dBc
–63.9dBc
–64.1dBc
–64.1dBc
1
–50
–60
–50
–60
–70
–70
–80
–80
–90
–90
4Δ1
–100
–110
–120
–130
–100
–110
–120
–130
3Δ1
2Δ1
CENTER 160MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 3kHz
VBW 2kHz
CARRIER POWER –25.250dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
OFFSET FREQ INTEG BW
dBc dBm
–10.95 –37.20 –61.30 –87.55 OFF
1
2
3
4
N
1
1
1
1
f
f
f
f
160.20MHz
–26.390dBm BAND POWER 6MHz
–26.391dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
(Δ) 80.75MHz (Δ) –64.811dB
(Δ) 232.75MHz (Δ) –65.150dB
(Δ) 452.20MHz (Δ) –51.688dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –64.927dB
(Δ) –65.369dB
(Δ) –51.688dB
5.250MHz –0.314 –26.56 –65.24 –91.49 OFF
6.000MHz –0.166 –26.42 –63.93 –90.18 OFF
6.000MHz –0.125 –26.38 –64.07 –90.32 OFF
6.000MHz –0.034 –26.28 –64.08 –90.33 OFF
Figure 60. Low Band Wideband ACLR
Figure 63. Low Band Narrow-Band ACLR
0.3dBc
0.3dBc
0.2dBc
–0.2dBc
–27.4dBm
–63.9dBc
–62.8dBc
–63.1dBc
–63.3dBc
1
–50
–60
–45
–55
–70
–65
–80
–75
–90
–85
–100
–110
–120
–130
–95
3Δ1
4Δ1
–105
–115
–125
2Δ1
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
CENTER 640MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 2kHz
VBW 3kHz
CARRIER POWER –27.386dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
1
2
3
4
N
1
1
1
1
f
f
f
f
549.70MHz
–27.503dBm BAND POWER 6MHz
–27.503dBm
OFFSET FREQ INTEG BW
dBc dBm
–11.65 –39.04 –60.24 –87.62 OFF
Δ1
Δ1
Δ1
(Δ) –486.40MHz (Δ) –63.639dB
(Δ) 126.35MHz (Δ) –62.748dB
(Δ) 254.60MHz (Δ) –63.408dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –63.639dB
(Δ) –62.631dB
(Δ) –63.408dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
5.250MHz –0.239 –27.63 –63.87 –91.26 OFF
6.000MHz –0.199 –27.19 –62.76 –90.15 OFF
6.000MHz –0.282 –27.10 –63.08 –90.46 OFF
6.000MHz –0.288 –27.10 –63.33 –90.72 OFF
Figure 61. Mid Band Wideband ACLR
Figure 64. Mid Band Narrow-Band ACLR (Worse Side)
–62.7dBc
–62.1dBc
–61.3dBc
61.8dBc
–28.1dBm
––0.4dBc
–0.3dBc
–0.3dBc
–0.1dBc
1
–50
–60
–45
–55
–70
–65
–80
–75
5Δ1
–90
–85
–100
–110
–120
–130
–95
2Δ1
4Δ1
3Δ1
–105
–115
–125
CENTER 900MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 3kHz
VBW 2kHz
CARRIER POWER –28.112dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
OFFSET FREQ INTEG BW
dBc dBm
–58.27 –86.38 –11.14 –39.25 OFF
1
2
3
4
5
N
1
1
1
1
1
f
f
f
f
f
899.30MHz
–28.493dBm BAND POWER 6MHz
–28.493dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
Δ1
(Δ) –343.90MHz (Δ) –60.066dB
(Δ) –504.45MHz (Δ) –61.070dB
(Δ) –563.35MHz (Δ) –61.014dB
(Δ) –285.95MHz (Δ) –49.417dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –60.066dB
(Δ) –61.070dB
(Δ) –61.014dB
(Δ) –49.417dB
5.250MHz –61.84 –89.95 –0.446 –28.56 OFF
6.000MHz –61.30 –89.42 –0.271 –28.38 OFF
6.000MHz –62.11 –90.22 –0.318 –28.43 OFF
6.000MHz –62.66 –90.77 –0.147 –28.26 OFF
Figure 62. High Band Wideband ACLR
Figure 65. High Band Narrow-Band ACLR
Rev.C | Page 23 of 64
AD9737A/AD9739A
Data Sheet
32-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
0.1dBc
0.1dBc
0.1dBc
–0.3dBc
–28.2dBm
–65.6dBc
–64.1dBc
–64.2dBc
–64.1dBc
–50
1
–50
–60
–70
–80
–90
–60
–70
–80
–90
–100
4Δ1
–100
–110
–120
–130
–110
–120
–130
3Δ1
2Δ1
CENTER 256MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
CARRIER POWER –28.229dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
LOWER
UPPER
dBc dBm FILTER
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
OFFSET FREQ INTEG BW
dBc dBm
–10.80 –39.03 –60.27 –88.50 OFF
5.250MHz –0.336 –28.56 –65.64 –93.87 OFF
1
2
3
4
N
1
1
1
1
f
f
f
f
256.15MHz
–29.852dBm BAND POWER 6MHz
–29.853dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
(Δ) 94.05MHz (Δ) –61.581dB
(Δ) 243.20MHz (Δ) –61.313dB
(Δ) 356.25MHz (Δ) –48.122dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –61.410dB
(Δ) –61.639dB
(Δ) –48.122dB
6.000MHz
6.000MHz
6.000MHz
0.060 –28.17 –64.12 –92.35 OFF
0.081 –28.15 –64.24 –92.47 OFF
0.080 –28.15 –64.12 –92.35 OFF
Figure 66. Low Band Wideband ACLR
Figure 69. Low Band Narrow-Band ACLR
–61.8dBc
–61.7dBc
–61.4dBc
–62.3dBc
–29.5dBm
––0.6dBc
–0.2dBc
–0.4dBc
–0.1dBc
1
–50
–60
–50
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
2Δ1
3Δ1
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
CENTER 550MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
FUNCTION FUNCTION
CARRIER POWER –29.512dBm/6MHz
ACP-IBW
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
dBc dBm
–58.70 –88.21 –10.88 –40.39 OFF
UPPER
1
2
3
N
Δ1
Δ1
1
1
1
f
f
f
550MHz
–29.461dbm BAND POWER 6MHz
–29.461dBm
(Δ) –61.621dB
(Δ) –61.831dB
OFFSET FREQ INTEG BW
dBc dBm FILTER
(Δ) –462.65MHz (Δ) –61.621dB
(Δ) 314.45MHz (Δ) –61.831dB
BAND POWER 6MHz
BAND POWER 6MHz
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
5.250MHz –62.34 –91.85 –0.576 –30.09 OFF
6.000MHz –61.36 –90.87 –0.222 –29.73 OFF
6.000MHz –61.70 –91.21 –0.423 –29.93 OFF
6.000MHz –61.84 –91.36 –0.133 –29.63 OFF
Figure 67. Mid Band Wideband ACLR
Figure 70. Mid Band Narrow-Band ACLR (Worse Side)
–60.0dBc
–59.6dBc
–59.9dBc
–61.4dBc
–32.2dBm
––0.2dBc
0.3dBc
0.3dBc
0.2dBc
–50
–60
–50
–60
1
–70
–70
–80
–80
–90
–90
4Δ1
–100
–110
–120
–130
–100
–110
–120
–130
2Δ1
3Δ1
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
CENTER 800MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
FUNCTION FUNCTION
CARRIER POWER –32.154dBm/6MHz
ACP-IBW
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
dBc dBm
–59.39 –91.54 –10.73 –42.89 OFF
UPPER
1
2
3
4
N
1
1
1
1
f
f
f
f
799.55MHz
–32.396dBm BAND POWER 6MHz
–32.396dBm
OFFSET FREQ INTEG BW
dBc dBm FILTER
Δ1
Δ1
Δ1
(Δ) –138.70MHz (Δ) –57.463dB
(Δ) –601.35MHz (Δ) –58.079dB
(Δ) –187.15MHz (Δ) –45.705dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –57.463dB
(Δ) –58.079dB
(Δ) –45.705dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
5.250MHz –61.40 –93.55 –0.201 –32.35 OFF
6.000MHz –59.86 –92.01 0.300 –31.85 OFF
6.000MHz –59.61 –91.77 0.296 –31.86 OFF
6.000MHz –60.04 –92.20 0.230 –31.92 OFF
Figure 68. High Band Wideband ACLR
Figure 71. High Band Narrow-Band ACLR
Rev.C | Page 24 of 64
Data Sheet
AD9737A/AD9739A
64- AND 128-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
0.1dBc
0.1dBc
0.0dBc
–0.4dBc
–33.4dBm
–60.0dBc
–58.7dBc
–59.0dBc
–58.9dBc
–50
–60
–50
–60
1
–70
–70
–80
–80
–90
–90
2Δ1
–100
–110
–120
–130
–100
–110
–120
–130
3Δ1
CENTER 448MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
STOP 1GHz
VBW 2kHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
CARRIER POWER –33.368dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
LOWER
UPPER
dBc dBm FILTER
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
OFFSET FREQ INTEG BW
dBc dBm
–11.02 –44.39 –59.56 –92.93 OFF
5.250MHz –0.337 –33.74 –60.04 –93.41 OFF
6.000MHz
6.000MHz
6.000MHz
1
2
3
N
Δ1
Δ1
1
1
1
f
f
f
448.05MHz
–33.679dBm BAND POWER 6MHz
–33.680dBm
(Δ) –46.450dB
(Δ) –56.577dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
(Δ) 165.30MHz (Δ) –46.452dB
(Δ) 372.40MHz (Δ) –56.577dB
BAND POWER 6MHz
BAND POWER 6MHz
0.050 –33.32 –58.69 –92.06 OFF
0.064 –33.30 –59.04 –92.40 OFF
0.099 –33.27 –58.86 –92.23 OFF
Figure 72. Low Band Wideband ACLR
Figure 75. 64-Carrier Low Band Narrow-Band ACLR
–58.0dBc
–57.8dBc
–58.4dBc
–59.3dBc
–33.8dBm
––0.4dBc
0.0dBc
0.0dBc
0.0dBc
–50
–60
–50
–60
1
3
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
2Δ1
CENTER 600MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
CARRIER POWER –33.849dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
LOWER
dBc dBm
–58.63 –92.48 –11.06 –44.91 OFF
UPPER
OFFSET FREQ INTEG BW
dBc dBm FILTER
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
1
2
3
N
Δ1
N
1
1
1
f
f
f
599.10MHz
–34.413dBm BAND POWER 6MHz
BAND POWER 6MHz
–36.289dBm BAND POWER 6MHz
–34.413dBm
5.250MHz –59.29 –93.14 –0.380 –34.23 OFF
6.000MHz –58.37 –92.22 –0.004 –33.85 OFF
6.000MHz –57.84 –91.69 –0.012 –33.86 OFF
6.000MHz –58.04 –91.89 0.043 –33.81 OFF
(Δ) –292.60MHz (Δ) –56.033dB
(Δ) –56.033dB
978.15MHz
–36.289dBm
Figure 73. High Band Wideband ACLR
Figure 76. 64-Carrier High Band Narrow-Band ACLR
0.3dBc
0.3dBc
0.4dBc
–0.2dBc
–38.5dBm
–54.3dBc
–53.4dBc
–53.3dBc
–53.1dBc
–50
–60
–50
–60
1
3
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
2Δ1
CENTER 832MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
STOP 1GHz
VBW 2kHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
CARRIER POWER –38.456dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
LOWER
UPPER
dBc dBm FILTER
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
OFFSET FREQ INTEG BW
dBc dBm
–11.07 –49.53 –59.28 –97.73 OFF
5.250MHz –0.210 –38.67 –54.33 –92.79 OFF
6.000MHz
6.000MHz
6.000MHz
1
2
3
N
Δ1
N
1
1
1
f
f
f
69.95MHz
–34.909dBm BAND POWER 6MHz
BAND POWER 6MHz
–38.646dBm BAND POWER 6MHz
–35.909dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
(Δ) 855.00MHz (Δ) –53.920dB
(Δ) –53.920dB
831.85MHz
–38.646dBm
0.353 –38.10 –53.36 –91.82 OFF
0.253 –38.20 –53.35 –91.81 OFF
0.292 –38.16 –53.07 –91.53 OFF
Figure 74. 128-Carrier Low Band Wideband ACLR
Figure 77. 128-Carrier Narrow-Band ACLR
Rev.C | Page 25 of 64
AD9737A/AD9739A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS—AD9739A
STATIC LINEARITY
3.0
1.0
2.5
0.5
2.0
1.5
0
1.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
0
0
0
2048
2048
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 78. Typical INL, 20 mA at 25°C
Figure 81. Typical DNL, 20 mA at −40°C
2.0
1.5
1.0
0.5
0
1.0
0.5
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
–0.5
–1.0
–1.5
–2.0
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 79. Typical DNL, 20 mA at 25°C
Figure 82. Typical INL, 20 mA at 85°C
3.0
2.5
1.0
0.5
2.0
1.5
1.0
0
0.5
–0.5
–1.0
–1.5
–2.0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 80. Typical INL, 20 mA at −40°C
Figure 83. Typical DNL, 20 mA at 85°C
Rev.C | Page 26 of 64
Data Sheet
AD9737A/AD9739A
2.0
1.0
0.5
1.5
1.0
0
0.5
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
0
0
0
2048
2048
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 84. Typical INL, 10 mA at 25°C
Figure 87. Typical DNL, 30 mA at 25°C
1.2
1.0
0.5
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
TOTAL
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
DVDD18
CLKVDD
AVDD
DVDD33
0
250 500 750 1000 1250 1500 1750 2000 2250 2500
fDAC (MHz)
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 85. Typical DNL, 10 mA at 25°C
Figure 88. Power Consumption vs. fDAC at 25°C
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 86. Typical INL, 30 mA at 25°C
Rev.C | Page 27 of 64
AD9737A/AD9739A
Data Sheet
AC (NORMAL MODE)
IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
START 20MHz
STOP 2.4GHz
START 20MHz
STOP 2.4GHz
VBW 10kHz
VBW 10kHz
Figure 89. Single-Tone Spectrum at fOUT = 91 MHz, fDAC = 2.4 GSPS
Figure 92. Single-Tone Spectrum at fOUT = 1091 MHz, fDAC = 2.4 GSPS
80
100
1.2GSPS
1.6GSPS
75
95
1.2GSPS
90
70
65
2.0GSPS
85
80
75
60
1.6GSPS
70
2.4GSPS
55
65
2.0GSPS
2.4GSPS
60
50
45
40
35
30
55
50
45
40
35
30
0
100 200 300 400 500 600 700 800 900 1000 1100 1200
fOUT (MHz)
0
100 200 300 400 500 600 700 800 900 1000 1100 1200
fOUT (MHz)
Figure 90. SFDR vs. fOUT over fDAC
Figure 93. IMD vs. fOUT over fDAC
–150
–152
–154
–156
–158
–160
–162
–164
–166
–168
–170
–160
–161
–162
–163
–164
–165
–166
–167
–168
–169
–170
2.4GSPS
2.4GSPS
1.2GSPS
1.2GSPS
0
100 200 300 400 500 600 700 800 900 1000 1100 1200
fOUT (MHz)
0
100 200 300 400 500 600 700 800 900 1000 1100 1200
fOUT (MHz)
Figure 91. Single-Tone NSD vs. fOUT
Figure 94. Eight-Tone NSD vs. fOUT
Rev.C | Page 28 of 64
Data Sheet
AD9737A/AD9739A
fDAC = 2 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
90
80
70
60
50
40
30
110
100
90
–6dBFS
–6dBFS
–3dBFS
80
70
0dBFS
–3dBFS
60
0dBFS
50
40
30
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
Figure 95. SFDR vs. fOUT over Digital Full Scale
Figure 98. IMD vs. fOUT over Digital Full Scale
90
80
70
60
50
40
30
90
80
70
60
50
40
30
–6dBFS
–6dBFS
–3dBFS
0dBFS
–3dBFS
0dBFS
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
Figure 96. SFDR for Second Harmonic over fOUT vs. Digital Full Scale
Figure 99. SFDR for Third Harmonic over fOUT vs. Digital Full Scale
90
110
100
80
20mA FS
90
80
70
60
50
40
30
30mA FS
10mA FS
70
60
50
40
30
10mA FS
20mA FS
30mA FS
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
Figure 97. SFDR vs. fOUT over DAC IOUTFS
Figure 100. IMD vs. fOUT over DAC IOUTFS
Rev.C | Page 29 of 64
AD9737A/AD9739A
Data Sheet
fDAC = 2 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
90
80
70
60
50
40
30
110
100
90
+85°C
+85°C
–40°C
80
70
+25°C
60
–40°C
+25°C
50
40
30
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
Figure 101. SFDR vs. fOUT over Temperature
Figure 104. IMD vs. fOUT over Temperature
–150
–152
–154
–156
–158
–160
–162
–164
–166
–168
–170
–150
–152
–154
–156
–158
–160
–162
–164
–166
–168
–170
–40°C
–40°C
+85°C
+25°C
+85°C
+25°C
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
0
100 200 300 400 500 600 700 800 900 1000
fOUT (MHz)
Figure 102. Single-Tone NSD vs. fOUT over Temperature
Figure 105. Eight-Tone NSD vs. fOUT over Temperature
–50
–55
–60
–65
–70
–75
–80
–85
–90
FIRST ADJ CH
SECOND ADJ CH
FIFTH ADJ CH
CENTER 350.27MHz
#RES BW 30kHz
SPAN 53.84MHz
SWEEP 174.6ms (601pts)
VBW 300kHz
REF
0
200
400
600
800
1000
1200
1400
FREQ
fOUT (MHz)
RMS RESULTS
CARRIER POWER
–14.54dBm/
OFFSET BW
LOWER
UPPER
(MHz)
5
(MHz) (dBc) (dBm) (dBc) (dBm)
3.84 –79.90 –94.44 –79.03 –93.57
3.84 –80.60 –95.14 –79.36 –94.40
3.84 –80.90 –95.45 –80.73 –95.27
3.84 –80.62 –95.16 –80.97 –95.51
3.84 –80.76 –95.30 –80.95 –95.49
10
3.84MHz
15
20
25
Figure 103. Single-Carrier WCDMA at 350 MHz, fDAC = 2457.6 MSPS
Figure 106. Single-Carrier WCDMA ACLR vs. fOUT at 2457.6 MSPS
Rev.C | Page 30 of 64
Data Sheet
AD9737A/AD9739A
AC (MIX-MODE)
fDAC = 2.4 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
START 20MHz
#RES BW 10kHz
STOP 2.4GHz
SWEEP 28.7s (601pts)
START 20MHz
#RES BW 10kHz
STOP 2.4GHz
SWEEP 28.7s (601pts)
VBW 10kHz
VBW 10kHz
Figure 110. Single-Tone Spectrum in Mix-Mode at fOUT = 1.31 GHz,
DAC = 2.4 GSPS
Figure 107. Single-Tone Spectrum at fOUT = 2.31 GHz, fDAC = 2.4 GSPS
f
90
85
80
75
70
65
60
55
50
45
40
35
30
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400
1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400
fOUT (MHz)
fOUT (MHz)
Figure 111. IMD in Mix-Mode vs. fOUT at 2.4 GSPS
Figure 108. SFDR in Mix-Mode vs. fOUT at 2.4 GSPS
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
SECOND NYQUIST ZONE
THIRD NYQUIST ZONE
FIRST ADJ CH
FIFTH ADJ CH
SECOND ADJ CH
1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686
CENTER 2.10706MHz
#RES VW 30kHz
SPAN 53.84MHz
SWEEP 174.6ms (601pts)
VBW 300kHz
REF
fOUT (MHz)
FREQ
RMS RESULTS
CARRIER POWER
–21.43dBm/
OFFSET BW
LOWER
UPPER
(MHz)
5
(MHz) (dBc) (dBm) (dBc) (dBm)
3.84 –68.99 –90.43 –63.94 –90.37
3.84 –72.09 –93.52 –71.07 –92.50
3.84 –72.86 –94.30 –71.34 –92.77
3.84 –74.34 –95.77 –72.60 –94.03
3.84 –74.77 –96.20 –73.26 –94.70
10
3.84MHz
15
20
25
Figure 109. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz,
fDAC = 2457.6 MSPS (Second Nyquist Zone)
Figure 112. Single-Carrier WCDMA ACLR vs. fOUT at 2457.6 MSPS
Rev.C | Page 31 of 64
AD9737A/AD9739A
Data Sheet
fDAC = 2.4 GSPS, IOUTFS = 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
CENTER 2.807GHz
#RES BW 30kHz
SPAN 53.84MHz
CENTER 2.81271GHz
#RES BW 30kHz
SPAN 63.84MHz
SWEEP 174.6ms (601pts)
SWEEP 207ms (601pts)
VBW 300kHz
REF
VBW 300kHz
REF
FREQ
FREQ
RMS RESULTS
RMS RESULTS
CARRIER POWER
–24.4dBm/
UPPER
OFFSET BW
LOWER
UPPER
OFFSET BW
LOWER
(MHz)
5
(MHz) (dBc) (dBm) (dBc) (dBm)
3.84 –0.42 –28.40 –0.10 –28.07
3.84 –64.32 –92.30 –0.08 –28.06
3.84 –66.03 –94.01 –65.37 –93.34
3.84 –66.27 –94.24 –66.06 –94.03
3.84 –66.82 –94.79 –63.36 –93.34
3.84 –67.16 –95.13 –66.54 –94.51
(MHz)
5
(MHz) (dBc) (dBm) (dBc) (dBm)
3.84 –64.90 –89.30 –63.82 –88.22
3.84 –66.27 –90.67 –65.70 –90.10
3.84 –68.44 –92.84 –66.55 –90.95
3.84 –70.20 –94.60 –68.95 –93.35
3.84 –70.85 –95.25 –70.45 –94.85
CARRIER POWER
–27.98dBm/
3.84MHz
10
10
3.84MHz
15
15
20
20
25
25
30
Figure 113. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz,
DAC = 2457.6 MSPS (Third Nyquist Zone)
Figure 115. Typical Four-Carrier WCDMA ACLR Performance at 2.8 GHz,
fDAC = 2457.6 MSPS (Third Nyquist Zone)
f
CENTER 2.09758GHz
#RES BW 30kHz
SPAN 63.84MHz
SWEEP 207ms (601pts)
VBW 300kHz
REF
FREQ
RMS RESULTS
CARRIER POWER
–25.53dBm/
OFFSET BW
LOWER
UPPER
(MHz)
5
(MHz) (dBc) (dBm) (dBc) (dBm)
3.84
0.22 –25.31
3.84 –66.68 –92.21
0.24 –25.29
0.14 –25.38
10
3.84MHz
15
3.84 –68.01 –93.53 –66.82 –92.35
3.84 –68.61 –94.14 –67.83 –93.36
3.84 –68.87 –94.40 –67.64 –93.17
3.84 –69.21 –94.74 –68.50 –94.03
20
25
30
Figure 114. Typical Four-Carrier WCDMA ACLR Performance at 2.1 GHz,
fDAC = 2457.6 MSPS (Second Nyquist Zone)
Rev.C | Page 32 of 64
Data Sheet
AD9737A/AD9739A
ONE-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
fOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–80.7dBc
–80.7dBc
–80.7dBc
–81.2dBc
–10.2dBm
–81.3Bc
–80.7dBc
–80.7dBc
–80.8dBc
–31
–42
–35
–45
1
–53
–55
–64
–65
–75
–75
–86
–85
–97
–95
5Δ1
–108
–119
4Δ1
–105
–115
2Δ1
3Δ1
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
CENTER 200MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 2kHz
VBW 3kHz
CARRIER POWER –10.190dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
dBc dBm
–59.38 –69.57 –60.16 –70.35 OFF
UPPER
1
2
3
4
5
N
1
1
1
1
1
f
f
f
f
f
200.00MHz
–11.476dBm BAND POWER 6MHz
–11.475dBm
OFFSET FREQ INTEG BW
dBc dBm FILTER
Δ1
Δ1
Δ1
Δ1
(Δ) 199.60MHz (Δ) –77.042dB
(Δ) 400.05MHz (Δ) –76.238dB
(Δ) 597.65MHz (Δ) –74.526dB
(Δ) 413.35MHz (Δ) –75.919dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –77.042dB
(Δ) –76.238dB
(Δ) –74.526dB
(Δ) –75.919dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
5.250MHz –81.23 –91.42 –81.26 –91.45 OFF
6.000MHz –80.71 –90.90 –80.72 –90.91 OFF
6.000MHz –80.72 –90.91 –80.76 –90.95 OFF
6.000MHz –80.73 –90.92 –80.78 –90.97 OFF
Figure 116. Low Band Wideband ACLR
Figure 119. Low Band Narrow-Band ACLR
–78.5dBc
–77.6dBc
–76.3dBc
–75.1Bc
–10.4dBm
–74.4Bc
–75.6dBc
–76.7dBc
–77.7dBc
1
–31
–42
–35
–45
–53
–55
–64
–65
–75
–75
–86
–85
–97
–95
4Δ1
5Δ1
2Δ1
3Δ1
–108
–119
6Δ1
–105
–115
START 50MHz
STOP 1GHz
VBW 2kHz
CENTER 550MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
FUNCTION FUNCTION
CARRIER POWER –10.368dBm/6MHz
ACP-IBW
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
1
2
3
4
5
6
N
1
1
1
1
1
1
f
f
f
f
f
f
549.60MHz
–10.231dBm BAND POWER 6MHz
–10.231dBm
OFFSET FREQ INTEG BW
dBc dBm
–57.91 –68.28 –58.53 –68.90 OFF
Δ1
Δ1
Δ1
Δ1
Δ1
(Δ) –485.35MHz (Δ) –76.444dB
(Δ) 127.40MHz (Δ) –75.649dB
(Δ) 254.70MHz (Δ) –70.658dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –76.425dB
(Δ) –75.626dB
(Δ) –70.658dB
(Δ) –75.824dB
(Δ) –78.118dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
5.250MHz –75.09 –85.46 –74.41 –84.78 OFF
6.000MHz –76.29 –86.65 –75.55 –85.92 OFF
6.000MHz –77.63 –88.00 –76.69 –87.06 OFF
6.000MHz –78.51 –88.88 –77.67 –88.03 OFF
(Δ)
63.75MHz (Δ) –75.836dB
(Δ) 293.65MHz (Δ) –78.054dB
Figure 120. Mid Band Narrow-Band ACLR
Figure 117. Mid Band Wideband ACLR
–76.7dBc
–75.9dBc
–75.3dBc
–72.2Bc
–13.8dBm
–72.1Bc
–73.4dBc
–75.0dBc
–76.3dBc
–30
–40
–31
–42
1
–50
–53
–60
–64
–70
–75
–80
–86
–90
–97
2Δ1
3Δ1
5Δ1
4Δ1
–100
–110
–108
–119
CENTER 980MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
STOP 1GHz
VBW 2kHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
CARRIER POWER –13.798dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
OFFSET FREQ INTEG BW
dBc dBm
–57.81 –71.61 –61.44 –75.24 OFF
1
2
3
4
5
N
1
1
1
1
1
f
f
f
f
f
979.00MHz
–13.703dBm BAND POWER 6MHz
–13.658dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
Δ1
(Δ) –484.40MHz (Δ) –65.548dB
(Δ) –118.65MHz (Δ) –66.990dB
(Δ) –613.60MHz (Δ) –69.044dB
(Δ) –365.65MHz (Δ) –72.789dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –66.548dB
(Δ) –66.990dB
(Δ) –69.049dB
(Δ) –72.789dB
5.250MHz –72.17 –85.97 –72.10 –85.90 OFF
6.000MHz –75.28 –89.08 –73.42 –87.22 OFF
6.000MHz –75.91 –89.71 –75.03 –88.83 OFF
6.000MHz –76.71 –90.50 –76.31 –90.11 OFF
Figure 118. High Band Wideband ACLR
Figure 121. High Band Narrow-Band ACLR
Rev.C | Page 33 of 64
AD9737A/AD9739A
Data Sheet
FOUR-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–53.4dBc
–0.1dBc
–0.1dBc
–0.5dBc
–17.6dBm
–73.6dBc
–75.4dBc
–78.1dBc
–79.1dBc
1
–37
–47
–40
–50
–57
–60
–67
–70
–77
–80
–87
–90
–97
–100
–110
–120
–107
–117
5Δ1
4Δ1
3Δ1
2Δ1
CENTER 210MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
STOP 1GHz
VBW 2kHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
CARRIER POWER –17.556dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
LOWER
UPPER
dBc dBm FILTER
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
OFFSET FREQ INTEG BW
dBc dBm
–11.15 –28.70 –58.78 –76.34 OFF
1
2
3
4
5
N
1
1
1
1
1
f
f
f
f
f
200MHz
–18.593dBm BAND POWER 6MHz
–18.594dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
Δ1
(Δ) 216.60MHz (Δ) –73.198dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –73.170dB
(Δ) –73.621dB
(Δ) –71.289dB
(Δ) –68.946dB
5.250MHz –0.454 –18.01 –73.56 –91.12 OFF
6.000MHz –0.065 –17.62 –75.42 –92.98 OFF
6.000MHz –0.091 –17.65 –78.08 –95.64 OFF
6.000MHz –53.44 –70.99 –79.06 –96.62 OFF
(Δ) 400MHz
(Δ) –73.654dB
(Δ) 621.30MHz (Δ) –71.306dB
(Δ) 413.25MHz (Δ) –68.955dB
Figure 122. Low Band Wideband ACLR
Figure 125. Low Band Narrow-Band ACLR (Worse Side)
–76.6dBc
–76.4dBc
–75.0dBc
–72.9dBc
–19.5dBm
–0.3dBc
–0.1dBc
–0.1dBc
–50.2dBc
–38
–48
–37
–47
1
–58
–57
–68
–67
–78
–77
–88
–87
–98
–97
–108
–118
–107
–117
2Δ1
6Δ1
4Δ1
3Δ1
5Δ1
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
CENTER 650MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
FUNCTION FUNCTION
CARRIER POWER –19.503dBm/6MHz
ACP-IBW
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
dBc dBm
–61.84 –81.35 –11.18 –30.68 OFF
UPPER
1
2
3
4
5
6
N
1
1
1
1
1
1
f
f
f
f
f
f
667.80MHz
–18.760dBm BAND POWER 6MHz
–18.760dBm
OFFSET FREQ INTEG BW
dBc dBm FILTER
Δ1
Δ1
Δ1
Δ1
Δ1
(Δ) –192.20MHz (Δ) –69.536dB
(Δ) –98.15MHz (Δ) –71.601dB
(Δ) –614.00MHz (Δ) –72.824dB
(Δ) –567.45MHz (Δ) –75.786dB
(Δ) –55.40MHz (Δ) –71.997dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –69.536dB
(Δ) –71.601dB
(Δ) –72.833dB
(Δ) –75.320dB
(Δ) –71.997dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
5.250MHz –72.95 –92.45 –0.294 –19.80 OFF
6.000MHz –74.99 –94.49 –0.075 –19.58 OFF
6.000MHz –76.38 –95.89 –0.145 –19.65 OFF
6.000MHz –76.59 –96.10 –50.21 –69.71 OFF
Figure 123. Mid Band Wideband ACLR
Figure 126. Mid Band Narrow-Band ACLR (Worse Side)
–74.2dBc
–73.0dBc
–70.7dBc
–68.7Bc
–20.7dBm
–0.5dBc
–0.1dBc
–0.5dBc
–52.3dBc
–38
–48
–37
–47
1
–58
–57
–68
–67
–78
–77
–88
–87
–98
–97
2Δ1
5Δ1
–108
–118
–107
–117
3Δ1
6Δ1
4Δ1
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
CENTER 970MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 2kHz
VBW 3kHz
CARRIER POWER –20.666dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
1
2
3
4
5
6
N
1
1
1
1
1
1
f
f
f
f
f
f
987.95MHz
–20.040dBm BAND POWER 6MHz
–21.029dBm
OFFSET FREQ INTEG BW
dBc dBm
–60.65 –81.32 –10.77 –31.44 OFF
Δ1
Δ1
Δ1
Δ1
Δ1
(Δ) –490.50MHz (Δ) –60.683dB
(Δ) –624.45MHz (Δ) –69.390dB
(Δ) –738.45MHz (Δ) –71.954dB
(Δ) –130.45MHz (Δ) –66.954dB
(Δ) –374.60MHz (Δ) –68.889dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –60.683dB
(Δ) –69.390dB
(Δ) –71.847dB
(Δ) –66.954dB
(Δ) –68.889dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
5.250MHz –68.68 –89.34 –0.522 –21.19 OFF
6.000MHz –70.67 –91.33 –0.140 –20.81 OFF
6.000MHz –72.96 –93.63 –0.511 –21.18 OFF
6.000MHz –74.22 –94.89 –52.31 –72.98 OFF
Figure 124. High Band Wideband ACLR
Figure 127. High Band Narrow-Band ACLR
Rev.C | Page 34 of 64
Data Sheet
AD9737A/AD9739A
EIGHT-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
0.0dBc
0.0dBc
0.1dBc
–0.3dBc
–21.9dBm
–70.0Bc
–69.9dBc
–69.7dBc
–70.1dBc
1
–40
–50
–37
–47
–60
–57
–67
–70
–77
–80
–87
–90
–97
–100
–110
–120
5Δ1
4Δ1
–107
–117
3Δ1
2Δ1
CENTER 222MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
STOP 1GHz
VBW 2kHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
CARRIER POWER –21.874dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
OFFSET FREQ INTEG BW
dBc dBm
–10.98 –32.85 –59.41 –81.28 OFF
5.250MHz –0.334 –22.21 –69.96 –91.83 OFF
6.000MHz 0.087 –21.79 –69.91 –91.78 OFF
6.000MHz –0.034 –21.91 –69.74 –91.62 OFF
6.000MHz 0.031 –21.84 –70.08 –91.95 OFF
1
2
3
4
5
N
1
1
1
1
1
f
f
f
f
f
200MHz
–22.043dBm BAND POWER 6MHz
–22.044dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
Δ1
(Δ) 216.60MHz (Δ) –71.545dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –71.492dB
(Δ) –70.555dB
(Δ) –68.566dB
(Δ) –65.237dB
(Δ)
400MHz (Δ) –70.510dB
(Δ) 621.30MHz (Δ) –68.566dB
(Δ) 413.25MHz (Δ) –65.219dB
Figure 128. Low Band Wideband ACLR
Figure 131. Low Band Narrow-Band ACLR (Worse Side)
–71.6dBc
–71.5dBc
–71.2dBc
–71.3dBc
–22.6dBm
–0.5Bc
–0.1dBc
–0.2dBc
–0.2dBc
–38
–48
–37
–47
1
–58
–57
–68
–67
–78
–77
–88
–87
–98
–97
6Δ1
–108
–118
–107
–117
3Δ1
2Δ1
4Δ1
5Δ1
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
CENTER 580MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
FUNCTION FUNCTION
CARRIER POWER –22.556dBm/6MHz
ACP-IBW
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
dBc dBm
–60.21 –82.77 –11.25 –33.80 OFF
UPPER
1
2
3
4
5
6
N
1
1
1
1
1
1
f
f
f
f
f
f
667.80MHz
–23.977dBm BAND POWER 6MHz
–23.977dBm
OFFSET FREQ INTEG BW
dBc dBm FILTER
Δ1
Δ1
Δ1
Δ1
Δ1
(Δ) –171.30MHz (Δ) –69.185dB
(Δ) –98.15MHz (Δ) –68.551dB
(Δ) –614.00MHz (Δ) –69.923dB
(Δ) –567.45MHz (Δ) –72.145dB
(Δ) –55.40MHz (Δ) –65.009dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –69.185dB
(Δ) –68.551dB
(Δ) –69.938dB
(Δ) –72.083dB
(Δ) –65.009dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
5.250MHz –71.35 –93.90 –0.459 –23.01 OFF
6.000MHz –71.20 –93.75 –0.137 –22.69 OFF
6.000MHz –71.51 –94.06 –0.181 –22.74 OFF
6.000MHz –71.60 –94.16 –0.221 –22.78 OFF
Figure 132. Mid Band Narrow-Band ACLR (Worse Side)
Figure 129. Mid Band Wideband ACLR
–67.7dBc
–67.7dBc
–67.3dBc
–67.4dBc
–25.3dBm
–0.5Bc
–0.2dBc
0.0dBc
0.0dBc
–38
–48
–37
–47
1
–58
–57
–68
–67
–78
–77
–88
–87
–98
–97
2Δ1
6Δ1
–108
–118
5Δ1
–107
–117
3Δ1
4Δ1
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
CENTER 950MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 2kHz
VBW 3kHz
CARRIER POWER –25.344dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
dBc dBm
–60.39 –85.73 –10.93 –36.27 OFF
UPPER
OFFSET FREQ INTEG BW
dBc dBm FILTER
1
2
3
4
5
6
N
1
1
1
1
1
1
f
f
f
f
f
f
990.80MHz
–25.435dBm BAND POWER 6MHz
–25.435dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
Δ1
Δ1
(Δ) –481.00MHz (Δ) –61.947dB
(Δ) –633.95MHz (Δ) –67.517dB
(Δ) –734.65MHz (Δ) –69.583dB
(Δ) –128.55MHz (Δ) –65.237dB
(Δ) –378.40MHz (Δ) –64.615dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –61.947dB
(Δ) –67.532dB
(Δ) –69.602dB
(Δ) –65.237dB
(Δ) –64.615dB
5.250MHz –67.44 –92.78 –0.487 –25.83 OFF
6.000MHz –67.29 –92.63 –0.205 –25.55 OFF
6.000MHz –67.65 –93.00 –0.047 –25.39 OFF
6.000MHz –67.65 –93.00 –0.016 –25.33 OFF
Figure 130. High Band Wideband ACLR
Figure 133. High Band Narrow-Band ACLR
Rev.C | Page 35 of 64
AD9737A/AD9739A
Data Sheet
16-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
0.0dBc
–0.2dBc
–0.1dBc
–0.5dBc
–24.8dBm
–70.4dBc
–69.7dBc
–69.7dBc
–69.8dBc
–38
–48
–44
–54
1
–58
–64
–68
–74
–78
–84
–88
–94
–98
–104
–114
–124
–108
–118
6Δ1
4Δ1
5Δ1
2Δ1
3Δ1
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
CENTER 290MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 2kHz
VBW 3kHz
CARRIER POWER –24.824dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
1
2
3
4
5
6
N
1
1
1
1
1
1
f
f
f
f
f
f
289.70MHz
–25.335dBm BAND POWER 6MHz
–25.335dBm
OFFSET FREQ INTEG BW
dBc dBm
–10.83 –35.76 –59.93 –84.76 OFF
Δ1
Δ1
Δ1
Δ1
Δ1
(Δ) 202.05MHz (Δ) –66.838dB
(Δ) –183.65MHz (Δ) –70.421dB
(Δ) 697.95MHz (Δ) –65.880dB
(Δ) 18.70MHz (Δ) –67.033dB
(Δ) 322.70MHz (Δ) –64.481dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –66.838dB
(Δ) –70.312dB
(Δ) –65.928dB
(Δ) –66.973dB
(Δ) –64.451dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
5.250MHz –0.545 –25.37 –70.37 –95.20 OFF
6.000MHz –0.099 –24.92 –69.75 –94.57 OFF
6.000MHz –0.155 –24.98 –69.75 –94.57 OFF
6.000MHz –0.041 –24.87 –69.79 –94.62 OFF
Figure 134. Low Band Wideband ACLR
Figure 137. Low Band Narrow-Band ACLR
0.4dBc
0.2dBc
0.0dBc
–0.5dBc
–26.8dBm
–67.5dBc
–66.8dBc
–66.8Bc
–66.8dBc
–38
–48
–44
–54
1
–58
–64
–68
–74
–78
–84
–88
–94
–98
–104
–114
–124
–108
–118
4Δ1
2Δ1
3Δ1
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
CENTER 690MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
FUNCTION FUNCTION
CARRIER POWER –26.792dBm/6MHz
ACP-IBW
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
1
2
3
4
N
1
1
1
1
f
f
f
f
690.60MHz
–28.317dBm BAND POWER 6MHz
–28.317dBm
OFFSET FREQ INTEG BW
dBc dBm
–11.17 –37.97 –58.12 –84.92 OFF
Δ1
Δ1
Δ1
(Δ) –141.85MHz (Δ) –64.672dB
(Δ) –623.50MHz (Δ) –65.202dB
(Δ) 152.65MHz (Δ) –64.574dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –64.672dB
(Δ) –65.207dB
(Δ) –64.574dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
5.250MHz –0.460 –27.25 –67.47 –94.26 OFF
6.000MHz –0.049 –26.74 –66.83 –93.62 OFF
6.000MHz –0.196 –26.60 –66.80 –93.59 OFF
6.000MHz –0.366 –26.43 –66.79 –93.58 OFF
Figure 135. Mid Band Wideband ACLR
Figure 138. Mid Band Narrow-Band ACLR (Worse Side)
–64.9dBc
–64.8dBc
–64.6dBc
–65.0dBc
–28.4dBm
–0.5dBc
–0.1dBc
0.0dBc
0.2dBc
–38
–48
–44
–54
1
–58
–64
–68
–74
–78
–84
–88
–94
–104
–114
–124
–98
–108
–118
6Δ1
2Δ1
5Δ1
3Δ1
4Δ1
CENTER 900MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
STOP 1GHz
VBW 2kHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
CARRIER POWER –28.435dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
dBc dBm
–57.24 –85.68 –11.30 –39.73 OFF
UPPER
OFFSET FREQ INTEG BW
dBc dBm FILTER
1
2
3
4
5
6
N
1
1
1
1
1
1
f
f
f
f
f
f
989.85MHz
–27.971dBm BAND POWER 6MHz
–27.960dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
Δ1
Δ1
(Δ) –422.10MHz (Δ) –61.110dB
(Δ) –922.75MHz (Δ) –63.327dB
(Δ) –668.15MHz (Δ) –65.509dB
(Δ) –137.10MHz (Δ) –62.779dB
(Δ) –377.45MHz (Δ) –59.858dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –61.110dB
(Δ) –63.332dB
(Δ) –65.483dB
(Δ) –62.779dB
(Δ) –59.828dB
5.250MHz –65.03 –93.46 –0.490 –28.92 OFF
6.000MHz –64.64 –93.08 –0.119 –28.55 OFF
6.000MHz –64.80 –93.24 –0.016 –28.45 OFF
6.000MHz –64.86 –93.29 0.153 –28.28 OFF
Figure 136. High Band Wideband ACLR
Figure 139. High Band Narrow-Band ACLR
Rev.C | Page 36 of 64
Data Sheet
AD9737A/AD9739A
32-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
0.1dBc
0.0dBc
–0.1dBc
–0.4dBc
–29.9dBm
–65.4dBc
–64.8dBc
–64.5dBc
–64.4dBc
1
–52
–62
–44
–54
–64
–72
–74
–82
–84
–92
–94
–102
–112
–122
–132
3Δ1
–104
–114
–124
4Δ1
2Δ1
CENTER 386MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
STOP 1GHz
VBW 2kHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
CARRIER POWER –29.920dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
LOWER
UPPER
dBc dBm FILTER
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
OFFSET FREQ INTEG BW
dBc dBm
–10.67 –40.59 –61.86 –91.78 OFF
1
2
3
4
N
1
1
1
1
f
f
f
f
384.70MHz
–29.646dBm BAND POWER 6MHz
–29.645dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
(Δ) –283.40MHz (Δ) –64.175dB
(Δ) 227.70MHz (Δ) –59.429dB
(Δ) 325.55MHz (Δ) –62.750dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –64.167dB
(Δ) –59.423dB
(Δ) –62.750dB
5.250MHz –0.431 –30.35 –65.40 –95.32 OFF
6.000MHz –0.070 –29.99 –64.76 –94.68 OFF
6.000MHz –0.011 –29.93 –64.50 –94.42 OFF
6.000MHz
0.116 –29.80 –64.40 –94.32 OFF
Figure 143. Low Band Narrow-Band ACLR
Figure 140. Low Band Wideband ACLR
–63.5dBc
–63.2dBc
–63.1dBc
–63.3dBc
–29.3dBm
–0.5dBc
–0.2dBc
–0.2dBc
–0.1dBc
1
–44
–54
–52
–62
–64
–72
–74
–82
–84
–92
–94
–102
–112
–122
–132
–104
–114
–124
4Δ1
3Δ1
2Δ1
CENTER 200MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
CARRIER POWER –29.311dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
LOWER
dBc dBm
–58.76 –88.07 –10.78 –40.09 OFF
UPPER
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
OFFSET FREQ INTEG BW
dBc dBm FILTER
1
2
3
4
N
1
1
1
1
f
f
f
f
685.5MHz
–30.335dBm BAND POWER 6MHz
–30.335dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
Δ1
Δ1
Δ1
(Δ) –611.15MHz (Δ) –63.136dB
(Δ) –243.50MHz (Δ) –63.860dB
(Δ) 162.15MHz (Δ) –62.151dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –63.112dB
(Δ) –63.860dB
(Δ) –62.151dB
5.250MHz –63.30 –92.61 –0.487 –29.80 OFF
6.000MHz –63.05 –92.36 –0.175 –29.49 OFF
6.000MHz –63.21 –92.52 –0.151 –29.46 OFF
6.000MHz –64.46 –92.78 –0.061 –29.37 OFF
Figure 144. Mid Band Narrow-Band ACLR (Worse Side)
Figure 141. Mid Band Wideband ACLR
–62.8dBc
–62.7dBc
–62.8dBc
–63.2dBc
–30.7dBm
–0.4dBc
–0.4dBc
–0.5dBc
–0.4dBc
1
–44
–54
–52
–62
–64
–72
–74
–82
–84
–92
–94
–102
–112
–122
–132
4Δ1
2Δ1
–104
–114
–124
3Δ1
CENTER 800MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 2kHz
CARRIER POWER –30.746dBm/6MHz
ACP-IBW
LOWER
dBc dBm
–60.75 –91.49 –10.84 –41.59 OFF
UPPER
FUNCTION FUNCTION
OFFSET FREQ INTEG BW
dBc dBm FILTER
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
1
2
3
4
N
1
1
1
1
f
f
f
f
985.10MHz
–31.516dBm BAND POWER 6MHz
–31.516dBm
5.250MHz –63.18 –93.92 –0.437 –31.18 OFF
6.000MHz –62.76 –93.50 –0.354 –31.10 OFF
6.000MHz –62.74 –93.48 –0.455 –31.20 OFF
6.000MHz –62.84 –93.59 –0.410 –31.16 OFF
Δ1
Δ1
Δ1
(Δ) –334.70MHz (Δ) –59.997dB
(Δ) –909.45MHz (Δ) –60.458dB
(Δ) –373.65MHz (Δ) –57.761dB
BAND POWER 6MHz
BAND POWER 6MHz
BAND POWER 6MHz
(Δ) –59.997dB
(Δ) –60.535dB
(Δ) –57.763dB
Figure 142. High Band Wideband ACLR
Figure 145. High Band Narrow-Band ACLR
Rev.C | Page 37 of 64
AD9737A/AD9739A
Data Sheet
64- AND 128-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)
IOUTFS = 20 mA, fDAC = 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
0.3dBc
0.2dBc
0.1dBc
–0.3dBc
–32.4dBm
–62.3dBc
–61.5dBc
–61.5dBc
–61.4dBc
–52
–62
–51
–61
1
–72
–71
–82
–81
–92
–91
–102
–112
–122
–132
–101
–111
–121
–131
3Δ1
2Δ1
CENTER 478MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
START 50MHz
#RES BW 20kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
VBW 3kHz
VBW 2kHz
CARRIER POWER –32.409dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
LOWER
UPPER
dBc dBm FILTER
OFFSET FREQ INTEG BW
dBc dBm
–10.83 –43.24 –60.80 –93.21 OFF
5.250MHz –0.267 –32.68 –62.25 –94.66 OFF
1
2
3
N
Δ1
Δ1
1
1
1
f
f
f
478.75MHz
(Δ) 372.10MHz (Δ) –58.746dB
(Δ) 132.70MHz (Δ) –55.165dB
–33.210dBm BAND POWER 6MHz
–33.209dBm
(Δ) –58.804dB
(Δ) –55.165dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
BAND POWER 6MHz
BAND POWER 6MHz
6.000MHz
6.000MHz
6.000MHz
0.139 –32.27 –61.47 –93.88 OFF
0.201 –32.21 –61.54 –93.95 OFF
0.308 –32.10 –61.40 –93.81 OFF
Figure 146. 64-Carrier Low Band Wideband ACLR
Figure 149. 64-Carrier Low Band Narrow-Band ACLR
–60.6dBc
–60.6dBc
–60.6dBc
–61.1dBc
–33.6dBm
–0.3dBc
–0.1dBc
0.2dBc
0.1dBc
–51
–61
–52
–62
1
–71
–72
–81
–82
–91
–92
–101
–111
–121
–131
–102
–112
–122
–132
2Δ1
3Δ1
CENTER 600MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
STOP 1GHz
VBW 2kHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
CARRIER POWER –33.558dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
LOWER
dBc dBm
–60.02 –93.58 –11.48 –45.04 OFF
UPPER
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
OFFSET FREQ INTEG BW
dBc dBm FILTER
1
2
3
N
Δ1
Δ1
1
1
1
f
f
f
978.45MHz
–35.872dBm BAND POWER 6MHz
–35.873dBm
(Δ) –58.625dB
(Δ) –59.286dB
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
(Δ) –901.85MHz (Δ) –58.5816dB BAND POWER 6MHz
5.250MHz –61.11 –94.66 –0.284 –33.84 OFF
6.000MHz –60.57 –94.13 0.099 –33.46 OFF
6.000MHz –60.64 –94.20 0.221 –33.34 OFF
6.000MHz –60.58 –94.14 0.060 –33.50 OFF
(Δ) –561.75MHz (Δ) –59.214dB
BAND POWER 6MHz
Figure 147. 64-Carrier High Band Wideband ACLR
Figure 150. 64-Carrier High Band Narrow-Band ACLR
0.3dBc
0.3dBc
0.3dBc
–0.3dBc
–37.3dBm
–57.7dBc
–56.6dBc
–56.5dBc
–56.4dBc
–50
–60
–50
–60
1
3
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
2Δ1
CENTER 832MHz
#RES BW 30kHz
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
START 50MHz
STOP 1GHz
VBW 2kHz
#RES BW 20kHz
SWEEP 24.1s (1001pts)
CARRIER POWER –37.33dBm/6MHz
ACP-IBW
FUNCTION FUNCTION
LOWER
UPPER
dBc dBm FILTER
MKR MODE TRC SCL
X
Y
FUNCTION
WIDTH
VALUE
OFFSET FREQ INTEG BW
dBc dBm
–10.77 –48.10 –59.34 –96.67 OFF
5.250MHz –0.277 –37.61 –57.70 –95.03 OFF
6.000MHz
6.000MHz
6.000MHz
1
2
3
N
Δ1
1
1
1
1
f
f
f
69.00MHz
–35.495dBm BAND POWER 6MHz
BAND POWER 6MHz
–37.544dBm BAND POWER 6MHz
–35.495dBm
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
750.0kHz
(Δ) 855.95MHz (Δ) –55.328dB
(Δ) –55.328dB
831.85MHz
–37.545dBm
0.318 –37.01 –56.56 –93.89 OFF
0.328 –37.00 –56.49 –93.82 OFF
0.337 –37.00 –56.35 –93.69 OFF
Figure 148. 128-Carrier Wideband ACLR
Figure 151. 128-Carrier Narrow-Band ACLR
Rev.C | Page 38 of 64
Data Sheet
AD9737A/AD9739A
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
The maximum deviation of the actual analog output from the
ideal output, determined by a straight line drawn from 0 to full
scale.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Differential Nonlinearity (DNL)
Spurious-Free Dynamic Range
The measure of the variation in analog value, normalized to full
scale, associated with a 1 LSB change in digital input code.
The difference, in decibels (dB), between the rms amplitude of
the output signal and the peak spurious signal over the specified
bandwidth.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal. It is expressed as
a percentage or in decibels (dB).
Offset Error
The deviation of the output current from the ideal of 0 is called
the offset error. For IOUTP, 0 mA output is expected when the
inputs are all 0s. For IOUTN, 0 mA output is expected when all
inputs are set to 1.
Noise Spectral Density (NSD)
NSD is the converter noise power per unit of bandwidth. This is
usually specified in dBm/Hz in the presence of a 0 dBm full-
scale signal.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1 minus the output when all inputs are set to 0.
Adjacent Channel Leakage Ratio (ACLR)
The adjacent channel leakage (power) ratio is a ratio, in dBc, of
the measured power within a channel relative to its adjacent
channels.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Modulation Error Ratio (MER)
Modulated signals create a discrete set of output values referred
to as a constellation. Each symbol creates an output signal
corresponding to one point on the constellation. MER is a measure
of the discrepancy between the average output symbol magnitude
and the rms error magnitude of the individual symbol.
Temperature Drift
Specified as the maximum change from the ambient (25°C)
value to the value at either TMIN or TMAX. For offset and gain
drift, the drift is reported in ppm of full-scale range (FSR)
per °C. For reference drift, the drift is reported in ppm per °C.
Intermodulation Distortion (IMD)
IMD is the result of two or more signals at different frequencies
mixing together. Many products are created according to the
formula, aF1 bF2, where a and b are integer values.
Rev.C | Page 39 of 64
AD9737A/AD9739A
Data Sheet
SERIAL PORT INTERFACE (SPI) REGISTER
SPI REGISTER MAP DESCRIPTION
SPI OPERATION
The serial port of the AD9737A/AD9739A, shown in Figure 152,
has a 3- or 4-wire SPI capability, allowing read/write access
to all registers that configure the device’s internal parameters.
It provides a flexible, synchronous serial communications
port, allowing easy interface to many industry-standard
microcontrollers and microprocessors. The 3.3 V serial I/O is
compatible with most synchronous transfer formats, including
the Motorola® SPI and the Intel® SSR protocols.
The AD9737A/AD9739A contain a set of programmable registers,
described in Table 10, that are used to configure and monitor
various internal parameters. Note the following points when
programming the AD9737A/AD9739A SPI registers:
•
Registers pertaining to similar functions are grouped together
and assigned adjacent addresses.
•
Bits that are undefined within a register should be assigned
a 0 when writing to that register.
•
•
Registers that are undefined should not be written to.
A hardware or software reset is recommended on power-
up to place SPI registers in a known state.
SDO (PIN H14)
SDIO (PIN G14)
AD9737A/AD9739A
SPI PORT
SCLK (PIN H13)
•
A SPI initialization routine is required as part of the boot
process. See Table 29 for an example procedure.
CS (PIN G13)
Figure 152. AD9737A/AD9739A SPI Port
Reset
The default 4-wire SPI interface consists of a clock (SCLK),
Issuing a hardware or software reset places the AD9737A/
AD9739A SPI registers in a known state. All SPI registers
(excluding 0x00) are set to their default states, as described in
Table 10, upon issuing a reset. After issuing a reset, the SPI
initialization process needs only to write to registers that are
required for the boot process as well as any other register
settings that must be modified, depending on the target
application.
CS
serial port enable ( ), serial data input (SDIO), and serial data
CS
output (SDO). The inputs to SCLK, , and SDIO contain a
Schmitt trigger with a nominal hysteresis of 0.4 V centered about
VDD33/2. The maximum frequency for SCLK is 20 MHz. The
SDO pin is active only during the transmission of data and
remains three-stated at any other time.
A 3-wire SPI interface can be enabled by setting the SDIO_DIR
bit (Register 0x00, Bit 7). This causes the SDIO pin to become
bidirectional such that output data appears on only the SDIO
pin during a read operation. The SDO pin remains three-stated
in a 3-wire SPI interface.
Although the AD9737A/AD9739A do feature an internal
power-on reset (POR), it is still recommended that a software
or hardware reset be implemented shortly after power-up. The
internal reset signal is derived from a logical OR operation from
the internal POR signal, the RESET pin, and the software reset
state. A software reset can be issued via the reset bit (Register 0x00,
Bit 5) by toggling the bit high, then low. Note that, because the
MSB/LSB format may still be unknown upon initial power-up
(that is, internal POR is unsuccessful), it is also recommended
that the bit settings for Bits[7:5] be mirrored onto Bits[2:0] for
the instruction cycle that issues a software reset. A hardware
reset can be issued from a host or external supervisory IC by
applying a high pulse with a minimum width of 40 ns to the RESET
pin (that is, Pin F14). RESET should be tied to VSS if unused.
Instruction Header Information
MSB
LSB
11
17
16
A6
15
A5
14
A4
13
A3
12
A2
10
A0
R/W
A1
An 8-bit instruction header must accompany each read and write
W
operation. The MSB is a R/ indicator bit with logic high
indicating a read operation. The remaining seven bits specify
the address bits to be accessed during the data transfer portion.
The eight data bits immediately follow the instruction header
for both read and write operations. For write operations, registers
change immediately upon writing to the last bit of each transfer
Table 9. SPI Registers Pertaining to SPI Options
Address (Hex)
Bit
Description
CS
byte.
the last byte) to stall the bus. The serial transfer resumes
CS
can be raised after each sequence of eight bits (except
0x00
7
Enable 3-wire SPI
Enable SPI LSB first
Software reset
6
when is lowered. Stalling on nonbyte boundaries resets the SPI.
5
Rev.C | Page 40 of 64
Data Sheet
AD9737A/AD9739A
The AD9737A/AD9739A serial port can support both most
significant bit (MSB) first and least significant bit (LSB) first
data formats. Figure 153 illustrates how the serial port words
are formed for the MSB first and LSB first modes. The bit order
is controlled by the LSB/MSB bit (Register 0x00, Bit 6). The
default value of Bit 6 is 0, MSB first. When the LSB/MSB bit is
set high, the serial port interprets both instruction and data bytes
LSB first.
Figure 154 illustrates the timing requirements for a write
CS
operation to the SPI port. After the serial port enable (
)
signal goes low, data (SDIO) pertaining to the instruction
header is read on the rising edges of the clock (SCLK). To
initiate a write operation, the read/not-write bit is set low. After
the instruction header is read, the eight data bits pertaining to
the specified register are shifted into the SDIO pin on the rising
edge of the next eight clock cycles.
Figure 155 illustrates the timing for a 3-wire read operation to
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
CS
the SPI port. After
goes low, data (SDIO) pertaining to the
SCLK
instruction header is read on the rising edges of SCLK. A read
operation occurs if the read/not-write indicator is set high. After
the address bits of the instruction header are read, the eight data
bits pertaining to the specified register are shifted out of the
SDIO pin on the falling edges of the next eight clock cycles.
R/W N1 N2 A4 A3 A2 A1 A0 D71 D61
D1N D0N
SDATA
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
Figure 156 illustrates the timing for a 4-wire read operation to
the SPI port. The timing is similar to the 3-wire read operation
with the exception that data appears at the SDO pin only, whereas
the SDIO pin remains at high impedance throughout the
operation. The SDO pin is an active output only during the data
transfer phase and remains three-stated at all other times.
SDATA
A0 A1 A2 A3 A4 N2 N1 R/W D01 D11
D6N D7N
Figure 153. SPI Timing, MSB First (Upper) and LSB First (Lower)
tS
1/fSCLK
tH
CS
tLOW
tHI
SCLK
tDS
tDS
tDS
tDH
R/W
N1
N0
A0
D7
D6 D1
D0
SDIO
Figure 154. SPI Write Operation Timing
tS
1/fSCLK
CS
tLOW
tHI
SCLK
tDV
tDH
R/W
tEZ
A1
A0
D6 D1 D0
N1
D7
A2
SDIO
Figure 155. SPI 3-Wire Read Operation Timing
tS
1/fSCLK
CS
tLOW
tHI
SCLK
tDH
tEZ
tEZ
A1
A0
N1
A2
SDIO
SDO
R/W
tDV
D6 D1 D0
D7
Figure 156. SPI 4-Wire Read Operation Timing
Rev.C | Page 41 of 64
AD9737A/AD9739A
Data Sheet
SPI REGISTER MAP
Table 10. Full Register Map (N/A = Not Applicable)
Name
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
N/A
N/A
Bit 2
N/A
N/A
Bit 1
Bit 0
Default
0x00
Mode
0x00
SDIO_DIR
N/A
LSB/MSB
N/A
Reset
N/A
N/A
N/A
Power-
Down
0x01
LVDS_
LVDS_
RCVR_PD
CLK_RCVR_
PD
DAC_BIAS_
PD
0x00
DRVR_PD
CNT_CLK_
DIS
0x02
N/A
N/A
N/A
N/A
CLKGEN_PD
N/A
REC_CNT_
CLK
MU_CNT_
CLK
0x03
IRQ_EN
0x03
0x04
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MU_LST_EN
MU_LST_IRQ
MU_LCK_EN
RCV_LST_EN RCV_LCK_EN
0x00
0x00
IRQ_REQ
MU_LCK_IRQ RCV_LST_
IRQ
RCV_LCK_
IRQ
RSVD
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
N/A
N/A
FSC[6]
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FSC[3]
N/A
N/A
N/A
N/A
N/A
N/A
FSC[2]
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FSC_1
FSC[7]
Sleep
N/A
FSC[5]
N/A
FSC[4]
N/A
FSC[1]
FSC[9]
DAC_DEC[1]
N/A
FSC[0]
FSC[8]
DAC_DEC[0]
N/A
0x00
0x02
0x00
N/A
FSC_2
DEC_CNT
RSVD
N/A
N/A
N/A
N/A
N/A
LVDS_CNT
DIG_STAT
LVDS_STAT1
N/A
N/A
N/A
N/A
N/A
0x00
RNDM
RNDM
N/A
N/A
N/A
N/A
N/A
SUP/HLD_
Edge1
DCI_PHS3
DCI_PHS1
DCI_PRE_
PH2
DCI_PRE_
PH0
DCI_PST_
PH2
DCI_PST_
PH0
LVDS_STAT2
RSVD
0x0D
0x0E
0x0F
0x10
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
RNDM/0
N/A
RSVD
N/A
LVDS_
REC_CNT1
RCVR_FLG_
RST
RCVR_
LOOP_ON
RCVR_CNT_
ENA
0x42
LVDS_
REC_CNT2
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
SMP_DEL[1]
SMP_DEL[9]
DCI_DEL[3]
N/A
SMP_DEL[0]
SMP_DEL[8]
DCI_DEL[2]
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0xDD
0x29
0x71
0x0A
0x42
0x00
0x00
0x00
0xC7
0x29
0xC0
0x29
0x86
0x00
0x00
0x00
0x00
0x00
LVDS_
REC_CNT3
SMP_DEL[7] SMP_DEL[6]
SMP_DEL[5]
SMP_DEL[4]
SMP_DEL[3]
SMP_DEL[2]
LVDS_
REC_CNT4
DCI_DEL[1]
DCI_DEL[9]
N/A
DCI_DEL[0]
DCI_DEL[8]
N/A
FINE_DEL_
SKW[3]
FINE_DEL_
SKW[2]
FINE_DEL_
SKW[1]
FINE_DEL_
SKW[0]
LVDS_
REC_CNT5
DCI_DEL[7]
DCI_DEL[6]
DCI_DEL[5]
DCI_DEL[4]
LVDS_
REC_CNT6
N/A
N/A
N/A
N/A
N/A
N/A
LVDS_
REC_CNT7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LVDS_
REC_CNT8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LVDS_
REC_CNT9
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LVDS_
REC_STAT1
SMP_DEL[1]
SMP_DEL[9]
DCI_DEL[1]
DCI_DEL[9]
N/A
SMP_DEL[0]
SMP_DEL[8]
DCI_DEL[0]
DCI_DEL[8]
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LVDS_
REC_STAT2
SMP_DEL[7] SMP_DEL[6]
SMP_DEL[5]
N/A
SMP_DEL[4]
N/A
SMP_DEL[3]
N/A
SMP_DEL[2]
N/A
LVDS_
REC_STAT3
N/A
N/A
LVDS_
REC_STAT4
DCI_DEL[7]
N/A
DCI_DEL[6]
N/A
DCI_DEL[5]
N/A
DCI_DEL[4]
N/A
DCI_DEL[3]
N/A
DCI_DEL[2]
N/A
LVDS_
REC_STAT5
LVDS_
REC_STAT6
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LVDS_
REC_STAT7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LVDS_
REC_STAT8
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LVDS_
REC_STAT9
N/A
N/A
N/A
N/A
RCVR_TRK_
ON
RCVR_FE_
ON
RCVR_LST
RCVR_LCK
CROSS_
CNT1
N/A
N/A
N/A
DIR_P
CLKP_
OFFSET[3]
CLKP_
OFFSET[2]
CLKP_
OFFSET[1]
CLKP_
OFFSET[0]
Rev.C | Page 42 of 64
Data Sheet
AD9737A/AD9739A
Name
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
CROSS_
CNT2
0x23
0x24
0x25
N/A
N/A
N/A
DIR_N
CLKN_
OFFSET[3]
CLKN_
OFFSET[2]
CLKN_
OFFSET[1]
CLKN_
OFFSET[0]
0x00
PHS_DET
N/A
N/A
CMP_BST
ADJ[5]
PHS_DET
AUTO_EN
N/A
N/A
N/A
N/A
0x00
0x00
MU_DUTY
MU_
POS/NEG
ADJ[4]
N/A
N/A
N/A
N/A
DUTYAUTO_
EN
MU_CNT1
MU_CNT2
0x26
0x27
N/A
Slope
Mode[1]
Mode[0]
Read
Gain[1]
Gain[0]
Enable
0x42
0x40
MUDEL[0]
SRCH_
SRCH_
SET_PHS[4]
SET_PHS[3]
SET_PHS[2]
SET_PHS[1]
SET_PHS[0]
MODE[1]
MODE[0]
MU_CNT3
MU_CNT4
MU_STAT1
RSVD
0x28
0x29
0x2A
0x2B
0x2C
0x32
0x33
0x34
0x35
MUDEL[8]
MUDEL[7]
MUDEL[6]
CONTRST
N/A
MUDEL[5]
Guard[4]
N/A
MUDEL[4]
Guard[3]
N/A
MUDEL[3]
Guard[2]
N/A
MUDEL[2]
Guard[1]
MU_LOST
N/A
MUDEL[1]
Guard[0]
MU_LKD
N/A
0x00
0x0B
0x00
N/A
SEARCH_TOL Retry
N/A
N/A
N/A
N/A
N/A
N/A
ID[7]
N/A
N/A
N/A
N/A
N/A
N/A
ID[6]
N/A
N/A
N/A
N/A
RSVD
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ANA_CNT1
ANA_CNT2
RSVD
N/A
N/A
N/A
N/A
N/A
N/A
0xCA
0x03
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PART_ID
ID[5]
ID[4]
ID[3]
ID[2]
ID[1]
ID[0]
0x40
SPI PORT CONFIGURATION AND SOFTWARE RESET
Table 11. SPI Port Configuration and Software Reset Register (Mode)
Default
Setting
Address
(Hex)
Bit Name
SDIO_DIR
LSB/MSB
Reset
Bits
7
R/W
R/W
R/W
R/W
Description
0x00
0x0
0x0
0x0
0 = 4-wire SPI, 1 = 3-wire SPI.
0 = MSB first, 1 = LSB first.
6
5
Software reset is recommended before modification of other SPI registers
from the default setting.
0 = inactive state; allows the user to modify registers from the default setting.
1 = causes all registers (except 0x00) to be set to the default setting.
POWER-DOWN LVDS INTERFACE AND TxDAC®
Table 12. Power-Down LVDS Interface and TxDAC Register (Power-Down)
Default
Setting
0x0
Address
(Hex)
Bit Name
Bits
5
R/W
R/W
R/W
R/W
R/W
Description
0x01
LVDS_DRVR_PD
LVDS_RCVR_PD
CLK_RCVR_PD
DAC_BIAS_PD
Power-down of the LVDS drivers/receivers and TxDAC.
0 = enable, 1 = disable.
4
0x0
1
0x0
0
0x0
CONTROLLER CLOCK DISABLE
Table 13. Controller Clock Disable Register (CNT_CLK_DIS)
Default
Setting
Address
(Hex)
Bit Name
Bits
3
R/W
R/W
R/W
Description
0x02
CLKGEN_PD
REC_CNT_CLK
0x0
0x1
Internal CLK distribution enable: 0 = enable, 1 = disable.
1
LVDS receiver and Mu controller clock disable.
0 = disable, 1 = enable.
MU_CNT_CLK
0
R/W
0x1
Rev.C | Page 43 of 64
AD9737A/AD9739A
Data Sheet
INTERRUPT REQUEST (IRQ) ENABLE/STATUS
Table 14. Interrupt Request (IRQ) Enable (IRQ_EN)/Status (IRQ_REQ) Register
Default
Setting
0x0
Address
(Hex)
Bit Name
Bits
3
R/W
W
Description
0x03
0x04
MU_LST_EN
MU_LCK_EN
RCV_LST_EN
RCV_LCK_EN
MU_LST_IRQ
This register enables the Mu and LVDS Rx controllers to update their
corresponding IRQ status bits in Register 0x04, which defines whether the
controller is locked (LCK) or unlocked (LST).
2
W
0x0
0x0
0x0
0x0
1
W
0 = disable (resets the status bit), 1 = enable.
0
W
3
R
This register indicates the status of the controllers.
For LCK_IRQ bits: 0 = lock lost, 1 = locked.
For LST_IRQ bits: 0 = lock not lost, 1 = unlocked.
Note that, if the controller IRQ is serviced, the relevant bits in Register 0x03
should be reset by writing 0, followed by another write of 1 to enable.
MU_LCK_IRQ
RCV_LST_IRQ
RCV_LCK_IRQ
2
1
0
R
R
R
0x0
0x0
0x0
TxDAC FULL-SCALE CURRENT SETTING (IOUTFS) AND SLEEP
Table 15. TxDAC Full-Scale Current Setting (IOUTFS) and Sleep Register (FSC_1 and FSC_2)
Default
Setting
Address
(Hex)
Bit Name
FSC[7:0]
FSC[9:8]
Sleep
Bits
[7:0]
[1:0]
7
R/W
R/W
R/W
R/W
Description
0x06
0x07
0x00
0x02
Sets the TxDAC IOUTFS current between 8 mA and 31 mA (default = 20 mA).
IOUTFS = 0.0226 × FSC[9:0] + 8.58, where FSC = 0 to 1023.
0 = enable DAC output, 1 = disable DAC output (sleep).
TxDAC QUAD-SWITCH MODE OF OPERATION
Table 16. TxDAC Quad-Switch Mode of Operation Register (DEC_CNT)
Default
Setting
Address
(Hex)
Bit Name
Bits
R/W
Description
0x08
DAC_DEC
[1:0]
R/W
0x00
0x00 = normal baseband mode.
0x02 = mix-mode.
DCI PHASE ALIGNMENT STATUS
Table 17. DCI Phase Alignment Status Register (LVDS_STAT1)
Default
Setting
0x0
Address
(Hex)
Bit Name
Bits
R/W
Description
0x0C
DCI_PRE_PH0
2
R
0 = DCI rising edge is after the PRE delayed version of the Phase 0 sampling
edge.
1 = DCI rising edge is before the PRE delayed version of the Phase 0 sampling
edge.
DCI_PST_PH0
0
R
0x0
0 = DCI rising edge is after the POST delayed version of the Phase 0 sampling
edge.
1 = DCI rising edge is before the POST delayed version of the Phase 0 sampling
edge.
DATA RECEIVER CONTROLLER CONFIGURATION
Table 18. Data Receiver Controller Configuration Register (LVDS_REC_CNT1)
Default
Setting
0x0
Address
(Hex)
Bit Name
Bits
2
R/W
W
Description
0x10
RCVR_FLG_RST
RCVR_LOOP_ON
Data receiver controller flag reset. Write 1 followed by 0 to reset flags.
1
R/W
0x1
0 = disable, 1 = enable.
When this bit is enabled, the data receiver controller generates an IRQ; it
falls out of lock and automatically begins a search/track routine.
RCVR_CNT_ENA
0
R/W
0x0
Data receiver controller enable. 0 = disable, 1 = enable.
Rev.C | Page 44 of 64
Data Sheet
AD9737A/AD9739A
DATA RECEIVER CONTROLLER_DATA SAMPLE DELAY VALUE
Table 19. Data Receiver Controller_Data Sample Delay Value Register (LVDS_REC_CNT2 and LVDS_REC_CNT3)
Default
Setting
0x11
Address
(Hex)
Bit Name
Bits
[7:6]
[7:0]
R/W
R/W
R/W
Description
0x11
0x12
SMP_DEL[1:0]
SMP_DEL[9:2]
Controller enabled: the 10-bit value (with a maximum of 384) represents
the start value for the delay line used by the state machine to sample data.
Leave at the default setting of 167, which is near the midpoint of the delay line.
Controller disabled: the value sets the actual value of the delay line.
0x25
DATA RECEIVER CONTROLLER_DCI DELAY VALUE/WINDOW AND PHASE ROTATION
Table 20. Data Receiver Controller_DCI Delay Value (LVDS_REC_CNT4)/Window and Phase Rotation Register (LVDS_REC_CNT5)
Default
Setting
0x0111
Address
(Hex)
Bit Name
Bits
[7:4]
[3:0]
R/W
R/W
R/W
Description
0x13
0x14
DCI_DEL[3:0]
Refer to the DCI_DEL description in Register 0x14.
FINE_DEL_
SKW[3:0]
0x0001
A 4-bit value sets the difference (that is, window) for the DCI PRE and POST
sampling clocks. Leave at the default value of 1 for a narrow window.
DCI_DEL[9:4]
[5:0]
R/W
0x001010 Controller enabled: the 10-bit value (with a maximum of 384) represents
the start value for the delay line used by the state machine to sample the
DCI input. Leave at the default setting of 167, which is near the midpoint
of the delay line.
Controller disabled: the value sets the actual value of the delay line.
DATA RECEIVER CONTROLLER_DELAY LINE STATUS
Table 21. Data Receiver Controller_Delay Line Status Register (LVDS_REC_STAT[1:4])
Default
Setting
0x00
Address
(Hex)
Bit Name
Bits
[7:6]
[7:0]
[7:6]
[7:0]
R/W
R
Description
0x19
0x1A
0x1B
0x1C
SMP_DEL[1:0]
SMP_DEL[9:2]
DCI_DEL[1:0]
DCI_DEL[9:2]
The actual value of the DCI and data delay lines are determined by the
data receiver controller (when enabled) after the state machine completes
its search and enters track mode. Note that these values should be equal.
R
0x00
0x00
0x00
R
R
DATA RECEIVER CONTROLLER LOCK/TRACKING STATUS
Table 22. Data Receiver Controller Lock/Tracking Status Register (LVDS_REC_STAT9)
Default
Setting
0x0
Address
(Hex)
Bit Name
Bits
3
R/W
R
Description
0x21
RCVR_TRK_ON
RCVR_FE_ON
0 = tracking not established, 1 = tracking established.
2
R
0x0
0 = find edge state machine is not active, 1 = find edge state machine is
active.
RCVR_LST
RCVR_LCK
1
0
R
R
0x0
0x0
0 = controller has not lost lock, 1 = controller has lost lock.
0 = controller is not locked, 1 = controller is locked.
Rev.C | Page 45 of 64
AD9737A/AD9739A
Data Sheet
CLK INPUT COMMON MODE
Table 23. CLK Input Common Mode Register (CROSS_CNT1 and CROSS_CNT2)
Default
Setting
0x0
Address
(Hex)
Bit Name
Bits
R/W
R/W
R/W
Description
0x22
DIR_P
4
DIR_P and DIR_N.
0 = VCM at the DACCLK_P input decreases with the offset value.
1 = VCM at the DACCLK_P input increases with the offset value.
CLKx_OFFSET sets the magnitude of the offset for the DACCLK_P and
DACCLK_N inputs. For optimum performance, set to 1111.
CLKP_OFFSET[3:0] [3:0]
DIR_N
CLKN_OFFSET[3:0] [3:0]
0x0000
0x23
4
R/W
R/W
0x0
0x0000
MU CONTROLLER CONFIGURATION AND STATUS
Table 24. Mu Controller Configuration and Status Register (PHS_DET, MU_DUTY, MU_CNT[1:4], and MU_STAT1)
Default
Setting
Address
(Hex)
Bit Name
Bits
5
R/W
R/W
R/W
Description
0x24
CMP_BST
0x0
0x0
Phase detector enable and boost bias bits.
Note that both bits should always be set to 1 to enable these functions.
PHS_DET
AUTO_EN
4
0x25
0x26
MU_
DUTYAUTO_EN
7
R/W
R/W
R/W
0x0
Mu controller duty cycle enable.
Note that this bit should always be set to 1 to enable.
Slope
6
0x1
Mu controller phase slope lock. 0 = negative slope, 1 = positive slope. Note
that a setting of 0 is recommended for best ac performance.
Mode[1:0]
[5:4]
0x00
Sets the Mu controller mode of operation.
00 = search and track (recommended).
01 = search only.
10 = track.
Read
3
R/W
R/W
0x0
Set to 1 to read the current value of the Mu delay line in.
Gain[1:0]
[2:1]
0x01
Sets the Mu controller tracking gain.
Recommended to leave at the default 01 setting.
Enable
0
R/W
0x0
0 = enable the Mu controller.
1 = disable the Mu controller.
0x27
MUDEL[0]
7
R/W
R/W
0x0
0x0
The LSB of the 9-bit MUDEL setting.
SRCH_MODE[1:0]
[6:5]
Sets the direction in which the Mu controller searches (from its initial MUDEL
setting) for the optimum Mu delay line setting that corresponds to the desired
phase/slope setting (that is, SET_PHS and slope ).
00 = down.
01 = up.
10 = down/up (recommended).
SET_PHS[4:0]
MUDEL[8:1]
[4:0]
[7:0]
R/W
W
0x0
Sets the target phase that the Mu controller locks to with a maximum setting
of 16.
A setting of 4 (that is, 00100) is recommended for optimum ac performance.
0x28
0x29
0x00
With enable (Bit 0, Register 0x26) set to 0, this 9-bit value represents the
value that the Mu delay is set to. Note that the maximum value is 432.
With enable set to 1, this value represents the Mu delay value at which the
controller begins its search. Setting this value to the delay line midpoint of
216 is recommended.
R
0x00
When read (Bit 3, Register 0x26) is set to 1, the value read back is equal to
the value written into the register when enable = 0 or the value that the
Mu controller locks to when enable = 1.
SEARCH_TOL
Retry
7
6
5
R/W
R/W
R/W
0x0
0x0
0x0
0 = not exact (can find a phase within two values of the desired phase).
1 = finds the exact phase that is targeted (optimal setting).
0 = stop the search if the correct value is not found,
1 = retry the search if the correct value is not found.
CONTRST
Controls whether the controller resets or continues when it does not find
the desired phase.
0 = continue (optimal setting), 1 = reset.
Rev.C | Page 46 of 64
Data Sheet
AD9737A/AD9739A
Default
Setting
Address
(Hex)
Bit Name
Bits
R/W
Description
Guard[4:0]
[4:0]
R/W
0x01011
Sets a guard band from the beginning and end of the Mu delay line, which
the Mu controller does not enter into unless it does not find a valid phase
outside the guard band (optimal value is Decimal 11 or 0x0B).
0x2A
MU_LOST
MU_LKD
1
0
R
R
0x0
0x0
0 = Mu controller has not lost lock.
1 = Mu controller has lost lock.
0 = Mu controller is not locked.
1= Mu controller is locked.
PART ID
Table 25. Part ID Register (PART_ID)
Default
Setting
Address
(Hex)
Bit Name
Bits
R/W
Description
0x35
ID[7:0]
[7:0]
R
0x24
0x24—AD9739A
0x27
0x27—AD9737A
Rev.C | Page 47 of 64
AD9737A/AD9739A
Data Sheet
THEORY OF OPERATION
The AD9739A and the AD9737A are 14- and 11-bit TxDACs
with a specified update rate of 1.6 GSPS to 2.5 GSPS. Figure 157
shows a top-level functional diagram of the AD9737A/AD9739A.
A high performance TxDAC core delivers a signal dependent,
differential current (nominal 10 mA) to a balanced load
referenced to ground. The frequency of the clock signal appearing
at the AD9737A/AD9739A differential clock receiver, DACCLK,
sets the TxDAC’s update rate. This clock signal, which serves as
the master clock, is routed directly to the TxDAC as well as to a
clock distribution block that generates all critical internal and
external clocks.
The AD9737A/AD9739A includes a delay lock loop (DLL)
circuit controlled via a Mu controller to optimize the timing
hand-off between the AD9737A/AD9739A digital clock domain
and TxDAC core. Besides ensuring proper data reconstruction,
the TxDAC’s ac performance is also dependent on this critical
hand-off between these clock domains with speeds of up to
2.5 GSPS. Once properly initialized and configured for track
mode, the DLL maintains optimum timing alignment over
temperature, time, and power supply variation.
A SPI interface is used to configure the various functional blocks
as well as monitor their status for debug purposes. Proper
operation of the AD9737A/AD9739A requires that controller
blocks be initialized upon power-up. A simple SPI initialization
routine is used to configure the controller blocks (see Table 28).
An IRQ output signal is available to alert the host should any of
the controllers fall out of lock during normal operation.
The AD9737A/AD9739A include two LVDS data ports (DB0
and DB1) to reduce the data interface rate to ½ the TxDAC
update rate. The host processor drives deinterleaved data with
offset binary format onto the DB0 and DB1 ports, along with
an embedded DCI clock that is synchronous with the data.
Because the interface is double data rate (DDR), the DCI clock
is essentially an alternating 0-1 bit pattern with a frequency that
is equal to ¼ the TxDAC update rate (fDAC). To simplify synch-
ronization with the host processor, the AD9737A/AD9739A
passes an LVDS clock output (DCO) that is also equal to the
DCI frequency.
The following sections discuss the various functional blocks
in more detail as well as their implications when interfacing
to external ICs and circuitry. Although a detailed description of
the various controllers (and associated SPI registers used to
configure and monitor) is also included for completeness, the
recommended SPI boot procedure can be used to ensure
reliable operation.
The AD9737A/AD9739A data receiver controller generates an
internal sampling clock for the DDR receiver such that the data
instance sampling is optimized. When enabled and configured
properly for track mode, it ensures proper data recovery between
the host and the AD9737A/AD9739A clock domains. The data
receiver controller has the ability to track several hundreds of
picoseconds of drift between these clock domains, typically caused
by supply and temperature variation.
RESET
IRQ
AD9737A/AD9739A
SDIO
SDO
CS
1.2V
SPI
DAC BIAS
SCLK
VREF
I120
As mentioned, the host processor provides the AD9737A/
AD9739A with a deinterleaved data stream such that the DB0
and DB1 data ports receive alternating samples (that is, odd/even
data streams). The AD9737A/AD9739A data assembler is used
to reassemble (that is, multiplex) the odd/even data streams
into their original order before delivery into the TxDAC for
signal reconstruction. The pipeline delay from a sample being
latched into the data port to when it appears at the DAC output
is on the order of 78 ( ) DACCLK cycles.
IOUTN
IOUTP
TxDAC
CORE
DCI
CLK DISTRIBUTIONꢀ
DLL
(DIV-BY-4)
(MU CONTROLLER)
DCO
DACCLK
Figure 157. Functional Block Diagram of the AD9737A/AD9739A
Rev.C | Page 48 of 64
Data Sheet
AD9737A/AD9739A
The maximum allowable skew and jitter out of the host
processor with respect to the DCI clock edge on each LVDS
port is calculated as follows:
LVDS DATA PORT INTERFACE
The AD9737A/AD9739A supports input data rates from 1.6 GSPS
to 2.5 GSPS using dual LVDS data ports. The interface is source
synchronous and double data rate (DDR) where the host provides
an embedded data clock input (DCI) at fDAC/4 with its rising
and falling edges aligned with the data transitions. The data
format is offset binary; however, twos complement format can
be realized by reversing the polarity of the MSB differential
trace. As shown in Figure 158, the host feeds the AD9737A/
AD9739A with deinterleaved input data into two 11-bit LVDS
data ports (DB0 and DB1) at ½ the DAC clock rate (that is,
MaxSkew + Jitter = Period(ps) − ValidWindow(ps) − Guard
= 800 ps − 344 ps − 100 ps
= 356 ps
where ValidWindow(ps) is represented by tVALID and Guard is
represented by tGUARD in Figure 159.
The minimum specified LVDS valid window is 344 ps, and a
guard band of 100 ps is recommended. Therefore, at the maxi-
mum operating frequency of 2.5 GSPS, the maximum allowable
FPGA and PCB bit skew plus jitter is equal to 356 ps.
f
DAC/2). The AD9737A/AD9739A internal data receiver controller
then generates a phase shifted version of DCI to register the
input data on both the rising and falling edges.
HOST
For synchronous operation, the AD9737A/AD9739A provides
a data clock output, DCO, to the host at the same rate as DCI
(that is, fDAC/4) to maintain the lowest skew variation between
these clock domains. The host processor has a worst case skew
between DCO and DCI that is both implementation and
process dependent. This worst case skew can also vary an
additional 30% over temperature and supply corners. The delay
line within the data receiver controller can track a 1.5 ns skew
variation after initial lock. While it is possible for the host to
have an internal PLL that generates a synchronous fDAC/4 from
which the DCI signal is derived, digital implementations that
result in the shortest propagation delays result in the lowest
skew variation.
AD9737A/AD9739A
PROCESSOR
EVEN DATA
SAMPLES
14 × 2
fDATA
= fDAC/2
ODD DATA
SAMPLES
14 × 2
1 × 2
DCI
fDCI
=
fDAC/4
1 × 2
fDCO fDAC/4
DCO
fDAC
DIV-BY-4
The data receiver controller is used to ensure proper data hand-
off between the host and AD9737A/AD9739A internal digital
clock domains. The circuit shown in Figure 160 functions as a
delay lock loop in which a 90° phase shifted version of the DCI
clock input is used to sample the input data into the DDR receiver
registers. This ensures that the sampling instance occurs in the
middle of the data pattern eyes (assuming matched DCI and
DBx[13:0] delays). Note that, because the DCI delay and sample
delay clocks are derived from the DIV-BY-4 circuitry, this 90°
phase relationship holds as long as the delay settings (that is,
DCI_DEL in Register 0x13 and Register 0x14, and SMP_DEL in
Register 0x11 and Register 0x12) are also matched.
=
Figure 158. Recommended Digital Interface Between the AD9737A/AD9739A
and Host Processor
As shown in Figure 159, the DCI clock edges must be coincident
with the data bit transitions with minimum skew, jitter, and
intersymbol interference. To ensure coincident transitions with
the data bits, the DCI signal should be implemented as an
additional data line with an alternating (010101…) bit sequence
from the same output drivers used for the data. Maximizing the
opening of the eye in both the DCI and data signals improves
the reliability of the data port interface. Differential controlled
impedance traces of equal length (that is, delay) should also be
used between the host processor and AD9737A/AD9739A
input to limit bit-to-bit skew.
2 × 1/f
DAC
DCI
tVALID
+ tGUARD
max skew
+ jitter
tVALID
DB0[13:0]
AND DB1[13:0]
Figure 159. LVDS Data Port Timing Requirements
Rev.C | Page 49 of 64
AD9737A/AD9739A
Data Sheet
DATA RECEIVER CONTROLLER
DCI WINDOW PRE
DDR
FF
DCI
FINE
DELAY
DELAY
DELAY
DCI
DELAY
PATH
PRE
DCI DELAY
DDR DCI WINDOW POST
FF
0
90
180
270
STATE MACHINE/
TRACKING LOOP
FINE
DELAY
DIV-BY-4
F
DAC
POST
SAMPLE
DELAY
DCI WINDOW SAMPLE
DDR
FF
SAMPLE
DELAY
PATH
FINE
DELAY
DELAY
DELAY
SAMPLE
DATA TO
CORE
DDR
FF
DDR
FF
DDR
FF
DDR
FF
DBx[13:1]
ELASTIC FIFO
DCO
Figure 160. Top Level Diagram of the Data Receiver Controller
The DIV-BY-4 circuit generates four clock phases that serve as
inputs to the data receiver controller. All DDR registers in the
data and DCI paths operate on both clock edges; however, for
clarity purposes, only the phases (that is, 0° and 90°) corresponding
to the positive edge of each path are shown. One of the DIV-BY-
4 phases is used to generate the DCO signal; therefore, the phase
relationship between DCO and clocks fed into the controller
remains fixed. Note that it is this attribute that allows possible
factory calibration of images and clock spurs that are attributed
to fDAC/4 modulation of the critical DAC clock.
The skew or window width (FINE_DEL_SKEW) is set via
Register 0x13, Bits[3:0], with a maximum skew of approximately
300 ps and resolution of 12 ps. It is recommended that the skew
be set to 36 ps (that is, Register 0x13 = 0x72) during initialization.
Note that the skew setting also affects the speed of the controller
loop, with tighter skew settings corresponding to longer
response time.
Data Receiver Controller Initialization Description
The data controller should be initialized and placed into track
mode as the second step in the SPI boot sequence. The following
steps are recommended for the initialization of the data receiver
controller:
After this data has been successively sampled into the first set of
registers, an elastic FIFO is used to transfer the data into the
AD9737A/AD9739A clock domain. To track any phase variation
continuously between the two clock domains, the data receiver
controller should always be enabled and placed into track mode
(Register 0x10, Bit 1 and Bit 0). Tracking mode operates cont-
inuously in the background to track delay variations between
the host and AD9737A/AD9739A clock domains. It does so by
ensuring that the DCI signal is sampled within a very narrow
window defined by two internally generated clocks (that is, PRE
and PST), as shown in Figure 161. Note that proper sampling of
the DCI signal can also be confirmed by monitoring the status
of DCI_PRE_PH0 (Register 0x0C, Bit 2) and DCI_PST_PH0
(Register 0x0C, Bit 0). If the delay settings are correct, the state
of DCI_ PRE_PH0 should be 0, and the state of DCI_PST_PH0
should be 1.
1. Set FINE_DEL_SKEW to 2 for a larger DCI sampling window
(Register 0x13 = 0x72). Note that the default DCI_DEL and
SMP_DEL settings of 167 are optimum.
2. Disable the controller before enabling (that is, Register 0x10
= 0x00).
3. Enable the Rx controller in two steps: Register 0x10 = 0x02
followed by Register 0x10 = 0x03.
4. Wait 135 k clock cycles.
5. Read back Register 0x21 and confirm that it is equal to
0x05 to ensure that the DLL loop is locked and tracking.
6. Read back the DCI_DEL value to determine whether the
value falls within a user defined tracking guard band. If it
does not, go back to Step 2.
DCI
FINE DELAY
PST
FINE DELAY
PRE
FINE_DEL_SKEW
Figure 161. Pre- and Post-Delay Sampling Diagram
Rev.C | Page 50 of 64
Data Sheet
AD9737A/AD9739A
After the controller is enabled during the initial SPI boot process
(see Table 29), the controller enters a search mode where it
seeks to find the closest rising edge of the DCI clock (relative to
a delayed version of an internal fDAC/4 clock) by simultaneously
adjusting the delays in the clocks used to register the DCI and
data inputs. A state machine searches above and below the
initial DCI_DEL value. The state machine first searches for the
first rising edge above the DCI_DEL and then searches for the
first rising edge below the DCI_DEL value. The state machine
selects the closest rising edge and then enters track mode. It is
recommended that the default midpoint delay setting (that is,
Decimal 167) for the DCI_DEL and SMP_DEL bits be kept to
ensure that the selected edge remains closest to the delay line
midpoint, thus providing the greatest range for tracking timing
variations and preventing the controller from falling out of lock.
The data receiver controller can also be configured to generate
an interrupt request (IRQ) upon losing lock. Losing lock can be
caused by disruption of the main DAC clock input or loss of a
power supply rail. To service the interrupt, the host can poll the
RCVR_LCK bit (Bit 0, Recister 0x21) to determine the current
state of the controller. If this bit is cleared, the search/track
procedure can be restarted by setting the RCVR_LOOP_ON bit
(Bit 1) in Register 0x10. After waiting the required lock time, the
host can poll the RCVR_LCK bit to see if it has been set. Before
leaving the interrupt routine, the RCVR_FLG_RST bit (Bit 2,
Register 0x10) should be reset by writing a high followed by a
low.
LVDS Driver and Receiver Input
The AD9737A/AD9739A feature an LVDS-compatible driver
and receivers. The LVDS driver output used for the DCO signal
includes an equivalent 200 Ω source resistor that limits its nominal
output voltage swing to 200 mV when driving a 100 Ω load.
The DCO output driver can be powered down via Register 0x01,
Bit 5. An equivalent circuit is shown in Figure 162.
VDD33
The adjustable delay span for these internal clocks (that is, DCI and
sample delay) is nominally 4 ns. The 10-bit delay value is user
programmable from the decimal equivalent code (0 to 384)
with approximately 12 ps/LSB resolution via the DCI_DEL
(Register 0x13 and Register 0x14)and SMP_DEL registers
(Register 0x11 and Register 0x12). When the controller is enabled,
it overwrites these registers with the delay value it converges
upon. The minimum difference between this delay value and
the minimum/maximum values (that is, 0 and 384) represents
the guard band for tracking. Therefore, if the controller initially
converges upon a DCI_DEL and SMP_DEL value between 80
and 3044, the controller has a guard band of at least 80 code
(approximately 1 ns) to track phase variations between the
clock domains.
V+
ESD
V–
V–
ESD
V+
100Ω 100Ω
DCO_P
DCO_N
VCM
VSS
Figure 162. Equivalent LVDS Output
On initialization of the AD9737A/AD9739A, a certain period of
time is required for the data receiver controller to establish a lock
of the DCI clock signal. Note that, due to its dependency on the
Mu controller, the data receiver controller should be enabled
only after the Mu controllers have been enabled and established
lock. All of the internal controllers operate at a submultiple of
the DAC update rate. The number of fDAC clock cycles required
to lock onto the DCI clock is typically 70 k clock cycles but can
be up to 135 k clock cycles. During the SPI initialization process,
the user has the option of polling Register 0x21 (Bit 0, Bit 1, and
Bit 3) to determine if the data receiver controller is locked, has
lost lock, or has entered into track mode before completing the
boot sequence. Alternatively, the appropriate IRQ bit (Register 0x03
and Register 0x04) can be enabled such that an IRQ output signal
is generated upon the controller establishing lock.
VDD33
100Ω
DCI_P
DBx[13:0]P
DCI_N
DBx[13:0]N
ESD
ESD
VSS
Figure 163. AD9739A Equivalent LVDS Input
Rev.C | Page 51 of 64
AD9737A/AD9739A
Data Sheet
14-BIT
DATA
14-BIT
DATA
The LVDS receivers include 100 Ω termination resistors, as shown
in Figure 163. These receivers meet the IEEE-1596.3-1996
reduced swing specification (with the exception of input hysteresis,
which cannot be guaranteed over all process corners). Figure 164
and Table 26 show an example of nominal LVDS voltage levels
seen at the input of the differential receiver with resulting
common-mode voltage and equivalent logic level. Note that
the AD9737A/AD9739A LVDS inputs do not include fail-safe
capability; hence, any unused input should be biased with an
external circuit or static driver. The LVDS receivers can be
powered-down via Register 0x01, Bit 4.
IOUTP
DIGITAL
ANALOG
CIRCUITRY
CIRCUITRY
IOUTN
MU
DELAY
PHASE
DETECTOR
MU
DELAY
DAC
CLOCK
CONTROLLER
Figure 165. AD97339A Mu Delay Controller Block Diagram
The Mu controller adjusts the timing relationship between the
digital and analog domains via a tapped digital delay line having
a nominal total delay of 864 ps. The delay value is programmable
to a 9-bit resolution (that is, 0 to 432 decimal) via the MUDEL
bits (Register 0x27 and 0x28), resulting in a nominal resolution
of 2 ps/LSB. Because a time delay maps to a phase offset for a
fixed clock frequency, the control loop essentially compares the
phase relationship between the two clock domains and adjusts
the phase (that is, via a tapped delay line) of the digital clock such
that it is at the desired fixed phase offset (SET_PHS) from the
critical analog clock.
LVDS INPUTS
(NO FAIL-SAFE)
V
LVDS
RECEIVER
V
COM
= (V + V )/2
100Ω
P,N
P
N
V
V
P
N
GND
Example
V
V
1.4V
P
1.0V
0.4V
18
N
V
P
N
16
GUARD
BAND
0V
GUARD
BAND
14
12
10
8
V
–0.4V
LOGIC 1
LOGIC BIT
EQUIVALENT
DESIRED
PHASE
LOGIC 0
Figure 164. LVDS Data Input Levels
6
Table 26. Example of LVDS Input Levels
Resulting
Common-
Differential Mode
4
SEARCH STARTING
LOCATION
Resulting
2
Logic Bit
Binary
Equivalent
0
Applied Voltages
Voltage
Voltage
0
40
80 120 160 200 240 280 320 360 400 440
MU DELAY
VP
VN
VP, N
VCOM
1.4 V
1.0 V
1.0 V
0.8 V
1.0 V
1.4 V
0.8 V
1.0 V
+0.4 V
1.2 V
1
0
1
0
Figure 166. Typical Mu Phase Characteristic Plot at 2.4 GSPS
−0.4 V
1.2 V
Figure 166 maps the typical Mu phase characteristic at 2.4 GSPS vs.
the 9-bit digital delay setting (MUDEL). The Mu phase scaling
is such that a value of 16 corresponds to 180 degrees. The critical
keep-out window between the digital and analog domains occurs
at a value of 0 (but can extend out to 2 depending on the clock
rate). The target Mu phase (and slope) is selected to provide
optimum ac performance while ensuring that the Mu controller
for any device can establish and maintain lock. For example,
although a slope and phase setting of −6 is considered optimum
for operation between 1.6 GSPS and 2.5 GSPS, other values are
required below 1.6 GSPS.
+200 mV
−200 mV
900 mV
900 mV
MU CONTROLLER
A delay lock loop (DLL) is used to optimize the timing between
the internal digital and analog domains of the AD9737A/AD9739A
such that data is successfully transferred into the TxDAC core at
rates of up to 2.5 GSPS. As shown in Figure 165, the DAC clock
is split into an analog and a digital path with the critical analog
path leading to the DAC core (for minimum jitter degradation)
and the digital path leading to a programmable delay line. Note that
the output of this delay line serves as the master internal digital
clock from which all other internal and external digital clocks
are derived. The amount of delay added to this path is under the
control of the Mu controller, which optimizes the timing between
these two clock domains and continuously tracks any variation
(once in track mode) to ensure proper data hand-off.
Rev.C | Page 52 of 64
Data Sheet
AD9737A/AD9739A
18
band setting of 11 (that is, Register 0x29 = 0xCB) corresponds
to 88 LSBs, thus providing sufficient margin.
NOM_P1
SLOW_P1
FAST_P1
16
14
12
10
8
Mu Controller Initialization Description
The Mu controller must be initialized and placed into track mode
as a first step in the SPI boot sequence. The following steps are
required for initialization of the Mu controller. Note that the
AD9737A/AD9739A data sheet specifications and characterization
data are based on the following Mu controller settings:
6
4
1. Turn on the phase detector with boost (Register 0x24 = 0x30).
2. Enable the Mu delay controller duty-cycle correction
circuitry and specify the recommended slope for phase.
(that is, Register 0x25 = 0x80 corresponds to a negative slope).
3. Specify search/track mode with a recommended target
phase, SET_PHS, of 6 (for example) and an initial
MUDEL[8:0] setting of 216 (Register 0x27 = 0x46 and
Register 0x28 = 0x6C).
4. Set search tolerance to exact, and retry if the search fails its
initial attempt. Also, set the guard band to the recommended
setting of 11 (Register 0x29 = 0xCB).
5. Set the Mu controller tracking gain to the recommended
setting and enable the Mu controller state machine
(Register 0x26 = 0x03).
2
0
0
40
80 120 160 200 240 280 320 360 400 440
DELAY LINE TAP
Figure 167. Mu Phase Characteristics of Three Devices from Different Process
Lots at 1.2 GSPS
The Mu phase characteristics can vary significantly among devices
due to gm variations in the digital delay line that are sensitive to
process skews, along with temperature and supply. As a result,
careful selection of the target phase location is required such that
the Mu controller can converge upon this phase location for all
devices.
Figure 167 shows the Mu phase characteristics of three devices
at 25°C from slow, nominal, and fast skew lots at 1.2 GSPS. Note
that a −6 Mu phase setting does not map to any delay line tap
setting for the fast process skew case; therefore, another target Mu
phase is recommended at this clock rate.
On completion of the last step, the Mu controller begins a search
algorithm that starts with an initial delay setting specified by the
MUDEL bits (that is, 216, which corresponds to the midpoint of
the delay line). The initial search algorithm works by sweeping
through different Mu delay values in an alternating manner until
the desired phase (that is, a SET_PHS of 4) is exactly measured.
When the desired phase is measured, the slope of the phase
measurement is then calculated and compared against the
specified slope (slope = negative).
Table 27 provides a list of recommended Mu phase/slope settings
over the specified clock range of the AD9737A/AD9739A based
on the considerations previously described. These values should
be used to ensure robust operation of the Mu controller.
Table 27. Recommended Target Mu Phase Settings vs. Clock Rate
Clock Rate (GSPS)
If everything matches, the search algorithm is finished. If not, the
search continues in both directions until an exact match is found
or a programmable guard band is reached in one of the directions.
When the guard band is reached, the search still continues but
only in the opposite direction. If the desired phase is not found
before the guard band is reached in the second direction, the search
changes back to the alternating mode and continues looking
within the guard band. The typical locking time for the Mu
controller is approximately 180 k DAC cycles (at 2 GSPS ~ 75 µs).
Slope
Mu Phase
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
−
−
+
+
+
−
−
−
−
6
4
5
8
12
12
10
8
The search fails if the Mu delay controller reaches the endpoints.
The Mu controller can be configured to retry (Register 0x29,
Bit 6) the search or stop. For applications that have a micro-
controller, the preferred approach is to poll the MU_LKD status
bit (Register 0x2A, Bit 0) after the typical locking time has expired.
This method lets the system controller check the status of other
system parameters (that is, power supplies and clock source)
before reattempting the search (by writing 0x03 to Register 0x26).
1.6 to 2.5
6
After the Mu controller completes its search and establishes lock
on the target Mu phase, it attempts to maintain a constant timing
relationship between the two clock domains over the specified
temperature and supply range. If the Mu controller requests a Mu
delay setting that exceeds the tapped delay line range (that is, <0
or >432), the Mu controller can lose lock, causing possible system
disruption (that is, can generate an IRQ or restart the search). To
avoid this scenario, symmetrical guard bands are recommended at
each end of the Mu delay range. The guard band scaling is such
that one LSB of Guard[4:0] (Register 0x29) corresponds to eight
LSBs of MUDEL[8:0] (Register 0x28). The recommended guard
Rev.C | Page 53 of 64
AD9737A/AD9739A
Data Sheet
For applications that do not have polling capabilities, the Mu
controller state machine should be reconfigured to restart the
search, such that lock can be re-attempted with system conditions
that may have changed and be different, and thus may enable
the controller to lock.
should validate the present status of the suspect controller by
reading back its current status bits, which are available in
Register 0x21 and/or Register 0x2A. Based on the status of these
bits, the host can take appropriate action, if required, to
reestablish lock. To clear an IRQ after servicing, it is necessary
to reset relevant bits in Register 0x03 by writing 0 followed by
another write of 1 to reenable. A detailed diagram of the
interrupt circuitry is shown in Figure 168.
After the Mu delay value is found that exactly matches the desired
Mu phase setting and slope (for example, 6 with a negative slope),
the Mu controller goes into track mode. In this mode, the Mu
controller makes slight adjustments to the delay value to track any
variations between the two clock paths due to temperature, time,
and supply variations. Two status bits, MU_LKD (Register 0x2A,
Bit 0) and MU_LST (Register 0x2A, Bit 1) are available to the
user to signal the existing status control loop. If the current
phase is more than four steps away from the desired phase, the
MU_LKD bit is cleared, and if the lock acquired was previously
set, the MU_LST bit is set. Should the phase deviation return to
within three steps, the MU_LKD bit is set again while the MU_LST
is cleared. Note that this sort of event may occur if the main
clock input (that is, DACCLK) is disrupted or the Mu controller
exceeds the tapped delay line range (that is, <0 or >432).
(PIN F13)
SPI ISR
INT
D
INT(n)
SOURCE
SPI
DATA
Q
READ DATA
INT
SOURCE
SPI WRITE
SCLK
SPI ADDRESS
IMR
DATA = 1
Figure 168. Interrupt Request Circuitry
It is also possible to use the IRQ during the AD9737A/AD9739A
initialization phase after power-up to determine when the Mu
and data receiver controllers have achieved lock. For example,
before enabling the Mu controller, the MU_LCK_EN bit can be set
and the IRQ output signal monitored to determine when lock has
been established before continuing in a similar manner with the
data receiver controllers. Note that the relevant LCK bit should
be cleared before continuing to the next controller. After all
controllers are locked, the lost lock enable bits (that is,
x_LST_EN) should be set.
If lock is lost, the Mu controller has the option of remaining in
the tracking loop or resetting and starting the search again via
the CONTRST bit (Register 0x29, Bit 5). Continued tracking is
the preferred state because it is the least disruptive to a system
in which the AD9737A/AD9739A temporarily loses lock. The
user can poll the Mu delay and phase value by first setting the
read bit high (Register 0x26, Bit 3). After the read bit is set, the
MUDEL[8:0] bits and the SET_PHS[4:0] bits (Register 0x27
and Register 0x28) that the controller is currently using can be
read.
Table 28. Interrupt Request Registers
Address (Hex)
Bit
Description
MU_LST_EN
MU_LCK_EN
RCV_LST_EN
RCV_LCK_EN
MU_LST_IRQ
MU_LCK_IRQ
RCV_LST_IRQ
RCV_LCK_IRQ
RCVR_TRK_ON
RCVR_LST
0x03
3
INTERRUPT REQUESTS
2
The AD9737A/AD9739A can provide the host processor with
an interrupt request output signal (IRQ) that indicates that one
or more of the AD9737A/AD9739A internal controllers have
achieved lock or lost lock. These controllers include the Mu, data
receiver, and synchronization controllers. The host can then
poll the IRQ status register (Register 0x04) to determine which
controller has lost lock. The IRQ output signal is an active high
output signal available on Pin F13. If used, its output should be
connected via a 10 kΩ pull-up resistor to VDD33.
1
0
0x04
3
2
1
0
0x21
0x2A
3
1
0
RCVR_LCK
Each IRQ is enabled by setting the enable bits in Register 0x03,
which purposely has the same bit mapping as the IRQ status bits in
Register 0x04. Note that these IRQ status bits are set only when
the controller transitions from a false to true state. Hence, it is
possible for the x_LCK_IRQ and x_LST_IRQ status bits to be set
when a controller temporarily loses lock but is able to reestablish
lock before the IRQ is serviced by the host. In this case, the host
1
MU_LST
0
MU_LKD
Rev.C | Page 54 of 64
Data Sheet
AD9737A/AD9739A
ANALOG INTERFACE CONSIDERATIONS
ANALOG MODES OF OPERATION
INPUT
DATA
D
D
D
D
D
D
D
D
D
D
10
1
2
3
4
5
6
7
8
9
DACCLK_x
The AD9737A/AD9739A use the quad-switch architecture
shown in Figure 169. The quad-switch architecture masks the
code-dependent glitches that occur in a conventional two-switch
DAC. Figure 170 compares the waveforms for a conventional
DAC and the quad-switch DAC. In the two-switch architecture,
a code-dependent glitch occurs each time the DAC switches to
a different state (that is, D1 to D2). This code-dependent glitching
causes an increased amount of distortion in the DAC. In quad-
switch architecture (no matter what the codes are), there are
always two switches transitioning at each half clock cycle, thus
eliminating the code-dependent glitches. However, a constant
glitch occurs at 2 × DACCLK_x because half the internal switches
change state on the rising DACCLK_x edge whereas the other
half change state on the falling DACCLK_x edge.
D
–D
8
3
D
D
–D
–D
9
2
4
7
D
D
–D
–D
10
1
5
6
FOUR-SWITCH
DAC OUTPUT
t
(
fS MIX MODE)
D
–D
5
D
10
–D
6
1
–D
–D
D
D
9
2
4
7
–D
D
8
3
Figure 171. Mix-Mode DAC Waveforms
Figure 171 shows the DAC waveforms for mix-mode. This ability
to change modes provides the user the flexibility to place a
carrier anywhere in the first two Nyquist zones, depending
on the operating mode selected. Switching between the analog
modes reshapes the sinc roll-off that is inherent at the DAC output.
The maximum amplitude in both Nyquist zones is impacted by
this sinc roll-off, depending on where the carrier is placed (see
Figure 172). As a practical matter, the usable bandwidth in the
third Nyquist zone becomes limited at higher DAC clock rates
(that is, >2 GSPS) when the output bandwidth of the DAC core
and the interface network (that is, balun) contributes to
additional roll-off.
VDD
DACCLK_x
CLK
V
V
V
V
1
2
3
4
G
G
G
V
1
V
2
V
3
V 4
G
LATCHES
G
G
G
DBx[13:0]
G
FIRST
NYQUIST ZONE
SECOND
NYQUIST ZONE
THIRD
NYQUIST ZONE
IOUTP
IOUTN
0
–5
Figure 169. AD9739A Quad-Switch Architecture
MIX MODE
INPUT
D
D
D
D
D
D
D
D
D
D
D
D
1
2
3
4
5
6
7
8
9
10
DATA
–10
–15
–20
–25
–30
–35
DACCLK_x
NORMAL
MODE
D
D
D
3
D
D
t
t
1
2
4
5
TWO-SWITCH
DAC OUTPUT
D
D
D
6
7
8
9
10
FOUR-SWITCH
DAC OUTPUT
(NORMAL MODE)
D
D
D
D
D
10
6
7
8
9
D
D
D
D
D
5
1
2
3
4
0FS
0.25FS
0.50FS
0.75FS
1.00FS
1.25FS
1.50FS
Figure 170. Two-Switch and Quad-Switch DAC Waveforms
FREQUENCY (Hz)
Another attribute of the quad-switch architecture is that it also
enables the DAC core to operate in one of the following two
modes: normal mode and mix-mode. The mode is selected via
SPI Register 0x08, Bits[1:0], with normal mode being the default
value. In the mix-mode, the output is effectively chopped at the
DAC sample rate. This has the effect of reducing the power of
the fundamental signal while increasing the power of the images
centered around the DAC sample rate, thus improving the
output power of these images.
Figure 172. Sinc Roll-Off for Each Analog Operating Mode
Rev.C | Page 55 of 64
AD9737A/AD9739A
Data Sheet
CLOCK INPUT CONSIDERATIONS
AD9737A/AD9739A
V
V
V
CC
REF
ADCLK914
T
50Ω 50Ω
50Ω
50Ω
10nF
10nF
100Ω
10nF
D
D
50Ω
Q
Q
DACCLK_P
DACCLK_N
10nF
50Ω
V
EE
Figure 173. ADCLK914 Interface to the AD9737A/AD9739A CLK Input
AD9737A/AD9739A
3.9nH
V
VCO
ADF4350
1nF
RF
RF
A+
A–
OUT
DACCLK_P
N
DIV-BY-2
N = 0 – 4
PLL
100Ω
1.8V p-p
VCO
1nF
DACCLK_N
FREF
OUT
RF
RF
A+
A–
OUT
OUT
Figure 174. ADF4350 Interface to the AD9737A/AD9739A CLK Input
The quality of the clock source and its drive strength are important
considerations in maintaining the specified ac performance.
The phase noise and spur characteristics of the clock source
should be selected to meet the target application requirements.
Phase noise and spurs at a given frequency offset on the clock
source are directly translated to the output signal. It can be shown
that the phase noise characteristics of a reconstructed output
Figure 174 shows a clock source based on the ADF4350 low phase
noise/jitter PLL. The ADF4350 can provide output frequencies
from 140 MHz up to 4.4 GHz with jitter as low as 0.5 ps rms.
Each single-ended output can provide a squared-up output
level that can be varied from −4 dBm to +5 dBm, allowing for
>2 V p-p output differential swings. The ADF4350 also includes
an additional CML buffer that can be used to drive another
AD9737A/AD9739A device.
sine wave are related to the clock source by 20 × log10(fOUT/fCLK
when the DAC clock path contribution, along with thermal and
quantization effects, are negligible.
)
VDDC
4-BIT PMOS
IOUT ARRAY
The AD9737A/AD9739A clock receiver provides optimum jitter
performance when driven by a fast slew rate originating from
the LVPECL or CML output drivers. For a low jitter sinusoidal
clock source, the ADCLK914 can be used to square-up the signal
and provide a CML input signal for the AD9737A/AD9739A
clock receiver. Note that all specifications and characterization
presented in the data sheet are with the ADCLK914 driven by a
high quality RF signal generator with the clock receiver biased at
an 800 mV level.
CLKx_OFFSET
DIR_x = 0
DACCLK_P
ESD
DACCLK_N
CLKx_OFFSET
DIR_x = 0
4-BIT NMOS
IOUT ARRAY
VSSC
Figure 175. Clock Input and Common-Mode Control
Rev.C | Page 56 of 64
Data Sheet
AD9737A/AD9739A
The AD9737A/AD9739A clock receiver features the ability to
independently adjust the common-mode level of its inputs over
a span of 100 mV centered about its mid-supply point (that is,
VDDC/2), as well as an offset for hysteresis purposes. Figure 175
shows the equivalent input circuit of one of the inputs. ESD
diodes are not shown for clarity purposes. It has been found
through characterization that the optimum setting is for both
inputs to be biased at approximately 0.8 V. This can be achieved
by writing a 0x0F (corresponding to a −15) setting to both cross
controller registers (that is, Register 0x22 and Register 0x23).
•
An external reference can be used to overdrive the internal
reference by connecting it to the VREF pin.
I
OUTFS can be adjusted digitally over 8.7 mA to 31.7 mA by using
FSC[9:0] (Register 0x06 and Register 0x07).
The following equation relates IOUTFS to the FSC[9:0] bits, which
can be set from 0 to 1023.
I
OUTFS = 22.6 × FSC[9:0]/1000 + 8.7
(1)
Note that a default value of 0x200 generates 20 mA full scale, which
is used for most of the characterization presented in this data
sheet (unless noted otherwise).
1.10
CLKP
CLKN
1.05
ANALOG OUTPUTS
Equivalent DAC Output and Transfer Function
1.00
0.95
0.90
0.85
0.80
0.75
0.70
The AD9737A/AD9739A provide complementary current
outputs, IOUTP and IOUTN, that source current into an external
ground reference load. Figure 178 shows an equivalent output
circuit for the DAC. Note that, compared to most current output
DACs of this type, the AD9737A/AD9739A outputs exhibit a
slight offset current (that is, IOUTFS/16), and the peak differential
ac current is slightly below IOUTFS/2 (that is, 15/32 × IOUTFS).
–15 –13 –11 –9 –7 –5 –3 –1
1
3
5
7
9 11 13 15
OFFSET CODE
I
= 8.6 – 31.2mA
OUTFS
Figure 176. Common-Mode Voltage with Respect to
CLKP_OFFSET/CLKN_OFFSET and DIR_P/DIR_N
17/32 × I
OUTFS
VOLTAGE REFERENCE
I =
PEAK
15/32 × I
OUTFS
AC
2.2pF
70Ω
The AD9737A/AD9739A output current is set by a combination
of digital control bits and the I120 reference current, as shown
in Figure 177.
17/32 × I
OUTFS
AD9737A/AD9739A
Figure 178. Equivalent DAC Output Circuit
FSC[9:0]
V
BG
DAC
1.2V
As shown in Figure 178, the DAC output can be modeled as a
pair of dc current sources that source a current of 17/32 × IOUTFS to
each output. A differential ac current source, IPEAK, is used to
model the signal-dependent nature of the DAC output. The
polarity and signal dependency of this ac current source are
related to the digital code by the following equation:
VREF
I120
–
+
CURRENT
SCALING
1nF
IFULL-SCALE
10kΩ
I120
VSSA
F(Code) = (DACCODE − 8192)/8192
−1 < F(Code) < 1
(2)
(3)
Figure 177. Voltage Reference Circuit
The reference current is obtained by forcing the band gap voltage
across an external 10 kΩ resistor from I120 (Pin B14) to ground.
The 1.2 V nominal band gap voltage (VREF) generates a 120 µA
reference current in the 10 kΩ resistor. Note the following
constraints when configuring the voltage reference circuit:
where DACCODE = 0 to 16,383 (decimal).
Because IPEAK can swing (15/32) × IOUTFS, the output currents
measured at IOUTP and IOUTN can span from IOUTFS/16 to IOUTFS
However, because the ac signal-dependent current component
is complementary, the sum of the two outputs is always constant
(that is, IOUTP + IOUTN = (34/32) × IOUTFS).
.
•
•
•
Both the 10 kΩ resistor and 1 nF bypass capacitor are required
for proper operation.
Digitally adjust the DAC’s output full-scale current, IOUTFS
from its default setting of 20 mA.
,
The AD9737A/AD9739A are not a multiplying DAC.
Modulating the reference current, I120, with an ac signal is
not supported.
•
The band gap voltage appearing at the VREF pin (Pin C14)
must be buffered for use with an external circuitry because
its output impedance is approximately 5 kΩ.
Rev.C | Page 57 of 64
AD9737A/AD9739A
Data Sheet
The code-dependent current measured at the IOUTP and
IOUTN outputs is as follows:
If the AD9737A/AD9739A are programmed for IOUTFS = 20 mA,
the peak ac current is 9.375 mA and the peak power delivered to
the equivalent load is 2.2 mW (that is, P = I2R). Because the source
and load resistance seen by the 1:1 balun are equal, this power is
shared equally; therefore, the output load receives 1.1 mW or
0.4 dBm.
IOUTP = 17/32 × IOUTFS + 15/32 × IOUTFS × F(Code)
IOUTN = 17/32 × IOUTFS − 15/32 × IOUTFS × F(Code)
(4)
(5)
Figure 179 shows the IOUTP vs. DACCODE transfer function
when IOUTFS is set to 19.65 mA.
To calculate the rms power delivered to the load, the following
must be considered:
20
18
16
14
12
10
8
•
•
•
Peak-to-rms of the digital waveform
Any digital backoff from digital full scale
The DAC’s sinc response and nonideal losses in external
network
For example, a reconstructed sine wave with no digital backoff
ideally measures −2.6 dBm because it has a peak-to-rms ratio of
3 dB. If a typical balun loss of 0.4 dBm is included, −3 dBm of
actual power can be expected in the region where the sinc response
of the DAC has negligible influence. Increasing the output
power is best accomplished by increasing IOUTFS, although any
degradation in linearity performance must be considered
acceptable for the target application.
6
4
2
0
0
4096
8192
12,288
16,384
DAC CODE
Figure 179. Gain Curve for FSC[9:0] = 512, DAC OFFSET = 1.228 mA
Peak DAC Output Power Capability
The maximum peak power capability of a differential current
output DAC is dependent on its peak differential ac current, IPEAK
and the equivalent load resistance it sees. Because the AD9737A/
,
AD9739A include a differential 70 Ω resistance, it is best to use
a doubly terminated external output network similar to what is
shown in Figure 181. In this case, the equivalent load seen by
the ac current source of the DAC is 25 Ω.
R
SOURCE
= 50Ω
I
= 8.6 – 31.2mA
OUTFS
=
LOSSLESS
BALUN
1:1
I
R
PEAK
15/32 × I
LOAD
= 50Ω
AC
70Ω
180Ω
OUTFS
Figure 180. Equivalent Circuit for Determining Maximum Peak Power
to a 50 Ω Load
Rev.C | Page 58 of 64
Data Sheet
AD9737A/AD9739A
Figure 183 shows an interface that can be considered when
interfacing the DAC output to a self-biased differential gain
block. The inductors shown serve as RF chokes (L) that provide
the dc bias path to analog ground. The value of the inductor, along
with the dc blocking capacitors (C), determines the lower cutoff
frequency of the composite pass-band response. An RF balun
should also be considered before the RF differential gain stage and
any filtering to ensure symmetrical common-mode impedance
seen by the DAC output while suppressing any common mode
noise, harmonics, and clock spurs prior to amplification.
OPTIONAL BALUN AND FILTER
OUTPUT STAGE CONFIGURATION
The AD9737A/AD9739A are intended to serve high dynamic
range applications that require wide signal reconstruction
bandwidth (that is, DOCSIS CMTS) and/or high IF/RF signal
generation. Optimum ac performance can be realized only if
the DAC output is configured for differential (that is, balanced)
operation with its output common-mode voltage biased to
analog ground. The output network used to interface to the
DAC should provide a near 0 Ω dc bias path to analog ground.
Any imbalance in the output impedance between the IOUTP
and IOUTN pins results in asymmetrical signal swings that
degrade the distortion performance (mostly even order) and noise
performance. Component selection and layout are critical in
realizing the performance potential of the AD9737A/AD9739A.
IOUTP
C
90Ω
L
RF DIFF
AMP
C
70Ω
LPF
90Ω
L
IOUTN
®
MINI-CIRCUITS
TC1-33-75G+
IOUTP
Figure 183. Interfacing the DAC Output to the Self-Biased Differential
Gain Stage
90Ω
70Ω
For applications operating the AD9737A/AD9739A in mix-mode
with output frequencies extending beyond 2.2 GHz, the circuits
shown in Figure 184 should be considered. The circuit in
Figure 184 uses a wideband balun with a configuration similar
to the one shown in Figure 183 to provide a dc bias path for the
DAC outputs. The circuit in Figure 185 takes advantage of ceramic
chip baluns to provide a dc bias path for the DAC outputs while
providing excellent amplitude/phase balance over a narrower
RF band. These low cost, low insertion loss baluns are available
for different popular RF bands and provide excellent amplitude/
phase balance over their specified frequency range.
IOUTN
90Ω
Figure 181. Recommended Balun for Wideband Applications with Upper
Bandwidths of up to 2.2 GHz
Most applications requiring balanced-to-unbalanced conversion
can take advantage of the Ruthroff 1:1 balun configuration
shown in Figure 181. This configuration provides excellent
amplitude/phase balance over a wide frequency range while
providing a 0 Ω dc bias path to each DAC output. Also, its design
provides exceptional bandwidth and can be considered for
applications requiring signal reconstruction of up to 2.2 GHz.
The characterization plots shown in this data sheet are based
on the AD9737A/AD9739A evaluation board, which uses this
configuration. Figure 182 compares the measured frequency
response for normal and mix-mode using the AD9737A/AD9739A
evaluation board vs. the ideal frequency response.
MINI-CIRCUITS
TC1-1-462M
C
IOUTP
90Ω
90Ω
L
L
70Ω
IOUTN
C
Figure 184. Recommended Mix-Mode Configuration Offering Extended RF
Bandwidth Using a TC1-1-43A+ Balun
0
IDEAL BASEBAND MODE
–3
MURATA
JOHANSON TECHNOLOGY
CHIP BALUNS
BASEBAND
TC1-33-75G
–6
–9
IOUTP
MIX MODE
TC1-33-75G
–12
–15
–18
–21
–24
–27
–30
–33
–36
70Ω
180Ω
IDEAL MIX MODE
IOUTN
Figure 185. Lowest Cost and Size Configuration for Narrow RF Band
Operation
0
500
1000
1500
2000
2500
3000
3500
FREQUENCY (MHz)
Figure 182. Measured vs. Ideal Frequency Response for Normal (Baseband)
and Mix-Mode Operation Using a TC1-33-75G Transformer on
the AD9737A/AD9739A EVB
Rev.C | Page 59 of 64
AD9737A/AD9739A
Data Sheet
3. Images appear as replicas of the original signal, hence, can
be easier to identify. In the case of the AD9737A/AD9739A,
internal modulation of the sampling clock at intervals
NONIDEAL SPECTRAL ARTIFACTS
The AD9737A/AD9739A output spectrum contains spectral
artifacts that are not part of the original digital input waveform.
These nonideal artifacts include harmonics (including alias
harmonics), images, and clock spurs. Figure 186 shows a spectral
plot of the AD9737A/AD9739A within the first Nyquist zone
(that is, dc to fDAC/2) reconstructing a 650 MHz, 0 dBFS sine wave
at 2.4 GSPS. Besides the desired fundamental tone at the −7.8 dBm
level, the spectrum also reveals these nonideal artifacts that also
appear as spurs above the measurement noise floor. Because
these nonideal artifacts are also evident in the second and third
Nyquist zones during mix-mode operation, the effects of these
artifacts should also be considered when selecting the DAC
clock rate for a target RF band.
related to fDAC/4 generate image pairs at ¼ × fDAC, ½ × fDAC
and ¾ × fDAC. Both upper and lower sideband images
,
associated with ¼ × fDAC fall within the first Nyquist zone,
whereas only the lower image of ½ × fDAC and ¾ × fDAC fall
back. Note that the lower images appear frequency inverted.
The ratio between the fundamental and various images (that
is, dBc) remains mostly signal independent because the
mechanism causing these images is related to corruption of
the sampling clock.
4. The magnitude of these images for a given device depends
on several factors, including DAC clock rate, output
frequency, and Mu controller phase setting. Because the
image magnitude is repeatable between power-up cycles
(assuming the same conditions), a one-time factory
calibration procedure can be used to improve suppression.
Calibration consists of additional dedicated DSP resources in
the host that can generate a replica of the image with proper
amplitude, phase, and frequency scaling to cancel the image
from the DAC. Because the image magnitude can vary
among devices, each device must be calibrated.
5. A clock spur appears at fDAC/4 and integer multiples of it.
Similar to images, the spur magnitude also depends on the
same factors that cause variations in image levels. However,
unlike images and harmonics, clock spurs always appear
as discrete spurs, albeit their magnitude shows a slight
dependency on the digital waveform and output frequency.
The calibration method is similar to image calibration;
however, only a digital tone of equal amplitude and
opposite phase at fDAC/4 need be generated.
0
FUND AT
–7.6dBm
–10
–20
–30
–40
fDAC/2 –
3/4 × fDAC/4 –
fOUT
fDAC/4
fOUT
–50
–60
HD3
fDAC/4 –
fOUT
HD2
HD5
HD6
–70
HD9
HD4
–80
–90
–100
0
200
400
600
800
1000
1200
FREQUENCY (MHz)
Figure 186. Spectral Plot
Note the following important observations pertaining to these
nonideal spectral artifacts:
6. A large clock spur also appears at 2 × fDAC in either normal
or mix-mode operation. This clock spur is due to the quad
switch DAC architecture causing switching events to occur
1. A full-scale sine wave (that is, single-tone) typically represents
the worst case condition because it is has a peak-to-rms
ratio of 3 dB and is unmodulated. Harmonics and aliased
harmonics of a sine wave are easy to identify because they
also appear as discrete spurs. Significant characterization of
a high speed DAC is performed using single (or multitone)
signals for this reason.
on both edges of fDAC
.
2. Modulated signals (that is, AM, PM, or FM) do not appear
as spurs but rather as signals whose power spectral density
is spread over a defined bandwidth determined by the
modulation parameters of the signals. Any harmonics from
the DAC spread over a wider bandwidth determined by the
order of the harmonic and bandwidth of the modulated signal.
For this reason, harmonics often appear as slight bumps in
the measurement noise floor and can be difficult to discern.
Rev.C | Page 60 of 64
Data Sheet
AD9737A/AD9739A
LAB EVALUATION OF THE AD9737A/AD9739A
RECOMMENDED START-UP SEQUENCE
Figure 187 shows a recommended lab setup that was used to
characterize the performance of the AD9737A/AD9739A. The
DPG2 is a dual port LVDS/CMOS data pattern generator that is
available from Analog Devices, Inc., with an up to 1.25 GSPS
data rate. The DPG2 directly interfaces to the AD9737A/AD9739A
evaluation board via Tyco Z-PACK HM-Zd connectors. A low
phase noise/jitter RF source such as an R&S SMA100A signal
generator is used for the DAC clock. A +5 V power supply is
used to power up the AD9737A/AD9739A evaluation board,
and SMA cabling is used to interface to the supply, clock source,
and spectrum analyzer. A USB 2.0 interface to a host PC is used
to communicate to both the AD9737A/AD9739A evaluation
board and the DPG2.
On power-up of the AD9737A/AD9739A, a host processor is
required to initialize and configure the AD9737A/AD9739A
via its SPI port. Figure 188 shows a flowchart of the sequential
steps required. Table 29 provides more detail on the SPI register
write/read operations required to implement the flowchart
steps. Note the following:
•
A software reset is optional because the AD9737A/AD9739A
have both an internal POR circuit and a RESET pin.
The Mu controller must be first enabled (and in track mode)
before the data receiver controller is enabled because the DCO
output signal is derived from this circuitry.
•
•
•
A wait period is related to fDATA periods.
Limit the number of attempts to lock the controllers to three;
locks typically occur on the first attempt.
A high dynamic range spectrum analyzer is required to evaluate
the ac performance of the AD9737A/AD9739A reconstructed
waveform. This is especially the case when measuring ACLR
performance for high dynamic range applications such as
multicarrier DOCSIS CMTS applications. Harmonic, SFDR,
and IMD measurements pertaining to unmodulated carriers
can benefit by using a sufficiently high RF attenuation setting
because these artifacts are easy to identify above the spectrum
analyzer noise floor. However, reconstructed waveforms having
modulated carrier(s) often benefit from the use of a high dynamic
range RF amplifier and/or passive filters to measure close-in
and wideband ACLR performance when using spectrum
analyzers of limited dynamic range.
•
Hardware or software interrupts can be used to monitor the
status of the controllers.
CONFIGURE
SPI PORT
NO
NO
CONFIGURE
MU CONT.
CONFIGURE
RX DATA
CONT.
RECONFIGURE
TXDAC FROM
DEFAULT SETTING
SOFTWARE
RESET
WAIT A
FEW 100µs
WAIT A
FEW 100µs
SET CLK
INPUT CMV
OPTIONAL
RX DATA
CONT.
LOCKED?
MU CONT.
LOCKED?
USB 2.0
YES
YES
LAB
PC
ADI PATTERN GENERATOR
DPG2
Figure 188. Flowchart for Initialization and Configuration of the
AD9737A/AD9739A
LVDS
DATA
AND DCI
DCO
GPIB
1.6GHz TO
2.5GHz
3dBm
POWER
SUPPLY
+5V
AD9739
EVAL. BOARD
RHODE AND
SCHWARTZ
SMA 100A
10 MHz
REFIN
AGILENT PSA
E4440A
10 MHz
REOUT
Figure 187. Lab Test Setup Used to Characterize the AD9737A/AD9739A
Rev.C | Page 61 of 64
AD9737A/AD9739A
Data Sheet
Table 29. Recommended SPI Initialization
Step
Address (Hex)
Write Value
Comments
1
0x00
0x00
Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto
Bits[2:0] because the MSB/LSB format can be unknown at power-up.
2
0x00
0x00
0x22
0x23
0x24
0x25
0x27
0x28
0x29
0x26
0x26
0x20
0x00
0x0F
0x0F
0x30
0x80
0x44
0x6C
0xCB
0x02
0x03
Software reset to default SPI values.
3
Clear the reset bit.
4
Set the common-mode voltage of DACCLK_P and DACCLK_N inputs
5
6
Configure the Mu controller.
7
8
9
10
11
12
13
14
Enable the Mu controller search and track mode.
Wait for 160 k × 1/fDATA cycles.
0x2A
Read back Register 0x2A and confirm that it is equal to 0x01 to ensure that the DLL loop
is locked. If it is not locked, return to Step 10 and repeat. Limit attempts to three before
breaking out of the loop and reporting a Mu lock failure.
15
16
17
18
19
20
21
Ensure that the AD9737A/AD9739A are fed with DCI clock input from the data source.
Set FINE_DEL_SKEW to 2.
0x13
0x10
0x10
0x10
0x72
0x00
0x02
0x03
Disable the data Rx controller before enabling it.
Enable the data Rx controller for loop and IRQ.
Enable the data Rx controller for search and track mode.
Wait for 135 k × 1/fDATA cycles.
0x21
Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop
is locked and tracking. If it is not locked and tracking, return to Step 16 and repeat. Limit
attempts to three before breaking out of the loop and reporting an Rx data lock failure.
22
23
0x06
0x07
0x00
0x02
Optional: modify the TxDAC IOUTFS setting (the default is 20 mA).
0x08
0x00
Optional: modify the TxDAC operation mode (the default is normal mode).
Rev.C | Page 62 of 64
Data Sheet
AD9737A/AD9739A
OUTLINE DIMENSIONS
12.10
12.00 SQ
11.90
A1 BALL
CORNER
A1 BALL
CORNER
13 11
14 12 10
9
7
5
3
1
8
6
4
2
A
B
C
D
E
F
10.40
BSC SQ
G
H
J
K
L
0.80
BSC
M
N
P
BOTTOM VIEW
DETAIL A
TOP VIEW
1.00 MAX
0.85 MIN
DETAIL A
0.43 MAX
1.40 MAX
0.25 MIN
0.55
0.50
0.45
COPLANARITY
0.12
SEATING
PLANE
BALL DIAMETER
COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1.
Figure 189. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-160-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
BC-160-1
BC-160-1
AD9737ABBCZ
AD9737ABBCZRL
AD9737A-EBZ
AD9739ABBCZ
AD9739ABBCZRL
AD9739A-EBZ
AD9739A-FMC-EBZ
−40°C to +85°C
−40°C to +85°C
160-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
160-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board for Normal, CMTS, and Mix-Mode Evaluation
160-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
160- Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board for Normal, CMTS, and Mix-Mode Evaluation
−40°C to +85°C
−40°C to +85°C
BC-160-1
BC-160-1
Evaluation Board with FMC connector for Xilinx based FPGA
development platforms
1 Z = RoHS Compliant Part.
Rev. C | Page 63 of 64
AD9737A/AD9739A
NOTES
Data Sheet
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09616-0-2/12(C)
Rev. C | Page 64 of 64
相关型号：
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PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 10-BIT DAC, QCC32, 5 X 5 MM, MO-220VHHD-2, LFCSP-32
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