AD9742ACP-PCBZ_技术文档

12-Bit, 210 MSPS

TxDAC Digital-to-Analog Converter

AD9742

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAM

3.3V

High performance member of pin-compatible TxDAC

product family

REFLO

1.2V REF

REFIO

AVDD ACOM

150pF

Excellent spurious-free dynamic range performance

SNR at 5 MHz output, 125 MSPS: 70 dB

Twos complement or straight binary data format

Differential current outputs: 2 mA to 20 mA

Power dissipation: 135 mW at 3.3 V

Power-down mode: 15 mW at 3.3 V

On-chip 1.2 V Reference

0.1µF

AD9742

CURRENT

SOURCE

ARRAY

FS ADJ

R

SET

3.3V

DVDD

DCOM

IOUTA

IOUTB

SEGMENTED

SWITCHES

LSB

SWITCHES

CLOCK

MODE

CLOCK

LATCHES

CMOS compatible digital interface

28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP

Edge-triggered latches

DIGITAL DATA INPUTS (DB11–DB0)

SLEEP

Figure 1.

APPLICATIONS

Wideband communication transmit channel:

Direct IF

Base stations

Wireless local loops

Digital radio links

Direct digital synthesis (DDS)

Instrumentation

GENERAL DESCRIPTION

The AD9742¹is a 12-bit resolution, wideband, third generation

member of the TxDAC series of high performance, low power

CMOS digital-to-analog converters (DACs). The TxDAC family,

consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs,

is specifically optimized for the transmit signal path of

communication systems. All of the devices share the same interface

options, small outline package, and pinout, providing an upward

or downward component selection path based on performance,

resolution, and cost. The AD9742 offers exceptional ac and dc

performance while supporting update rates up to 210 MSPS.

Edge-triggered input latches and a 1.2 V temperature compensated

band gap reference have been integrated to provide a complete

monolithic DAC solution. The digital inputs support 3 V CMOS

logic families.

PRODUCT HIGHLIGHTS

1. The AD9742 is the 12-bit member of the pin-compatible

TxDAC family, which offers excellent INL and DNL

performance.

2. Data input supports twos complement or straight binary

data coding.

The AD9742’s low power dissipation makes it well suited for

portable and low power applications. Its power dissipation can

be further reduced to a mere 60 mW with a slight degradation

in performance by lowering the full-scale current output. Also,

a power-down mode reduces the standby power dissipation to

approximately 15 mW. A segmented current source architecture

is combined with a proprietary switching technique to reduce

spurious components and enhance dynamic performance.

3. High speed, single-ended CMOS clock input supports

210 MSPS conversion rate.

4. Low power: Complete CMOS DAC function operates on

135 mW from a 2.7 V to 3.6 V single supply. The DAC full-

scale current can be reduced for lower power operation,

and a sleep mode is provided for low power idle periods.

5. On-chip voltage reference: The AD9742 includes a 1.2 V

temperature compensated band gap voltage reference.

6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and

32-lead LFCSP packages.

¹Protected by U.S. Patent Numbers: 5,568,145; 5,689,257; and 5,703,519.

Rev. C

Document Feedback

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

AD9742

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Reference Control Amplifier .................................................... 13

DAC Transfer Function............................................................. 13

Analog Outputs .......................................................................... 13

Digital Inputs .............................................................................. 14

Clock Input.................................................................................. 14

DAC Timing................................................................................ 15

Power Dissipation....................................................................... 15

Applying the AD9742 ................................................................ 16

Differential Coupling Using a Transformer ............................... 16

Differential Coupling Using an Op Amp................................ 16

Single-Ended, Unbuffered Voltage Output............................. 17

Single-Ended, Buffered Voltage Output Configuration........ 17

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DC Specifications ......................................................................... 3

Dynamic Specifications ............................................................... 4

Digital Specifications ................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 11

Functional Description.................................................................. 12

Reference Operation .................................................................. 12

Power and Grounding Considerations, Power Supply

Rejection...................................................................................... 17

Evaluation Board ............................................................................ 19

General Description................................................................... 19

Outline Dimensions....................................................................... 29

Ordering Guide .......................................................................... 30

REVISION HISTORY

2/13—Rev. B to Rev. C

5/03—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Figure 4 and Table 6..................................................... 7

Moved Terminology Section......................................................... 11

Updated Outline Dimensions....................................................... 29

Changes to Ordering Guide .......................................................... 30

Added 32-Lead LFCSP Package .......................................Universal

Edits to Features and Product Highlights ......................................1

Edits to DC Specifications................................................................2

Edits to Dynamic Specifications......................................................3

Edits to Digital Specifications..........................................................4

Edits to Absolute Maximum Ratings, Thermal Characteristics,

and Ordering Guide..........................................................................5

Edits to Pin Configuration and Pin Function Descriptions ........6

Edits to Figure 2.................................................................................7

Replaced TPCs 1, 4, 7, and 8............................................................8

Edits to Figure 3 and Functional Description Section .............. 10

Added Clock Input Section and Figure 7.................................... 12

Edits to DAC Timing Section ....................................................... 12

Edits to Sleep Mode Operation Section and Power Dissipation

Section.............................................................................................. 13

Renumbered Figure 8 to Figure 26............................................... 13

Added Figure 11 ............................................................................. 13

Added Figure 27 to Figure 35 ....................................................... 21

Updated Outline Dimensions....................................................... 26

6/04—Rev. A to Rev. B

Changes to the Title, General Description, and Product

Highlights .......................................................................................... 1

Changes to Dynamic Specifications............................................... 4

Changes to Figure 6 and Figure 10................................................. 9

Changes to Figure 12 to Figure 15................................................ 10

Changes to the Functional Description Section......................... 12

Changes to the Digital Inputs Section ......................................... 14

Changes to Figure 29...................................................................... 15

Changes to Figure 30...................................................................... 16

5/02—Revision 0: Initial Version

Rev. C | Page 2 of 32

Data Sheet

AD9742

SPECIFICATIONS

DC SPECIFICATIONS

T_MINto T_MAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I_OUTFS= 20 mA, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

RESOLUTION

12

Bits

DC ACCURACY¹

Integral Linearity Error (INL)

Differential Nonlinearity (DNL)

ANALOG OUTPUT

−2.5

−1.3

0.5

0.4

+2.5

+1.3

LSB

Offset Error

−0.02

−0.5

2

+0.02

+0.5

20

% of FSR

mA

V

kΩ

Gain Error (Without Internal Reference)

Gain Error (With Internal Reference)

Full-Scale Output Current²

Output Compliance Range

Output Resistance

0.1

−1

+1.25

100

5

Output Capacitance

REFERENCE OUTPUT

Reference Voltage

pF

1.14

0.1

1.20

100

1.26

1.25

V

nA

Reference Output Current³

REFERENCE INPUT

Input Compliance Range

Reference Input Resistance (Ext. Reference)

Small Signal Bandwidth

TEMPERATURE COEFFICIENTS

Offset Drift

Gain Drift (Without Internal Reference)

Gain Drift (With Internal Reference)

Reference Voltage Drift

POWER SUPPLY

V

MΩ

MHz

1

0.5

0

ppm of FSR/°C

ppm/°C

50

100

50

Supply Voltages

AVDD

DVDD

2.7

3.3

33

8

3.6

36

9

V

mA

CLKVDD

Analog Supply Current (I_AVDD

Digital Supply Current (I_DVDD

)

4

mA

Clock Supply Current (I_CLKVDD

)

5

6

mA

Supply Current Sleep Mode (I_AVDD

)

5

135

145

6

145

mA

mW

Power Dissipation⁴

Power Dissipation⁵

Power Supply Rejection Ratio—AVDD⁶

Power Supply Rejection Ratio—DVDD⁶

OPERATING RANGE

−1

−0.04

−40

+1

+0.04

+85

% of FSR/V

°C

¹Measured at IOUTA, driving a virtual ground.

²Nominal full-scale current, I_OUTFS, is 32 times the I_REFcurrent.

³An external buffer amplifier with input bias current <100 nA should be used to drive any external load.

⁴Measured at f_CLOCK= 25 MSPS and f_OUT= 1 MHz.

⁵Measured as unbuffered voltage output with I_OUTFS= 20 mA and 50 Ω R_LOADat IOUTA and IOUTB, f_CLOCK= 100 MSPS and f_OUT= 40 MHz.

6

5% power supply variation.

Rev. C | Page 3 of 32

AD9742

Data Sheet

DYNAMIC SPECIFICATIONS

T_MINto T_MAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I_OUTFS= 20 mA, differential transformer coupled output, 50 Ω doubly

terminated, unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f_CLOCK

Output Settling Time (t_ST) (to 0.1%)¹

Output Propagation Delay (t_PD)

Glitch Impulse

Output Rise Time (10% to 90%)¹

Output Fall Time (10% to 90%)¹

Output Noise (I_OUTFS= 20 mA)²

Output Noise (I_OUTFS= 2 mA)²

Noise Spectral Density³

)

210

MSPS

ns

pV-sec

ns

pA/√Hz

dBm/Hz

11

1

5

2.5

50

30

−152

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

f_CLOCK= 25 MSPS; f_OUT= 1.00 MHz

0 dBFS Output

74

84

85

82

76

85

83

80

75

74

72

60

67

60

dBc

−6 dBFS Output

−12 dBFS Output

−18 dBFS Output

f_CLOCK= 65 MSPS; f_OUT= 1.00 MHz

f_CLOCK= 65 MSPS; f_OUT= 2.51 MHz

f_CLOCK= 65 MSPS; f_OUT= 10 MHz

f_CLOCK= 65 MSPS; f_OUT= 15 MHz

f_CLOCK= 65 MSPS; f_OUT= 25 MHz

f_CLOCK= 165 MSPS; f_OUT= 21 MHz

f_CLOCK= 165 MSPS; f_OUT= 41 MHz

f_CLOCK= 210 MSPS; f_OUT= 40 MHz

f_CLOCK= 210 MSPS; f_OUT= 69 MHz

Spurious-Free Dynamic Range within a Window

f_CLOCK= 25 MSPS; f_OUT= 1.00 MHz; 2 MHz Span

f_CLOCK= 50 MSPS; f_OUT= 5.02 MHz; 2 MHz Span

f_CLOCK= 65 MSPS; f_OUT= 5.03 MHz; 2.5 MHz Span

f_CLOCK= 125 MSPS; f_OUT= 5.04 MHz; 4 MHz Span

Total Harmonic Distortion

80

dBc

90

f_CLOCK= 25 MSPS; f_OUT= 1.00 MHz

f_CLOCK= 50 MSPS; f_OUT= 2.00 MHz

f_CLOCK= 65 MSPS; f_OUT= 2.00 MHz

f_CLOCK= 125 MSPS; f_OUT= 2.00 MHz

Signal-to-Noise Ratio

−82

−77

−74

dBc

f_CLOCK= 65 MSPS; f_OUT= 5 MHz; I_OUTFS= 20 mA

f_CLOCK= 65 MSPS; f_OUT= 5 MHz; I_OUTFS= 5 mA

f_CLOCK= 125 MSPS; f_OUT= 5 MHz; I_OUTFS= 20 mA

f_CLOCK= 125 MSPS; f_OUT= 5 MHz; I_OUTFS= 5 mA

f_CLOCK= 165 MSPS; f_OUT= 5 MHz; I_OUTFS= 20 mA

f_CLOCK= 165 MSPS; f_OUT= 5 MHz; I_OUTFS= 5 mA

f_CLOCK= 210 MSPS; f_OUT= 5 MHz; I_OUTFS= 20 mA

f_CLOCK= 210 MSPS; f_OUT= 5 MHz; I_OUTFS= 5 mA

78

86

73

78

69

71

69

66

dB

Rev. C | Page 4 of 32

Data Sheet

AD9742

Parameter

Min

Typ

Max

Unit

Multitone Power Ratio (8 Tones at 400 kHz Spacing)

f_CLOCK= 78 MSPS; f_OUT= 15.0 MHz to 18.2 MHz

0 dBFS Output

65

67

65

63

dBc

−6 dBFS Output

−12 dBFS Output

−18 dBFS Output

¹Measured single-ended into 50 Ω load.

²Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.

³Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.

DIGITAL SPECIFICATIONS

T_MINto T_MAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I_OUTFS= 20 mA, unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit

DIGITAL INPUTS¹

Logic 1 Voltage

Logic 0 Voltage

2.1

3

0

V

0.9

Logic 1 Current

Logic 0 Current

−10

+10

µA

pF

ns

Input Capacitance

Input Setup Time (t_S)

Input Hold Time (t_H)

Latch Pulse Width (t_LPW

CLK INPUTS²

5

2.0

1.5

)

Input Voltage Range

Common-Mode Voltage

Differential Voltage

0

0.75

0.5

3

2.25

V

1.5

¹Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.

²Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode.

DB0–DB11

t_S

t_H

CLOCK

t_LPW

t_ST

t_PD

IOUTA

OR

IOUTB

0.1%

Figure 2. Timing Diagram

Rev. C | Page 5 of 32

AD9742

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 4.

THERMAL RESISTANCE

Thermal impedance measurements were taken on a 4-layer

board in still air, in accordance with EIA/JESD51-7.

With

Respect to

Parameter

AVDD

Min Max

Unit

V

ACOM

−0.3 +3.9

Table 5. Thermal Resistance

DVDD

DCOM

−0.3 +3.9

Package Type

28-Lead SOIC

28-Lead TSSOP

32-Lead LFCSP

θ_JA

Unit

°C/W

CLKVDD

ACOM

CLKCOM

DCOM

−0.3 +3.9

−0.3 +0.3

55.9

67.7

32.5

ACOM

DCOM

AVDD

CLKCOM

DVDD

−0.3 +0.3

−3.9 +3.9

AVDD

DVDD

CLOCK, SLEEP

Digital Inputs, MODE

IOUTA, IOUTB

CLKVDD

DCOM

ACOM

−3.9 +3.9

V

°C

ESD CAUTION

−0.3 DVDD + 0.3

−1.0 AVDD + 0.3

−0.3 AVDD + 0.3

−0.3 CLKVDD + 0.3

150

REFIO, REFLO, FS ADJ ACOM

CLK+, CLK−, MODE

Junction Temperature

Storage Temperature

Lead Temperature

(10 sec)

CLKCOM

−65

+150

300

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. C | Page 6 of 32

Data Sheet

AD9742

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

28

(MSB) DB11

DB10

DB9

CLOCK

DVDD

2

3

27

26

DCOM

MODE

AVDD

4

5

25

24

23

22

21

20

19

18

17

16

15

DB8

DB7

DB5 1

DB4 2

DVDD 3

DB3 4

DB2 5

DB1 6

24 FS ADJ

23 REFIO

22 ACOM

21 IOUTA

20 IOUTB

19 ACOM

18 AVDD

17 AVDD

PIN 1

AD9742

INDICATOR

6

DB6

RESERVED

IOUTA

IOUTB

ACOM

NC

TOP VIEW

7

DB5

(Not to Scale)

AD9742

8

DB4

TOP VIEW

(Not to Scale)

9

DB3

(LSB) DB0 7

NC 8

10

11

12

13

14

DB2

DB1

FS ADJ

REFIO

REFLO

SLEEP

(LSB) DB0

NC

NOTES

1. NC = NO CONNECT.

NC = NO CONNECT

2. IT IS RECOMMENDED THAT THE EXPOSED PAD

BE THERMALLY CONNECTED TO A COPPER

GROUND PLANE FOR ENHANCED ELECTRICAL

AND THERMAL PERFORMANCE.

Figure 3. 28-Lead SOIC and 28-Lead TSSOP Pin Configuration

Figure 4. 32-Lead LFCSP Pin Configuration

Table 6. Pin Function Descriptions (N/A = Not Applicable)

SOIC/TSSOP LFCSP

Pin No.

Mnemonic

Description

1

27

DB11

Most Significant Data Bit (MSB).

2 to 11

28 to 32,

DB10 to DB1 Data Bits 10 to 1.

1, 2, 4 to 6

12

13, 14

15

7

8, 9

25

DB0

NC

SLEEP

Least Significant Data Bit (LSB).

No Internal Connection.

Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left

unterminated if not used.

16

17

N/A

23

REFLO

REFIO

Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal

reference.

Reference Input/Output. Serves as reference input when internal reference disabled (that is, tie

REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (that is, tie

REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated.

18

19

20

21

22

23

24

25

N/A

24

FS ADJ

NC

Full-Scale Current Output Adjust.

No Internal Connection.

Analog Common.

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

DAC Current Output. Full-scale current when all data bits are 1s.

Reserved. Do not connect to common or supply.

Analog Supply Voltage (3.3 V).

Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.

Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float

CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip).

N/A

19, 22

20

ACOM

IOUTB

IOUTA

RESERVED

AVDD

21

N/A

17, 18

16

MODE

CMODE

15

26

27

28

N/A

10, 26

3

N/A

12

13

11

DCOM

DVDD

CLOCK

CLK+

Digital Common.

Digital Supply Voltage (3.3 V).

Clock Input. Data latched on positive edge of clock.

Differential Clock Input.

Clock Supply Voltage (3.3 V).

Clock Common.

CLK−

CLKVDD

CLKCOM

EPAD

14

It is recommended that the exposed pad be thermally connected to a copper ground plane for

enhanced electric and thermal performance.

Rev. C | Page 7 of 32

AD9742

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

95

90

85

80

75

70

65

60

55

50

45

95

125MSPS

0dBFS

90

85

80

75

70

65

60

55

50

45

210MSPS (LFCSP)

–6dBFS (LFCSP)

165MSPS (LFCSP)

65MSPS

–12dBFS

210MSPS

165MSPS

125MSPS (LFCSP)

–12dBFS (LFCSP)

0dBFS (LFCSP)

–6dBFS

0

10

20

30

40

50

60

1

10

100

f_OUT(MHz)

Figure 5. SFDR vs. f_OUT@ 0 dBFS

Figure 8. SFDR vs. f_OUT@ 165 MSPS

95

90

85

80

75

70

65

60

55

50

45

95

90

85

80

75

70

65

60

55

50

45

0dBFS (LFCSP)

0dBFS

–12dBFS

–6dBFS

–6dBFS (LFCSP)

–6dBFS

–12dBFS

–12dBFS (LFCSP)

0dBFS

0

5

10

15

20

25

0

10

20

30

40

50

60

70

f_OUT(MHz)

Figure 6. SFDR vs. f_OUT@ 65 MSPS

Figure 9. SFDR vs. f_OUT@ 210 MSPS

95

90

85

80

75

70

65

60

55

50

45

95

90

85

80

75

70

65

60

55

50

45

20mA

10mA

5mA

–6dBFS

–12dBFS

0dBFS

0

5

10

15

20

25

30

35

40

45

0

5

10

15

20

25

f_OUT(MHz)

Figure 7. SFDR vs. f_OUT@ 125 MSPS

Figure 10. SFDR vs. f_OUTand I_OUTFS@ 65 MSPS and 0 dBFS

Rev. C | Page 8 of 32

Data Sheet

AD9742

95

90

85

80

75

70

65

60

55

50

45

95

90

85

80

75

70

65

60

55

50

45

78MSPS (10.1,12.1)

65MSPS (8.3,10.3)

65MSPS

125MSPS

125MSPS (16.9, 18.9)

210MSPS (29, 31)

165MSPS

165MSPS (22.6, 24.6)

210MSPS

210MSPS (29, 31)

210MSPS (LFCSP)

–25

–20

–15

–10

(dBFS)

–5

0

–25

–20

–15

–10

(dBFS)

–5

0

A

OUT

Figure 11. Single-Tone SFDR vs. A_OUT@ f_OUT= f_CLOCK/11

Figure 14. Dual-Tone IMD vs. A_OUT@ f_OUT= f_CLOCK/7

1.0

0.5

95

90

85

80

75

70

65

60

55

50

45

125MSPS (LFCSP)

65MSPS

165MSPS (LFCSP)

0

165MSPS

125MSPS

–0.5

–1.0

210MSPS (LFCSP)

210MSPS

0

1024

2048

3072

4096

–25

–20

–15

A

–10

(dBFS)

–5

0

CODE

OUT

Figure 12. Single-Tone SFDR vs. A_OUT@ f_OUT= f_CLOCK/5

Figure 15. Typical INL

80

75

70

65

60

55

50

1.0

0.8

20mA

0.6

0.4

0.2

0

5mA

10mA

–0.2

–0.4

–0.6

–0.8

–1.0

25

45

65

85

105

125

145

165

185 205

0

1024

2048

3072

4096

f_CLOCK(MHz)

CODE

Figure 13. SNR vs. f_CLOCKand I_OUTFS@ f_OUT= 5 MHz and 0 dBFS

Figure 16. Typical DNL

Rev. C | Page 9 of 32

AD9742

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

90

85

80

75

70

65

60

55

f_CLOCK= 78MSPS

f_OUT1= 15.0MHz

f_OUT2= 15.4MHz

SFDR = 77dBc

AMPLITUDE = 0dBFS

4MHz

19MHz

49MHz

34MHz

50

–40

1

6

11

16

21

26

31

36

–20

0

20

40

60

80

TEMPERATURE (°C)

FREQUENCY (MHz)

Figure 17. SFDR vs. Temperature @ 165 MSPS, 0 dBFS

Figure 19. Dual-Tone SFDR

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

f

= 78MSPS

f_CLOCK= 78MSPS

f_OUT= 15.0MHz

SFDR = 79dBc

CLOCK

f_OUT1= 15.0MHz

f_OUT2= 15.4MHz

f_OUT3= 15.8MHz

f_OUT4= 16.2MHz

AMPLITUDE = 0dBFS

SFDR = 75dBc

AMPLITUDE = 0dBFS

1

6

11

16

21

26

31

36

1

6

11

16

21

26

31

36

FREQUENCY (MHz)

Figure 18. Single-Tone SFDR

Figure 20. Four-Tone SFDR

3.3V

REFLO

AVDD

ACOM

150pF

1.2V REF

AD9742

V

REFIO

PMOS

CURRENT SOURCE

ARRAY

I

REF

FS ADJ

0.1µF

V

= V

– V

OUTA OUTB

R

DIFF

SET

2kΩ

3.3V

DVDD

DCOM

IOUTA

IOUTB

IOUTA

V

OUTA

SEGMENTED SWITCHES

FOR DB11–DB3

LSB

SWITCHES

IOUTB

MODE

V

OUTB

R

LOAD

50Ω

CLOCK

SLEEP

R

LOAD

50Ω

LATCHES

CLOCK

DIGITAL DATA INPUTS (DB11–DB0)

Figure 21. Simplified Block Diagram (SOIC/TSSOP Packages)

Rev. C | Page 10 of 32

Data Sheet

AD9742

TERMINOLOGY

Power Supply Rejection

Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the

actual analog output from the ideal output, determined by a

straight line drawn from zero to full scale.

The maximum change in the full-scale output as the supplies

are varied from nominal to minimum and maximum specified

voltages.

Settling Time

Differential Nonlinearity (or DNL)

The time required for the output to reach and remain within a

specified error band about its final value, measured from the

start of the output transition.

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input

code.

Glitch Impulse

Monotonicity

Asymmetrical switching times in a DAC give rise to undesired

output transients that are quantified by a glitch impulse. It is

specified as the net area of the glitch in pV-s.

A DAC is monotonic if the output either increases or remains

constant as the digital input increases.

Offset Error

Spurious-Free Dynamic Range

The deviation of the output current from the ideal of zero is

called the offset error. For IOUTA, 0 mA output is expected

when the inputs are all 0s. For IOUTB, 0 mA output is expected

when all inputs are set to 1s.

The difference, in dB, between the rms amplitude of the output

signal and the peak spurious signal over the specified

bandwidth.

Total Harmonic Distortion (THD)

Gain Error

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured input signal. It is

expressed as a percentage or in decibels (dB).

The difference between the actual and ideal output span. The

actual span is determined by the output when all inputs are set

to 1s minus the output when all inputs are set to 0s.

Multitone Power Ratio

Output Compliance Range

The spurious-free dynamic range containing multiple carrier

tones of equal amplitude. It is measured as the difference

between the rms amplitude of a carrier tone to the peak

spurious signal in the region of a removed tone.

The range of allowable voltage at the output of a current output

DAC. Operation beyond the maximum compliance limits may

cause either output stage saturation or breakdown, resulting in

nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (25°C) value to the value at either T_MINor T_MAX. For

offset and gain drift, the drift is reported in ppm of full-scale

range (FSR) per °C. For reference drift, the drift is reported in

ppm per °C.

3.3V

REFLO

1.2V REF

REFIO

AVDD

ACOM

150pF

AD9742

0.1µF

PMOS

CURRENT SOURCE

ARRAY

FS ADJ

MINI-CIRCUITS

T1-1T

R

SET

2kΩ

ROHDE & SCHWARZ

FSEA30

SPECTRUM

3.3V

DVDD

DCOM

IOUTA

IOUTB

LSB

SWITCHES

SEGMENTED SWITCHES

FOR DB11–DB3

ANALYZER

CLOCK

SLEEP

MODE

LATCHES

DVDD

DCOM

50Ω

RETIMED

CLOCK

OUTPUT*

50Ω

DIGITAL

DATA

CLOCK

OUTPUT

*AWG2021 CLOCK RETIMED

SO THAT THE DIGITAL DATA

TRANSITIONS ON FALLING EDGE

OF 50% DUTY CYCLE CLOCK.

LECROY 9210

PULSE GENERATOR

TEKTRONIX AWG-2021

WITH OPTION 4

Figure 22. Basic AC Characterization Test Set-Up (SOIC/TSSOP Packages)

Rev. C | Page 11 of 32

AD9742

Data Sheet

FUNCTIONAL DESCRIPTION

AD9742 consists of a DAC, digital control logic, and full-scale

output current control. The DAC contains a PMOS current

source array capable of providing up to 20 mA of full-scale

current (I_OUTFS). The array is divided into 31 equal currents that

make up the five most significant bits (MSBs). The next four

bits, or middle bits, consist of 15 equal current sources whose

value is 1/16th of an MSB current source. The remaining LSBs

are binary weighted fractions of the middle bits current sources.

Implementing the middle and lower bits with current sources,

instead of an R-2R ladder, enhances its dynamic performance

for multitone or low amplitude signals and helps maintain the

DAC’s high output impedance (i.e., >100 kΩ).

REFERENCE OPERATION

The AD9742 contains an internal 1.2 V band gap reference. The

internal reference can be disabled by raising REFLO to AVDD.

It can also be easily overridden by an external reference with no

effect on performance. REFIO serves as either an input or an

output depending on whether the internal or an external

reference is used. To use the internal reference, simply decouple

the REFIO pin to ACOM with a 0.1 µF capacitor and connect

REFLO to ACOM via a resistance less than 5 Ω. The internal

reference voltage will be present at REFIO. If the voltage at

REFIO is to be used anywhere else in the circuit, an external

buffer amplifier with an input bias current of less than 100 nA

should be used. An example of the use of the internal reference

is shown in Figure 23.

All of these current sources are switched to one or the other of

the two output nodes (i.e., IOUTA or IOUTB) via PMOS

differential current switches. The switches are based on the

architecture that was pioneered in the AD9764 family, with

further

refinements to reduce distortion contributed by the switching

transient. This switch architecture also reduces various timing

errors and provides matching complementary drive signals to

the inputs of the differential current switches.

3.3V

OPTIONAL

EXTERNAL

REF BUFFER

AVDD

REFLO

1.2V REF

150pF

REFIO

FS ADJ

CURRENT

SOURCE

ARRAY

ADDITIONAL

LOAD

0.1µF

2kΩ

AD9742

The analog and digital sections of the AD9742 have separate

power supply inputs (i.e., AVDD and DVDD) that can operate

independently over a 2.7 V to 3.6 V range. The digital section,

which is capable of operating at a rate of up to 210 MSPS,

consists of edge-triggered latches and segment decoding logic

circuitry. The analog section includes the PMOS current

sources, the associated differential switches, a 1.2 V band gap

voltage reference, and a reference control amplifier.

Figure 23. Internal Reference Configuration

An external reference can be applied to REFIO, as shown in

Figure 24. The external reference may provide either a fixed

reference voltage to enhance accuracy and drift performance or

a varying reference voltage for gain control. Note that the 0.1 µF

compensation capacitor is not required since the internal

reference is overridden, and the relatively high input impedance

of REFIO minimizes any loading of the external reference.

3.3V

The DAC full-scale output current is regulated by the reference

control amplifier and can be set from 2 mA to 20 mA via an

external resistor, R_SET, connected to the full-scale adjust (FS

ADJ) pin. The external resistor, in combination with both the

reference control amplifier and voltage reference ,V_REFIO, sets the

reference current, I_REF, which is replicated to the segmented

current sources with the proper scaling factor. The full-scale

REFLO

1.2V REF

150pF

AVDD

V

REFIO

FS ADJ

EXTERNAL

REF

CURRENT

SOURCE

ARRAY

current, I_OUTFS, is 32 times I_REF

.

R

I

=

SET

REF

V

/R

REFIO SET

REFERENCE

CONTROL

AMPLIFIER

AD9742

Figure 24. External Reference Configuration

Rev. C | Page 12 of 32

Data Sheet

AD9742

V_DIFF

=

(

IOUTA − IOUTB

)

×R_LOAD

(7)

REFERENCE CONTROL AMPLIFIER

The AD9742 contains a control amplifier that is used to regulate

the full-scale output current, I_OUTFS. The control amplifier is

configured as a V-I converter, as shown in Figure 24, so that its

current output, I_REF, is determined by the ratio of the V_REFIOand

an external resistor, R_SET, as stated in Equation 4. I_REFis copied

to the segmented current sources with the proper scale factor to

set I_OUTFS, as stated in Equation 3.

Substituting the values of IOUTA, IOUTB, I_REF, and V_DIFFcan be

expressed as:

V _DIFF

=

{(2×DAC CODE − 4095

×V_REFIO

)

/4096

}

(8)

(

32×R_LOAD/R_SET

)

Equations 7 and 8 highlight some of the advantages of operating

the AD9742 differentially. First, the differential operation helps

cancel common-mode error sources associated with IOUTA

and IOUTB, such as noise, distortion, and dc offsets. Second,

the differential code-dependent current and subsequent voltage,

The control amplifier allows a wide (10:1) adjustment span of

IOUTFS over a 2 mA to 20 mA range by setting IREF between

62.5 µA and 625 µA. The wide adjustment span of IOUTFS

provides several benefits. The first relates directly to the power

dissipation of the AD9742, which is proportional to IOUTFS (see

the Power Dissipation section). The second relates to the 20 dB

adjustment, which is useful for system gain control purposes.

V

_DIFF, is twice the value of the single-ended voltage output (i.e.,

_OUTAor V_OUTB), thus providing twice the signal power to the load.

Note that the gain drift temperature performance for a single-

ended (V_OUTAand V_OUTB) or differential output (V_DIFF) of the

AD9742 can be enhanced by selecting temperature tracking

resistors for R_LOADand R_SETdue to their ratiometric relationship,

as shown in Equation 8.

The small signal bandwidth of the reference control amplifier is

approximately 500 kHz and can be used for low frequency small

signal multiplying applications.

ANALOG OUTPUTS

DAC TRANSFER FUNCTION

The complementary current outputs in each DAC, IOUTA,

and IOUTB may be configured for single-ended or differential

operation. IOUTA and IOUTB can be converted into comple-

mentary single-ended voltage outputs, V_OUTAand V_OUTB, via a

load resistor, R_LOAD, as described in the DAC Transfer Function

section by Equations 5 through 8. The differential voltage, V_DIFF

existing between V_OUTAand V_OUTB, can also be converted to a

single-ended voltage via a transformer or differential amplifier

configuration. The ac performance of the AD9742 is optimum and

specified using a differential transformer-coupled output in which

the voltage swing at IOUTA and IOUTB is limited to 0.5 V.

Both DACs in the AD9742 provide complementary current

outputs, IOUTA and IOUTB. IOUTA provides a near full-scale

current output, I_OUTFS, when all bits are high (i.e., DAC CODE =

4095), while IOUTB, the complementary output, provides no

current. The current output appearing at IOUTA and IOUTB is

a function of both the input code and I_OUTFSand can be

expressed as:

,

IOUTA =

IOUTB =

(

DAC CODE/4096

)

×I_OUTFS

(1)

(2)

(

4095 − DAC CODE

/4096×I_OUTFS

where DAC CODE = 0 to 4095 (i.e., decimal representation).

The distortion and noise performance of the AD9742 can be

enhanced when it is configured for differential operation. The

common-mode error sources of both IOUTA and IOUTB can

be significantly reduced by the common-mode rejection of a

transformer or differential amplifier. These common-mode

error sources include even-order distortion products and noise.

The enhancement in distortion performance becomes more

significant as the frequency content of the reconstructed

waveform increases and/or its amplitude decreases. This is due

to the first-order cancellation of various dynamic common-

mode distortion mechanisms, digital feedthrough, and noise.

As mentioned previously, I_OUTFSis a function of the reference

current I_REF, which is nominally set by a reference voltage,

V_REFIO, and external resistor, R_SET. It can be expressed as:

I_OUTFS= 32×I_REF

(3)

(4)

where

I_REF= V_REFIO/R_SET

The two current outputs will typically drive a resistive load

directly or via a transformer. If dc coupling is required, IOUTA

and IOUTB should be directly connected to matching resistive

loads, R_LOAD, that are tied to analog common, ACOM. Note that

Performing a differential-to-single-ended conversion via a

transformer also provides the ability to deliver twice the

reconstructed signal power to the load (assuming no source

termination). Since the output currents of IOUTA and IOUTB

are complementary, they become additive when processed

differentially. A properly selected transformer will allow the

AD9742 to provide the required power and voltage levels to

different loads.

R_LOADmay represent the equivalent load resistance seen by

IOUTA or IOUTB as would be the case in a doubly terminated

50 Ω or 75 Ω cable. The single-ended voltage output appearing

at the IOUTA and IOUTB nodes is simply

V_OUTA= IOUTA×R_LOAD

V_OUTB= IOUTB×R_LOAD

(5)

(6)

Note that the full-scale value of V_OUTAand V_OUTBshould not exceed

the specified output compliance range to maintain specified

distortion and linearity performance.

Rev. C | Page 13 of 32

AD9742

Data Sheet

The output impedance of IOUTA and IOUTB is determined by

the equivalent parallel combination of the PMOS switches

associated with the current sources and is typically 100 kΩ in

parallel with 5 pF. It is also slightly dependent on the output

voltage (i.e., V_OUTAand V_OUTB) due to the nature of a PMOS

device. As a result, maintaining IOUTA and/or IOUTB at a

virtual ground via an I-V op amp configuration will result in

the optimum dc linearity. Note that the INL/DNL specifications

for the AD9742 are measured with IOUTA maintained at a

virtual ground via an op amp.

CLOCK INPUT

SOIC/TSSOP Packages

The 28-lead package options have a single-ended clock input

(CLOCK) that must be driven to rail-to-rail CMOS levels. The

quality of the DAC output is directly related to the clock quality,

and jitter is a key concern. Any noise or jitter in the clock will

translate directly into the DAC output. Optimal performance

will be achieved if the CLOCK input has a sharp rising edge,

since the DAC latches are positive edge triggered.

LFCSP Package

IOUTA and IOUTB also have a negative and positive voltage

compliance range that must be adhered to in order to achieve

optimum performance. The negative output compliance range

of −1 V is set by the breakdown limits of the CMOS process.

Operation beyond this maximum limit may result in a breakdown

of the output stage and affect the reliability of the AD9742.

A configurable clock input is available in the LFCSP package,

which allows for one single-ended and two differential modes.

The mode selection is controlled by the CMODE input, as

summarized in Table 7. Connecting CMODE to CLKCOM

selects the single-ended clock input. In this mode, the CLK+

input is driven with rail-to-rail swings and the CLK− input is

left floating. If CMODE is connected to CLKVDD, the differential

receiver mode is selected. In this mode, both inputs are high

impedance. The final mode is selected by floating CMODE. This

mode is also differential, but internal terminations for positive

emitter-coupled logic (PECL) are activated. There is no significant

performance difference between any of the three clock input modes.

The positive output compliance range is slightly dependent on

the full-scale output current, I_OUTFS. It degrades slightly from its

nominal 1.2 V for an I_OUTFS= 20 mA to 1 V for an I_OUTFS= 2 mA.

The optimum distortion performance for a single-ended or

differential output is achieved when the maximum full-scale

signal at IOUTA and IOUTB does not exceed 0.5 V.

DIGITAL INPUTS

Table 7. Clock Mode Selection

The AD9742 digital section consists of 12 input bit channels

and a clock input. The 12-bit parallel data inputs follow standard

positive binary coding, where DB11 is the most significant bit

(MSB) and DB0 is the least significant bit (LSB). IOUTA produces

a full-scale output current when all data bits are at Logic 1. IOUTB

produces a complementary output with the full-scale current

split between the two outputs as a function of the input code.

DVDD

CMODE Pin

CLKCOM

CLKVDD

Float

Clock Input Mode

Single-Ended

Differential

PECL

The single-ended input mode operates in the same way as the

CLOCK input in the 28-lead packages, as described previously.

In the differential input mode, the clock input functions as a

high impedance differential pair. The common-mode level of

the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and

the differential voltage can be as low as 0.5 V p-p. This mode

can be used to drive the clock with a differential sine wave since

the high gain bandwidth of the differential inputs will convert

the sine wave into a single-ended square wave internally.

DIGITAL

INPUT

Figure 25. Equivalent Digital Input

The final clock mode allows for a reduced external component

count when the DAC clock is distributed on the board using

PECL logic. The internal termination configuration is shown in

Figure 26. These termination resistors are untrimmed and can

vary up to 20%. However, matching between the resistors

should generally be better than 1%.

The digital interface is implemented using an edge-triggered

master/slave latch. The DAC output updates on the rising edge

of the clock and is designed to support a clock rate as high as

210 MSPS. The clock can be operated at any duty cycle that meets

the specified latch pulse width. The setup and hold times can

also be varied within the clock cycle as long as the specified

minimum times are met, although the location of these

transition edges may affect digital feedthrough and distortion

performance. Best performance is typically achieved when the

input data transitions on the falling edge of a 50% duty cycle clock.

AD9742

CLK+

CLOCK

RECEIVER

TO DAC CORE

CLK–

50Ω

V

= 1.3V NOM

TT

Figure 26. Clock Termination in PECL Mode\

Rev. C | Page 14 of 32

Data Sheet

AD9742

The power dissipation is directly proportional to the analog supply

current, I_AVDD, and the digital supply current, I_DVDD. I_AVDDis directly

proportional to I_OUTFS, as shown in Figure 28, and is insensitive to

DAC TIMING

Input Clock and Data Timing Relationship

Dynamic performance in a DAC is dependent on the relationship

between the position of the clock edges and the time at which

the input data changes. The AD9742 is rising edge triggered,

and so exhibits dynamic performance sensitivity when the data

transition is close to this edge. In general, the goal when applying

the AD9742 is to make the data transition close to the falling

clock edge. This becomes more important as the sample rate

increases. Figure 27 shows the relationship of SFDR to clock

placement with different sample rates. Note that at the lower

sample rates, more tolerance is allowed in clock placement,

while at higher rates, more care must be taken.

f

_CLOCK. Conversely, I_DVDDis dependent on both the digital input

waveform, f_CLOCK, and digital supply DVDD. Figure 29 shows

_DVDDas a function of full-scale sine wave output ratios

I

(f_OUT/f_CLOCK) for various update rates with DVDD = 3.3 V.

35

30

25

20

15

10

0

75

70

65

20MHz SFDR

60

55

50

45

40

35

2

4

6

8

10

12

14

16

18

20

I

(mA)

OUTFS

50MHz SFDR

Figure 28. I_AVDDvs. I_OUTFS

20

18

16

14

12

10

50MHz SFDR

–2

210MSPS

–3

–1

0

1

2

3

ns

165MSPS

125MSPS

Figure 27. SFDR vs. Clock Placement @ f_OUT= 20 MHz and 50 MHz

Sleep Mode Operation

8

6

4

The AD9742 has a power-down function that turns off the

output current and reduces the supply current to less than 6 mA

over the specified supply range of 2.7 V to 3.6 V and temperature

range. This mode can be activated by applying a Logic Level 1

to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω

AVDD. This digital input also contains an active pull-down circuit

that ensures that the AD9742 remains enabled if this input is

left disconnected. The AD9742 takes less than 50 ns to power

down and approximately 5 µs to power back up.

65MSPS

0.1

2

0

0.01

1

RATIO (f )

/f

OUT CLOCK

Figure 29. I_DVDDvs. Ratio @ DVDD = 3.3 V

12

POWER DISSIPATION

10

8

DIFF

The power dissipation, P_D, of the AD9742 is dependent on several

factors that include:

PECL

•

The power supply voltages (AVDD, CLKVDD, and DVDD)

The full-scale current output I_OUTFS

The update rate f_CLOCK

6

4

SE

The reconstructed digital input waveform

2

0

50

100

150

200

250

f

(MSPS)

CLOCK

Figure 30. I_CLKVDDvs. f_CLOCKand Clock Mode

Rev. C | Page 15 of 32

AD9742

Data Sheet

termination that results in a low VSWR. Note that approximately

APPLYING THE AD9742

Output Configurations

half the signal power will be dissipated across R_DIFF

.

DIFFERENTIAL COUPLING USING AN OP AMP

The following sections illustrate some typical output configurations

for the AD9742. Unless otherwise noted, it is assumed that I_OUTFSis

set to a nominal 20 mA. For applications requiring the optimum

dynamic performance, a differential output configuration is

suggested. A differential output configuration may consist of

either an RF transformer or a differential op amp configuration.

The transformer configuration provides optimum high frequency

performance and is recommended for any application that allows

ac coupling. The differential op amp configuration is suitable

for applications requiring dc coupling, a bipolar output, signal

gain, and/or level shifting within the bandwidth of the chosen

op amp.

An op amp can also be used to perform a differential-to-single-

ended conversion, as shown in Figure 32. The AD9742 is configured

with two equal load resistors, R_LOAD, of 25 Ω. The differential

voltage developed across IOUTA and IOUTB is converted to a

single-ended signal via the differential op amp configuration.

An optional capacitor can be installed across IOUTA and IOUTB,

forming a real pole in a low-pass filter. The addition of this

capacitor also enhances the op amp’s distortion performance by

preventing the DAC’s high slewing output from overloading the

op amp’s input.

500Ω

AD9742

A single-ended output is suitable for applications requiring a

unipolar voltage output. A positive unipolar output voltage will

result if IOUTA and/or IOUTB are connected to an appropriately

sized load resistor, R_LOAD, referred to ACOM. This configuration

may be more suitable for a single-supply system requiring a

dc-coupled, ground-referred output voltage. Alternatively, an

amplifier could be configured as an I-V converter, thus converting

IOUTA or IOUTB into a negative unipolar voltage. This

configuration provides the best dc linearity since IOUTA or

IOUTB is maintained at a virtual ground.

225Ω

22

21

IOUTA

AD8047

225Ω

IOUTB

C

OPT

500Ω

25Ω

Figure 32. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically

determined by the resistor matching. In this circuit, the

differential op amp circuit using the AD8047 is configured to

provide some additional signal gain. The op amp must operate

off a dual supply since its output is approximately 1 V. A high

speed amplifier capable of preserving the differential performance

of the AD9742 while meeting other system level objectives (e.g.,

cost or power) should be selected. The op amp’s differential gain,

gain setting resistor values, and full-scale output swing capabilities

should all be considered when optimizing this circuit.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to-single-

ended signal conversion, as shown in Figure 31. A differentially

coupled transformer output provides the optimum distortion

performance for output signals whose spectral content lies within

the transformer’s pass band. An RF transformer, such as the

Mini-Circuits T1–1T, provides excellent rejection of common-

mode distortion (that is, even-order harmonics) and noise over

a wide frequency range. It also provides electrical isolation and

the ability to deliver twice the power to the load. Transformers with

different impedance ratios may also be used for impedance matching

purposes. Note that the transformer provides ac coupling only.

The differential circuit shown in Figure 33 provides the necessary

level shifting required in a single-supply system. In this case,

AVDD, which is the positive analog supply for both the AD9742

and the op amp, is also used to level shift the differential output

of the AD9742 to midsupply (i.e., AVDD/2). The AD8041 is a

suitable op amp for this application.

MINI-CIRCUITS

T1-1T

IOUTA

22

500Ω

R

LOAD

AD9742

225Ω

IOUTB 21

22

IOUTA

OPTIONAL R

DIFF

AD8041

225Ω

21

IOUTB

Figure 31. Differential Output Using a Transformer

C

OPT

1kΩ

AVDD

The center tap on the primary side of the transformer must be

connected to ACOM to provide the necessary dc current path

for both IOUTA and IOUTB. The complementary voltages

appearing at IOUTA and IOUTB (i.e., V_OUTAand V_OUTB) swing

symmetrically around ACOM and should be maintained with the

specified output compliance range of the AD9742. A differential

resistor, R_DIFF, may be inserted in applications where the output

of the transformer is connected to the load, R_LOAD, via a passive

reconstruction filter or cable. R_DIFFis determined by the

25Ω

1kΩ

Figure 33. Single-Supply DC Differential Coupled Circuit

transformer’s impedance ratio and provides the proper source

Rev. C | Page 16 of 32

Data Sheet

AD9742

SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT

POWER AND GROUNDING CONSIDERATIONS,

POWER SUPPLY REJECTION

Figure 34 shows the AD9742 configured to provide a unipolar

output range of approximately 0 V to 0.5 V for a doubly terminated

50 Ω cable since the nominal full-scale current, I_OUTFS, of 20 mA

flows through the equivalent R_LOADof 25 Ω. In this case, R_LOAD

represents the equivalent load resistance seen by IOUTA or

IOUTB. The unused output (IOUTA or IOUTB) can be connected

to ACOM directly or via a matching R_LOAD. Different values of

Many applications seek high speed and high performance under

less than ideal operating conditions. In these application circuits,

the implementation and construction of the printed circuit

board is as important as the circuit design. Proper RF techniques

must be used for device selection, placement, and routing as

well as power supply bypassing and grounding to ensure

optimum performance. Figure 40 to Figure 43 illustrate the

recommended printed circuit board ground, power, and signal

plane layouts implemented on the AD9742 evaluation board.

I_OUTFSand R_LOADcan be selected as long as the positive compliance

range is adhered to. One additional consideration in this mode

is the integral nonlinearity (INL), discussed in the Analog Outputs

section. For optimum INL performance, the single-ended, buffered

voltage output configuration is suggested.

One factor that can measurably affect system performance is

the ability of the DAC output to reject dc variations or ac noise

superimposed on the analog or digital dc power distribution.

This is referred to as the power supply rejection ratio (PSRR).

For dc variations of the power supply, the resulting performance

of the DAC directly corresponds to a gain error associated with

the DAC’s full-scale current, I_OUTFS. AC noise on the dc supplies

is common in applications where the power distribution is

generated by a switching power supply. Typically, switching

power supply noise will occur over the spectrum from tens of

kHz to several MHz. The PSRR versus frequency of the AD9742

AVDD supply over this frequency range is shown in Figure 36.

85

I

= 20mA

OUTFS

AD9742

V

= 0V TO 0.5V

OUTA

22

21

IOUTA

50

Ω

50Ω

IOUTB

25Ω

Figure 34. 0 V to 0.5 V Unbuffered Voltage Output

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT

CONFIGURATION

Figure 35 shows a buffered single-ended output configuration

in which the op amp U1 performs an I-V conversion on the

AD9742 output current. U1 maintains IOUTA (or IOUTB) at a

virtual ground, minimizing the nonlinear output impedance

effect on the DAC’s INL performance as described in the Analog

Outputs section. Although this single-ended configuration typically

provides the best dc linearity performance, its ac distortion

performance at higher DAC update rates may be limited by U1’s

slew rate capabilities. U1 provides a negative unipolar output

voltage, and its full-scale output voltage is simply the product of

80

75

70

65

60

55

50

45

R

_FBand I_OUTFS. The full-scale output should be set within U1’s

voltage output swing capabilities by scaling I_OUTFSand/or R_FB. An

improvement in ac distortion performance may result with a

reduced I_OUTFSsince U1 will be required to sink less signal current.

40

0

2

4

6

8

10

12

FREQUENCY (MHz)

C

OPT

Figure 36. Power Supply Rejection Ratio (PSRR)

R

FB

Note that the ratio in Figure 36 is calculated as amps out/volts

in. Noise on the analog power supply has the effect of modulating

the internal switches, and therefore the output current. The

voltage noise on AVDD, therefore, will be added in a nonlinear

manner to the desired IOUT. Due to the relative different size of

these switches, the PSRR is very code dependent. This can produce

a mixing effect that can modulate low frequency power supply

noise to higher frequencies. Worst-case PSRR for either one of

the differential DAC outputs will occur when the full-scale current

is directed toward that output. As a result, the PSRR measurement

in Figure 36 represents a worst-case condition in which the

digital inputs remain static and the full-scale output current of

20 mA is directed to the DAC output being measured.

200Ω

I

= 10mA

OUTFS

AD9742

22

21

IOUTA

U1

V

= I

OUTFS

× R

FB

OUT

IOUTB

200Ω

Figure 35. Unipolar Buffered Voltage Output

Rev. C | Page 17 of 32

AD9742

Data Sheet

An example serves to illustrate the effect of supply noise on the

analog supply. Suppose a switching regulator with a switching

frequency of 250 kHz produces 10 mV of noise and, for simplicity’s

sake (ignoring harmonics), all of this noise is concentrated at

250 kHz. To calculate how much of this undesired noise will

appear as current noise superimposed on the DAC’s full-scale

current, I_OUTFS, one must determine the PSRR in dB using Figure 36

at 250 kHz. To calculate the PSRR for a given R_LOAD, such that the

units of PSRR are converted from A/V to V/V, adjust the curve in

Figure 36 by the scaling factor 20 Ω log (R_LOAD). For instance, if

possible. Similarly, DVDD, the digital supply, should be decoupled

to DCOM as close to the chip as physically possible.

For those applications that require a single 3.3 V supply for both

the analog and digital supplies, a clean analog supply may be

generated using the circuit shown in Figure 37. The circuit consists

of a differential LC filter with separate power supply and return

lines. Lower noise can be attained by using low ESR type

electrolytic and tantalum capacitors.

FERRITE

BEADS

AVDD

TTL/CMOS

R_LOADis 50 Ω, the PSRR is reduced by 34 dB (i.e., PSRR of the DAC

LOGIC

100µF

ELECT.

10µF–22µF

TANT.

0.1µF

CER.

CIRCUITS

at 250 kHz, which is 85 dB in Figure 36, becomes 51 dB V_OUT/V_IN).

ACOM

Proper grounding and decoupling should be a primary objective in

any high speed, high resolution system. The AD9742 features

separate analog and digital supplies and ground pins to optimize

the management of analog and digital ground currents in a

system. In general, AVDD, the analog supply, should be decoupled

to ACOM, the analog common, as close to the chip as physically

3.3V

POWER SUPPLY

Figure 37. Differential LC Filter for Single 3.3 V Applications

Rev. C | Page 18 of 32

Data Sheet

AD9742

EVALUATION BOARD

This board allows the user the flexibility to operate the AD9742

in various configurations. Possible output configurations include

transformer coupled, resistor terminated, and single and

differential outputs. The digital inputs are designed to be driven

from various word generators, with the on-board option to add

a resistor network for proper load termination. Provisions are

also made to operate the AD9742 with either the internal or

external reference or to exercise the power-down feature.

GENERAL DESCRIPTION

The TxDAC family evaluation boards allow for easy setup and

testing of any TxDAC product in the SOIC and LFCSP packages.

Careful attention to layout and circuit design, combined with a

prototyping area, allows the user to evaluate the AD9742 easily

and effectively in any application where high resolution, high

speed conversion is required.

J1

2

4

1

DB13X

DB12X

DB11X

DB10X

DB9X

DB8X

DB7X

DB6X

DB5X

DB4X

DB3X

DB2X

DB1X

DB0X

3

6

5

8

7

RP5

OPT

RP1

OPT

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

RP3 22Ω

RP4 22Ω

1

16

15

14

13

12

11

10

9

DB13X

DB12X

DB11X

DB10X

DB9X

DB8X

DB7X

DB6X

DB5X

DB4X

DB3X

DB2X

DB1X

DB0X

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

JP3

CKEXTX

9

CKEXT

CKEXTX

RIBBON

RP6

OPT

RP2

OPT

RED

TP2

L2 BEAD

DVDD

TB1

1

2

3

4

C4

+

C7

C6

10µF

25V

BLK

TP4

BLK

TP7

BLK

TP8

0.1µF

RED

TP5

L3 BEAD

AVDD

C5

10µF

25V

+

C9

0.1µF

C8

0.1µF

BLK

TP6

BLK

TP10

BLK

TP9

Figure 38. SOIC Evaluation Board—Power Supply and Digital Inputs

Rev. C | Page 19 of 32

AD9742

Data Sheet

AVDD

CUT

C14

10µF

16V

+

UNDER DUT

C16

0.1µF

C17

0.1µF

JP6

DVDD

C15

10µF

16V

JP10

C18

0.1µF

C19

0.1µF

1

3

A

B

IX

2

R5

OPT

S2

IOUTA

CLOCK

S5

R11

50Ω

CKEXT

CLOCK

DVDD

JP4

R4

50Ω

TP1

WHT

R2

10kΩ

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

C13

OPT

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

CLOCK

DVDD

DCOM

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

2

3

4

JP8

T1

DVDD

JP2

MODE

IOUT

S3

MODE

5

AVDD

3

4

5

6

AVDD

6

7

8

RESERVED

IOUTA

2

1

R6

OPT

U1

AD9742

IOUTB

9

ACOM

NC

FS ADJ

REFIO

REFLO

SLEEP

DB5

DB4

DB3

DB2

DB1

DB0

10

11

12

13

14

T1-1T

JP9

REF

TP3

WHT

C1

0.1µF

C2

0.1µF

C12

OPT

C11

0.1µF

R1

2kΩ

AVDD

2

R10

50Ω

AVDD

A

B

3

INT

SLEEP

S1

IOUTB

1

EXT

TP11

WHT

JP5

REF

R3

10kΩ

2

IY

A

B

3

1

JP11

Figure 39. SOIC Evaluation Board—Output Signal Conditioning

Rev. C | Page 20 of 32

Data Sheet

AD9742

Figure 40. SOIC Evaluation Board—Primary Side

Figure 41. SOIC Evaluation Board—Secondary Side

Rev. C | Page 21 of 32

AD9742

Data Sheet

Figure 42. SOIC Evaluation Board—Ground Plane

Figure 43. SOIC Evaluation Board—Power Plane

Rev. C | Page 22 of 32

Data Sheet

AD9742

Figure 44. SOIC Evaluation Board Assembly—Primary Side

Figure 45. SOIC Evaluation Board Assembly—Secondary Side

Rev. C | Page 23 of 32

AD9742

Data Sheet

RED

TP12

L1

BEAD

CVDD

TB1

1

2

4

6

1

3

5

DB13X

DB12X

DB11X

DB10X

DB9X

DB8X

DB7X

DB6X

DB5X

DB4X

DB3X

DB2X

DB1X

DB0X

BLK

C2

10µF

6.3V

C10

0.1µF

C3

0.1µF

TP2

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

7

9

11

13

15

17

19

21

23

25

27

29

RED

TP13

L2

BEAD

DVDD

TB3

1

BLK

C7

0.1µF

C4

10µF

6.3V

C6

0.1µF

TP4

TB3

TB4

2

1

RED

TP5

L3

BEAD

31

33

AVDD

JP3

CKEXTX

35

BLK

TP6

C9

0.1µF

C5

10µF

6.3V

C8

0.1µF

38

40

37

39

TB4

2

J1

R3

R4

R15

R16

R17

R18

R19

R20

100Ω

100Ω 100Ω 100Ω 100Ω 100Ω 100Ω 100Ω

1 RP3

2 RP3

3 RP3

4 RP3

5 RP3

6 RP3

7 RP3

8 RP3

1 RP4

2 RP4

3 RP4

4 RP4

22Ω 16

22Ω 15

22Ω 14

DB13X

DB13

DB12X

DB11X

DB10X

DB9X

DB8X

DB7X

DB6X

DB5X

DB4X

DB3X

DB2X

DB1X

DB0X

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

22Ω 13

22Ω 12

22Ω 11

22Ω 10

22Ω

9

22Ω 16

22Ω 15

22Ω 14

22Ω 13

22Ω 12

5 RP4

6 RP4

7 RP4

22Ω 11

22Ω 10

DB0

8 RP4

22Ω 9

CKEXT

CKEXTX

R21

R24

R25

R26

R27

R28

100Ω

Figure 46. LFCSP Evaluation Board Schematic—Power Supply and Digital Inputs

Rev. C | Page 24 of 32

Data Sheet

AD9742

AVDD

DVDD

CVDD

C19

0.1µF

C17

0.1µF

C32

0.1µF

SLEEP

TP11

WHT

R29

10kΩ

32

1

DB7

DB8

DB9

DB7

DB8

R11

50Ω

2

31

30

DB6

DB9

3

DVDD

DB5

DB10

DB11

DB12

DB13

DCOM1

SLEEP

FS ADJ

REFIO

ACOM

IA

DVDD

DB10

DB11

DB12

DB13

DNP

C13

4

5

29

28

DB5

DB4

27

6

DB3

7

26

25

JP8

T1

DB2

TP3

TP1

DB2

8

DB1

IOUT

DB1

WHT

9

10

24

23

DB0

DCOM

CVDD

CLK

3

4

U1

11

22

CVDD

S3

12

13

21

20

CLK

5

6

2

1

AGND: 3, 4, 5

CLKB

CCOM

CMODE

MODE

IB

CLKB

14

19

18

17

ACOM1

AVDD

AVDD1

15

AVDD C11

0.1µF

T1 – 1T

JP9

16

CMODE

AD9744LFCSP

DNP

C12

TP7

R30

10kΩ

WHT

R10

50Ω

CVDD

JP1

R1

2kΩ

0.1%

MODE

Figure 47. LFCSP Evaluation Board Schematic—Output Signal Conditioning

CVDD

1

7

U4

C20

2

C35

0.1µF

10µF

16V

AGND: 5

CVDD: 8

CVDD

R5

120Ω

3

4

CLKB

6

U4

JP2

S5

AGND: 3, 4, 5

CKEXT

CLK

C34

0.1µF

AGND: 5

CVDD: 8

R2

R6

120Ω

50Ω

Figure 48. LFCSP Evaluation Board Schematic—Clock Input

Rev. C | Page 25 of 32

AD9742

Data Sheet

Figure 49. LFCSP Evaluation Board Layout—Primary Side

Figure 50. LFCSP Evaluation Board Layout—Secondary Side

Rev. C | Page 26 of 32

Data Sheet

AD9742

Figure 51. LFCSP Evaluation Board Layout—Ground Plane

Figure 52. LFCSP Evaluation Board Layout—Power Plane

Rev. C | Page 27 of 32

AD9742

Data Sheet

Figure 53. LFCSP Evaluation Board Layout Assembly—Primary Side

Figure 54. LFCSP Evaluation Board Layout Assembly—Secondary Side

Rev. C | Page 28 of 32

Data Sheet

AD9742

OUTLINE DIMENSIONS

9.80

9.70

9.60

28

15

4.50

4.40

4.30

6.40 BSC

1

14

PIN 1

0.65

BSC

1.20 MAX

0.15

0.05

8°

0°

0.75

0.60

0.45

0.30

0.19

0.20

0.09

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AE

Figure 55. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

18.10 (0.7126)

17.70 (0.6969)

28

1

15

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

14

10.00 (0.3937)

0.75 (0.0295)

0.25 (0.0098)

45°

2.65 (0.1043)

2.35 (0.0925)

8°

0.30 (0.0118)

0.10 (0.0039)

0°

COPLANARITY

0.10

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)

BSC

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AE

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 56. 28-Lead Standard Small Outline Package [SOIC_W]

Wide Body (RW-28)

Dimensions shown in millimeters and (inches)

Rev. C | Page 29 of 32

AD9742

Data Sheet

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

25

24

32

1

INDICATOR

0.50

BSC

3.25

3.10 SQ

2.95

EXPOSED

PAD

17

16

8

9

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

AD9742AR

AD9742ARZ

AD9742ARZRL

AD9742ARU

AD9742ARURL7

AD9742ARUZ

AD9742ARUZRL7

AD9742ACPZ

AD9742ACPZRL7

AD9742-EBZ

Temperature Range

−40°C to +85°C

Package Description

Package Option

RW-28

RU-28

CP-32-7

28-Lead Standard Small Outline Package [SOIC]

28-Lead Thin Shrink Small Outline Package [TSSOP]

32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

Evaluation Board [SOIC]

AD9742ACP-PCBZ

Evaluation Board [LFCSP]

¹Z = RoHS Compliant Part.

Rev. C | Page 30 of 32

Data Sheet

NOTES

AD9742

Rev. C | Page 31 of 32

AD9742

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D02912-0-2/13(C)

Rev. C | Page 32 of 32


型号：	AD9742ACP-PCBZ
厂家：	ADI
描述：	12-Bit, 210 MSPS TxDAC Digital-to-Analog Converter 12位， 210 MSPS TxDAC系列数位类比转换器转换器
文件：	总32页 (文件大小：1071K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9742ACP-PCBZ [ADI]

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