AD9779A-EBZ_技术文档

Dual, 12-/14-/16-Bit,1 GSPS

Digital-to-Analog Converters

AD9776A/AD9778A/AD9779A

GENERAL DESCRIPTION

FEATURES

Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS,

full operating conditions

Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF

Analog output: adjustable 8.7 mA to 31.7 mA,

R_L= 25 Ω to 50 Ω

Novel 2×, 4×, and 8× interpolator/coarse complex modulator

allows carrier placement anywhere in DAC bandwidth

Auxiliary DACs allow control of external VGA and offset control

Multiple chip synchronization interface

High performance, low noise PLL clock multiplier

Digital inverse sinc filter

The AD9776A/AD9778A/AD9779A are dual, 12-/14-/16-bit,

high dynamic range digital-to-analog converters (DACs) that

provide a sample rate of 1 GSPS, permitting a multicarrier

generation up to the Nyquist frequency. They include features

optimized for direct conversion transmission applications,

including complex digital modulation and gain and offset

compensation. The DAC outputs are optimized to interface

seamlessly with analog quadrature modulators such as the

ADL537x FMOD series from Analog Devices, Inc. A 3-wire

interface provides for programming/readback of many internal

parameters. Full-scale output current can be programmed over

a range of 10 mA to 30 mA. The devices are manufactured on

an advanced 0.18 μm CMOS process and operate on 1.8 V and

3.3 V supplies for a total power consumption of 1.0 W. They are

enclosed in a 100-lead thin quad flat package (TQFP).

100-lead, exposed paddle TQFP

APPLICATIONS

Wireless infrastructure

W-CDMA, CDMA2000, TD-SCDMA, WiMax, GSM, LTE

Digital high or low IF synthesis

PRODUCT HIGHLIGHTS

Internal digital upconversion capability

Transmit diversity

Wideband communications: LMDS/MMDS, point-to-point

1. Ultralow noise and intermodulation distortion (IMD)

enable high quality synthesis of wideband signals from

baseband to high intermediate frequencies.

2. A proprietary DAC output switching technique enhances

dynamic performance.

3. The current outputs are easily configured for various

single-ended or differential circuit topologies.

4. CMOS data input interface with adjustable setup and hold.

5. Novel 2×, 4×, and 8× interpolator/coarse complex

modulator allows carrier placement anywhere in DAC

bandwidth.

TYPICAL SIGNAL CHAIN

QUADRATURE

MODULATOR/

MIXER/

COMPLEX I AND Q

AMPLIFIER

LO

DC

DIGITAL INTERPOLATION FILTERS

I DAC

POST DAC

ANALOG FILTER

FPGA/ASIC/DSP

Q DAC

A

AD9776A/AD9778A/AD9779A

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

AD9776A/AD9778A/AD9779A

TABLE OF CONTENTS

Features .............................................................................................. 1

Inverse Sinc Filter....................................................................... 38

Sourcing the DAC Sample Clock ................................................. 39

Direct Clocking .......................................................................... 39

Clock Multiplication.................................................................. 39

Driving the REFCLK Input....................................................... 42

Full-Scale Current Generation ..................................................... 43

Internal Reference ...................................................................... 43

Gain and Offset Correction .......................................................... 44

I/Q Channel Gain Matching..................................................... 44

Auxiliary DAC Operation......................................................... 44

LO Feedthrough Compensation .............................................. 45

Results of Gain and Offset Correction .................................... 45

Input Data Ports ............................................................................. 46

Single Port Mode........................................................................ 46

Dual Port Mode.......................................................................... 46

Input Data Referenced to DATACLK...................................... 46

Input Data Referenced to REFCLK ......................................... 47

Optimizing the Data Input Timing.......................................... 48

Device Synchronization................................................................. 49

Synchronization Logic Overview............................................. 49

Synchronizing Devices to a System Clock .............................. 50

Interrupt Request Operation .................................................... 50

Power Dissipation........................................................................... 51

Power-Down and Sleep Modes................................................. 52

Evaluation Board Overview.......................................................... 53

Evaluation Board Operation..................................................... 53

Outline Dimensions....................................................................... 55

Ordering Guide .......................................................................... 55

Applications....................................................................................... 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Typical Signal Chain......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

DC Specifications ......................................................................... 5

Digital Specifications ................................................................... 6

Digital Input Data Timing Specifications ................................. 7

AC Specifications.......................................................................... 8

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 16

Terminology .................................................................................... 24

Theory of Operation ...................................................................... 25

Differences Between AD9776/AD9778/ AD9779 and

AD9776A/AD9778A/AD9779A............................................... 25

3-Wire Interface.............................................................................. 26

General Operation of the Serial Interface............................... 26

Instruction Byte .......................................................................... 26

Serial Interface Port Pin Descriptions ..................................... 27

MSB/LSB Transfers..................................................................... 27

3-Wire Interface Register Map...................................................... 28

Interpolation Filter Architecture .................................................. 33

Interpolation Filter Bandwidth Limits .................................... 37

Rev. B | Page 2 of 56

AD9776A/AD9778A/AD9779A

REVISION HISTORY

9/08—Rev. A to Rev. B

Changes to Auxiliary DAC Operation Section ...........................44

Replaced Figure 79..........................................................................45

Deleted Figure 79; Renumbered Sequentially.............................41

Changes to LO Feedthrough Compensation Section.................45

Changes to Table 28 ........................................................................47

Changes to Optimizing the Data Input Timing Section............48

Change to Synchronization Logic Overview Section.................49

Changes to Figure 88 ......................................................................49

Changes to Figure 101 ....................................................................53

Deleted Using the ADL5372 Quadrature Modulator Section and

Figure 104....................................................................................51

Deleted Evaluation Board Schematics Section and Figure 105;

Renumbered Sequentially.........................................................52

Deleted Figure 106 ..........................................................................53

Deleted Figure 107 ..........................................................................54

Deleted Figure 108 ..........................................................................55

Deleted Figure 109 ..........................................................................56

Deleted Figure 110 ..........................................................................57

Deleted Figure 111 ..........................................................................58

Deleted Figure 112 ..........................................................................59

Updated Outline Dimensions........................................................60

Changed Serial Peripheral Interface (SPI) to 3-Wire Interface

Throughout ...................................................................................1

Change to Features Section..............................................................1

Change to Applications Section ......................................................1

Changes to Integral Nonlinearity (INL) Parameter, Table 1 .......5

Changes to DAC Clock Input (REFCLK+, REFCLK−)

Parameter, Table 2 ........................................................................6

Changes to Input Data Parameter, Table 3.....................................7

Changes to Hold Time Parameters, Table 3...................................7

Added 3-Wire Interface Parameter, Table 3...................................7

Added Reset Parameter, Table 3......................................................7

Changes to Endnotes, Table 3..........................................................7

Added Exposed Pad Notation to Figure 3, Changes to Table 7......10

Added Exposed Pad Notation to Figure 4, Changes to Table 8......12

Added Exposed Pad Notation to Figure 5, Changes to Table 9......14

Changes to DATACLK Delay Range Section ..............................25

Changes to Version Register Section............................................25

Changes to Table 10 ........................................................................25

Changes to Table 12 ........................................................................26

Changes to Table 13 ........................................................................28

Changes to Table 14 ........................................................................29

Changes to Interpolation Filter Architecture Section ................33

Changes to Figure 60 ......................................................................34

Changes to Table 19 ........................................................................36

Changes to Interpolation Filter Bandwidth Limits Section.......37

Changes to Figure 70 ......................................................................37

Added Digital Modulation Section...............................................37

Added Table 20 and Table 21; Renumbered Sequentially..........38

Added Inverse Sinc Filter Section .................................................38

Added Figure 71; Renumbered Sequentially...............................38

Changes to Clock Multiplication Section ....................................39

Changes to Figure 72 ......................................................................39

Changes to Configuring the PLL Band Select Value Section....39

Changes to Configuring the PLL Band Select with Temperature

Sensing Section...........................................................................41

Changes to Known Temperature Calibration with Memory

Section .........................................................................................41

Changes to Set-and-Forget Device Option Section....................41

Added Table 26 ................................................................................41

Changes to Internal Reference Section.........................................43

Changed Transmit Path Gain and Offset Correction Heading to

Gain and Offset Correction ......................................................44

Changes to I/Q Channel Gain Matching Section .......................44

3/08—Rev. 0 to Rev. A

Changes to Features..........................................................................1

Added Note 2.....................................................................................4

Changes to Table 2 ............................................................................5

Changes to Table 3 ............................................................................6

Changes to Thermal Resistance Section ........................................7

Inserted Table 6 .................................................................................8

Changes to Pin 39 Description, Table 7 .........................................9

Changes to Pin 39 Description, Table 8 .......................................10

Changes to Pin 39 Description, Table 9 .......................................12

Changes to Theory of Operation Section ....................................23

Changes to Table 10 ........................................................................23

Changes to Table 13 ........................................................................26

Changes to Table 14 ........................................................................27

Changes to Interpolation Filter Architecture Section................33

Replaced Sourcing the DAC Sample Clock Section...................36

Replaced Transmit Path Gain and Offset Correction Section ........40

Replaced Input Data Ports Section...............................................42

Replaced Device Synchronization Section ..................................45

Deleted Figure 112 to Figure 117..................................................58

8/07—Revision 0: Initial Version

Rev. B | Page 3 of 56

AD9776A/AD9778A/AD9779A

FUNCTIONAL BLOCK DIAGRAM

DELAY

LINE

SYNC_O

SYNC_I

CLOCK GENERATION/DISTRIBUTION

CLOCK

MULTIPLIER

2×/4×/8×

REFCLK+

REFCLK–

DELAY

DATACLK

LINE

DATA

ASSEMBLER

SINC^-1

OUT1_P

OUT1_N

16-BIT

I DAC

I

P1D[15:0]

LATCH

2×

n × f_DAC/8

n = 0, 1, 2 ... 7

Q

OUT2_P

OUT2_N

16-BIT

Q DAC

LATCH

P2D[15:0]

SINC^-1

VREF

I120

DIGITAL CONTROLLER

10

GAIN

SERIAL

PERIPHERAL

INTERFACE

POWER-ON

RESET

10

AUX1_P

AUX1_N

GAIN

AD9779A

AUX2_P

AUX2_N

Figure 2. AD9779A Functional Block Diagram

Rev. B | Page 4 of 56

AD9776A/AD9778A/AD9779A

SPECIFICATIONS

DC SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I_OUTFs= 20 mA, maximum sample rate, unless

otherwise noted.

Table 1.

AD9776A

Typ

AD9778A

Typ

AD9779A

Typ Max

16

Parameter

Min

Max

Min

Max

Min

Unit

RESOLUTION

12

14

Bits

ACCURACY

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

MAIN DAC OUTPUTS

Offset Error

Gain Error (with Internal Reference)

Full-Scale Output Current¹

Output Compliance Range

Output Resistance

0.1

0.86

0.65

1.5

2.1

6.0

LSB

−0.001

0

+0.001 −0.001

0

+0.001 −0.001

0

+0.001 % FSR

% FSR

2

20.2

2

20.2

2

8.66

−1.0

31.66

+1.0

8.66

−1.0

31.66

+1.0

8.66

−1.0

20.2 31.66

+1.0

10

mA

V

MΩ

10

Gain DAC Monotonicity

MAIN DAC TEMPERATURE DRIFT

Offset

Gain

Reference Voltage

Guaranteed

0.04

100

30

0.04

100

30

0.04

100

30

ppm/°C

AUXILIARY DAC OUTPUTS

Resolution

10

Bits

Full-Scale Output Current¹

Output Compliance Range (Source)

Output Compliance Range (Sink)

Output Resistance

−1.998

0

0.8

+1.998 −1.998

+1.998 mA

1.6

0

0.8

1.6

0

0.8

1.6

V

1

MΩ

Auxiliary DAC Monotonicity

REFERENCE

Guaranteed

Internal Reference Voltage

Output Resistance

1.2

5

1.2

5

1.2

5

V

kΩ

ANALOG SUPPLY VOLTAGES

AVDD33

CVDD18

3.13

1.70

3.3

1.8

3.47

2.05

3.13

1.70

3.3

1.8

3.47

2.05

3.13

1.70

3.3

1.8

3.47

2.05

V

DIGITAL SUPPLY VOLTAGES

DVDD33

DVDD18

3.13

1.70

3.3

1.8

3.47

2.05

3.13

1.70

3.3

1.8

3.47

2.05

3.13

1.70

3.3

1.8

3.47

2.05

V

POWER CONSUMPTION²

1× Mode, f_DAC= 100 MSPS, IF = 1 MHz

2× Mode, f_DAC= 320 MSPS, IF = 16 MHz, PLL Off

2× Mode, f_DAC= 320 MSPS, IF = 16 MHz, PLL On

4× Mode, f_DAC/4 Modulation, f_DAC= 500 MSPS,

IF = 137.5 MHz, Q DAC Off

250

498

588

572

300

250

498

588

572

300

250

498

588

572

300

mW

8× Mode, f_DAC/4 Modulation, f_DAC= 1 GSPS,

IF = 262.5 MHz

Power-Down Mode

980

2.5

980

2.5

980

2.5

mW

9.8

mW

Power Supply Rejection Ratio, AVDD33

OPERATING RANGE

−0.3

−40

+0.3

+85

−0.3

−40

+0.3

+85

−0.3

−40

+0.3

+85

% FSR/V

°C

+25

¹Based on a 10 kΩ external resistor.

²See the Power Dissipation section for more details.

Rev. B | Page 5 of 56

AD9776A/AD9778A/AD9779A

DIGITAL SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I_OUTFs= 20 mA, maximum sample rate, unless

otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.

Table 2.

Parameter

Conditions

Min

Typ Max

Unit

CMOS INPUT LOGIC LEVEL

Input V_INLogic High

Input V_INLogic Low

2.0

V

0.8

Maximum Input Data Rate at Interpolation

1×

2×

4×

8×

300

250

200

112.5

125

MSPS

DVDD18, CVDD18 = 1.8 V 5%

DVDD18, CVDD18 = 1.9 V 5%

DVDD18, CVDD18 = 2.0 V 2%

137.5

CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37)¹

Output V_OUTLogic High

Output V_OUTLogic Low

2.4

40

V

%

0.4

60

DATACLK Output Duty Cycle

At 250 MHz, into 5 pF load

SYNC_I+ = V_IA, SYNC_I− = V_IB

50

20

LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−)

Input Voltage Range, V_IAor V_IB

Input Differential Threshold, V_IDTH

Input Differential Hysteresis, V_IDTHH− V_IDTHL

Receiver Differential Input Impedance, R_IN

LVDS Input Rate

825

−100

1575 mV

+100 mV

mV

80

120

250

Ω

MSPS

Additional limits on f_{SYNC_I}apply; see description of

Register 0x05, Bits[3:1], in Table 14

Setup Time, SYNC_I to REFCLK

Hold Time, SYNC_I to REFCLK

LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−)

Output Voltage High, V_OAor V_OB

Output Voltage Low, V_OAor V_OB

Output Differential Voltage, |V_OD|

Output Offset Voltage, V_OS

0.4

0.55

ns

SYNC_O+ = V_OA, SYNC_O− = V_OB, 100 Ω termination

1375 mV

mV

1250 mV

1025

150

1150

80

200 250

Output Impedance, R_O

Single-ended

100 120

Ω

DAC CLOCK INPUT (REFCLK+, REFCLK−)

Differential Peak-to-Peak Voltage

Common-Mode Voltage

400

300

800 2000 mV

400 500

mV

Maximum Clock Rate

DVDD18, CVDD18 = 1.8 V 5%, PLL off

DVDD18, CVDD18 = 1.9 V 5%, PLL off

DVDD18, CVDD18 = 2.0 V 2%, PLL off

DVDD18, CVDD18 = 2.0 V 2%, PLL on

900

MHz

1000

1100

250

¹Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load, with maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests

using an external buffer for this signal.

Rev. B | Page 6 of 56

AD9776A/AD9778A/AD9779A

DIGITAL INPUT DATA TIMING SPECIFICATIONS

All modes, −40°C to +85°C.

Table 3.

Parameter

INPUT DATA¹

Conditions

Min

Typ

Max

Unit

Setup Time

Hold Time

Setup Time

Hold Time

Input data to DATACLK

Input data to REFCLK

3.0

ns

−0.05

−0.80

3.80

LATENCY

1× Interpolation

2× Interpolation

4× Interpolation

8× Interpolation

Inverse Sync

With or without modulation

25

70

146

297

18

DACCLK cycles

3-WIRE INTERFACE

Maximum Clock Rate (SCLK)

Minimum Pulse Width High, t_PWH

Minimum Pulse Width Low, t_PWL

Setup Time, t_DS

Hold Time, t_DH

40

MHz

ns

12.5

SDIO to SCLK

CSB to SCLK

SDO to SCLK

2.8

0.0

2.8

2.0

Setup Time, t_DS

Data Valid, t_DV

ns

POWER-UP TIME²

RESET

260

ms

Minimum Pulse Width, High

2

DACCLK cycles

¹Specified values are with PLL disabled. Timing vs. temperature and data valid keep out windows (that is, the minimum amount of time valid data must be presented to

the device to ensure proper sampling) are delineated in Table 28.

²Measured from CSB rising edge when Register 0x00, Bit 4, is written from 1 to 0 with the VREF decoupling capacitor equal to 0.1 μF.

Rev. B | Page 7 of 56

AD9776A/AD9778A/AD9779A

AC SPECIFICATIONS

T_MINto T_MAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, I_OUTFs= 20 mA, maximum sample rate, unless

otherwise noted.

Table 4.

AD9776A

Min Typ

AD9778A

Max Min Typ

AD9779A

Max Min Typ

Parameter

Max Unit

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_DAC= 100 MSPS, f_OUT= 20 MHz

f_DAC= 200 MSPS, f_OUT= 50 MHz

f_DAC= 400 MSPS, f_OUT= 70 MHz

f_DAC= 800 MSPS, f_OUT= 70 MHz

TWO-TONE INTERMODULATION DISTORTION (IMD)

f_DAC= 200 MSPS, f_OUT= 50 MHz

f_DAC= 400 MSPS, f_OUT= 60 MHz

f_DAC= 400 MSPS, f_OUT= 80 MHz

f_DAC= 800 MSPS, f_OUT= 100 MHz

82

81

80

85

82

81

80

85

82

80

87

dBc

87

80

75

87

85

81

80

91

85

81

dBc

NOISE SPECTRAL DENSITY (NSD), EIGHT-TONE, 500 kHz

TONE SPACING

f_DAC= 200 MSPS, f_OUT= 80 MHz

f_DAC= 400 MSPS, f_OUT= 80 MHz

f_DAC= 800 MSPS, f_OUT= 80 MHz

−152

−155

−157.5

−155

−159

−160

−158

−160

−161

dBm/Hz

W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),

SINGLE CARRIER

f_DAC= 491.52 MSPS, f_OUT= 100 MHz

f_DAC= 491.52 MSPS, f_OUT= 200 MHz

76

69

78

73

79

74

dBc

W-CDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO

(ACLR), SINGLE CARRIER

f_DAC= 491.52 MSPS, f_OUT= 100 MHz

f_DAC= 491.52 MSPS, f_OUT= 200 MHz

77.5

76

80

78

81

78

dBc

Rev. B | Page 8 of 56

AD9776A/AD9778A/AD9779A

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

With Respect To

Rating

AVDD33, DVDD33

AGND, DGND,

CGND

AGND, DGND,

CGND

DGND, CGND

AGND, CGND

AGND, DGND

AGND

−0.3 V to +3.6 V

DVDD18, CVDD18

−0.3 V to +2.1 V

AGND

DGND

CGND

I120, VREF, IPTAT

−0.3 V to +0.3 V

THERMAL RESISTANCE

−0.3 V to

For optimal thermal performance, the exposed paddle (EPAD)

should be soldered to the ground plane for the 100-lead,

thermally enhanced TQFP package.

AVDD33 + 0.3 V

−1.0 V to

AVDD33 + 0.3 V

OUT1_P, OUT1_N,

OUT2_P, OUT2_N,

AUX1_P, AUX1_N,

AUX2_P, AUX2_N

P1D[15:0], P2D[15:0]

DATACLK, TXENABLE

REFCLK+, REFCLK−

AGND

Typical θ_JAand θ_JCare specified for a 4-layer board in still air.

Airflow increases heat dissipation, effectively reducing θ_JA.

DGND

CGND

DGND

−0.3 V to

DVDD33 + 0.3 V

−0.3 V to

DVDD33 + 0.3 V

−0.3 V to

CVDD18 + 0.3 V

−0.3 V to

DVDD33 + 0.3 V

Table 6. Thermal Resistance

Package Type

100-Lead TQFP

EPAD Soldered

EPAD Not Soldered

θ_JA

θ_JB

θ_JC

Unit

19.1

27.4

12.4

7.1

°C/W

RESET, IRQ, PLL_LOCK,

SYNC_O+, SYNC_O−,

SYNC_I+, SYNC_I−,

CSB, SCLK, SDIO, SDO

ESD CAUTION

Junction Temperature

+125°C

Storage Temperature

Range

−65°C to +150°C

Rev. B | Page 9 of 56

AD9776A/AD9778A/AD9779A

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

CVDD18

CGND

I120

PIN 1

2

VREF

IPTAT

AGND

IRQ

3

ANALOG DOMAIN

DIGITAL DOMAIN

4

CGND

5

REFCLK+

REFCLK–

CGND

6

RESET

CSB

7

8

CGND

SCLK

SDIO

9

AD9776A

CVDD18

CGND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

SDO

TOP VIEW

(Not to Scale)

PLL_LOCK

DGND

SYNC_O+

SYNC_O–

DVDD33

DVDD18

NC

AGND

SYNC_I+

SYNC_I–

DGND

DVDD18

P1D11

P1D10

NC

P1D9

NC

P1D8

NC

P1D7

P2D0

DGND

DVDD18

P2D1

DVDD18

P1D6

P1D5

P2D2

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NC = NO CONNECT

NOTES

1. FOR OPTIMAL THERMAL PERFORMANCE, THE EXPOSED

PAD SHOULD BE SOLDERED TO THE GROUND PLANE FOR

THE 100-LEAD, THERMALLY ENHANCED TQFP PACKAGE.

Figure 3. AD9776A Pin Configuration

Table 7. AD9776A Pin Function Descriptions

No.

Mnemonic Description

1

2

3

4

5

6

7

8

CVDD18

CGND

1.8 V Clock Supply.

Clock Ground.

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

P1D11

P1D10

P1D9

P1D8

P1D7

DGND

DVDD18

P1D6

P1D5

P1D4

P1D3

P1D2

P1D1

P1D0

NC

Port 1, Data Input D11 (MSB).

Port 1, Data Input D10.

Port 1, Data Input D9.

Port 1, Data Input D8.

Port 1, Data Input D7.

Digital Ground.

1.8 V Digital Supply.

Port 1, Data Input D6.

Port 1, Data Input D5.

Port 1, Data Input D4.

Port 1, Data Input D3.

Port 1, Data Input D2.

Port 1, Data Input D1.

Port 1, Data Input D0 (LSB).

No Connect.

CGND

Clock Ground.

REFCLK+

REFCLK−

CGND

Differential Clock Input.

Clock Ground.

CGND

Clock Ground.

9

CVDD18

CGND

1.8 V Clock Supply.

Clock Ground.

10

11

12

13

14

15

16

AGND

Analog Ground.

SYNC_I+

SYNC_I−

DGND

Differential Synchronization Input.

Digital Ground.

DVDD18

1.8 V Digital Supply.

DGND

Digital Ground.

Rev. B | Page 10 of 56

AD9776A/AD9778A/AD9779A

No.

Mnemonic Description

33

34

35

36

37

38

39

DVDD18

NC

DATACLK

DVDD33

1.8 V Digital Supply.

No Connect.

Data Clock Output.

3.3 V Digital Supply.

69

70

71

72

73

CSB

RESET

IRQ

AGND

IPTAT

3-Wire Interface Port Chip Select Bar.

Reset, Active High.

Interrupt Request.

Analog Ground.

Factory Test Pin. Output current is

proportional to absolute temperature,

approximately 14 μA at 25°C with

approximately 20 nA/°C slope. This pin

should remain floating.

Voltage Reference Output.

120 μA Reference Current.

3.3 V Analog Supply.

Analog Ground.

3.3 V Analog Supply.

Analog Ground.

3.3 V Analog Supply.

TXENABLE/ Transmit Enable. In single port mode, this

IQSELECT

P2D11

P2D10

P2D9

DVDD18

DGND

P2D8

P2D7

P2D6

P2D5

P2D4

P2D3

P2D2

P2D1

DVDD18

DGND

P2D0

NC

pin also functions as IQSELECT.

Port 2, Data Input D11 (MSB).

Port 2, Data Input D10.

Port 2, Data Input D9.

1.8 V Digital Supply.

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

VREF

I120

AVDD33

AGND

AVDD33

AGND

AVDD33

AGND

OUT2_P

OUT2_N

AGND

AUX2_P

AUX2_N

AGND

AUX1_N

AUX1_P

AGND

OUT1_N

OUT1_P

AGND

AVDD33

AGND

Digital Ground.

Port 2, Data Input D8.

Port 2, Data Input D7.

Port 2, Data Input D6.

Port 2, Data Input D5.

Port 2, Data Input D4.

Port 2, Data Input D3.

Port 2, Data Input D2.

Port 2, Data Input D1.

1.8 V Digital Supply.

Digital Ground.

Port 2, Data Input D0 (LSB).

No Connect.

1.8 V Digital Supply.

3.3 V Digital Supply.

Differential Synchronization Output.

Digital Ground.

Analog Ground.

Differential DAC Current Output, Channel 2.

Analog Ground.

Auxiliary DAC Current Output, Channel 2.

Analog Ground.

Auxiliary DAC Current Output, Channel 1.

Analog Ground.

Differential DAC Current Output, Channel 1.

Analog Ground.

3.3 V Analog Supply.

Analog Ground.

3.3 V Analog Supply.

Analog Ground.

3.3 V Analog Supply.

NC

DVDD18

DVDD33

SYNC_O−

SYNC_O+

DGND

PLL_LOCK

SDO

AVDD33

AGND

PLL Lock Indicator.

3-Wire Interface Port Data Output.

3-Wire Interface Port Data Input/Output.

3-Wire Interface Port Clock.

100 AVDD33

SDIO

SCLK

Rev. B | Page 11 of 56

AD9776A/AD9778A/AD9779A

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

CVDD18

CGND

I120

PIN 1

2

VREF

IPTAT

AGND

IRQ

3

ANALOG DOMAIN

DIGITAL DOMAIN

4

CGND

5

REFCLK+

REFCLK–

CGND

6

RESET

CSB

7

8

CGND

SCLK

SDIO

9

CVDD18

CGND

AD9778A

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

SDO

TOP VIEW

(Not to Scale)

PLL_LOCK

DGND

SYNC_O+

SYNC_O–

DVDD33

DVDD18

NC

AGND

SYNC_I+

SYNC_I–

DGND

DVDD18

P1D13

P1D12

NC

P1D11

P2D0

P1D10

P2D1

P1D9

P2D2

DGND

DVDD18

P2D3

DVDD18

P1D8

P1D7

P2D4

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NC = NO CONNECT

NOTES

1. FOR OPTIMAL THERMAL PERFORMANCE, THE EXPOSED

PAD SHOULD BE SOLDERED TO THE GROUND PLANE FOR

THE 100-LEAD, THERMALLY ENHANCED TQFP PACKAGE.

Figure 4. AD9778A Pin Configuration

Table 8. AD9778A Pin Function Descriptions

No.

Mnemonic Description

1

2

3

4

5

6

7

8

CVDD18

CGND

1.8 V Clock Supply.

Clock Ground.

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

P1D11

P1D10

P1D9

DGND

DVDD18

P1D8

P1D7

P1D6

P1D5

P1D4

P1D3

P1D2

P1D1

DGND

DVDD18

P1D0

NC

Port 1, Data Input D11.

Port 1, Data Input D10.

Port 1, Data Input D9.

Digital Ground.

CGND

Clock Common.

REFCLK+

REFCLK−

CGND

Differential Clock Input.

Clock Ground.

1.8 V Digital Supply.

Port 1, Data Input D8.

Port 1, Data Input D7.

Port 1, Data Input D6.

Port 1, Data Input D5.

Port 1, Data Input D4.

Port 1, Data Input D3.

Port 1, Data Input D2.

Port 1, Data Input D1.

Digital Ground.

CGND

Clock Ground.

9

CVDD18

CGND

1.8 V Clock Supply.

Clock Ground.

10

11

12

13

14

15

16

17

18

AGND

Analog Ground.

SYNC_I+

SYNC_I−

DGND

DVDD18

P1D13

Differential Synchronization Input.

Digital Ground.

1.8 V Digital Supply.

Port 1, Data Input D13 (MSB).

Port 1, Data Input D12.

1.8 V Digital Supply.

Port 1, Data Input D0 (LSB).

No Connect.

P1D12

NC

No Connect.

Rev. B | Page 12 of 56

AD9776A/AD9778A/AD9779A

No.

Mnemonic Description

DATACLK

DVDD33

37

38

39

Data Clock Output.

3.3 V Digital Supply.

71

72

73

IRQ

AGND

IPTAT

Interrupt Request.

Analog Ground.

Factory Test Pin. Output current is

proportional to absolute temperature,

approximately 14 μA at 25°C with

approximately 20 nA/°C slope. This pin

should remain floating.

Voltage Reference Output.

120 μA Reference Current.

3.3 V Analog Supply.

Analog Ground.

3.3 V Analog Supply.

Analog Ground.

3.3 V Analog Supply.

TXENABLE/ Transmit Enable. In single port mode, this

IQSELECT

P2D13

P2D12

P2D11

DVDD18

DGND

P2D10

P2D9

P2D8

P2D7

P2D6

P2D5

P2D4

P2D3

DVDD18

DGND

P2D2

P2D1

P2D0

NC

DVDD18

DVDD33

SYNC_O−

SYNC_O+

DGND

PLL_LOCK

SDO

SDIO

SCLK

CSB

RESET

pin also functions as IQSELECT.

Port 2, Data Input D13 (MSB).

Port 2, Data Input D12.

Port 2, Data Input D11.

1.8 V Digital Supply.

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

VREF

I120

AVDD33

AGND

AVDD33

AGND

AVDD33

AGND

OUT2_P

OUT2_N

AGND

AUX2_P

AUX2_N

AGND

AUX1_N

AUX1_P

AGND

OUT1_N

OUT1_P

AGND

AVDD33

AGND

Digital Ground.

Port 2, Data Input D10.

Port 2, Data Input D9.

Port 2, Data Input D8.

Port 2, Data Input D7.

Port 2, Data Input D6.

Port 2, Data Input D5.

Port 2, Data Input D4.

Port 2, Data Input D3.

1.8 V Digital Supply.

Analog Ground.

Differential DAC Current Output, Channel 2.

Analog Ground.

Auxiliary DAC Current Output, Channel 2.

Analog Ground.

Auxiliary DAC Current Output, Channel 1.

Analog Ground.

Differential DAC Current Output, Channel 1.

Analog Ground.

3.3 V Analog Supply.

Analog Ground.

3.3 V Analog Supply.

Analog Ground.

3.3 V Analog Supply.

Digital Ground.

Port 2, Data Input D2.

Port 2, Data Input D1.

Port 2, Data Input D0 (LSB).

No Connect.

1.8 V Digital Supply.

3.3 V Digital Supply.

Differential Synchronization Output.

Digital Ground.

PLL Lock Indicator.

3-Wire Interface Port Data Output.

3-Wire Interface Port Data Input/Output.

3-Wire Interface Port Clock.

3-Wire Interface Port Chip Select Bar.

Reset, Active High.

AVDD33

AGND

100 AVDD33

Rev. B | Page 13 of 56

AD9776A/AD9778A/AD9779A

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

CVDD18

CGND

I120

PIN 1

2

VREF

3

IPTAT

AGND

IRQ

ANALOG DOMAIN

DIGITAL DOMAIN

4

CGND

5

REFCLK+

REFCLK–

CGND

6

RESET

CSB

7

8

CGND

SCLK

SDIO

9

CVDD18

CGND

AD9779A

TOP VIEW

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

SDO

(Not to Scale)

PLL_LOCK

DGND

SYNC_O+

SYNC_O–

DVDD33

DVDD18

P2D0

AGND

SYNC_I+

SYNC_I–

DGND

DVDD18

P1D15

P1D14

P2D1

P1D13

P2D2

P1D12

P2D3

P1D11

P2D4

DGND

DVDD18

P2D5

DVDD18

P1D10

P1D9

P2D6

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NOTES

1. FOR OPTIMAL THERMAL PERFORMANCE, THE EXPOSED

PAD SHOULD BE SOLDERED TO THE GROUND PLANE FOR

THE 100-LEAD, THERMALLY ENHANCED TQFP PACKAGE.

Figure 5. AD9779A Pin Configuration

Table 9. AD9779A Pin Function Descriptions

No. Mnemonic Description

1

2

3

4

5

6

7

8

CVDD18

CGND

1.8 V Clock Supply.

Clock Ground.

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

P1D13

P1D12

P1D11

DGND

DVDD18

P1D10

P1D9

P1D8

P1D7

P1D6

P1D5

P1D4

P1D3

DGND

DVDD18

P1D2

Port 1, Data Input D13.

Port 1, Data Input D12.

Port 1, Data Input D11.

Digital Ground.

CGND

Clock Ground.

REFCLK+

REFCLK−

CGND

Differential Clock Input.

Clock Ground.

1.8 V Digital Supply.

Port 1, Data Input D10.

Port 1, Data Input D9.

Port 1, Data Input D8.

Port 1, Data Input D7.

Port 1, Data Input D6.

Port 1, Data Input D5.

Port 1, Data Input D4.

Port 1, Data Input D3.

Digital Ground.

CGND

Clock Ground.

9

CVDD18

CGND

1.8 V Clock Supply.

Clock Ground.

10

11

12

13

14

15

16

17

18

AGND

Analog Ground.

SYNC_I+

SYNC_I−

DGND

DVDD18

P1D15

Differential Synchronization Input.

Digital Ground.

1.8 V Digital Supply.

Port 1, Data Input D15 (MSB).

Port 1, Data Input D14.

1.8 V Digital Supply.

Port 1, Data Input D2.

Port 1, Data Input D1.

Port 1, Data Input D0 (LSB).

P1D1

P1D0

P1D14

Rev. B | Page 14 of 56

AD9776A/AD9778A/AD9779A

No. Mnemonic Description

DATACLK

DVDD33

37

38

39

Data Clock Output.

3.3 V Digital Supply.

71

72

73

IRQ

AGND

IPTAT

Interrupt Request.

Analog Ground.

Factory Test Pin. Output current is

proportional to absolute temperature,

approximately 14 μA at 25°C with

approximately 20 nA/°C slope. This pin

should remain floating.

Voltage Reference Output.

120 μA Reference Current.

3.3 V Analog Supply.

Analog Ground.

3.3 V Analog Supply.

Analog Ground.

3.3 V Analog Supply.

TXENABLE/ Transmit Enable. In single port mode, this

IQSELECT

P2D15

P2D14

P2D13

DVDD18

DGND

P2D12

P2D11

P2D10

P2D9

P2D8

P2D7

P2D6

P2D5

DVDD18

DGND

P2D4

P2D3

P2D2

pin also functions as IQSELECT.

Port 2, Data Input D15 (MSB).

Port 2, Data Input D14.

Port 2, Data Input D13.

1.8 V Digital Supply.

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

VREF

I120

AVDD33

AGND

AVDD33

AGND

AVDD33

AGND

OUT2_P

OUT2_N

AGND

AUX2_P

AUX2_N

AGND

AUX1_N

AUX1_P

AGND

OUT1_N

OUT1_P

AGND

AVDD33

AGND

Digital Ground.

Port 2, Data Input D12.

Port 2, Data Input D11.

Port 2, Data Input D10.

Port 2, Data Input D9.

Port 2, Data Input D8.

Port 2, Data Input D7.

Port 2, Data Input D6.

Port 2, Data Input D5.

1.8 V Digital Supply.

Digital Ground.

Port 2, Data Input D4.

Port 2, Data Input D3.

Port 2, Data Input D2.

Port 2, Data Input D1.

Port 2, Data Input D0 (LSB).

1.8 V Digital Supply.

3.3 V Digital Supply.

Differential Synchronization Output.

Digital Ground.

Analog Ground.

Differential DAC Current Output, Channel 2.

Analog Ground.

Auxiliary DAC Current Output, Channel 2.

Analog Ground.

Auxiliary DAC Current Output, Channel 1.

Analog Ground.

Differential DAC Current Output, Channel 1.

Analog Ground.

3.3 V Analog Supply.

Analog Ground.

3.3 V Analog Supply.

Analog Ground.

3.3 V Analog Supply.

P2D1

P2D0

DVDD18

DVDD33

SYNC_O−

SYNC_O+

DGND

PLL_LOCK

SDO

SDIO

SCLK

CSB

RESET

PLL Lock Indicator.

3-Wire Interface Port Data Output.

3-Wire Interface Port Data Input/Output.

3-Wire Interface Port Clock.

3-Wire Interface Port Chip Select Bar.

Reset, Active High.

AVDD33

AGND

100 AVDD33

Rev. B | Page 15 of 56

AD9776A/AD9778A/AD9779A

TYPICAL PERFORMANCE CHARACTERISTICS

100

90

80

70

60

50

4

3

f_DATA= 160MSPS

2

f_DATA= 200MSPS

1

0

–1

–2

–3

–4

–5

–6

f_DATA= 250MSPS

0

20

40

60

80

100

50

0

10k

20k

30k

CODE

40k

50k

60k

f_OUT(MHz)

Figure 9. AD9779A In-Band SFDR vs. f_OUT

,

Figure 6. AD9779A Typical INL

2× Interpolation

100

90

80

70

60

50

1.5

1.0

f_DATA= 200MSPS

f_DATA= 100MSPS

0.5

0

f_DATA= 150MSPS

–0.5

–1.0

–1.5

–2.0

20

40

60

80

0

10k

20k

30k

CODE

40k

50k

60k

f_OUT(MHz)

Figure 7. AD9779A Typical DNL

Figure 10. AD9779A In-Band SFDR vs. f_OUT

,

4× Interpolation

100

90

80

70

60

50

100

90

80

70

60

50

f_DATA= 100MSPS

f_DATA= 50MSPS

f_DATA= 160MSPS

f_DATA= 250MSPS

f_DATA= 125MSPS

f_DATA= 200MSPS

0

20

40

60

80

100

10

20

30

40

f_OUT(MHz)

Figure 8. AD9779A In-Band SFDR vs. f_OUT

,

Figure 11. AD9779A In-Band SFDR vs. f_OUT

,

1× Interpolation

8× Interpolation

Rev. B | Page 16 of 56

AD9776A/AD9778A/AD9779A

100

90

80

70

60

50

100

90

80

70

60

50

PLL OFF

PLL ON

f_DATA= 160MSPS

f_DATA= 200MSPS

f_DATA= 250MSPS

0

20

40

60

80

100

50

0

10

20

30

40

80

f_OUT(MHz)

Figure 12. AD9779A Out-of-Band SFDR vs. f_OUT

,

Figure 15. AD9779A In-Band SFDR vs. f_OUT,

4× Interpolation, f_DATA= 100 MSPS, PLL On/Off

2× Interpolation

100

90

80

70

60

50

100

90

80

70

60

50

0dBFS

–3dBFS

–6dBFS

f_DATA= 150MSPS

f_DATA= 100MSPS

f_DATA= 200MSPS

20

40

60

80

20

40

60

f_OUT(MHz)

Figure 13. AD9779A Out-of-Band SFDR vs. f_OUT

,

Figure 16. AD9779A In-Band SFDR vs. f_OUT

,

4× Interpolation

Digital Full Scale

100

90

80

70

60

50

100

90

80

70

60

50

10mA

20mA

f_DATA= 50MSPS

f_DATA= 100MSPS

30mA

f_DATA= 125MSPS

10

20

30

40

20

40

60

f_OUT(MHz)

Figure 14. AD9779A Out-of-Band SFDR vs. f_OUT

,

Figure 17. AD9779A In-Band SFDR vs. f_OUT

,

8× Interpolation

Output Full-Scale Current

Rev. B | Page 17 of 56

AD9776A/AD9778A/AD9779A

100

90

80

70

60

50

f_DATA= 160MSPS

f_DATA= 200MSPS

90

80

70

60

50

f_DATA= 250MSPS

f_DATA= 75MSPS

f_DATA= 100MSPS

f_DATA= 50MSPS

f_DATA= 125MSPS

0

20

40

60

80

100

120

f_OUT(MHz)

Figure 21. AD9779A Third-Order IMD vs. f_OUT

,

Figure 18. AD9779A Third-Order IMD vs. f_OUT

,

8× Interpolation

1× Interpolation

100

90

80

70

60

50

100

90

80

70

60

50

f_DATA= 160MSPS

PLL OFF

f_DATA= 200MSPS

PLL ON

f_DATA= 250MSPS

0

20

40

60

80 100 120 140 160 180 200 220

f_OUT(MHz)

0

20

40

60

80

100 120 140 160 180 200

f_OUT(MHz)

Figure 19. AD9779A Third-Order IMD vs. f_OUT

,

Figure 22. AD9779A Third-Order IMD vs. f_OUT

,

4× Interpolation, f_DATA= 100 MSPS, PLL On/Off

2× Interpolation

100

90

80

70

60

50

100

95

90

85

80

f_DATA= 150MSPS

75

70

65

60

f_DATA= 100MSPS

f_DATA= 200MSPS

55

50

0

40

80

120 160 200 240 280 320 360 400

f_OUT(MHz)

0

40

80

120 160 200 240 280 320 360 400

f_OUT(MHz)

Figure 20. AD9779A Third-Order IMD vs. f_OUT

,

Figure 23. AD9779A Third-Order IMD vs. f_OUT

,

4× Interpolation

Over 50 Parts, 4× Interpolation, f_DATA= 200 MSPS

Rev. B | Page 18 of 56

AD9776A/AD9778A/AD9779A

100

95

90

85

80

75

70

65

60

55

50

REF 0dBm

*ATTEN 20dB

*PEAK

Log

10dB

EXT REF

DC-COUPLED

0dBFS

–3dBFS

LGAV

51

–6dBFS

S2

FC

AA

W1

S3

£(f):

FTUN

SWP

0

40

80

120 160 200 240 280 320 360 400

f_OUT(MHz)

START 1.0MHz

*RES BW 20kHz

STOP 400.0MHz

SWEEP 1.203s (601 pts)

VBW 20kHz

Figure 24. AD9779A IMD Performance vs. f_OUT

Digital Full-Scale Input Over Output Frequency,

4× Interpolation, f_DATA= 200 MSPS

,

Figure 27. AD9779A Two-Tone Spectrum,

4× Interpolation, f_DATA= 100 MSPS, f_OUT= 30 MHz, 35 MHz

100

95

90

85

80

75

70

65

60

55

50

–142

–146

20mA

10mA

–150

–154

–158

–162

–3dBFS

0dBFS

30mA

–6dBFS

–166

–170

0

20

40

f_OUT(MHz)

60

80

0

40

80

120 160 200 240 280 320 360 400

f_OUT(MHz)

Figure 25. AD9779A IMD Performance vs. f_OUT

,

Figure 28. AD9779A Noise Spectral Density vs. f_OUT,

Full-Scale Output Current Over Output Frequency,

4× Interpolation, f_DATA= 200 MSPS

Digital Full-Scale Over Output Frequency of Single-Tone Input,

2× Interpolation, f_DATA= 200 MSPS

REF 0dBm

*ATTEN 20dB

–150

*PEAK

log

10dB

EXT REF

–154

DC-COUPLED

f_DAC= 400MSPS

–158

–162

–166

–170

f_DAC= 200MSPS

LGAV

51

S2

FC

AA

W1

S3

f_DAC= 800MSPS

£(f):

FTUN

SWP

0

20

40

60

80

100

START 1.0MHz

*RES BW 20kHz

STOP 400.0MHz

SWEEP 1.203s (601 pts)

VBW 20kHz

f_OUT(MHz)

Figure 29. AD9779A Noise Spectral Density vs. f_OUT

f_DACOver Output Frequency for Eight-Tone Input with 500 kHz Spacing,

f_DATA= 200 MSPS

,

Figure 26. AD9779A Single Tone,

4× Interpolation, f_DATA= 100 MSPS, f_OUT= 30 MHz

Rev. B | Page 19 of 56

AD9776A/AD9778A/AD9779A

–150

–55

–60

–65

–70

–75

–80

–85

–90

–154

0dBFS, PLL ENABLED

–6dBFS, PLL DISABLED

f_DAC= 200MSPS

–158

f_DAC= 400MSPS

–162

–166

–170

f_DAC= 800MSPS

0dBFS, PLL DISABLED

–3dBFS, PLL DISABLED

0

20

40

60

80

100

0

20 40 60 80 100 120 140 160 180 200 220 240 260

f_OUT(MHz)

Figure 30. AD9779A Noise Spectral Density vs. f_OUT

f_DACOver Output Frequency with a Single-Tone Input at −6 dBFS

,

Figure 33. AD9779A ACLR for Second Adjacent Band W-CDMA,

4× Interpolation, f_DATA= 122.88 MSPS,

On-Chip Modulation Translates Baseband Signal to IF

–55

–60

–65

–60

0dBFS, PLL ENABLED

–65

0dBFS, PLL DISABLED

–70

–6dBFS, PLL DISABLED

–75

0dBFS, PLL ENABLED

–3dBFS, PLL DISABLED

–80

–6dBFS, PLL DISABLED

–85

–90

–85

–90

0dBFS, PLL DISABLED

–3dBFS, PLL DISABLED

0

20 40 60 80 100 120 140 160 180 200 220 240 260

f_OUT(MHz)

0

20 40 60 80 100 120 140 160 180 200 220 240 260

f_OUT(MHz)

Figure 31. AD9779A ACLR for First Adjacent Band W-CDMA,

4× Interpolation, f_DATA= 122.88 MSPS,

On-Chip Modulation Translates Baseband Signal to IF

Figure 34. AD9779A ACLR for Third Adjacent Band W-CDMA,

4× Interpolation, f_DATA= 122.88 MSPS,

On-Chip Modulation Translates Baseband Signal to IF

REF –30.28dBm

*ATTEN 4dB

REF –25.28dBm

*ATTEN 4dB

*AVG

log

10dB

*AVG

log

10dB

EXT REF

PAVG

10

W1 S2

PAVG

10

W1 S2

CENTER 151.38MHz

*RES BW 30kHz

TOTAL CARRIER POWER –12.61dBm/15.3600MHz

REF CARRIER POWER –17.87dBm/3.84000MHz

SPAN 50MHz

SWEEP 162.2ms (601 pts)

VBW 300kHz

CENTER 143.88MHz

*RES BW 30kHz

SPAN 50MHz

SWEEP 162.2ms (601 pts)

VBW 300kHz

LOWER

UPPER

LOWER

dBm

UPPER

dBc dBm

3.840MHz –67.70 –85.57 –67.70 –85.57

3.840MHz –70.00 –97.87 –69.32 –87.19

3.840MHz –71.65 –99.52 –71.00 –88.88

RMS RESULTS FREQ OFFSET REF BW

CARRIER POWER 5.000MHz

–12.49dBm/

3.84000MHz

dBc dBm

FREQ OFFSET INTEG BW dBc

3.840MHz –76.75 –89.23 –77.42 –89.91

3.840MHz –80.94 –93.43 –80.47 –92.96

3.840MHz –79.95 –92.44 –78.96 –91.45

1 –17.87dBm

2 –20.65dBm

3 –18.26dBm

4 –18.23dBm

5.000MHz

10.00MHz

15.00MHz

10.00MHz

15.00MHz

Figure 32. AD9779A W-CDMA Signal,

4× Interpolation, f_DATA= 122.88 MSPS, f_DAC/4 Modulation

Figure 35. AD9779A Multicarrier W-CDMA Signal,

4× Interpolation, f_DAC= 122.88 MSPS, f_DAC/4 Modulation

Rev. B | Page 20 of 56

AD9776A/AD9778A/AD9779A

100

90

80

70

60

50

1.5

1.0

f_DATA= 200MSPS

f_DATA= 160MSPS

0.5

0

f_DATA= 250MSPS

–0.5

–1.0

–1.5

0

20

40

60

80

100

0

2k

4k

6k

8k

10k

f_OUT(MHz)

CODE

Figure 36. AD9778A Typical INL

Figure 39. AD9778A In-Band SFDR vs. f_OUT

,

2× Interpolation

0.6

0.4

–60

–70

0.2

0

FIRST ADJACENT CHANNEL

–0.2

–0.4

–0.6

–0.8

–1.0

THIRD ADJACENT

CHANNEL

–80

–90

SECOND ADJACENT

CHANNEL

0

25

50

75

100 125 150 175 200 225 250

f_OUT(MHz)

0

2k

4k

6k

8k

10k

12k

14k

16k

CODE

Figure 37. AD9778A Typical DNL

Figure 40. AD9778A ACLR, Single Carrier W-CDMA,

4× Interpolation, f_DATA= 122.88 MSPS, Amplitude = −3 dBFS

REF –25.39dBm

*ATTEN 4dB

*AVG

log

10dB

100

90

80

70

60

4× 150MSPS

4× 200MSPS

4× 100MSPS

PAVG

10

W1 S2

CENTER 143.88MHz

*RES BW 30kHz

SPAN 50MHz

SWEEP 162.2ms (601 pts)

50

0

VBW 300kHz

40

80

120 160 200 240 280 320 360 400

f_OUT(MHz)

LOWER

UPPER

RMS RESULTS FREQ OFFSET REF BW

CARRIER POWER 5.000MHz

dBc dBm

3.884MHz –76.49 –89.23 –76.89 –89.63

3.840MHz –80.13 –92.87 –80.02 –92.76

3.840MHz –80.90 –93.64 –79.53 –92.27

–12.74dBm/

3.84000MHz

10.00MHz

15.00MHz

Figure 41. AD9778A ACLR,

_DATA= 122.88 MSPS, 4× Interpolation, f_DAC/4 Modulation

Figure 38. AD9778A IMD vs. f_OUT

,

f

4× Interpolation

Rev. B | Page 21 of 56

AD9776A/AD9778A/AD9779A

–150

0.20

0.15

0.10

0.05

0

–154

f_DAC= 200MSPS

–158

f_DAC= 400MSPS

–162

–166

–170

–0.05

–0.10

–0.15

–0.20

f_DAC= 800MSPS

0

20

40

60

80

100

0

512

1024 1536

2048

2560

3072

3584

4096

CODE

f_OUT(MHz)

Figure 42. AD9778A Noise Spectral Density vs. f_OUT

for Eight-Tone Input with 500 kHz Spacing, f_DATA= 200 MSPS

Figure 45. AD9776A Typical DNL

–150

100

95

90

85

80

75

70

65

60

55

50

–154

–158

–162

–166

–170

f_DAC= 200MSPS

f_DAC= 400MSPS

4× 100MSPS

4× 150MSPS

4× 200MSPS

f_DAC= 800MSPS

0

20

40

60

80

100

0

40

80

120 160 200 240 280 320 360 400

f_OUT(MHz)

Figure 43. AD9778A Noise Spectral Density vs. f_OUT

with Single-Tone Input at −6 dBFS, f_DATA= 200 MSPS

Figure 46. AD9776A IMD vs. f_OUT,

4× Interpolation

100

90

80

70

60

50

0.4

0.3

0.2

f_DATA= 160MSPS

0.1

0

f_DATA= 250MSPS

f_DATA= 200MSPS

–0.1

–0.2

–0.3

–0.4

0

20

40

60

80

100

0

512

1024

1536

2048 2560

CODE

3072

3584 4096

f_OUT(MHz)

Figure 47. AD9776A In-Band SFDR vs. f_OUT

,

Figure 44. AD9776A Typical INL

2× Interpolation

Rev. B | Page 22 of 56

AD9776A/AD9778A/AD9779A

–55

–60

–65

–70

–75

–80

–85

–90

–150

–154

–158

–162

–166

–170

f_DAC= 200MSPS

f_DAC= 400MSPS

FIRST ADJACENT CHANNEL

THIRD ADJACENT

CHANNEL

f_DAC= 800MSPS

SECOND ADJACENT

CHANNEL

0

25

50

75

100 125 150 175 200 225 250

(MHz)

0

10

20

30

40

50

60

70

80

90

100

F

f_OUT(MHz)

OUT

Figure 48. AD9776A ACLR vs. f_OUT

,

Figure 50. AD9776A Noise Spectral Density vs. f_OUT

,

f_DATA= 122.88 MSPS, 4× Interpolation, f_DAC/4 Modulation

Eight-Tone Input with 500 kHz Spacing, f_DATA= 200 MSPS

REF –25.29dBm

*ATTEN 4dB

*AVG

log

–150

10dB

f_DAC= 200MSPS

f_DAC= 400MSPS

–154

–158

–162

–166

–170

f_DAC= 800MSPS

PAVG

10

W1 S2

CENTER 143.88MHz

*RES BW 30kHz

SPAN 50MHz

SWEEP 162.2ms (601 pts)

VBW 300kHz

0

10

20

30

40

50

60

70

80

90

100

LOWER

UPPER

f_OUT(MHz)

RMS RESULTS FREQ OFFSET REF BW

dBc dBm

CARRIER POWER 5.000MHz

3.884MHz –75.00 –87.67 –75.30 –87.97

3.840MHz –78.05 –90.73 –77.99 –90.66

3.840MHz –77.73 –90.41 –77.50 –90.17

–12.67dBm/

3.84000MHz

10.00MHz

15.00MHz

Figure 51. AD9776A Noise Spectral Density vs. f_OUT

Single-Tone Input at −6 dBFS, f_DATA= 200 MSPS

,

Figure 49. AD9776A Single Carrier W-CDMA,

4× Interpolation, f_DATA= 122.88 MSPS, Amplitude = −3 dBFS

Rev. B | Page 23 of 56

AD9776A/AD9778A/AD9779A

TERMINOLOGY

Integral Nonlinearity (INL)

In-Band Spurious-Free Dynamic Range (SFDR)

INL is defined as the maximum deviation of the actual analog

output from the ideal output, determined by a straight line

drawn from zero scale to full scale.

In-band SFDR is the difference, in decibels, between the peak

amplitude of the output signal and the peak spurious signal

between dc and the frequency equal to half the input data rate.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input code.

Out-of-Band Spurious-Free Dynamic Range (SFDR)

Out-of-band SFDR is the difference, in decibels, between the

peak amplitude of the output signal and the peak spurious signal

within the band that starts at the frequency of the input data

rate and ends at the Nyquist frequency of the DAC output sample

rate. Normally, energy in this band is rejected by the interpolation

filters. This specification, therefore, defines how well the inter-

polation filters work and the effect of other parasitic coupling

paths to the DAC output.

Monotonicity

A DAC is monotonic if the output either increases or remains

constant as the digital input increases.

Offset Error

The deviation of the output current at Code 0 from the ideal

of zero is called offset error. For I_OUTA, 0 mA output is expected

when the inputs are all 0s. For I_OUTB, 0 mA output is expected

when all inputs are set to 1s.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic com-

ponents to the rms value of the measured fundamental. It is

expressed as a percentage or in decibels.

Gain Error

Gain error is the difference between the actual and the ideal

output spans. The actual span is determined by the difference

between the full-scale output and the bottom-scale output.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal

to the rms sum of all other spectral components below the

Nyquist frequency, excluding the first six harmonics and dc.

The value for SNR is expressed in decibels.

Output Compliance Range

Output compliance range is the range of allowable voltage at

the output of a current-output DAC. Operation beyond the

maximum compliance limits may cause either output stage

saturation or breakdown, resulting in nonlinear performance.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of

f

_DATA(interpolation rate), a digital filter can be constructed that

Temperature Drift

Temperature drift is specified as the maximum change from

the ambient (25°C) value to the value at either T_MINor T_MAX

For offset and gain drift, the drift is reported in ppm of full-

scale range (FSR) per degree Celsius. For reference drift, the

drift is reported in ppm per degree Celsius.

has a sharp transition band near f_DATA/2. Images that typically

appear around f_DAC(output data rate) can be greatly suppressed.

.

Adjacent Channel Leakage Ratio (ACLR)

ACLR is the ratio in dBc of the measured power within a

channel relative to its adjacent channel.

Complex Image Rejection

Power Supply Rejection (PSR)

In a traditional two-part upconversion, two images are created

around the second IF frequency. These images have the effect of

wasting transmitter power and system bandwidth. By placing

the real part of a second complex modulator in series with the

first complex modulator, either the upper or lower frequency

image near the second IF can be rejected.

PSR is the maximum change in the full-scale output as the

supplies are varied from minimum to maximum specified

voltages.

Settling Time

Settling time is the time required for the output to reach and

remain within a specified error band around its final value,

measured from the start of the output transition.

Rev. B | Page 24 of 56

AD9776A/AD9778A/AD9779A

THEORY OF OPERATION

The AD9776A/AD9778A/AD9779A have many features that

make them highly suited for wired and wireless communications

systems. The dual digital signal path and dual DAC structure

allow an easy interface with common quadrature modulators

when designing single sideband transmitters. The speed and

performance of the parts allow wider bandwidths and more

carriers to be synthesized than in previously available DACs.

The digital engine uses an innovative filter architecture that

combines the interpolation with a digital quadrature modulator.

This allows the parts to perform digital quadrature frequency

upconversions. The on-chip synchronization circuitry enables

multiple devices to be synchronized to each other, or to a

system clock.

This means that the AD9776A/AD9778A/AD9779A PLL

remains in lock in a given range over a wider temperature range

than the AD9776/AD9778/AD9779. See Table 23 for PLL lock

ranges for the AD9776A/AD9778A/AD9779A.

PLL Optimal Settings

The optimal settings for the AD9776/AD9778/AD9779 differ

from the AD9776A/AD9778A/AD9779A. Refer to the PLL Bias

Settings section for complete details.

Input Data Delay Line, Manual and Automatic

Correction Modes

The AD9776A/AD9778A/AD9779A can be programmed to not

only sense when the timing margin on the input data falls below

a preset threshold but to also take action. The device can be

programmed to either set the IRQ (pin and register) or

automatically reoptimize the timing input data timing.

DIFFERENCES BETWEEN AD9776/AD9778/

AD9779 AND AD9776A/AD9778A/AD9779A

REFCLK Maximum Frequency vs. Supply

Input Data Timing

With some restrictions on the DVDD18 and CVDD18 power

supplies, the AD9776A/AD9778A/AD9779A support a maxi-

mum sample rate of 1100 MHz. Table 2 lists the valid operating

frequencies vs. power supply voltage.

See Table 28 for timing specifications vs. temperature. The

input data timing specifications (setup and hold) are different

for the AD9776A/AD9778A/AD9779A than they are for the

AD9776/AD9778/AD9779.

REFCLK Amplitude

DATACLK Delay Range

With a differential sinusoidal clock applied to REFCLK, the

PLL on the AD9776/AD9778/AD9779 does not achieve optimal

noise performance unless the REFCLK differential amplitude is

increased to 2 V p-p. Note that if an LVPECL driver is used on the

AD9776/AD9778/AD9779, the PLL exhibits optimal performance

if the REFCLK amplitude is well within LVPECL specifications

(<1.6 V p-p differential). The design of the PLL on the AD9779A

has been improved so that even with a sinusoidal clock, the PLL

still achieves optimal amplitude if the swing is 1.6 V p-p.

In the AD9776/AD9778/AD9779, the input data delay was

controlled by Register 0x04, Bits[7:4]. At 25°C, the delay was

stepped by approximately 180 ps/increment. In the AD9776A/

AD9778A/AD9779A, an extra bit has been added, which effectively

doubles the delay range. This bit is now located at Register 0x01,

Bit 1. The increment/step on the AD9776A/AD9778A/AD9779A

remains at ~180 ps.

Version Register

PLL Lock Ranges

The version register (Register 0x1F) of the AD9776A/AD9778A/

AD9779A reads a value of 0x07. The version register of the

AD9776/AD9778/AD9779 reads a value of 0x03.

The individual lock ranges for the AD9776A/AD9778A/AD9779A

PLL are wider than those for the AD9776/AD9778/AD9779.

Table 10. Register Value Differences Between AD9776/AD9778/AD9779 and AD9776A/AD9778A/AD9779A

PLL Loop Bandwidth, PLL Bias, VCO Control Voltage,

Register 0x0A, Bits[4:0] Register 0x09, Bits[2:0] Register 0x0A, Bits[7:5] Register 0x08, Bits[1:0]

PLL VCO Drive,

Part No.

AD9776/AD9778/AD9779

AD9776A/AD9778A/AD9779A 01111

11111

111

011

010

011

00

11

Rev. B | Page 25 of 56

AD9776A/AD9778A/AD9779A

3-WIRE INTERFACE

The 3-wire port is a flexible, synchronous serial communications

port allowing easy interface to many industry-standard micro-

controllers and microprocessors. The port is compatible with

most synchronous transfer formats, including both the

Motorola SPI and Intel® SSR protocols.

A logic high on the CSB pin followed by a logic low resets the

3-wire interface port timing to the initial state of the instruction

cycle. From this state, the next eight rising SCLK edges represent

the instruction bits of the current I/O operation, regardless of

the state of the internal registers or the other signal levels at the

inputs to the 3-wire interface port. If the 3-wire interface port is

in an instruction cycle or a data transfer cycle, none of the present

data is written.

The interface allows read and write access to all registers

that configure the AD9776A/AD9778A/AD9779A. Single-

or multiple-byte transfers are supported, as well as MSB-first

or LSB-first transfer formats. Serial data input/output can be

accomplished through a single bidirectional pin (SDIO) or

through two unidirectional pins (SDIO/SDO).

The remaining SCLK edges are for Phase 2 of the communica-

tion cycle. Phase 2 is the actual data transfer between the device

and the system controller. Phase 2 of the communication cycle

is a transfer of one, two, three, or four data bytes, as determined

by the instruction byte. Using one multibyte transfer is preferred.

Single-byte data transfers are useful in reducing CPU overhead

when register access requires only one byte. Registers change

immediately upon writing to the last bit of each transfer byte.

The serial port configuration is controlled by Register 0x00,

Bits[7:6]. It is important to note that any change made to the

serial port configuration occurs immediately upon writing to

the last bit of this byte. Therefore, it is possible with a multibyte

transfer to write to this register and change the configuration in

the middle of a communication cycle. Care must be taken to

compensate for the new configuration within the remaining

bytes of the current communication cycle.

INSTRUCTION BYTE

See Table 11 for information contained in the instruction byte.

Table 11. 3-Wire Interface Instruction Byte

MSB

Use of a single-byte transfer when changing the serial port

configuration is recommended to prevent unexpected device

behavior.

LSB

I0

I7

I6

I5

I4

I3

I2

I1

R/W

N1

N0

A4

A3

A2

A1

A0

As described in this section, all serial port data is transferred

to/from the device in synchronization with the SCLK pin. If

synchronization is lost, the device has the ability to asynchro-

nously terminate an I/O operation, putting the serial port

controller into a known state and, thereby, regaining synchro-

nization.

W

R/ , Bit 7 of the instruction byte, determines whether a read

or a write data transfer occurs after the instruction byte write.

Logic 1 indicates a read operation. Logic 0 indicates a write

operation.

N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine

the number of bytes to be transferred during the data transfer

cycle. The translation for the number of bytes to be transferred

is listed in Table 12.

66

SDO

67

SDIO

SPI

PORT

68

69

SCLK

CSB

A4, A3, A2, A1, and A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0,

respectively, of the instruction byte—determine the register that

is accessed during the data transfer portion of the communication

cycle. For multibyte transfers, this address is the starting byte

address. The remaining register addresses are generated by the

device, based on the LSB-first bit (Register 0x00, Bit 6).

Figure 52. 3-Wire Interface Port

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases of a communication cycle with the

AD9776A/AD9778A/AD9779A. Phase 1 is the instruction cycle

(the writing of an instruction byte into the device), coinciding with

the first eight SCLK rising edges. The instruction byte provides

the serial port controller with information regarding the data

transfer cycle, which is Phase 2 of the communication cycle. The

Phase 1 instruction byte defines whether the upcoming data

transfer is a read or write, the number of bytes in the data transfer,

and the starting register address for the first byte of the data

transfer. The first eight SCLK rising edges of each communication

cycle are used to write the instruction byte into the device.

Table 12. Byte Transfer Count

N1

N0

Description

0

1

0

1

0

1

Transfer one byte

Transfer two bytes

Transfer three bytes

Transfer four bytes

Rev. B | Page 26 of 56

AD9776A/AD9778A/AD9779A

The serial port controller data address decrements from the data

address written toward 0x00 for multibyte I/O operations if the

MSB-first format is active. The serial port controller address

increments from the data address written toward 0x1F for

multibyte I/O operations if the LSB-first format is active.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

Serial Clock (SCLK)

The serial clock pin synchronizes data to and from the device

and controls the internal state machines. The maximum frequency

of SCLK is 40 MHz. All data input is registered on the rising edge

of SCLK. All data is driven out on the falling edge of SCLK.

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

Chip Select (CSB)

Active low input starts and gates a communication cycle. It

allows more than one device to be used on the same serial

communication lines. The SDO and SDIO pins go to a high

impedance state when this input is high. Chip select should

stay low during the entire communication cycle.

R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5

N

D3 D2 D1 D0

0 0 0

N

0

D7 D6 D5

N

D3 D2 D1 D0

0 0 0

N

Figure 53. Serial Register Interface Timing, MSB First

Serial Data I/O (SDIO)

Data is always written into the device on this pin. However, this

pin can be used as a bidirectional data line. The configuration

of this pin is controlled by Register 0x00, Bit 7. The default is

Logic 0, configuring the SDIO pin as unidirectional.

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

Serial Data Out (SDO)

A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2

D4 D5 D6 D7

N N N

0

N

Data is read from this pin for protocols that use separate lines

for transmitting and receiving data. In the case where the device

operates in a single bidirectional I/O mode, this pin does not

output data and is set to a high impedance state.

D0 D1 D2

D4 D5 D6 D7

N N N

0

Figure 54. Serial Register Interface Timing, LSB First

MSB/LSB TRANSFERS

t_DS

The serial port can support both MSB-first and LSB-first data

formats. This functionality is controlled by the LSB-/MSB-first

register bit (Register 0x00, Bit 6). The default is MSB-first format

(LSB/MSB first = 0).

t_SCLK

CSB

t_PWH

t_PWL

SCLK

When MSB-first format is selected (LSB/MSB first = 0), the

instruction and data bit must be written from MSB to LSB.

Multibyte data transfers in MSB-first format start with an

instruction byte that includes the register address of the most

significant data byte. Subsequent data bytes should follow from

high address to low address. In MSB-first mode, the serial port

internal byte address generator decrements for each data byte of

the multibyte communication cycle.

t_DS

t_DH

INSTRUCTION BIT 7

INSTRUCTION BIT 6

SDIO

Figure 55. Timing Diagram for 3-Wire Interface Register Write

CSB

SCLK

When LSB/MSB first = 1 (LSB first) the instruction and data

bit must be written from LSB to MSB. Multibyte data transfers

in LSB-first format start with an instruction byte that includes

the register address of the least significant data byte, followed by

multiple data bytes. The serial port internal byte address genera-

tor increments for each byte of the multibyte communication cycle.

t_DV

SDIO

SDO

DATA BIT n

DATA BIT n – 1

Figure 56. Timing Diagram for 3-Wire Interface Register Read

Rev. B | Page 27 of 56

AD9776A/AD9778A/AD9779A

3-WIRE INTERFACE REGISTER MAP

Note that all unused register bits should be kept at the device default values.

Table 13.

Address

Register

Name

Hex Decimal Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Def.

Comm

0x00 00

SDIO

bidirectional first

LSB/MSB

Software

reset

Power-

down

mode

Auto

PLL lock

indicator

(read

0x00

power-

down

enable

only)

Digital

Control

0x01 01

0x02 02

Interpolation Factor[1:0]

Filter Modulation Mode[3:0]

DATACLK

Delay[4]

Zero

stuffing

enable

0x00

Data format

Single port

Real mode

DATACLK Inverse

DATACLK

invert

TxEnable

invert

Q first

delay

sinc

enable

Sync

Control

0x03 03

0x04 04

0x05 05

DATACLK

delay mode

Reserved

(set to 1)

DATACLK Divide[1:0]

Data Timing Margin[3:0]

SYNC_O Divide[2:0]

0x00

DATACLK Delay[3:0]

SYNC_O Delay[3:0]

SYNC_I Delay[3:0]

SYNC_O

Delay[4]

SYNC_I Ratio[2:0]

SYNC_I

Delay[4]

0x06 06

0x07 07

SYNC_I Timing Margin[3:0]

Clock State[4:0]

0x00

SYNC_I

enable

SYNC_O

enable

SYNC_O

triggering

edge

PLL

Control

0x08 08

0x09 09

PLL Band Select[5:0]

PLL VCO Drive[1:0]

PLL Bias[2:0]

0xE7

0x52

PLL enable

PLL VCO Divide Ratio[1:0]

PLL Loop Divide

Ratio[1:0]

Misc.

0x0A 10

VCO Control Voltage[2:0] (read only)

PLL Loop Bandwidth[4:0]

0x1F

Control

I DAC

Control

0x0B 11

0x0C 12

I DAC Gain Adjustment[7:0]

Auxiliary DAC1 Data[7:0]

0xF9

0x01

I DAC sleep

I DAC

power-

down

I DAC Gain

Adjustment[9:8]

Aux

DAC1

Control

0x0D 13

0x0E 14

0x00

Auxiliary

DAC1 sign

Auxiliary

DAC1

Auxiliary

DAC1

Auxiliary DAC1

Data[9:8]

current

direction

power-

down

Q DAC

Control

0x0F 15

0x10 16

Q DAC Gain Adjustment[7:0]

0xF9

0x01

Q DAC sleep Q DAC

power-

Q DAC Gain

Adjustment[9:8]

down

Aux

DAC2

Control

0x11 17

0x12 18

Auxiliary DAC2 Data[7:0]

0x00

Auxiliary

DAC2 sign

Auxiliary

DAC2

Auxiliary

DAC2

Auxiliary DAC2

Data[9:8]

current

direction

power-

down

0x13 19 to 24

Reserved

to

0x18

Interrupt

Version

0x19 25

Data timing

error IRQ

Sync timing

error IRQ

Data

timing

error type error

IRQ

Data

timing

Sync

Internal

sync

loopback

0x00

0x07

timing

error IRQ

enable

0x1F 31

Version[7:0]

Rev. B | Page 28 of 56

AD9776A/AD9778A/AD9779A

Table 14. 3-Wire Interface Register Description

Register

Address Bits

Register Name

Parameter

Function

Default

Comm

0x00

7

6

5

4

SDIO bidirectional

0: use SDIO pin as input data only.

0

1: use SDIO as both input and output data.

0: first bit of serial data is MSB of data byte.

1: first bit of serial data is LSB of data byte.

Bit must be written with a 1 and then 0 to soft reset

the 3-wire interface register map.

LSB/MSB first

Software reset

Power-down mode

0: all circuitry is active.

1: disable all digital and analog circuitry, only

3-wire interface port is active.

0x00

3

1

Auto power-down enable

Controls auto power-down mode. See the Power-

Down and Sleep Modes section.

0: PLL is not locked.

1: PLL is locked.

0

PLL lock indicator

(read only)

Digital Control

0x01

7:6

Interpolation Factor[1:0]

00: 1× interpolation.

01: 2× interpolation.

10: 4× interpolation.

11: 8× interpolation.

00

0x01

5:2

1

Filter Modulation Mode[3:0]

DATACLK Delay[4]

See Table 19 for filter modes.

0000

0

Sets MSB of delay of REFCLK input to DATACLK

output.

0x01

0x02

0

7

6

5

Zero stuffing enable

Data format

0: zero stuffing off.

1: zero stuffing on.

0

0: twos compliment.

1: unsigned binary.

Single port

0: both P1D and P2D data ports enabled.

1: data for both DACs received on P1D data port.

Real mode

0: enable Q path for signal processing.

1: disable Q path data (internal Q channel clocks

disabled, I and Q modulators disabled).

0x02

4

DATACLK delay enable

Enables the DATACLK delay feature. More details

on this feature are shown in the Optimizing the

Data Input Timing section.

0x02

3

2

Inverse sinc enable

DATACLK invert

0: inverse sinc filter disabled.

1: inverse sinc filter enabled.

0

0: output DATACLK same phase as internal data

sampling clock, DCLK_SMP signal.

1: output DATACLK opposite phase as internal data

sampling clock, DCLK_SMP signal.

0x02

1

0

TxEnable invert

Q first

Inverts the polarity of Pin 39, the TXENABLE input

pin (also functions as IQSELECT).

0

0: in interleaved mode, the I data precedes the

Q data on the input port.

1: in interleaved mode, the Q data precedes the

I data on the input port.

Rev. B | Page 29 of 56

AD9776A/AD9778A/AD9779A

Register

Register Name

Address Bits

Parameter

Function

Default

Sync Control

0x03

7

DATACLK delay mode

0: manual data timing error detect mode.

1: automatic data timing error detect mode.

Should always be set to 1.

DATACLK output divider value.

00: divide by 1.

0

0x03

6

5:4

Reserved

DATACLK Divide[1:0]

0

00

01: divide by 2.

10: divide by 4.

11: divide by 1.

0x03

0x04

3:0

7:4

3:1

Data Timing Margin[3:0]

DATACLK Delay[3:0]

SYNC_O Divide[2:0]

Sets the timing margin required to prevent the

data timing error IRQ bit from being asserted.

0000

Sets delay of REFCLK input to DATACLK output (see 0000

Table 29 for details).

The frequency of the SYNC_O signal is equal to

f_DAC/N, where N is set as follows:

000: N = 32.

000

001: N = 16.

010: N = 8.

011: N = 4.

100: N = 2.

101: N = 1.

110: N = undefined.

111: N = undefined.

0x04

0x05

0

7:4

SYNC_O Delay[4]

SYNC_O Delay[3:0]

The SYNC_O Delay[4:0] value programs the value

of the delay line of the SYNC_O signal. The delay of

SYNC_O is relative to REFCLK. The delay line

resolution is 80 ps per step.

0

0000

00000: nominal delay.

00001: adds 80 ps delay to SYNC_O.

00010: adds 160 ps delay to SYNC_O.

…

11111: Adds 2480 ps delay to SYNC_O.

0x05

3:1

SYNC_I Ratio[2:0]

This value controls the number of SYNC_I input

pulses required to generate a synchronization

pulse (see Table 30 for details).

000

0x05

0x06

0

7:4

SYNC_I Delay[4]

SYNC_I Delay[3:0]

The SYNC_I Delay[4:0] value programs the value of

the delay line of the SYNC_I signal. The delay line

resolution is 80 ps per step.

0

0000

00000: nominal delay.

00001: adds 80 ps delay to SYNC_I.

00010: adds 160 ps delay to SYNC_I.

…

11111: adds 2480 ps delay to SYNC_I.

0x06

0x07

3:0

7

6

SYNC_I Timing Margin[3:0]

SYNC_I enable

SYNC_O enable

0000

1: enables the SYNC_I input.

1: enables the SYNC_O output.

0: SYNC_O changes on REFCLK falling edge.

1: SYNC_O changes on REFCLK rising edge.

0

5

SYNC_O triggering edge

0x07

4:0

Clock State[4:0]

This value determines the state of the internal

clock generation state machine upon

synchronization.

0

Rev. B | Page 30 of 56

AD9776A/AD9778A/AD9779A

Register

Register Name

Address Bits

Parameter

Function

Default

PLL Control

0x08

7:2

PLL Band Select[5:0]

111001

This sets the operating frequency range of the

VCO. For details (see Table 23).

0x08

0x09

1:0

7

PLL VCO Drive[1:0]

PLL enable

Controls the signal strength of the VCO output. Set 11

to 11 for optimal performance.

0: PLL off, DAC sample clock is sourced directly by

the REFCLK input.

0

1: PLL on, DAC clock synthesized internally from

REFCLK input via PLL clock multiplier.

0x09

6:5

PLL VCO Divide Ratio[1:0]

PLL Loop Divide Ratio[1:0]

PLL Bias[2:0]

Sets the value of the VCO output divider, which

determines the ratio of the VCO output frequency

10

to the DAC sample clock frequency, f_VCO/f_DACCLK

.

00: f_VCO/f_DACCLK= 1.

01: f_VCO/f_DACCLK= 2.

10: f_VCO/f_DACCLK= 4.

11: f_VCO/f_DACCLK= 8.

Sets the value of the DACCLK divider, which

determines the ratio of the DAC sample clock

0x09

4:3

10

frequency to the REFCLK frequency, f_DACCLK/f_REFCLK

.

00: f_DACCLK/f_REFCLK= 2.

01: f_DACCLK/f_REFCLK= 4.

10: f_DACCLK/f_REFCLK= 8.

11: f_DACCLK/f_REFCLK= 16.

Controls VCO bias current. Set to 011 for optimal

performance.

0x09

0x0A

2:0

7:5

010

000

Misc. Control

I DAC Control

VCO Control Voltage[2:0]

(read only)

000 to 111, proportional to voltage at VCO control

voltage input, readback only. A value of 011

indicates the VCO centered in its frequency range.

0x0A

4:0

PLL Loop Bandwidth[4:0]

Controls the bandwidth of the PLL filter. Increasing 11111

the value lowers the loop bandwidth. Set to 01111

for optimal performance.

0x0C

0x0B

1:0

7:0

I DAC Gain Adjustment[9:8]

I DAC Gain Adjustment[7:0]

The I DAC Gain Adjustment[9:0] value is the I DAC

10-bit gain setting word. Bit 9 is the MSB and Bit 0

is the LSB.

01

11111001

0x0C

7

6

I DAC sleep

0: I DAC on.

1: I DAC off, but reference remains powered.

0: I DAC on.

1: I DAC off.

0

I DAC power-down

Aux DAC1 Control

0x0E

0x0D

1:0

7:0

Auxiliary DAC1 Data[9:8]

Auxiliary DAC1 Data[7:0]

The auxiliary DAC 1 Data [9:0] value is the Aux DAC1

10-bit output current control word. Magnitude of

the auxiliary DAC current increases with increasing

value. Bit 9 is the MSB and Bit 0 is the LSB.

00

00000000

0x0E

7

6

5

Auxiliary DAC1 sign

0: AUX1_P active.

1: AUX1_N active.

0

Auxiliary DAC1 current

direction

0: source.

1: sink.

Auxiliary DAC1 power-down

0: auxiliary DAC1 on.

1: auxiliary DAC1 off.

Q DAC Control

0x10

0x0F

1:0

7:0

Q DAC Gain Adjustment[9:8]

Q DAC Gain Adjustment[7:0]

The Q DAC Gain Adjustment[9:0] value is the Q DAC

10-bit gain setting word. Bit 9 is the MSB and Bit 0

is the LSB.

01

11111001

0x10

7

6

Q DAC sleep

0: Q DAC on.

1: Q DAC off.

0

Q DAC power-down

0: Q DAC on.

1: Q DAC off.

Rev. B | Page 31 of 56

AD9776A/AD9778A/AD9779A

Register

Register Name

Address Bits

Parameter

Function

Default

AUX DAC2 Control

0x12

0x11

1:0

7:0

Auxiliary DAC2 Data[9:8]

Auxiliary DAC2 Data[7:0]

Auxiliary DAC2 Data[9:0] is the 10-bit output

current control word. Magnitude of the auxiliary

DAC current increases with increasing value. Bit 9 is

the MSB and Bit 0 is the LSB.

00

00000000

0x12

7

6

5

Auxiliary DAC2 sign

0: AUX2_P active.

1: AUX2_N active.

0: source.

1: sink.

0: auxiliary DAC2 on.

1: auxiliary DAC2 off.

0

Auxiliary DAC2 current

direction

Auxiliary DAC2 power-down

0x13 to

0x18

Reserved

Interrupt

0x19

7

6

4

Data timing error IRQ

Read only. Active high indicates a timing violation

occurred on the input data port. The IRQ is latched.

This bit is cleared when the Interrupt register is read.

Read only. Active high indicates a timing violation

occurred on the SYNC_I input. The IRQ is latched.

This bit is cleared when the Interrupt register is read.

0

Sync timing error IRQ

Data timing error type

Read only. Indicates the timing error type.

0: hold time violation.

1: setup time violation.

Meaningful when data timing error IRQ is active.

0: data timing error IRQ is masked.

1: data timing error IRQ is enabled.

0: sync timing error IRQ is masked.

1: sync timing error IRQ is enabled.

0x19

0x1F

3

Data timing error IRQ enable

Sync timing error IRQ enable

Internal sync loopback

Version[7:0]

0

2

0

The received SYNC_O signal is looped back to the

SYNC_I signal.

0

Version

7:0

Indicates device hardware revision number.

00000111

Rev. B | Page 32 of 56

AD9776A/AD9778A/AD9779A

INTERPOLATION FILTER ARCHITECTURE

The AD9776A/AD9778A/AD9779A can provide up to 8× inter-

polation, or the interpolation filters can be entirely disabled. It

is important to note that the input signal should be backed off

by approximately 0.01 dB from full scale to avoid overflowing

the interpolation filters. The coefficients of the low-pass filters

and the inverse sinc filter are given in Table 15, Table 16, Table 17,

and Table 18. Spectral plots for the filter responses are shown in

Figure 57, Figure 58, and Figure 59.

Table 16. Low-Pass Filter 2

Lower Coefficient

Upper Coefficient

Integer Value

H(1)

H(2)

H(3)

H(4)

H(5)

H(6)

H(7)

H(8)

H(9)

H(10)

H(11)

H(12)

H(23)

H(22)

H(21)

H(20)

H(19)

H(18)

H(17)

H(16)

−2

0

+17

0

−75

0

+238

0

−660

0

+2530

+4096

Table 15. Low-Pass Filter 1

Lower Coefficient

Upper Coefficient

H(55)

H(54)

H(53)

H(52)

H(51)

H(50)

H(49)

H(48)

H(47)

H(46)

H(45)

H(44)

H(43)

H(42)

H(41)

H(40)

H(39)

H(38)

H(37)

H(36)

H(35)

H(34)

H(33)

H(32)

H(31)

H(30)

H(29)

Integer Value

H(15)

H(14)

H(13)

H(1)

H(2)

H(3)

H(4)

H(5)

H(6)

H(7)

H(8)

−4

0

+13

0

−34

0

+72

0

−138

0

+245

0

−408

0

+650

0

−1003

0

+1521

0

Table 17. Low-Pass Filter 3

Lower Coefficient

Upper Coefficient

Integer Value

H(1)

H(2)

H(3)

H(4)

H(5)

H(6)

H(7)

H(8)

H(15)

H(14)

H(13)

H(12)

H(11)

H(10)

H(9)

−39

0

+273

0

−1102

0

+4964

+8192

H(9)

H(10)

H(11)

H(12)

H(13)

H(14)

H(15)

H(16)

H(17)

H(18)

H(19)

H(20)

H(21)

H(22)

H(23)

H(24)

H(25)

H(26)

H(27)

H(28)

Table 18. Inverse Sinc Filter

Lower Coefficient

Upper Coefficient

Integer Value

H(1)

H(2)

H(3)

H(4)

H(5)

H(9)

H(8)

H(7)

H(6)

+2

−4

+10

−35

+401

−2315

0

+3671

0

−6642

0

+20,755

+32,768

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–4

–3

–2

–1

0

1

2

3

4

f_OUT(× Input Data Rate)

Figure 57. 2× Interpolation, Low-Pass Response to 4× Input Data Rate

(Dotted Lines Indicate 1 dB Roll-Off)

Rev. B | Page 33 of 56

AD9776A/AD9778A/AD9779A

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–4

–3

–2

–1

0

1

2

3

4

–4

–3

–2

–1

0

1

2

3

4

f_OUT(× Input Data Rate)

Figure 58. 4× Interpolation, Low-Pass Response to 4× Input Data Rate

(Dotted Lines Indicate 1 dB Roll-Off)

Figure 61. Interpolation/Modulation Combination of 4f_DAC/8 Filter

10

0

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–4

–3

–2

–1

0

1

2

3

4

–4

–3

–2

–1

0

1

2

3

4

f_OUT(× Input Data Rate)

Figure 62. Interpolation/Modulation Combination of −3f_DAC/8 Filter

Figure 59. 8× Interpolation, Low-Pass Response to 4× Input Data Rate

(Dotted Lines Indicate 1 dB Roll-Off)

10

0

With the interpolation filter and modulator combined, the

incoming signal can be placed anywhere within the Nyquist

region of the DAC output sample rate. When the input signal

is complex, this architecture allows modulation of the input

signal to positive or negative Nyquist regions (see Table 19).

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

The Nyquist regions of up to 4× the input data rate can be seen

in Figure 60.

–8 –7 –6 –5 –4 –3 –2 –1

0

1

2

3

4

5

6

7

8

–4

–3×

–2×

–1×

DC

1×

2×

3×

4×

Figure 60. Nyquist Zones

–4

–3

–2

–1

0

1

2

3

4

Figure 57, Figure 58, and Figure 59 show the low-pass response

of the digital filters with no modulation. By turning on the modu-

lation feature, the response of the digital filters can be tuned to

anywhere within the DAC bandwidth. As an example, Figure 61

to Figure 67 show the nonshifted mode filter responses for 8×

interpolation (refer to Table 19 for shifted/nonshifted mode

filter responses).

f_OUT(× Input Data Rate)

Figure 63. Interpolation/Modulation Combination of −2f_DAC/8 Filter

Rev. B | Page 34 of 56

AD9776A/AD9778A/AD9779A

10

0

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–4

–3

–2

–1

0

1

2

3

4

–4

–3

–2

–1

0

1

2

3

4

f_OUT(× Input Data Rate)

Figure 64. Interpolation/Modulation Combination of −f_DAC/8 Filter

Figure 67. Interpolation/Modulation Combination of 3f_DAC/8 Filter

Shifted mode filter responses allow the pass band to be centered

around 0.5 f_DATA, 1.5 f_DATA, 2.5 f_DATA, and 3.5 f_DATA. Switching to

the shifted mode response does not affect the center frequency

of the signal. Instead, the pass band of the filter is simply shifted.

For example, use the response shown in Figure 67 and assume

the signal in-band is a complex signal over the bandwidth 3.2 f_DATA

to 3.3 f_DATA. If the shifted mode filter response is then selected,

the pass band becomes centered at 3.5 f_DATA. However, the signal

remains at the same place in the spectrum. The shifted mode

capability allows the filter pass band to be placed anywhere in

the DAC Nyquist bandwidth.

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

The AD9776A/AD9778A/AD9779A are dual DACs with

internal complex modulators built into the interpolating filter

response. In dual channel mode, the devices expect the real and

imaginary components of a complex signal at Digital Input Port 1

and Digital Input Port 2 (I and Q, respectively). The DAC outputs

then represent the real and imaginary components of the input

signal, modulated by the complex carrier (f_DAC/2, f_DAC/4, or f_DAC/8).

–4

–3

–2

–1

0

1

2

3

4

f_OUT(× Input Data Rate)

Figure 65. Interpolation/Modulation Combination of f_DAC/8 Filter

10

0

With Register 0x02, Bit 6, set, the device accepts interleaved data

on Port 1 in the I, Q, I, Q … sequence. Note that in interleaved

mode, the channel data rate at the beginning of the I and Q data

paths is now half the input data rate because of the interleaving.

The maximum input data rate is still subject to the maximum

specification of the device. This limits the synthesis bandwidth

available at the input in interleaved mode.

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

With Register 0x02, Bit 5 (the real mode bit), set, the Q channel

and the internal I and Q digital modulation are turned off. The

output spectrum at the I DAC then represents the signal at

Digital Input Port 1, interpolated by 1×, 2×, 4×, or 8×.

–4

–3

–2

–1

0

1

2

3

4

The general recommendation is that if the desired signal is

within 0.4 × f_DATA, use the nonshifted filter mode. Outside of

this, the shifted filter mode should be used. In any situation, the

f_OUT(× Input Data Rate)

Figure 66. Interpolation/Modulation Combination of 2f_DAC/8 Filter

total bandwidth of the signal is less than 0.8 × f_DATA

.

Rev. B | Page 35 of 56

AD9776A/AD9778A/AD9779A

Table 19. Interpolation Filter Modes, (Register 0x01, Bits[5:2])

Frequency Normalized to f_DAC

Interpolation

Factor[7:6]

Filter Modulation

Mode[5:2]

Nyquist Zone

Pass Band

Modulation

DC

Low

Center

0

High

Comments

8

4

2

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x00

0x01

0x02

0x03

0

−0.05

+0.05

In 8× interpolation;

BW (min) = 0.0375 × f_DAC

BW (max) = 0.1 × f_DAC

DC shifted

f_DAC/8

f_DAC/8 shifted

f_DAC/4

f_DAC/4 shifted

3f_DAC/8

3f_DAC/8 shifted

f_DAC/2

f_DAC/2 shifted

−3f_DAC/8

−3f_DAC/8 shifted

−f_DAC/4

−f_DAC/4 shifted

−f_DAC/8

−f_DAC/8 shifted

DC

DC shifted

f_DAC/4

f_DAC/4 shifted

f_DAC/2

f_DAC/2 shifted

−f_DAC/4

−f_DAC/4 shifted

DC

+1

+2

+3

+4

+5

+6

+7

8

−7

−6

−5

−4

−3

−2

−1

0

+1

+2

+3

4

−3

−2

−1

0

+0.0125

+0.075

+0.1375

+0.2

+0.2625

+0.325

+0.3875

−0.55

−0.4875

−0.425

−0.3625

−0.3

−0.2375

−0.175

−0.1125

−0.1

+0.025

+0.15

+0.275

−0.6

−0.475

−0.35

−0.225

−0.2

+0.0625

+0.125

+0.1875

+0.25

+0.3125

+0.375

+0.4375

−0.5

−0.4375

−0.375

−0.3125

−0.25

−0.1875

−0.125

−0.0625

0

+0.125

+0.25

+0.375

−0.5

−0.375

−0.25

−0.125

0

+0.1125

+0.175

+0.2375

+0.3

+0.3625

+0.425

+0.4875

−0.45

−0.3875

−0.343

−0.2625

−0.2

−0.1375

−0.075

−0.0125

+0.1

+0.225

+0.35

+0.475

−0.4

−0.275

−0.15

−0.025

+0.2

In 4× interpolation;

BW (min) = 0.075 × f_DAC

BW (max) = 0.2 × f_DAC

In 2× interpolation;

BW (min) = 0.15 × f_DAC

BW (max) = 0.4 × f_DAC

DC shifted

f_DAC/2

f_DAC/2 shifted

+1

2

−1

+0.05

−0.7

−0.45

+0.25

−0.5

−0.25

+0.45

−0.3

−0.05

Rev. B | Page 36 of 56

AD9776A/AD9778A/AD9779A

10

0

INTERPOLATION FILTER BANDWIDTH LIMITS

The AD9776A/AD9778A/AD9779A use a novel interpolation

filter architecture that allows DAC IF frequencies to be gener-

ated anywhere in the spectrum. Figure 68 shows the traditional

choice of DAC IF output bandwidth placement. Note that there

are no possible filter modes in which the carrier can be placed

near 0.5 × f_DATA, 1.5 × f_DATA, 2.5 × f_DATA, and so on.

10

–10

–20

–30

–40

–50

–60

–70

–80

0

–10

–20

–30

–40

–50

–60

–70

–80

–4

–3

–2

–1

f_OUT(× Input Data Rate),

ASSUMING 8× INTERPOLATION

0

1

2

3

4

Figure 70. Shifted Bandwidths Accessible with the Filter Architecture

With this filter architecture, a signal placed anywhere in the

spectrum is possible. However, the signal bandwidth is limited

by the input sample rate of the DAC and the specific placement

of the carrier in the spectrum. The bandwidth restriction resulting

from the combination of filter response and input sample rate is

often referred to as the synthesis bandwidth, because this is the

largest bandwidth that the DAC can synthesize.

–4

–3

–2

–1

0

1

2

3

4

f_OUT(× Input Data Rate),

ASSUMING 8× INTERPOLATION

Figure 68. Traditional Bandwidth Options for TxDAC Output IF

The maximum bandwidth condition exists if the carrier is

placed directly in the center of one of the filter pass bands. In

this case, the total 0.1 dB bandwidth of the interpolation filters

is equal to 0.8 × f_DATA. As Table 19 shows, the synthesis band-

width as a fraction of the DAC output sample rate drops by a

factor of 2 for every doubling of interpolation rate. The mini-

mum bandwidth condition exists, for example, if a carrier is

placed at 0.25 × f_DATA. In this situation, if the nonshifted filter

response is enabled, the high end of the filter response cuts off

at 0.4 × f_DATA, thus limiting the high end of the signal bandwidth.

If the shifted filter response is instead enabled, then the low end

of the filter response cuts off at 0.1 × f_DATA, thus limiting the low

end of the signal bandwidth. The minimum bandwidth speci-

fication that applies for a carrier at 0.25 × f_DATAis therefore 0.3 ×

f_DATA. The minimum bandwidth behavior is repeated over the

spectrum for carriers placed at ( n 0.25) × f_DATA, where n is

any integer.

The filter architecture not only allows the interpolation filter

pass bands to be centered in the middle of the input Nyquist

zones (as explained in this section), but also allows the possi-

bility of a 3 × f_DAC/8 modulation mode when interpolating by 8.

With all of these filter combinations, a carrier of given bandwidth

can be placed anywhere in the spectrum and fall into a possible

pass band of the interpolation filters. The possible bandwidths

accessible with the filter architecture are shown in Figure 69 and

Figure 70. Note that the shifted and nonshifted filter modes are

all accessible by programming the filter mode for a particular

interpolation rate.

10

0

–10

–20

–30

–40

–50

–60

–70

–80

Digital Modulation

The digital quadrature modulation occurs within the interpolation

filter. The modulation shifts the frequency spectrum of the

incoming data by the frequency offset selected. The frequency

offsets available are multiples of the input data rate. The

modulation is equivalent to multiplying the quadrature input

signal by a complex carrier signal, C(t), of the following form:

–4

–3

–2

–1

0

1

2

3

4

f_OUT(× Input Data Rate),

ASSUMING 8× INTERPOLATION

C(t) = cos(ω_ct) + j sin(ω_ct)

Figure 69. Nonshifted Bandwidths Accessible with the Filter Architecture

Rev. B | Page 37 of 56

AD9776A/AD9778A/AD9779A

As shown in Table 20, the mixing functions of most of the

modes result in cross-coupling of samples between the I and Q

channels. The I and Q channels only operate independently

with the f_S/2 mode. This means that real modulation using both

the I and Q DAC outputs can only be done in the f_S/2 mode. All

other modulation modes require complex input data and

produce complex output signals.

Table 21. Inverse Sinc Filter

Lower Coefficient

Upper Coefficient

Integer Value

H(1)

H(2)

H(3)

H(4)

H(5)

H(9)

H(8)

H(7)

H(6)

N/A

+2

−4

+10

−35

+401

Table 20. Modulation Mixing Sequences

Modulation Mixing Sequence

The inverse sinc filter is disabled by default. It can be enabled by

setting the inverse sinc enable bit (Bit 3) in Register 0x02.

f_DAC/2

f_DAC/4

−f_DAC/4

I = I, −I, I, −I, …

0

Q = Q, −Q, Q, −Q, …

I = I, Q, −I, −Q, …

Q = Q, −I, −Q, I, …

I = I, −Q, −I, Q, …

Q = Q, I, −Q, −I, …

–0.5

–1.0

–1.5

–1

SINC RESPONSE

–2.0

–2.5

–3.0

–3.5

f

_DAC/8

I = I, r(I + Q), Q, r(−I + Q), −I, −r(I + Q), −Q, r(I − Q),

…

Q = Q, r(Q − I), −I, −r(Q + I), −Q, r(−Q + I), I, r(Q + I),

…

where r = √2/2

–1

COMBINED SINC AND SINC RESPONSE

–4.0

–4.5

INVERSE SINC FILTER

The inverse sinc filter is implemented as a nine-tap FIR filter. It

is designed to provide less than 0.05 dB pass-band ripple up to

a frequency of 0.4 × f_DATA. To provide the necessary gain at the

upper end of the pass band, the inverse sinc filter has an intrinsic

insertion loss of 3.4 dB. The transfer function is shown in

Figure 71 and the tap coefficients are given in Table 21.

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

f/f

SAMPLE

Figure 71. Transfer Function of Inverse Sinc Filter with the DAC sin(x)/x Output

Rev. B | Page 38 of 56

AD9776A/AD9778A/AD9779A

SOURCING THE DAC SAMPLE CLOCK

The AD9776A/AD9778A/AD9779A offer two modes of sourcing

the DAC sample clock (DACCLK). The first mode employs an

on-chip clock multiplier that accepts a reference clock operating

at the lower input frequency, most commonly the data input

frequency. The on-chip PLL then multiplies the reference clock

up to a higher frequency, which can then be used to generate all

of the internal clocks required by the DAC. The clock multiplier

provides a high quality clock that meets the performance require-

ments of most applications. Using the on-chip clock multiplier

removes the burden of generating and distributing the high

speed DACCLK at the board level. The second mode bypasses

the clock multiplier circuitry and allows DACCLK to be directly

sourced through the REFCLK pins. This mode enables the user

to source a very high quality input clock directly to the DAC

core. Sourcing the DACCLK directly through the REFCLK pins

may be necessary in demanding applications that require the

lowest possible DAC output noise at higher output frequencies.

The clock multiplier circuit operates such that the VCO outputs

a frequency, f_VCO, equal to the REFCLK input signal frequency

multiplied by N1 × N2.

f_VCO= f_REFCLK× (N1 × N2)

The DAC sample clock frequency, f_DACCLK, is equal to

f_DACCLK= f_REFCLK× N2

When the PLL is enabled, the maximum input clock frequency

f

_REFCLKis 250 MHz. The values of N1 and N2 must be chosen to

keep f_VCOin the optimal operating range of 1.0 GHz to 2.0 GHz.

Once the VCO output frequency is known, the correct PLL

band select (Register 0x08, Bits[7:2]) value can be chosen.

PLL Bias Settings

There are three bias settings for the PLL circuitry that should be

programmed to their nominal values. The PLL values shown in

Table 22 are the recommended settings for these parameters.

In either case (that is, using the on-chip clock multiplier or

sourcing the DACCLK directly though the REFCLK pins), it is

necessary that the REFCLK signal have low jitter to maximize

the DAC noise performance.

Table 22. PLL Settings

Address

Register

PLL 3-Wire Interface

Control

Bits Optimal Setting

[4:0] 01111

[1:0] 11

PLL Loop Bandwidth

PLL VCO Drive

PLL Bias

0x0A

0x08

0x09

DIRECT CLOCKING

When the PLL is disabled (Register 0x09, Bit 7 = 0), the REFCLK

input is used directly as the DAC sample clock (DACCLK). The

frequency of REFCLK needs to be the input data rate multiplied

by the interpolation factor (and by an additional factor of 2 if

zero stuffing is enabled).

[2:0] 011

The PLL loop bandwidth variable configures the bandwidth of

the PLL loop filter. A setting of 00000 configures the bandwidth

to be approximately 1 MHz. A setting of 11111 configures the

bandwidth to be approximately 10 MHz. The optimal value of

01111 sets the loop bandwidth to be approximately 3 MHz.

CLOCK MULTIPLICATION

When the PLL is enabled (Register 0x09, Bit 7 = 1), the clock

multiplication circuit generates the DAC sample clock from the

lower rate REFCLK input. The functional diagram of the clock

multiplier is shown in Figure 72.

Configuring the PLL Band Select Value

The PLL VCO has a valid operating range from approximately

1.0 GHz to 2.0 GHz. This range is covered in 63 overlapping

frequency bands, as shown in Table 23. For any desired VCO

output frequency, there are multiple valid PLL band select values.

It is important to note that the data shown in Table 23 is for a

typical device. Device-to-device variations can shift the actual

VCO output frequency range by 30 MHz to 40 MHz. In addition,

the VCO output frequency varies as a function of temperature.

Therefore, it is required that the optimal PLL band select value

be determined for each individual device at a particular

operating temperature.

PIN 65 AND

0x0A[7:5]

0x00[1]

ADC

PLL CONTROL

VOLTAGE

PLL LOCK

DETECT

0x08[7:2]

VCO BAND

SELECT

PHASE

DETECTOR

LOOP

FILTER

VCO

REFCLK

(PIN 5,

PIN 6)

÷N

1

2

0x09[4:3]

PLL LOOP

DIVISOR

0x09[6:5]

PLL VCO

DIVISOR

The device has an automatic PLL band select feature on chip.

When this feature is enabled, the device determines the optimal

PLL band setting for the device at the given temperature. This

setting holds for a 60°C temperature swing in ambient tem-

perature. If the device is operated in an environment that

experiences a larger temperature swing, an offset should be

applied to the automatically selected PLL band.

DATACLK OUT

(PIN 37)

÷IF

0x01[7:6]

INTERPOLATION

FACTOR

0x09[7]

PLL ENABLE

DACCLK

Figure 72. Clock Multiplier Circuit

Rev. B | Page 39 of 56

AD9776A/AD9778A/AD9779A

Table 23. Typical VCO Frequency Range vs. PLL Band Select Value

PLL Lock Ranges Over Temperature, −40°C to +85°C

VCO Frequency Range (MHz)

PLL Lock Ranges Over Temperature, −40°C to +85°C

VCO Frequency Range (MHz)

PLL Band Select

111111 (63)

111110 (62)

111101 (61)

111100 (60)

111011 (59)

111010 (58)

111001 (57)

111000 (56)

110111 (55)

110110 (54)

110101 (53)

110100 (52)

110011 (51)

110010 (50)

110001 (49)

110000 (48)

101111 (47)

101110 (46)

101101 (45)

101100 (44)

101011 (43)

101010 (42)

101001 (41)

101000 (40)

100111 (39)

100110 (38)

100101 (37)

100100 (36)

100011 (35)

100010 (34)

100001 (33)

100000 (32)

f_LOW

f_HIGH

Auto mode

2026

2008

1992

1977

1961

1942

1931

1915

1897

1885

1869

1853

1840

1825

1810

1794

1780

1766

1748

1729

1702

1681

1658

1639

1606

1600

1575

1553

1529

1505

1489

PLL Band Select

011111 (31)

011110 (30)

011101 (29)

011100 (28)

011011 (27)

011010 (26)

011001 (25)

011000 (24)

010111 (23)

010110 (22)

010101 (21)

010100 (20)

010011 (19)

010010 (18)

010001 (17)

010000 (16)

001111 (15)

001110 (14)

001101 (13)

001100 (12)

001011 (11)

001010 (10)

001001 (9)

001000 (8)

000111 (7)

000110 (6)

000101 (5)

000100 (4)

000011 (3)

000010 (2)

000001 (1)

000000 (0)

f_LOW

f_HIGH

1402

1397

1361

1356

1324

1317

1287

1282

1250

1245

1215

1210

1182

1174

1149

1141

1115

1109

1086

1078

1055

1047

1026

1019

998

1468

1451

1427

1412

1389

1375

1352

1336

1313

1299

1277

1264

1242

1231

1210

1198

1178

1166

1145

1135

1106

1103

1067

1072

1049

1041

1026

1011

996

1975

1956

1938

1923

1902

1883

1870

1848

1830

1822

1794

1779

1774

1748

1729

1730

1699

1685

1684

1651

1640

1604

1596

1564

1555

1521

1514

1480

1475

1439

1435

991

976

963

950

935

922

911

981

966

951

Rev. B | Page 40 of 56

AD9776A/AD9778A/AD9779A

Configuring PLL Band Select with Temperature Sensing

Known Temperature Calibration with Memory

The following procedure outlines a method for setting the PLL

band select value for a device operating at a particular temperature

that holds for a change in ambient temperature over the total

−40°C to +85°C operating range of the device without further

user intervention. Note that REFCLK must be applied to the

device during this procedure.

If temperature sensing is not available in the system, a factory

calibration at a known temperature is another method for

guaranteeing lock over temperature. Factory calibration can be

performed as follows:

1. Program the values of N1 (Register 0x09, Bits[6:5]) and N2

(Register 0x09, Bits[4:3]), along with the PLL settings

shown in Table 22.

2. Set the PLL band (Register 0x08, Bits[7:2]) to 63 to enable

PLL auto mode.

1. Program the values of N1 (Register 0x09, Bits[6:5]) and N2

(Register 0x09, Bits[4:3]), along with the PLL settings

shown in Table 22.

2. Set the PLL band (Register 0x08, Bits[7:2]) to 63 to enable

PLL auto mode.

3. Wait for the PLL_LOCK pin or the PLL lock indicator

(Register 0x00, Bit 1) to go high. This should occur

within 5 ms.

4. Read back the 6-bit PLL band (Register 0x08, Bits[7:2]).

5. Based on the temperature when the PLL auto band select is

performed, set the PLL band indicated in either Table 24 or

Table 25 by rewriting the readback values into the PLL

Band Select parameter (Register 0x08, Bits[7:2]).

3. Wait for the PLL_LOCK pin or the PLL lock indicator

(Register 0x00, Bit 1) to go high. This should occur

within 5 ms.

4. Read back the 6-bit PLL band (Register 0x08, Bits[7:2]).

5. Based on the temperature when the PLL auto band select is

performed, store into nonvolatile memory the PLL band

indicated in either Table 24 or Table 25. On system power-

up or restart, load the stored PLL band value into the PLL

band select parameter (Register 0x08, Bits[7:2]).

Set-and-Forget Device Option

This procedure requires temperature sensing upon start-up or

reset of the device to optimally choose the PLL band select

value that holds over the entire operating temperature range. If

the optimal band is in the range of 0 to 31 (lower VCO

frequency), refer to Table 24.

If the PLL band select configuration methods described in

the previous sections cannot be implemented in a particular

system, there may be a screened device option that can satisfy

the system requirements. This allows the user to preload a

specific PLL band select value for all devices that holds over

temperature. Example REFCLK and VCO frequencies are

shown in Table 26.

Table 24. Setting Optimal PLL Band, When Band Is in the

Lower Range (0 to 31)

If System Startup

Table 26. Typical VCO Frequency Range vs.

PLL Band Select Value

Temperature Is

−40°C to −10°C

−10°C to +15°C

15°C to 55°C

Set PLL Band as Follows

Set PLL band = readback band + 2

Set PLL band = readback band + 1

Set PLL band = readback band

Set PLL band = readback band − 1

Guaranteed

PLL Band

Total PLL

Divide Ratio

f_REFCLK(MHz)

59.73335

61.44

67.2

76.8

80.01

81.92

92.16

112.0

f_VCO(MHz)

955.7336

1966.08

1075.2

1228.8

1280

1310.72

1474.56

1792.0

955.7336

1966.08

2

16

32

16

8

55°C to 85°C

61

11

20

23

25

34

50

2

If the optimal band is in the range of 32 to 62 (higher VCO

frequency), refer to Table 25.

Table 25. Setting Optimal PLL Band, When Band Is in the

Higher Range (32 to 62)

If System Startup

Temperature Is

−40°C to −30°C

−30°C to −10°C

−10°C to +15°C

15°C to 55°C

119.4667

122.88

Set PLL Band as Follows

61

16

Set PLL band = readback band + 3

Set PLL band = readback band + 2

Set PLL band = readback band + 1

Set PLL band = readback band

Set PLL band = readback band − 1

55°C to 85°C

Rev. B | Page 41 of 56

AD9776A/AD9778A/AD9779A

0.1µF

50Ω

TTL OR CMOS

CLK INPUT

DRIVING THE REFCLK INPUT

REFCLK+

REFCLK–

The REFCLK input requires a low jitter differential drive signal.

The signal level can range from 400 mV p-p differential to

1.6 V p-p differential centered about a 400 mV input common-

mode voltage. Looking at the single-ended inputs, REFCLK+ or

REFCLK−, each input pin can safely swing from 200 mV p-p to

800 mV p-p about the 400 mV common-mode voltage. Although

these input levels are not directly LVDS compatible, REFCLK

can be driven by an offset ac-coupled LVDS signal, as shown in

Figure 73.

BAV99ZXCT

HIGH SPEED

DUAL DIODE

V

= 400mV

CM

Figure 74. TTL or CMOS REFCLK Drive Circuit

A simple bias network for generating V_CMis shown in Figure 75.

It is important to use CVDD18 and CGND for the clock bias

circuit. Any noise or other signal that is coupled onto the clock

is multiplied by the DAC digital input signal and can degrade

DAC performance.

0.1µF

LVDS_P_IN

REFCLK+

50Ω

V

= 400mV

CM

V

= 400mV

CM

50Ω

CVDD18

LVDS_N_IN

REFCLK–

1kΩ

0.1µF

1nF

Figure 73. LVDS REFCLK Drive Circuit

0.1µF

1nF

287Ω

CGND

If a clean sine clock is available, it can be transformer-coupled

to REFCLK, as shown in Figure 73. Use of a CMOS or TTL

clock is also acceptable for lower sample rates. It can be routed

through a CMOS to LVDS translator, and then ac-coupled as

described in this section. Alternatively, it can be transformer-

coupled and clamped, as shown in Figure 74.

Figure 75. REFCLK V_CMGenerator Circuit

Rev. B | Page 42 of 56

AD9776A/AD9778A/AD9779A

FULL-SCALE CURRENT GENERATION

INTERNAL REFERENCE

AD9776A/AD9778A/AD9779A

I DAC GAIN

Full-scale current on the I DAC and Q DAC can be set from

8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is

used to set up a current in an external resistor connected to I120

(Pin 75). A simplified block diagram of the reference circuitry is

shown in Figure 76. The recommended value for the external

resistor is 10 kΩ, which sets up an I_REFERENCEin the resistor of

120 μA, which in turn provides a DAC output full-scale current

of 20 mA. Because the gain error is a linear function of this resistor,

a high precision resistor improves gain matching to the internal

matching specification of the devices. Gain drift over temperature

is also affected by this resistor. A resistor with a low temperature

coefficient is recommended in applications requiring good gain

stability.

I DAC

1.2V BAND GAP

VREF

I120

DAC FULL-SCALE

CURRENT

REFERENCE

SCALING

0.1µF

CURRENT

10kΩ

Q DAC

Q DAC GAIN

Figure 76. Reference Circuitry

35

30

25

20

15

10

5

Internal current mirrors provide a current-gain scaling, where

the I DAC or Q DAC gain is a 10-bit word in the 3-wire interface

port register (Register 0x0B, Register 0x0C, Register 0x0F, and

Register 0x10). The default value for the DAC gain registers

gives an I_FSof approximately 20 mA. I_FSis equal to

1.2 V

R

27

12

6

⎛

⎜

⎞

⎛

⎜

⎝

⎞

⎠

I_FS

=

×

+

× DAC Gain ×32

⎟

1024

⎝

⎠

0

200

400

600

800

1000

DAC GAIN CODE

Figure 77. I_FSvs. DAC Gain Code

Rev. B | Page 43 of 56

AD9776A/AD9778A/AD9779A

GAIN AND OFFSET CORRECTION

Analog quadrature modulators make it very easy to realize

single sideband radios. However, there are several nonideal

aspects of quadrature modulator performance. Among these

analog degradations are

scale (10-bit values, 3-wire interface Register 0x0D and 3-wire

interface Register 0x11). This results in a full-scale current of

approximately 2 mA for auxiliary DAC1 and auxiliary DAC2.

The auxiliary DAC structure is shown in Figure 78. Only one of

the two output pins of the auxiliary DAC is active at a time. The

inactive side goes to a high impedance state (>100 kΩ). The

active output pin is chosen by writing to Bit 7 of Register 0x0E

and Register 0x12.

•

Gain mismatch: The gain in the real and imaginary signal

paths of the quadrature modulator may not be matched

perfectly. This leads to less than optimal image rejection

because the cancellation of the negative frequency image is

less than perfect.

The active output can act as either a current source or a current

sink. When sourcing current, the output compliance voltage is

0 V to 1.6 V. When sinking current, the output compliance voltage

is 0.8 V to 1.6 V. The output pin is chosen to be a current source or

current sink by writing to Bit 6 of Register 0x0E and Register 0x12.

0mA TO 2mA

•

Local oscillator (LO) feedthrough: The quadrature mod-

ulator has a finite dc-referred offset, as well as coupling

from its LO port to the signal inputs. These can lead to

significant spectral spurs at the frequency of the quadrature

modulator LO.

(SOURCE)

AUXP

V

The AD9776A/AD9778A/AD9779A have the capability to

correct for both of these analog degradations. Note that these

degradations drift over temperature; therefore, if close to optimal

single sideband performance is desired, a scheme for sensing

these degradations over temperature and correcting for them

may be necessary.

BIAS

0mA TO 2mA

(SINK)

AUXN

P/N

SOURCE/

SINC

Figure 78. Auxiliary DAC Source/Sink for AD9776A/AD9778A/AD97779A

The magnitude of the auxiliary DAC1 current is controlled by the

0x0D and 0x0E auxiliary DAC1 control registers; the magnitude of

the auxiliary DAC2 current is controlled by the 0x11 and 0x12

auxiliary DAC2 control registers. These auxiliary DACs have

the ability to source or sink current. This is programmable via

Bit 6 in either auxiliary DAC control register. The choice of

sinking or sourcing should be made at circuit design time.

There is no advantage to switching between current source or

current sink once the circuit is in place.

I/Q CHANNEL GAIN MATCHING

Gain matching is achieved by adjusting the values in the DAC

gain registers. For the I DAC, these values are in the 0x0B and

0x0C I DAC control registers. For the Q DAC, these values are

in the 0x0F and 0x10 Q DAC control registers. These are 10-bit

values. To perform gain compensation, raise or lower the value

of one of these registers by a fixed step size and measure the

amplitude of the unwanted image. If the unwanted image is

increasing in amplitude, stop the procedure and try the same

adjustment on the other DAC control register. Do this until the

image rejection cannot be improved through further adjustment

of these registers.

The auxiliary DACs can be used for LO cancellation when the

DAC output is followed by a quadrature modulator. This LO

feedthrough is caused by the input-referred dc offset voltage of

the quadrature modulator (and the DAC output offset voltage

mismatch) and may degrade system performance.

It should be noted that LO feedthrough compensation is inde-

pendent of gain. However, gain compensation can affect the LO

compensation because the gain compensation may change the

common-mode level of the signal. The dc offset of some

modulators is common-mode level dependent. Therefore, it is

recommended that the gain adjustment be performed prior to

LO compensation.

Typical DAC-to-quadrature modulator interfaces are shown

in Figure 79. Often, the input common-mode voltage for the

modulator is much higher than the output compliance range of

the DAC, making ac coupling or a dc level shift necessary. If the

required common-mode input voltage on the quadrature modu-

lator matches that of the DAC, then the dc shown in Figure 79 can

be used. A low-pass or band-pass passive filter is recommended

when spurious signals from the DAC (distortion and DAC images)

at the quadrature modulator inputs may affect the system perfor-

mance. Placing the filter at the location shown in Figure 79 allows

easy design of the filter because the source and load impedances

can easily be designed close to 50 ꢀ.

AUXILIARY DAC OPERATION

Two auxiliary DACs are provided on the AD9776A/AD9778A/

AD9779A. The full-scale output current on these DACs is derived

from the 1.2 V band gap reference and external resistor between

the I120 pin and ground. The gain scale from the reference

amplifier current (I_REFERENCE) to the auxiliary DAC reference

current is 16.67 mA with the auxiliary DAC gain set to full

Rev. B | Page 44 of 56

AD9776A/AD9778A/AD9779A

90

RESULTS OF GAIN AND OFFSET CORRECTION

AUX1_P

AD9779A

OUT1_P

500Ω

93

The results of gain and offset correction can be seen in Figure 80

and Figure 81. Figure 80 shows the output spectrum of the quad-

rature demodulator before gain and offset correction. Figure 81

shows the output spectrum after correction. The LO feedthrough

spur at 2.1 GHz has been suppressed to the noise level. This

result can be achieved by applying the correction, but the correc-

tion needs to be repeated after a large change in temperature.

250Ω

LPI

390nH

21

22

IBBP

IBBN

RBIP

50Ω

82pF

C1I

RSLI

100Ω

39pF

C2I

RBIN

50Ω

92

89

OUT1_N

AUX1_N

LNI

390nH

82pF

C3I

250Ω

Note that the gain matching improved the negative frequency

image rejection, but there is still a significant image present.

The remaining image is now due to phase mismatch in the

quadrature modulator. Phase mismatch can be distinguished

from gain mismatch by the shape of the image. Note that the

image in Figure 80 is relatively flat and the image in Figure 81

slopes down with frequency. Phase mismatch is frequency

dependent, so an image dominated by phase mismatch has

this sloping characteristic.

500Ω

87

AUX2_N

OUT2_N

LNQ

390nH

500Ω

250Ω

84

9

QBBN

QBBP

RBQN

50Ω

82pF

C1Q

39pF

C2Q

RSLQ

100Ω

RBQP

83

50Ω

10

OUT2_P

AUX2_P

LPQ

390nH

82pF

C3Q

250Ω

86

RBW

VBW

SWT

3kHz

56s

REF ATT

MIXER

UNIT

30dB

500Ω

REF LVL

0dBm

–40dBm

dBm

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Figure 79. Typical Use of Auxiliary DACs AC Coupling to

Quadrature Modulator

LO FEEDTHROUGH COMPENSATION

The LO feedthrough compensation is the most complex of all

three operations. This is due to the structure of the offset aux-

iliary DACs, as shown in Figure 78. To achieve LO feedthrough

compensation in a circuit, each of four outputs of these auxiliary

DACs can be connected through a 500 Ω resistor to ground

and through a 250 Ω resistor to one of the four quadrature

modulator signal inputs. The purpose of these connections is

to drive a very small amount of current into the nodes at the

quadrature modulator inputs, therefore adding a slight dc bias

to one of the quadrature modulator signal inputs.

CENTER 2.1GHz

20MHz

SPAN 200MHz

Figure 80. AD9779A and ADL5372 with a Multitone Signal at 2.1 GHz,

No Gain or LO Compensation

To achieve LO feedthrough compensation, the user should start

with the default conditions of the auxiliary DAC sign registers,

and then increment the magnitude of one or the other auxiliary

DAC output currents. While this is being done, the amplitude of

the LO feedthrough at the quadrature modulator output should

be sensed. If the LO feedthrough amplitude increases, try either

changing the sign of the auxiliary DAC being adjusted or

adjusting the output current of the other auxiliary DAC. It may

take practice before an effective algorithm is achieved.

RBW

VBW

SWT

20kHz

1.25s

REF ATT

MIXER

UNIT

20dB

REF LVL

0dBm

–40dBm

dBm

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

Using the AD9776A/AD9778A/AD9779A evaluation board, the

LO feedthrough can typically be adjusted down to the noise

floor, although this is not stable over temperature.

CENTER 2.1GHz

20MHz

SPAN 200MHz

Figure 81. AD9779A and ADL5372 with a Multitone Signal at 2.1 GHz,

Gain and LO Compensation Optimized

Rev. B | Page 45 of 56

AD9776A/AD9778A/AD9779A

INPUT DATA PORTS

The AD9776A/AD9778A/AD9779A can operate in two data

input modes: dual port mode and single port mode. For the

default dual port mode (single port bit = 0), each DAC receives

data from a dedicated input port. In single port mode (single

port bit = 1), both DACs receive data from Port 1. In single port

mode, DAC1 and DAC2 data is interleaved, and the TXENABLE

input is used to steer data to the intended DAC. In dual port

mode, the TXENABLE input is used to power down the digital

data path.

DUAL PORT MODE

In dual port mode, data for each DAC is received on the

respective input bus (P1D[15:0] or P2D[15:0]). I and Q data

arrive simultaneously and are sampled on the rising edge of the

DATACLK signal. The TXENABLE signal must be high to enable

the transmit path.

INPUT DATA REFERENCED TO DATACLK

The simplest method of interfacing to the AD9776A/AD9778A/

AD9779A is when the input data is referenced to the DATACLK

output. The DATACLK output is a buffered version (with some

fixed delay) of the internal clock that is used to latch the input

data. Therefore, if setup and hold times of the input data with

respect to DATACLK are met, the input data is latched correctly.

Detailed timing diagrams for the single and dual port cases

using DATACLK as the timing reference are shown in Figure 82.

In dual port mode, the data must be delivered at the input data

rate. In single port mode, data must be delivered at twice the

input data rate of each DAC. Because the data inputs function

up to a maximum of 300 MSPS, it is practical to operate with

input data rates up to 150 MHz per DAC in single port mode.

In dual port and single port modes, a data clock output

(DATACLK) signal is available as a fixed time base with which

to drive data from an FPGA or other data source. This output

signal operates at the input data rate.

DATACLK

t_SDATACLK

t_HDATACLK

SINGLE PORT MODE

DATA

In single port mode, data for both DACs is received on the Port 1

input bus (P1D[15:0]). I and Q data samples are interleaved and

are sampled on the rising edges of DATACLK. Along with the

data, a framing signal must be supplied on the TXENABLE

input (Pin 39), which steers incoming data to its respective DAC.

When TXENABLE is high, the corresponding data-word is sent

to the I DAC. When TXENABLE is low, the corresponding data is

sent to the Q DAC. The timing of the digital interface in

interleaved mode is shown in Figure 83.

Figure 82. Input Data Port Timing, Data Referenced to DATACLK

Table 28 shows the setup and hold time requirements for the

input data over the operating temperature range of the device.

Also shown is the keep out window (KOW). The keep out

window is the sum of the setup and hold times of the interface.

This is the minimum amount of time valid data must be

presented to the device to ensure proper sampling.

DATACLK Frequency Settings

The DATACLK signal is derived from the internal DAC sample

clock, DACCLK. The frequency of the DATACLK output depends

on several programmable settings. Normally, the frequency of

DATACLK is equal to the input data rate. The relationship

between the frequency of DACCLK and DATACLK is

The Q first bit (Register 0x02, Bit 0) controls the pairing order

of the input data. With the Q first bit set to the default of 0, the

I-Q pairing sent to the DACs is the two input data-words

corresponding to TXENABLE low followed by TXENABLE

high. With the Q first bit set to 1, the I-Q pairing sent to the

DACs is the two input data-words corresponding to TXENABLE

high, followed by TXENABLE low. Note that with either order

pairing, the data sent with TXENABLE high is directed to the

I DAC, and the data sent with TXENABLE low is directed to the

Q DAC.

f_DACCLK

f_DATACLK

=

IF × ZS × SP × DATACLKDIV

where the variables IF, ZS, SP, and DATACLKDIV have the

values shown in Table 27.

DATACLK

P1D[15:0]

P1D1

P1D2

P1D3

P1D4

P1D5

P1D6

P1D7

P1D8

TXENABLE

I DAC[15:0]

Q DAC[15:0]

P1D1

P1D2

P1D3

P1D4

P1D5

P1D6

Q FIRST = 0

Q FIRST = 1

I DAC[15:0]

Q DAC[15:0]

P1D1

P1D0

P1D3

P1D2

P1D5

P1D4

Figure 83. Single Port Mode Digital Interface Timing

Rev. B | Page 46 of 56

AD9776A/AD9778A/AD9779A

The DATACLKDIV only affects the DATACLK output frequency,

not the frequency of the data sampling clock. To maintain an

f_DATACLKfrequency that samples the input data that remains

consistent with the expected data rate, DATACLKDIV should

be set to 00.

SYNC_I

t_{H_SYNC}

t_{S_SYNC}

REFCLK

DATA

t_SREFCLK

t_HREFCLK

Table 27. DACCLK to DATACLK Divisor Values

Address

Variable

Value

Register Bit

0x01 [7:6]

Figure 84. Input Data Port Timing, Data Referenced to REFCLK, f_DACCLK= f_REFCLK

IF

Interpolation factor (1, 2, 4,

or 8)

1, if zero stuffing is disabled 0x01

2, if zero stuffing is enabled

0.5, if single port is enabled 0x02

1, if dual port is selected

Note that even though the setup and hold times of SYNC_I

are relative to REFCLK, the SYNC_I input is sampled at the

internal DACCLK rate. In the case where the PLL is employed,

SYNC_I must be asserted to meet the setup time with respect to

REFCLK (t_{S_SYNC}), but cannot be asserted prior to the previous

rising edge of the internal SYNC_I sample clock. In other words,

the SYNC_I assert edge has to be placed between its successive

keep out windows that replicate at the DACCLK rate, not the

REFCLK rate. The valid window for asserting SYNC_I is

shaded gray in Figure 85 for the case where the PLL provides a

DACCLK frequency of four times the REFCLK frequency.

Thus, the minimum setup time is t_{S_SYNC}, and the maximum

ZS

SP

[0]

[6]

DATACLKDIV 1, 2, or 4

0x03

[5:4]

INPUT DATA REFERENCED TO REFCLK

In some systems, it may be more convenient to use the REFCLK

input than the DATACLK output as the input data timing

reference. If the frequency of DACCLK is equal to the frequency

of the data input (without interpolation), then the data with

respect to REFCLK timing specifications in Table 28 apply

directly without further considerations. If the frequency of

DACCLK is greater than the frequency of the input data, a

divider is used to generate the DATACLK output (and the

internal data sampling clock). This divider creates a phase

ambiguity between REFCLK and DATACLK, which results in

uncertainty in the sampling time. To establish fixed setup and

hold times of the data interface, this phase ambiguity must be

eliminated.

setup time is t_DACCLK− t_{H_SYNC}

.

t_DACCLK

SYNC_I

t_{H_SYNC}

t_{S_SYNC}

REFCLK

DACCLK

To eliminate the phase ambiguity, the SYNC_I input pins (Pin 13

and Pin 14) must be used to force the data to be sampled on a

specific REFCLK edge. The relationship among REFCLK,

SYNC_I, and input data is shown in Figure 84 and Figure 85.

Therefore, both SYNC_I and data must meet the timing in

Table 28 for reliable data transfer into the device.

t_SREFCLK

t_HREFCLK

DATA

Figure 85. Input Data Port Timing, Data Referenced to REFCLK,

f_DACCLK= f_REFCLK× 4

More details of the synchronization circuitry are found in the

Device Synchronization section of this data sheet.

Table 28. Data Timing Specifications vs. Temperature

PLL Disabled

PLL Enabled

Timing Parameter

Temperature

−40°C

+25°C

+85°C

−40°C to +85°C −0.80

Min t_S(ns) Min t_H(ns) Min KOW (ns) Min t_S(ns) Min t_H(ns) Min KOW (ns)

Data with Respect to REFCLK

−0.80

−1.00

−1.10

3.35

3.50

3.80

2.55

2.50

2.70

3.00

2.45

2.50

2.60

2.95

0.95

1.00

1.05

1.20

−0.83

−1.06

−1.19

−0.83

2.50

3.87

4.04

4.37

2.99

2.98

3.16

3.54

2.45

2.50

2.60

2.95

1.39

1.48

1.51

1.74

3.80

4.37

Data with Respect to DATACLK

SYNC_I to REFCLK

−40°C

+25°C

+85°C

2.50

2.70

3.00

−0.05

−0.20

−0.40

−0.05

0.65

−0.05

−0.20

−0.40

−0.05

1.17

2.70

3.00

−40°C to +85°C 3.00

−40°C

+25°C

+85°C

0.30

0.25

0.15

0.27

0.19

0.06

0.75

0.90

1.29

1.47

−40°C to +85°C 0.30

0.90

0.27

1.47

Rev. B | Page 47 of 56

AD9776A/AD9778A/AD9779A

In addition to setting the data timing error IRQ, the data timing

error type bit is indicated when an error occurs. The data timing

error type bit is set low to indicate a hold error and high to

indicate a setup error. Figure 87 shows a timing diagram of the

data interface and the status of the data timing error type bit.

OPTIMIZING THE DATA INPUT TIMING

The AD9776A/AD9778A/AD9779A have on-chip circuitry that

enables the user to optimize the input data timing by adjusting

the relationship between the DATACLK output and DCLK_SMP

(the internal clock that samples the input data). This optimization

is made by a sequence of 3-wire interface register read and write

operations. The timing optimization can be done under strict

control of the user, or the device can be programmed to maintain a

configurable timing margin automatically. This function is only

available when the input data is referenced to the DATACLK

output. Each of these methods is detailed in the following section.

DATA

TIMING ERROR = 0

Δ

t_M

Δ

t_M

DATA

TIMING ERROR = 1

DATA TIMING ERROR TYPE = 1

t_M

Figure 86 shows the circuitry that detects sample timing errors

and adjusts the data interface timing. The DCLK_SMP signal is

the internal clock used to latch the input data. Ultimately, it is

the rising edge of this signal that needs to be centered in the

valid sampling period of the input data. This is accomplished by

adjusting the time delay, t_D, which changes the DATACLK

timing and, as a result, the arrival time of the input data with

respect to DCLK_SMP.

TIMING ERROR = 1

DATA TIMING ERROR TYPE = 0

Δ

t_M

Δ

t_M

DELAYED

DATA

SAMPLING

ACTUAL

SAMPLING

INSTANT

DELAYED

CLOCK

SAMPLING

Figure 87. Timing Diagram of Margin Test Data

TIMING

ERROR IRQ

Δ

t_M

D

Q

Automatic Timing Optimization

TIMING

MARGIN[3:0]

TIMING

ERROR

CLK

When automatic timing optimization mode is enabled

TIMING

ERROR TYPE

DETECTION

(Register 0x03, Bit 7 = 1), the device continuously monitors

the data timing error IRQ and data timing error type bits. The

DATACLK Delay[3:0] is increased if a setup error is detected and

decreased if a hold error is detected. The value of the DATACLK

Delay[3:0] setting currently in use can be read back by the user.

PD1[0]

D

Q

Δ

t_M

CLK

DATACLK

DELAY[3:0]

DCLK_SMP

DATACLK

Δ

t_D

Manual Timing Optimization

When the device is operating in manual timing optimization

mode (Register 0x03, Bit 7 = 0), the device does not alter the

DATACLK Delay[3:0] value from what is programmed by the

user. By default, the DATACLK delay enable bit is inactive. This

bit must be set high for the DATACLK Delay[3:0] value to be

realized. The delay (in absolute time) when programming

DATACLK delay between 00000 and 11111 varies from about

700 ps to about 6.5 ns. The typical delays per increment over

temperature are shown in Table 29.

Figure 86. Timing Error Detection and Optimization Circuitry

The error detect circuitry works by creating two sets of sampled

data (referred to as the margin test data) in addition to the

actual sampled data used in the device data path. One set of

sampled data is latched before the actual data sampling point.

The other set of sampled data is latched after the actual data

sampling point. If the margin test data match the actual data,

the sampling is considered valid and no error is declared. If

there is a mismatch between the actual data and the margin test

data, an error is declared.

Table 29. Data Delay Line Typical Delays Over Temperature

Delay

−40°C +25°C +85°C Unit

The Data Timing Margin[3:0] variable determines how much

before and after the actual data sampling point the margin test

data are latched. Therefore, the data timing margin variable

determines how much setup and hold margin the interface

needs for the data timing error IRQ to remain inactive (show

error free operation). Therefore, the timing error IRQ is set

whenever the setup and hold margins drop below the Data

Timing Margin[3:0] value and does not necessarily indicate that

the data latched into the device is incorrect.

Zero Code Delay (Delay Upon 630

Enabling Delay Line)

Average Unit Delay

700

740

ps

175

190

210

ps

When the device is placed into manual mode, the error

checking logic is activated. If the IRQs are enabled, an interrupt

is generated if a setup/hold violation is detected. One error

check operation is performed per device configuration. Any

change to the Data Timing Margin[3:0] or DATACLK

Delay[3:0] values triggers a new error check operation.

Rev. B | Page 48 of 56

AD9776A/AD9778A/AD9779A

DEVICE SYNCHRONIZATION

System demands can impose two different requirements for

synchronization. Some systems require multiple DACs to be

synchronized to each other. This is the case when supporting

transmit diversity or beam forming, where multiple antennas

are used to transmit a correlated signal. In this case, the DAC

outputs need to be phase aligned with each other, but there may

not be a requirement for the DAC outputs to be aligned with a

system level reference clock. In systems with a time division

multiplexing transmit chain, one or more DACs may need to be

synchronized with a system level reference clock. The options

for synchronizing devices under these two conditions are

described in the Synchronization Logic Overview section

and the Synchronizing Devices to a System Clock section.

multiple of 32 DACCLK periods. In any case, the maximum

frequency of SYNC_I must be less than f_DATACLK

.

Table 30. Settings Required to Support Various SYNC_I

Frequencies

SYNC_I

Ratio[2:0]

SYNC_I Rising Edges Required for

Synchronization Pulse

000

001

010

011

100

101

110

111

1 (default)

2

4

8

16

Invalid setting

SYNCHRONIZATION LOGIC OVERVIEW

Figure 88 shows the block diagram of the on-chip synchroniza-

tion logic. The basic operation of the synchronization logic is to

generate a single DACCLK-cycle-wide initialization pulse that

sets the clock generation state machine logic to a known state.

This initialization pulse loads the clock generation state machine

with the Clock State[4:0] value as its next state. If the initializa-

tion pulse from the synchronization logic is generated properly,

it is active for one DACCLK cycle, every 32 DACCLK cycles.

Because the clock generation state machine has 32 states operating

at the DACCLK rate, every initialization pulse received after the

first pulse loads the state in which the state machine is already

in, maintaining proper clocking operation of the device.

PLL

As an example, if a SYNC_I signal with a frequency of f_DACCLK/4

is used, then both 011 and 100 are valid settings for the SYNC_I

Ratio[2:0] value. A setting of 011 results in one initialization

pulse being generated every 32 DACCLK cycles, and a setting

of 100 results in one initialization pulse being generated every

64 DACCLK cycles. Both cases result in proper device

synchronization.

The Clock State[4:0] value is the state to which the clock

generation state machine resets upon initialization. By varying

this value, the timing of the internal clocks with respect to the

SYNC_I signal can be adjusted. Every increment of the Clock

State[4:0] value advances the internal clocks by one DACCLK

period.

BYPASS

INTERNAL

REFCLK

PLL

DACCLK

BIT 0 (1× INTERPOLATION)

CLOCK

GENERATION

STATE

Synchronization Timing Error Detection

BIT 1 (2×)

BIT 2 (4×)

BIT 3 (8×)

The synchronization logic has error detection circuitry similar to

the input data timing. The SYNC_I Timing Margin[3:0] variable

determines how much setup and hold margin the synchronization

interface needs for the sync timing error IRQ bit to remain inactive

(that is, to indicate error free operation). Therefore, the sync timing

error IRQ bit is set whenever the setup and hold margins drop

below the SYNC_I Timing Margin[3:0] value and, therefore,

does not necessarily indicate that the SYNC_I input was latched

incorrectly.

MUX

MACHINE

BIT 4 (8× WITH

ZERO STUFFING)

LOAD DACCLK OFFSET VALUE (REG 0x07,

BITS[4:0]), ONE DACCLK CYCLE/INCREMENT

SYNC

DELAY

ERROR DETECT

CIRCUITRY

SYNC_I

SYNC IRQ

DELAY REGISTER

(REG 0x0, BITS[7:4])

PULSE

GENERATION

LOGIC

When the sync timing error IRQ bit is set, corrective action can

be taken to restore timing margin. One course of action is to

temporarily reduce the timing margin until the sync timing

error IRQ is cleared. Then, increase the SYNC_I delay by two

increments and check whether the timing margin has increased

or decreased. If it has increased, continue incrementing the

value of SYNC_I delay until the margin is maximized. However,

if incrementing the SYNC_I delay reduced the timing margin,

then the delay should be reduced until the timing margin is

optimized.

f_{SYNC_1}

<

f_DATA/2^N

Figure 88. Synchronization Circuitry Block Diagram

Nominally, the SYNC_I input should have one rising edge every

32 clock cycles (or multiple of 32 clock cycles) to maintain

proper synchronization. The pulse generation logic can be

programmed to suppress outgoing pulses if the incoming

SYNC_I frequency is greater than DACCLK/32. Extra pulses

can be suppressed by the ratios listed in Table 30. The SYNC_I

frequency can be lower than DACCLK/32 as long as output

pulses are generated from the pulse generation circuit on a

Rev. B | Page 49 of 56

AD9776A/AD9778A/AD9779A

Figure 90 shows the timing of the SYNC_I input with respect to

the REFCLK input. Note that although the timing is relative to

the REFCLK signal, SYNC_I is sampled at the DACCLK rate.

This means that the rising edge of the SYNC_I signal must occur

after the hold time of the preceding DACCLK rising edge, not

the preceding REFCLK rising edge.

SYNCHRONIZING DEVICES TO A SYSTEM CLOCK

The AD9776A/AD9778A/AD9779A offer a pulse mode synchro-

nization scheme (see Figure 89) to align the DAC outputs of

multiple devices within a system to the same DACCLK edge.

The internal clocks are synchronized by providing either a one-

time pulse or a periodic signal to the SYNC_I inputs (SYNC_I+,

SYNC_I−). The SYNC_I signal is sampled by the internal

DACCLK sample rate clock.

INTERRUPT REQUEST OPERATION

The IRQ pin (Pin 71) acts as an alert in the event that the

device has a timing error and should be queried (by reading

Register 0x19) to determine the exact fault condition. The IRQ pin

is an open-drain, active low output. The IRQ pin should be pulled

high external to the device. This pin can be tied to the IRQ pins

of other devices with open-drain outputs to wire-OR these pins

together.

The SYNC_I input frequency has the following constraint:

f

_{SYNC_I}≤ f_DATA

When the internal clocks are synchronized, the data-sampling

clocks between all devices are phase aligned. The data input

timing relationships can be referenced to either REFCLK or

DATACLK.

There are two different error flags that can trigger an interrupt

request: a data timing error flag or a sync timing error flag. By

default, when either or both of these error flags are set, the IRQ pin

is active low. Either or both of these error flags can be masked

to prevent them from activating an interrupt on the IRQ pin.

For this synchronization scheme, all devices are slave devices,

and the system clock generation/distribution chip serves as the

master. It is vital that the SYNC_I signal be distributed between

the DACs with low skew. Likewise, the REFCLK signals must be

distributed with low skew. Any skew on these signals between the

DACs must be accounted for in the timing budget. Figure 89

shows an example clock and synchronization input scheme.

The error flags are latched and remain active until the interrupt

register, Register 0x19, is either read from or the error flag bits

are overwritten.

MATCHED

LENGTH TRACES

REFCLK

SYNC_I

OUT

SYSTEM CLOCK

LOW SKEW

CLOCK DRIVER

REFCLK

SYNC_I

OUT

PULSE

GENERATOR

LOW SKEW

CLOCK DRIVER

MATCHED

LENGTH TRACES

Figure 89. Multichip Synchronization in Pulse Mode

SYNC_I

t_{H_SYNC}

t_{S_SYNC}

REFCLK

DACCLK

Figure 90. Timing Diagram of SYNC_I with Respect to REFCLK When Synchronizing Multiple Devices to Each Other

Rev. B | Page 50 of 56

AD9776A/AD9778A/AD9779A

POWER DISSIPATION

Figure 91 to Figure 99 show the power dissipation of the 1.8 V and 3.3 V digital and clock supplies in single DAC mode and dual DAC

mode. In addition to this, the power dissipation/current of the 3.3 V analog supply (mode and speed independent) in single DAC mode is

102 mW/31 mA. In dual DAC mode, this is 182 mW/55 mA. When the PLL is enabled, it adds 50 mA/90 mW to the 1.8 V clock supply.

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.075

0.050

0.025

0

8× INTERPOLATION

4× INTERPOLATION

4× INTERPOLATION,

ZERO STUFFING

8× INTERPOLATION,

ZERO STUFFING

ALL INTERPOLATION MODES

2× INTERPOLATION,

ZERO STUFFING

2× INTERPOLATION

1× INTERPOLATION,

ZERO STUFFING

1× INTERPOLATION

0

25

50

75

100 125 150 175 200 225 250

f_DATA(MSPS)

0

25

50

75

100 125 150 175 200 225 250

f_DATA(MSPS)

Figure 91. Total Power Dissipation, I Data Only, Real Mode

Figure 94. Power Dissipation, Digital 3.3 V Supply, I Data Only, Real Mode,

Includes Modulation Modes and Zero Stuffing

0.4

1.0

8× INTERPOLATION, ALL

MODULATION MODES

8× INTERPOLATION,

0.9

ZERO STUFFING

4× INTERPOLATION,

ALL MODULATION

8× INTERPOLATION

4× INTERPOLATION

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

MODES

0.3

0.2

0.1

0

2× INTERPOLATION,

2× INTERPOLATION

ALL MODULATION MODES

2× INTERPOLATION,

ZERO STUFFING

4× INTERPOLATION,

ZERO STUFFING

1× INTERPOLATION

1× INTERPOLATION,

ZERO STUFFING

1× INTERPOLATION

0

25

50

75

100 125 150 175 200 225 250

f_DATA(MSPS)

0

25 50 75 100 125 150 175 200 225 250 275 300

f_DATA(MSPS)

Figure 92. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode,

Does Not Include Zero Stuffing

Figure 95. Total Power Dissipation, Dual DAC Mode

0.8

0.7

0.6

0.08

8× INTERPOLATION, f

/8,

/4,

/2,

DAC

f

NO MODULATION

4× INTERPOLATION

0.06

8× INTERPOLATION

4× INTERPOLATION

0.5

0.4

0.3

0.2

0.1

0

0.04

2× INTERPOLATION

0.02

1× INTERPOLATION,

NO MODULATION

1× INTERPOLATION

0

25

50

75

100 125 150 175 200 225 250

f_DATA(MSPS)

0

25

50

75

100 125 150 175 200 225 250

f_DATA(MSPS)

Figure 96. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Dual DAC

Mode, Does Not Include Zero Stuffing

Figure 93. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode,

Includes Modulation Modes, Does Not Include Zero Stuffing

Rev. B | Page 51 of 56

AD9776A/AD9778A/AD9779A

0.125

POWER-DOWN AND SLEEP MODES

8× INTERPOLATION, f

/8,

/4,

/2,

DAC

f

The AD9776A/AD9778A/AD9779A have a variety of power-down

modes; thus, the digital engine, main TxDACs, or auxiliary DACs

can be powered down individually or together. Via the 3-wire

interface port, the main TxDACs can be placed in sleep or power-

down mode. In sleep mode, the TxDAC output is turned off,

thus reducing power dissipation. The reference remains powered

on, however, so that recovery from sleep mode is very fast. With

the power-down mode bit set (Register 0x00, Bit 4), all analog

and digital circuitry, including the reference, is powered down.

The 3-wire interface port remains active in this mode. This

mode offers more substantial power savings than sleep mode,

but the turn-on time is much longer. The auxiliary DACs also

have the capability to be programmed into sleep mode via the

3-wire interface port. The auto power-down enable bit (Register

0x00, Bit 3) controls the power-down function for the digital

section of the devices. The auto power-down function works in

conjunction with the TXENABLE pin (Pin 39); see Table 31 for

details.

NO MODULATION

0.100

0.075

0.050

0.025

0

4× INTERPOLATION

2× INTERPOLATION

1× INTERPOLATION,

NO MODULATION

0

25

50

75

100 125 150 175 200 225 250

f_DATA(MSPS)

Figure 97. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC

Mode, Does Not Include Zero Stuffing

0.075

Table 31.

TXENABLE

(Pin 39)

ALL INTERPOLATION MODES

0.050

0.025

0

Description

0

If auto power-down enable bit = 0, flush data

path with 0s.

If auto power-down enable bit = 1, flush data for

multiple REFCLK cycles; then, automatically

place the digital engine in power-down state.

DACs, reference, and 3-wire interface port are

not affected.

1

Normal operation.

0

25

50

75

100 125 150 175 200 225 250

f_DATA(MSPS)

Figure 98. Power Dissipation, Digital 3.3 V Supply, I and Q Data,

Dual DAC Mode

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

200

400

600

800

1000

1200

f_DAC(MSPS)

Figure 99. DVDD18 Power Dissipation of Inverse Sinc Filter

Rev. B | Page 52 of 56

AD9776A/AD9778A/AD9779A

EVALUATION BOARD OVERVIEW

The typical evaluation setup is shown in Figure 100. A sine or

square wave clock can be used to source the DAC sample clock.

The spectral purity of the clock directly affects the device per-

formance. A low noise, low jitter clock source is required.

EVALUATION BOARD OPERATION

The AD9776A/AD9778A/AD9779A evaluation board is provided

to help users quickly become familiar with the operation of the

device and to evaluate the device performance. To operate the

evaluation board, the user needs a PC, a 5 V power supply, a

clock source, and a digital data source. The user also needs a

spectrum analyzer or an oscilloscope to observe the DAC output.

All necessary connections to the evaluation board are shown in

more detail in Figure 101.

CLOCK

GENERATOR

ADAPTER

CABLES

CLKIN

SPI PORT

SPECTRUM

ANALYZER

AD9776A/

AD9778A/

DIGITAL

PATTERN

GENERATOR

AD9779A

EVALUATION

BOARD

CLOCK IN

1.8V POWER SUPPLY

3.3V POWER SUPPLY

DATACLK OUT

Figure 100. Typical Test Setup

DVDD18

DVDD33

CVDD18

AVDD33

J2

5V SUPPLY

P4 DIGITAL INPUT CONNECTOR

MODULATOR

OUTPUT

J1 CLOCK IN

JP4

JP15

JP8

S5 OUTPUT 1

+5V

JP14

AD9779A

ADL537x

GND

JP3

JP16

JP2

S6 OUTPUT 2

JP17

LOCAL OSC

INPUT

ANALOG

DEVICES

S7 DCLKOUT

AD9776A/

AD9778A/

AD9779A

SPI PORT

Figure 101. AD9776A/AD9778A/AD9779A Evaluation Board Showing All Connections

Rev. B | Page 53 of 56

AD9776A/AD9778A/AD9779A

The evaluation board comes with software that allows the user

to program the on-chip configuration registers. Via the 3-wire

interface port, the devices can be programmed into any of its

various operating modes. The default software window is

shown in Figure 102.

The evaluation board also comes populated with the ADL537x

modulator to allow for the evaluation of an RF subsystem.

Complete details on the evaluation board and the 3-wire

interface software can be downloaded from the Analog Devices

website.

1. SET INTERPOLATION RATE

2. SET INTERPOLATION FILTER MODE

3. SET INPUT DATA FORMAT

4. SET DATACLK POLARITY TO MATCH INPUT TIMING

Figure 102. 3-Wire Interface Port Software Window

Rev. B | Page 54 of 56

AD9776A/AD9778A/AD9779A

OUTLINE DIMENSIONS

16.00 BSC SQ

1.20

0.75

0.60

0.45

MAX

14.00 BSC SQ

100

1

76

75

76

100

1

75

SEATING

PLANE

PIN 1

BOTTOM VIEW

(PINS UP)

TOP VIEW

(PINS DOWN)

CONDUCTIVE

HEAT SINK

51

25

26

50

26

0.20

0.09

1.05

1.00

0.95

6.50

NOM

7°

3.5°

0°

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.15

0.05

COPLANARITY

0.08

0.27

0.22

0.17

0.50 BSC

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MS-026-AED-HDT

Figure 103. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-100-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

−40°C to +85°C

Package Description

Package Option

SV-100-1

AD9776ABSVZ¹

AD9776ABSVZRL¹

AD9778ABSVZ¹

AD9778ABSVZRL¹

AD9779ABSVZ¹

AD9779ABSVZRL¹

AD9776A-EBZ¹

AD9778A-EBZ¹

AD9779A-EBZ¹

100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

Evaluation Board

SV-100-1

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. B | Page 55 of 56

AD9776A/AD9778A/AD9779A

NOTES

registered trademarks are the property of their respective owners.

D06452-0-9/08(B)

Rev. B | Page 56 of 56


型号：	AD9779A-EBZ
厂家：	ADI
描述：	Dual, 12-/14-/16-Bit,1 GSPS 双通道， 12位/ 14位/ 16位， 1 GSPS
文件：	总56页 (文件大小：1177K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9779A-EBZ [ADI]

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AD9779ABSVZ

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AD9779BSVZ1

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AD9779BSVZRL1

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