AD9780BCPZRL [ADI]
Dual 12-/14-/16-Bit, LVDS Interface, 500 MSPS DACs; 双12位/ 14位/ 16位， LVDS接口， 500 MSPS数模转换器
| 型号： | AD9780BCPZRL |
| 厂家： | 
ADI |
| 描述： | Dual 12-/14-/16-Bit, LVDS Interface, 500 MSPS DACs |
| 文件： | 总36页 (文件大小：1275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 12-/14-/16-Bit,
LVDS Interface, 500 MSPS DACs
AD9780/AD9781/AD9783
GENERAL DESCRIPTION
FEATURES
High dynamic range, dual DAC parts
The AD9780/AD9781/AD9783 include pin-compatible, high
dynamic range, dual digital-to-analog converters (DACs) with
12-/14-/16-bit resolutions, and sample rates of up to 500 MSPS.
The devices include specific features for direct conversion transmit
applications, including gain and offset compensation, and they
interface seamlessly with analog quadrature modulators such as
the ADL5370.
Low noise and intermodulation distortion
Single carrier W-CDMA ACLR = 80 dBc @ 61.44 MHz IF
Innovative switching output stage permits usable outputs
beyond Nyquist frequency
LVDS inputs with dual-port or optional interleaved single-
port operation
Differential analog current outputs are programmable from
8.6 mA to 31.7 mA full scale
Auxiliary 10-bit current DACs with source/sink capability for
external offset nulling
A proprietary, dynamic output architecture permits synthesis
of analog outputs even above Nyquist by shifting energy away
from the fundamental and into the image frequency.
Full programmability is provided through a serial peripheral
interface (SPI) port. Some pin-programmable features are also
offered for those applications without a controller.
Internal 1.2 V precision reference voltage source
Operates from 1.8 V and 3.3 V supplies
315 mW power dissipation
Small footprint, RoHS compliant, 72-lead LFCSP
PRODUCT HIGHLIGHTS
APPLICATIONS
1. Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals.
2. Proprietary switching output for enhanced dynamic
performance.
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX
Wideband communications
3. Programmable current outputs and dual auxiliary DACs
provide flexibility and system enhancements.
LMDS/MMDS, point-to-point
RF signal generators, arbitrary waveform generators
FUNCTIONAL BLOCK DIAGRAM
CLKP
CLKN
AD9783 DUAL LVDS DAC
IOUT1P
IOUT1N
16-BIT
I DAC
INTERFACE LOGIC
IOUT2P
IOUT2N
16-BIT
Q DAC
LVDS
INTERFACE
D[15:0]
GAIN
DAC
V
, V
IA IB
GAIN
DAC
AUX1P
AUX1N
OFFSET
DAC
INTERNAL
REFERENCE
AND
SERIAL
PERIPHERAL
INTERFACE
AUX2P
AUX2N
OFFSET
DAC
BIAS
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved.
AD9780/AD9781/AD9783
TABLE OF CONTENTS
Features .............................................................................................. 1
General Operation of the Serial Interface............................... 18
Instruction Byte.......................................................................... 18
MSB/LSB Transfers .................................................................... 19
Serial Interface Port Pin Descriptions ..................................... 19
SPI Register Map ............................................................................ 20
SPI Register Descriptions.............................................................. 21
SPI Port, RESET, and Pin Mode............................................... 23
Parallel Data Port Interface ........................................................... 24
Optimizing the Parallel Port Timing....................................... 24
Driving the CLK Input .............................................................. 26
Full-Scale Current Generation ................................................. 26
DAC Transfer Function............................................................. 27
Analog Modes of Operation ..................................................... 27
Power Dissipation....................................................................... 29
Evaluation Board Schematics........................................................ 30
Outline Dimensions....................................................................... 35
Ordering Guide .......................................................................... 35
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
AC Specifications.......................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
Serial Peripheral Interface......................................................... 18
REVISION HISTORY
6/08—Rev. 0 to Rev. A
Changed Maximum Sample Rate to 500 MHz Throughout....... 1
Changes to Table 3............................................................................ 4
Changes to Building the Array Section ....................................... 25
Changes to Determining the SMP Value Section....................... 25
Added Evaluation Board Schematics Section............................. 30
Updated Outline Dimensions....................................................... 35
11/07—Revision 0: Initial Version
Rev. A | Page 2 of 36
AD9780/AD9781/AD9783
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless
otherwise noted.
Table 1.
AD9780
Typ
AD9781
Typ
AD9783
Typ
Parameter
Min
Max
Min
Max
Min
Max
Unit
RESOLUTION
12
14
16
Bits
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error (with Internal Reference)
Full-Scale Output Current1
Output Compliance Range
Output Resistance
Main DAC Monotonicity Guaranteed
MAIN DAC TEMPERATURE DRIFT
Offset
±±.13
±±.2ꢀ
±±.ꢀ
±1
±2
±4
LSB
LSB
–±.±±1
±
±2
2±.2
+±.±±1
–±.±±1
±
±2
2±.2
+±.±±1
–±.±±1
±
±2
+±.±±1
% FSR
% FSR
mA
V
MΩ
8.66
–1.±
31.66
+1.±
8.66
–1.±
31.66
+1.±
8.66
–1.±
2±.2 31.66
+1.±
1±
1±
1±
±.±4
1±±
3±
±.±4
1±±
3±
±.±4
1±±
3±
ppm/°C
ppm/°C
ppm/°C
Gain
Reference Voltage
AUX DAC OUTPUTS
Resolution
Full-Scale Output Current
Output Compliance Range (Source)
Output Compliance Range (Sink)
Output Resistance
AUX DAC Monotonicity Guaranteed
REFERENCE
1±
1±
1±
+2
1.6
1.6
1
Bits
mA
V
V
MΩ
–2
±
±.8
+2
1.6
1.6
–2
±
±.8
+2
1.6
1.6
–2
±
±.8
1
1
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
1.2
ꢀ
1.2
ꢀ
1.2
ꢀ
V
kΩ
3.13
1.7±
3.3
1.8
3.47
1.9±
3.13
1.7±
3.3
1.8
3.47
1.9±
3.13
1.7±
3.3
1.8
3.47
1.9±
V
V
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD33
DVDD18
3.13
1.7±
3.3
1.8
3.47
1.9±
3.13
1.7±
3.3
1.8
3.47
1.9±
3.13
1.7±
3.3
1.8
3.47
1.9±
V
V
POWER CONSUMPTION
fDAC = ꢀ±± MSPS, IF = 2± MHz
fDAC = ꢀ±± MSPS, IF = 1± MHz
Power-Down Mode
SUPPLY CURRENTS2
AVDD33
CVDD18
DVDD33
DVDD18
V × I
44±
3
V × I
ꢀ
V × I V × I
44±
V × I V × I
44±
mW
mW
mW
3
ꢀ
3
3ꢀ
ꢀꢀ
34
13
68
ꢀ8
38
1ꢀ
8ꢀ
ꢀꢀ
34
13
68
ꢀ8
38
1ꢀ
8ꢀ
ꢀꢀ
34
13
68
ꢀ8
38
1ꢀ
8ꢀ
mA
mA
mA
mA
1 Based on a 1± kΩ external resistor.
2 fDAC = ꢀ±± MSPS, fOUT = 2± MHz.
Rev. A | Page 3 of 36
AD9780/AD9781/AD9783
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
DAC CLOCK INPUT (CLKP, CLKN)
Peak-to-Peak Voltage at CLKP and CLKN
Common-Mode Voltage
4±±
3±±
ꢀ±±
8±±
4±±
16±±
ꢀ±±
mV
mV
MSPS
Maximum Clock Rate
SERIAL PERIPHERAL INTERFACE (CMOS INTERFACE)
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
4±
12.ꢀ
12.ꢀ
MHz
ns
ns
Minimum Pulse Width Low
DIGITAL INPUT DATA (LVDS INTERFACE)
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH to VIDTHL
Input Differential Input Impedance, RIN
Maximum LVDS Input Rate (per DAC)
8±±
−1±±
16±±
+1±±
mV
mV
mV
Ω
2±
8±
ꢀ±±
12±
MSPS
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 3.
AD9780
Min Typ
AD9781
Max Min Typ
AD9783
Max Min Typ
Parameter
Max Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = ꢀ±± MSPS, fOUT = 2± MHz
fDAC = ꢀ±± MSPS, fOUT = 12± MHz
fDAC = ꢀ±± MSPS, fOUT = 38± MHz (Mix Mode)
fDAC = ꢀ±± MSPS, fOUT = 48± MHz (Mix Mode)
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = ꢀ±± MSPS, fOUT = 2± MHz
79
67
ꢀꢀ
ꢀ8
78
66
ꢀ8
62
8±
68
62
ꢀ9
dBc
dBc
dBc
dBc
91
8±
69
6±.ꢀ
93
7ꢀ
7±
61.ꢀ
86
79
64
66
dBc
dBc
dBc
dBc
fDAC = ꢀ±± MSPS, fOUT = 12± MHz
fDAC = ꢀ±± MSPS, fOUT = 38± MHz (Mix Mode)
fDAC = ꢀ±± MSPS, fOUT = 48± MHz (Mix Mode)
ONE-TONE NOISE SPECTRAL DENSITY (NSD)
fDAC = ꢀ±± MSPS, fOUT = 4± MHz
fDAC = ꢀ±± MSPS, fOUT = 12± MHz
fDAC = ꢀ±± MSPS, fOUT = 38± MHz (Mix Mode)
fDAC = ꢀ±± MSPS, fOUT = 48± MHz (Mix Mode)
−1ꢀ7
−1ꢀ4.ꢀ
−1ꢀ3
−1ꢀ2
−162
−1ꢀ6.ꢀ
−1ꢀ3
−1ꢀ2
−16ꢀ
−1ꢀ7
−1ꢀ4
−1ꢀ3
dBc
dBc
dBc
dBc
W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),
SINGLE CARRIER
fDAC = 491.ꢀ2 MSPS, fOUT = 2± MHz
fDAC = 491.ꢀ2 MSPS, fOUT = 8± MHz
fDAC = 491.ꢀ2 MSPS, fOUT = 411.ꢀ2 MHz
fDAC = 491.ꢀ2 MSPS, fOUT = 471.ꢀ2 MHz
−81
−8±
−71
−69
−82.ꢀ
−82.ꢀ
−68
−82
−81
−69
−7±
dBc
dBc
dBc
dBc
−69
Rev. A | Page 4 of 36
AD9780/AD9781/AD9783
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
Thermal resistance is tested using a JEDEC standard 4-layer
thermal test board with no airflow.
With
Respect to
Parameter
AVDD33, DVDD33
DVDD18, CVDD18
AGND
DGND
CGND
Rating
AGND, DGND, CGND −±.3 V to +3.6 V
AGND, DGND, CGND −±.3 V to +1.98 V
DGND, CGND
AGND, CGND
AGND, DGND
AGND
Table 5.
Package Type
θJA
Unit
−±.3 V to +±.3 V
−±.3 V to +±.3 V
−±.3 V to +±.3 V
−±.3 V to
AVDD33 + ±.3 V
CP-72-1 (Exposed Pad Soldered to PCB)
2ꢀ
°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
REFIO
IOUT1P, IOUT1N,
IOUT2P, IOUT2N,
AUX1P, AUX1N,
AUX2P, AUX2N
AGND
−1.± V to
AVDD33 + ±.3 V
D1ꢀ to D±
DGND
CGND
−±.3 V to
DVDD33 + ±.3 V
−±.3 V to
ESD CAUTION
CLKP, CLKN
CVDD18 + ±.3 V
CSB, SCLK, SDIO, SDO DGND
–±.3 V to
DVDD33 + ±.3 V
Junction Temperature
Storage Temperature
+12ꢀ°C
−6ꢀ°C to +1ꢀ±°C
Rev. A | Page ꢀ of 36
AD9780/AD9781/AD9783
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
D11P
1
2
3
4
5
6
7
8
9
54 FS ADJ
53 RESET
52 CSB
51 SCLK
50 SDIO
49 SDO
48 DVSS
47 DVDD18
46 NC
PIN 1
INDICATOR
AD9780
(TOP VIEW)
D11N 10
D10P 11
D10N 12
D9P 13
D9N 14
D8P 15
D8N 16
D7P 17
D7N 18
45 NC
44 NC
43 NC
42 NC
41 NC
40 NC
39 NC
38 D0N
37 D0P
NOTES
1. NC = NO CONNECT
2. EXPOSED PAD MUST BE
SOLDERED TO PCB AND
CONNECTED TO AVSS.
Figure 2. AD9780 Pin Configuration
Table 6. AD9780 Pin Function Descriptions
Pin No.
1, 6
2, ꢀ
Mnemonic
CVDD18
CVSS
Description
Clock Supply Voltage (1.8 V).
Clock Supply Return.
3, 4
7, 28, 48
CLKP, CLKN
DVSS
Differential DAC Sampling Clock Input.
Digital Common.
8, 47
9 to 24, 31 to 38
2ꢀ, 26
27
29, 3±
39 to 46
DVDD18
D11P, D11N to D±P, D±N
DCOP, DCON
DVDD33
DCIP, DCIN
NC
Digital Supply Voltage (1.8 V).
LVDS Data Inputs. D11 is the MSB, D± is the LSB.
Differential Data Clock Output. LVDS clock at the DAC sample rate.
Digital Input and Output Pad Ring Supply Voltage (3.3 V).
Differential Data Clock Input. LVDS clock aligned with input data.
No Connection. Leave these pins floating.
49
SDO
Serial Port Data Output.
ꢀ±
ꢀ1
SDIO
SCLK
Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode).
Serial Port Clock Input.
ꢀ2
CSB
Serial Port Chip Select (Active Low).
ꢀ3
RESET
Chip Reset (Active High).
ꢀ4
FS ADJ
Full-Scale Current Output Adjust.
ꢀꢀ
REFIO
AVDD33
AVSS
Analog Reference Input/Output (1.2 V Nominal).
Analog Supply Voltage (3.3 V).
Analog Common.
ꢀ6, ꢀ7, 71, 72
ꢀ8, 61, 64, 67, 7±
ꢀ9
6±
62, 63
6ꢀ, 66
68
69
IOUT2P
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are ±s.
Differential Auxiliary DAC Current Output (Channel 2).
Differential Auxiliary DAC Current Output (Channel 1).
Complementary DAC Current Output. Full-scale current is sourced when all data bits are ±s.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
IOUT2N
AUX2P, AUX2N
AUX1N, AUX1P
IOUT1N
IOUT1P
Heat Sink Pad
N/A
The heat sink pad on the bottom of the package should be soldered to the PCB plane that
carries AVSS.
Rev. A | Page 6 of 36
AD9780/AD9781/AD9783
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
D13P
1
2
3
4
5
6
7
8
9
54 FS ADJ
RESET
52 CSB
PIN 1
INDICATOR
53
51 SCLK
50
SDIO
49 SDO
48 DVSS
AD9781
(TOP VIEW)
47
DVDD18
46 NC
D13N 10
D12P 11
D12N 12
D11P 13
D11N 14
D10P 15
D10N 16
D9P 17
NC
NC
43 NC
D0N
41 D0P
40 D1N
45
44
42
39
38 D2N
D2P
D1P
D9N 18
37
NOTES
1. NC = NO CONNECT
2. EXPOSED PAD MUST BE
SOLDERED TO PCB AND
CONNECTED TO AVSS.
Figure 3. AD9781 Pin Configuration
Table 7. AD9781 Pin Function Descriptions
Pin No.
Mnemonic
CVDD18
CVSS
Description
1, 6
2, ꢀ
Clock Supply Voltage (1.8 V).
Clock Supply Return.
3, 4
7, 28, 48
CLKP, CLKN
DVSS
Differential DAC Sampling Clock Input.
Digital Common.
8, 47
DVDD18
Digital Supply Voltage (1.8 V).
9 to 24, 31 to 42
D13P, D13N to D±P, D±N LVDS Data Inputs. D13 is the MSB, D± is the LSB.
2ꢀ, 26
27
29, 3±
43 to 46
DCOP, DCON
DVDD33
DCIP, DCIN
NC
Differential Data Clock Output. LVDS clock at the DAC sample rate.
Digital Input and Output Pad Ring Supply Voltage (3.3 V).
Differential Data Clock Input. LVDS clock aligned with input data.
No Connection. Leave these pins floating.
49
SDO
Serial Port Data Output.
ꢀ±
ꢀ1
SDIO
SCLK
Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode).
Serial Port Clock Input.
ꢀ2
CSB
Serial Port Chip Select (Active Low).
ꢀ3
RESET
Chip Reset (Active High).
ꢀ4
ꢀꢀ
FS ADJ
REFIO
AVDD33
AVSS
Full-Scale Current Output Adjust.
Analog Reference Input/Output (1.2 V Nominal).
Analog Supply Voltage (3.3 V).
ꢀ6, ꢀ7, 71, 72
ꢀ8, 61, 64, 67, 7±
Analog Common.
ꢀ9
6±
62, 63
6ꢀ, 66
68
69
IOUT2P
IOUT2N
AUX2P, AUX2N
AUX1N, AUX1P
IOUT1N
IOUT1P
N/A
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are ±s.
Differential Auxiliary DAC Current Output (Channel 2).
Differential Auxiliary DAC Current Output (Channel 1).
Complementary DAC Current Output. Full-scale current is sourced when all data bits are ±s.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Heat Sink Pad
The heat sink pad on the bottom of the package should be soldered to the PCB plane that
carries AVSS.
Rev. A | Page 7 of 36
AD9780/AD9781/AD9783
CVDD18
CVSS
CLKP
CLKN
CVSS
1
2
3
4
5
6
7
8
9
54 FS ADJ
RESET
52 CSB
PIN 1
INDICATOR
53
51 SCLK
50
SDIO
CVDD18
DVSS
DVDD18
D15P
D15N 10
D14P 11
D14N 12
D13P 13
D13N 14
D12P 15
D12N 16
D11P 17
D11N 18
49 SDO
48 DVSS
AD9783
(TOP VIEW)
47
DVDD18
46 D0N
45
D0P
44 D1N
43 D1P
42
D2N
41 D2P
40 D3N
39
38 D4N
D4P
D3P
37
NOTES
1. EXPOSED PAD MUST BE
SOLDERED TO PCB AND
CONNECTED TO AVSS.
Figure 4. AD9783 Pin Configuration
Table 8. AD9783 Pin Function Descriptions
Pin No.
Mnemonic
CVDD18
CVSS
Description
1, 6
2, ꢀ
Clock Supply Voltage (1.8 V).
Clock Supply Return.
3, 4
7, 28, 48
CLKP, CLKN
DVSS
Differential DAC Sampling Clock Input.
Digital Common.
8, 47
DVDD18
Digital Supply Voltage (1.8 V).
9 to 24, 31 to 46
D1ꢀP, D1ꢀN to D±P, D±N LVDS Data Inputs. D1ꢀ is the MSB, D± is the LSB.
2ꢀ, 26
27
29, 3±
49
DCOP, DCON
DVDD33
DCIP, DCIN
SDO
Differential Data Clock Output. LVDS clock at the DAC sample rate.
Digital Input and Output Pad Ring Supply Voltage (3.3 V).
Differential Data Clock Input. LVDS clock aligned with input data.
Serial Port Data Output.
ꢀ±
ꢀ1
SDIO
SCLK
Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode).
Serial Port Clock Input.
ꢀ2
CSB
Serial Port Chip Select (Active Low).
ꢀ3
RESET
Chip Reset (Active High).
ꢀ4
FS ADJ
Full-Scale Current Output Adjust.
ꢀꢀ
REFIO
AVDD33
AVSS
Analog Reference Input/Output (1.2 V Nominal).
Analog Supply Voltage (3.3 V).
Analog Common.
ꢀ6, ꢀ7, 71, 72
ꢀ8, 61, 64, 67, 7±
ꢀ9
6±
62, 63
6ꢀ, 66
68
69
IOUT2P
IOUT2N
AUX2P, AUX2N
AUX1N, AUX1P
IOUT1N
IOUT1P
N/A
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are ±s.
Differential Auxiliary DAC Current Output (Channel 2).
Differential Auxiliary DAC Current Output (Channel 1).
Complementary DAC Current Output. Full-scale current is sourced when all data bits are ±s.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Heat Sink Pad
The heat sink pad on the bottom of the package should be soldered to the PCB plane that
carries AVSS.
Rev. A | Page 8 of 36
AD9780/AD9781/AD9783
TYPICAL PERFORMANCE CHARACTERISTICS
1.5
0.4
0.2
0
1.0
0.5
–0.2
–0.4
–0.6
0
–0.5
–1.0
–0.8
–1.0
–1.2
–1.4
–1.5
–2.0
–2.5
–1.6
0
0
0
16,384
32,768
CODE
49,152
65,535
65,535
65,535
0
0
0
16,384
32,768
CODE
49,152
65,535
65,535
65,535
Figure 5. AD9783 INL, TA = 85°C, FS = 20 mA
Figure 8. AD9783 DNL, TA = 85°C, FS = 20 mA
5
4
3
2
1
0
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1
–2
–3
–1.6
16,384
32,768
CODE
49,152
16,384
32,768
CODE
49,152
Figure 6. AD9783 INL, TA = 25°C, FS = 20 mA
Figure 9. AD9783 DNL, TA = 25°C, FS = 20 mA
5
4
3
2
1
0
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
–2
–3
–1.0
16,384
32,768
CODE
49,152
16,384
32,768
CODE
49,152
Figure 7. AD9783 INL, TA = −40°C, FS = 20 mA
Figure 10. AD9783 DNL, TA = −40°C, FS = 20 mA
Rev. A | Page 9 of 36
AD9780/AD9781/AD9783
0.059
–0.060
–0.179
–0.297
–0.416
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
0
0
0
4096
8192
12,288
16,383
16,383
4096
0
4096
8192
12,288
16,383
CODE
CODE
Figure 11. AD9781 INL, TA = 85°C, FS = 20 mA
Figure 14. AD9781 DNL, TA = 85°C, FS = 20 mA
0.1
0
0.6
0.4
0.2
–0.1
0
–0.2
–0.3
–0.2
–0.4
–0.6
–0.8
–1.0
–0.4
–0.5
0
4096
8192
12,288
16,383
4096
8192
12288
CODE
CODE
Figure 12. AD9781 INL, TA = −40°C, FS = 20 mA
Figure 15. AD9781 DNL, TA = −40°C, FS = 20 mA
0.2
0.2
0.1
0
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.6
0
1024
2048
3072
1024
2048
3072
4096
CODE
CODE
Figure 16. AD9780 INL, TA = 85°C, FS = 20 mA
Figure 13. AD9780 INL, TA = −40°C, FS = 20 mA
Rev. A | Page 1± of 36
AD9780/AD9781/AD9783
100
95
90
85
80
75
70
65
60
55
50
45
40
90
85
80
75
70
65
60
55
50
45
40
250MSPS
+25°C
400MSPS
–40°C
+85°C
500MSPS
0
25
50
75
100 125 150 175 200 225 250
fOUT (MHz)
0
50
100 150 200 250 300 350 400 450 500
fOUT (MHz)
Figure 20. AD9783 SFDR vs. fOUT Over Temperature, at 500 MSPS, FS = 20 mA
Figure 17. AD9783 SFDR vs. fOUT Over fDAC in Baseband and Mix Modes,
FS = 20 mA
100
95
100
95
90
90
250MSPS
85
85
20mA
80
75
70
80
30mA
75
70
65
60
400MSPS
65
60
55
50
45
40
55
50
45
40
10mA
500MSPS
0
50
100 150 200 250 300 350 400 450 500
fOUT (MHz)
0
25
50
75
100 125 150 175 200 225 250
fOUT (MHz)
Figure 21. AD9783 IMD vs. fOUT Over fDAC in Baseband and Mix Modes,
FS = 20 mA
Figure 18. AD9783 SFDR vs. fOUT Over Analog Output, TA = 25°C, at 500 MSPS
100
95
100
95
90
90
10mA
85
85
–3dBFS
80
80
20mA
75
75
70
70
30mA
65
60
55
50
65
60
55
50
45
40
–6dBFS
0dBFS
45
40
0
25
50
75
100 125 150 175 200 225 250
fOUT (MHz)
0
25
50
75
100 125 150 175 200 225 250
fOUT (MHz)
Figure 19. AD9783 SFDR vs. fOUT Over Digital Input Level,
TA = 25°C, at 500 MSPS, FS = 20 mA
Figure 22. AD9783 IMD vs. fOUT Over Analog Output, TA = 25°C, at 500 MSPS
Rev. A | Page 11 of 36
AD9780/AD9781/AD9783
100
–140
–143
–146
–149
–152
–155
–158
–161
–164
–167
–170
95
–6dBFS
90
–3dBFS
85
80
75
70
65
60
250MSPS
0dBFS
55
500MSPS
50
45
40
400MSPS
0
30
60
90
120
150
180
210
240
0
50
100 150 200 250 300 350 400 450 500
fOUT (MHz)
fOUT (MHz)
Figure 23. AD9783 IMD vs. fOUT Over Digital Input Level, TA = 25°C, at
500 MSPS, FS = 20 mA
Figure 26. AD9783 Eight-Tone NSD vs. fOUT Over fDAC Baseband and
Mix Modes, FS = 20 mA
100
95
–140
–143
–146
–149
90
85
+85°C
80
+85°C
–152
–155
75
70
65
60
55
50
45
40
+25°C
+25°C
–40°C
–158
–40°C
–161
–164
–167
–170
0
30
60
90
120
150
180
210
240
0
25
50
75
100 125 150 175 200 225 250
fOUT (MHz)
fOUT (MHz)
Figure 24. AD9783 IMD vs. fOUT Over Temperature, at 500 MSPS, FS = 20 mA
Figure 27. AD9783 One-Tone NSD vs. fOUT Over Temperature, at 500 MSPS,
FS = 20 mA
–140
–143
–146
–140
–143
–146
–149
–152
–155
–149
250MSPS
–152
500MSPS
–155
–158
–158
+85°C
–161
–161
400MSPS
–164
–167
–170
–164
+25°C
–167
–170
–40°C
0
50
100 150 200 250 300 350 400 450 500
fOUT (MHz)
0
25
50
75
100 125 150 175 200 225 250
fOUT (MHz)
Figure 25. AD9783 One-Tone NSD vs. fOUT Over fDAC Baseband and Mix Modes,
FS = 20 mA
Figure 28. AD9783 Eight-Tone NSD vs. fOUT Over Temperature, at 500 MSPS,
FS = 20 mA
Rev. A | Page 12 of 36
AD9780/AD9781/AD9783
–50
–55
–60
–65
–70
–75
–80
–85
–90
–50
–55
–60
–65
–70
–75
–80
–85
–90
491.52MSPS
0dB
245.76MSPS
–3dB
0
100
200
300
400
500
0
100
200
300
400
500
fOUT (MHz)
fOUT (MHz)
Figure 29. AD9783 ACLR for First Adjacent Band One-Carrier W-CDMA
Baseband and Mix Modes, FS = 20 mA
Figure 32. AD9783 ACLR for First Adjacent Channel Two-Carrier W-CDMA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
–50
–55
–60
–65
–70
–50
–55
–60
–65
–70
–75
–80
–85
–90
–3dB
245.76MSPS
491.52MSPS
–75
–80
–85
–90
0dB
200
0
100
200
300
400
500
0
100
300
400
500
fOUT (MHz)
fOUT (MHz)
Figure 30. AD9783 ACLR for Second Adjacent Band One-Carrier W-CDMA
Baseband and Mix Modes, FS = 20 mA
Figure 33. AD9783 ACLR for Second Adjacent Channel Two-Carrier W-CDMA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
–50
–55
–60
–65
–50
–55
–60
–65
245.76MSPS
491.52MSPS
–70
–75
–80
–85
–90
–70
–75
–80
–85
–90
–3dB
0dB
0
100
200
300
400
500
0
100
200
300
400
500
fOUT (MHz)
fOUT (MHz)
Figure 31. AD9783 ACLR for Third Adjacent Band One-Carrier W-CDMA
Baseband and Mix Modes, FS = 20 mA
Figure 34. AD9783 ACLR for Third Adjacent Channel Two-Carrier W-CDMA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
Rev. A | Page 13 of 36
AD9780/AD9781/AD9783
–50
1.0
0.5
–55
0
–60
–0.5
0dB
–1.0
–1.5
–2.0
NORMAL MODE
–65
–70
–3dB
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–75
–80
–85
–90
MIX MODE
0
100
200
300
400
500
0
60
120 180 240 300 360 420 480 540 600
fOUT (MHz)
fOUT (MHz)
Figure 35. AD9783 ACLR for First Adjacent Channel Four-Carrier W-CDMA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
Figure 38. Nominal Power in the Fundamental, FS = 20 mA, at 500 MSPS,
FS = 20 mA
0.8
0.6
–50
–55
–60
0.4
0.2
–3dB
–65
–70
–75
–80
–85
–90
0
0dB
–0.2
–0.4
–0.6
–0.8
0
4096
8192
12,288
16,383
0
100
200
300
400
500
fOUT (MHz)
CODE
Figure 39. AD9781 INL, FS = 20 mA
Figure 36. AD9783 ACLR for Second Adjacent Channel Four-Carrier W-CDMA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
0.1
0
–50
–55
–60
–0.1
–65
–70
–75
–80
–85
–90
–3dB
–0.2
–0.3
0dB
–0.4
–0.5
0
4096
8192
12,288
16,383
0
100
200
300
400
500
CODE
fOUT (MHz)
Figure 40. AD9781 DNL, FS = 20 mA
Figure 37. AD9783 ACLR for Third Adjacent Channel Four-Carrier W-CDMA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
Rev. A | Page 14 of 36
AD9780/AD9781/AD9783
100
95
90
85
80
75
70
65
60
55
50
45
40
–50
–55
–60
–65
–70
–75
–80
–85
–90
FIRST
ADJACENT
CHANNEL
THIRD
ADJACENT
SECOND
CHANNEL
ADJACENT
CHANNEL
0
50
100 150 200 250 300 350 400 450 500
fOUT (MHz)
0
100
200
300
400
500
fOUT (MHz)
Figure 44. AD9781 ACLR for One-Carrier W-CDMA Baseband and Mix Modes,
at 491.52 MSPS, FS = 20 mA
Figure 41. AD9781 SFDR vs. fOUT in Baseband and Mix Modes, at 500 MSPS,
FS = 20 mA
0.2
100
IMD @ 500MSPS
95
0.1
0
90
85
80
75
70
65
60
55
50
45
40
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
0
0
60
120 180 240 300 360 420 480 540 600
fOUT (MHz)
1024
2048
3072
4096
CODE
Figure 45. AD9780 INL, FS = 20 mA
Figure 42. AD9781 IMD vs. fOUT in Baseband and Mix Modes, at 500 MSPS,
FS = 20 mA
0.04
0.02
–140
–142
–144
–146
–148
0
1-TONE
–150
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–152
–154
–156
8-TONE
–158
–160
–162
–164
–166
–168
–170
0
1024
2048
3072
4096
0
50
100 150 200 250 300 350 400 450 500
fOUT (MHz)
CODE
Figure 46. AD9780 DNL, FS = 20 mA
Figure 43. AD9781 One-Tone, Eight-Tone NSD vs. fOUT in Baseband and Mix
Modes, at 500 MSPS, FS = 20 mA
Rev. A | Page 1ꢀ of 36
AD9780/AD9781/AD9783
100
95
90
85
80
75
70
65
60
55
50
45
40
–140
–142
–144
–146
–148
–150
–152
–154
–156
–158
–160
–162
–164
–166
–168
–170
1-TONE
8-TONE
0
50
100 150 200 250 300 350 400 450 500
fOUT (MHz)
0
50
100 150 200 250 300 350 400 450 500
fOUT (MHz)
Figure 47. AD9780 SFDR vs. fOUT in Baseband and Mix Modes, at 500 MSPS,
FS = 20 mA
Figure 49. AD9780 One-Tone, Eight-Tone NSD vs. fOUT in Baseband and Mix
Modes, at 500 MSPS, FS = 20 mA
100
95
90
85
80
75
70
65
60
55
50
45
40
–50
–55
–60
FIRST
–65
–70
–75
–80
–85
–90
ADJACENT
CHANNEL
SECOND
THIRD
ADJACENT
CHANNEL
ADJACENT
CHANNEL
35
30
0
50
100 150 200 250 300 350 400 450 500
fOUT (MHz)
0
100
200
300
400
500
fOUT (MHz)
Figure 48. AD9780 IMD vs. fOUT in Baseband and Mix Modes, at 500 MSPS,
FS = 20 mA
Figure 50. AD9780 ACLR for One-Carrier W-CDMA Baseband and Mix Modes,
at 491.52 MSPS, FS = 20 mA
Rev. A | Page 16 of 36
AD9780/AD9781/AD9783
TERMINOLOGY
Linearity Error or Integral Nonlinearity (INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero scale to full scale.
Power Supply Rejection
Power supply rejection is the maximum change in the full-scale
output as the supplies are varied from minimum to maximum
specified voltages.
Differential Nonlinearity (DNL)
Settling Time
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the peak amplitude
of the output signal and the peak spurious signal between dc
and the frequency equal to half the input data rate.
Offset Error
Offset error is the deviation of the output current from the ideal
of zero. For IOUTA, 0 mA output is expected when the inputs are
all 0s. For IOUTB, 0 mA output is expected when all inputs are
set to 1s.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the difference between
the output when all inputs are set to 1s and the output when all
inputs are set to 0s.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Output Compliance Range
Output compliance range is the range of allowable voltage at
the output of a current-output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in dBc between the measured power within a
channel relative to its adjacent channel.
Complex Image Rejection
Temperature Drift
Temperature drift is specified as the maximum change from
the ambient (25°C) value to the value at either TMIN or TMAX
For offset and gain drift, the drift is reported in ppm of full-
scale range (FSR) per degree Celsius. For reference drift, the
drift is reported in ppm per degree Celsius.
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images usually waste
transmitter power and system bandwidth. By placing the real
part of a second complex modulator in series with the first
complex modulator, either the upper or lower frequency image
near the second IF can be rejected.
.
Rev. A | Page 17 of 36
AD9780/AD9781/AD9783
THEORY OF OPERATION
The AD9780/AD9781/AD9783 have a combination of features
that make them very attractive for wired and wireless commu-
nications systems. The dual DAC architecture facilitates easy
interface to common quadrature modulators when designing
single sideband transmitters. In addition, the speed and
performance of the devices allow wider bandwidths and more
carriers to be synthesized than in previously available products.
The Phase 1 instruction byte defines whether the upcoming
data transfer is a read or write, the number of bytes in the data
transfer, and a reference register address for the first byte of the
data transfer. A logic high on the CSB pin followed by a logic
low resets the SPI port to its initial state and defines the start of
the instruction cycle. From this point, the next eight rising
SCLK edges define the eight bits of the instruction byte for the
current communication cycle.
All features and options are software programmable through
the SPI port.
The remaining SCLK edges are for Phase 2 of the communication
cycle, which is the data transfer between the serial port controller
and the system controller. Phase 2 can be a transfer of one, two,
three, or four data bytes as determined by the instruction byte.
Using multibyte transfers is usually preferred, although single-
byte data transfers are useful to reduce CPU overhead or when
only a single register access is required.
SERIAL PERIPHERAL INTERFACE
SDO
AD9783
SPI
SDIO
SCLK
CSB
PORT
All serial port data is transferred to and from the device in
synchronization with the SCLK pin. Input data is always latched
on the rising edge of SCLK, whereas output data is always valid
after the falling edge of SCLK. Register contents change imme-
diately upon writing to the last bit of each transfer byte.
Figure 51. SPI Port
The serial peripheral interface (SPI) port is a flexible, synchron-
ous serial communications port allowing easy interface to many
industry-standard microcontrollers and microprocessors. The
port is compatible with most synchronous transfer formats,
including both the Motorola SPI and Intel® SSR protocols.
Anytime synchronization is lost, the device has the ability to
asynchronously terminate an I/O operation whenever the CSB pin
is taken to logic high. Any unwritten register content data is lost
if the I/O operation is aborted. Taking CSB low then resets the
serial port controller and restarts the communication cycle.
The interface allows read and write access to all registers that
configure the AD9780/AD9781/AD9783. Single or multiple
byte transfers are supported as well as MSB-first or LSB-first
transfer formats. Serial data input/output can be accomplished
through a single bidirectional pin (SDIO) or through two
unidirectional pins (SDIO/SDO).
INSTRUCTION BYTE
The instruction byte contains the information shown in Table 9.
Table 9.
MSB
The serial port configuration is controlled by Register 0x00,
Bits[7:6]. It is important to note that any change made to the
serial port configuration occurs immediately upon writing to
the last bit of this byte. Therefore, it is possible with a multibyte
transfer to write to this register and change the configuration in
the middle of a communication cycle. Care must be taken to
compensate for the new configuration within the remaining
bytes of the current communication cycle.
LSB
B0
B7
B6
B5
B4
B3
B2
B1
R/W
N1
N±
A4
A3
A2
A1
A±
Bit 7, R/W, determines whether a read or a write data transfer
occurs after the instruction byte write. Logic 1 indicates a read
operation. Logic 0 indicates a write operation.
Bits[6:5], N1 and N0, determine the number of bytes to be
transferred during the data transfer cycle. The bits decode as
shown in Table 10.
Use of a single-byte transfer when changing the serial port
configuration is recommended to prevent unexpected device
behavior.
GENERAL OPERATION OF THE SERIAL INTERFACE
Table 10. Byte Transfer Count
N1
N0
Description
There are two phases to any communication cycle with the
AD9780/AD9781/AD9783: Phase 1 and Phase 2. Phase 1 is
the instruction cycle, which writes an instruction byte into
the device. This byte provides the serial port controller with
information regarding Phase 2 of the communication cycle:
the data transfer cycle.
±
±
1
1
±
1
±
1
Transfer one byte
Transfer two bytes
Transfer three bytes
Transfer four bytes
Rev. A | Page 18 of 36
AD9780/AD9781/AD9783
Serial Port Data I/O (SDIO)
Bits[4:0], A4, A3, A2, A1, and A0, determine which register is
accessed during the data transfer of the communication cycle.
For multibyte transfers, this address is a starting or ending
address depending on the current data transfer mode. For
MSB-first format, the specified address is an ending address
or the most significant address in the current cycle. Remaining
register addresses for multiple byte data transfers are generated
internally by the serial port controller by decrementing from
the specified address. For LSB-first format, the specified address
is a beginning address or the least significant address in the
current cycle. Remaining register addresses for multiple byte
data transfers are generated internally by the serial port
controller by incrementing from the specified address.
Data is always written into the device on this pin. However,
SDIO can also function as a bidirectional data output line. The
configuration of this pin is controlled by Register 0x00, Bit 7.
The default is Logic 0, which configures the SDIO pin as
unidirectional.
Serial Port Data Output (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. The configuration of this
pin is controlled by Register 0x00, Bit 7. If this bit is set to a
Logic 1, the SDO pin does not output data and is set to a high
impedance state.
MSB/LSB TRANSFERS
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by Register 0x00, Bit 6.
The default is Logic 0, which is MSB-first format.
CSB
SCLK
SDIO
SDO
When using MSB-first format (LSBFIRST = 0), the instruction
and data bit must be written from MSB to LSB. Multibyte data
transfers in MSB-first format start with an instruction byte that
includes the register address of the most significant data byte.
Subsequent data bytes are loaded into sequentially lower address
locations. In MSB-first mode, the serial port internal address
generator decrements for each byte of the multibyte data
transfer.
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6N D5N
D30 D20 D10 D00
D30 D20 D10 D00
D7 D6N D5N
Figure 52. Serial Register Interface Timing Diagram, MSB First
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
When using LSB-first format (LSBFIRST = 1), the instruction
and data bit must be written from LSB to MSB. Multibyte data
transfers in LSB-first format start with an instruction byte that
includes the register address of the least significant data byte.
Subsequent data bytes are loaded into sequentially higher
address locations. In LSB-first mode, the serial port internal
address generator increments for each byte of the multibyte
data transfer.
A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2
D4 D5 D6 D7
N N N
0
0
0
N
N
D0 D1 D2
D4 D5 D6 D7
N N N
0
0
0
Figure 53. Serial Register Interface Timing Diagram, LSB First
Use of a single-byte transfer when changing the serial port data
format is recommended to prevent unexpected device behavior.
–1
tS
fSCLK
CSB
SERIAL INTERFACE PORT PIN DESCRIPTIONS
tPWH
tPWL
Chip Select Bar (CSB)
SCLK
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communication lines. CSB must stay low during the entire
communication cycle. Incomplete data transfers are aborted
anytime the CSB pin goes high. SDO and SDIO pins go to a
high impedance state when this input is high.
tDS
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
SDIO
Figure 54. Timing Diagram for SPI Write Register
CSB
Serial Clock (SCLK)
The serial clock pin is used to synchronize data to and from the
device and to run the internal state machines. The maximum
frequency of SCLK is 40 MHz. All data input is registered on
the rising edge of SCLK. All data is driven out on the falling
edge of SCLK.
SCLK
tDV
SDIO
SDO
DATA BIT N
DATA BIT N – 1
Figure 55. Timing Diagram for SPI Read Register
Rev. A | Page 19 of 36
AD9780/AD9781/AD9783
SPI REGISTER MAP
Table 11.
Register Name
Addr Default Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI Control
0x00 0x00
0x02 0x00
0x03 0x00
0x04 0x00
0x05 0x00
0x06 0x00
0x0A 0x00
0x0B 0xF9
0x0C 0x01
0x0D 0x00
SDIO_DIR LSBFIRST
DATA
RESET
Data Control
Power-Down
Setup and Hold
Timing Adjust
Seek
INVDCO
PD_DCO
PD_INPT
PD_AUX2 PD_AUX1 PD_BIAS PD_CLK
PD_DAC2
PD_DAC1
SET[3:0]
HLD[3:0]
SAMP_DLY[4:0]
LVDS low
DAC1MIX[1:0]
DAC1FSC[7:0]
LVDS high SEEK
DAC2MIX[1:0]
Mix Mode
DAC1 FSC
DAC1 FSC MSBs
AUXDAC1
DAC1FSC[9:8]
AUXDAC1[9:8]
DAC2FSC[9:8]
AUXDAC2[9:8]
AUXDAC1[7:0]
DAC2FSC[7:0]
AUXDAC2[7:0]
AUXDAC1 MSB
DAC2 FSC
0x0E
0x0F
0x00
0xF9
AUX1SGN AUX1DIR
AUX2SGN AUX2DIR
DAC2 FSC MSBs
AUXDAC2
0x10 0x01
0x11 0x00
0x12 0x00
0x1A 0x00
AUXDAC2 MSB
BIST Control
BISTEN
BISTRD
BISTCLR
BIST Result 1 Low 0x1B 0x00
BIST Result 1 High 0x1C 0x00
BIST Result 2 Low 0x1D 0x00
BISTRES1[7:0]
BISTRES1[15:8]
BISTRES2[7:0]
BISTRES2[15:8]
BIST Result 2 High 0x1E
Hardware Version 0x1F
0x00
N/A
VERSION[3:0]
DEVICE[3:0]
Rev. A | Page 20 of 36
AD9780/AD9781/AD9783
SPI REGISTER DESCRIPTIONS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 12.
Register
Address Bit
Name
Function
SPI Control
±x±±
7
SDIO_DIR
±, operate SPI in 4-wire mode. The SDIO pin operates as an input only pin.
1, operate SPI in 3-wire mode. The SDIO pin operates as a bidirectional data line.
±, MSB first per SPI standard.
6
LSBFIRST
1, LSB first per SPI standard.
Only change LSB/MSB order in single-byte instructions to avoid erratic behavior
due to bit order errors.
ꢀ
7
RESET
DATA
±, execute software reset of SPI and controllers, reload default register values
except Register ±x±±.
1, set software reset, write ± on the next (or any following) cycle to release the reset.
Data Control
Power-Down
±x±2
±x±3
±, DAC input data is twos complement binary format.
1, DAC input data is unsigned binary format.
1, inverts the data clock output. Used for adjusting timing of input data.
1, power down data clock output driver circuit.
1, power down input.
4
INVDCO
PD_DCO
PD_INPT
PD_AUX2
PD_AUX1
PD_BIAS
PD_CLK
7
6
ꢀ
1, power down AUX2 DAC
4
1, power down AUX1 DAC.
3
1, power down voltage reference bias circuit.
1, power down DAC clock input circuit.
1, power down DAC2.
2
1
PD_DAC2
PD_DAC1
SET[3:±]
±
1, power down DAC1.
Setup and Hold
±x±4
7:4
3:±
4:±
2
4-bit value used to determine input data setup timing.
4-bit value used to determine input data hold timing.
HLD[3:±]
Timing Adjust
Seek
±x±ꢀ
±x±6
SAMP_DLY[4:±] ꢀ-bit value used to optimally position input data relative to internal sampling clock.
LVDS low
LVDS high
SEEK
One of the LVDS inputs is above the input voltage limits of the IEEE reduced link
specification.
1
One of the LVDS inputs is below the input voltage limits of the IEEE reduced link
specification.
±
Indicator bit used with LVDS_SET and LVDS_HLD to determine input data timing
margin.
Mix Mode
±x±A
3:2
DAC1MIX[1:±]
±±, selects normal mode, DAC1.
±1, selects return-to-zero mode, DAC1.
1±, selects return-to-zero mode, DAC1.
11, selects mix mode, DAC1.
1:±
DAC2MIX[1:±]
DAC1FSC[9:±]
±±, selects normal mode, DAC2.
±1, selects return-to-zero mode, DAC2.
1±, selects return-to-zero mode, DAC2.
11, selects mix mode, DAC2.
DAC1 FSC
±x±B
±x±C
7:±
1:±
DAC1 full-scale 1±-bit adjustment word.
±x3FF, sets DAC full-scale output current to the maximum value of 31.66 mA.
±x2±±, sets DAC full-scale output current to the nominal value of 2±.± mA.
±x±±±, sets DAC full-scale output current to the minimum value of 8.66 mA.
Rev. A | Page 21 of 36
AD9780/AD9781/AD9783
Register
Address Bit
Name
Function
AUXDAC1
±x±D
±x±E
7:±
1:±
AUXDAC1[9:±]
AUXDAC1 output current adjustment word.
±x3FF, sets AUXDAC1 output current to 2.± mA.
±x2±±, sets AUXDAC1 output current to 1.± mA.
±x±±±, sets AUXDAC1 output current to ±.± mA.
±, AUX1P output pin is active.
±x±E
7
6
AUX1SGN
1, AUX1N output pin is active.
AUX1DIR
±, configures AUXDAC1 output to source current.
1, configures AUXDAC1 output to sink current.
DAC2 full-scale 1±-bit adjustment word.
DAC2 FSC
AUXDAC2
±x±F
±x1±
7:±
1:±
DAC2FSC[9:±]
±x3FF, sets DAC full-scale output current to the maximum value of 31.66 mA.
±x2±±, sets DAC full-scale output current to the nominal value of 2±.± mA.
±x±±±, sets DAC full-scale output current to the minimum value of 8.66 mA.
AUXDAC2 output current adjustment word.
±x3FF, sets AUXDAC2 output current to 2.± mA.
±x2±±, sets AUXDAC2 output current to 1.± mA.
±x±±±, sets AUXDAC2 output current to ±.± mA.
±, AUX2P output pin is active.
±x11
±x12
7:±
1:±
AUXDAC2[9:±]
±x12
±x1A
7
6
AUX2SGN
AUX2DIR
1, AUX2N output pin is active.
±, configures AUXDAC2 output to source current.
1, configures AUXDAC2 output to sink current.
1, enables and starts built-in self-test.
BIST Control
7
BISTEN
BISTRD
BISTCLR
6
1, transfers BIST result registers to SPI for readback.
1, reset BIST logic and clear BIST result registers.
ꢀ
BIST Result 1
BIST Result 2
±x1B
±x1C
±x1D
±x1E
7:±
7:±
7:±
7:±
7:4
3:±
BISTRES1[1ꢀ:±] 16-bit result generated by BIST 1.
BISTRES2[1ꢀ:±] 16-bit result generated by BIST 2.
Hardware Version ±x1F
VERSION[3:±]
DEVICE[3:±]
Read only register; indicates the version of the chip.
Read only register; indicates the device type.
Rev. A | Page 22 of 36
AD9780/AD9781/AD9783
In pin mode, the four SPI port pins take on secondary
functions, as shown in Table 13.
SPI PORT, RESET, AND PIN MODE
In general, when the AD9780/AD9781/AD9783 are powered
up, an active high pulse applied to the RESET pin should follow.
This ensures the default state of all control register bits. In
addition, once the RESET pin goes low, the SPI port can be
activated; thus, CSB should be held high.
Table 13. SPI Pin Functions (Pin Mode)
Pin
Name
Pin Mode Function
SDIO
DATA (Register ±x±2, Bit 7), bit value (1/±) equals pin
state (high/low).
For applications without a controller, the AD9780/AD9781/
AD9783 also supports pin mode operation, which allows some
functional options to be pin selected without the use of the SPI
port. Pin mode is enabled anytime the RESET pin is held high.
CSB
Enable mix mode. If CSB is high, Register ±x±A is set
to ±x±ꢀ, putting both DAC1 and DAC2 into mix mode.
SDO
Enable full power-down. If SDO is high, Register ±x±3
is set to ±xFF.
Rev. A | Page 23 of 36
AD9780/AD9781/AD9783
PARALLEL DATA PORT INTERFACE
The parallel port data interface consists of up to 18 differential
LVDS signals, DCO, DCI, and up to 16 data lines (D[15:0]), as
shown in Figure 56. DCO is the output clock generated by the
AD9780/AD9781/AD9783 that is used to clock out the data
from the digital data engine. The data lines transmit the multip-
lexed I and Q data words for the I and Q DACs, respectively.
DCI provides timing information about the parallel data and
signals the I/Q status of the data.
OPTIMIZING THE PARALLEL PORT TIMING
Before outlining the procedure for determining the delay for
SMP (that is, the positioning of DSS with respect to the data
signals), it is worthwhile to describe the simplified block
diagram of the digital data port. As can be seen in Figure 57, the
data signals are sampled on the rising and falling edges of DSS.
From there, the data is demultiplexed and retimed before being
sent to the DACs.
As diagrammed in Figure 56, the incoming LVDS data is
latched by an internally generated clock referred to as the data
sampling signal (DSS). DSS is a delayed version of the main
DAC clock signal, CLKP/CLKN. Optimal positioning of the
rising and falling edges of DSS with respect to the incoming
data signals results in the most robust transmission of the DAC
data. Positioning the edges of DSS with respect to the data
signals is achieved by selecting the value of a programmable
delay element, SMP. A procedure for determining the optimal
value of SMP is given in the Optimizing the Parallel Port
Timing section.
The clock input signal provides timing information about the
parallel data, as well as indicating the destination (that is, I DAC
or Q DAC) of the data. A delayed version of DCI is generated
by a delay element, SET, and is referred to as DDCI. DDCI is
sampled by a delayed version of the DSS signal, labeled as DDSS
in Figure 56. DDSS is simply DSS delayed by a period of time,
HLD. The pair of delays, SET and HLD, allows accurate timing
information to be extracted from the clock input. Increasing the
delay of the HLD block results in the clock input being sampled
later in its cycle. Increasing the delay of the SET block results in
the clock input being sampled earlier in its cycle. The result of
this sampling is stored and can be queried by reading the SEEK
bit. Because DSS and the clock input signal are the same
frequency, the SEEK bit should be a constant value. By varying
the SET and HLD delay blocks and seeing the effect on the
SEEK bit, the setup-and-hold timing of DSS with respect to
clock input (and, hence, data) can be measured.
In addition to properly positioning the DSS edges, maximizing
the opening of the eye in the clock input (DCIP/DCIN) and
data signals improves the reliability of the data port interface.
The two sources of degradation that reduce the eye in the clock
input and data signals are the jitter on these signals and the
skew between them. Therefore, it is recommended that the clock
input signals be generated in the same manner as the data
signals with the same output driver and data line routing. In
other words, it should be implemented as a 17th data line with
an alternating (010101 …) bit sequence.
I0
Q0
I1
Q1
I2
Q2
DATA
DCIP/DCIN
tHLD0
tHLD0
D15:D0
I DAC
DSS
FF
RETIMING
AND
DEMUX
FF
SAMPLE 1
SAMPLE 2
SAMPLE 3
SAMPLE 4
SAMPLE 5
SAMPLE 6
Q DAC
Figure 57. Timing Diagram of Parallel Interface
The incremental units of SET, HLD, and SMP are in units of
real time, not fractions of a clock cycle. The nominal step size
for SET and HLD is 80 ps. The nominal step size for SMP is
160 ps. Note that the value of SMP refers to Register 0x05,
Bits[4:0], SET refers to Register 0x04, Bits[7:4], and HLD refers
to Register 0x04, Bits[3:0].
DCIP/DCIN
DDCI
SET_DLY
HLD_DLY
SEEK
FF
DDSS
CLK
DSS
CLOCK
DISTRIBUTION
SMP_DLY
DCOP/DCON
A procedure for configuring the device to ensure valid sampling
of the data signals follows. Generally speaking, the procedure
begins by building an array of setup-and-hold values as the sample
delay is swept through a range of values. Based on this infor-
mation, a value of SMP is programmed to establish an optimal
sampling point. This new sampling point is then double-checked
to verify that it is optimally set.
Figure 56. Digital Data Port Block Diagram
Rev. A | Page 24 of 36
AD9780/AD9781/AD9783
Table 14 shows example arrays taken at DAC sample rates of
200 MHz, 400 MHz, and 600 MHz. It should be noted that the
delay from the DCO input to the DCI output of the data source
has a profound effect on when the SEEK bit toggles over the
range of SMP values. Therefore, the tables generated in any
particular system do not necessarily match the example timing
data arrays in Table 14.
Building the Array
The following procedure is used to build the array:
1. Set the values of SMP, SET, and HLD to 0. Read and record
the value of the SEEK bit.
2. With SMP and SET set to 0, increment the HLD value until
the SEEK bit toggles, and then record the HLD value. This
measures the hold time as shown in Figure 57.
As may be seen in Table 14, at 600 MHz the device has only two
working SMP settings. There is no way to monitor timing
margin in real time, so the output must be interrupted to check
or correct timing errors. The device should therefore not be
clocked above 500 MHz in applications where 100% up time is a
requirement.
3. With SMP and HLD set to 0, increment the SET value until
the SEEK bit toggles, and then record the SET value. This
measures the setup time as shown in Figure 57.
4. Set the value of SET and HLD to 0. Increment the value of
SMP and record the value of the SEEK bit.
5. Increment HLD until the SEEK bit toggles, and then record
the HLD value. Set HLD to 0 and increment SET until the
SEEK bit toggles, and then record the SET value.
6. Repeat Step 4 and Step 5 until the procedure has been
completed for SMP values from 0 to 31.
Determining the SMP Value
Once the timing data array has been built, the value of SMP can
be determined using the following procedure:
1. Look for the SMP value that corresponds to the 0-to-1
transition of the SEEK bit in the table. In the 600 MHz case
from Table 14, this occurs for an SMP value of 6.
2. Look for the SMP value that corresponds to the 1-to-0
transition of the SEEK bit in the table. In the 600 MHz case
from Table 14, this occurs for an SMP value of 11.
3. The same two values found in Step 1 and Step 2 indicate
the valid sampling window. In the 500 MHz case, this
occurs for an SMP value of 11.
Note that while building the table, a value for either SET or
HLD may not be found to make the SEEK bit toggle. In this
case, assume a value of 15.
Table 14. Timing Data Arrays
fDACCLK = 200 MHz
fDACCLK = 400 MHz
fDACCLK = 600 MHz
SMP SEEK SET HLD SEEK SET HLD SEEK SET HLD
±
±
±
±
±
±
±
±
±
±
±
±
±
±
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
±
±
±
±
6
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
13
11
9
±
±
±
±
±
±
±
1
1
1
1
1
1
1
±
±
±
±
±
±
±
±
±
1
1
1
1
1
1
1
1
1
2
13
11
9
±
±
±
±
±
±
1
1
1
1
1
±
±
±
±
±
±
1
1
1
1
1
±
±
±
±
±
±
1
1
1
1
±
2
3
ꢀ
8
1±
1
2
4
7
9
1
2
4
6
9
11
1
3
ꢀ
7
9
1
2
4
7
9
1±
1
1
1
1
11
9
7
ꢀ
2
1
9
7
4
2
1
1±
8
7
4
2
±
8
7
ꢀ
2
1
1±
8
6
4
2
±
8
8
8
8
1
8
4
4. The optimal SMP value in the valid sampling window is
where the following two conditions are true: SET < HLD
and |HLD − SET| is the smallest value.
2
1±
12
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1
6
3
8
7
4
1±
12
14
1
4
ꢀ
2
In the 600 MHz case, the optimal SMP value is 7.
6
1
7
13
11
9
After programming the calculated value of SMP (referred to as
SMPOPTIMAL), the configuration should be tested to verify that
there is sufficient timing margin. This can be accomplished by
ensuring that the SEEK bit reads back as a 1 for SMP values
equal to SMPOPTIMAL + 1 and SMPOPTIMAL − 1. Also, it should be
noted that the sum of SET and HLD should be a minimum of 8.
If the sum is lower than this, you should check for excessive jitter
on the clock input line and check that the frequency of the clock
input does not exceed the data sheet maximum of 500 MHz (or
1000 Mbps).
8
7
3
9
ꢀ
4
1±
11
12
13
14
1ꢀ
16
17
18
19
2±
21
22
23
24
2ꢀ
26
27
28
29
3±
31
3
6
7
1
8
ꢀ
±
1±
12
±
3
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
13
11
9
1
4
1ꢀ
13
11
9
6
2
8
4
1±
12
13
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1ꢀ
1
6
7
7
As mentioned previously, low jitter and skew between the input
data bits and DCI are critical for reliable operation at the maxi-
mum input data rates. Figure 58 shows the eye diagram for the
input data signals that were used to collect the data in Table 14.
9
ꢀ
11
13
1ꢀ
2
3
1
±
7
11
9
ꢀ
4
3
6
7
1
8
ꢀ
±
9
3
1ꢀ
1ꢀ
1ꢀ
1ꢀ
11
11
11
11
2
1
2
1
2
1
2
Rev. A | Page 2ꢀ of 36
AD9780/AD9781/AD9783
coupled, as described in this section. Alternatively, it can be
transformer-coupled and clamped, as shown in Figure 60.
0.1µF
50Ω
TTL OR CMOS
CLK INPUT
CLKP
V1: 296mV
CLKN
V2: –228mV
1
50Ω
ΔV: –524mV
BAV99ZXCT
HIGH SPEED
DUAL DIODE
V
= 400mV
CM
Figure 60. TTL or CMOS DAC CLK Drive Circuit
A simple bias network for generating the 400 mV common-
mode voltage is shown in Figure 61. It is important to use
CVDD18 and CGND for the clock bias circuit. Any noise or
other signal coupled onto the clock is multiplied by the DAC
digital input signal and can degrade the DAC’s performance.
CH1 100mV
125ps/DIV 2.12ns
A CH1
58mV
20GSPS IT 2.5ps/PT
Figure 58. Eye Diagram of Data Source Used in Building the 600 MHz Timing
Data Array of Table 14
Over temperature, the valid sampling window shifts. Therefore,
when attempting operation of the device over 500 MHz, the
timing must be optimized again whenever the device undergoes
a temperature change of more than 20oC. Another consideration
in the timing of the digital data port is the propagation delay
variation from the clock output (DCOP/DCON) to the clock
input. If this varies significantly over time (more than 25% of
SET or HLD) due to temperature changes or other effects,
repeat this timing calibration procedure.
V
= 400mV
CM
CVDD18
1kΩ
1nF
CGND
0.1µF
1nF
287Ω
Figure 61. DAC CLK VCM Generator Circuit
FULL-SCALE CURRENT GENERATION
Internal Reference
At sample rates of ≤400 MSPS, the interface timing margin is
sufficient to allow for a simplified procedure. In this case, the
SEEK bit can be recorded as SMP is swept through the range
from 0 to 31. The center of the first valid sampling window can
then be chosen as the optimal value of SMP. Using the 400 MHz
case from Table 14 as an example, the first valid sampling
window occurs for SMP values of 7 to 13. The center of this
window is 10, so 10 can be used as the optimal SMP value.
Full-scale current on the I DAC and Q DAC can be set from
8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is
used to set up a current in an external resistor connected to
FS ADJ (Pin 54). A simplified block diagram of the reference
circuitry is shown in Figure 62. The recommended value for
the external resistor is 10 kΩ, which sets up an IREFERENCE in the
resistor of 120 μA, which in turn provides a DAC output full-
scale current of 20 mA. Because the gain error is a linear function
of this resistor, a high precision resistor improves gain matching
to the internal matching specification of the devices. Internal
current mirrors provide a current-gain scaling, where I DAC or
Q DAC gain is a 10-bit word in the SPI port register. The default
value for the DAC gain registers gives a full-scale current output
(IFS) of approximately 20 mA, where IFS is equal to
DRIVING THE CLK INPUT
The CLK input requires a low jitter differential drive signal. It is
a PMOS input differential pair powered from the 1.8 V supply;
therefore, it is important to maintain the specified 400 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 1 V p-p about the 400 mV common-mode
voltage. While these input levels are not directly LVDS-compatible,
CLK can be driven by an offset ac-coupled LVDS signal, as
shown in Figure 59.
I
FS = (86.6 + (0.220 × DAC gain)) × 1000/R
AD9783
0.1µF
I DAC GAIN
LVDS_P_IN
CLKP
1.2V BAND GAP
I DAC
50Ω
50Ω
REFIO
DAC FULL-SCALE
REFERENCE CURRENT
CURRENT
SCALING
V
= 400mV
CM
0.1µF
FS ADJ
Q DAC
10kΩ
LVDS_N_IN
CLKN
Q DAC GAIN
0.1µF
Figure 59. LVDS DAC CLK Drive Circuit
Figure 62. Reference Circuitry
If a clean sine clock is available, it can be transformer-coupled
to CLKP and CLKN as shown in Figure 60. Use of a CMOS or
TTL clock is also acceptable for lower sample rates. It can be
routed through a CMOS-to-LVDS translator, and then ac-
Rev. A | Page 26 of 36
AD9780/AD9781/AD9783
35
30
25
20
15
10
5
ANALOG MODES OF OPERATION
The AD9780/AD9781/AD9783 use a proprietary quad-switch
architecture that lowers the distortion of the DAC by eliminating a
code-dependent glitch that occurs with conventional dual-switch
architectures. This architecture eliminates the code-dependent
glitches, but creates a constant glitch at a rate of 2 × fDAC. For
communications systems and other applications requiring good
frequency domain performance from the DAC, this is seldom
problematic.
The quad-switch architecture also supports two additional
modes of operation: mix mode and return-to-zero mode. The
waveforms of these two modes are shown in Figure 64. In mix
mode, the output is inverted every other half clock cycle. This
effectively chops the DAC output at the sample rate. This chop-
ping has the effect of frequency shifting the sinc roll-off from dc
to fDAC. Additionally, there is a second subtle effect on the output
spectrum. The shifted spectrum is also shaped by a second sinc
function with a first null at 2 × fDAC. The reason for this shaping
is that the data is not continuously varying at twice the clock
rate, but is simply repeated.
0
256
512
768
1024
DAC GAIN CODE
Figure 63. IFS vs. DAC Gain Code
DAC TRANSFER FUNCTION
Each DAC output of the AD9780/AD9781/AD9783 drives two
complementary current outputs, IOUTP and IOUTN. IOUTP provides
a near IFS when all bits are high. For example,
DAC CODE = 2N − 1
In return-to-zero mode, the output is set to midscale every
other half clock cycle. The output is similar to the DAC output
in normal mode except that the output pulses are half the width
and half the area. Because the output pulses have half the width,
the sinc function is scaled in frequency by two and has a first
null at 2 × fDAC. Because the area of the pulses is half that of the
pulses in normal mode, the output power is half the normal
mode output power.
where N = 12/14/16 bits for AD9780/AD9781/AD9783
(respectively), while IOUTN provides no current.
The current output appearing at IOUTP and IOUTN is a function of
both the input code, and IFS and can be expressed as
I
I
OUTP = (DAC DATA/2N) × IFS
OUTN = ((2N − 1) − DAC DATA)/2N × IFS
(1)
(2)
where DAC DATA = 0 to 2N − 1 (decimal representation).
D
D
D
D
D
D
D
D
D
D
9 10
INPUT DATA
1
2
3
4
5
6
7
8
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTP and IOUTN
should be connected to matching resistive loads (RLOAD) that are
tied to analog common (AVSS). The single-ended voltage
output appearing at the IOUTP and IOUTN pins is
DAC CLK
QUAD-SWITCH
DAC OUTPUT
t
t
(
fS MIX MODE)
V
V
OUTP = IOUTP × RLOAD
OUTN = IOUTN × RLOAD
(3)
(4)
Note that to achieve the maximum output compliance of 1 V at
the nominal 20 mA output current, RLOAD must be set to 50 Ω.
Also note that the full-scale value of VOUTP and VOUTN should
not exceed the specified output compliance range to maintain
specified distortion and linearity performance.
QUAD-SWITCH
DAC OUTPUT
(RETURN-TO-
ZERO MODE)
Figure 64. Mix Mode and Return-to-Zero Mode DAC Waveforms
There are two distinct advantages to operating the AD9780/
AD9781/AD9783 differentially. First, differential operation
helps cancel common-mode error sources associated with IOUTP
and IOUTN, such as noise, distortion, and dc offsets. Second, the
differential code-dependent current and subsequent output
voltage (VDIFF) is twice the value of the single-ended voltage
output (VOUTP or VOUTN), providing 2× signal power to the load.
The functions that shape the output spectrums for the three
modes of operation, normal mode, mix mode, and return-to-
zero mode, are shown in Figure 65. Switching between the
analog modes reshapes the sinc roll-off inherent at the DAC
output. This ability to change modes in the AD9780/AD9781/
AD9783 makes the parts suitable for direct IF applications. The
user can place a carrier anywhere in the first three Nyquist
zones depending on the operating mode selected. The perfor-
mance and maximum amplitude in all three Nyquist zones is
V
DIFF = (IOUTP – IOUTN) × RLOAD
(5)
Rev. A | Page 27 of 36
AD9780/AD9781/AD9783
0mA
TO
impacted by this sinc roll-off depending on where the carrier is
placed, as shown in Figure 65.
2mA
AUXP
AUXN
V
BIAS
0
MIX
RETURN-TO-ZERO
0mA
TO
2mA
SINK
OR
SOURCE
POSITIVE
OR
NEGATIVE
–10
Figure 66. Auxiliary DAC Functional Diagram
NORMAL
In a single sideband transmitter application, the combination of
the input referred dc offset voltage of the quadrature modulator
and the DAC output offset voltage can result in local oscillator
(LO) feedthrough at the modulator output, which degrades system
performance. The auxiliary DACs can be used to remove the dc
offset and the resulting LO feedthrough. The circuit configura-
tion for using the auxiliary DACs for performing dc offset
correction depends on the details of the DAC and modulator
interface. An example of a dc-coupled configuration with low-
pass filtering is shown in Figure 67.
–20
–30
–40
0
0.5
1.0
fS
1.5
2.0
(
)
Figure 65. Transfer Function for Each Analog Operating Mode
Auxiliary DACs
Two auxiliary DACs are provided on the AD9780/AD9781/
AD9783. A functional diagram is shown in Figure 66. The
auxiliary DACs are current output devices with two output
pins, AUXP and AUXN. The active pin can be programmed to
either source or sink current. When either sinking or sourcing,
the full-scale current magnitude is 2 mA. The available compliance
range at the auxiliary DAC outputs depends on whether the output
is configured to sink or source current. When sourcing current,
the compliance voltage is 0 V to 1.6 V, but when sinking current,
the output compliance voltage is reduced to 0.8 V to 1.6 V. Either
output can be used, but only one output of the AUX DAC (P or
N) is active at any time. The inactive pin is always in a high
impedance state (>100 kΩ).
QUADRATURE
MODULATOR V+
AD9783
AUX
DAC1 OR
DAC2
QUAD MOD
I OR Q INPUTS
OPTIONAL
PASSIVE
FILTERING
AD9783
DAC1 OR
DAC2
25Ω TO 50Ω
25Ω TO 50Ω
Figure 67. DAC DC-Coupled to Quadrature Modulator with a Passive DC Shift
Rev. A | Page 28 of 36
AD9780/AD9781/AD9783
POWER DISSIPATION
Figure 68 through Figure 73 show the power dissipation of the part in single DAC and dual DAC modes.
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0
100
200
300
400
500
0
100
200
300
400
500
CLOCK SPEED (MSPS)
CLOCK SPEED (MSPS)
Figure 68. Power Dissipation, I Data Only, Single DAC Mode
Figure 71. Power Dissipation, I and Q Data, Dual DAC Mode
0.200
0.200
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
DVDD18
DVDD18
CVDD
CVDD
0
100
200
300
400
500
0
100
200
300
400
500
CLOCK SPEED (MSPS)
CLOCK SPEED (MSPS)
Figure 69. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply,
I Data Only
Figure 72. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply,
I and Q Data, Dual DAC Mode
0.200
0.175
0.150
0.200
AVDD33
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
0.125
AVDD33
0.100
0.075
0.050
DVDD33
DVDD33
0.025
0
0
100
200
300
400
500
0
100
200
300
400
500
CLOCK SPEED (MSPS)
CLOCK SPEED (MSPS)
Figure 70. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply,
I Data Only
Figure 73. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply,
I and Q Data, Dual DAC Mode
Rev. A | Page 29 of 36
AD9780/AD9781/AD9783
EVALUATION BOARD SCHEMATICS
7
0 7 6 - 9 3 0 6
Figure 74. Power Distribution
Rev. A | Page 3± of 36
AD9780/AD9781/AD9783
7 0 8 - 3 6 6 9
0 8 R 0 5
0 8 R 0 5
0 8 R 0 5
0 8 R 0 5
0 8 R 0 5
Figure 75. SPI Interface
Rev. A | Page 31 of 36
AD9780/AD9781/AD9783
9
0 7 6 - 9 3 0 6
2 0 4 R 0
2 0 4 R 0
2 0 4 R 0
2 0 4 R 0
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1
2
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
D13P
D13N
D12P
D12N
D11P
D11N
D10P
D10N
D9P
FS ADJ
RESET
CSB
3
CLKP
CLKN
4
SCLK
SDIO
SDO
DVSS
DVDD18
NC
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NC
NC
NC
D0N
D0P
D1N
DIP
D2N
D9N
D2P
Figure 76. Main Schematic
Rev. A | Page 32 of 36
AD9780/AD9781/AD9783
8 0 6 - 9 3 0 6
D 0 / G 2 4 0 - F 8 2 6 C F N -
k
J a c
0
G 5
9
7
7
5
5
3
3
1
1
9
9
7
7
5
5
3
3
1
1
9
9
7
7
5
5
3
3
1
1
9
9
7
7
5
5
3
3
1
1
G 4
S 4
G 4
S 4
G 4
S 4
G 4
S 4
G 4
S 3
G 3
S 3
G 3
S 3
G 3
S 3
G 3
S 3
G 3
S 2
G 2
S 2
G 2
S 2
G 2
S 2
G 2
S 2
G 2
S 1
G 1
S 1
G 1
S 1
G 1
S 1
G 1
S 1
G 1
8 4 S
8
G 4
6 4 S
6
G 4
4 4 S
4
G 4
2 4 S
2
G 4
0 4 S
0
G 4
8 3 S
8
G 3
6 3 S
6
G 3
4 3 S
4
G 3
2 3 S
2
G 3
0 3 S
0
G 3
8 2 S
8
G 2
6 2 S
6
G 2
4 2 S
4
G 2
2 2 S
2
G 2
0 2 S
0
G 2
8 1 S
8
G 1
6 1 S
6
G 1
4 1 S
4
G 1
2 1 S
2
G 1
0 1 S
0 1 G
S 9
G 9
S 7
G 7
S 5
G 5
S 3
G 3
S 8
G 8
S 6
G 6
S 4
G 4
S 2
G 2
S 1
G 1
k
J a c
Figure 77. Data Input Detail
Rev. A | Page 33 of 36
AD9780/AD9781/AD9783
8 1 0 6 - 9 3 0 6
4 0 2 R
2 4 0 R 0
0 4 C 0 2
2 4 0 C 0
0 4 R 0 2
0 4 R 0 2
2
0 4 R 0
Figure 78. AUX DAC and Clock Input Circuit Details
Rev. A | Page 34 of 36
AD9780/AD9781/AD9783
OUTLINE DIMENSIONS
0.60
0.42
0.24
10.00
BSC SQ
0.60
0.42
0.24
55
54
72
1
PIN 1
INDICATOR
PIN 1
INDICATOR
(BOTTOM VIEW)
0.50
BSC
9.75
BSC SQ
TOP VIEW
4.70
BSC SQ
EXPOSED
PAD
0.50
0.40
0.30
18
19
37
36
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
8.50 REF
EXPOSED PAD MUST BE
SOLDERED TO PCB AND
CONNECTED TO AVSS.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4
Figure 79. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm, Very Thin Quad
(CP-72-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−4±°C to +8ꢀ°C
Package Description
Package Option
CP-72-1
CP-72-1
AD978±BCPZ1
AD978±BCPZRL1
AD9781BCPZ1
AD9781BCPZRL1
AD9783BCPZ1
AD9783BCPZRL1
AD978±-EBZ1
AD9781-EBZ1
AD9783-EBZ1
72-Lead LFCSP_VQ
72-Lead LFCSP_VQ
72-Lead LFCSP_VQ
72-Lead LFCSP_VQ
72-Lead LFCSP_VQ
72-Lead LFCSP_VQ
Evaluation Board
Evaluation Board
Evaluation Board
−4±°C to +8ꢀ°C
−4±°C to +8ꢀ°C
−4±°C to +8ꢀ°C
−4±°C to +8ꢀ°C
−4±°C to +8ꢀ°C
CP-72-1
CP-72-1
CP-72-1
CP-72-1
1 Z = RoHS Compliant Part.
Rev. A | Page 3ꢀ of 36
AD9780/AD9781/AD9783
NOTES
©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06936-0-6/08(A)
Rev. A | Page 36 of 36
相关型号：
AD9780BCPZRL7
IC PARALLEL, WORD INPUT LOADING, 12-BIT DAC, QCC72, 10 X 10 MM, ROHS COMPLIANT, MO-220VNND-3, LFCSP-72, Digital to Analog Converter
ADI
AD9781BCPZRL7
IC PARALLEL, WORD INPUT LOADING, 14-BIT DAC, QCC72, 10 X 10 MM, ROHS COMPLIANT, MO-220VNND-3, LFCSP-72, Digital to Analog Converter
ADI
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