AD9826 [ADI]
Complete 16-Bit Imaging Signal Processor; 完整的16位成像信号处理器
| 型号： | AD9826 |
| 厂家： | 
ADI |
| 描述： | Complete 16-Bit Imaging Signal Processor |
| 文件： | 总20页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete 16-Bit Imaging
Signal Processor
a
AD9826
P RO D UCT D ESCRIP TIO N
FEATURES
T he AD9826 is a complete analog signal processor for imaging
applications. It features a 3-channel architecture designed to
sample and condition the outputs of trilinear color CCD arrays.
Each channel consists of an input clamp, Correlated Double
Sampler (CDS), offset DAC, and Programmable Gain Amplifier
(PGA), multiplexed to a high-performance 16-bit A/D converter.
16-Bit 15 MSPS A/D Converter
3-Channel 16-Bit Operation up to 15 MSPS
1-Channel 16-Bit Operation up to 12.5 MSPS
2-Channel Mode for Mono Sensors with Odd/Even Outputs
Correlated Double Sampling
1~6
؋
Programmable Gain ؎300 mV Programmable Offset
Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output
Optional Single Byte Output Mode
3-Wire Serial Digital Interface
3 V/5 V Digital I/O Compatibility
28-Lead SSOP Package
T he AD9826 can operate at speeds greater than 15 MSPS with
reduced performance.
T he CDS amplifiers may be disabled for use with sensors that
do not require CDS, such as Contact Image Sensors (CIS),
CMOS active pixel sensors, and Focal Plane Arrays.
The 16-bit digital output is multiplexed into an 8-bit output word,
which is accessed using two read cycles. T here is an optional
single byte output mode. T he internal registers are programmed
through a 3-wire serial interface, and provide adjustment of
the gain, offset, and operating mode.
Low Power CMOS: 400 mW (Typ)
Power-Down Mode Available
APPLICATIONS
Flatbed Document Scanners
Digital Copier
T he AD9826 operates from a single 5 V power supply, typically
consumes 400 mW of power, and is packaged in a 28-lead SSOP.
Multifunction Peripherals
Infrared Imaging Applications
Machine Vision
FUNCTIO NAL BLO CK D IAGRAM
AVDD AVSS
CAPT
AVSS
CML
CAPB
DRVDD
DRVSS
AVDD
AD9826
VINR
VING
PGA
CDS
OEB
BANDGAP
REFERENCE
9-BIT
DAC
16
8
16:8
MUX
3:1
MUX
16-BIT
ADC
DOUT
PGA
CDS
CDS
9-BIT
DAC
CONFIGURATION
REGISTER
MUX
REGISTER
VINB
PGA
SCLK
DIGITAL
CONTROL
INTERFACE
RED
GREEN
BLUE
SLOAD
SDATA
6
9-BIT
DAC
GAIN
REGISTERS
INPUT
CLAMP
BIAS
RED
9
OFFSET
GREEN
BLUE
OFFSET
REGISTERS
CDSCLK1 CDSCLK2
ADCCLK
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
AD9826–SPECIFICATIONS
MIN to T , AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, PGA
ANALOG SPECIFICATIONS (GTain = 1, Input range = 4 V p-p, unless otherwise noted.)
MAX
P aram eter
Min
Typ
Max
Unit
MAXIMUM CONVERSION RAT E
3-Channel Mode with CDS
2-Channel Mode with CDS
1-Channel Mode with CDS
30
30
18
MSPS
MSPS
MSPS
ACCURACY (ENT IRE SIGNAL PAT H)
ADC Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
No Missing Codes
16
±16
±0.5
Bits
LSB
LSB
Guaranteed
ANALOG INPUT S
Input Signal Range (Programmable)1
Allowable Reset T ransient1
Input Limits2
2.0/4.0
1.0
V p-p
V
V
AVSS – 0.3
AVDD + 0.3
Input Capacitance
Input Bias Current
10
10
pF
nA
AMPLIFIERS
PGA Gain
1
6
V/V
Steps
PGA Gain Resolution2
PGA Gain Monotonicity
Programmable Offset
Programmable Offset Resolution
Programmable Offset Monotonicity
64
Guaranteed
–300
+300
mV
Steps
512
Guaranteed
NOISE AND CROSST ALK
T otal Output Noise @ PGA Minimum
T otal Output Noise @ PGA Maximum
Channel-to-Channel Crosstalk
@ 15 MSPS
3.0
9.0
LSB rms
LSB rms
70
90
dB
dB
@ 6 MSPS
POWER SUPPLY REJECT ION
AVDD = 5 V ꢀ 0.25 V
0.1
2.0
% FSR
V
DIFFERENT IAL VREF (at 25°C)
CAPT –CAPB
T EMPERAT URE RANGE
Operating
Storage
–40
–65
+85
+150
°C
°C
POWER SUPPLIES
AVDD
DRVDD
4.75
3.0
5.0
5.0
5.25
5.25
V
V
OPERAT ING CURRENT
AVDD
DRVDD
75
5
200
mA
mA
µA
Power-Down Mode
POWER DISSIPAT ION
3-Channel Mode
1-Channel Mode
400
300
mW
mW
NOT ES
1Linear Input Signal Range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9826’s input clamp.
4V SET BY INPUT CLAMP
(3V OPTION ALSO AVAILABLE)
1V TYP
RESETTRANSIENT
4V p-p MAX INPUT SIGNAL RANGE
GND
6.0
2T he PGA Gain is approximately “linear in dB” and follows the equation:
Specifications subject to change without notice.
where G is the register value.
G
ain =
63 – G
63
1 + 5.0
REV. A
–2–
AD9826
MIN to T , AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz,
DIGITAL SPECIFICATIONS (CT = 10 pF, unless otherwise noted.)
MAX
L
P aram eter
Sym bol
Min
Typ
Max
Unit
LOGIC INPUT S
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.0
V
V
µA
µA
pF
0.8
10
10
10
LOGIC OUT PUT S
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
VOH
VOL
IOH
IOL
4.5
V
V
µA
µA
0.1
50
50
LOGIC OUT PUT S (with DRVDD = 3 V)
High Level Output Voltage, (IOH = 50 µA)
Low Level Output Voltage (IOL = 50 µA)
VOH
VOL
2.95
V
V
0.05
Specifications subject to change without notice.
(TMIN to T , AVDD = 5 V, DRVDD = 5 V, specs are for 16-bit performance.)
TIMING SPECIFICATIONS
P aram eter
MAX
Sym bol
Min
Typ
Max
Unit
CLOCK PARAMET ERS
3-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulsewidth
CDSCLK1 Pulsewidth
tPRA
tPRB
tADCLK
tC1
tC2
tC1C2
tADC2
tC2ADR
tC2ADF
tC2C1
tAD
200
80
30
8
8
0
0
5
30
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CDSCLK2 Pulsewidth
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Rising to ADCCLK Rising
CDSCLK2 Falling to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
2
SERIAL INT ERFACE
Maximum SCLK Frequency
SLOAD to SCLK Set-Up T ime
SCLK to SLOAD Hold T ime
SDAT A to SCLK Rising Set-Up T ime
SCLK Rising to SDAT A Hold T ime
SCLK Falling to SDAT A Valid
fSCLK
tLS
tLH
tDS
tDH
10
10
10
10
10
10
MHz
ns
ns
ns
ns
tRDV
ns
DAT A OUT PUT S
Output Delay
tOD
tDV
tHZ
6
10
10
3 (Fixed)
ns
ns
ns
Cycles
3-State to Data Valid
Output Enable High to 3-State
Latency (Pipeline Delay)
NOT ES
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
Specifications subject to change without notice.
REV. A
–3–
AD9826
ABSO LUTE MAXIMUM RATINGS*
O RD ERING GUID E
With
Respect
To
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
P aram eter
Min Max
Unit
AD9826KRS –40°C to +85°C
5.3 mm SSOP RS-28
VIN, CAPT , CAPB
Digital Inputs
AVDD
DRVDD
AVSS
Digital Outputs
Junction T emperature
Storage T emperature
Lead T emperature
(10 sec)
AVSS
AVSS
AVSS
DRVSS –0.5 +6.5
DRVSS –0.3 +0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.5 +6.5
V
V
V
V
V
V
°C
°C
°C
TH ERMAL CH ARACTERISTICS
Ther m al Resistance
28-Lead 5.3 mm SSOP
θJA = 109°C/W
DRVSS –0.3 DRVDD + 0.3
150
–65 +150
300
θJC = 39°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9826 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. T herefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–4–
AD9826
P IN CO NFIGURATIO N
CDSCLK1
CDSCLK2
ADCCLK
OEB
1
2
3
4
5
6
7
8
9
28 AVDD
AVSS
27
26 VINR
25 OFFSET
24 VING
23 CML
DRVDD
DRVSS
(MSB) D7
D6
AD9826
TOP VIEW
22 VINB
(Not to Scale) 21 CAPT
D5
20
CAPB
D4 10
19 AVSS
11
12
13
14
18
D3
D2
AVDD
17
SLOAD
16
15
D1
SCLK
(LSB) D0
SDATA
P IN FUNCTIO N D ESCRIP TIO NS
P in No.
Mnem onic
Type
D escription
1
CDSCLK1
CDSCLK2
ADCCLK
OEB
DI
CDS Reference Level Sampling Clock
CDS Data Level Sampling Clock
A/D Converter Sampling Clock
Output Enable, Active Low
2
DI
3
DI
4
DI
5
DRVDD
DRVSS
D7
P
Digital Output Driver Supply
Digital Output Driver Ground
6
P
7
DO
DO
DO
DO
DO
DO
DO
DO
DI/DO
DI
Data Output MSB. ADC DB15 High Byte, ADC DB7 Low Byte
Data Output. ADC DB14 High Byte, ADC DB6 Low Byte
Data Output. ADC DB13 High Byte, ADC DB5 Low Byte
Data Output. ADC DB12 High Byte, ADC DB4 Low Byte
Data Output. ADC DB11 High Byte, ADC DB3 Low Byte
Data Output. ADC DB10 High Byte, ADC DB2 Low Byte
Data Output. ADC DB9 High Byte, ADC DB1 Low Byte
Data Output LSB. ADC DB8 High Byte, ADC DB0 Low Byte
Serial Interface Data Input/Output
8
D6
9
D5
10
11
12
13
14
15
16
17
18, 28
19, 27
20
21
22
23
24
25
26
D4
D3
D2
D1
D0
SDAT A
SCLK
SLOAD
AVDD
AVSS
CAPB
CAPT
VINB
CML
Serial Interface Clock Input
DI
Serial Interface Load Pulse
P
5 V Analog Supply
P
Analog Ground
AO
AO
AI
ADC Bottom Reference Voltage Decoupling
ADC T op Reference Voltage Decoupling
Analog Input, Blue Channel
AO
AI
Internal Bias Level Decoupling
VING
OFFSET
VINR
Analog Input, Green Channel
AO
AI
Clamp Bias Level Decoupling
Analog Input, Red Channel
T YPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. A
–5–
AD9826
INP UT REFERRED NO ISE
D EFINITIO NS O F SP ECIFICATIO NS
T he rms output noise is measured using histogram techniques.
T he ADC output codes’ standard deviation is calculated in
LSB, and can be converted to an equivalent voltage, using the
relationship 1 LSB = 4 V/65536 = 61 µV. T he noise may then
be referred to the input of the AD9826 by dividing by the
PGA gain.
INTEGRAL NO NLINEARITY (INL)
Integral nonlinearity error refers to the deviation of each individual
code from a line drawn from “zero scale” through “positive full
scale.” T he point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a level
1 1/2 LSB beyond the last code transition. T he deviation is
measured from the middle of each particular code to the true
straight line.
CH ANNEL-TO -CH ANNEL CRO SSTALK
In an ideal 3-channel system, the signal in one channel will not
influence the signal level of another channel. T he channel-to-
channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD9826, one channel is grounded and the other two chan-
nels are exercised with full scale input signals. The change in the
output codes from the first channel is measured and compared
with the result when all three channels are grounded. The differ-
ence is the channel-to-channel crosstalk, stated in LSB.
D IFFERENTIAL NO NLINEARITY (D NL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. T hus every
code must have a finite width. No missing codes guaranteed
to 16-bit resolution indicates that all 65536 codes, respec-
tively, must be present over all operating ranges.
O FFSET ERRO R
T he first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. T he offset error is the
deviation of the actual first code transition level from the
ideal level.
AP ERTURE D ELAY
T he aperture delay is the time delay that occurs from when a
sampling edge is applied to the AD9826 until the actual sample
of the input signal is held. Both CDSCLK1 and CDSCLK2
sample the input signal during the transition from high to low,
so the aperture delay is measured from each clock’s falling edge
to the instant the actual internal sample is taken.
GAIN ERRO R
T he last code transition should occur for an analog value
1 1/2 LSB below the nominal full scale voltage. Gain error is
the deviation of the actual difference between first and last
code transitions and the ideal difference between the first and
last code transitions.
P O WER SUP P LY REJECTIO N
Power supply rejection specifies the maximum full-scale change
that occurs from the initial value when the supplies are varied
over the specified limits.
REV. A
–6–
AD9826
Typical Performance Characteristics–
20
10
1.0
0.5
0
–10
–20
0
–0.5
–1.0
24000
36000
48000
64000
12000
0
200
400
600
800
1000
0
TPC 1. Typical INL Performance at 15 MSPS
TPC 4. Typical INL Performance at 30 MSPS
1.0
1.0
0.5
0.5
0
0
–0.5
–1.0
–0.5
–1.0
200
400
600
800
1000
0
64000
0
12000
24000
36000
48000
TPC 5. Typical DNL Performance at 30 MSPS
TPC 2. Typical DNL Performance at 15 MSPS
10
10
5
5
0
0
15
30
45
63
0
0
15
30
45
63
GAIN SETTING
GAIN SETTING
TPC 3. Output Noise vs. Gain
TPC 6. Input Referred Noise vs. Gain
REV. A
–7–
AD9826
TIMING D IAGRAMS
ANALOG
INPUTS
PIXEL n (R,G,B)
PIXEL
(n+2)
PIXEL
(n+1)
t
AD
t
AD
t
t
PRA
C1
t
C2C1
CDSCLK1
CDSCLK2
t
t
C2
C1C2
t
C2ADF
t
t
t
ADCLK
ADC2
C2ADR
ADCCLK
OUTPUT
t
t
OD
ADCLK
DATA
D<7:0>
R(n–2) G(n–2) G(n–2) B(n–2) B(n–2) R(n–1) R(n–1) G(n–1) G(n–1) B(n–1)
B(n–1)
R(n)
HB
R(n)
LB
G(n)
HB
G(n)
LB
LOW
HB
LB
HB
LB
HB
LB
HB
LB
HIGH
BYTE
BYTE
Figure 1. 3-Channel CDS Mode Timing
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
ANALOG
INPUTS
PIXEL n
PIXEL
(n+1)
PIXEL
(n+2)
t
AD
t
AD
t
C1
t
PRB
t
C2C1
CDSCLK1
CDSCLK2
t
C1C2
t
C2
t
C2ADR
t
C2ADF
ADCCLK
t
ADCLK
t
t
OD
ADCLK
OUTPUT
DATA
D<7:0>
PIXEL (n–4)
PIXEL (n–4)
PIXEL (n–3)
PIXEL (n–3)
PIXEL (n–2)
PIXEL (n–2)
HIGH BYTE
NOTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
IN 1-CHANNEL CDS MODE, THE CDSCLK1 FALLING EDGE ANDTHE CDSCLK2 RISING EDGE MUST OCCURWHILE ADCCLK IS “LOW.”
Figure 2. 1-Channel CDS Mode Timing
REV. A
–8–
AD9826
ANALOG
INPUTS
PIXEL n
t
PIXEL (n+1)
PIXEL (n+2)
t
AD
AD
t
PRA
t
C1
t
C2C1
CDSCLK1
t
t
C2
C1C2
CDSCLK2
ADCCLK
t
C2ADR
t
t
ADC2
C2ADF
t
ADCLK
t
ADCLK
OUTPUT
DATA
D<7:0>
CH1(n)
CH1(n–2)
CH2(n–2)
CH1(n–1)
CH2(n–1)
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
Figure 3. 2-Channel CDS Mode Timing
PIXEL
(n+1)
PIXEL n
t
ANALOG
INPUTS
AD
t
C2
CDSCLK2
ADCCLK
t
C2ADR
t
ADC2
t
C2ADF
t
t
ADCLK
ADCLK
OUTPUT
DATA
CH1(n–2)
CH1(n–1)
CH2(n–1)
CH1(n)
CH2(n–2)
D<7:0>
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
Figure 4. 2-Channel SHA Mode Timing
REV. A
–9–
AD9826
PIXEL n (R,G,B)
PIXEL (n+1)
t
AD
ANALOG
INPUTS
t
PRA
t
C2
t
C2AD
CDSCLK2
ADCCLK
t
t
t
ADC2
C2ADR
ADCLK
t
t
OD
ADCLK
OUTPUT
DATA
D<7:0>
R (n–2) G (n–2) G (n–2) B (n–2) B (n–2) R (n–1) R (n–1) G (n–1) G (n–1) B (n–1) B (n–1)
R (n)
HB
R (n)
LB
G (n)
HB
G (n)
LB
LB
HIGH
BYTE
LOW
HB
LB
HB
LB
HB
LB
HB
BYTE
Figure 5. 3-Channel SHA Mode Timing
PIXEL n
t
AD
ANALOG
INPUTS
t
PRB
t
C2
CDSCLK2
ADCCLK
t
C2ADR
t
C2ADF
t
ADCLK
t
t
t
ADCLK
OD
OUTPUT
DATA
D<7:0>
PIXEL (n–4)
PIXEL (n–4)
PIXEL (n–3)
PIXEL (n–3)
PIXEL (n–2)
PIXEL (n–2)
HIGH BYTE
NOTE
LOW BYTE
HIGH BYTE
LOW BYTE
HIGH BYTE
LOW BYTE
IN 1-CHANNEL SHA MODE,THE CDSCLK2 RISING EDGE MUST OCCURWHILE ADCCLK IS “LOW.”
Figure 6. 1-Channel SHA Mode Timing
REV. A
–10–
AD9826
ADCCLK
t
t
OD
OD
OUTPUT
DATA
<D7:D0>
HIGH BYTE
DB15–DB8
LOW BYTE
DB7–DB0
HB
n+1
LB
n+1
LB
n+2
HB
n+3
PIXEL n
PIXEL n
t
t
DV
HZ
OEB
Figure 7. Digital Output Data Timing
ADCCLK
t
OD
OUTPUT
DATA
<D7:D0>
HIGH BYTE
DB15–DB8
HIGH BYTE
DB15–DB8
HB
n+2
HB
n+3
PIXEL n
PIXEL n+1
t
t
HZ
DV
OEB
Figure 8. Single Byte Mode Digital Output Data Timing
R/Wb
t
SDATA
A2
A1
A0
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
DH
DS
SCLK
t
t
LS
LH
SLOAD
Figure 9. Serial Write Operation Timing
A2
A1
A0
D8
D6
D5
D3
D2
D0
D7
D4
D1
SDATA
R/Wb
t
RDV
SCLK
t
t
LH
LS
SLOAD
Figure 10. Serial Read Operation Timing
REV. A
–11–
AD9826
ANALOG
INPUTS
PIXEL (n+1)
PIXEL n (R,G,B)
CDSCLK1
CDSCLK2
ADCCLK
RED
PGA
OUT
RED (n)
GREEN (n)
BLUE (n)
RED (n+1)
GREEN (n+1)
BLUE (n+1)
RED (n–1)
GREEN (n–1)
BLUE (n–1)
GREEN
PGA
OUT
BLUE
PGA
OUT
MUX
OUT
GREEN (n–1)
BLUE (n–1)
RED (n)
GREEN (n)
BLUE (n)
RED (n+1)
GREEN (n+1)
OUTPUT
DATA
D<7:0>
R(n–2) G(n–2) G(n–2) B(n–2) B(n–2) R(n–1) R(n–1) G(n–1) G(n–1) B(n–1) B(n–1)
R(n)
HB
R(n)
LB
G(n)
HB
G(n)
LB
HB
LB
HB
LB
HB
LB
HB
LB
HIGH
BYTE
LOW
BYTE
NOTES
1.THE MUX STATE MACHINE IS INTERNALLY RESET ATTHE CDSCLK2 RISING EDGE.
2. EACH PIXEL IS SAMPLED AND AMPLIFIED BYTHE PGAs AT CDSCLK2 FALLING EDGE.
3. AFTER CDSCLK2 RISING EDGE,THE NEXT ADCCLK RISING EDGEWILL ALWAYS SELECT RED PGA OUTPUT.
4.THE ADC SAMPLESTHE MUX OUTPUT ON ADCCLK FALLING EDGES.
5.THE MUX SWITCHESTOTHE NEXT PGA OUTPUT AT ADCCLK RISING EDGES.
Figure 11. Internal Timing Diagram for 3-Channel CDS Mode
REV. A
–12–
AD9826
FUNCTIO NAL D ESCRIP TIO N
2-Channel CD S Mode
T he AD9826 can be operated in six different modes: 3-Channel
CDS Mode, 3-Channel SH A Mode, 2-Channel CDS Mode,
2-Channel SHA Mode, 1-Channel CDS Mode, and 1-Channel
SHA Mode. Each mode is selected by programming the Configura-
tion Registers through the serial interface. For more detail on
CDS or SHA mode operation, see the Circuit Operation section.
The 2-Channel Mode is selected by writing a “1” into two of the
channel select bits of the MUX register (D4–D6). Bit D5 of the
configuration register also needs to be set low to take the part out
of 3-Channel Mode. The channels that will be used is determined
by the contents of Bits D4–D6 of the MUX Configuration Reg-
ister (see T able III). T he combination of inputs that can be
selected are; RG, RB, or GB by writing a “1” into the appropri-
ate bit. T he sample order is selected by Bit D7. If D7 is high,
the MUX will sample in the following order: RG or RB or GB
depending on which channels are turned on. If Bit D7 is set low
the mux will sample in the following order: GR or BR or BG
depending on which channels are turned on.
3-Channel CD S Mode
In 3-Channel CDS Mode, the AD9826 simultaneously samples
the Red, Green, and Blue input voltages from the CCD outputs.
The sampling points for each Correlated Double Sampler (CDS)
are controlled by CDSCLK1 and CDSCLK2 (see Figures 11
and 13). CDSCLK1’s falling edge samples the reference level of
the CCD waveform. CDSCLK2’s falling edge samples the data
level of the CCD waveform. Each CDS amplifier outputs the
difference between the CCD’s reference and data levels. Next,
the output voltage of each CDS amplifier is level-shifted by an
Offset DAC. T he voltages are then scaled by the three Program-
mable Gain Amplifiers before being multiplexed through the
16-Bit ADC. T he ADC sequentially samples the PGA outputs
on the falling edges of ADCCLK.
T he AD9826 simultaneously samples the selected channels’
input voltages from the CCD outputs. T he sampling points
for each Correlated Double Sampler (CDS) are controlled by
CDSCLK1 and CDSCLK2 (see Figure 11). CDSCLK1’s fall-
ing edge samples the reference level of the CCD waveform.
CDSCLK2’s falling edge samples the data level of the CCD
waveform. Each CDS amplifier outputs the difference between
the CCD’s reference and data levels. Next, the output voltage of
each CDS amplifier is level-shifted by an Offset DAC. The volt-
ages are then scaled by the two Programmable Gain Amplifiers
before being multiplexed through the 16-bit ADC. T he ADC
sequentially samples the PGA outputs on the falling edges of
ADCCLK.
T he offset and gain values for the Red, Green, and Blue chan-
nels are programmed using the serial interface. T he order in
which the channels are switched through the multiplexer is
selected by programming the MUX Configuration register.
T iming for this mode is shown in Figure 1. It is recommended
that the falling edge of CDSCLK2 occur before the rising edge
of ADCCLK, although this is not required to satisfy the mini-
mum timing constraints. T he rising edge of CDSCLK2 should
not occur before the previous falling edge of ADCCLK, as
shown by tADC2. T he output data latency is three clock cycles.
T he offset and gain values for the Red, Green, and Blue chan-
nels are programmed using the serial interface. T he order in
which the channels are switched through the multiplexer is
selected by programming the MUX Configuration Register.
T iming for this mode is shown in Figure 3. T he rising edge of
CDSCLK2 should not occur before the previous falling edge of
ADCCLK, as shown by tADC2. T he output data latency is three
clock cycles.
3-Channel SH A Mode
In 3-Channel SHA Mode, the AD9826 simultaneously samples
the Red, Green, and Blue input voltages. T he sampling point is
controlled by CDSCLK2. CDSCLK2’s falling edge samples the
input waveforms on each channel. T he output voltages from the
three SHAs are modified by the offset DACs and then scaled by
the three PGAs. T he outputs of the PGAs are then multiplexed
through the 16-bit ADC. T he ADC sequentially samples the
PGA outputs on the falling edges of ADCCLK.
2-Channel SH A Mode
The 2-Channel Mode is selected by writing a “1” into two of the
channel select bits of the MUX Register (D4–D6). Bit D5 of the
configuration register also needs to be set low to take the part
out of 3-Channel Mode. T he channels that will be used is deter-
mined by the contents of Bits D4–D6 of the MUX Configuration
Register (see T able III ). T he combination of inputs that can be
selected are; RG, RB, or GB by writing a “1” into the appropri-
ate bit. T he sample order is selected by Bit D7. If D7 is high,
the mux will sample in the following order: RG or RB or GB,
depending on which channels are turned on. If Bit D7 is set low,
the mux will sample in the following order: GR or BR or BG,
depending on which channels are turned on.
T he input signal is sampled with respect to the voltage applied
to the OFFSET pin (see Figure 14). With the OFFSET pin
grounded, a zero volt input corresponds to the ADC’s zero scale
output. T he OFFSET pin may also be used as a coarse offset
adjust pin. A voltage applied to this pin will be subtracted from
the voltages applied to the Red, Green, and Blue inputs in the first
amplifier stage of the AD9826. The input clamp is disabled in this
mode. For more information, see the Circuit Operation section.
In 2-Channel SHA Mode, the AD9826 simultaneously samples
the selected channels’ input voltages. T he sampling point is
controlled by CDSCLK2. CDSCLK2’s falling edge samples the
input waveforms on each channel. T he output voltages from the
two SHAs are modified by the offset DACs and then scaled by
the two PGAs. T he outputs of the PGAs are then multiplexed
through the 16-bit ADC. The ADC sequentially samples the PGA
outputs on the falling edges of ADCCLK.
T iming for this mode is shown in Figure 5. CDSCLK1 should
be grounded in this mode. Although it is not required, it is recom-
mended that the falling edge of CDSCLK2 occur before the
rising edge of ADCCLK. T he rising edge of CDSCLK2 should
not occur before the previous falling edge of ADCCLK, as shown
by tADC2. T he output data latency is three ADCCLK cycles.
T he offset and gain values for the Red, Green, and Blue chan-
nels are programmed using the serial interface. T he order in
which the channels are switched through the multiplexer is
selected by programming the MUX Configuration register.
T he input signal is sampled with respect to the voltage applied
to the OFFSET pin (see Figure 14). With the OFFSET pin
grounded, a zero volt input corresponds to the ADC’s zero scale
output. T he OFFSET pin may also be used as a coarse offset
REV. A
–13–
AD9826
adjust pin. A voltage applied to this pin will be subtracted from
the voltages applied to the Red, Green, and Blue inputs in the first
amplifier stage of the AD9826. The input clamp is disabled in this
mode. For more information, see the Circuit Operation section.
Bit D7 controls the input range of the AD9826. Setting D7 high
sets the input range to 4 V while setting Bit D7 low sets the
input range to 2 V. Bit D6 controls the internal voltage refer-
ence. If the AD9826’s internal voltage reference is used, then
this bit is set high. Setting Bit D6 low will disable the internal
voltage reference, allowing an external voltage reference to be
used. Setting Bit D5 high will configure the AD9826 for 3-
channel operation. If D5 is set low, the part will be in either
2CH or 1CH mode based on the settings in the MUX Configu-
ration Register (See T able III and the MUX Configuration
Register description). Setting Bit D4 high will enable the CDS
mode of operation, and setting this bit low will enable the SHA
mode of operation. Bit D3 sets the dc bias level of the AD9826’s
input clamp.
T iming for this mode is shown in Figure 4. CDSCLK1 should
be grounded in this mode. The rising edge of CDSCLK2 should
not occur before the previous falling edge of ADCCLK, as shown
by tADC2. The output data latency is three ADCCLK cycles. The
offset and gain values for the Red, Green, and Blue channels are
programmed using the serial interface. T he order in which the
channels are switched through the multiplexer is selected by
programming the MUX Configuration Register.
1-Channel CD S Mode
T his mode operates the same way as the 3-Channel CDS mode.
The difference is that the multiplexer remains fixed in this mode,
so only the channel specified in the MUX Configuration Regis-
ter is processed.
T his bit should always be set high for the 4 V clamp bias, unless
a CCD with a reset feedthrough transient exceeding 2 V is used.
If the 3 V clamp bias level is used, then the peak-to-peak input
signal range to the AD9826 is reduced to 3 V maximum. Bit D2
controls the power-down mode. Setting Bit D2 high will place
the AD9826 into a very low-power “sleep” mode. All register
contents are retained while the AD9826 is in the powered-down
state. Bit D0 controls the output mode of the AD9826. Setting
Bit D0 high will enable a single byte output mode where only
the 8 MSBs of the 16 b ADC will be output on each rising edge
of ADCCLK (see Figure 8). If Bit D0 is set low, then the 16 b
ADC output is multiplexed into two bytes. T he MSByte is
output on ADCCLK rising edge and the LSByte is output on
ADCCLK falling edge.
T iming for this mode is shown in Figure 2.
1-Channel SH A Mode
T his mode operates the same way as 3-Channel SHA mode,
except that the multiplexer remains stationary. Only the channel
specified in the MUX Configuration Register is processed.
T iming for this mode is shown in Figure 6. CDSCLK1 should
be grounded in this mode of operation.
Configur ation Register
T he Configuration Register controls the AD9826’s operating
mode and bias levels. Bits D8 and D1 should always be set low.
Table I. Internal Register Map
Register
Nam e
Address
A2 A1 A0 D 8
D ata Bits
D 4
D 7
D 6
D 5
D 3
D 2
D 1
0
D 0
Configuration
MUX Config
Red PGA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Input Rng
VREF 3CH Mode
CDS On Clamp Pwr Dn
Blue
1 Byte Out
0
0
RGB/BGR
Red
Green
MSB
MSB
MSB
0
0
0
0
0
0
0
0
0
0
LSB
LSB
LSB
LSB
LSB
LSB
Green PGA
Blue PGA
0
0
Red Offset
MSB
MSB
MSB
Green Offset
Blue Offset
Table II. Configuration Register Settings
D
8
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
Set
to
0
Input Range Internal VREF 3CH Mode CDS Operation
Input Clamp Bias
Power-Down
1 = On
0 = Off (Normal)*
Set
to
0
Output Mode
1 = 4 V*
1 = Enabled*
1 = On*
1 = CDS Mode* 1 = 4 V*
0 = SHA Mode 0 = 3 V
0 = 2 Byte*
1 = 1 Byte
0 = 2 V
0 = Disabled
0 = Off
*Power-on default value.
REV. A
–14–
AD9826
MUX Configur ation Register
P GA Gain Register s
T he MUX Configuration Register controls the sampling chan-
nel order and the 2-Channel Mode configuration in the AD9826.
Bits D8 and D3–D0 should always be set low. Bit D7 is used
when operating in 3-Channel or 2-Channel Mode. Setting Bit
D7 high will sequence the MUX to sample the Red channel
first, then the Green channel, and then the Blue channel. When
in 3-channel mode, the CDSCLK2 pulse always resets the MUX
to sample the Red channel first (see Figure 11). When Bit D7 is
set low, the channel order is reversed to Blue first, Green sec-
ond, and Red third. T he CDSCLK2 pulse will always reset the
MUX to sample the Blue channel first. Bits D6, D5, and D4 are
used when operating in 1 or 2-Channel Mode. Bit D6 is set high
to sample the Red channel. Bit D5 is set high to sample the
Green channel. Bit D4 is set high to sample the Blue channel.
The MUX will remain stationary during 1-channel mode. Two-
Channel Mode is selected by setting two of the channel select
Bits (D4–D6) high. T he MUX samples the channels in the
order selected by Bit D7.
T here are three PGA registers for individually programming the
gain in the Red, Green, and Blue channels. Bits D8, D7, and
D6 in each register must be set low, and Bits D5 through D0
control the gain range from 1× to 6× in 64 increments. See
Figure 17 for a graph of the PGA gain versus PGA register
code. T he coding for the PGA registers is straight binary, with
an all “zeros” word corresponding to the minimum gain setting
(1×) and an all “ones” word corresponding to the maximum
gain setting (6×).
O ffset Register s
T here are three Offset Registers for individually programming
the offset in the Red, Green, and Blue channels. Bits D8 through
D0 control the offset range from –300 mV to +300 mV in 512
increments. T he coding for the Offset Registers is Sign Mag-
nitude, with D8 as the sign bit. T able V shows the offset range
as a function of the Bits D8 through D0.
Table III. MUX Configuration Register Settings
D
8
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
Set
to
0
MUX Order
Channel Select
Channel Select
Channel Select
Set
to
0
Set
to
0
Set
to
0
Set
to
0
1 = R-G-B*
0 = B-G-R
1 = RED*
0 = Off
1 = GREEN
0 = Off*
1 = BLUE
0 = Off*
*Power-on default value.
Table IV. P GA Gain Register Settings
D 8
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
Gain (V/V)
Gain (dB)
Set to 0 Set to 0 Set to 0 MSB
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0*
1
1.0
1.013
0.0
0.12
•
•
•
•
•
•
•
•
•
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
5.56
6.0
14.9
15.56
*Power-on default value.
Table V. O ffset Register Settings
D 8
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
O ffset (m V)
MSB
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0*
1
0
+1.2
•
•
•
•
•
•
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
+300
0
–1.2
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
–300
*Power-on default value.
REV. A
–15–
AD9826
Exter nal Input Coupling Capacitor s
CIRCUIT O P ERATIO N
T he recommended value for the input coupling capacitors is
0.1 µF. While it is possible to use a smaller capacitor, this larger
value is chosen for several reasons:
Analog Inputs—CD S Mode O per ation
Figure 12 shows the analog input configuration for the CDS
mode of operation. Figure 13 shows the internal timing for the
sampling switches. T he CCD reference level is sampled when
CDSCLK1 transitions from high to low, opening S1. T he CCD
data level is sampled when CDSCLK2 transitions from high to
low, opening S2. S3 is then closed, generating a differential
output voltage representing the difference between the two
sampled levels.
Cr ossta lk
T he input coupling capacitor creates a capacitive divider with
any parasitic capacitance between PCB traces and on chip traces.
C
IN should be large relative to these parasitic capacitances in
order to minimize this effect. For example, with a 100 pF input
capacitance and just a few hundred fF of parasitic capacitance
on the PCB and/or the IC the imaging system could expect
to have hundreds of LSBs of crosstalk at the 16 b level. Using
a large capacitor value = 0.1 µF will minimize any errors due
to crosstalk.
T he input clamp is controlled by CDSCLK1. When CDSCLK1
is high, S4 closes and the internal bias voltage is connected to
the analog input. T he bias voltage charges the external 0.1 µF
input capacitor, level-shifting the CCD signal into the AD9826’s
input common-mode range. T he time constant of the input
clamp is determined by the internal 5 kΩ resistance and the
external 0.1 µF input capacitance.
Signa l Attenua tion
T he input coupling capacitor creates a capacitive divider with a
CMOS integrated circuit’s input capacitance, attenuating the
CCD signal level. CIN should be large relative to the IC’s 10 pF
input capacitance in order to minimize this effect.
AD9826
Linea r ity
S1
Some of the input capacitance of a CMOS IC is junction capaci-
tance, which varies nonlinearly with applied voltage. If the input
coupling capacitor is too small, then the attenuation of the CCD
signal will vary nonlinearly with signal level. T his will degrade
the system linearity performance.
4pF
VINR
CCD
SIGNAL
CML
0.1F
S3
5K
CML
Sa m pling Er r or s
S2
4pF
T he internal 4 pF sample capacitors have a “memory” of the
previously sampled pixel. T here is a charge redistribution error
between CIN and the internal sample capacitors for larger pixel-
to-pixel voltage swings. As the value of CIN is reduced, the
resulting error in the sampled voltage will increase. With a CIN
value of 0.1 µF, the charge redistribution error will be less than
1 LSB for a full-scale pixel-to-pixel voltage swing.
S4
1.7k⍀
OFFSET
4V
3V
+
INPUT CLAMP LEVEL
IS SELECTED INTHE
CONFIGURATION
REGISTER
1F
0.1F
2.2k⍀
6.9k⍀
Figure 12. CDS-Mode Input Configuration (All Three
Channels Are Identical)
S1, S4 CLOSED
S1, S4 CLOSED
CDSCLK1
S1, S4 OPEN
S2 CLOSED
S2 CLOSED
CDSCLK2
S2 OPEN
S3 OPEN
S3 CLOSED
S3 CLOSED
Q3
(INTERNAL)
Figure 13. CDS-Mode Internal Switch Timing
REV. A
–16–
AD9826
Analog Inputs—SH A Mode O per ation
Figure 16 shows how the OFFSET pin may be used in a CIS
application for coarse offset adjustment. Many CIS signals have
dc offsets ranging from several hundred millivolts to more than
1 V. By connecting the appropriate dc voltage to the OFFSET
pin, the CIS signal will be restored to “zero.” After the large dc
offset is removed, the signal can be scaled using the PGA to
maximize the ADC’s dynamic range.
Figure 14 shows the analog input configuration for the SHA
mode of operation. Figure 15 shows the internal timing for the
sampling switches. The input signal is sampled when CDSCLK2
transitions from high to low, opening S1. T he voltage on the
OFFSET pin is also sampled on the falling edge of CDSCLK2,
when S2 opens. S3 is then closed, generating a differential out-
put voltage representing the difference between the sampled
input voltage and the OFFSET voltage. T he input clamp is
disabled during SHA mode operation.
AD9826
VINR
RED
AD9826
RED-
SHA
OFFSET
4pF
S1
VINR
INPUT
SIGNAL
CML
VING
GREEN
GREEN-
SHA
OFFSET
S3
S2
4pF
OPTIONAL DC
OFFSET (OR
CONNECT
OFFSET
VING
CML
VINB
BLUE
BLUE-
SHA
TO GND)
OFFSET
VRED FROM
CIS MODULE
OFFSET
AVDD
0.1F
R1
DC OFFSET
VINB
R2
Figure 16. SHA-Mode Used with External DC Offset
Figure 14. SHA-Mode Input Configuration (All Three
Channels Are Identical)
S1, S2 CLOSED
S1, S2 OPEN
S1, S2 CLOSED
CDSCLK2
S3 CLOSED
S3 CLOSED
Q3
S3 OPEN
(INTERNAL)
Figure 15. SHA-Mode Internal Switch Timing
REV. A
–17–
AD9826
P r ogr am m able Gain Am plifier s
AP P LICATIO NS INFO RMATIO N
T he AD9826 uses one Programmable Gain Amplifier (PGA) for
each channel. Each PGA has a gain range from 1× (0 dB) to
6.0× (15.56 dB), adjustable in 64 steps. Figure 17 shows the
PGA gain as a function of the PGA register code. Although the
gain curve is approximately “linear in dB,” the gain in V/V var-
ies nonlinearly with register code, following the equation:
Cir cuit and Layout Recom m endations
T he recommended circuit configuration for 3-Channel CDS
Mode operation is shown in Figure 18. T he recommended
input coupling capacitor value is 0.1 µF (see Circuit Operation
section for more details). A single ground plane is recommended
for the AD9826. A separate power supply may be used for
DRVDD, the digital driver supply, but this supply pin should
still be decoupled to the same ground plane as the rest of the
AD9826. T he loading of the digital outputs should be mini-
mized, either by using short traces to the digital ASIC, or by
using external digital buffers. T o minimize the effect of digital
transients during major output code transitions, the falling edge
of CD SCLK2 should occur coincident with or before the
rising edge of ADCCLK (see Figures 1 through 6 for timing).
All 0.1 µF decoupling capacitors should be located as close as
possible to the AD9826 pins. When operating in 1CH or 2CH
Mode, the unused analog inputs should be grounded.
6.0
Gain =
63 – G
1 + 5.0
63
where G is the decimal value of the gain register contents, and
varies from 0 to 63.
6.00
4.75
3.50
2.25
1.00
16
12
8
For 3-Channel SHA Mode, all of the above considerations also
apply, except that the analog input signals are directly connected
to the AD9826 without the use of coupling capacitors. The analog
input signals must already be dc-biased between 0 V and 4 V.
Also, the OFFSET pin should be grounded if the inputs to the
AD9826 are to be referenced to ground, or a dc offset voltage
should be applied to the OFFSET pin in the case where a coarse
offset needs to be removed from the inputs. (See Figure 16 and
the Circuit Operation section for more details.)
GAIN – dB
4
0
GAIN –V/V
0
12
24
36
48
60 63
PGA REGISTERVALUE – Decimal
Figure 17. PGA Gain Transfer Function
5V
0.1F
RED INPUT
CLOCK
INPUTS
0.1F
0.1F
GREEN INPUT
CDSCLK1
1
AVDD
AVSS
VINR
28
27
26
25
24
23
22
CDSCLK2
2
ADCCLK
3
0.1F
BLUE INPUT
OEB
OFFSET
VING
5V/3V
4
DRVDD
0.1F
0.1F
10F
0.1F
1.0F
5
0.1F
DRVSS
CML
0.1F
6
7
(MSB) D7
D6
AD9826
TOP VIEW
VINB
CAPT
CAPB
AVSS
AVDD
SLOAD
SCLK
SDATA
8
(Not to Scale) 21
0.1F
D5
9
20
19
18
17
16
15
D4
10
11
12
13
14
D3
0.1F
D2
D1
5V
(LSB)D0
DATA
INPUTS
SERIAL
INTERFACE
Figure 18. Recommended Circuit Configuration, 3-Channel CDS Mode
REV. A
–18–
AD9826
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-Lead 5.3 m m SSO P
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
14
1
0.07 (1.79)
0.078 (1.98)
PIN 1
0.066 (1.67)
0.068 (1.73)
0.03 (0.762)
8°
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0°
0.022 (0.558)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
Revision History
Location
P age
D ata Sheet changed fr om REV. 0 to REV. A.
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Edits to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
REV. A
–19–
–20–
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