AD9830AST [ADI]
CMOS Complete DDS; CMOS DDS完成
| 型号： | AD9830AST |
| 厂家： | 
ADI |
| 描述： | CMOS Complete DDS |
| 文件： | 总16页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS
Complete DDS
a
AD9830
FEATURES
GENERAL D ESCRIP TIO N
+5 V Pow er Supply
50 MHz Speed
On-Chip SINE Look-Up Table
On-Chip 10-Bit DAC
Parallel Loading
T his DDS device is a numerically controlled oscillator em-
ploying a phase accumulator, a sine look-up table and a
10-bit D/A converter integrated on a single CMOS chip.
Modulation capabilities are provided for phase modulation
and frequency modulation.
Pow er-Dow n Option
72 dB SFDR
250 m W Pow er Consum ption
48-Pin TQFP
Clock rates up to 50 MHz are supported. Frequency accu-
racy can be controlled to one part in 4 billion. Modulation
is effected by loading registers through the parallel micro-
processor interface.
APPLICATIONS
DDS Tuning
Digital Dem odulation
A power-down pin allows external control of a power-down
mode. The part is available in a 48-pin TQFP package.
FUNCTIO NAL BLO CK D IAGRAM
AVDD AGND REFOUT
FS ADJUST REFIN
DVDD DGND
MCLK
ON-BOARD
FULL SCALE
CONTROL
REFERENCE
COMP
FSELECT
12
FREQ0 REG
FREQ1 REG
IOUT
PHASE
ACCUMULATOR
(32-BIT)
SIN
ROM
10-BIT DAC
MUX
Σ
IOUT
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
AD9830
MUX
SLEEP
RESET
PARALLEL REGISTER
TRANSFER CONTROL
MPU INTERFACE
D0
D15
A0
A1
A2
PSEL0
PSEL1
WR
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
(V = +5 V ؎ 5%; AGND = DGND = 0 V; T = TMIN to T ; REFIN = REFOUT;
R = 1 k⍀; RLOAD = 51 ⍀ for IOUT and IOUT unless otherwise noted)
SET
1
DD
A
MAX
AD9830–SPECIFICATIONS
P aram eter
AD 9830A
Units
Test Conditions/Com m ents
SIGNAL DAC SPECIFICAT IONS
Resolution
10
50
20
1
Bits
Update Rate (fMAX
IOUT Full Scale
)
MSPS max
mA max
V max
Output Compliance
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
±1
±0.5
LSB typ
LSB typ
DDS SPECIFICAT IONS2
Dynamic Specifications
Signal-to-Noise Ratio
T otal Harmonic Distortion
Spurious Free Dynamic Range (SFDR)3
Narrow Band
50
–53
dB min
dBc max
fMCLK = fMAX , fOUT = 2 MHz
fMCLK = fMAX , fOUT = 2 MHz
fMCLK = 6.25 MHz, fOUT = 2.11 MHz
(±50 kHz)
(±200 kHz)
Wide Band (±2 MHz)
Clock Feedthrough
Wake Up T ime
–72
–68
–50
–55
1
dBc min
dBc min
dBc min
dBc typ
ms typ
Power-Down Option
Yes
VOLT AGE REFERENCE
Internal Reference @ +25°C
T MIN to TMAX
REFIN Input Impedance
Reference T C
1.21
1.21 ± 7%
10
100
300
Volts typ
Volts min/max
MΩ typ
ppm/°C typ
Ω typ
REFOUT Impedance
LOGIC INPUT S
V
V
INH, Input High Voltage
INL, Input Low Voltage
VDD–0.9
0.9
10
V min
V max
µA max
pF max
I
INH, Input Current
CIN, Input Capacitance
10
POWER SUPPLIES
fOUT = 2 MHz
AVDD
DVDD
IAA
4.75/5.25
4.75/5.25
25
V min/V max
V min/V max
mA max
IDD
6 + 0.5/MHz
mA typ
mA max
mA typ
mA max
4
I
AA + IDD
60
0.25
1
Low Power Sleep Mode5
1 MΩ Resistor T ied Between
REFOUT and AGND
NOT ES
1Operating temperature range is as follows: A Version: –40 °C to +85°C.
2All dynamic specifications are measured using IOUT . 100% production tested.
3fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, fOUT = 2.11 MHz.
4Measured with the digital inputs static and equal to 0 V or DVDD.
5T he Low Power Sleep Mode current is 2 mA typically when a 1 M Ω resistor is
not tied from REFOUT to AGND.
R
10nF
SET
1kΩ
REFOUT
ON-BOARD
REFIN
FS
ADJUST
AVDD
10nF
COMP
REFERENCE
FULL-SCALE
CONTROL
T he AD9830 is tested with a capacitive load of 50 pF. T he part can be operated
with higher capacitive loads, but the magnitude of the analog output will be attenu-
ated. For example, a 10 MHz output signal will be attenuated by 3 dB when the
load capacitance equals 250 pF.
IOUT
12
SIN
10-BIT
ROM
DAC
51Ω
50pF
50pF
Specifications subject to change without notice.
IOUT
51Ω
Figure 1. Test Circuit with Which Specifications Are
Tested
–2–
REV. A
AD9830
(V = +5 V ؎ 5%; AGND = DGND = 0 V, unless otherwise noted)
DD
TIMING CHARACTERISTICS
Lim it at
TMIN to TMAX
P aram eter
(A Version)
Units
Test Conditions/Com m ents
t1
t2
20
8
8
8
8
8
t1
5
3
8
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MCLK Period
MCLK High Duration
MCLK Low Duration
WR Rising Edge Before MCLK Rising Edge
WR Rising Edge After MCLK Rising Edge
WR Pulse Width
Duration Between Consecutive WR Pulses
Data/Address Setup T ime
t31
t4
1
t4A
t5
t6
t7
t81
Data/Address Hold T ime
t9
FSELECT , PSEL0, PSEL1 Setup T ime Before MCLK Rising Edge
FSELECT , PSEL0, PSEL1 Setup T ime After MCLK Rising Edge
RESET Pulse Duration
1
t9A
t10
8
t1
NOT ES
1See Pin Description section.
Guaranteed by design, but not production tested.
t
1
MCLK
t
4
t
t
3
2
t
5
t
WR
4A
t
6
Figure 2. WR–MCLK Relationship
t
6
t
5
WR
t
8
t
7
A0, A1, A2
DATA
VALID DATA
VALID DATA
Figure 3. Writing to a Phase/Frequency Register
MCLK
t
9A
t
9
FSELECT
PSEL0, PSEL1
VALID DATA
VALID DATA
VALID DATA
t
10
RESET
Figure 4. Control Tim ing
–3–
REV. A
AD9830
Maximum Junction T emperature . . . . . . . . . . . . . . . . +150°C
T QFP θJA T hermal Impedance . . . . . . . . . . . . . . . . . 75°C/W
Lead T emperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ABSO LUTE MAXIMUM RATINGS*
(
T A = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating T emperature Range
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
O RD ERING GUID E
Model
Tem perature Range
P ackage O ption*
AD9830AST
–40°C to +85°C
ST -48
*ST = T hin Quad Flatpack (T QFP).
P IN CO NFIGURATIO N
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
REFIN
REFOUT
SLEEP
DVDD
36 AGND
PIN 1
IDENTIFIER
35
RESET
34
A0
33 A1
DVDD
32
31
30
29
28
27
26
25
A2
AD9830
TOP VIEW
(Not to Scale)
DGND
DB0
DB1
DGND
DB2
DB3
DB4
DVDD
MCLK
WR
DVDD
FSELECT 10
11
PSEL0
PSEL1 12
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
–4–
REV. A
AD9830
P IN D ESCRIP TIO N
Mnem onic
Function
P O WER SUP P LY
AVDD
Positive power supply for the analog section. A 0.1 µF capacitor should be connected between AVDD and
AGND. AVDD has a value of +5 V ± 5%.
AGND
DVDD
Analog Ground.
Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between DVDD
and DGND. DVDD has a value of +5 V ± 5%.
DGND
Digital Ground.
ANALO G SIGNAL AND REFERENCE
IOUT , IOUT
Current Output. T his is a high impedance current source. A load resistor should be connected between IOUT
and AGND. IOUT should be either tied directly to AGND or through an external load resistor to AGND.
FS ADJUST
Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. T his determines the mag-
nitude of the full-scale DAC current. T he relationship between RSET and the full-scale current is as follows:
IOUTFULL-SCALE = 16 VREFIN/RSET
VREFIN = 1.21 V nominal, RSET = 1 kΩ typical
REFIN
Voltage Reference Input. T he AD9830 can be used with either the on-board reference, which is available from pin
REFOUT , or an external reference. T he reference to be used is connected to the REFIN pin. T he AD9830 ac-
cepts a reference of 1.21 V nominal.
REFOUT
COMP
Voltage Reference Output. T he AD9830 has an on-board reference of value 1.21 V nominal. T he reference is
made available on the REFOUT pin. T his reference is used as the reference to the DAC by connecting REFOUT
to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
Compensation pin. T his is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
D IGITAL INTERFACE AND CO NTRO L
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. T he
output frequency accuracy and phase noise are determined by this clock.
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase ac-
cumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an
MCLK rising edge occurs. If FSELECT changes value when an MCLK rising edge occurs, there is an uncertainty
of one MCLK cycle as to when control is transferred to the other frequency register. T o avoid any uncertainty, a
change on FSELECT should not coincide with an MCLK rising edge.
WR
Write, Edge-T riggered Digital Input. T he WR pin is used when writing data to the AD9830. T he data is loaded
into the AD9830 on the rising edge of the WR pulse. T his data is then loaded into the destination register on the
MCLK rising edge. T he WR pulse rising edge should not coincide with the MCLK rising edge as there will be an
uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. T he WR ris-
ing edge should occur before an MCLK rising edge. T he data will then be transferred into the destination register
on the MCLK rising edge. Alternatively, the WR rising edge can occur after the MCLK rising edge and the desti-
nation register will be loaded on the next MCLK rising edge.
D0–D15
A0–A2
Data Bus, Digital Inputs for destination registers.
Address Digital Inputs. T hese address bits are used to select the destination register to which the digital data is to
be written.
PSEL0, PSEL1 Phase Select Input. T he AD9830 has four phase registers. T hese registers can be used to alter the value being in-
put to the SIN ROM. T he contents of the phase register can be added to the phase accumulator output, the inputs
PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, the AD9830 samples the
PSEL0 and PSEL1 inputs on the MCLK rising edge. T herefore, these inputs should be in steady state at the
MCLK rising edge or, there is an uncertainty of one MCLK cycle as to when control is transferred to the selected
phase register.
SLEEP
Low Power Control, active low digital input. SLEEP puts the AD9830 into a low power mode. Internal clocks
are disabled and the DAC’s current sources and REFOUT are turned off. T he AD9830 is re-enabled by taking
SLEEP high.
RESET
Reset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analog
output of midscale.
–5–
REV. A
AD9830
TERMINO LO GY
O utput Com pliance
T he output compliance refers to the maximum voltage which
can be generated at the output of the DAC to meet the specifi-
cations. When voltages greater than that specified for the out-
put compliance are generated, the AD9830 may not meet the
specifications listed in the data sheet. For the AD9830, the
maximum voltage which can be generated by the DAC is 1V.
Integr al Nonlinear ity
T his is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. T he
endpoints of the transfer function are zero scale, a point 0.5
LSB below the first code transition (000 . . . 00 to 000 . . . 01)
and full scale, a point 0.5 LSB above the last code transition
(111 . . . 10 to 111 . . . 11). T he error is expressed in LSBs.
Spur ious Fr ee D ynam ic Range
Along with the frequency of interest, harmonics of the funda-
mental frequency and images of the MCLK frequency will be
present at the output of a DDS device. T he spurious free dy-
namic range (SFDR) refers to the largest spur or harmonic
which is present in the band of interest. T he wideband SFDR
gives the magnitude of the largest harmonic or spur relative to
the magnitude of the fundamental frequency in the bandwidth
±2 MHz about the fundamental frequency. T he narrowband
SFDR gives the attenuation of the largest spur or harmonic in a
bandwidth of ±200 kHz and ±50 kHz about the fundamental
frequency.
D iffer ential Nonlinear ity
T his is the difference between the measured and the ideal 1 LSB
change between two adjacent codes in the DAC.
Signal to (Noise + D istor tion)
Signal to (Noise + Distortion) is measured signal to noise at the
output of the DAC. T he signal is the rms magnitude of the fun-
damental. Noise is the rms sum of all the nonfundamental sig-
nals up to half the sampling frequency (fMCLK/2) but excluding
the dc component. Signal to (Noise + Distortion) is dependent
on the number of quantization levels used in the digitization
process; the more levels, the smaller the quantization noise.
T he theoretical Signal to (Noise + Distortion) ratio for a sine
wave input is given by
Clock Feedthr ough
T here will be feedthrough from the MCLK input to the analog
output. T he clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
AD9830’s output spectrum.
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
where N is the number of bits. T hus, for an ideal 10-bit con-
verter, Signal to (Noise + Distortion) = 61.96 dB.
Total H ar m onic D istor tion
T otal Harmonic Distortion (T HD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD9830, T HD is defined as
2
2
2
2
2
(V2 +V3 +V4 +V5 +V6
THD = 20log
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
–6–
REV. A
Typical Performance Characteristics–AD9830
–35
60
55
50
45
40
35
30
50MHz
AVDD = DVDD = +5V
T
f
= +25°C
–40
A
= 200kHz
OUT
–45
30MHz
–50
10MHz
–55
–60
AVDD = DVDD = +5V
–65
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
10
20
30
40
50
f
/f
OUT MCLK
MCLK FREQUENCY – MHz
Figure 8. WB SFDR vs. fOUT/fMCLK for Various MCLK
Frequencies
Figure 5. Typical Current Consum ption vs. MCLK
Frequency
60
–50
AVDD = DVDD = +5V
AVDD = DVDD = +5V
f
/f = 1/3
OUT MCLK
f
= f /3
OUT
MCLK
–55
–60
–65
–70
–75
–80
55
50
45
40
10
20
30
40
50
10
20
30
40
50
MCLK FREQUENCY – MHz
MCLK FREQUENCY – MHz
Figure 9. SNR vs. MCLK Frequency
Figure 6. Narrow Band SFDR vs. MCLK Frequency
–40
60
55
50
45
40
AVDD = DVDD = +5V
AVDD = DVDD = +5V
f
/f = 1/3
OUT MCLK
–45
–50
–55
–60
–65
10MHz
30MHz
50MHz
0
0.1
0.2
0.3
0.4
10
20
30
MCLK FREQUENCY – MHz
40
50
f
/f
OUT MCLK
Figure 10. SNR vs. fOUT/fMCLK for Various MCLK
Frequencies
Figure 7. Wide Band SFDR vs. MCLK Frequency
–7–
REV. A
AD9830
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–80
–90
–90
START 0Hz
RBW 1kHz
STOP 25MHz
ST 50 SEC
START 0Hz
STOP 25MHz
ST 50 SEC
VBW 3kHz
RBW 1kHz
VBW 3kHz
Figure 11. fMCLK = 50 MHz, fOUT = 2.1 MHz, Frequency
Word = ACO8312
Figure 14. fMCLK = 50 MHz, fOUT = 9.1 MHz, Frequency
Word = 2E978D50
0
0
–10
–10
–20
–30
–40
–50
–60
–70
–80
–90
–20
–30
–40
–50
–60
–70
–80
–90
START 0Hz
RBW 1kHz
STOP 25MHz
ST 50 SEC
START 0Hz
RBW 1kHz
STOP 25MHz
ST 50 SEC
VBW 3kHz
VBW 3kHz
Figure 12. fMCLK = 50 MHz, fOUT = 3.1 MHz, Frequency
Word = FDF3B64
Figure 15. fMCLK = 50 MHz, fOUT = 11.1 MHz, Frequency
Word = 38D4FDF4
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
START 0Hz
RBW 1kHz
STOP 25MHz
ST 50 SEC
START 0Hz
RBW 1kHz
STOP 25MHz
ST 50 SEC
VBW 3kHz
VBW 3kHz
Figure 13. fMCLK = 50 MHz, fOUT = 7.1 MHz, Frequency
Word = 245A1CAC
Figure 16. fMCLK = 50 MHz, fOUT = 13.1 MHz, Frequency
Word = 43126E98
–8–
REV. A
AD9830
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
START 0Hz
STOP 25MHz
ST 50 SEC
RBW 1kHz
VBW 3kHz
Figure 17. fMCLK = 50 MHz, fOUT = 16.5 MHz, Frequency
Word = 547AE148
Register
Size
D escription
A2
A1
A0
D estination Register
FREQ0 REG
32 Bits
Frequency Register 0. T his defines
the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FREQ0 REG 16 LSBs
FREQ0 REG 16 MSBs
FREQ1 REG 16 LSBs
FREQ1 REG 16 MSBs
PHASE0 REG
FREQ1 REG
32 Bits
Frequency Register 1. T his de-
fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
PHASE1 REG
PHASE2 REG
PHASE0 REG 12 Bits
PHASE1 REG 12 Bits
Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the out-
put of the phase accumulator.
PHASE3 REG
Figure 19. Addressing the Control Registers
Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the
contents of this register are added
to the output of the phase
accumulator.
D15
MSB
D0
LSB
Figure 20. Frequency Register Bits
PHASE2 REG 12 Bits
PHASE3 REG 12 Bits
Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the
contents of this register are added
to the output of the phase
accumulator.
D15 D14 D13 D12 D11
MSB
D0
X
X
X
X
LSB
X = Don't Care
Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the out-
put of the phase accumulator.
Figure 21. Phase Register Bits
Figure 18. AD9830 Control Registers
–9–
REV. A
AD9830
Num er ical Contr olled O scillator + P hase Modulator
CIRCUIT D ESCRIP TIO N
T his consists of two frequency select registers, a phase accumu-
lator and four phase offset registers. T he main component of
the NCO is a 32-bit phase accumulator which assembles the
phase component of the output signal. Continuous time signals
have a phase range of 0 to 2π. Outside this range of numbers,
the sinusoid functions repeat themselves in a periodic manner.
T he digital implementation is no different. T he accumulator
simply scales the range of phase numbers into a multibit digital
word. T he phase accumulator in the AD9830 is implemented
with 32 bits. T herefore, in the AD9830, 2π = 232. Likewise,
the ∆Phase term is scaled into this range of numbers 0 < ∆Phase
< 232 –1. Making these substitutions into the equation above
T he AD9830 provides an exciting new level of integration
for the RF/Communications system designer. T he AD9830
combines the Numerical Controlled Oscillator (NCO), SINE
Look-Up table, Frequency and Phase Modulators, and a
Digital-to-Analog Converter on a single integrated circuit.
T he internal circuitry of the AD9830 consists of three main
sections. T hese are:
Numerical Controlled Oscillator (NCO) + Phase Modulator
SINE Look-Up T able
Digital-to-Analog Converter
T he AD9830 is a fully integrated Direct Digital Synthesis
(DDS) chip. T he chip requires one reference clock, two low
precision resistors and eight decoupling capacitors to provide
digitally created sine waves up to 25 MHz. In addition to the
generation of this RF signal, the chip is fully capable of a broad
range of simple and complex modulation schemes. T hese
modulation schemes are fully implemented in the digital do-
main allowing accurate and simple realization of complex
modulation algorithms using DSP techniques.
f = ∆Phase × fMCLK/232
where 0 < ∆Phase < 232
With a clock signal of 50 MHz and a phase word of 051EB852
hex
f = 51EB852 × 50 MHz/232 = 1.000000000931 MHz
T he input to the phase accumulator (i.e., the phase step) can be
selected either from the FREQ0 Register or FREQ1 Register
and this is controlled by the FSELECT pin. NCOs inherently
generate continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies. More com-
plex frequency modulation schemes can be implemented by up-
dating the contents of these registers. T his facilitates complex
frequency modulation schemes, such as GMSK.
TH EO RY O F O P ERATIO N
Sine waves are typically thought of in terms of their magnitude
form a (t) = sin (ωt). However, these are nonlinear and not
easy to generate except through piece wise construction. On
the other hand, the angular information is linear in nature.
T hat is, the phase angle rotates through a fixed angle for each
unit of time. T he angular rate depends on the frequency of the
signal by the traditional rate of ω = 2πf
Following the NCO, a phase offset can be added to perform
phase modulation using the 12-bit PHASE Registers. The con-
tents of this register are added to the most significant bits of the
NCO. T he AD9830 has four PHASE registers. T he resolution
of the phase registers equals 2π/4096.
MAGNITUDE
+1
Sine Look-Up Table (LUT)
0
T o make the output useful, the signal must be converted from
phase information into a sinusoidal value. Since phase informa-
tion maps directly into amplitude, a ROM LUT converts the
phase information into amplitude. T o do this, the digital phase
information is used to address a sine ROM LUT . Although the
NCO contains a 32-bit phase accumulator, the output of the
NCO is truncated to 12 bits. Using the full resolution of the
phase accumulator is impractical and unnecessary as this would
require a look-up table of 232 entries.
–1
PHASE
2
π
0
Figure 22. Sine Wave
It is necessary only to have sufficient phase resolution in the
LUT s such that the dc error of the output waveform is domi-
nated by the quantization error in the DAC. T his requires the
look-up table to have two more bits of phase resolution than the
10-bit DAC.
Knowing that the phase of a sine wave is linear and given a ref-
erence interval (clock period), the phase rotation for that period
can be determined.
∆Phase = ωδt
Solving for ω
D igital-to-Analog Conver ter
T he AD9830 includes a high impedance current source 10-bit
DAC, capable of driving a wide range of loads at different
speeds. Full-scale output current can be adjusted, for optimum
power and external load requirements, through the use of a
single external resistor (RSET ).
ω = ∆Phase/δt = 2πf
Solving for f and substituting the reference clock frequency for
the reference period (1/fMCLK = δt)
f = ∆Phase × fMCLK/2π
T he DAC can be configured for single or differential ended op-
eration. IOUT can be tied directly to AGND for single ended
operation or through a load resistor to develop an output volt-
age. T he load resistor can be any value required, as long as the
T he AD9830 builds the output based on this simple equation.
A simple DDS chip can implement this equation with three
major subcircuits.
–10–
REV. A
AD9830
FSELECT , PSEL0 and PSEL1 are sampled on the MCLK
rising edge. Again, these inputs should be valid when an
MCLK rising edge occurs as there will be an uncertainty of one
MCLK cycle introduced otherwise. When these inputs change
value, there will be a pipeline delay before control is transferred
to the selected register—there will be a pipeline delay before the
analog output is controlled by the selected register. Similarly,
there is a delay when a new word is written to a register. PSEL0,
PSEL1, FSELECT and WR have latencies of six MCLK cycles.
full-scale voltage developed across it does not exceed the voltage
compliance range. Since full-scale current is controlled by RSET
adjustments to RSET can balance changes made to the load resistor.
However, if the DAC full-scale output current is significantly less
than 20 mA, the linearity of the DAC may degrade.
,
D SP and MP U Inter facing
T he AD9830 has a parallel interface, with 16 bits of data being
loaded during each write cycle.
T he frequency or phase registers are loaded by asserting the WR
signal. T he destination register for the 16-bit data is selected
using the address inputs A0, A1 and A2. T he phase registers
are 12 bits wide so, only the 12 LSBs need to be valid—the
4 MSBs of the 16 bit word do not have to contain valid data.
Data is loaded into the AD9830 by pulsing WR low, the data
being latched into the AD9830 on the rising edge of WR. T he
values of inputs A0, A1 and A2 are also latched into the
AD9830 on the WR rising edge. T he appropriate register is up-
dated on the next MCLK rising edge. T o ensure that the
AD9830 contains valid data at the rising edge of MCLK, the
rising edge of the WR pulse should not coincide with the rising
MCLK edge. T he WR pulse must occur several nanoseconds
before the MCLK rising edge. If the WR rising edge occurs at
the MCLK rising edge, there is an uncertainty of one MCLK
cycle regarding the loading of the destination register—the desti-
nation register may be loaded with the new data immediately or
the destination register may be updated on the next MCLK ris-
ing edge. T o avoid any uncertainty, the times listed in the speci-
fications should be complied with.
T he flow chart in Figure 23 shows the operating routine for the
AD9830. When the AD9830 is powered up, the part should be
reset using RESET. T his will reset the phase accumulator to
zero so that the analog output is at midscale. RESET does not
reset the phase and frequency registers. These registers will con-
tain invalid data and, therefore, should be set to zero by the user.
T he registers to be used should be loaded, the analog output be-
ing fMCLK/232 × FREG where FREG is the value contained in
the selected frequency register. T his signal will be phase shifted
by an amount 2π/4096 × PHASEREG where PHASEREG is the
value contained in the selected phase register. When FSELECT ,
PSEL0 and PSEL1 are programmed, there will be a pipeline de-
lay of approximately 6 MCLK cycles before the analog output
reacts to the change on these inputs.
RESET
DATA WRITE
FREG<0, 1> = 0
PHASEREG<0, 1, 2, 3> = 0
DATA WRITE
32
32
FREG<0> = f 0/f
OUT MCLK
*2
*2
FREG<1> = f 1/f
OUT MCLK
PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3>
SELECT DATA SOURCES
SET FSELECT
SET PSEL0, PSEL1
WAIT 6 MCLK CYCLES
DAC OUTPUT
32 12
*t/2 + PHASEREG/2 )))
MCLK
V
= V
*8*R
/R
(1 + SIN(2π(FREG*f
OUT
REFIN
OUT SET*
YES
CHANGE PHASE?
NO
NO
NO
CHANGE FOUT?
YES
NO
CHANGE PHASEREG?
YES
CHANGE PSEL0, PSEL1
CHANGE FREG?
YES
CHANGE FSELECT
Figure 23. Flow Chart for AD9830 Initialization and Operation
–11–
REV. A
AD9830
AP P LICATIO NS
related to the bit stream being input to the modulator. T he
presence of four shift registers eases the interaction needed
between the DSP and the AD9830.
T he AD9830 contains functions which make it suitable for
modulation applications. T he part can be used to perform
simple modulation such as FSK. More complex modulation
schemes such as GMSK and QPSK can also be implemented
using the AD9830. In a FSK application, the two frequency reg-
isters of the AD9830 are loaded with different values, one fre-
quency will represent the space frequency while the other will
represent the mark frequency. T he digital data stream is fed to
the FSELECT pin which will cause the AD9830 to modulate
the carrier frequency between the two values.
T he frequency and phase registers can be written to continuously,
if required. T he maximum update rate equals the frequency of
the MCLK. However, if a selected register is loaded with a new
word, there will be a delay of 6 MCLK cycles before the analog
output will change accordingly.
T he AD9830 is also suitable for signal generator applications.
With its low current consumption, the part is suitable for
mobile applications in which it can be used as a local oscillator.
Figure 24 shows the interface between the AD9830 and AD6459
which is a down converter used on the receive side of mobile
phones or basestations.
T he AD9830 has four phase registers which enable the part to
perform PSK. With phase shift keying, the carrier frequency is
phase shifted, the phase being altered by an amount which is
AD9830
R
10 BITS
SET
1kΩ
FILTER
51Ω
51Ω
0.1µF
LOIP
IRxP
AD6459
RFHI
IRxN
MXOP
MXOM
IFIP
ANTENNA
0°
FREF
BANDPASS
FILTER
PLL
RFLO
FLTR
90°
IFIM
QRxP
MIDPOINT
BIAS
QRxN
GENERATOR
GAIN TC
GAIN
COMPENSATION
VPS1
VPS2
PRUP
GREF
BIAS
CIRCUIT
COM1 COM2
Figure 24. AD9830 and AD6459 Receiver Circuit
–12–
REV. A
AD9830
Gr ounding and Layout
AD 9830 Evaluation Boar d
T he printed circuit board that houses the AD9830 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. T his facilitates the
use of ground planes which can be separated easily. A mini-
mum etch technique is generally best for ground planes as it
gives the best shielding. Digital and analog ground planes
should only be joined in one place. If the AD9830 is the only
device requiring an AGND to DGND connection, then the
ground planes should be connected at the AGND and DGND
pins of the AD9830. If the AD9830 is in a system where mul-
tiple devices require AGND to DGND connections, the con-
nection should be made at one point only, a star ground point
that should be established as close as possible to the AD9830.
T he AD9830 Evaluation Board allows designers to evaluate the
high performance AD9830 DDS Modulator with a minimum of
effort.
T o prove that this device will meet the user’s waveform synthesis
requirements, the user only requires a +5 V power supply, an
IBM-compatible PC and a spectrum analyzer along with the
evaluation board. T he evaluation setup is shown below.
T he DDS Evaluation kit includes a populated, tested AD9830
printed circuit board along with software which controls the
AD9830 in a Windows environment.
IBM COMPATIBLE PC
PARALLEL PORT
CENTRONICS
Avoid running digital lines under the device as these will couple
noise onto the die. T he analog ground plane should be allowed
to run under the AD9830 to avoid noise coupling. T he power
supply lines to the AD9830 should use as large a track as is pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board. Avoid crossover of digital
and analog signals. T races on opposite sides of the board
should run at right angles to each other. T his will reduce the ef-
fects of feedthrough through the board. A microstrip technique
is by far the best but is not always possible with a double-sided
board. In this technique, the component side of the board is
dedicated to ground planes while signals are placed on the other
side.
PRINTER CABLE
AD9830.EXE
AD9830 EVALUATION
BOARD
Figure 25. AD9830 Evaluation Board Setup
Using the AD 9830 Evaluation Boar d
T he AD9830 Evaluation kit is a test system designed to simplify
the evaluation of the AD9830. Provisions to control the AD9830
from the printer port of an IBM-compatible PC are included
along with the necessary software. An application note is also
available with the evaluation board which gives information on
operating the evaluation board.
Good decoupling is important. T he analog and digital supplies
to the AD9830 are independent and separately pinned out to
minimize coupling between analog and digital sections of the
device. All analog and digital supplies should be decoupled to
AGND and DGND respectively with 0.1 µF ceramic capacitors
in parallel with 10 µF tantalum capacitors. T o achieve the best
from the decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against the device. In
systems where a common supply is used to drive both the AVDD
and DVDD of the AD9830, it is recommended that the system’s
AVDD supply be used. T his supply should have the recom-
mended analog supply decoupling between the AVDD pins of
the AD9830 and AGND and the recommended digital supply
decoupling capacitors between the DVDD pins and DGND.
P r ototyping Ar ea
An area is available on the evaluation board where the user can
add additional circuits to the evaluation test set. Users may
want to build custom analog filters for the outputs or add buf-
fers and operational amplifiers which are to be used in the final
application.
XO vs. Exter nal Clock
T he AD9830 can operate with master clocks up to 50 MHz. A
50 MHz oscillator is included on the evaluation board. How-
ever, this oscillator can be removed and an external CMOS
clock connected to the part, if required.
P ower Supply
Power to the AD9830 evaluation board must be provided exter-
nally through the pin connections. T he power leads should be
twisted to reduce ground loops.
–13–
REV. A
AD9830
DVDD
0.1µF
C1, C2, C3
AVDD
0.1µF
C4, C5
AVDD
DVDD
0.1µF
C13
1
2
3
4
5
6
7
8
10nF
C6
DVDD
4, 5, 9, 25
AVDD
38, 43
LATCH
U2
D0
D1
D2
D3
D4
D5
D6
D7
V
14
21
48
DD
D15
D8
COMP
REFIN
SMB5
DVDD
J1
74HC574
CK
1
PC INTERFACE
WR
LOAD
DVDD
LK5
RESET
LATCH
LOAD
D7
2
9
U3
REFOUT
0.1µF
C14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
10nF
V
J2
J3
DD
22
31
AVDD
D7
D0
C7
74HC574
CK
AD9830
D0
10µF
C9
0.1µF
C8
0.1µF
C10
10µF
C11
U1
RESET
LATCH
32
34
A2
A0
47
FSADJUST
1kΩ
R5
8
WR
WR
R1
R2
R3
35
10kΩ 10kΩ 10kΩ
RESET
RESET
12
11
LK1
SMB1
SMB2
SMB3
SMB6
PSEL1
PSEL0
44
45
IOUT
LK2
51Ω
R6
10
7
FSELECT
MCLK
LK3
SMB7
MCLK
DVDD
IOUT
3
51Ω
R7
SLEEP
DGND
AGND
LOAD
6,13, 29
36, 39, 41, 46
DVDD
SW
LK4
SMB4
WR
DVDD
R4
50Ω
U4
DVDD
C12
0.1µF
OUT
XTAL1
DGND
Figure 26. Evaluation Board Layout
CO MP O NENT LIST
Integrated Circuits
U1
U2, U3
XT AL1
Links
LK5
T wo Pin Link
T hree Pin Link
AD9830 (48-Pin T QFP)
74HC574 Latches
OSC XT AL 50 MHz
LK1, LK2, LK3, LK4
Switch
SW
End Stackable Switch (SDC
Double T hrow)
Capacitor s
C9, C11
C8, C10, C12–C14
C1–C5
10 µF T antalum Capacitor
0.1 µF Ceramic Capacitor
0.1 µF Ceramic Chip Capacitor
10 nF Ceramic Capacitor
Sockets
SMB1–SMB7
Sub-Miniature BNC Connector
Connector s
J2, J3
J1
C6, C7
PCB Mounting T erminal Block
36-Pin Edge Connector
Resistor s
R5
R6, R7
R4
1 kΩ Resistor
51 Ω Resistor
50 Ω Resistor
10 kΩ Resistor
R1–R3
–14–
REV. A
AD9830
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
48-Lead TQFP
(ST-48)
0.063 (1.60) MAX
0.354 (9.00) BSC
0.276 (7.0) BSC
0.057 (1.45)
0.030 (0.75)
0.053 (1.35)
0.018 (0.45)
37
36
48
1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.006 (0.15)
12
13
25
24
0.002 (0.05)
0° MIN
0° – 7°
0.007 (0.18)
0.004 (0.09)
0.011 (0.27)
0.006 (0.17)
0.019 (0.5)
BSC
–15–
REV. A
–16–
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