AD9840AJSTZRL [ADI]
Complete 10-Bit 40 MSPS CCD Signal Processor; 完整的10位， 40 MSPS CCD信号处理器
| 型号： | AD9840AJSTZRL |
| 厂家： | 
ADI |
| 描述： | Complete 10-Bit 40 MSPS CCD Signal Processor |
| 文件： | 总16页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete 10-Bit 40 MSPS
CCD Signal Processor
a
AD9840A
PRODUCT DESCRIPTION
FEATURES
The AD9840A is a complete analog signal processor for CCD
applications. It features a 40 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9840A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally controlled variable gain amplifier (VGA), black level
clamp, and 10-bit A/D converter. Additional input modes are
provided for processing analog video signals.
40 MSPS Correlated Double Sampler (CDS)
4 dB ꢀ 6 dB Variable CDS Gain with 6-Bit Resolution
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit 40 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 155 mW @ 3.0 V Supply
48-Lead LQFP Package
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment,
black level adjustment, input configuration, and power-down modes.
APPLICATIONS
The AD9840A operates from a 3 V power supply, typically
dissipates 155 mW, and is packaged in a 48-lead LQFP.
Digital Video Camcorders
Digital Still Cameras
Industrial Imaging
FUNCTIONAL BLOCK DIAGRAM
PBLK
CLPOB
AVDD
AVSS
DRVDD
CLP
4dBꢀ6dB
DRVSS
2dB TO 36dB
CDS
CCDIN
10
2:1
MUX
10-BIT
ADC
DOUT
VGA
CLP
VRT
VRB
BANDGAP
CLPDM
AUX1IN
REFERENCE
OFFSET
DAC
10
2:1
MUX
BUF
INTERNAL
BIAS
6
CML
AUX2IN
8
INTERNAL
REGISTERS
CLP
DVDD
DVSS
DIGITAL
INTERFACE
INTERNAL
TIMING
AD9840A
SHP
SHD DATACLK
SL
SCK
SDATA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD9840A–SPECIFICATIONS
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.)
GENERAL SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
–20
–65
+85
+150
°C
°C
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver
2.7
3.6
V
POWER CONSUMPTION
Normal Operation
Power-Down Modes
Fast Recovery Mode
Standby
(Specified Under Each Mode of Operation)
90
5
1
mW
mW
mW
Total Power-Down
MAXIMUM CLOCK RATE
40
10
MHz
A/D CONVERTER
Resolution
Bits
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
Data Output Coding
0.5
2.0
1.0
LSB
Bits Guaranteed
V
10
Straight Binary
VOLTAGE REFERENCE
Reference Top Voltage (VRT)
Reference Bottom Voltage (VRB)
2.0
1.0
V
V
Specifications subject to change without notice.
(DRVDD = 2.7 V, CL = 20 pF unless otherwise noted.)
DIGITAL SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.1
V
V
µA
µA
pF
0.6
10
10
10
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA
Low Level Output Voltage, IOL = 2 mA
VOH
VOL
2.2
V
V
0.5
Specifications subject to change without notice.
REV. 0
–2–
AD9840A
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 40 MHz, unless otherwise noted.)
CCD-MODE SPECIFICATIONS
Parameter
OWER CONSUMPTION
Min
Typ
Max
Unit
mW
Notes
P
155
MAXIMUM CLOCK RATE
20
MHz
CDS
Allowable CCD Reset Transient1
Max CCD Black Pixel Amplitude1
Max Input Range before Saturation1
Max Input Range before Saturation
Max Input Range before Saturation
Max Output Range
500
200
mV
mV
V p-p
V p-p
V p-p
V p-p
Steps
See Input Waveform in Note 1
1.0
1.6
With 4 dB CDS Gain
With –2 dB CDS Gain
With 10 dB CDS Gain
At Any CDS Gain Setting
1.5
0.5
Gain Resolution
64
Gain Range (Two’s Complement Coding)
Min Gain (CDS Gain Register Code 32)
Medium Gain (CDS Gain Code 63)
Max Gain (CDS Gain Code 31)
See Figure 15 for CDS Gain Curve
–2
4
10
dB
dB
dB
4 dB is Default with CDS Gain Disabled
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
1.6
2.0
V p-p
V p-p
Steps
Gain Control Resolution
1024
Gain Monotonicity
Guaranteed
Gain Range
Low Gain (VGA Register Code 91)
Max Gain (VGA Code 1023)
See Figure 13 for VGA Gain Curve
See Page 12 for Gain Equations
2
36
dB
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
256
Steps
Measured at ADC Output
Min Clamp Level
Max Clamp Level
0
LSB
LSB
63.75
SYSTEM PERFORMANCE
Gain Accuracy, VGA Code 91 to 1023
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Specifications Include Entire Signal Chain
Use Equations on Page 12 to Calculate Gain
12 dB Gain Applied (4 dB CDS Gain)
–1.0
+1.0
dB
%
0.4
0.25
40
LSB rms AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR)
dB
Measured with Step Change on Supply
POWER-UP RECOVERY TIME
From Fast Recovery Mode
From Reference Standby Mode
From Total Shutdown Mode
From Power-Off Condition
Clocks Must Be Applied, as in Figures 8 and 9
0.1
1
3
ms
ms
ms
ms
15
NOTES
1Input Signal Characteristics defined as follows, with 4 dB CDS gain:
500mV TYP
RESET
TRANSIENT
1V MAX
200mV MAX
OPTICAL
INPUT
SIGNAL RANGE
BLACK PIXEL
Specifications subject to change without notice.
REV. 0
–3–
AD9840A–SPECIFICATIONS
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.)
AUX1-MODE SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
mW
POWER CONSUMPTION
MAXIMUM CLOCK RATE
105
40
MHz
INPUT BUFFER
Gain
0
dB
Max Input Range
1.0
2.0
V p-p
VGA
Max Output Range
Gain Control Resolution
Gain (Selected Using VGA Gain Register)
Min Gain
V p-p
Steps
1023
0
36
dB
dB
Max Gain
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 40 MHz, unless otherwise noted.)
AUX2-MODE SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
mW
POWER CONSUMPTION
MAXIMUM CLOCK RATE
INPUT BUFFER
105
40
MHz
(Same as AUX1-MODE)
512
VGA
Max Output Range
Gain Control Resolution
Gain (Selected Using VGA Gain Register)
Min Gain
2.0
V p-p
Steps
0
18
dB
dB
Max Gain
ACTIVE CLAMP
Clamp Level Resolution
Clamp Level (Measured at ADC Output)
Min Clamp Level
256
Steps
0
LSB
LSB
Max Clamp Level
63.75
Specification subject to change without notice.
REV. 0
–4–
AD9840A
(CL = 20 pF, fSAMP = 40 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 8–10.)
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
DATACLK Hi/Low Pulsewidth
SHP Pulsewidth
tCP
25
10
5
5
4
2
0
10
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
tADC
tSHP
tSHD
tCDM
tCOB
tS1
12.5
6
6
10
20
6
12.5
3.0
SHD Pulsewidth
CLPDM Pulsewidth
CLPOB Pulsewidth1
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
tS2
tID
Inhibited Clock Period
tINH
10
ns
DATA OUTPUTS
Output Delay
Output Hold Time
Pipeline Delay
tOD
tH
14.5
7.6
9
16
ns
ns
Cycles
7.0
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
NOTES
1Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS
With
Respect
To
Temperature
Range
Package
Description
Package
Option
Model
Parameter
Min Max
Unit
AD9840AJST –20°C to +85°C
Thin Plastic
Quad Flatpack
(LQFP)
ST-48
AVDD1, AVDD2
DVDD1, DVDD2
DRVDD
AVSS
DVSS
DRVSS –0.3 +3.9
–0.3 +3.9
–0.3 +3.9
V
V
V
Digital Outputs
SHP, SHD, DATACLK
CLPOB, CLPDM, PBLK DVSS
SCK, SL, SDATA
VRT, VRB, CMLEVEL
BYP1-4, CCDIN
Junction Temperature
Lead Temperature
(10 sec)
DRVSS –0.3 DRVDD + 0.3
V
V
V
V
V
V
°C
°C
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
DVSS
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
150
DVSS
AVSS
AVSS
θJA = 92°C
300
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9840A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
AD9840A
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
1
2
DRVSS
DRVSS
(LSB) D0
D1
36
35
34
33
32
31
30
29
28
27
26
25
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
PIN 1
IDENTIFIER
3
4
5
D2
AD9840A
TOP VIEW
(Not to Scale)
6
D3
NC
7
D4
CCDIN
BYP2
8
D5
9
D6
BYP1
10
11
D7
AVDD1
AVSS
AVSS
D8
12
(MSB) D9
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin Number
Name
Type
Description
1, 2
3–12
13
14
DRVSS
D0–D9
DRVDD
DRVSS
DVSS
P
DO
P
P
P
Digital Driver Ground
Digital Data Outputs
Digital Output Driver Supply
Digital Output Driver Ground
Digital Ground
15, 18, 24, 41
16
17
19
20
21
22
23
DATACLK
DVDD1
PBLK
CLPOB
SHP
SHD
CLPDM
AVSS
AVDD1
BYP1
BYP2
CCDIN
NC
BYP4
AVDD2
AUX2IN
AUX1IN
CML
VRT
VRB
DVDD2
THREE-STATE
NC
STBY
NC
DI
P
Digital Data Output Latch Clock
Digital Supply
Preblanking Clock Input
Black Level Clamp Clock Input
CDS Sampling Clock for CCD’s Reference Level
CDS Sampling Clock for CCD’s Data Level
Input Clamp Clock Input
DI
DI
DI
DI
DI
P
25, 26, 35
27
28
29
30
31
32
33
34
36
37
38
39
40
42
43
44
Analog Ground
Analog Supply
P
AO
AO
AI
NC
AO
P
AI
AI
AO
AO
AO
P
DI
NC
DI
NC
DI
DI
DI
Internal Bias Level. Decoupling
Internal Bias Level Decoupling
Analog Input for CCD Signal
Leave Floating or Decouple to Ground with 0.1 F
Internal Bias Level Decoupling
Analog Supply
Analog Input
Analog Input
Internal Bias Level Decoupling
A/D Converter Top Reference Voltage Decoupling
A/D Converter Bottom Reference Voltage Decoupling
Digital Supply
Digital Output Disable. Active High
May be tied High or Low. Should not be left floating.
Standby Mode, Active High. Same as Serial Interface Standby Mode
Internally Not Connected. May be tied high or low
Serial Digital Interface Load Pulse
Serial Digital Interface Data
45
46
47
48
SL
SDATA
SCK
Serial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. 0
–6–
AD9840A
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2N codes) when N is the bit resolution of the
ADC. For the AD9840A, 1 LSB is 2 mV.
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 10-bit
resolution indicates that all 1024 codes, respectively, must be
present over all operating conditions.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high-frequency disturbance on the
AD9840A’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
PEAK NONLINEARITY
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9840A from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level
1, 1/2 LSB beyond the last code transition. The deviation is mea-
sured from the middle of each particular output code to the true
straight line. The error is then expressed as a percentage of the 2 V
ADC full-scale signal. The input signal is always appropriately
gained up to fill the ADC’s full-scale range.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD9840A
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
EQUIVALENT INPUT CIRCUITS
DVDD
ACVDD
330ꢁ
ACVSS
ACVSS
DVSS
Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
Figure 3. CCDIN (Pin 30)
DVDD
DRVDD
DATA
DVDD
DVDD
DATA IN
330ꢁ
THREE-
STATE
DATA OUT
DOUT
RNW
DVSS
DVSS
DVSS
Figure 4. SDATA (Pin 47)
DVSS
DRVSS
Figure 2. Data Outputs
REV. 0
–7–
AD9840A
CCD-MODE AND AUX-MODE TIMING
CCD
SIGNAL
N
N+1
N+2
N+9
N+10
tID
tID
SHP
tS1
tCP
tS2
SHD
tINH
DATACLK
tOD
tH
OUTPUT
DATA
N–10
N–9
N–8
N–1
N
NOTES:
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
Figure 5. CCD-Mode Timing
HORIZONTAL
BLANKING
EFFECTIVE PIXELS
OPTICAL BLACK PIXELS
DUMMY PIXELS
EFFECTIVE PIXELS
CCD
SIGNAL
CLPOB
CLPDM
PBLK
OUTPUT
DATA
OB PIXEL DATA
DUMMY BLACK
EFFECTIVE DATA
EFFECTIVE PIXEL DATA
NOTES:
1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
Figure 6. Typical CCD-Mode Line Clamp Timing
N+9
N
N+1
N+8
N+2
VIDEO
SIGNAL
tID
tCP
DATACLK
tOD
tH
OUTPUT
DATA
N–10
N–9
N–8
N–1
N
Figure 7. AUX-Mode Timing
REV. 0
–8–
AD9840A
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
Table I. Internal Register Map
Register
Name
Address
A0 A1 A2
Data Bits
D4
D0
D1
D2
D3
D5
D6
D7
D8
D9
D10
Operation
0
0
0
Channel Select
CCD/AUX
Power-Down
Modes
Software OB Clamp 0*
Reset On/Off
1**
0*
0*
0*
VGA Gain
Clamp Level
Control
1
0
1
0
1
1
0
0
0
LSB
LSB
MSB
X
X
X
X
MSB
X
0*
0*
0*
CDS Gain Clock Polarity Select for
On/Off SHP/SHD/CLP/DATA
0*
0*
Three-
State
CDS Gain
0
0
1
LSB
MSB
X
X
X
X
X
*
Internal use only, must be set to zero. **Should be set to one.
RNW
0
TEST
0
SDATA
A0
A1
A2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
tDS
tDH
SCK
SL
tLS
tLH
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BIT = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
Figure 8. Serial Write Operation
RNW
1
TEST
SDATA
SCK
0
A0
tDH
A1
A2
D9
D0
tDV
D1
D2
D3
D4
D5
D6
D7
D8
D10
tDS
tLS
tLH
SL
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON SCK
FALLING EDGES.
Figure 9. Serial Readback Operation
11 BITS
10 BITS
8 BITS
10 BITS
OPERATION
AGC GAIN
CLAMP LEVEL
CONTROL
RNW A0
A1
0
...
...
...
...
SDATA
SCK
SL
0
0
0
0
D0 D1 D2 D3
D10 D0 D1 D2 D3
D9 D0
D9
44
D7 D0
...
...
...
...
2
3
4
5
6
7
8
9
16
17
18
19
20
26
34
35
27
1
...
NOTES:
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING
ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
Figure 10. Continuous Serial Write Operation to Multiple Registers
–9–
REV. 0
AD9840A
Table II. Operation Register Contents (Default Value x000)
Optical Black Clamp
D5
Reset
D4
Power-Down Modes
D3 D2
Channel Selection
D1 D0
D10
D9
D8
D7
**
D6
0
*
0
*
0
*
1
0
*
0
1
Enable Clamping
Disable Clamping
0 Normal
1 Reset all
Registers
0
0
1
1
0
1
0
1
Normal Power
Fast Recovery
Standby
0
0
1
0
1
0
1
CCD-Mode
AUX1-Mode
AUX2-Mode
Test Only
to Default
Total Power-Down 1
*Must be set to zero. **Set to one.
Table III. VGA Gain Register Contents (Default Value x096)
MSB
D9
LSB
D0
D10
D8
D7
D6
D5
D4
D3
D2
D1
Gain (dB)
X
0
0
0
1
0
1
•
1
1
1
1
2.0
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
35.965
36.0
Table IV. Clamp Level Register Contents (Default Value x080)
MSB
D7
LSB
D0
D10
D9
D8
D6
D5
D4
D3
D2
D1
Clamp Level (LSB)
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
•
0
0
0
0
0
0
0
0
1
0
1
0
0
0.25
0.5
•
•
•
•
1
1
•
1
1
1
1
1
1
1
1
1
1
1
1
0
1
63.5
63.75
Table V. Control Register Contents (Default Value x000)
Data Out
D9
DATACLK
D6
CLP/PBLK
D5
SHP/SHD
D4
CDS Gain
D3
D10
D8
D7
0*
D2 D1 D0
X
0 Enable
0*
0 Rising Edge Trigger
0 Active Low
0 Active Low 0 Disabled** 0*
0*
0*
1 Three-State
1 Falling Edge Trigger 1 Active High 1 Active High 1 Enabled
*Must be set to zero.
**When D3 = 0 (CDS Gain Disabled), the CDS Gain Register is fixed at 4 dB (code 63 dec).
Table VI. CDS Gain Register Contents (Default Value x000)
MSB
D5
LSB
D0
D10
D9
D8
D7
D6
D4
D3
D2
D1
Gain (dB)*
X
X
X
X
X
0
0
0
0
0
0
+4.3
•
•
•
•
•
•
0
1
1
0
1
0
1
0
1
0
0
0
+10.0
–2.0
•
•
•
•
•
•
1
1
1
1
1
1
+4.0
*Control Register Bit D3 must be set high for the CDS Gain Register to be used.
REV. 0
–10–
AD9840A
DC RESTORE
CDS GAIN
REGISTER
INTERNAL
V
6
REF
2dB TO 36dB
VGA
2V FULL SCALE
–2dB TO +10dB
0.1ꢂF
CCDIN
10
10-BIT
ADC
CDS
DOUT
INPUT OFFSET
CLAMP
CLPOB
OPTICAL BLACK
CLAMP
8-BIT
DAC
10
CLPDM
DIGITAL
FILTERING
0 TO 64 LSB
8
VGA GAIN
REGISTER
CLAMP LEVEL
REGISTER
Figure 11. CCD-Mode Block Diagram
CIRCUIT DESCRIPTION AND OPERATION
The AD9840A signal processing chain is shown in Figure 11.
Each processing step is essential in achieving a high-quality
image from the raw CCD pixel data.
Table VII. Example CDS Gain Settings
Recommended
Max Input Signal
Gain Range
Register Code Range
250 mV p-p
500 mV p-p
800 mV p-p
1 V p-p
1.25 V p-p
1.5 V p-p
8 dB to 10 dB
6 dB to 8 dB
4 dB to 6 dB
2 dB to 4 dB
0 dB to 2 dB
–2 dB to 0 dB
21 to 31
10 to 21
63 to 10
53 to 63
42 to 53
32 to 42
DC Restore
To reduce the large dc offset of the CCD output signal, a
dc-restore circuit is used with an external 0.1 µF series-coupling
capacitor. This restores the dc level of the CCD signal to approxi-
mately 1.5 V, to be compatible with the 3 V single supply of
the AD9840A.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low-frequency noise. The timing
shown in Figure 5 illustrates how the two CDS clocks, SHP
and SHD, are used to sample the reference level and data level
of the CCD signal respectively. The CCD signal is sampled on the
rising edges of SHP and SHD. Placement of these two clock
signals is critical in achieving the best performance from the CCD.
An internal SHP/SHD delay (tID) of 3 ns is caused by internal
propagation delays.
10
8
6
4
2
The CDS stage has a default gain of 4 dB, but uses a unique
architecture that allows the CDS gain to be varied. Using the
CDS Gain Register, the gain-of is programmable from –2 dB to
+10 dB in 64 steps, using two’s complement coding. The CDS
Gain curve is shown in Figure 12. To change the gain of the
CDS using the CDS Gain Register, the Control Register bit D3
must be set high (CDS Gain Enabled). The default gain setting
when bit Control Register Bit D3 is low (CDS Gain Disabled) is
4 dB. See Tables V and VI for more details.
0
-2
32
40
48
56
0
8
16
24
31
(011111)
(100000)
CDS GAIN REGISTER CODE
Figure 12. CDS Gain Curve
Input Clamp
A line-rate input clamping circuit is used to remove the CCD’s
optical black offset. This offset exists in the CCD’s shielded
black reference pixels. Unlike some AFE architectures, the
AD9840A removes this offset in the input stage to minimize the
effect of a gain change on the system black level, usually called the
“gain step.” Another advantage of removing this offset at the
input stage is to maximize system headroom. Some area CCDs
have large black level offset voltages, which, if not corrected at
the input stage, can significantly reduce the available headroom
in the internal circuitry when higher VGA gain settings are used.
A CDS gain of 4 dB provides some front-end signal gain and
improves the overall signal-to-noise ratio. This gain setting
works very well in most applications, and the CCD-Mode
Specifications use this default gain setting. However, the CDS
gain may be varied to optimize the AD9840A operation in a
particular application. Increased CDS gain can be useful with
low output level CCDs, while decreased CDS gain allows the
AD9840A to accept CCD signal swings greater than 1 V p-p.
Table VII summarizes some example CDS gain settings for
different maximum signal swings. The CDS Gain Register may
also be used “on the fly” to provide a +6 dB boost or –6 dB
attenuation when setting exposure levels. It is best to keep the
CDS output level from exceeding 1.5 V–1.6 V.
Horizontal timing is shown in Figure 6. It is recommended
that the CLPDM pulse be used during valid CCD dark pixels.
CLPDM may be used during the optical black pixels, either
REV. 0
–11–
AD9840A
together with CLPOB or separately. The CLPDM pulse should
be a minimum of four pixels wide.
black clamp loop is turned on once per horizontal line, but this
loop can be updated more slowly to suit a particular application.
If external digital clamping is used during the post processing, the
AD9840A’s optical black clamping may be disabled using Bit D5
in the Operation Register (see Serial Interface Timing and
Internal Register Description section). When the loop is dis-
abled, the Clamp Level Register may still be used to provide
programmable offset adjustment.
Variable Gain Amplifier
The VGA stage provides a gain range of 2 dB to 36 dB, program-
mable with 10-bit resolution through the serial digital interface.
Combined with the typical 4 dB gain from the CDS stage, the
total gain range for the AD9840A is 6 dB to 40 dB. A gain of 6 dB
will match a 1 V input signal with the ADC full-scale range of 2 V.
When compared to 1 V full-scale systems (such as ADI’s AD9803),
the equivalent gain range is 0 dB to 34 dB.
Horizontal timing is shown in Figure 6. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least 20
pixels wide to minimize clamp noise. Shorter pulsewidths may be
used, but clamp noise may increase, and the loop’s ability to
track low-frequency variations in the black level will be reduced.
The VGA gain curve is divided into two separate regions. When
the VGA Gain Register code is between 0 and 511, the curve
follows a (1 + x)/(1 – x) shape, which is similar to a “linear-in-
dB” characteristic. From code 512 to code 1023, the curve follows
a “linear-in-dB” shape. The exact VGA gain can be calculated
for any Gain Register value by using the following two equations:
A/D Converter
The AD9840A uses a high-performance ADC architecture,
optimized for high speed and low power. Differential nonlin-
earity (DNL) performance is typically better than 0.5 LSB.
Instead of the 1 V full-scale range used by the earlier AD9801 and
AD9803 products from Analog Devices, the AD9840A’s ADC
uses a 2 V input range. Better noise performance results from
using a larger ADC full-scale range.
Code Range Gain Equation (dB)
0–511
512–1023
Gain = 20 log10 ([658 + code]/[658 – code]) – 0.35
Gain = (0.0354)(code) – 0.35
Using these two equations, the actual gain of the AD9840A can
be accurately predicted to within ꢀ0.5 dB. As shown in the CCD-
Mode Specifications, only the VGA gain range from 2 dB to 36 dB
is specified. This corresponds to a VGA gain code range of 91 to
1023. The Gain Accuracy specifications also include a CDS gain
of 4 dB, for a total gain range of 6 dB to 40 dB.
AUX1-Mode
For applications that do not require CDS, the AD9840A can be
configured to sample ac-coupled waveforms. Figure 14 shows the
circuit configuration for using the AUX1 channel input (Pin
36). A single 0.1 µF ac-coupling capacitor is needed between the
input signal driver and the AUX1IN pin. An on-chip dc-bias
circuit sets the average value of the input signal to approxi-
mately 0.4 V, which is referenced to the midscale code of the ADC.
The VGA gain register provides a gain range of 0 dB to 36 dB
in this mode of operation (see VGA Gain Curve, Figure 13).
The VGA gains up the signal level with respect to the 0.4 V bias
level. Signal levels above the bias level will be further increased
to a higher ADC code, while signal levels below the bias level
will be further decreased to a lower ADC code.
36
30
24
18
12
6
AUX2-Mode
For sampling video-type waveforms, such as NTSC and PAL
signals, the AUX2 channel provides black level clamping, gain
adjustment, and A/D conversion. Figure 15 shows the circuit
configuration for using the AUX2 channel input (Pin 34). An
external 0.1 µF blocking capacitor is used with the on-chip
video clamp circuit, to level-shift the input signal to a desired
reference level. The clamp circuit automatically senses the most
negative portion of the input signal, and adjusts the voltage
across the input capacitor. This forces the black level of the input
signal to be equal to the value programmed into the Clamp Level
register (see Serial Interface Register Description). The VGA
provides gain adjustment from 0 dB to 18 dB. The same VGA
Gain register is used, but only the 9 MSBs of the gain register
are used (see Table VIII.)
0
0
127
255
383
511
639
767
895
1023
VGA GAIN REGISTER CODE
Figure 13. VGA Gain Curve (Gain from CDS Not Included)
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain, and to track low-frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the Clamp Level
Register. Any value between 0 LSB and 64 LSB may be pro-
grammed, with 8-bit resolution. The resulting error signal is
filtered to reduce noise, and the correction value is applied to
the ADC input through a D/A converter. Normally, the optical
REV. 0
–12–
AD9840A
0.4V
0.8V
??V
0dB TO 36dB
VGA
5kꢁ
0.1ꢂF
AUX1IN
INPUT SIGNAL
ADC
MIDSCALE
10
0.4V
0.4V
VGA GAIN
REGISTER
Figure 14. AUX1 Circuit Configuration
VGA GAIN
REGISTER
9
0dB TO 18dB
BUFFER
AUX2IN
VIDEO
SIGNAL
VGA
ADC
0.1ꢂF
CLAMP LEVEL
VIDEO CLAMP
CIRCUIT
LPF
8
CLAMP LEVEL
REGISTER
Figure 15. AUX2 Circuit Configuration
Table VIII. VGA Gain Register Used for AUX2-Mode
MSB
D9
LSB
D0
D10
D8
D7
D6
D5
D4
D3
D2
D1
Gain (dB)
X
0
1
X
0
X
0
X
0
X
0
•
X
0
X
0
X
0
X
0
X
0
0.0
0.0
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
18.0
REV. 0
–13–
AD9840A
AD9840A
CCD
DIGITAL
OUTPUTS
V
OUT
ADC
0.1ꢂF
OUT
DIGITAL IMAGE
PROCESSING
ASIC
SERIAL
INTERFACE
CCDIN
REGISTER
DATA
BUFFER
CDS/CLAMP
TIMING
V-DRIVE
CCD
TIMING
TIMING
GENERATOR
Figure 16. System Applications Diagram
APPLICATIONS INFORMATION
Grounding and Decoupling Recommendations
The AD9840A is a complete Analog Front End (AFE) product
for digital still camera and camcorder applications. As shown in
Figure 16, the CCD image (pixel) data is buffered and sent to
the AD9840A analog input through a series input capacitor. The
AD9840A performs the dc restoration, CDS, gain adjustment,
black level correction, and analog-to-digital conversion. The
AD9840A’s digital output data is then processed by the image
processing ASIC. The internal registers of the AD9840A—used
to control gain, offset level, and other functions—are programmed
by the ASIC or microprocessor through a 3-wire serial digital
interface. A system timing generator provides the clock signals
for both the CCD and the AFE.
As shown in Figure 17, a single ground plane is recommended
for the AD9840A. This ground plane should be as continuous
as possible, particularly around Pins 25 through 39. This will
ensure that all analog decoupling capacitors provide the lowest
possible impedance path between the power and bypass pins
and their respective ground pins. All decoupling capacitors
should be located as close as possible to the package pins. A
single clean power supply is recommended for the AD9840A,
but a separate digital driver supply may be used for DRVDD
(Pin 13). DRVDD should always be decoupled to DRVSS (Pin
14), which should be connected to the analog ground plane.
Advantages of using a separate digital driver supply include
using a lower voltage (2.7 V) to match levels with a 2.7 V ASIC,
reducing digital power dissipation, and reducing potential noise
coupling. If the digital outputs (Pins 3–12) must drive a load
larger than 20 pF, buffering is recommended to reduce digital
code transition noise. Alternatively, placing series resistors
close to the digital output pins may help reduce noise.
Internal Power-On Reset Circuitry
After power-on, the AD9840A will automatically reset all internal
registers and perform internal calibration procedures. This takes
approximately 1 ms to complete. During this time, normal clock
signals and serial write operations may occur. However, serial
register writes will be ignored until the internal reset operation is
completed. Pin 43 (formerly RSTB on the AD9843 non-A) is no
longer used for the reset operation. Toggling Pin 43 in the
AD9840A will have no effect.
REV. 0
–14–
AD9840A
3V
ANALOG SUPPLY
0.1ꢂF
1.0ꢂF
1.0ꢂF
0.1ꢂF
3
SERIAL
INTERFACE
48 47 46 45 44 43 42 41 40 39 38 37
DRVSS
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
1
2
36
35
34
PIN 1
DRVSS
(LSB) D0
D1
IDENTIFIER
0.1ꢂF
0.1ꢂF
3V
ANALOG
SUPPLY
3
4
33
32
31
D2
5
D3
NC
AD9840A
6
0.1ꢂF
D4
CCDIN
BYP2
TOP VIEW
CCD
SIGNAL
7
30
29
28
(Not to Scale)
D5
8
D6
BYP1
0.1ꢂF
9
D7
AVDD1
AVSS
AVSS
10
11
12
27
26
25
D8
(MSB) D9
3V
ANALOG
SUPPLY
0.1ꢂF
0.1ꢂF
10
DATA
OUTPUTS
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
3V
DRIVER
6
CLOCK
INPUTS
SUPPLY
0.1ꢂF
0.1ꢂF
3V
ANALOG SUPPLY
Figure 17. Recommended Circuit Configuration for CCD-Mode
REV. 0
–15–
AD9840A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead LQFP
(ST-48)
0.063 (1.60)
MAX
0.354 (9.00) BSC SQ
0.030 (0.75)
0.018 (0.45)
37
48
36
1
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
COPLANARITY
0.003 (0.08)
25
12
0ꢃ
MIN
13
24
0.011 (0.27)
0.006 (0.17)
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
0.057 (1.45)
0.053 (1.35)
7ꢃ
0ꢃ
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
–16–
REV. 0
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