AD9898KCPRL-20_技术文档

CCD Signal Processor with

Precision Timing^™Generator

AD9898

FEATURES

GENERAL DESCRIPTION

Correlated Double Sampler (CDS)

6 dB to 40 dB Variable Gain Amplifier (VGA)

Black Level Clamp with Variable Level Control

Complete On-Chip Timing Generator

Precision Timing Core with 1 ns Resolution

On-Chip: 2-Channel Horizontal and

1-Channel RG Drivers

The AD9898 is a highly integrated CCD signal processor for

digital still camera and digital video camera applications. It

includes a complete analog front end with A/D conversion

combined with a full function programmable timing generator.

A Precision Timing core allows adjustment of high speed clocks

with 1 ns resolution at 20 MHz operation.

The AD9898 is specified at pixel rates as high as 20 MHz. The

analog front end includes black level clamping, CDS, VGA, and

a 10-bit A/D converter. The timing generator provides all the

necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate

pulses, substrate clock, and substrate bias pulse. Operation is

programmed using a 3-wire serial interface.

2-Phase H-Clock Modes

4-Phase Vertical Transfer Clocks

Electronic and Mechanical Shutter Modes

On-Chip Sync Generator with External Sync Option

Space Saving 48-Lead LFCSP Package

APPLICATIONS

Digital Still Cameras

Digital Video Camcorders

Packaged in a space saving 48-Lead LFCSP, the AD9898 is

specified over an operating temperature range of –20°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

REFT REFB

AD9898

6dBTO 40dB

VGA

VREF

10

ADC

CDS

DOUT

CLAMP

INTERNAL CLOCKS

RG

DCLK1

HORIZONTAL

FD/DCLK2

MSHUT

PRECISION

TIMING

DRIVERS

2

4

2

H1, H2

GENERATOR

STROBE

V1, V2, V3, V4

VSG1, VSG2

V-H

CONTROL

SYNC

GENERATOR

INTERNAL

REGISTERS

VSUB

SUBCK

HD VD SYNC

CLI

SL SCK SDATA

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

AD9898

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3

ANALOG SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7

SPECIFICATION DEFINITIONS . . . . . . . . . . . . . . . . . . . 8

Differential Nonlinearity (DNL) . . . . . . . . . . . . . . . . . . . . 8

Peak Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Total Output Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Power Supply Rejection (PSR) . . . . . . . . . . . . . . . . . . . . . . 8

EQUIVALENT INPUT CIRCUITS . . . . . . . . . . . . . . . . . . 8

TYPICAL PERFORMANCE CHARACTERISTICS . . . . . 9

SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

CLI INPUT CLOCK DIVIDER . . . . . . . . . . . . . . . . . . . . . 16

GRAY CODE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . 16

SERIAL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . 17

Control Register Serial Interface . . . . . . . . . . . . . . . . . . . 17

System Register Serial Interface . . . . . . . . . . . . . . . . . . . . 17

Mode_A and Mode_B Register Serial Interface . . . . . . . . 17

VD SYNCHRONOUS AND ASYNCHRONOUS

High Precision Shutter Mode . . . . . . . . . . . . . . . . . . . . . . 37

Single Pulse Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Multiple Pulse Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

VSG TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

VSUB CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

VSUB Placement and Polarity . . . . . . . . . . . . . . . . . . . . . 41

MSHUT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

MSHUT Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . 42

MSHUT High Precision Operation . . . . . . . . . . . . . . . . . 43

STROBE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

SLAVE AND MASTER MODE OPERATION . . . . . . . . . 44

Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 44

VARIABLE GAIN AMPLIFIER . . . . . . . . . . . . . . . . . . . . . 45

Optical Black Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Digital I/O States for Different Operating Conditions . . . 45

POWER-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Recommended Power-Up Sequence for Master Mode . . . 46

STANDBY MODE OPERATION . . . . . . . . . . . . . . . . . . . 47

Recommended Standby Mode Sequence . . . . . . . . . . . . . 47

POWER-DOWN MODE OPERATION . . . . . . . . . . . . . . 48

Recommended Power-Down Sequence . . . . . . . . . . . . . . 48

HORIZONTAL TIMING SEQUENCE EXAMPLE . . . . . 49

CIRCUIT LAYOUT INFORMATION . . . . . . . . . . . . . . . 51

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 52

48-Lead LFCSP Package . . . . . . . . . . . . . . . . . . . . . . . . . 52

REGISTER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 18

Asynchronous Register Operation . . . . . . . . . . . . . . . . . . 18

VD Synchronous Register Operation . . . . . . . . . . . . . . . . 18

ANALOG FRONT END DESCRIPTION AND

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Correlated Double Sampler . . . . . . . . . . . . . . . . . . . . . . . 19

PRECISION TIMING HIGH SPEED TIMING

GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Timing Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

High Speed Clock Programmability . . . . . . . . . . . . . . . . . 19

H-Driver and RG Outputs . . . . . . . . . . . . . . . . . . . . . . . . 20

Digital Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

EXTERNAL SYNCHRONIZATION (MASTER MODE) 23

HORIZONTAL AND VERTICAL SYNCHRONOUS

TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Special Note About the HDLEN Register . . . . . . . . . . . . 24

HORIZONTAL CLAMPING AND BLANKING . . . . . . . 25

Controlling CLPOB Clamp Pulse Timing . . . . . . . . . . . . 25

Controlling CLPOB Clamp Pulse Outputs . . . . . . . . . . . 26

H1 AND H2 BLANKING . . . . . . . . . . . . . . . . . . . . . . . . . 27

Normal H-Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Selective Positioning for Two H1 and H2 Outputs . . . . . 27

Extended Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

VGATE MASKING OF V1–V4 AND CLPOB

TABLES

Table I. Control Register Address Map . . . . . . . . . . . . . . . . 10

Table II. System Register Address Map . . . . . . . . . . . . . . . . 12

Table III. Mode_A Register Map . . . . . . . . . . . . . . . . . . . . . 14

Table IV. Mode_B Register Map . . . . . . . . . . . . . . . . . . . . . 15

Table V. Grade Code Registers . . . . . . . . . . . . . . . . . . . . . . 16

Table VI. Type of Serial Interface Registers . . . . . . . . . . . . 17

Table VII. AFE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table VIII. RG, H1, SHP, SHD, DCLK, and

DOUTPHASE Timing Parameters . . . . . . . . . . . . . . . . . 21

Table IX. Precision Timing Edge Locations for RG, H1, SHP,

SHD, DCLK, and DOUTPHASE . . . . . . . . . . . . . . . . . . 21

Table X. External Synchronization (Master Mode) . . . . . . . 23

Table XI. HD and VD Registers . . . . . . . . . . . . . . . . . . . . . 24

Table XII. CLPOB Registers . . . . . . . . . . . . . . . . . . . . . . . . 25

Table XIII. SCP and CLPEN . . . . . . . . . . . . . . . . . . . . . . . 26

Table XIV. H1 Blanking Registers . . . . . . . . . . . . . . . . . . . . 27

Table XV. V1–V4 Registers to Configure V1–V4 Pulse

for Each VTP Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table XVI. Mode_A and Mode_B Registers for VTPx

Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table XVII. Mode_A and Mode_B Registers for CCD

Region Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table XVIII. Description of SVREP_MODE Register . . . . 34

Table XIX. HD and VD Registers . . . . . . . . . . . . . . . . . . . . 35

Table XX. SPATLOGIC Register . . . . . . . . . . . . . . . . . . . . 35

Table XXI. SUBCK Registers . . . . . . . . . . . . . . . . . . . . . . . 37

Table XXII. Single and Multiple Pulse Mode . . . . . . . . . . . 37

Table XXIII. VSG Registers . . . . . . . . . . . . . . . . . . . . . . . . 40

Table XXIV. VSUB Registers . . . . . . . . . . . . . . . . . . . . . . . 41

Table XXV. MSHUT and STROBE Registers . . . . . . . . . . 42

Table XXVI. I/O Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

VERTICAL TIMING GENERATION . . . . . . . . . . . . . . . 30

Creating Vertical Sequences . . . . . . . . . . . . . . . . . . . . . . . 30

Special Vertical Sweep Mode Operation . . . . . . . . . . . . . 34

Special Vertical Timing (SPAT) . . . . . . . . . . . . . . . . . . . 35

ELECTRONIC SHUTTER TIMING CONTROL . . . . . . 37

Normal Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SUBCK Suppression Mode . . . . . . . . . . . . . . . . . . . . . . . 37

–2–

REV. 0

AD9898

SPECIFICATIONS

Parameter

Min

Typ

Max

Unit

TEMPERATURE RANGE

Operating

Storage

–20

–65

+85

+150

°C

POWER SUPPLY VOLTAGE

AVDD (AFE Analog Supply)

TCVDD (Timing Core Analog Supply)

RGVDD (RG Driver)

HVDD (H1–H2 Drivers)

DRVDD (Data Output Drivers)

DVDD (Digital)

2.7

3.0

3.6

V

POWER DISSIPATION

20 MHz, Typical Supply Levels, 100 pF H1–H2 Loading

Power from HVDD Only*

150

36

3

mW

Power-Down Mode (AFE and Digital in Standby Operation)

MAXIMUM CLOCK RATE (CLI)

AD9898

20

MHz

*The total power dissipated by the HVDD supply may be approximated using the equation

Total HVDD Power = (CLOAD × HVDD × Pixel Frequency) × HVDD × Number of H-Outputs Used

Actual HVDD power may be slightly higher than the calculated value because of stray capacitance inherent in the PCB layout/routing.

Specifications subject to change without notice.

(RGVDD = HVDD = 2.7 V to 3.6 V, DVDD = DRVDD = 2.7 V to 3.6 V, C_L= 20 pF, T_MINto T_MAX, unless

DIGITAL SPECIFICATIONS ^{otherwise noted.)}

Parameter

Symbol

Min

Typ

Max

Unit

LOGIC INPUTS

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

V_IH

V_IL

I_IH

I_IL

C_IN

2.1

V

µA

pF

0.6

10

LOGIC OUTPUTS (Except H and RG)

High Level Output Voltage @ I_OH= 2 mA

Low Level Output Voltage @ I_OL= 2 mA

V_OH

V_OL

2.2

V

0.5

RG and H-DRIVER OUTPUTS (H1–H2)

High Level Output Voltage @ Maximum Current

Low Level Output Voltage @ Maximum Current

RG Maximum Output Current (Programmable)

H1 and H2 Maximum Output Current (Programmable)

Maximum Load Capacitance

V_OH

V_OL

VDD – 0.5

V

mA

pF

0.5

15

30

100

Specifications subject to change without notice.

REV. 0

–3–

AD9898

ANALOG SPECIFICATIONS

Parameter

(AVDD = 3.0 V, f_CLI= 20 MHz, T_MINto T_MAX, unless otherwise noted.)

Min

Typ

Max

Unit

Comments

CDS

Allowable CCD Reset Transient

500

mV

Input Signal Characteristics

Maximum Input Range before Saturation* 1.0

Maximum CCD Black Pixel Amplitude

V p-p

mV

100

VARIABLE GAIN AMPLIFIER (VGA)

Maximum Output Range

Gain Control Resolution

Gain Monotonicity

Gain Range

2.0

V p-p

Steps

1024

Guaranteed

Low Gain

Maximum Gain

6

40

dB

BLACK LEVEL CLAMP

Clamp Level Resolution

Clamp Level

64

Steps

LSB

LSB is measured at ADC output.

Minimum Clamp Level

Maximum Clamp Level

0

63

A/D CONVERTER

Resolution

Differential Nonlinearity (DNL)

No Missing Codes

10

Bits

LSB

0.5

Guaranteed

2.0

Full-Scale Input Voltage

V

VOLTAGE REFERENCE

Reference Top Voltage (REFT)

Reference Bottom Voltage (REFB)

2.0

1.0

V

SYSTEM PERFORMANCE

Gain Accuracy

Low Gain (VGA Code = 20)

Maximum Gain (VGA Code = 991)

Peak Nonlinearity, 500 mV Input Signal

Total Output Noise

Includes entire signal chain

5

39

6

7

41

dB

%

LSB rms

dB

Gain = (0.035 ×Code) + 5.3 dB

40

0.1

0.3

40

12 dB gain applied

AC grounded input, 6 dB gain applied

Measured with step change on supply

Power Supply Rejection (PSR)

*Input signal characteristics defined as follows:

500mV TYP

RESET

TRANSIENT

1V MAX

INPUT

SIGNAL RANGE

100mV MAX

OPTICAL

BLACK PIXEL

Specifications subject to change without notice.

–4–

REV. 0

AD9898

(C_L= 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f_CLI= 20 MHz, unless otherwise noted.)

TIMING SPECIFICATIONS

Parameter

Symbol

Min

Typ

Max

Unit

MASTER CLOCK, CLI

CLI Clock Period

CLI High/Low Pulsewidth

Delay from CLI Rising Edge to Internal Pixel Position 0

t_CONV

50

20

ns

25

6

t_CLIDLY

AFE CLAMP PULSES*

CLPOB Pulsewidth

4

10

25

Pixels

AFE SAMPLE LOCATION* (See Figure 13)

SHP Sample Edge to SHD Sample Edge

t_S1

20

DATA OUTPUTS (See Figure 15)

Output Delay from DCLK Rising Edge

Pipeline Delay from SHP/SHD Sampling

t_OD

9

ns

Cycles

SERIAL INTERFACE (See Figures 7 and 8)

Maximum SCK Frequency

SL to SCK Setup Time

f_SCLK

t_LS

t_LH

t_DS

t_DH

t_DV

10

MHz

ns

SCK to SL Hold Time

SDATA Valid to SCK Rising Edge Setup

SCK Falling Edge to SDATA Valid Hold

SCK Falling Edge to SDATA Valid Read

ns

*Parameter is programmable.

Specifications subject to change without notice.

REV. 0

–5–

AD9898

ABSOLUTE MAXIMUM RATINGS*

Parameter

With Respect To

Min

Max

Unit

AVDD

TCVDD

HVDD

RGVDD

DVDD

DRVDD

RG Output

H1–H2 Output

Digital Outputs

Digital Inputs

SCK, SL, SDATA

REFT, REFB

CCDIN

AVSS

–0.3

+3.9

RGVDD + 0.3

HVDD + 0.3

DVDD + 0.3

AVDD + 0.3

150

V

°C

TCVSS

HVSS

RGVSS

DVSS

DRVSS

RGVSS

HVSS

DVSS

AVSS

Junction Temperature

Lead Temperature, 10 sec

300

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL CHARACTERISTICS

Thermal Resistance

␪

_JA= 92°C/W

ORDERING GUIDE

Package Description

Model

Temperature Range

Package Option

AD9898KCP-20

AD9898KCPRL-20

–20ºC to +85ºC

Lead Frame Chip Scale Package (LFCSP)

CP-48

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD9898 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

–6–

REV. 0

AD9898

PIN CONFIGURATION

48 47 46 45 44 43 42 41 40 39 38 37

1

2

D0

D1

36

35

34

33

32

31

30

29

28

27

26

25

SCK

PIN 1

IDENTIFIER

SL

3

D2

SDATA

REFB

REFT

AVSS

CCDIN

AVDD

CLI

4

D3

5

D4

AD9898

TOP VIEW

6

DRVSS

DRVDD

D5

7

(Not to Scale)

8

9

D6

10

11

12

D7

TCVDD

TCVSS

RGVDD

D8

D9

13 14 15 16 17 18 19 20 21 22 23 24

PIN FUNCTION DESCRIPTION

Pin No. Mnemonic Type* Description

1

2

D0

DO

P

Data Output

28

29

30

31

32

33

CLI

DI

P

Reference Clock Input

D1

Data Output

AVDD

CCDIN

AVSS

REFT

REFB

Analog Supply for AFE

CCD Input Signal

3

D2

Data Output

AI

P

4

D3

Data Output

Analog Ground for AFE

Voltage Reference Top Bypass

5

D4

Data Clock Output

Data Output Driver Ground

Data Output Driver Supply

Data Output

AO

6

DRVSS

DRVDD

D5

Voltage Reference Bottom

Bypass

7

P

34

35

36

37

38

39

40

41

42

43

44

45

SDATA

SL

DI

3-Wire Serial Data Input

3-Wire Serial Load Pulse

3-Wire Serial Clock

8

DO

DI

9

D6

Data Output

SCK

V1

DI

10

11

12

13

14

15

16

D7

Data Output

DO

CCD Vertical Transfer Clock 1

CCD Vertical Transfer Clock 2

CCD Vertical Transfer Clock 3

CCD Vertical Transfer Clock 4

CCD Sensor Gate Pulse 1

CCD Sensor Gate Pulse 2

Output Control

D8

Data Output

V2

D9

Data Output

V3

DCLK1

MSHUT

STROBE

Data Clock Output

Mechanical Shutter Pulse

Strobe Pulse

V4

VSG1

VSG2

FD/

DCLK2

DO

Field Designator Output

DCLK2 Output

OUTCONT DI

17

18

19

20

21

22

23

24

25

26

HD

DI

P

Horizontal Sync Pulse

Vertical Sync Pulse

VSUB

DO

CCD Substrate Bias

VD

SYNC/

VGATE

DI

External System Sync Input

VGATE Input

HVDD

HVSS

H2

H1–H2 Driver Supply

H1–H2 Driver Ground

CCD Horizontal Clock 2

CCD Horizontal Clock 1

RG Driver Ground

46

DVDD

P

Digital Supply for VSG,

V1–V4, HD, VD, MSHUT,

STROBE, and Serial Interface

P

DO

P

H1

47

48

DVSS

P

Digital Ground

RGVSS

RG

SUBCK

DO

CCD Substrate Clock

(E-Shutter)

DO

P

CCD Reset Gate Clock

RG Driver Supply

*AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital

Output, P = Power.

RGVDD

TCVSS

P

Analog Ground for Timing

Core

27

TCVDD

P

Analog Supply for Timing Core

REV. 0

–7–

AD9898

SPECIFICATION DEFINITIONS

Total Output Noise

Differential Nonlinearity (DNL)

The rms output noise is measured using histogram techniques.

The standard deviation of the ADC output codes is calculated

in LSB and represents the rms noise level of the total signal

chain at the specified gain setting. The output noise can be

converted to an equivalent voltage, using the relationship 1 LSB =

(ADC Full Scale/2^Ncodes) where N is the bit resolution of the

ADC. For the AD9898, 1 LSB is 2 mV.

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Thus every

code must have a finite width. No missing codes guaranteed to

10-bit resolution indicates that all 1024 codes, respectively,

must be present over all operating conditions.

Peak Nonlinearity

Peak nonlinearity, a full signal chain specification, refers to the

peak deviation of the output of the AD9898 from a true straight

line. The point used as zero scale occurs 1/2 LSB before the

first code transition. Positive full scale is defined as a level 1

1/2 LSB beyond the last code transition. The deviation is

measured from the middle of each particular output code to the

true straight line. The error is then expressed as a percentage of

the 2 V ADC full-scale signal. The input signal is always appro-

priately gained up to fill the ADC’s full-scale range.

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply

pins. The PSR specification is calculated from the change in the

data outputs for a given step change in the supply voltage.

EQUIVALENT INPUT CIRCUITS

DVDD

AVDD

330ꢀ

R

DVSS

AVSS

Figure 3. Digital Inputs

Figure 1. CCDIN

HVDD OR

RGVDD

DVDD

DRVDD

RG,

H1–H2

DATA

THREE-

STATE

ENABLE

OUTPUT

DOUT

HVSS OR RGVSS

DVSS

DRVSS

Figure 4. H1–H2, RG Drivers

Figure 2. Digital Data Outputs

–8–

REV. 0

Typical Performance Characteristics–AD9898

180

160

0.3

V

= 3.3V

= 3.0V

DD

0.15

0

140

120

100

80

V

DD

V

= 2.7V

DD

–0.15

–0.3

60

10

0

200

400

600

800

1000

15

20

SAMPLE RATE – MHz

CODE

TPC 2. Typical DNL Performance

TPC 1. Power vs. Sample Rate

REV. 0

–9–

AD9898

Table I. Control Register Address Map (Register Names Are Subject to Change)

Bit

Default

Register

Name

Address Content Width Value

Register Description

00

01

(23:0)

23

000000

SW_RESET

Software Reset = 000000. (Reset all registers to default.)

(23:21)

20

(19:18)

17

16

(15:14)

13

3

1

2

1

2

1

0

1

0

Unused

Unused. Test Mode. Should be set = 0.

Unused

Masking Polarity for H1 during blanking period (0 = Low, 1 = High)

External SYNC Active Polarity (0 = Active Low)

Unused

High Precision Shutter Mode Operation (0 = Single Pulse, 1 = Multiple

Pulse)

Suppress First SUBCK after Last VSG Line Pulse (0 = No Suppression,

1 = Suppression of 1 SUBCK)

HBLKMASK

SYNCPOL

SUBCKMODE_HP

SUBCKSUPPRESS

12

1

0

(11:10)

(9:8)

2

0

Unused

MSHUTPAT

Selects MSHUT Pattern (See Figure 44) (0 = MSHUTPAT0,

1 = MSHUTPAT1, 2 = MSHUTPAT2, 3 = MSHUTPAT3)

MSHUT Masking of VGATE Input (0 = MSHUT does not mask

VGATE, 1 = MSHUT does mask VGATE)

MSHUT Masking of SUBCK (0 = MSHUT does not mask SUBCK,

1 = MSHUT does mask SUBCK)

7

6

1

0

MSHUT/VGATE_EN

MSHUT/SUBCK_EN

5

4

(3:1)

0

1

3

1

0

CLP_CONT

CLP_MODE

CLPOB Control (0 = CLPOB OFF, 1 = CLPOB ON)

CLPOB CCD Region Control (See Table XII)

Unused

VD Synchronous/Asynchronous Mode Setting (0 = VD Synchronous,

1 = VD Asynchronous)

VDMODE

02

03

04

(23:22)

(21:16)

(15:14)

(13:8)

(7:6)

2

6

2

6

2

6

0

0x34

0

0x18

0

0x0B

Unused

SHD Sample Location

Unused

SHP Sample Location

DCLK Pulse Adjustment

Data Output [9:0] Phase Adjustment

SHDLOC

SHPLOC

DCLKPHASE

DOUTPHASE

(5:0)

(23:17)

16

(15:14)

(13:8)

(7:6)

7

1

2

6

2

6

0x00

0

0x00

0

0x10

Unused

H1BLKRETIME

H1POSLOC

Retimes the H1 HBLK to Internal Clock

Unused

H1 Positive Edge Location

Unused

(5:0)

RGNEGLOC

RG Negative Edge Location

(23:22)

(21:16)

(14:12)

2

6

3

0

0x20

5

Unused

Black Clamp Level

REFBLACK

H2DRV

H2 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,

4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)

Unused

H1 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,

4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA)

Unused

11

(10:8)

1

3

0

5

H1DRV

RGDRV

(7:3)

(2:0)

5

3

0x00

2

RG Drive Strength (0 = Off, 1 = 2.15 mA, 2 = 4.2 mA, 3 = 6.45 mA,

4 = 8.6 mA, 5 = 10.75 mA, 6 = 12.9 mA, 7 = 15.05 mA)

05

(23:10)

9

8

(7:2)

1

14

1

6

1

0x0000

0

00

0

Unused

AFESTBY

DIGSTBY

AFE Standby (0 = Standby , 1 = Normal Operation)

Digital Standby (0 = Standby , 1 = Normal Operation)

Unused

Internal OUTCONT Signal Control (0 = Digital Outputs held at fixed

dc level, 1 = Normal Operation)

OUTCONT_REG

OUTCONT_ENB

0

1

External OUTCONT Signal Input Pin 43 Control (0 = Pin Enabled,

1 = Pin Disabled)

–10–

REV. 0

AD9898

Table I. Control Register Address Map (Register Names Are Subject to Change)

Bit

Default

Register

Name

Address Content Width Value

Register Description

0A

23

22

(21:16)

(15:12)

(11:10)

1

6

4

2

1

4

2

1

0

0x00

0

C

3

0

Unused

FDPOL

FD Polarity Control (0 = Low, 1 = High)

VSG Masking (See Table XXIII)

External SYNC Setting

VSGMASK

SYNCCNT

SVREP_MODE

HBLKEXT

HPULSECNT

SPATLOGIC

SVOS

(VD

SyncReg)* 9

Super Vertical Repetition Mode

H Pulse Blanking Extend Control

H Pulse Control during Blanking

SPAT Logic Setting (See Table XX)

Second V Output Setting (10 = Output Repetition 1)

SPAT Control (0 = SPAT Disable, 1 = SPAT Enable)

Mode Control Bit (0 = Mode_A, 1 = Mode_B)

8

(7:4)

(3:2)

1

0

SPAT_EN

MODE

0

0B

(23:22)

21

20

2

1

3

1

0

1

0

Unused

SUBCK_EN

VSG_EN

SUBCK Output Enable Control (0 = Disable, 1 = Enable)

VSG Output Enable Control (0 = Disable, 1 = Enable)

Unused

STROBE Output Control (0 = STROBE Output Held Low,

1 = STROBE Output Enabled)

(VD

SyncReg)* 16

(19:17)

STROBE_EN

15

1

0

Unused

(14:12)

11

(10:0)

3

1

11

0

SUBCKNUM_HP

SUBCKNUM

High Precision Shutter SUBCLK Pulse Position/Number

Unused

Total Number of SUBCKs per Field

0x7FF

0C

(23:21)

20

3

1

0

Unused

MSHUTINIT

MSHUT Initialize (1 = Forces MSHUT Low)

(19:18)

17

2

1

0

Unused

(VD

SyncReg)* 16

1

0

MSHUTEN

MSHUT Control ( 0 = MSHUT Held at Last State, 1 = MSHUT Output)

15

1

0

Unused

(14:12)

11

(10:0)

3

1

11

0

MSHUTPOS_HP

MSHUTPOS

MSHUT Position during High Precision Operation

Unused

MSHUT Position during Normal Operation

0x000

0D

(23:17)

16

(15:11)

7

1

5

11

Unused

0

VSUBPOL

VSUBTOG

VSUB Active Polarity (0 = Low, 1 = High)

Unused

VSUB Toggle Position. Active starting line in any field.

(VD

SyncReg)* (10:0)

0x000

0E

(23:21)

20

(19:18)

17

3

1

2

1

6

10

0

Unused

Unused. Test Mode. Should be set = 0.

Unused

Unused. Test Mode. Should be set = 0.

Unused

(VD

SyncReg)* 16

(15:10)

0

0x00

0x000

(9:0)

VGAGAIN

VGA Gain

D5

(23:4)

3

20

1

0x00000

1

Unused

DCLK2SEL

DCLK1SEL

CLKDIV

DCLK2 Selector (0 = Select Internal FD Signal to be Output on FD/

DCLK2 Pin 16, 1 = Select CLI to be Output on FD/DCLK2 Pin 16)

DCLK1 Selector (0 = Select DLL Version for DCLK1 Output,

1 = Select CLI for DCLK1 Output)

2

1

2

0

(1:0)

Input Clock Divider (0 = No Division, 1 = 1/2, 2 = 1/3, 3 = 1/4)

D6

(23:1)

0

23

1

0x000000

1

Unused

SLAVE_MODE

Operating Mode ( 0 = Master Mode, 1 = Slave Mode)

*This register defaults to VD synchronous mode type at power up. VD sync type registers do not get updated until the first falling edge of VD is asserted after the

register has been programmed. VD sync type registers can be programmed to be asynchronous registers by setting VDMODE = 1 (Addr 0x01).

REV. 0

–11–

AD9898

Table II. System Register Address Map (Addr 0x14)

Default

Bit

Register

Content Width (Decimal) Register Name

Register Description

Sys_Reg(0)

(31:24)

(23:0)

8

24

NA

System_Reg_Addr

System_Number_N

System Register Address Is (Addr 0x14)

Number N Register Writes (0x000000 = Write All Registers)

Sys_Reg(1)

(31:23)

22

21

20

19

(18:10)

(9:1)

0

9

1

9

1

37

0

1

0

19

0

VTPLEN0

Vertical Sequence No. 0: Length between Repetitions

Vertical Sequence No. 0: V1 Start Polarity

Vertical Sequence No. 0: V2 Start Polarity

Vertical Sequence No. 0: V3 Start Polarity

Vertical Sequence No. 0: V4 Start Polarity

Vertical Sequence No. 0: V1 Toggle Position 1

Vertical Sequence No. 0: V1 Toggle Position 2

V1STARTPOL0

V2STARTPOL0

V3STARTPOL0

V4STARTPOL0

V1TOG1POS0

V1TOG2POS0

V2TOG1POS0 [8]

Sys_Reg(2)

Sys_Reg(3)

(31:24)

(23:15)

(14:6)

(5:0)

8

9

6

12

31

0

V2TOG1POS0 [7:0] Vertical Sequence No. 0: V2 Toggle Position 1

V2TOG2POS0

V3TOG1POS0

Vertical Sequence No. 0: V2 Toggle Position 2

Vertical Sequence No. 0: V3 Toggle Position 1

V3TOG2POS0 [8:3]

(31:29)

(28:20)

(19:11)

(10:2)

1

3

9

1

19

12

31

104

0

V3TOG2POS0 [2:0] Vertical Sequence No. 0: V3 Toggle Position 2

V4TOG1POS0

V4TOG2POS0

VTPLEN1

V1STARTPOL1

V2STARTPOL1

Vertical Sequence No. 0: V4 Toggle Position 1

Vertical Sequence No. 0: V4 Toggle Position 2

Vertical Sequence No. 1: Length between Repetitions

Vertical Sequence No. 1: V1 Start Polarity

Vertical Sequence No. 1: V2 Start Polarity

0

Sys_Reg(4)

31

30

(29:21)

(20:12)

(11:3)

(2:0)

1

9

3

1

18

58

47

V3STARTPOL1

V4STARTPOL1

V1TOG1POS1

V1TOG2POS1

V2TOG1POS1

V2TOG2POS1 [8:6]

Vertical Sequence No. 1: V3 Start Polarity

Vertical Sequence No. 1: V4 Start Polarity

Vertical Sequence No. 1: V1 Toggle Position 1

Vertical Sequence No. 1: V1 Toggle Position 2

Vertical Sequence No. 1: V2 Toggle Position 1

Sys_Reg(5)

Sys_Reg(6)

(31:26)

(25:17)

(16:8)

(7:0)

6

9

8

96

0

76

V2TOG2POS1 [5:0] Vertical Sequence No. 1: V2 Toggle Position 2

V3TOG1POS1

V3TOG2POS1

Vertical Sequence No. 1: V3 Toggle Position 1

Vertical Sequence No. 1: V3 Toggle Position 2

V4TOG1POS1 [8:1]

31

1

9

1

9

38

105

57

0

1

V4TOG1POS1 [0]

V4TOG2POS1

VTPLEN2

V1STARTPOL2

V2STARTPOL2

V3STARTPOL2

V4STARTPOL2

V1TOG1POS2

Vertical Sequence No. 1: V4 Toggle Position 1

Vertical Sequence No. 1: V4 Toggle Position 2

Vertical Sequence No. 2: Length between Repetitions

Vertical Sequence No. 2: V1 Start Polarity

Vertical Sequence No. 2: V2 Start Polarity

Vertical Sequence No. 2: V3 Start Polarity

Vertical Sequence No. 2: V4 Start Polarity

Vertical Sequence No. 2: V1 Toggle Position 1

(30:22)

(21:13)

12

11

10

9

(8:0)

1

0

Sys_Reg(7)

Sys_Reg(8)

(31:23)

(22:14)

(13:5)

(4:0)

9

5

29

19

48

V1TOG2POS2

V2TOG1POS2

V2TOG2POS2

V3TOG1POS2 [8:4]

Vertical Sequence No. 2: V1 Toggle Position 2

Vertical Sequence No. 2: V2 Toggle Position 1

Vertical Sequence No. 2: V2 Toggle Position 2

(31:28)

(27:19)

(18:10)

(9:1)

4

9

1

0

V3TOG1POS2 [3:0] Vertical Sequence No. 2: V3 Toggle Position 1

29

19

48

V3TOG2POS2

V4TOG1POS2

V4TOG2POS2

Vertical Sequence No. 2: V3 Toggle Position 2

Vertical Sequence No. 2: V4 Toggle Position 1

Vertical Sequence No. 2: V4 Toggle Position 2

Unused

0

–12–

REV. 0

AD9898

Table II. System Register Address Map (Addr 0x14) (continued)

Default

Bit

Register

Content Width (Decimal) Register Name

Register Description

Sys_Reg(9)

(31:23)

22

21

20

19

(18:10)

(9:1)

0

9

1

9

1

89

0

1

VTPLEN3

Vertical Sequence No. 3: Length between Repetitions

Vertical Sequence No. 3: V1 Start Polarity

Vertical Sequence No. 3: V2 Start Polarity

Vertical Sequence No. 3: V3 Start Polarity

Vertical Sequence No. 3: V4 Start Polarity

Vertical Sequence No. 3: V1 Toggle Position 1

Vertical Sequence No. 3: V1 Toggle Position 2

V1STARTPOL3

V2STARTPOL3

V3STARTPOL3

V4STARTPOL3

V1TOG1POS3

V1TOG2POS3

V2TOG1POS3 [8]

0

60

Sys_Reg(10) (31:24)

8

9

6

30

90

0

V2TOG1POS3 [7:0] Vertical Sequence No. 3: V2 Toggle Position 1

(23:15)

(14:6)

(5:0)

V2TOG2POS3

V3TOG1POS3

Vertical Sequence No. 3: V2 Toggle Position 2

Vertical Sequence No. 3: V3 Toggle Position 1

V3TOG2POS3 [8:3]

Sys_Reg(11) (31:29)

3

9

10

1

60

30

90

0

V3TOG2POS3 [2:0] Vertical Sequence No. 3: V3 Toggle Position 2

(28:20)

(19:11)

(10:1)

0

V4TOG1POS3

V4TOG2POS3

HBLKHPOS

Vertical Sequence No. 3: V4 Toggle Position 1

Vertical Sequence No. 3: V4 Toggle Position 2

H1 Pulse ON Position during Blanking Period

Unused

Sys_Reg(12) (31:20)

12

10

9

2283

130

100

HDLEN*

HLEN

OLEN

12-Bit Gray Code HD Counter Value (Gray Code Number)

10-Bit HL Counter Value

9-Bit OL Counter Value

(19:10)

(9:1)

0

1

BLLEN [8]

Sys_Reg(13) (31:24)

8

11

5

0

BLLEN[7:0]

MSHUTLEN

VSGTOG1_0

9-Bit BL Counter Value

MSHUT Sequence Length

VSG Sequence No. 1 Toggle Position 1

(23:16)

(15:5)

(4:0)

118

1048

VSGTOG1_1 [10:6]

Sys_Reg(14) (31:26)

6

8

9

1198

60

19

VSGTOG1_1 [5:0]

VSGLEN

SUBCK1TOG1

SUBCK1TOG2

VSG Sequence No. 2 Toggle Position 1

VSG Pulsewidth

SUBCK1 First Toggle Position

SUBCK1 Second Toggle Position

(25:18)

(17:9)

(8:0)

88

Sys_Reg(15) (31:23)

9

12

2

19

88

2243

SUBCK2TOG1

SUBCK2TOG2

CLPTOG1*

SUBCK2 First Toggle Position

SUBCK2 Second Toggle Position

CLPOB Toggle Position No. 1

(22:14:)

(13:2)

(1:0)

CLPTOG2 [11]*

Sys_Reg(16) (31:22)

10

4

10

8

2278

9

120

CLPTOG2 [10:0]*

VDRISE

HDRISE

CLPOB Toggle Position No. 2

VD Toggle Position No. 1

HD Toggle Position No. 2

Unused

(21:18)

(17:8)

(7:0)

*Register value must be a gray code number. (See Gray Code Registers section.)

REV. 0

–13–

AD9898

Table III. Mode_A Register Map (Addr 0x15)

Default

Bit

Content Width (Decimal) Register Name

Register

Register Description

Mode_Reg(0) (31:24)

(23:0)

8

24

NA

Mode_A_Addr

Mode_A Address Is (Addr 0x15)

Mode_A_Number_N Number N Register Writes (0x000000 = Write All Registers)

Mode_Reg(1) (31:21)

11

12

1

7

262

1139

1

0

VDLEN

HDLASTLEN

VSGSEL0

VSGSEL1

VSGACTLINE

VD Counter Value

(20:9)

8

7

Number of Pixels in Last Line (Gray Code Number)

VSG1 Sequence Selector (See Table XXIII)

VSG2 Sequence Selector (See Table XXIII)

VSG Active Line

(6:0)

Mode_Reg(2) 31

1

3

1

8

3

0

1

0

SUBCKSEL

VTPSEQPTR0

VTPSEQPTR1

VTPSEQPTR2

VTPSEQPTR3

VTPSEQPTR4

CLPEN0

CLPEN1

CLPEN2

CLPEN3

CLPEN4

Select one of two SUBCK Patterns

Vertical Transfer Sequence Region No. 0

Vertical Transfer Sequence Region No. 1

Vertical Transfer Sequence Region No. 2

Vertical Transfer Sequence Region No. 3

Vertical Transfer Sequence Region No. 4

CLPOB Output Control No. 1

CLPOB Output Control No. 2

CLPOB Output Control No. 3

CLPOB Output Control No. 4

CLPOB Output Control No. 5

(30:28)

(27:25)

(24:22)

(21:19)

(18:16)

15

14

13

12

11

(10:3)

(2:0)

SCP1

SCP2

Sequence Change Position No. 1

Mode_Reg(3) (31:27)

5

8

2

3

0

3

SCP2

SCP3

SCP4

VTPSEL0

VTPSEL1

VTPSEL2

VTPSEL3

VTPREP0

Sequence Change Position No. 2

Sequence Change Position No. 3

Sequence Change Position No. 4

Vertical Pattern Selection 0

Vertical Pattern Selection 1

Vertical Pattern Selection 2

(26:19)

(18:11)

(10:9)

(8:7)

(6:5)

(4:3)

Vertical Pattern Selection 3

Number of Vertical Pulse Repetitions for Pattern0

(2:0)

Mode_Reg(4) (31:29)

3

11

1

0

VTPREP1

VTPREP2

VTPREP3

SVREP0

Number of Vertical Pulse Repetitions for Pattern1

Number of Vertical Pulse Repetitions for Pattern2

Number of Vertical Pulse Repetitions for Pattern3

Vertical Sweep Repetition Number for CCD Region0

Vertical Sweep Repitition Number for CCD Region3

Unused

(28:26)

(25:23)

(22:12)

(11:1)

0

SVREP3

Mode_Reg(5) (31:19)

13

6

988

1138

V1SPAT_TOG1

V1SPAT_TOG2

V2SPAT_TOG1

Polarity Change Position Start for V1 SPAT

Polarity Change Position End for V1 SPAT

(18:6)

(5:0)

Mode_Reg(6) (31:25)

(24:12)

7

13

12

1078

1168

V2SPAT_TOG1

V2SPAT_TOG2

V3SPAT_TOG1

Polarity Change Position Start for V2 SPAT

Polarity Change Position End for V2 SPAT

(11:0)

Mode_Reg(7) 31

(30:18)

1

958

1138

988

V3SPAT_TOG1

V3SPAT_TOG2

V4SPAT_TOG1

V4SPAT_TOG2

Polarity Change Position Start for V3 SPAT

Polarity Change Position End for V3 SPAT

Polarity Change Position Start for V4 SPAT

13

5

(17:5)

(4:0)

Mode_Reg(8) (31:24)

8

13

2

1228

1392

3

V4SPAT_TOG2

SECONDVPOS

VPATSECOND

Polarity Change Position End for V4 SPAT

Second V Pattern Output Position

Selected Second V Pattern Group for VSG Active Line

Unused

(23:11)

(10:9)

(8:0)

9

–14–

REV. 0

AD9898

Table IV. Mode_B Register Map (Addr 0x16)

Default

Bit

Content Width (Decimal) Register Name

Register

Register Description

Mode_Reg(0) (31:24)

(23:0)

8

24

NA

Mode_B_Addr

Mode_B Address Is (Addr 0x16)

Mode_B_Number_N Number N Register Writes (0x000000 = Write All Registers)

Mode_Reg(1) (31:21)

11

12

1

7

262

1139

1

0

VDLEN

HDLASTLEN*

VSGSEL0

VSGSEL1

VD Counter Value

(20:9)

8

7

Number of Pixels in Last Line (Gray Code Number)

VSG1 Sequence Selector (See Table XXIII)

VSG2 Sequence Selector (See Table XXIII)

VSG Active Line

(6:0)

VSGACTLINE

Mode_Reg(2) 31

1

3

1

8

3

0

1

0

SUBCKSEL

VTPSEQPTR0

VTPSEQPTR1

VTPSEQPTR2

VTPSEQPTR3

VTPSEQPTR4

CLPEN0

CLPEN1

CLPEN2

CLPEN3

CLPEN4

Select One of Two SUBCK Patterns

Vertical Transfer Sequence Region No. 0

Vertical Transfer Sequence Region No. 1

Vertical Transfer Sequence Region No. 2

Vertical Transfer Sequence Region No. 3

Vertical Transfer Sequence Region No. 4

CLPOB Output Control No. 1

CLPOB Output Control No. 2

CLPOB Output Control No. 3

CLPOB Output Control No. 4

CLPOB Output Control No. 5

(30:28)

(27:25)

(24:22)

(21:19)

(18:16)

15

14

13

12

11

(10:3)

(2:0)

SCP1

SCP2

Sequence Change Position No. 1

Mode_Reg(3) (31:27)

5

8

2

3

0

3

SCP2

SCP3

SCP4

VTPSEL0

VTPSEL1

VTPSEL2

VTPSEL3

VTPREP0

Sequence Change Position No. 2

Sequence Change Position No. 3

Sequence Change Position No. 4

Vertical Pattern Selection 0

Vertical Pattern Selection 1

Vertical Pattern Selection 2

(26:19)

(18:11)

(10:9)

(8:7)

(6:5)

(4:3)

Vertical Pattern Selection 3

Number of VTP0 Pulse Repetitions for Pattern0

(2:0)

Mode_Reg(4) (31:29)

3

11

1

0

VTPREP1

VTPREP2

VTPREP3

SVREP0

Number of VTP1 Pulse Repetitions for Pattern1

Number of VTP2 Pulse Repetitions for Pattern2

Number of VTP0 Pulse Repetitions for Pattern3

Vertical Sweep Repetition Number for CCD Region0

Vertical Sweep Repetition Number for CCD Region3

Unused

(28:26)

(25:23)

(22:12)

(11:1)

0

SVREP3

Mode_Reg(5) (31:19)

13

6

988

1138

V1SPAT_TOG1

V1SPAT_TOG2

V2SPAT_TOG1

Polarity Change Position Start for V1 SPAT

Polarity Change Position End for V1 SPAT

(18:6)

(5:0)

Mode_Reg(6) (31:25)

(24:12)

7

13

12

1078

1168

V2SPAT_TOG1

V2SPAT_TOG2

V3SPAT_TOG1

Polarity Change Position Start for V2 SPAT

Polarity Change Position End for V2 SPAT

(11:0)

Mode_Reg(7) 31

(30:18)

1

958

1138

988

V3SPAT_TOG1

V3SPAT_TOG2

V4SPAT_TOG1

V4SPAT_TOG2

Polarity Change Position Start for V3 SPAT

Polarity Change Position End for V3 SPAT

Polarity Change Position Start for V4 SPAT

13

5

(17:5)

(4:0)

Mode_Reg(8) (31:24)

8

13

2

1228

1392

3

V4SPAT_TOG2

SECONDVPOS

VPATSECOND

Polarity Change Position End for V4 SPAT

Second V Pattern Output Position

Selected Second V Pattern Group for VSG Active Line

Unused

(23:11)

(10:9)

(8:0)

9

*Register value must be a gray code number. (See Gray Code Registers section.)

REV. 0

–15–

AD9898

SYSTEM OVERVIEW

MAXIMUM FIELD DIMENSIONS

Figure 5 shows the typical system block diagram for the AD9898.

The CCD output is processed by the AD9898’s AFE circuitry,

which consists of a CDS, VGA, black level clamp, and A/D

converter. The digitized pixel information is sent to the digital

image processor chip, which performs the postprocessing and

compression. To operate the CCD, all CCD timing parameters

are programmed into the AD9898 from the system micropro-

cessor, through the 3-wire serial interface. From the system

master clock, CLI, provided by the image processor or external

crystal, the AD9898 generates all the CCD’s horizontal and

vertical clocks and all internal AFE clocks. External synchroni-

zation is provided by a SYNC pulse from the microprocessor,

which will reset internal counters and resynchronize the VD and

HD outputs.

12-BIT HORIZONTALCOUNTER = 4096 PIXELS MAX

V1–V4, VSG1, VSG2, SUBCK

V-DRIVER

Figure 6. Horizontal and Vertical Counters

H1, H2, RG, VSUB

DOUT[9:0]

CCDIN

DCLK1

FD

CCD

CLI INPUT CLOCK DIVIDER

DIGITAL

IMAGE

PROCESSING

ASIC

The AD9898 provides the capability of dividing the CLI input

clock using register CLKDIV (Addr 0xD5). The following

procedure must be followed to reset the AFE and digital circuits

when CLKDIV is reprogrammed back to 0 from CLKDIV = 1,

2, or 3. The DCLK1 output will become unstable if this proce-

dure is not followed:

AD9898

HD, VD

VGATE

CLI

MSHUT

STROBE

SERIAL

INTERFACE

OUTCONT

SYNC

ꢁP

Step 1: CLKDIV = 1, 2, or 3 (CLI divided by setting value)

Step 2: CLKDIV = 0 (CLI reprogrammed for no division)

Step 3: DIGSTBY = AFESTBY = 0

Figure 5. Typical System Block Diagram, Master Mode

Step 4: DIGSTBY = AFESTBY = 1

The AD9898 powers up in slave mode, in which the VD and

HD are provided externally from the image processor. In this

mode, all AD9898 timing will be synchronized with VD and

HD. The H-drivers for H1–H2 and RG are included in the

AD9898, allowing these clocks to be directly connected to the

CCD. H-drive voltage of up to 3.6 V is supported. An external

V-driver is required for the vertical transfer clocks, the sensor

gate pulses, and the substrate clock. The AD9898 also includes

programmable MSHUT and STROBE outputs, which may be

used to trigger mechanical shutter and strobe (flash) circuitry.

GRAY CODE REGISTERS

Table V lists the AD9898 registers requiring gray code values.

Below is an example of applying a gray code number for

HDLEN using a line length of 1560 pixels:

HDLEN = (1560 – 4) = 1556₁₀

(See Table XI note about HDLEN.)

1556₁₀= 0x51E

The gray code value of 0x51E would be programmed in the

12-bit HDLEN register.

Figure 6 shows the horizontal and vertical counter dimensions

for the AD9898. All internal horizontal and vertical clocking is

programmed using these dimensions and is used to specify line

and pixel locations.

Table V. Gray Code Registers

Register Name

Register Type

HDLEN

System_Reg(12)

System_Reg(15)

System_Reg(15 and 16)

Mode_Reg(1)

CLPTOG1

CLPTOG2

HDLASTLEN

–16–

REV. 0

AD9898

System Register Serial Interface

SERIAL INTERFACE TIMING

There are seventeen 32-bit system registers that get accessed

sequentially at Address 0x14 beginning with Sys_Reg[0]. When

writing to the system registers, SDATA contains the 8-bit address

of 0x14, followed by Number Writes N[23:0], followed by the

Sys_Reg[31:0] data as shown in Figure 8. The system register

map is listed in Table II.

All of the internal registers of the AD9898 are accessed through a

3-wire serial interface. The interface consists of a clock (SCK),

serial load (SL), and serial data (SDATA).

The AD9898 has three different register types that are config-

ured by the 3-wire serial interface. They are control registers,

system registers, and mode registers and are described in Table VI.

There are two options available when writing to the system

registers. The choice is automatically determined by the value of

the Number Writes N[23:0] word. If Number Writes N[23:0] =

0x000000, the device gets put into a mode where it expects all

17 Sys_Reg[31:0] data-words to be clocked in before SL is

asserted high. If the Number Writes N[23:0] is decoded as

some number N other than 0x000000, the device expects N

number of registers to be programmed where N is equal to the

value of Number Writes N[23:0]. For example, if Number

Writes N[23:0] = 0x000004, the device would expect data to be

provided for Sys_Reg[3:0]. In all cases, the system registers

would be written to begin with Sys_Reg[0], no matter what the

value of Number Writes N[23:0] is. Note that SL can be brought

high or low during access to system registers, as shown in Figure 8.

Table VI. Type of Serial Interface Registers

Register

Address

No. of Registers

Control

0x00 through There is a 24-bit register at each

0xD6

0x14

0x15

0x16

address. Not all addresses are

used. See Table I.

System

Seventeen 32-bit system registers

at Address 0x14. See Table II.

Mode_A

Mode_B

Eight 32-bit Mode_A registers at

Address 0x15. See Table III.

Eight 32-bit Mode_B registers at

Address 0x16. See Table IV.

Mode_A and Mode_B Register Serial Interface

There are eight 32-bit Mode_A and eight 32-bit Mode_B regis-

ters that get accessed sequentially at Address 0x15 and Address

0x16, respectively. The Mode_A and Mode_B registers get

written to exactly as the system registers are. (See the descrip-

tion above.) The mode registers are listed in Tables III and IV.

Control Register Serial Interface

The control register 3-wire interface timing requirements are

shown in Figure 7. Control data must be written into the device

one address at a time due to the noncontiguous address spacing

for the control registers. This requires eight bits of address data

followed by 24 bits of configuration data between each active

low period of SL for each address. The SL signal must be kept

high for at least one full SCK cycle between successive writes to

control registers.

Changing operation between Mode_A and Mode_B is done by

setting the 1-bit MODE register (Addr 0x0A). The desired

Mode_A (Addr 0x15) or Mode_B (Addr 0x16) data must be

programmed into the Mode_A or Mode_B registers before

changing the MODE bit.

....

SDATA

SCK

A7

A6

t_DH

A5

A4

A3

A2

A1

A0

D23

D22

D21

D3

D2

D1

D0

t_DS

1

2

3

4

5

6

7

8

9

10

11

29

30

31

t_LH

32

t_LS

SL

1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.

2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.

3. THIS TIMING PATTERN MUST BE WRITTEN FOR EACH REGISTER WRITE WITH SL REMAINING HIGH FOR AT

LEAST ONE FULL SCK PERIOD BEFORE ASSERTING SL LOW AGAIN FOR THE NEXT REGISTER WRITE.

Figure 7. 3-Wire Serial Interface Timing for Control Registers

REV. 0

–17–

AD9898

ADDRESS [7:0]

DATA 1 [31:0]

1

NUMBER WRITES N [23:0]

DATA 2 [31:0]

1

DATA N [31:0]

SDATA

8-BIT

ADDRESS

NUMBER OF 32-BIT

DATA WRITES (N)

SCK

SL

1

2

1. ALL SL PULSES ARE IGNORED UNTIL THE LSB OF THE LAST DATA N WORD IS CLOCKED IN.

2. VALID SL PULSE. SL MUST BE ASSERTED HIGH WHEN ALL SDI DATA TRANSMISSIONS HAVE BEEN FINISHED.

Figure 8. System and Mode Register Writes

OPERATION OF VD SYNCHRONOUS TYPE

REGISTER WRITES BEGIN AT THE NEXT VD

FALLING EDGE.

VD

HD

CLI

PROGRAMMING OF VD SYNCHRONOUS

TYPE REGISTERS MUST BE COMPLETED

AT LEAST 4 CLI CYCLES BEFORE THE

FALLING EDGE OF VD.

Figure 9. VD Synchronous Type Register Writes

VD SYNCHRONOUS AND ASYNCHRONOUS REGISTER

OPERATION

VD Synchronous Register Operation

For VD synchronous type registers, SDATA data is temporarily

stored in a buffer register at the rising edge of SL. This data is

held in the buffer register until the next falling edge of VD is

applied. Once the next falling edge of VD occurs, the buffered

SDATA data is loaded into the serial register and the register

operation begins (see Figure 9).

There are two types of control registers, VD synchronous and

VD asynchronous, as indicated in the address column of Table I.

Register writes to synchronous and asynchronous type registers

operate differently, as described below. Writes to system, Mode_A,

and Mode_B registers occur asynchronously.

Asynchronous Register Operation

All control registers at the following addresses are VD Synchro-

nous type registers—Addr: 0x0A, 0x0B, 0x0C, 0x0D, and 0x0E

(see Table I).

For VD asynchronous register writes, SDATA data is stored

directly into the serial register at the rising edge of SL. As a

result, register operation begins immediately after the rising

edge of SL.

–18–

REV. 0

AD9898

ANALOG FRONT END (AFE) DESCRIPTION AND

OPERATION

The AD9898 AFE signal processing chain is shown in Figure 10.

Each processing step is essential to achieving a high quality image

from the raw CCD pixel data. Registers for the AD9898 AFE

section are listed in Table VII.

PRECISION TIMING HIGH SPEED TIMING GENERATION

The AD9898 generates flexible high speed timing signals using

the Precision Timing core. This core is the foundation for gen-

erating the timing used for both the CCD and the AFE signals,

including the reset gate RG, the horizontal drivers H1–H2, and

the CDS sample clocks. By providing precise control over the

horizontal CCD readout and the AFE correlated double sampling,

the unique architecture of the AD9898 makes optimizing image

quality a routine task for a system designer.

DC Restore

To reduce the large dc offset of the CCD output signal, a dc

restore circuit is used with an external 0.1 µF series coupling

capacitor. This restores the dc level of the CCD signal to approxi-

mately 1.5 V, which is compatible with the 3 V analog supply of

the AD9898.

Timing Resolution

The Precision Timing core uses a 1× master clock input (CLI)

as a reference. This clock should be the same as the CCD pixel

clock frequency. Figure 11 illustrates how the internal timing

core divides the master clock period into 48 steps or edge posi-

tions. Using a 20 MHz CLI frequency for the AD9898, the

edge resolution of the Precision Timing core is 1 ns. A 40 MHz

CLI frequency can be applied where the AD9898 will inter-

nally divide the CLI frequency by two. Division by one-third

and one-fourth is also provided. CLI frequency division is con-

trolled using the CLKDIV (Addr 0xD5) register.

Correlated Double Sampler

To extract the video information and reject low frequency noise,

the CDS circuit samples each CCD pixel twice. The timing

shown in Figure 12 illustrates how the two internally generated

CDS clocks, SHP and SHD, are used to sample the reference

level and the data level of the CCD signal, respectively. The

placement of the SHP and SHD sampling edges is determined

by the setting of the SHPLOC (Addr 0x02) and SHDLOC

(Addr 0x02) registers. Placement of these two clock edges is criti-

cal to achieving the best performance from the CCD.

High Speed Clock Programmability

Figure 13 shows how the high speed clocks RG, H1–H2, SHP,

and SHD are generated. The RG pulse has a fixed rising edge

and a programmable falling edge. The horizontal clock H1

has a programmable rising and a fixed falling edge occurring at

H1POSLOC + 24 steps. The H2 clock is always the inverse of

H1. Table VIII summarizes the high speed timing registers and

the parameters for the high speed clocks. Each register is six bits

wide with the 2 MSB used to select the quadrant region as

outlined in Table VIII. Figure 13 shows the range and de-

fault locations of the high speed clock signals.

Table VII. AFE Registers

Register

Name

Bit

Width Register Type

Description

VGAGAIN

REFBLACK

AFESTBY

10

6

1

Control (Addr 0x0E) VGA Gain

Control (Addr 0x04) Blk Clamp Level

Control (Addr 0x05) AFE Standby

1.0ꢁF

REFT

2.0V

1.0ꢁF

REFB

1.0V

DC RESTORE

AD9898

INTERNAL

1.5V

V

REF

DOUT

PHASE

2V FULL

SCALE

SHP

SHD

6dB TO 40dB

0.1ꢁF

OUTPUT

DATA

LATCH

10

CCDIN

ADC

CDS

VGA

DOUT

10

OPTICAL BLACK

CLAMP

8-BIT

DAC

VGA GAIN

REGISTER

CLPOB

DIGITAL

FILTER

6

DOUT

PHASE

SHD

CLPOB

SHP

CLAMP LEVEL

REGISTER

V-H

PRECISION

TIMING

GENERATION

Figure 10. AFE Block Diagram

REV. 0

–19–

AD9898

H-Driver and RG Outputs

As shown in Figure 13, the H2 output is the inverse of H1. The

internal propagation delay resulting from the signal inversion is

less than 1 ns, which is significantly less than the typical rise

time driving the CCD load. This results in an H1/H2 crossover

voltage of approximately 50% of the output swing. The cross-

over voltage is not programmable.

In addition to the programmable timing positions, the AD9898

features on-chip output drivers for the RG and H1–H2 outputs.

They are sufficiently powerful to directly drive the CCD inputs.

The H-driver current can be adjusted for optimum rise/fall time

into a particular load by using the H1DRV and H2DRV regis-

ters (Addr 0x04). The RG drive current is adjustable using the

RGDRV register (Addr 0x04). The H1DRV and H2DRV regis-

ter is adjustable in 4.3 mA increments. The RGDRV register is

adjustable in 2.15 mA increments. All DRV registers have a setting

of 0 equal to OFF or three-state, and the maximum setting of 7.

Digital Data Outputs

The AD9898 DOUT[9:0] and DCLK phases are independently

programmable using the DOUTPHASE register (Addr 0x02)

and DCLKPHASE register (Addr 0x02) (see Figure 15).

POSITION

CLI

P[0]

P[12]

P[24]

P[36]

P[48] = P[0]

t_CLIDLY

1 PIXEL

PERIOD

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (t_CLIDLY= 6 ns TYP).

Figure 11. High Speed Clock Resolution from CLI Master Clock Input

3

CCD

SIGNAL

4

cds

(INTERNAL)

1

5

2

RG

6

H1

H2

PROGRAMMABLE CLOCK POSITIONS

1. RG RISING EDGE (FIXED EDGE AT 000000).

2. RG FALLING EDGE (RGNEGLOC (ADDR 0x03)).

3. SHP SAMPLE LOCATION (SHPLOC (ADDR 0x02)).

4. SHD SAMPLE LOCATION (SHDLOC (ADDR 0x02)).

5. H1 RISING EDGE LOCATION (H1POSLOC (ADDR 0x03))

6. H1 NEGATIVE EDGE LOCATION (FIXED AT (H1POSLOC + 24 STEPS)).

7. H2 IS ALWAYS THE INVERSE OF H1.

Figure 12. High Speed Clock Programmable Locations

–20–

REV. 0

AD9898

Table VIII. RG, H1, SHP, SHD, DCLK, and DOUTPHASE Timing Parameters

Register Name

Bit Width

Register Type

Range

Description

RGNEGLOC

H1POSLOC

SHPLOC

SHDLOC

DOUTPHASE

DCLKPHASE

6

Control (Addr 0x03)

Control (Addr 0x02)

0–47 Edge Location

Falling Edge Location for RG

Positive Edge Location for H1

Sample Location for SHP

Sample Location for SHD

Phase Location of Data Output [9:0]

Positive Edge of DCLK 1

The 2 MSB are used to select the quadrant.

Table IX. Precision Timing Edge Locations for RG, H1, SHP, SHD, DCLK, and DOUTPHASE

RG Rising Edge

RG Falling Edge

Signal Name

Quadrant

(Not Programmable)

RGNEGLOC

Quadrant Range

RG

I

II

III

IV

Fixed at 000000

000000 to 001011

010000 to 011011

100000 to 101011

110000 to 111011

P[0] to P[11]

P[12] to P[23]

P[24] to P[35]

P[36] to P[47]

H1 Rising Edge

Quadrant Range

H1 Falling Edge

Signal Name

Quadrant

H1POSLOC

(Not Programmable)

H1

I

II

III

IV

000000 to 001011

010000 to 011011

100000 to 101011

110000 to 111011

P[0] to P[11]

P[12] to P[23]

P[24] to P[35]

P[36] to P[47]

H1POSLOC + 24 Steps

cds Rising Edge

cds Falling Edge

Signal Name

Quadrant

SHPLOC

Quadrant Range

SHDLOC

Quadrant Range

cds

I

II

III

IV

000000 to 001011

010000 to 011011

100000 to 101011

110000 to 111011

P[0] to P[11]

P[12] to P[23]

P[24] to P[35]

P[36] to P[47]

000000 to 001011

010000 to 011011

100000 to 101011

110000 to 111011

P[0] to P[11]

P[12] to P[23]

P[24] to P[35]

P[36] to P[47]

Data Output[9:0] Rising Edge

Data Output[9:0] Falling Edge

(Not Programmable)

Signal Name

Quadrant

DOUTPHASE

Quadrant Range

Data Output[9:0]

I

II

III

IV

000000 to 001011

010000 to 011011

100000 to 101011

110000 to 111011

P[0] to P[11]

P[12] to P[23]

P[24] to P[35]

P[36] to P[47]

DOUTPHASE + 24 Steps

Signal Name

DCLKPHASE Value

DCLKPHASE Rising Edge

DCLKPHASE Falling Edge

DCLK1

00

01

10

11

P[6]

P[26]

P[36]

P[06]

P[16]

P[26]

P[36]

REV. 0

–21–

AD9898

P[0]

P[12]

P[24]

P[36]

P[48] = P[0]

POSITION

PIXEL

PERIOD

RGr[0]

Hr[0]

RGf[12]

RG

H1

Hf[24]

cds

(INTERNAL)

t_S1

SHP[20]

CCD

SIGNAL

SHD[40]

1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLETO ANY OFTHE 48 POSITIONSWITHIN ONE PIXEL PERIOD.

2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.

Figure 13. High Speed Clock Default and Programmable Locations

t_RISE

H1

H2

t_PD< t_RISE

t_PD

H2

H1

FIXED CROSSOVER VOLTAGE

Figure 14. H-Clock Inverse Phase Relationship

P[0]

P[12]

P[24]

P[36]

P[48] = P[0]

PIXEL

PERIOD

DCLK1

t_OD

DOUT

1. DCLK1 PHASE IS ADJUSTED BY SETTING THE DCLKPHASE REGISTER (ADDR 0x02).

2. DOUT PHASE CAN BE ADJUSTED BY SETTING THE DOUTPHASE REGISTER (ADDR 0x02).

Figure 15. Digital Output Phase Adjustment

–22–

REV. 0

AD9898

EXTERNAL SYNCHRONIZATION (MASTER MODE)

External synchronization can be used to synchronize the VD

and HD signal by applying an external pulse on the SYNC/

VGATE pin (Pin 45) for master mode operation. The SYNC/

VGATE pin is configured as an external SYNC input for mas-

ter mode operation by setting the SLAVE_MODE register

(Addr 0xD6) = 0. (The AD9898 defaults to slave mode at

power-up.)

Table X. External Synchronization (Master Mode)

SYNCCNT

External Synchronization Options

0

1

2

3

4

5

6

7

Disable External Synchronization

VD Sync at every SYNC Pulse

VD Sync after Second Applied SYNC Pulse

VD Sync after Third Applied SYNC Pulse

VD Sync after Fourth Applied SYNC Pulse

VD Sync after Fifth Applied SYNC Pulse

VD Sync after Sixth Applied SYNC Pulse

VD Sync after Seventh Applied SYNC Pulse

VD Sync after Eighth Applied SYNC Pulse

VD Sync after Ninth Applied SYNC Pulse

VD Sync after Tenth Applied SYNC Pulse

VD Sync after Eleventh Applied SYNC Pulse

VD Sync after Twelfth Applied SYNC Pulse

VD Sync after Thirteenth Applied SYNC Pulse

VD Sync after Fourteenth Applied SYNC Pulse

VD Sync after First Applied SYNC Pulse Only

SYNCCNT (Addr 0x0A) and SYNCPOL (Addr 0x01) are the

only two registers used for configuring the AD9898 for external

synchronization. The SYNCPOL is a 1-bit register used for

configuring the SYNC input as either active low or active high.

The AD9898 defaults to active low at power-up. The function

of the SYNCCNT register is described in Table X. Figures 16

and 17 provide two examples of external synchronization with

SYNCPOL = 0.

8

9

10

11

12

13

14

15

4 CLI

VD

SYNC

2 CLI

MIN

CHANGE TO MODE B

SERIAL

WRITES

OPERATION

MODE

MODE A

MODE B

Figure 16. Example of Synchronization with SYNCPOL = 0 and SYNCCNT = 1

4 CLI

VD

SYNC

2 CLI

MIN

Figure 17. Example of Synchronization with SYNCPOL = 0 and SYNCCNT = 3

REV. 0

–23–

AD9898

HORIZONTAL AND VERTICAL SYNCHRONOUS TIMING

The HD and VD output pulses are programmable using the

registers listed in Table XI. The HD output is asserted low at

the start of the horizontal line shift. The VD output is asserted

low at the start of each line. As shown in Figure 18, the 11-bit

VD counter is used to count the number of lines set by the

VDLEN register. The 12-bit HD counter is used to count the

number of pixels in each line set by the HDLEN register. For

example, if the CCD array size is 2000 lines by 2100 pixels per

line, VDLEN = 2000 and HDLEN = 0xC28. The HLEN regis-

ter sets the HL counter that is used as a reference for the rising

edge of the HD pulse.

Special Note about the HDLEN Register

The 12-bit HD counter value must be programmed using a gray

code number. There is also a 4-clock cycle setup period that

must be considered when determining the HDLEN register

value, as shown in Figure 18. As a result of the 4-clock cycle

setup period, the value of HDLEN is always equal to the actual

number of pixels per line minus four. For example, if there are

2100 pixels per line, HDLEN equals (2100 – 4) = 2096. The

gray code value of 2096 is 0xC28, which is what would be pro-

grammed in the HDLEN register.

Table XI. HD and VD Registers

Register

Name

Bit

Width

Reference

Counter

Register Type

Range

Description

HDLEN

HLEN

HDRISE

HDLASTLEN*

VDLEN

12

10

12

11

4

Sys_Reg(12)

Sys_Reg(16)

Mode_Reg(1)

Sys_Reg(16)

0–4095 Pixels

0–1023 Pixels

0–4095 Pixels

0–2047 Lines

0–15 Lines

12-Bit Gray Code Counter Value

10-Bit HL Counter Value

HD Rise Position

HD Last Line Length

VD Counter Value

HL

HD

VDRISE

VD

VD Rise Position

*Register value must be a gray code number. (See Gray Code Registers section.)

VDLEN

11-BIT

VD COUNTER

000

001

002

N

2048

HDLEN

SETUP

HDLASTLEN

12-BIT

GRAY COUNTER

+ SETUP

HLEN

10-BIT

HL COUNTER

VD

HD

2

1

LINE LENGTH =

HDLEN + 4

1. THE SETUP DELAY IS 4 CLI CYCLES. THE ACTUAL LENGTH OF ONE LINE IS 4

MORE CYCLES THAN THE VALUE SET IN HDLEN AND HDLASTLEN DUE TO SETUP DELAY.

2. VDRISE REFERENCES THE 11-BIT VD COUNTER.

3. HDRISE REFERENCES THE 10-BIT HL COUNTER.

PROGRAMMABLE CLOCK POSITIONS

1. HDRISE (SYS_REG(16))

2. VDRISE (SYS_REG(16))

Figure 18. VD and HD Horizontal Timing

–24–

REV. 0

AD9898

Table XII. CLPOB Registers

Reference

Register

Name

Bit

Width Register Type

Counter Range

Description

CLP_CONT

CLP_MODE 1

1

Control (0x01)

Control(0x01)

CLPOB Control (0 = CLPOB Off, 1 = CLPOB On)

CLPOB CCD Region Control

(0 = Enable CLPENx Register Settings,

1 = Disable CLPENx Register Settings)

CLPTOG1

CLPTOG2

CLPEN0

12

1

Sys_Reg(15)

Sys_Reg(15 and 16) HD

Mode_Reg(2)

HD

0–4095 Pixel Locations CLPOB Toggle Position 1 (Gray Code Number)

0–4095 Pixel Locations CLPOB Toggle Position 2 (Gray Code Number)

CLPOB Control for CCD Region 0

(0 = CLPOB Disabled, 1 = CLPOB Enabled)

CLPOB Control for CCD Region 1

(0 = CLPOB Disabled, 1 = CLPOB Enabled)

CLPOB Control for CCD Region 2

(0 = CLPOB Disabled, 1 = CLPOB Enabled)

CLPOB Control for CCD Region 3

(0 = CLPOB Disabled, 1 = CLPOB Enabled)

CLPOB Control for CCD Region 4

CLPEN1

CLPEN2

CLPEN3

CLPEN4

1

Mode_Reg(2)

(0 = CLPOB Disabled, 1 = CLPOB Enabled)

VD

HD

12-BIT

GRAY COUNTER

+ SETUP

CLPOB

1

2

PROGRAMMABLE CLOCK POSITIONS

1. CLPTOG1 (SYS_REG(15))

2. CLPTOG2 (SYS_REG(15 AND 16))

Figure 19. Location of CLPOB Using CLPTOG1 and CLPTOG2 Registers

HORIZONTAL CLAMPING AND BLANKING

Figure 21 shows that no CLPOB pulse will be applied when the

last HD length set by HDLASTLEN is longer than the regular

HD length. Note that the CLPOB pulse is applied in the last

line only when HDLASTLEN = HDLEN.

The AD9898’s horizontal clamping and blanking pulses are

programmable to suit a variety of applications. Similar to verti-

cal timing generation, individual sequences are defined for each

signal and are then organized into multiple regions during

image readout. This allows the dark pixel clamping and blanking

patterns to be changed at each stage of the readout to accommo-

date different image transfer timing and high speed line shifts.

HD

CLPOB

Controlling CLPOB Clamp Pulse Timing

LAST LINE

The AFE horizontal CLPOB pulse is generated based on the

12-bit gray code counter. Once the length of the 12-bit gray

code counter is set using the HDLEN register (Sys_Reg(12)),

CLPTOG1 and CLPTOG2 registers (Sys_Reg(15 and16)) can

be used to place the CLPOB pulse location, as shown in Figure 19.

Table XII lists all CLPOB registers that are used to configure

and control the placement and output of the CLPOB pulse.

Figure 20. Last HD Shorter Than Regular HD

HD

CLPOB

LAST LINE

The length of the last HD line is set using the HDLASTLEN

register (Sys_Reg(1)). Figure 20 shows that no CLPOB pulse

will be asserted when the last HD length set by HDLASTLEN

is shorter than the regular HD length set by HDLEN.

Figure 21. Last HD Longer Than Regular HD

REV. 0

–25–

AD9898

Controlling CLPOB Clamp Pulse Outputs

Table XIII. SCP and CLPEN

The registers in Table XII are used for programming the CLPOB

pulse, which will be disabled in all CCD regions by setting

CLPCNT = 0. The CLPTOGx (x = 0, 1) are used to set the

CLPOB toggle positions. The CLPENx (x = 0, 1, 2, 3, and 4)

are used to enable or disable the CLPOB pulse separately in

each CCD region when CLPMODE = 0. The CLPEN regis-

ters have no effect if CLPMODE = 1. In this case, the CLPOB

pulse will be asserted in all CCD regions, regardless of the value

set in the CLPENx registers.

SCP[4:1]

CLPEN[4:0]

SCP0*

SCP1

SCP2

SCP3

SCP4

CLPEN0

CLPEN1

CLPEN2

CLPEN3

CLPEN4

*SCP0 is not a programmable register and therefore is not listed in the register

map tables. SCP0 is a fixed sequence and always starts at the falling edge of

VD. Although this register is not programmable, the CLPEN0 register is still

used to enable or disable the CLPOB pulse for the SCP0 region.

Figure 22 shows an example of the CLPOB pulse being disabled

in CCD Regions 1 and 3 by setting CLPEN1 = 1 and CLPEN3

= 1. Note that the CLPOB pulse remains disabled in the first

line of the following CCD region.

VD

HD

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CLPOB

CLPMASK

(INTERNAL)

A

B

1

2

3

4

5

PROGRAMMING POSITIONS

1. SCP0 = 0 (FIXED), CLPEN0 = 1

2. SCP1 = 3, CLPEN1 = 0

3. SCP2 = 4, CLPEN2 = 1

4. SCP3 = 5, CLPEN3 = 0

5. SCP4 = 1, CLPEN4 = 1

NOTE

THE INTERNAL CLPMASK SIGNAL EXTENDS ONE EXTRA HD CYCLE FROM THE TIME WHEN THE

CLPMASK PERIOD CHANGES FROM LOW TO HIGH. AS A RESULT, ONE ADDITIONAL CLPOB PULSE

IS MASKED, AS SHOWN AT POSITIONS A AND B.

Figure 22. CLPOB Outputs with CLPMODE = 0

–26–

REV. 0

AD9898

H1 AND H2 BLANKING

Selective Positioning for Two H1 and H2 Outputs

The AD9898 provides three options for controlling the period

where H1 and H2 pulses get blanked. These options are normal

H blanking, selective positioning for 2 H1 and H2 outputs, and

extended blanking. In all cases, HBLKMASK is used to set the

polarity of H1 during the blanking period. Table XIV describes

the registers used to control H blanking.

For selective positioning operation, HPULSECNT = 1 and

HBLKMASK = 0 or 1. In this mode, two H1 pulses are output

during the blanking period. The location of these two pulses are

set using the HBLKHPOS register, as shown in Figure 24.

Extended Blanking

Extended blanking is enabled by setting HBLKEXT = 1. The

HBLKEXT register uses the 9-bit BL counter to suspend operation

of the HD and HL counters. This delays the blanking period by

the length set in the BLLEN register as shown in Figure 25.

Normal H Blanking

For normal H blanking operation, HPULSECNT = 0 and

BLKMASK = 0 or 1. The HBLKHPOS register is not used in

this mode. Figure 23 shows one example where HBLKMASK = 0.

As seen in Figure 23, H1 and H2 are blanked while HD is Low.

Table XIV. H1 Blanking Registers

Register

Name

Bit

Width

Register Type

Description

HBLKMASK

HPULSECNT

1

Control (0x01)

Control (0x0A)

Masking Polarity for H1 during Blanking Period¹(0 = Low, 1 = High)

H Pulse Control during Blanking Period

(0 = No Output during Blanking, 1 = Output during Blanking)

HBLKEXT

1

Control (0x0A)

Control (0x03)

Sys_Reg(11)

H Pulse Blanking Extend Control²

(0 = Extended Blanking Disabled, 1 = Extended Blanking Enabled)

Retimes the H1 HBLK to Internal Clock

(0 = Retiming Disabled, 1 = Retiming Enabled)

H1 Pulse ON Position during Blanking Period

H1BLKRETIME

1

HBLKHPOS

10

NOTES

¹The polarity of H2 is always the opposite polarity of the H1 polarity.

²The HBLKEXT extend control extends the blanking period by the number of counts set in the BLLEN register for the 9-bit BL counter.

HD

HDRISE

HBLK

(INTERNAL)

1

H1

H2

RG

1. THE RISING EDGE OF HBLK IS ALWAYS THE SAME AS HDRISE.

Figure 23. Normal H-Blanking Operation HBLKMASK = 0, HPULSECNT = 0, HBLKHPOS = xxx

REV. 0

–27–

AD9898

HD

HBLK

(INTERNAL)

H12

(INTERNAL)

RG

H1

THE H2 POLARITY IS OPPOSITE THE POLARITY OF H1.

Figure 24. Selective H-Blanking Operation HBLKMASK = 0, HPULSECNT = 1, HBLKHPOS = 003

BLLEN

9-BIT

BL COUNTER

VD

HD

H1

1

2

CLPOB

3

4

1. POSITIONS 1, 2, 3, AND 4 ARE DELAYED BY THE VALUE OF THE BL COUNTER.

2. VSG1, VSG2, V1–V4, AND SUBCK PULSES ARE NOT DELAYED BY THE BL COUNTER.

Figure 25. VD, HD, and H1 Extended Blanking Operation HBLKEXT = 1

–28–

REV. 0

AD9898

VGATE MASKING OF V1–V4 AND CLPOB OUTPUTS

During slave mode operation, the SYNC/VGATE, Pin 45, is

configured as an input for an external VGATE signal. While

operating in this mode, the external VGATE signal can be used

to mask the V1–V4 and CLPOB outputs. There are two options

available for masking the V1–V4 and CLPOB outputs. The

selection is made by setting the MSHUT/VGATE_EN register

located at Control Addr 0x01. Examples of these two options

are shown in Figures 26 and 27.

Figure 26 shows an example of MSHUT/VGATE_EN = 0. In

this example, the VGATE signal is internally latched on the

falling edge of HD, resulting in the V1–V4 and CLPOB outputs

being masked when the internally latched VGATE signal is High.

Figure 27 shows an example when MSHUT/VGATE_EN = 1.

In this example, the preprogrammed MSHUT signal blocks the

VGATE input from masking V1–V4 and CLPOB outputs while

MSHUT is Low. The internally latched VGATE signal will

only mask V1–V4 and CLPOB when MSHUT is High while

operating in this mode.

VD

HD

VGATE

(PIN 45)

VGATE

(INTERNAL)

V1–V4

CLPOB

V1–V4 AND CLPOB MASKED

Figure 26. Example of VGATE Input Masking V1–V4 and CLPOB Outputs with MSHUT/VGATE_EN = 0

VD

HD

VGATE

(PIN 45)

VGATE

(INTERNAL)

MSHUT

V1–V4

CLPOB

V1–V4 AND CLPOB MASKED

Figure 27. Example of VGATE Input Masking V1–V4 and CLPOB Outputs with MSHUT/VGATE_EN = 1

REV. 0

–29–

AD9898

VERTICAL TIMING GENERATION

Step 2

The AD9898 provides a very flexible solution for generating

vertical CCD timing and can support multiple CCDs and dif-

ferent system architectures. The 4-phase vertical transfer clocks

V1–V4 are used to shift each line of pixels into the horizontal

output register of the CCD. The AD9898 vertical outputs can

be individually programmed into four different vertical pulse

patterns identified as VTP0, VTP1, VTP2, and VTP3. Each

vertical pulse pattern is a unique set of preconfigured V1–V4

sequences. Once the vertical patterns have been configured

using the registers in Table XVII, pointer registers are used to

select which region of the CCD a particular vertical pattern is

output in. The pointer registers are described in Table XV.

Create the Individual Vertical Sequences (See Figure 29)

The individual vertical sequences are created by assigning pulse

repetitions to patterns VTP0, VTP1, VTP2, and VTP3, using

VTPREPx registers in Table XVI. The number of repetitions

(VTPREPx) determines the number of pulse repetitions desired

within a single line. Programming 1 for VTPREPx gives a single

pulse, while setting it to 0 will provide a fixed dc output based

on the start polarity value. Figure 29 shows an example of a VTPx

sequence of two VTPx patterns made by setting VTPREPx = 2.

Step 3

Output Vertical Sequences into CCD Regions (See Figure 30)

The AD9898 arranges individual sequences into CCD regions

through the use of sequence pointers (VTPSEQPTRx) and

vertical transfer pattern select (VTPSELx) registers, as described

in Table XVI. The VTPSEQPTRx registers are used to point to

a desired VTPSELx register whose value determines what VTPx

pattern will be output on the V1–V4 pins. For example, if

VTPSEQPTR0 = 1 and VTPSEL1 = 2, the VTP2 pulse pattern

would output while operating in Region 0 of the CCD.

Up to five unique CCD regions may be specified. The readout

of the entire field is constructed by combining one or more of

the individual regions sequentially. With up to five region areas

available, different steps of the readout, such as high speed line

shifts and vertical image transfer, can be supported.

Creating Vertical Sequences

Figures 28, 29, and 30 provide an overview of how the vertical

timing is generated in four basic steps.

Step 4

Combining CCD Regions (See Figure 30)

The entire field readout can be built by combining multiple regions

by using mode registers SCP0, SCP1, SCP2, SCP3, and SCP4.

Step 1

Create the Individual Pulses for Patterns VTP0, VTP1, VTP2,

and VTP3 (See Figure 28)

The registers shown in Table XV are used to generate the

individual vertical timing pulses, as shown in Figure 28. The

VTPLENx determines the number of pixels between pulse

repetitions. The start polarity (VxSTARTPOLx) sets the start-

ing polarity of the vertical sequence and can be programmed

high or low. The first toggle position (VxTOG1POSx) and

second toggle position (VxTOG2POSx) are the pixel locations

within the line where the pulse transitions.

The individual CCD regions are combined into a complete field

readout using the sequence change position (SCPx) pointers as

described in Table XVII. Figure 30 shows how each field is

divided into multiple regions which allows the user to change

vertical timing during various stages of the image readout. The

boundaries of each region are defined by the sequence change

position (SCP). Each SCP is an 8-bit value representing the line

number boundary region. A total of four SCPs allow up to five

different regions in the field to be defined. The first SCP0 is

always hard coded to line zero, and the remaining four SCPs are

register programmable.

0

50

100

150

200

250

300

350

400

HD

1

4

2

3

V1

V2

5

6

7

8

9

V3

V4

10

11

12

VTPLENx [8:0] = 210

PROGRAMMABLE CLOCK POSITIONS

1. V1STARTPOLx = 0

2. V1TOG1x[8:0] = 50

3. V1TOG2x[8:0] = 130

4. V2STARTPOLx = 1

5. V2TOG1x[8:0] = 30

6. V2TOG2x[8:0] = 150

7. V3STARTPOLx = 1

8. V3TOG1x[8:0] = 110

9. V3TOG2x[8:0] = 180

10. V4STARTPOLx = 0

11. V4TOG1x[8:0] = 20

12. V4TOG2x[8:0] = 160

Figure 28. Step 1: Create Individual Vertical Pulses for VTP0, VTP1, VTP2, and VTP3 Patterns

–30–

REV. 0

AD9898

0

50

100

150

200

250

300

350

400

HD

1

2

3

V1

V2

4

7

5

6

8

9

V3

V4

10

11

12

VTPLENx [8:0] = 210

Figure 29. Step 2: Create Individual Sequences for V1–V4 Outputs by Assigning Pulse Repetitions to VTP0, VTP1,

VTP2, and VTP3 Patterns. This Example Shows VTPREPx = 2.

SCP0

(FIXED AT LINE 0)

CCD REGION0

VERTICAL TRANSFER PULSES

SCP1 [7:0]

CCD REGION1

V1

V2

V3

V4

V1

V2

V3

V4

VTP0

VTP2

VTP1

VTP3

SCP2 [7:0]

CCD REGION2

V1

V2

V3

V4

V1

V2

V3

V4

SCP3 [7:0]

SCP4 [7:0]

CCD REGION3

CCD REGION4

SCP 0

SCP 1

REGION 1

(LINE 4)

SCP 2

REGION 2

(LINE 7)

SCP 4

REGION 4

(LINE (N + 7))

REGION 0

(FIXED AT LINE 0)

VD

HD

V1

V2

V3

V4

VTP0

VTPREP0 = 2

VTP0

VTPREP0 = 1

VTP2

VTPREP2 = 2

VTP1

VTPREP1 = 1

Figure 30. Steps 3 and 4: Example of Building an Entire Field Readout by Assigning Sequences to Multiple CCD Regions

REV. 0 –31–

AD9898

Table XV. V1–V4 Registers to Configure V1–V4 Pulse for Each VTP Pattern

Register

Name

Bit

Register

Reference

Counter

VTP

Pattern

Width Type

Range

Description

VTPLEN0

9

1

9

Sys_Reg(1)

V Counter

0–511

Length between Repetitions

V1STARTPOL0

V2STARTPOL0

V3STARTPOL0

V4STARTPOL0

V1TOG1POS0

V1TOG2POS0

V2TOG1POS0

V2TOG2POS0

V3TOG1POS0

V3TOG2POS0

V4TOG1POS0

V4TOG2POS0

Sys_Reg(1)

Sys_Reg(1 and 2)

Sys_Reg(2)

Sys_Reg(2 and 3)

Sys_Reg(3)

High/Low

0–511

V1 Starting Polarity for VTP0 (0 = LO, 1 = HI)

V2 Starting Polarity for VTP0 (0 = LO, 1 = HI)

V3 Starting Polarity for VTP0 (0 = LO, 1 = HI)

V4 Starting Polarity for VTP0 (0 = LO, 1 = HI)

V1 Toggle Position 1 for VTP0

V1 Toggle Position 2 for VTP0

V2 Toggle Position 1 for VTP0

V2 Toggle Position 2 for VTP0

V3 Toggle Position 1 for VTP0

V Counter

V

T

P

0

0–511

V3 Toggle Position 2 for VTP0

V4 Toggle Position 1 for VTP0

V4 Toggle Position 2 for VTP0

VTPLEN1

9

1

9

Sys_Reg(3)

Sys_Reg(4)

Sys_Reg(4 and 5)

Sys_Reg(5)

Sys_Reg(5 and 6)

Sys_Reg(6)

V Counter

0–512

Length between Repetitions

V1STARTPOL1

V2STARTPOL1

V3STARTPOL1

V4STARTPOL1

V1TOG1POS1

V1TOG2POS1

V2TOG1POS1

V2TOG2POS1

V3TOG1POS1

V3TOG2POS1

V4TOG1POS1

V4TOG2POS1

High/Low

0–511

V1 Starting Polarity for VTP1 (0 = LO, 1 = HI)

V2 Starting Polarity for VTP1 (0 = LO, 1 = HI)

V3 Starting Polarity for VTP1 (0 = LO, 1 = HI)

V4 Starting Polarity for VTP1 (0 = LO, 1 = HI)

V1 Toggle Position 1 for VTP1

V1 Toggle Position 2 for VTP1

V2 Toggle Position 1 for VTP1

V2 Toggle Position 2 for VTP1

V3 Toggle Position 1 for VTP1

V Counter

V

T

P

1

0–511

V3 Toggle Position 2 for VTP1

V4 Toggle Position 1 for VTP1

V4 Toggle Position 2 for VTP1

VTPLEN2

9

1

9

Sys_Reg(6)

Sys_Reg(7)

Sys_Reg(7 and 8)

Sys_Reg(8)

V Counter

0–512

Length between Repetitions

V1STARTPOL2

V2STARTPOL2

V3STARTPOL2

V4STARTPOL2

V1TOG1POS2

V1TOG2POS2

V2TOG1POS2

V2TOG2POS2

V3TOG1POS2

V3TOG2POS2

V4TOG1POS2

V4TOG2POS2

High/Low

0–511

V1 Starting Polarity for VTP2 (0 = LO, 1 = HI)

V2 Starting Polarity for VTP2 (0 = LO, 1 = HI)

V3 Starting Polarity for VTP2 (0 = LO, 1 = HI)

V4 Starting Polarity for VTP2 (0 = LO, 1 = HI)

V1 Toggle Position 1 for VTP2

V1 Toggle Position 2 for VTP2

V2 Toggle Position 1 for VTP2

V2 Toggle Position 2 for VTP2

V3 Toggle Position 1 for VTP2

V Counter

V

T

P

2

0–511

V3 Toggle Position 2 for VTP2

V4 Toggle Position 1 for VTP2

V4 Toggle Position 2 for VTP2

VTPLEN3

9

1

9

Sys_Reg(9)

Sys_Reg(9 and 10)

Sys_Reg(10)

Sys_Reg(10 and 11)

Sys_Reg(11)

V Counter

0–512

Length between Repetitions

V1STARTPOL3

V2STARTPOL3

V3STARTPOL3

V4STARTPOL3

V1TOG1POS3

V1TOG2POS3

V2TOG1POS3

V2TOG2POS3

V3TOG1POS3

V3TOG2POS3

V4TOG1POS3

V4TOG2POS3

High/Low

0–511

V1 Starting Polarity for VTP3 (0 = LO, 1 = HI)

V1 Toggle Position 1 for VTP3

V1 Toggle Position 2 for VTP3

V2 Toggle Position 1 for VTP3

V2 Toggle Position 2 for VTP3

V3 Toggle Position 1 for VTP3

V Counter

V

T

P

3

0–511

V3 Toggle Position 2 for VTP3

V4 Toggle Position 1 for VTP3

V4 Toggle Position 2 for VTP3

–32–

REV. 0

AD9898

Table XVI. Mode_A and Mode_B Registers for VTPx Selection

Register

Name

Bit

Width

Type

Range

Description

VTPSEQPTR0*

VTPSEQPTR1*

VTPSEQPTR2*

VTPSEQPTR3*

VTPSEQPTR4*

3

Mode_Reg(2)

Vertical Transfer Pulse Pointer Used in CCD Region 0

(0 = VTPSEL0, 1 = VTPSEL1, 2 = VTPSEL2, 3 = VTPSEL3