AD9901KPZ-REEL [ADI]
Ultrahigh Speed Phase/Frequency Discriminator;
| 型号： | AD9901KPZ-REEL |
| 厂家： | 
ADI |
| 描述： | Ultrahigh Speed Phase/Frequency Discriminator |
| 文件： | 总8页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultrahigh Speed
a
Phase/Frequency Discriminator
AD9901
PHASE-LOCKED LOOP
FEATURES
Phase and Frequency Detection
ECL/TTL/CMOS Compatible
Linear Transfer Function
No “Dead Zone”
REFERENCE
INPUT
LOW-
OSCILLATOR
OUTPUT
PASS
VCO
FILTER
MIL-STD-883 Compliant Versions Available
AD9901
APPLICATIONS
1/N
Low Phase Noise Reference Loops
Fast-Tuning “Agile” IF Loops
Secure “Hopping” Communications
Coherent Radar Transmitter/Receiver Chains
OPTIONAL 1/N PRESCALER
TYPICAL OF DIGITAL PLLs
GENERAL DESCRIPTION
A major feature of the AD9901 is its ability to compare
phase/frequency inputs at standard IF frequencies without
prescalers. Excessive phase uncertainty which is common with
standard PLL configurations is also eliminated. The AD9901
provides the locking speed of traditional phase/frequency dis-
criminators, with the phase stability of analog mixers.
The AD9901 is a digital phase/frequency discriminator capable
of directly comparing phase/frequency inputs up to 200 MHz.
Processing in a high speed trench-oxide isolated process, com-
bined with an innovative design, gives the AD9901 a linear
detection range, free of indeterminate phase detection zones
common to other digital designs.
The AD9901 is available as a commercial temperature range
device, 0°C to +70°C, and as a military temperature device,
–55°C to +125°C. The commercial versions are packaged in a
14-lead ceramic DIP and a 20-lead PLCC.
With a single +5 V supply, the AD9901 can be configured to
operate with TTL or CMOS logic levels; it can also operate
with ECL inputs when operated with a –5.2 V supply. The
open-collector outputs allow the output swing to be matched to
post-filtering input requirements. A simple current setting resis-
tor controls the output stage current range, permitting a reduc-
tion in power when operated at lower frequencies.
The AD9901 Phase/Frequency Discriminator is available in
versions compliant with MIL-STD-883. Refer to the Analog
Devices Military Products Databook or current AD9901/883B
data sheet for specifications.
FUNCTIONAL BLOCK DIAGRAM
D
Q
D
Q
REFERENCE
FREQUENCY
DISCRIMINATOR
FLIP-FLOP
REFERENCE
INPUT
FLIP-FLOP
REFERENCE
INPUT
OUTPUT
OUTPUT
Q
Q
R
XOR
D
Q
OSCILLATOR
INPUT
S
D
Q
FLIP-FLOP
OSCILLATOR
FREQUENCY
DISCRIMINATOR
FLIP-FLOP
OSCILLATOR
INPUT
Q
Q
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD9901–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1
Operating Temperature Range
AD9901KQ/KP . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature2
Plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C
Positive Supply Voltage (+VS for TTL Operation) . . . . . +7 V
Negative Supply Voltage (–VS for ECL Operation) . . . . . –7 V
Input Voltage Range (TTL Operation) . . . . . . . 0 V to +5.5 V
Differential Input Voltage (ECL Operation) . . . . . . . . . .4.0 V
ISET Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mA
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
(؎V = +5.0 V [for TTL] or –5.2 V [for ECL], unless otherwise noted)
ELECTRICAL CHARACTERISTICS
S
Commercial Temperature
0؇C to +70؇C
AD9901KQ/KP
Test
Temp
Level
Min
Typ
Max
Units
INPUT CHARACTERISTICS
TTL Input Logic “1” Voltage
TTL Input Logic “0” Voltage
TTL Input Logic “1” Current3
TTL Input Logic “0” Current3
ECL Differential Switching Voltage
ECL Input Current
Full
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
VI
2.0
V
V
mA
mA
mV
µA
0.8
0.6
1.6
300
1.6
20
OUTPUT CHARACTERISTICS
Peak-to-Peak Output Voltage Swing4
TTL Output Compliance Range
ECL Output Compliance Range
IOUT Range
Full
Full
Full
Full
Full
VI
V
V
V
VI
1.8
3–7
±2
0.9–11
0.47
2.0
V
V
V
mA
V
Internal Reference Voltage
0.42
0.52
AC CHARACTERISTICS
Linear Phase Detection Range4
40 kHz
30 MHz
70 MHz
Functionality @ 70 MHz
+25°C
+25°C
+25°C
+25°C
V
V
V
I
360
320
270
Pass/Fail
Degrees
Degrees
Degrees
POWER SUPPLY CHARACTERISTICS
TTL Supply Current (+5.0 V)5, 6
+25°C
Full
+25°C
Full
I
I
I
I
43.5
43.5
42.5
42.5
218
54.0
54.0
52.5
52.5
mA
mA
mA
mA
mW
ECL Supply Current (–5.2 V)5, 6
Nominal Power Dissipation
+25°C
V
NOTES
1Absolute maximum ratings are limiting values, to be applied individually, and beyond which the service ability of the circuit may be impaired. Functional operability
is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2Maximum junction temperature should not exceed +175°C for ceramic packages, +150°C for plastic packages. Junction temperature can be calculated by:
tJ = PD (θJA) +tA = PD (θJC) +tC
where:
PD = power dissipation
θJA = thermal impedance from junction to air (°C/W)
θJC = thermal impedance from junction to case (°C/W)
tA = ambient temperature (°C)
tC = case temperature (°C)
typical thermal impedances:
AD9901 Ceramic DIP = θJA = 74°C/W; θJC = 21°C/W
AD9901 LCC = θJA = 80°C/W; θJC = 19°C/W
AD9901 PLCC = θJA = 88.2°C/W; θJC = 45.2°C/W
3VL = +0.4 V; VH = +2.4 V.
4RSET = 47.5 Ω; RL = 182 Ω.
5lncludes load current of 10 mA (load resistors = 182 Ω).
6Supply should remain stable within ± 5% for normal operation.
Specifications subject to change without notice.
–2–
REV. B
AD9901
INPUT/OUTPUT EQUIVALENT CIRCUITS
(Based on DIP Pinouts)
TTL MODE = +V (+5.0V)
S
ECL MODE = GROUND
+5.0V
4/13
3/14
VCO/REF, INPUT
5/12
VCO/REF, INPUT
VCO/REF, INPUT
R
SET
0.47V
REFERENCE
–5.2V
TTL MODE = GROUND
ECL MODE = V (–5.2V)
S
TTL Input
ECL Input
Output
AD9901 BURN-IN CIRCUIT
(Based on DIP ECL Pinouts)
DIE LAYOUT AND MECHANICAL INFORMATION
R
REFERENCE IN (–V
)
+V (GND)
OUTPUT
SET
S
S
GND (REFERENCE IN)
DA3
GND (REFERENCE IN)
–V (–5.2V)
S
V
MID
GND (–V
)
S
0.01F
50⍀
180⍀
1k⍀
GND (–V
)
)
S
V
(–V
S
S
+V (GND)
S
GND (VCO IN)
OUTPUT
GND (VCO IN)
VCO IN (–V )
S
AD9901
REG
Die Dimensions . . . . . . . . . . . . . . . . . 63 × 118 × 16 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic
180⍀
1k⍀
DA2
V
MID
ALL RESISTORS ؎5%
ALL CAPACITORS ؎20%
ALL SUPPLY VOLTAGES ؎5%
= –1.3V ؎5%
ECL HIGH
DA2
ECL LOW
V
MID
STATIC: DA2 = ECL HIGH; DA3 = ECL LOW
DYNAMIC: ECL HIGH
Bond Wire . . . . . . . . 1.25 mil Aluminum; Ultrasonic Bonding
ECL HIGH
DA3
ECL LOW
ORDERING GUIDE
Temperature
Ranges
Package
Descriptions
Package
Options
Model
AD9901KQ
0°C to +70°C
14-Lead Cerdip
Q-14
AD9901KP
0°C to +70°C
–55°C to +125°C
–55°C to +125°C
20-Lead Plastic Leaded Chip Carrier
14-Lead Cerdip
20-Terminal Ceramic Leadless Chip Carrier
P-20A
Q-14
E-20A
AD9901TQ/8831
AD9901TE/8831
NOTE
1For specifications, refer to Analog Devices Military Products Databook.
REV. B
–3–
AD9901
TTL/CMOS MODE FUNCTIONAL PIN DESCRIPTIONS
ECL MODE FUNCTIONAL PIN DESCRIPTIONS
GROUND
Ground connections for AD9901. Connect
all grounds together and to low impedance
ground plane as close to the device as
possible.
–VS
Negative supply connection, nominally
–5.2 V for ECL operation.
BIAS
Connect to –5.2 V for ECL operation.
VCO INPUT
Inverted side of ECL compatible differential
input, normally connected to the VCO output
signal.
+VS
Positive supply connection; nominally +5.0 V
for TTL operation.
BIAS
Connect to +VS (+5 V) for TTL operation.
VCO INPUT
Noninverted side of ECL-compatible
differential input, normally connected to the
VCO output signal.
VCO INPUT
TTL compatible input; normally connected
to the VCO output signal. VCO INPUT and
REFERENCE INPUT are equivalent to one
another.
OUTPUT
GROUND
The noninverted output. In ECL mode, the
output swing is approximately 0 V to –1.8 V.
OUTPUT
The noninverted output. In TTL/CMOS
mode, the output swing is approximately
+3.2 V to +5 V.
Ground connections for AD9901. Connect
all grounds together and to low-impedance
ground plane as close to the device as
possible.
RSET
External RSET connection. The current
through the RSET resistor is equal to the maxi-
mum full-scale output current. RSET should
be connected to ground through an external
RSET
External RSET connection. The current
through the RSET resistor is equal to the maxi-
mum full-scale output current. RSET should
be connected to –VS through an external
resistor in TTL mode. ISET = 0.47 V/RSET
ILOAD (max).
=
resistor in ECL mode. ISET = 0.47 V/RSET
ILOAD (max).
=
OUTPUT
The inverted output. In TTL/CMOS mode,
the output swing is approximately +3.2 V to
+5 V.
OUTPUT
The inverted output. In ECL mode, the out-
put swing is approximately 0 V to –1.8 V.
REFERENCE
INPUT
TTL compatible input, normally connected
to the reference input signal. The VCO
INPUT and the REFERENCE INPUT are
equivalent.
REFERENCE
INPUT
Noninverted side of ECL-compatible
differential input, normally connected to the
reference input signal. The VCO INPUT and
the REFERENCE INPUT are equivalent to
one another.
REFERENCE
INPUT
Inverted side of ECL-compatible differential
input, normally connected to the reference
input signal. The VCO INPUT and the
REFERENCE INPUT are equivalent.
+V
S
–V
S
R1
R2
R1
REFERENCE
OUTPUT +V
R2
REFERENCE
INPUT
REFERENCE
INPUT
R
S
OUTPUT
SET
–V
S
R
SET
OUTPUT
AD9901
AD9901
REG
REG
BIAS
+V
OUTPUT
R3
VCO
INPUT
+V
S
BIAS
OUTPUT
R3
VCO –V
INPUT
VCO
INPUT
S
S
–V
S
+V
S
Figure 1. TTL Mode (Based on DIP Pinouts)
Figure 2. ECL Mode (Based on DIP Pinouts)
–4–
REV. B
AD9901
EXPLANATION OF TEST LEVELS
– Parameter is a typical value only.
Test Level
I
– 100% production tested.
V
II – 100% production tested at +25°C, and sample tested
at specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characteriza-
tion testing.
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
PIN CONFIGURATIONS
ECL DIP Pinouts
TTL DIP Pinouts
1
2
3
4
5
6
7
14
–V
S
REFERENCE INPUT
1
2
3
4
5
6
7
14 GROUND
GROUND
BIAS
13
12
REFERENCE INPUT
BIAS
13
12
GROUND
–V
S
VCO INPUT
GROUND
GROUND
VCO INPUT
OUTPUT
REFERENCE INPUT
AD9901
TOP VIEW
(Not to Scale)
AD9901
TOP VIEW
(Not to Scale)
11 GROUND
VCO INPUT
11 +V
10
S
10
–V
S
OUTPUT
OUTPUT
9
8
OUTPUT
GROUND
R
SET
9
8
R
SET
–V
S
+V
GROUND
S
ECL LCC Pinouts
TTL LCC Pinouts
3
2
1
20 19
3
2
1
20 19
18
17
16
15
4
REFERENCE INPUT
NC
GROUND
NC
5
6
7
8
18
17
16
15
4
5
6
7
8
–V
S
VCO INPUT
AD9901
TOP VIEW
(Not to Scale)
+V
S
GROUND
NC
NC
NC
VCO INPUT
NC
AD9901
TOP VIEW
(Not to Scale)
NC
GROUND
NC
VCO INPUT
14
OUTPUT
–V
S
14
OUTPUT
9
10 11 12 13
NC = NO CONNECT
9
10 11 12 13
NC = NO CONNECT
ECL PLCC Pinouts
TTL PLCC Pinouts
3
2
1
20 19
PIN 1
IDENTIFIER
4
5
6
7
8
18
GROUND
GROUND
VCO INPUT
OUTPUT
NC
REFERENCE INPUT
17 NC
16 +V
3
2
1
20 19
AD9901
TOP VIEW
(Not to Scale)
S
PIN 1
IDENTIFIER
4
5
6
7
8
18
–V
S
VCO INPUT
15
14
NC
OUTPUT
VCO INPUT
17 NC
AD9901
TOP VIEW
(Not to Scale)
–V
16 GROUND
S
15
14
OUTPUT
NC
NC
9
10 11 12 13
NC = NO CONNECT
OUTPUT
9
10 11 12 13
NC = NO CONNECT
REV. B
–5–
AD9901
THEORY OF OPERATION
REFERENCE
INPUT
A phase detector is one of three basic components of a phase-
locked loop (PLL); the other two are a filter and a tunable oscil-
lator. A basic PLL control system is shown in Figure 3.
OSCILLATOR
INPUT
REFERENCE
FLIP-FLOP
OUTPUT
REFERENCE
INPUT
OSCILLATOR
FLIP-FLOP
OUTPUT
LOW-
OSCILLATOR
OUTPUT
PASS
VCO
DC MEAN VALUE
FILTER
XORGATE
OUTPUT
AD9901
1/N
OPTIONAL 1/N PRESCALER
TYPICAL OF DIGITAL PLLs
Figure 6. Timing Waveforms (φOUT Lags φ )
IN
oscillator leading the reference frequency; and with the oscillator
lagging. This output pulse train is low-pass filtered to extract the
dc mean value [Kφ (φI – φO)] where Kφ is a proportionality con-
stant (phase gain).
Figure 3. Phase-Locked Loop Control System
The function of the phase detector is to generate an error signal
that is used to retune the oscillator frequency whenever its out-
put deviates from a reference input signal. The two most com-
mon methods of implementing phase detectors are (1) an analog
mixer and (2) a family of sequential logic circuits known as
digital phase detectors.
At or near lock (Figures 4, 5 and 6), only the two input flip-
flops and the exclusive-OR gate (the phase detection circuit) are
active. The input flip-flops divide both the reference and oscilla-
tor frequencies by a factor of two. This insures that inputs to the
exclusive-OR are square waves, regardless of the input duty
cycles of the frequencies being compared. This division-by-two
also moves the nonlinear detection range to the ends of the
range rather than near lock, which is the case with conventional
digital phase detectors.
The AD9901 is a digital phase detector. As illustrated in the
block diagram of the unit, straightforward sequential logic de-
sign is used. The main components include four “D” flip-flops,
an exclusive-OR gate (XOR) and some combinational output
logic. The circuit operates in two distinct modes: as a linear
phase detector and as a frequency discriminator.
Figure 7 illustrates the constant gain near lock.
When the reference and oscillator are very close in frequency,
only the phase detection circuit is active. If the two inputs are
substantially different in frequency, the frequency discrimina-
tion circuit overrides the phase detector portion to drive the
oscillator frequency toward the reference frequency and put it
within range of the phase detector.
2
F
= 70MHz
O
F
= 200MHz
O
F
= 50MHz
O
Input signals to the AD9901 are pulse trains, and its output
duty cycle is proportional to the phase difference of the oscilla-
tor and reference inputs. Figures 4, 5 and 6 illustrate, respec-
tively, the input/output relationships at lock; with the
1
TYPICAL PHASE DETECTOR
GAIN IS 0.2865V/RAD
⌬V
= 1.8V
OUT
REFERENCE
INPUT
OSCILLATOR
INPUT
0
–2
0
–
PHASE DIFFERENCE AT INPUTS
REFERENCE
FLIP-FLOP
OUTPUT
Figure 7. Phase Gain Plot
OSCILLATOR
FLIP-FLOP
When the two square waves are combined by the XOR, the
output has a 50% duty cycle if the reference and oscillator in-
puts are exactly 180° out of phase; under these conditions, the
AD9901 is operating in a locked mode. Any shift in the phase
relationship between these input signals causes a change in the
output duty cycle. Near lock, the frequency discriminator flip-
flops provide constant HIGH levels to gate the XOR output to
the final output.
OUTPUT
DC MEAN VALUE
XORGATE
OUTPUT
Figure 4. AD9901 Timing Waveforms at “Lock”
REFERENCE
INPUT
OSCILLATOR
INPUT
The duty cycle of the AD9901 is a direct measure of the phase
difference between the two input signals when the unit is near
lock. The transfer function can be stated as [Kφ(φI – φO](V/RAD),
where Kφ is the allowable output voltage range of the AD9901
divided by 2 π.
REFERENCE
FLIP-FLOP
OUTPUT
OSCILLATOR
FLIP-FLOP
OUTPUT
DC MEAN VALUE
For a typical output swing of 1.8 V, the transfer function can be
stated as (1.8 V/2 π = 0.285 V/RAD). Figure 7 shows the rela-
tionship of the dc mean value of the AD9901 output as a func-
tion of the phase difference of the two inputs.
XORGATE
OUTPUT
Figure 5. Timing Waveforms (φOUT Leads φIN)
–6–
REV. B
AD9901
500mV
500mV
500mV
100
90
100
90
100
90
10
10
10
0%
0%
0%
5ns
200ns
200ns
Figure 8. AD9901 Output Waveform
(FO << FI)
Figure 9. AD9901 Output Waveform
(FO >> FI)
Figure 10. AD9901 Output Waveform
(FO = FI = 50 MHz)
165
It is important to note that the slope of the transfer function is
constant near its midpoint. Many digital phase comparators have
an area near the lock point where their gain goes to zero, result-
ing in a “dead zone.” This causes increased phase noise (jitter) at
the lock point.
155
145
135
125
115
105
95
The AD9901 avoids this dead zone by shifting it to the end-
points of the transfer curve, as indicated in Figure 7. The in-
creased gain at either end increases the effective error signal to
pull the oscillator back into the linear region. This does not
affect phase noise, which is far more dependent upon lock region
characteristics.
85
75
65
It should be noted, however, that as frequency increases, the
linear range is decreased. At the ends of the detection range, the
reference and oscillator inputs approach phase alignment. At this
point, slew rate limiting in the detector effectively increases
phase gain. This decreases the linear detection by nominally
3.6 ns. Therefore, the typical detection range can be found by
calculating [(1/F – 3.6 ns)/(1/F)] × 360°. As an example, at
200 MHz the linear phase detection range is ±50°.
0
–1
1
2
3
4
5
6
VARACTORS TUNING VOLTAGE – Volts
Figure 11. VCO Frequency vs. Voltage
Next, the range of frequencies over which the VCO is to operate
is examined to assure that it lies on a linear portion of the transfer
curve. In this case, frequencies from 100 MHz to 120 MHz
result from tuning voltages of approximately +1.5 V to +2.5 V.
Because the nominal output swing of the AD9901 is 0 V to –1.8 V,
an inverting amplifier with a gain of 2 follows the loop filter.
Away from lock, the AD9901 becomes a frequency discrimina-
tor. Any time either the reference or oscillator input occurs twice
before the other, the Frequency High or Frequency Low flip-flop
is clocked to logic LOW. This overrides the XOR output and
holds the output at the appropriate level to pull the oscillator
toward the reference frequency. Once the frequencies are within
the linear range, the phase detector circuit takes over again.
Combining the frequency discriminator with the phase detector
eliminates locking to a harmonic of the reference.
As shown in the illustration, a simple passive RC low-pass filter
made up of two resistors and a tantalum capacitor eliminates the
need for an expensive high speed op amp active-filter design. In
this passive-filter second-order-loop system, where n = 2, the
damping factor is equal to:
δ = 0.5 [KOKd /n(τ1 + τ2)]1/2 [τ2 + (n/KOKd)]
and the values for τ1 and τ2 are the low-pass filter’s time con-
stants R1C and R2C. The gain of 2 of the inverting stage, when
combined with the phase detector’s gain, gives:
Figure 8 shows the effect of the “Frequency Low” flip-flop when
the oscillator frequency is much lower than the reference input.
The narrow pulses, which result from cycles when two positive
reference-input transitions occur before a positive VCO edge,
increase the dc mean value. Figure 9 illustrates the inverse effect
when the “Frequency High” flip-flop reacts to a much higher
VCO frequency.
Kd = 0.572 V/RAD
With KO = 115.2 MRAD/s/V, τ1 equals 1.715s, and τ2 equals
3.11 × 10–4s for the required damping factor of 0.7. The illus-
trated values of 30 Ω (R1), 160 Ω (R2), and 10 µF (C) in the
diagram approximate these time constants.
Figure 10 shows the output waveform at lock for 50 MHz opera-
tion. This output results when the phase difference between
reference and oscillator is approximately – πRad.
The gain of the RC filter is:
VO/VI = (1 + sR2C)/[1 + s(R1 + R2)C].
Where KOKd >> ωn, the system’s natural frequency:
ωn = [KOKd/n(τ1 + τ2)]1/2 = 4.5 kHz.
AD9901 APPLICATIONS
The figure below illustrates a phase-locked loop (PLL) system
utilizing the AD9901. The first step in designing this type of
circuit is to characterize the VCO’s output frequency as a func-
tion of tuning voltage. The transfer function of the oscillator in
the diagram is shown in Figure 11.
For general information about phase-locked loop design, the
user is advised to consult the following references: Gardner,
Phase-Lock Techniques (Wiley); or Best, Phase Locked Loops
(McGraw-Hill).
REV. B
–7–
AD9901
REFERENCE
INPUT
AD96685
+V
55MHz
OFFSET
1k⍀
1k⍀
S
–5.2V
182⍀
2k⍀
–5.2V
–5.2V
+5.0V
REF
REF
AD9901OUT
OUTPUT
160k⍀
30⍀
OUT
OUTPUT
AD741
AD741
OSC
OSC
390⍀
10F
47.5⍀
R
SET
LOOP
AD9901
–5.2V
FILTER
DIP
PINOUTS
OSCILLATOR
OUTPUT
110MHz
MV1404
51k⍀
OSCILLATOR
MC1648
DIVIDE-
BY-TWO
100nH
ALTERNATE HIGH LEVEL
OUTPUT CIRCUIT
S
MV1404
50⍀
–2V
50⍀
50⍀
(؎V TYPICALLY +15V TO +60V)
–5.2V
–5.2V
–2V
Figure 12. Phased-Locked Loop Using AD9901
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Cerdip
(Q-14)
0.005 (0.13) MIN
14
0.098 (2.49) MAX
8
0.310 (7.87)
0.220 (5.59)
1
7
0.320 (8.13)
0.290 (7.37)
PIN 1
0.785 (19.94) MAX
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.023 (0.58)
0.070 (1.78)
0.030 (0.76)
0.100
(2.54)
BSC
15°
0°
0.014 (0.36)
20-Terminal Ceramic Leadless Chip Carrier
(E-20A)
20-Lead Plastic Leaded Chip Carrier
(P-20A)
0.200 (5.08)
0.180 (4.57)
BSC
0.075
(1.91)
REF
0.165 (4.19)
0.100 (2.54)
0.064 (1.63)
0.048 (1.21)
0.056 (1.42)
0.042 (1.07)
0.100 (2.54) BSC
0.025 (0.63)
0.042 (1.07)
0.015 (0.38)
MIN
0.015 (0.38)
0.095 (2.41)
0.075 (1.90)
0.048 (1.21)
0.042 (1.07)
3
19
18
3
19
18
20
4
0.021 (0.53)
0.013 (0.33)
4
8
0.028 (0.71)
0.022 (0.56)
PIN 1
0.358
1
0.050
(1.27)
BSC
0.358 (9.09)
IDENTIFIER
0.011 (0.28)
0.330 (8.38)
0.290 (7.37)
(9.09)
MAX
SQ
BOTTOM
VIEW
0.342 (8.69)
SQ
TOP VIEW
(PINS DOWN)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.032 (0.81)
0.026 (0.66)
0.050 (1.27)
BSC
14
13
8
14
13
9
9
0.020
(0.50)
R
0.040 (1.01)
0.025 (0.64)
45° TYP
0.356 (9.04)
0.350 (8.89)
0.395 (10.02)
0.385 (9.78)
SQ
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
0.150 (3.81)
BSC
0.110 (2.79)
0.085 (2.16)
SQ
–8–
REV. B
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